Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 643:c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
Summary: bitCount() should use POPC on SPARC processors where POPC is implemented directly in hardware.
Reviewed-by: kvn, never
| author | twisti |
|---|---|
| date | Fri, 13 Mar 2009 11:35:17 -0700 |
| parents | 337400e7a5dd |
| children | c517646eef23 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 624 | 2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Special Registers | |
| 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); | |
| 79 | |
| 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 81 // allocator, and only shows up in the encodings. | |
| 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 84 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 85 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 87 // the stack will not have this element so FPR1 == st(0) from the | |
| 88 // oopMap viewpoint. This same weirdness with numbering causes | |
| 89 // instruction encoding to have to play games with the register | |
| 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 91 // where it does flt->flt moves to see an example | |
| 92 // | |
| 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 107 | |
| 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. | |
| 109 // Word a in each register holds a Float, words ab hold a Double. | |
| 110 // We currently do not use the SIMD capabilities, so registers cd | |
| 111 // are unused at the moment. | |
| 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 128 | |
| 129 // Specify priority of register selection within phases of register | |
| 130 // allocation. Highest priority is first. A useful heuristic is to | |
| 131 // give registers a low priority when they are required by machine | |
| 132 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 134 // For the Intel integer registers, the equivalent Long pairs are |
| 135 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 139 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 140 | |
| 141 alloc_class chunk1( XMM0a, XMM0b, | |
| 142 XMM1a, XMM1b, | |
| 143 XMM2a, XMM2b, | |
| 144 XMM3a, XMM3b, | |
| 145 XMM4a, XMM4b, | |
| 146 XMM5a, XMM5b, | |
| 147 XMM6a, XMM6b, | |
| 148 XMM7a, XMM7b, EFLAGS); | |
| 149 | |
| 150 | |
| 151 //----------Architecture Description Register Classes-------------------------- | |
| 152 // Several register classes are automatically defined based upon information in | |
| 153 // this architecture description. | |
| 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 158 // | |
| 159 // Class for all registers | |
| 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 161 // Class for general registers | |
| 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); | |
| 163 // Class for general registers which may be used for implicit null checks on win95 | |
| 164 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
| 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); | |
| 166 // Class of "X" registers | |
| 167 reg_class x_reg(EBX, ECX, EDX, EAX); | |
| 168 // Class of registers that can appear in an address with no offset. | |
| 169 // EBP and ESP require an extra instruction byte for zero offset. | |
| 170 // Used in fast-unlock | |
| 171 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 172 // Class for general registers not including ECX | |
| 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 174 // Class for general registers not including EAX | |
| 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 176 // Class for general registers not including EAX or EBX. | |
| 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 178 // Class of EAX (for multiply and divide operations) | |
| 179 reg_class eax_reg(EAX); | |
| 180 // Class of EBX (for atomic add) | |
| 181 reg_class ebx_reg(EBX); | |
| 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 183 reg_class ecx_reg(ECX); | |
| 184 // Class of EDX (for multiply and divide operations) | |
| 185 reg_class edx_reg(EDX); | |
| 186 // Class of EDI (for synchronization) | |
| 187 reg_class edi_reg(EDI); | |
| 188 // Class of ESI (for synchronization) | |
| 189 reg_class esi_reg(ESI); | |
| 190 // Singleton class for interpreter's stack pointer | |
| 191 reg_class ebp_reg(EBP); | |
| 192 // Singleton class for stack pointer | |
| 193 reg_class sp_reg(ESP); | |
| 194 // Singleton class for instruction pointer | |
| 195 // reg_class ip_reg(EIP); | |
| 196 // Singleton class for condition codes | |
| 197 reg_class int_flags(EFLAGS); | |
| 198 // Class of integer register pairs | |
| 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 200 // Class of integer register pairs that aligns with calling convention | |
| 201 reg_class eadx_reg( EAX,EDX ); | |
| 202 reg_class ebcx_reg( ECX,EBX ); | |
| 203 // Not AX or DX, used in divides | |
| 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 205 | |
| 206 // Floating point registers. Notice FPR0 is not a choice. | |
| 207 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 208 // a 2-address instructions out of Intels FP stack. | |
| 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); | |
| 210 | |
| 211 // make a register class for SSE registers | |
| 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); | |
| 213 | |
| 214 // make a double register class for SSE2 registers | |
| 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, | |
| 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); | |
| 217 | |
| 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, | |
| 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, | |
| 220 FPR7L,FPR7H ); | |
| 221 | |
| 222 reg_class flt_reg0( FPR1L ); | |
| 223 reg_class dbl_reg0( FPR1L,FPR1H ); | |
| 224 reg_class dbl_reg1( FPR2L,FPR2H ); | |
| 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, | |
| 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); | |
| 227 | |
| 228 // XMM6 and XMM7 could be used as temporary registers for long, float and | |
| 229 // double values for SSE2. | |
| 230 reg_class xdb_reg6( XMM6a,XMM6b ); | |
| 231 reg_class xdb_reg7( XMM7a,XMM7b ); | |
| 232 %} | |
| 233 | |
| 234 | |
| 235 //----------SOURCE BLOCK------------------------------------------------------- | |
| 236 // This is a block of C++ code which provides values, functions, and | |
| 237 // definitions necessary in the rest of the architecture description | |
| 238 source %{ | |
| 304 | 239 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 240 #define RELOC_DISP32 Assembler::disp32_operand |
| 241 | |
| 242 #define __ _masm. | |
| 243 | |
| 244 // How to find the high register of a Long pair, given the low register | |
| 245 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 246 | |
| 247 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 248 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 249 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 250 | |
| 251 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 254 // of 128-bits operands for SSE instructions. | |
| 255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 256 // Store the value to a 128-bits operand. | |
| 257 operand[0] = lo; | |
| 258 operand[1] = hi; | |
| 259 return operand; | |
| 260 } | |
| 261 | |
| 262 // Buffer for 128-bits masks used by SSE instructions. | |
| 263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 264 | |
| 265 // Static initialization during VM startup. | |
| 266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 270 | |
| 271 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 272 // from the start of the call to the point where the return address | |
| 273 // will point. | |
| 274 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points | |
| 276 } | |
| 277 | |
| 278 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points | |
| 280 } | |
| 281 | |
| 282 static int sizeof_FFree_Float_Stack_All = -1; | |
| 283 | |
| 284 int MachCallRuntimeNode::ret_addr_offset() { | |
| 285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
| 286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); | |
| 287 } | |
| 288 | |
| 289 // Indicate if the safepoint node needs the polling page as an input. | |
| 290 // Since x86 does have absolute addressing, it doesn't. | |
| 291 bool SafePointNode::needs_polling_address_input() { | |
| 292 return false; | |
| 293 } | |
| 294 | |
| 295 // | |
| 296 // Compute padding required for nodes which need alignment | |
| 297 // | |
| 298 | |
| 299 // The address of the call instruction needs to be 4-byte aligned to | |
| 300 // ensure that it does not span a cache line so that it can be patched. | |
| 301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
| 302 if (Compile::current()->in_24_bit_fp_mode()) | |
| 303 current_offset += 6; // skip fldcw in pre_call_FPU, if any | |
| 304 current_offset += 1; // skip call opcode byte | |
| 305 return round_to(current_offset, alignment_required()) - current_offset; | |
| 306 } | |
| 307 | |
| 308 // The address of the call instruction needs to be 4-byte aligned to | |
| 309 // ensure that it does not span a cache line so that it can be patched. | |
| 310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
| 311 if (Compile::current()->in_24_bit_fp_mode()) | |
| 312 current_offset += 6; // skip fldcw in pre_call_FPU, if any | |
| 313 current_offset += 5; // skip MOV instruction | |
| 314 current_offset += 1; // skip call opcode byte | |
| 315 return round_to(current_offset, alignment_required()) - current_offset; | |
| 316 } | |
| 317 | |
| 318 #ifndef PRODUCT | |
| 319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 320 st->print("INT3"); | |
| 321 } | |
| 322 #endif | |
| 323 | |
| 324 // EMIT_RM() | |
| 325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 327 *(cbuf.code_end()) = c; | |
| 328 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 329 } | |
| 330 | |
| 331 // EMIT_CC() | |
| 332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 333 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 334 *(cbuf.code_end()) = c; | |
| 335 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 336 } | |
| 337 | |
| 338 // EMIT_OPCODE() | |
| 339 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 340 *(cbuf.code_end()) = (unsigned char)code; | |
| 341 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 342 } | |
| 343 | |
| 344 // EMIT_OPCODE() w/ relocation information | |
| 345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 346 cbuf.relocate(cbuf.inst_mark() + offset, reloc); | |
| 347 emit_opcode(cbuf, code); | |
| 348 } | |
| 349 | |
| 350 // EMIT_D8() | |
| 351 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 352 *(cbuf.code_end()) = (unsigned char)d8; | |
| 353 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 354 } | |
| 355 | |
| 356 // EMIT_D16() | |
| 357 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 358 *((short *)(cbuf.code_end())) = d16; | |
| 359 cbuf.set_code_end(cbuf.code_end() + 2); | |
| 360 } | |
| 361 | |
| 362 // EMIT_D32() | |
| 363 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 364 *((int *)(cbuf.code_end())) = d32; | |
| 365 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 366 } | |
| 367 | |
| 368 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 370 int format) { | |
| 371 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 372 | |
| 373 *((int *)(cbuf.code_end())) = d32; | |
| 374 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 375 } | |
| 376 | |
| 377 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 379 int format) { | |
| 380 #ifdef ASSERT | |
| 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
| 382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code"); | |
| 383 } | |
| 384 #endif | |
| 385 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 386 | |
| 387 *((int *)(cbuf.code_end())) = d32; | |
| 388 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 389 } | |
| 390 | |
| 391 // Access stack slot for load or store | |
| 392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 394 if( -128 <= disp && disp <= 127 ) { | |
| 395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 397 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 398 } else { | |
| 399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 401 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 402 } | |
| 403 } | |
| 404 | |
| 405 // eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { | |
| 407 // There is no index & no scale, use form without SIB byte | |
| 408 if ((index == 0x4) && | |
| 409 (scale == 0) && (base != ESP_enc)) { | |
| 410 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 411 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 412 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 413 } | |
| 414 else { // If 8-bit displacement, mode 0x1 | |
| 415 if ((displace >= -128) && (displace <= 127) | |
| 416 && !(displace_is_oop) ) { | |
| 417 emit_rm(cbuf, 0x1, reg_encoding, base); | |
| 418 emit_d8(cbuf, displace); | |
| 419 } | |
| 420 else { // If 32-bit displacement | |
| 421 if (base == -1) { // Special flag for absolute address | |
| 422 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 423 // (manual lies; no SIB needed here) | |
| 424 if ( displace_is_oop ) { | |
| 425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 426 } else { | |
| 427 emit_d32 (cbuf, displace); | |
| 428 } | |
| 429 } | |
| 430 else { // Normal base + offset | |
| 431 emit_rm(cbuf, 0x2, reg_encoding, base); | |
| 432 if ( displace_is_oop ) { | |
| 433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 434 } else { | |
| 435 emit_d32 (cbuf, displace); | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 } | |
| 440 } | |
| 441 else { // Else, encode with the SIB byte | |
| 442 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 443 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 444 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 445 emit_rm(cbuf, scale, index, base); | |
| 446 } | |
| 447 else { // If 8-bit displacement, mode 0x1 | |
| 448 if ((displace >= -128) && (displace <= 127) | |
| 449 && !(displace_is_oop) ) { | |
| 450 emit_rm(cbuf, 0x1, reg_encoding, 0x4); | |
| 451 emit_rm(cbuf, scale, index, base); | |
| 452 emit_d8(cbuf, displace); | |
| 453 } | |
| 454 else { // If 32-bit displacement | |
| 455 if (base == 0x04 ) { | |
| 456 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 457 emit_rm(cbuf, scale, index, 0x04); | |
| 458 } else { | |
| 459 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 460 emit_rm(cbuf, scale, index, base); | |
| 461 } | |
| 462 if ( displace_is_oop ) { | |
| 463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 464 } else { | |
| 465 emit_d32 (cbuf, displace); | |
| 466 } | |
| 467 } | |
| 468 } | |
| 469 } | |
| 470 } | |
| 471 | |
| 472 | |
| 473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 474 if( dst_encoding == src_encoding ) { | |
| 475 // reg-reg copy, use an empty encoding | |
| 476 } else { | |
| 477 emit_opcode( cbuf, 0x8B ); | |
| 478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 479 } | |
| 480 } | |
| 481 | |
| 482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 483 if( dst_encoding == src_encoding ) { | |
| 484 // reg-reg copy, use an empty encoding | |
| 485 } else { | |
| 486 MacroAssembler _masm(&cbuf); | |
| 487 | |
| 488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 489 } | |
| 490 } | |
| 491 | |
| 492 | |
| 493 //============================================================================= | |
| 494 #ifndef PRODUCT | |
| 495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 496 Compile* C = ra_->C; | |
| 497 if( C->in_24_bit_fp_mode() ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
498 st->print("FLDCW 24 bit fpu control word"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
499 st->print_cr(""); st->print("\t"); |
| 0 | 500 } |
| 501 | |
| 502 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 504 // Remove two words for return addr and rbp, | |
| 505 framesize -= 2*wordSize; | |
| 506 | |
| 507 // Calls to C2R adapters often do not accept exceptional returns. | |
| 508 // We require that their callers must bang for them. But be careful, because | |
| 509 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 510 // stack. But the stack safety zone should account for that. | |
| 511 // See bugs 4446381, 4468289, 4497237. | |
| 512 if (C->need_stack_bang(framesize)) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
513 st->print_cr("# stack bang"); st->print("\t"); |
| 0 | 514 } |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
515 st->print_cr("PUSHL EBP"); st->print("\t"); |
| 0 | 516 |
| 517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
519 st->print_cr(""); st->print("\t"); |
| 0 | 520 framesize -= wordSize; |
| 521 } | |
| 522 | |
| 523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 524 if (framesize) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
525 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 526 } |
| 527 } else { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
528 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 529 } |
| 530 } | |
| 531 #endif | |
| 532 | |
| 533 | |
| 534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 535 Compile* C = ra_->C; | |
| 536 | |
| 537 if (UseSSE >= 2 && VerifyFPU) { | |
| 538 MacroAssembler masm(&cbuf); | |
| 539 masm.verify_FPU(0, "FPU stack must be clean on entry"); | |
| 540 } | |
| 541 | |
| 542 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 543 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 545 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 546 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 547 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 548 // If method sets FPU control word do it now | |
| 549 if( C->in_24_bit_fp_mode() ) { | |
| 550 MacroAssembler masm(&cbuf); | |
| 551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 552 } | |
| 553 | |
| 554 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 556 // Remove two words for return addr and rbp, | |
| 557 framesize -= 2*wordSize; | |
| 558 | |
| 559 // Calls to C2R adapters often do not accept exceptional returns. | |
| 560 // We require that their callers must bang for them. But be careful, because | |
| 561 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 562 // stack. But the stack safety zone should account for that. | |
| 563 // See bugs 4446381, 4468289, 4497237. | |
| 564 if (C->need_stack_bang(framesize)) { | |
| 565 MacroAssembler masm(&cbuf); | |
| 566 masm.generate_stack_overflow_check(framesize); | |
| 567 } | |
| 568 | |
| 569 // We always push rbp, so that on return to interpreter rbp, will be | |
| 570 // restored correctly and we can correct the stack. | |
| 571 emit_opcode(cbuf, 0x50 | EBP_enc); | |
| 572 | |
| 573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
| 574 emit_opcode(cbuf, 0x68); // push 0xbadb100d | |
| 575 emit_d32(cbuf, 0xbadb100d); | |
| 576 framesize -= wordSize; | |
| 577 } | |
| 578 | |
| 579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 580 if (framesize) { | |
| 581 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 582 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 583 emit_d8(cbuf, framesize); | |
| 584 } | |
| 585 } else { | |
| 586 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 587 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 588 emit_d32(cbuf, framesize); | |
| 589 } | |
| 590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); | |
| 591 | |
| 592 #ifdef ASSERT | |
| 593 if (VerifyStackAtCalls) { | |
| 594 Label L; | |
| 595 MacroAssembler masm(&cbuf); | |
| 304 | 596 masm.push(rax); |
| 597 masm.mov(rax, rsp); | |
| 598 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 600 masm.pop(rax); | |
| 0 | 601 masm.jcc(Assembler::equal, L); |
| 602 masm.stop("Stack is not properly aligned!"); | |
| 603 masm.bind(L); | |
| 604 } | |
| 605 #endif | |
| 606 | |
| 607 } | |
| 608 | |
| 609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 610 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 611 } | |
| 612 | |
| 613 int MachPrologNode::reloc() const { | |
| 614 return 0; // a large enough number | |
| 615 } | |
| 616 | |
| 617 //============================================================================= | |
| 618 #ifndef PRODUCT | |
| 619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 620 Compile *C = ra_->C; | |
| 621 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 623 // Remove two words for return addr and rbp, | |
| 624 framesize -= 2*wordSize; | |
| 625 | |
| 626 if( C->in_24_bit_fp_mode() ) { | |
| 627 st->print("FLDCW standard control word"); | |
| 628 st->cr(); st->print("\t"); | |
| 629 } | |
| 630 if( framesize ) { | |
| 631 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 632 st->cr(); st->print("\t"); | |
| 633 } | |
| 634 st->print_cr("POPL EBP"); st->print("\t"); | |
| 635 if( do_polling() && C->is_method_compilation() ) { | |
| 636 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 637 st->cr(); st->print("\t"); | |
| 638 } | |
| 639 } | |
| 640 #endif | |
| 641 | |
| 642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 643 Compile *C = ra_->C; | |
| 644 | |
| 645 // If method set FPU control word, restore to standard control word | |
| 646 if( C->in_24_bit_fp_mode() ) { | |
| 647 MacroAssembler masm(&cbuf); | |
| 648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 649 } | |
| 650 | |
| 651 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 653 // Remove two words for return addr and rbp, | |
| 654 framesize -= 2*wordSize; | |
| 655 | |
| 656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 657 | |
| 658 if( framesize >= 128 ) { | |
| 659 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 660 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 661 emit_d32(cbuf, framesize); | |
| 662 } | |
| 663 else if( framesize ) { | |
| 664 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 665 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 666 emit_d8(cbuf, framesize); | |
| 667 } | |
| 668 | |
| 669 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 670 | |
| 671 if( do_polling() && C->is_method_compilation() ) { | |
| 672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0); | |
| 673 emit_opcode(cbuf,0x85); | |
| 674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 675 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 676 } | |
| 677 } | |
| 678 | |
| 679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 680 Compile *C = ra_->C; | |
| 681 // If method set FPU control word, restore to standard control word | |
| 682 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 683 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 684 | |
| 685 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 687 // Remove two words for return addr and rbp, | |
| 688 framesize -= 2*wordSize; | |
| 689 | |
| 690 size++; // popl rbp, | |
| 691 | |
| 692 if( framesize >= 128 ) { | |
| 693 size += 6; | |
| 694 } else { | |
| 695 size += framesize ? 3 : 0; | |
| 696 } | |
| 697 return size; | |
| 698 } | |
| 699 | |
| 700 int MachEpilogNode::reloc() const { | |
| 701 return 0; // a large enough number | |
| 702 } | |
| 703 | |
| 704 const Pipeline * MachEpilogNode::pipeline() const { | |
| 705 return MachNode::pipeline_class(); | |
| 706 } | |
| 707 | |
| 708 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 709 | |
| 710 //============================================================================= | |
| 711 | |
| 712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 713 static enum RC rc_class( OptoReg::Name reg ) { | |
| 714 | |
| 715 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 716 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 717 | |
| 718 VMReg r = OptoReg::as_VMReg(reg); | |
| 719 if (r->is_Register()) return rc_int; | |
| 720 if (r->is_FloatRegister()) { | |
| 721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 722 return rc_float; | |
| 723 } | |
| 724 assert(r->is_XMMRegister(), "must be"); | |
| 725 return rc_xmm; | |
| 726 } | |
| 727 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
729 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 730 if( cbuf ) { |
| 731 emit_opcode (*cbuf, opcode ); | |
| 732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); | |
| 733 #ifndef PRODUCT | |
| 734 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
735 if( size != 0 ) st->print("\n\t"); |
| 0 | 736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 739 } else { // FLD, FST, PUSH, POP |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
740 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 741 } |
| 742 #endif | |
| 743 } | |
| 744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 745 return size+3+offset_size; | |
| 746 } | |
| 747 | |
| 748 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 0 | 751 if( cbuf ) { |
| 752 if( reg_lo+1 == reg_hi ) { // double move? | |
| 753 if( is_load && !UseXmmLoadAndClearUpper ) | |
| 754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load | |
| 755 else | |
| 756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise | |
| 757 } else { | |
| 758 emit_opcode(*cbuf, 0xF3 ); | |
| 759 } | |
| 760 emit_opcode(*cbuf, 0x0F ); | |
| 761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) | |
| 762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load | |
| 763 else | |
| 764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); | |
| 765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); | |
| 766 #ifndef PRODUCT | |
| 767 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
768 if( size != 0 ) st->print("\n\t"); |
| 0 | 769 if( reg_lo+1 == reg_hi ) { // double move? |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
770 if( is_load ) st->print("%s %s,[ESP + #%d]", |
| 0 | 771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", |
| 772 Matcher::regName[reg_lo], offset); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
773 else st->print("MOVSD [ESP + #%d],%s", |
| 0 | 774 offset, Matcher::regName[reg_lo]); |
| 775 } else { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]", |
| 0 | 777 Matcher::regName[reg_lo], offset); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
778 else st->print("MOVSS [ESP + #%d],%s", |
| 0 | 779 offset, Matcher::regName[reg_lo]); |
| 780 } | |
| 781 #endif | |
| 782 } | |
| 783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 784 return size+5+offset_size; | |
| 785 } | |
| 786 | |
| 787 | |
| 788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
789 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 0 | 790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers |
| 791 if( cbuf ) { | |
| 792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { | |
| 793 emit_opcode(*cbuf, 0x66 ); | |
| 794 } | |
| 795 emit_opcode(*cbuf, 0x0F ); | |
| 796 emit_opcode(*cbuf, 0x28 ); | |
| 797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 798 #ifndef PRODUCT | |
| 799 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
800 if( size != 0 ) st->print("\n\t"); |
| 0 | 801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 803 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 805 } |
| 806 #endif | |
| 807 } | |
| 808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); | |
| 809 } else { | |
| 810 if( cbuf ) { | |
| 811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); | |
| 812 emit_opcode(*cbuf, 0x0F ); | |
| 813 emit_opcode(*cbuf, 0x10 ); | |
| 814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 815 #ifndef PRODUCT | |
| 816 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
817 if( size != 0 ) st->print("\n\t"); |
| 0 | 818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 820 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 822 } |
| 823 #endif | |
| 824 } | |
| 825 return size+4; | |
| 826 } | |
| 827 } | |
| 828 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 830 if( cbuf ) { |
| 831 emit_opcode(*cbuf, 0x8B ); | |
| 832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 833 #ifndef PRODUCT | |
| 834 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
835 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 837 #endif |
| 838 } | |
| 839 return size+2; | |
| 840 } | |
| 841 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
843 int offset, int size, outputStream* st ) { |
| 0 | 844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 845 if( cbuf ) { | |
| 846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 848 #ifndef PRODUCT | |
| 849 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
850 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
851 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 852 #endif |
| 853 } | |
| 854 size += 2; | |
| 855 } | |
| 856 | |
| 857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 858 const char *op_str; | |
| 859 int op; | |
| 860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 862 op = 0xDD; | |
| 863 } else { // 32-bit store | |
| 864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 865 op = 0xD9; | |
| 866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 867 } | |
| 868 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 870 } |
| 871 | |
| 872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { | |
| 873 // Get registers to move | |
| 874 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 875 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 876 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 877 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 878 | |
| 879 enum RC src_second_rc = rc_class(src_second); | |
| 880 enum RC src_first_rc = rc_class(src_first); | |
| 881 enum RC dst_second_rc = rc_class(dst_second); | |
| 882 enum RC dst_first_rc = rc_class(dst_first); | |
| 883 | |
| 884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 885 | |
| 886 // Generate spill code! | |
| 887 int size = 0; | |
| 888 | |
| 889 if( src_first == dst_first && src_second == dst_second ) | |
| 890 return size; // Self copy, no move | |
| 891 | |
| 892 // -------------------------------------- | |
| 893 // Check for mem-mem move. push/pop to move. | |
| 894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 895 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 900 } | |
| 901 // move low bits | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 907 } |
| 908 return size; | |
| 909 } | |
| 910 | |
| 911 // -------------------------------------- | |
| 912 // Check for integer reg-reg copy | |
| 913 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 915 |
| 916 // Check for integer store | |
| 917 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 919 |
| 920 // Check for integer load | |
| 921 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 923 |
| 924 // -------------------------------------- | |
| 925 // Check for float reg-reg copy | |
| 926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 929 if( cbuf ) { | |
| 930 | |
| 931 // Note the mucking with the register encode to compensate for the 0/1 | |
| 932 // indexing issue mentioned in a comment in the reg_def sections | |
| 933 // for FPR registers many lines above here. | |
| 934 | |
| 935 if( src_first != FPR1L_num ) { | |
| 936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 940 } else { | |
| 941 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 943 } | |
| 944 #ifndef PRODUCT | |
| 945 } else if( !do_size ) { | |
| 946 if( size != 0 ) st->print("\n\t"); | |
| 947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 948 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 949 #endif | |
| 950 } | |
| 951 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 952 } | |
| 953 | |
| 954 // Check for float store | |
| 955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 957 } |
| 958 | |
| 959 // Check for float load | |
| 960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 961 int offset = ra_->reg2offset(src_first); | |
| 962 const char *op_str; | |
| 963 int op; | |
| 964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 965 op_str = "FLD_D"; | |
| 966 op = 0xDD; | |
| 967 } else { // 32-bit load | |
| 968 op_str = "FLD_S"; | |
| 969 op = 0xD9; | |
| 970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 971 } | |
| 972 if( cbuf ) { | |
| 973 emit_opcode (*cbuf, op ); | |
| 974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); | |
| 975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 977 #ifndef PRODUCT | |
| 978 } else if( !do_size ) { | |
| 979 if( size != 0 ) st->print("\n\t"); | |
| 980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 981 #endif | |
| 982 } | |
| 983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 984 return size + 3+offset_size+2; | |
| 985 } | |
| 986 | |
| 987 // Check for xmm reg-reg copy | |
| 988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 990 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 991 "no non-adjacent float-moves" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 993 } |
| 994 | |
| 995 // Check for xmm store | |
| 996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 998 } |
| 999 | |
| 1000 // Check for float xmm load | |
| 1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1003 } |
| 1004 | |
| 1005 // Copy from float reg to xmm reg | |
| 1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1007 // copy to the top of stack from floating point reg | |
| 1008 // and use LEA to preserve flags | |
| 1009 if( cbuf ) { | |
| 1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1013 emit_d8(*cbuf,0xF8); | |
| 1014 #ifndef PRODUCT | |
| 1015 } else if( !do_size ) { | |
| 1016 if( size != 0 ) st->print("\n\t"); | |
| 1017 st->print("LEA ESP,[ESP-8]"); | |
| 1018 #endif | |
| 1019 } | |
| 1020 size += 4; | |
| 1021 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1023 |
| 1024 // Copy from the temp memory to the xmm reg. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1026 |
| 1027 if( cbuf ) { | |
| 1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1031 emit_d8(*cbuf,0x08); | |
| 1032 #ifndef PRODUCT | |
| 1033 } else if( !do_size ) { | |
| 1034 if( size != 0 ) st->print("\n\t"); | |
| 1035 st->print("LEA ESP,[ESP+8]"); | |
| 1036 #endif | |
| 1037 } | |
| 1038 size += 4; | |
| 1039 return size; | |
| 1040 } | |
| 1041 | |
| 1042 assert( size > 0, "missed a case" ); | |
| 1043 | |
| 1044 // -------------------------------------------------------------------- | |
| 1045 // Check for second bits still needing moving. | |
| 1046 if( src_second == dst_second ) | |
| 1047 return size; // Self copy; no move | |
| 1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1049 | |
| 1050 // Check for second word int-int move | |
| 1051 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1053 |
| 1054 // Check for second word integer store | |
| 1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1057 |
| 1058 // Check for second word integer load | |
| 1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1061 |
| 1062 | |
| 1063 Unimplemented(); | |
| 1064 } | |
| 1065 | |
| 1066 #ifndef PRODUCT | |
| 1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1068 implementation( NULL, ra_, false, st ); | |
| 1069 } | |
| 1070 #endif | |
| 1071 | |
| 1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1073 implementation( &cbuf, ra_, false, NULL ); | |
| 1074 } | |
| 1075 | |
| 1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1077 return implementation( NULL, ra_, true, NULL ); | |
| 1078 } | |
| 1079 | |
| 1080 //============================================================================= | |
| 1081 #ifndef PRODUCT | |
| 1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 1083 st->print("NOP \t# %d bytes pad for loops and calls", _count); | |
| 1084 } | |
| 1085 #endif | |
| 1086 | |
| 1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1088 MacroAssembler _masm(&cbuf); | |
| 1089 __ nop(_count); | |
| 1090 } | |
| 1091 | |
| 1092 uint MachNopNode::size(PhaseRegAlloc *) const { | |
| 1093 return _count; | |
| 1094 } | |
| 1095 | |
| 1096 | |
| 1097 //============================================================================= | |
| 1098 #ifndef PRODUCT | |
| 1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1101 int reg = ra_->get_reg_first(this); | |
| 1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1103 } | |
| 1104 #endif | |
| 1105 | |
| 1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1108 int reg = ra_->get_encode(this); | |
| 1109 if( offset >= 128 ) { | |
| 1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1111 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1113 emit_d32(cbuf, offset); | |
| 1114 } | |
| 1115 else { | |
| 1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1117 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1119 emit_d8(cbuf, offset); | |
| 1120 } | |
| 1121 } | |
| 1122 | |
| 1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1125 if( offset >= 128 ) { | |
| 1126 return 7; | |
| 1127 } | |
| 1128 else { | |
| 1129 return 4; | |
| 1130 } | |
| 1131 } | |
| 1132 | |
| 1133 //============================================================================= | |
| 1134 | |
| 1135 // emit call stub, compiled java to interpreter | |
| 1136 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1137 // Stub is fixed up when the corresponding call is converted from calling | |
| 1138 // compiled code to calling interpreted code. | |
| 1139 // mov rbx,0 | |
| 1140 // jmp -1 | |
| 1141 | |
| 1142 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1143 | |
| 1144 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1145 // That's why we must use the macroassembler to generate a stub. | |
| 1146 MacroAssembler _masm(&cbuf); | |
| 1147 | |
| 1148 address base = | |
| 1149 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1150 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1151 // static stub relocation stores the instruction address of the call | |
| 1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
| 1153 // static stub relocation also tags the methodOop in the code-stream. | |
| 1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time | |
| 304 | 1155 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1156 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1157 |
| 1158 __ end_a_stub(); | |
| 1159 // Update current stubs pointer and restore code_end. | |
| 1160 } | |
| 1161 // size of call stub, compiled java to interpretor | |
| 1162 uint size_java_to_interp() { | |
| 1163 return 10; // movl; jmp | |
| 1164 } | |
| 1165 // relocation entries for call stub, compiled java to interpretor | |
| 1166 uint reloc_java_to_interp() { | |
| 1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1168 } | |
| 1169 | |
| 1170 //============================================================================= | |
| 1171 #ifndef PRODUCT | |
| 1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1175 st->print_cr("\tNOP"); | |
| 1176 st->print_cr("\tNOP"); | |
| 1177 if( !OptoBreakpoint ) | |
| 1178 st->print_cr("\tNOP"); | |
| 1179 } | |
| 1180 #endif | |
| 1181 | |
| 1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1183 MacroAssembler masm(&cbuf); | |
| 1184 #ifdef ASSERT | |
| 1185 uint code_size = cbuf.code_size(); | |
| 1186 #endif | |
| 304 | 1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1188 masm.jump_cc(Assembler::notEqual, |
| 1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1190 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1191 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1192 int nops_cnt = 2; | |
| 1193 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1194 nops_cnt += 1; | |
| 1195 masm.nop(nops_cnt); | |
| 1196 | |
| 1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node"); | |
| 1198 } | |
| 1199 | |
| 1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1201 return OptoBreakpoint ? 11 : 12; | |
| 1202 } | |
| 1203 | |
| 1204 | |
| 1205 //============================================================================= | |
| 1206 uint size_exception_handler() { | |
| 1207 // NativeCall instruction size is the same as NativeJump. | |
| 1208 // exception handler starts out as jump and can be patched to | |
| 1209 // a call be deoptimization. (4932387) | |
| 1210 // Note that this value is also credited (in output.cpp) to | |
| 1211 // the size of the code section. | |
| 1212 return NativeJump::instruction_size; | |
| 1213 } | |
| 1214 | |
| 1215 // Emit exception handler code. Stuff framesize into a register | |
| 1216 // and call a VM stub routine. | |
| 1217 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1218 | |
| 1219 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1220 // That's why we must use the macroassembler to generate a handler. | |
| 1221 MacroAssembler _masm(&cbuf); | |
| 1222 address base = | |
| 1223 __ start_a_stub(size_exception_handler()); | |
| 1224 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1225 int offset = __ offset(); | |
| 1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); | |
| 1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1228 __ end_a_stub(); | |
| 1229 return offset; | |
| 1230 } | |
| 1231 | |
| 1232 uint size_deopt_handler() { | |
| 1233 // NativeCall instruction size is the same as NativeJump. | |
| 1234 // exception handler starts out as jump and can be patched to | |
| 1235 // a call be deoptimization. (4932387) | |
| 1236 // Note that this value is also credited (in output.cpp) to | |
| 1237 // the size of the code section. | |
| 1238 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1239 } | |
| 1240 | |
| 1241 // Emit deopt handler code. | |
| 1242 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1243 | |
| 1244 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1245 // That's why we must use the macroassembler to generate a handler. | |
| 1246 MacroAssembler _masm(&cbuf); | |
| 1247 address base = | |
| 1248 __ start_a_stub(size_exception_handler()); | |
| 1249 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1250 int offset = __ offset(); | |
| 1251 InternalAddress here(__ pc()); | |
| 1252 __ pushptr(here.addr()); | |
| 1253 | |
| 1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1256 __ end_a_stub(); | |
| 1257 return offset; | |
| 1258 } | |
| 1259 | |
| 1260 | |
| 1261 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
| 1262 int mark = cbuf.insts()->mark_off(); | |
| 1263 MacroAssembler _masm(&cbuf); | |
| 1264 address double_address = __ double_constant(x); | |
| 1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1266 emit_d32_reloc(cbuf, | |
| 1267 (int)double_address, | |
| 1268 internal_word_Relocation::spec(double_address), | |
| 1269 RELOC_DISP32); | |
| 1270 } | |
| 1271 | |
| 1272 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
| 1273 int mark = cbuf.insts()->mark_off(); | |
| 1274 MacroAssembler _masm(&cbuf); | |
| 1275 address float_address = __ float_constant(x); | |
| 1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1277 emit_d32_reloc(cbuf, | |
| 1278 (int)float_address, | |
| 1279 internal_word_Relocation::spec(float_address), | |
| 1280 RELOC_DISP32); | |
| 1281 } | |
| 1282 | |
| 1283 | |
| 1284 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1285 return regnum - 32; // The FP registers are in the second chunk | |
| 1286 } | |
| 1287 | |
| 1288 bool is_positive_zero_float(jfloat f) { | |
| 1289 return jint_cast(f) == jint_cast(0.0F); | |
| 1290 } | |
| 1291 | |
| 1292 bool is_positive_one_float(jfloat f) { | |
| 1293 return jint_cast(f) == jint_cast(1.0F); | |
| 1294 } | |
| 1295 | |
| 1296 bool is_positive_zero_double(jdouble d) { | |
| 1297 return jlong_cast(d) == jlong_cast(0.0); | |
| 1298 } | |
| 1299 | |
| 1300 bool is_positive_one_double(jdouble d) { | |
| 1301 return jlong_cast(d) == jlong_cast(1.0); | |
| 1302 } | |
| 1303 | |
| 1304 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1305 const bool Matcher::convL2FSupported(void) { | |
| 1306 return true; | |
| 1307 } | |
| 1308 | |
| 1309 // Vector width in bytes | |
| 1310 const uint Matcher::vector_width_in_bytes(void) { | |
| 1311 return UseSSE >= 2 ? 8 : 0; | |
| 1312 } | |
| 1313 | |
| 1314 // Vector ideal reg | |
| 1315 const uint Matcher::vector_ideal_reg(void) { | |
| 1316 return Op_RegD; | |
| 1317 } | |
| 1318 | |
| 1319 // Is this branch offset short enough that a short branch can be used? | |
| 1320 // | |
| 1321 // NOTE: If the platform does not provide any short branch variants, then | |
| 1322 // this method should return false for offset 0. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1323 bool Matcher::is_short_branch_offset(int rule, int offset) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1324 // the short version of jmpConUCF2 contains multiple branches, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1325 // making the reach slightly less |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1326 if (rule == jmpConUCF2_rule) |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1327 return (-126 <= offset && offset <= 125); |
| 0 | 1328 return (-128 <= offset && offset <= 127); |
| 1329 } | |
| 1330 | |
| 1331 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1332 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1333 return false; | |
| 1334 } | |
| 1335 | |
| 1336 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1337 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1338 | |
| 1339 // Threshold size for cleararray. | |
| 1340 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1341 | |
| 1342 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1343 // be subsumed into complex addressing expressions or compute them into | |
| 1344 // registers? True for Intel but false for most RISCs | |
| 1345 const bool Matcher::clone_shift_expressions = true; | |
| 1346 | |
| 1347 // Is it better to copy float constants, or load them directly from memory? | |
| 1348 // Intel can load a float constant from a direct address, requiring no | |
| 1349 // extra registers. Most RISCs will have to materialize an address into a | |
| 1350 // register first, so they would do better to copy the constant from stack. | |
| 1351 const bool Matcher::rematerialize_float_constants = true; | |
| 1352 | |
| 1353 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1354 // needed. Else we split the double into 2 integer pieces and move it | |
| 1355 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1356 // Java calling convention forces doubles to be aligned. | |
| 1357 const bool Matcher::misaligned_doubles_ok = true; | |
| 1358 | |
| 1359 | |
| 1360 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1361 // Get the memory operand from the node | |
| 1362 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1363 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1364 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1365 uint opcnt = 1; // First operand | |
| 1366 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1367 while( idx >= skipped+num_edges ) { | |
| 1368 skipped += num_edges; | |
| 1369 opcnt++; // Bump operand count | |
| 1370 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1371 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1372 } | |
| 1373 | |
| 1374 MachOper *memory = node->_opnds[opcnt]; | |
| 1375 MachOper *new_memory = NULL; | |
| 1376 switch (memory->opcode()) { | |
| 1377 case DIRECT: | |
| 1378 case INDOFFSET32X: | |
| 1379 // No transformation necessary. | |
| 1380 return; | |
| 1381 case INDIRECT: | |
| 1382 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1383 break; | |
| 1384 case INDOFFSET8: | |
| 1385 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1386 break; | |
| 1387 case INDOFFSET32: | |
| 1388 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1389 break; | |
| 1390 case INDINDEXOFFSET: | |
| 1391 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1392 break; | |
| 1393 case INDINDEXSCALE: | |
| 1394 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1395 break; | |
| 1396 case INDINDEXSCALEOFFSET: | |
| 1397 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1398 break; | |
| 1399 case LOAD_LONG_INDIRECT: | |
| 1400 case LOAD_LONG_INDOFFSET32: | |
| 1401 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1402 return; | |
| 1403 default: | |
| 1404 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1405 return; | |
| 1406 } | |
| 1407 node->_opnds[opcnt] = new_memory; | |
| 1408 } | |
| 1409 | |
| 1410 // Advertise here if the CPU requires explicit rounding operations | |
| 1411 // to implement the UseStrictFP mode. | |
| 1412 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1413 | |
| 1414 // Do floats take an entire double register or just half? | |
| 1415 const bool Matcher::float_in_double = true; | |
| 1416 // Do ints take an entire long register or just half? | |
| 1417 const bool Matcher::int_in_long = false; | |
| 1418 | |
| 1419 // Return whether or not this register is ever used as an argument. This | |
| 1420 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1421 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1422 // arguments in those registers not be available to the callee. | |
| 1423 bool Matcher::can_be_java_arg( int reg ) { | |
| 1424 if( reg == ECX_num || reg == EDX_num ) return true; | |
| 1425 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; | |
| 1426 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; | |
| 1427 return false; | |
| 1428 } | |
| 1429 | |
| 1430 bool Matcher::is_spillable_arg( int reg ) { | |
| 1431 return can_be_java_arg(reg); | |
| 1432 } | |
| 1433 | |
| 1434 // Register for DIVI projection of divmodI | |
| 1435 RegMask Matcher::divI_proj_mask() { | |
| 1436 return EAX_REG_mask; | |
| 1437 } | |
| 1438 | |
| 1439 // Register for MODI projection of divmodI | |
| 1440 RegMask Matcher::modI_proj_mask() { | |
| 1441 return EDX_REG_mask; | |
| 1442 } | |
| 1443 | |
| 1444 // Register for DIVL projection of divmodL | |
| 1445 RegMask Matcher::divL_proj_mask() { | |
| 1446 ShouldNotReachHere(); | |
| 1447 return RegMask(); | |
| 1448 } | |
| 1449 | |
| 1450 // Register for MODL projection of divmodL | |
| 1451 RegMask Matcher::modL_proj_mask() { | |
| 1452 ShouldNotReachHere(); | |
| 1453 return RegMask(); | |
| 1454 } | |
| 1455 | |
| 1456 %} | |
| 1457 | |
| 1458 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1459 // This block specifies the encoding classes used by the compiler to output | |
| 1460 // byte streams. Encoding classes generate functions which are called by | |
| 1461 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1462 // instruction. Operands specify their base encoding interface with the | |
| 1463 // interface keyword. There are currently supported four interfaces, | |
| 1464 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1465 // operand to generate a function which returns its register number when | |
| 1466 // queried. CONST_INTER causes an operand to generate a function which | |
| 1467 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1468 // operand to generate four functions which return the Base Register, the | |
| 1469 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1470 // queried. COND_INTER causes an operand to generate six functions which | |
| 1471 // return the encoding code (ie - encoding bits for the instruction) | |
| 1472 // associated with each basic boolean condition for a conditional instruction. | |
| 1473 // Instructions specify two basic values for encoding. They use the | |
| 1474 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1475 // the class names specified in the encoding block), and they use the | |
| 1476 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1477 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1478 // needs for encoding need to be specified. | |
| 1479 encode %{ | |
| 1480 // Build emit functions for each basic byte or larger field in the intel | |
| 1481 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1482 // code in the enc_class source block. Emit functions will live in the | |
| 1483 // main source block for now. In future, we can generalize this by | |
| 1484 // adding a syntax that specifies the sizes of fields in an order, | |
| 1485 // so that the adlc can build the emit functions automagically | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1486 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1487 // Emit primary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1488 enc_class OpcP %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1489 emit_opcode(cbuf, $primary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1490 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1491 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1492 // Emit secondary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1493 enc_class OpcS %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1494 emit_opcode(cbuf, $secondary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1495 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1496 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1497 // Emit opcode directly |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1498 enc_class Opcode(immI d8) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1499 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1500 %} |
| 1501 | |
| 1502 enc_class SizePrefix %{ | |
| 1503 emit_opcode(cbuf,0x66); | |
| 1504 %} | |
| 1505 | |
| 1506 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1507 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1508 %} | |
| 1509 | |
| 1510 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) | |
| 1511 emit_opcode(cbuf,$opcode$$constant); | |
| 1512 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1513 %} | |
| 1514 | |
| 1515 enc_class mov_r32_imm0( eRegI dst ) %{ | |
| 1516 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 | |
| 1517 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1518 %} | |
| 1519 | |
| 1520 enc_class cdq_enc %{ | |
| 1521 // Full implementation of Java idiv and irem; checks for | |
| 1522 // special case as described in JVM spec., p.243 & p.271. | |
| 1523 // | |
| 1524 // normal case special case | |
| 1525 // | |
| 1526 // input : rax,: dividend min_int | |
| 1527 // reg: divisor -1 | |
| 1528 // | |
| 1529 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1530 // rdx: remainder (= rax, irem reg) 0 | |
| 1531 // | |
| 1532 // Code sequnce: | |
| 1533 // | |
| 1534 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1535 // 0F 85 0B 00 00 00 jne normal_case | |
| 1536 // 33 D2 xor rdx,edx | |
| 1537 // 83 F9 FF cmp rcx,0FFh | |
| 1538 // 0F 84 03 00 00 00 je done | |
| 1539 // normal_case: | |
| 1540 // 99 cdq | |
| 1541 // F7 F9 idiv rax,ecx | |
| 1542 // done: | |
| 1543 // | |
| 1544 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1545 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1546 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1547 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1548 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1549 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1550 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1551 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1552 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1553 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1554 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1555 // normal_case: | |
| 1556 emit_opcode(cbuf,0x99); // cdq | |
| 1557 // idiv (note: must be emitted by the user of this rule) | |
| 1558 // normal: | |
| 1559 %} | |
| 1560 | |
| 1561 // Dense encoding for older common ops | |
| 1562 enc_class Opc_plus(immI opcode, eRegI reg) %{ | |
| 1563 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); | |
| 1564 %} | |
| 1565 | |
| 1566 | |
| 1567 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1568 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1569 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1571 emit_opcode(cbuf, $primary | 0x02); | |
| 1572 } | |
| 1573 else { // If 32-bit immediate | |
| 1574 emit_opcode(cbuf, $primary); | |
| 1575 } | |
| 1576 %} | |
| 1577 | |
| 1578 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m | |
| 1579 // Emit primary opcode and set sign-extend bit | |
| 1580 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1582 emit_opcode(cbuf, $primary | 0x02); } | |
| 1583 else { // If 32-bit immediate | |
| 1584 emit_opcode(cbuf, $primary); | |
| 1585 } | |
| 1586 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1587 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1588 %} | |
| 1589 | |
| 1590 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1591 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1592 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1593 $$$emit8$imm$$constant; | |
| 1594 } | |
| 1595 else { // If 32-bit immediate | |
| 1596 // Output immediate | |
| 1597 $$$emit32$imm$$constant; | |
| 1598 } | |
| 1599 %} | |
| 1600 | |
| 1601 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1602 // Emit primary opcode and set sign-extend bit | |
| 1603 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1604 int con = (int)$imm$$constant; // Throw away top bits | |
| 1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1606 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1607 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1609 else emit_d32(cbuf,con); | |
| 1610 %} | |
| 1611 | |
| 1612 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1613 // Emit primary opcode and set sign-extend bit | |
| 1614 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1615 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1616 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1617 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1618 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1619 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1620 else emit_d32(cbuf,con); | |
| 1621 %} | |
| 1622 | |
| 1623 enc_class Lbl (label labl) %{ // JMP, CALL | |
| 1624 Label *l = $labl$$label; | |
| 1625 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); | |
| 1626 %} | |
| 1627 | |
| 1628 enc_class LblShort (label labl) %{ // JMP, CALL | |
| 1629 Label *l = $labl$$label; | |
| 1630 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; | |
| 1631 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 1632 emit_d8(cbuf, disp); | |
| 1633 %} | |
| 1634 | |
| 1635 enc_class OpcSReg (eRegI dst) %{ // BSWAP | |
| 1636 emit_cc(cbuf, $secondary, $dst$$reg ); | |
| 1637 %} | |
| 1638 | |
| 1639 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1640 int destlo = $dst$$reg; | |
| 1641 int desthi = HIGH_FROM_LOW(destlo); | |
| 1642 // bswap lo | |
| 1643 emit_opcode(cbuf, 0x0F); | |
| 1644 emit_cc(cbuf, 0xC8, destlo); | |
| 1645 // bswap hi | |
| 1646 emit_opcode(cbuf, 0x0F); | |
| 1647 emit_cc(cbuf, 0xC8, desthi); | |
| 1648 // xchg lo and hi | |
| 1649 emit_opcode(cbuf, 0x87); | |
| 1650 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1651 %} | |
| 1652 | |
| 1653 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... | |
| 1654 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); | |
| 1655 %} | |
| 1656 | |
| 1657 enc_class Jcc (cmpOp cop, label labl) %{ // JCC | |
| 1658 Label *l = $labl$$label; | |
| 1659 $$$emit8$primary; | |
| 1660 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1661 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); | |
| 1662 %} | |
| 1663 | |
| 1664 enc_class JccShort (cmpOp cop, label labl) %{ // JCC | |
| 1665 Label *l = $labl$$label; | |
| 1666 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 1667 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; | |
| 1668 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 1669 emit_d8(cbuf, disp); | |
| 1670 %} | |
| 1671 | |
| 1672 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1673 $$$emit8$primary; | |
| 1674 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1675 %} | |
| 1676 | |
| 1677 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV | |
| 1678 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); | |
| 1679 emit_d8(cbuf, op >> 8 ); | |
| 1680 emit_d8(cbuf, op & 255); | |
| 1681 %} | |
| 1682 | |
| 1683 // emulate a CMOV with a conditional branch around a MOV | |
| 1684 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1685 // Invert sense of branch from sense of CMOV | |
| 1686 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1687 emit_d8( cbuf, $brOffs$$constant ); | |
| 1688 %} | |
| 1689 | |
| 1690 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1691 Register Redi = as_Register(EDI_enc); // result register | |
| 1692 Register Reax = as_Register(EAX_enc); // super class | |
| 1693 Register Recx = as_Register(ECX_enc); // killed | |
| 1694 Register Resi = as_Register(ESI_enc); // sub class | |
| 1695 Label hit, miss; | |
| 1696 | |
| 1697 MacroAssembler _masm(&cbuf); | |
| 1698 // Compare super with sub directly, since super is not in its own SSA. | |
| 1699 // The compiler used to emit this test, but we fold it in here, | |
| 1700 // to allow platform-specific tweaking on sparc. | |
| 304 | 1701 __ cmpptr(Reax, Resi); |
| 0 | 1702 __ jcc(Assembler::equal, hit); |
| 1703 #ifndef PRODUCT | |
| 304 | 1704 __ incrementl(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); |
| 0 | 1705 #endif //PRODUCT |
| 304 | 1706 __ movptr(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())); |
| 0 | 1707 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes())); |
| 304 | 1708 __ addptr(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
| 0 | 1709 __ repne_scan(); |
| 1710 __ jcc(Assembler::notEqual, miss); | |
| 304 | 1711 __ movptr(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax); |
| 0 | 1712 __ bind(hit); |
| 1713 if( $primary ) | |
| 304 | 1714 __ xorptr(Redi,Redi); |
| 0 | 1715 __ bind(miss); |
| 1716 %} | |
| 1717 | |
| 1718 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1719 MacroAssembler masm(&cbuf); | |
| 1720 int start = masm.offset(); | |
| 1721 if (UseSSE >= 2) { | |
| 1722 if (VerifyFPU) { | |
| 1723 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1724 } | |
| 1725 } else { | |
| 1726 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1727 // Compiled code leaves it dirty. Do cleanup now. | |
| 1728 masm.empty_FPU_stack(); | |
| 1729 } | |
| 1730 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1731 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1732 } else { | |
| 1733 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1734 } | |
| 1735 %} | |
| 1736 | |
| 1737 enc_class Verify_FPU_For_Leaf %{ | |
| 1738 if( VerifyFPU ) { | |
| 1739 MacroAssembler masm(&cbuf); | |
| 1740 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1741 } | |
| 1742 %} | |
| 1743 | |
| 1744 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1745 // This is the instruction starting address for relocation info. | |
| 1746 cbuf.set_inst_mark(); | |
| 1747 $$$emit8$primary; | |
| 1748 // CALL directly to the runtime | |
| 1749 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1750 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1751 | |
| 1752 if (UseSSE >= 2) { | |
| 1753 MacroAssembler _masm(&cbuf); | |
| 1754 BasicType rt = tf()->return_type(); | |
| 1755 | |
| 1756 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1757 // A C runtime call where the return value is unused. In SSE2+ | |
| 1758 // mode the result needs to be removed from the FPU stack. It's | |
| 1759 // likely that this function call could be removed by the | |
| 1760 // optimizer if the C function is a pure function. | |
| 1761 __ ffree(0); | |
| 1762 } else if (rt == T_FLOAT) { | |
| 304 | 1763 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1764 __ fstp_s(Address(rsp, 0)); |
| 1765 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1766 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1767 } else if (rt == T_DOUBLE) { |
| 304 | 1768 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1769 __ fstp_d(Address(rsp, 0)); |
| 1770 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1771 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1772 } |
| 1773 } | |
| 1774 %} | |
| 1775 | |
| 1776 | |
| 1777 enc_class pre_call_FPU %{ | |
| 1778 // If method sets FPU control word restore it here | |
| 1779 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1780 MacroAssembler masm(&cbuf); | |
| 1781 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1782 } | |
| 1783 %} | |
| 1784 | |
| 1785 enc_class post_call_FPU %{ | |
| 1786 // If method sets FPU control word do it here also | |
| 1787 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1788 MacroAssembler masm(&cbuf); | |
| 1789 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1790 } | |
| 1791 %} | |
| 1792 | |
| 1793 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1794 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1795 // who we intended to call. | |
| 1796 cbuf.set_inst_mark(); | |
| 1797 $$$emit8$primary; | |
| 1798 if ( !_method ) { | |
| 1799 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1800 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1801 } else if(_optimized_virtual) { | |
| 1802 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1803 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1804 } else { | |
| 1805 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1806 static_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1807 } | |
| 1808 if( _method ) { // Emit stub for static call | |
| 1809 emit_java_to_interp(cbuf); | |
| 1810 } | |
| 1811 %} | |
| 1812 | |
| 1813 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 1814 // !!!!! | |
| 1815 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info | |
| 1816 // emit_call_dynamic_prologue( cbuf ); | |
| 1817 cbuf.set_inst_mark(); | |
| 1818 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 | |
| 1819 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); | |
| 1820 address virtual_call_oop_addr = cbuf.inst_mark(); | |
| 1821 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1822 // who we intended to call. | |
| 1823 cbuf.set_inst_mark(); | |
| 1824 $$$emit8$primary; | |
| 1825 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1826 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); | |
| 1827 %} | |
| 1828 | |
| 1829 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 1830 int disp = in_bytes(methodOopDesc::from_compiled_offset()); | |
| 1831 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); | |
| 1832 | |
| 1833 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] | |
| 1834 cbuf.set_inst_mark(); | |
| 1835 $$$emit8$primary; | |
| 1836 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1837 emit_d8(cbuf, disp); // Displacement | |
| 1838 | |
| 1839 %} | |
| 1840 | |
| 1841 enc_class Xor_Reg (eRegI dst) %{ | |
| 1842 emit_opcode(cbuf, 0x33); | |
| 1843 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 1844 %} | |
| 1845 | |
| 1846 // Following encoding is no longer used, but may be restored if calling | |
| 1847 // convention changes significantly. | |
| 1848 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1849 // | |
| 1850 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1851 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1852 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1853 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1854 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1855 // | |
| 1856 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1857 // // // so we load it immediately before the call | |
| 1858 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1859 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1860 // | |
| 1861 // // xor rbp,ebp | |
| 1862 // emit_opcode(cbuf, 0x33); | |
| 1863 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1864 // | |
| 1865 // // CALL to interpreter. | |
| 1866 // cbuf.set_inst_mark(); | |
| 1867 // $$$emit8$primary; | |
| 1868 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4), | |
| 1869 // runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1870 // %} | |
| 1871 | |
| 1872 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR | |
| 1873 $$$emit8$primary; | |
| 1874 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1875 $$$emit8$shift$$constant; | |
| 1876 %} | |
| 1877 | |
| 1878 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate | |
| 1879 // Load immediate does not have a zero or sign extended version | |
| 1880 // for 8-bit immediates | |
| 1881 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1882 $$$emit32$src$$constant; | |
| 1883 %} | |
| 1884 | |
| 1885 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate | |
| 1886 // Load immediate does not have a zero or sign extended version | |
| 1887 // for 8-bit immediates | |
| 1888 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1889 $$$emit32$src$$constant; | |
| 1890 %} | |
| 1891 | |
| 1892 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1893 // Load immediate does not have a zero or sign extended version | |
| 1894 // for 8-bit immediates | |
| 1895 int dst_enc = $dst$$reg; | |
| 1896 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1897 if (src_con == 0) { | |
| 1898 // xor dst, dst | |
| 1899 emit_opcode(cbuf, 0x33); | |
| 1900 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1901 } else { | |
| 1902 emit_opcode(cbuf, $primary + dst_enc); | |
| 1903 emit_d32(cbuf, src_con); | |
| 1904 } | |
| 1905 %} | |
| 1906 | |
| 1907 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1908 // Load immediate does not have a zero or sign extended version | |
| 1909 // for 8-bit immediates | |
| 1910 int dst_enc = $dst$$reg + 2; | |
| 1911 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1912 if (src_con == 0) { | |
| 1913 // xor dst, dst | |
| 1914 emit_opcode(cbuf, 0x33); | |
| 1915 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1916 } else { | |
| 1917 emit_opcode(cbuf, $primary + dst_enc); | |
| 1918 emit_d32(cbuf, src_con); | |
| 1919 } | |
| 1920 %} | |
| 1921 | |
| 1922 | |
| 1923 enc_class LdImmD (immD src) %{ // Load Immediate | |
| 1924 if( is_positive_zero_double($src$$constant)) { | |
| 1925 // FLDZ | |
| 1926 emit_opcode(cbuf,0xD9); | |
| 1927 emit_opcode(cbuf,0xEE); | |
| 1928 } else if( is_positive_one_double($src$$constant)) { | |
| 1929 // FLD1 | |
| 1930 emit_opcode(cbuf,0xD9); | |
| 1931 emit_opcode(cbuf,0xE8); | |
| 1932 } else { | |
| 1933 emit_opcode(cbuf,0xDD); | |
| 1934 emit_rm(cbuf, 0x0, 0x0, 0x5); | |
| 1935 emit_double_constant(cbuf, $src$$constant); | |
| 1936 } | |
| 1937 %} | |
| 1938 | |
| 1939 | |
| 1940 enc_class LdImmF (immF src) %{ // Load Immediate | |
| 1941 if( is_positive_zero_float($src$$constant)) { | |
| 1942 emit_opcode(cbuf,0xD9); | |
| 1943 emit_opcode(cbuf,0xEE); | |
| 1944 } else if( is_positive_one_float($src$$constant)) { | |
| 1945 emit_opcode(cbuf,0xD9); | |
| 1946 emit_opcode(cbuf,0xE8); | |
| 1947 } else { | |
| 1948 $$$emit8$primary; | |
| 1949 // Load immediate does not have a zero or sign extended version | |
| 1950 // for 8-bit immediates | |
| 1951 // First load to TOS, then move to dst | |
| 1952 emit_rm(cbuf, 0x0, 0x0, 0x5); | |
| 1953 emit_float_constant(cbuf, $src$$constant); | |
| 1954 } | |
| 1955 %} | |
| 1956 | |
| 1957 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate | |
| 1958 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 1959 emit_float_constant(cbuf, $con$$constant); | |
| 1960 %} | |
| 1961 | |
| 1962 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate | |
| 1963 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 1964 emit_double_constant(cbuf, $con$$constant); | |
| 1965 %} | |
| 1966 | |
| 1967 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant | |
| 1968 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
| 1969 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 1970 emit_opcode(cbuf, 0x0F); | |
| 1971 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 1972 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 1973 emit_double_constant(cbuf, $con$$constant); | |
| 1974 %} | |
| 1975 | |
| 1976 enc_class Opc_MemImm_F(immF src) %{ | |
| 1977 cbuf.set_inst_mark(); | |
| 1978 $$$emit8$primary; | |
| 1979 emit_rm(cbuf, 0x0, $secondary, 0x5); | |
| 1980 emit_float_constant(cbuf, $src$$constant); | |
| 1981 %} | |
| 1982 | |
| 1983 | |
| 1984 enc_class MovI2X_reg(regX dst, eRegI src) %{ | |
| 1985 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 1986 emit_opcode(cbuf, 0x0F ); | |
| 1987 emit_opcode(cbuf, 0x6E ); | |
| 1988 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1989 %} | |
| 1990 | |
| 1991 enc_class MovX2I_reg(eRegI dst, regX src) %{ | |
| 1992 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 1993 emit_opcode(cbuf, 0x0F ); | |
| 1994 emit_opcode(cbuf, 0x7E ); | |
| 1995 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 1996 %} | |
| 1997 | |
| 1998 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ | |
| 1999 { // MOVD $dst,$src.lo | |
| 2000 emit_opcode(cbuf,0x66); | |
| 2001 emit_opcode(cbuf,0x0F); | |
| 2002 emit_opcode(cbuf,0x6E); | |
| 2003 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2004 } | |
| 2005 { // MOVD $tmp,$src.hi | |
| 2006 emit_opcode(cbuf,0x66); | |
| 2007 emit_opcode(cbuf,0x0F); | |
| 2008 emit_opcode(cbuf,0x6E); | |
| 2009 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2010 } | |
| 2011 { // PUNPCKLDQ $dst,$tmp | |
| 2012 emit_opcode(cbuf,0x66); | |
| 2013 emit_opcode(cbuf,0x0F); | |
| 2014 emit_opcode(cbuf,0x62); | |
| 2015 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); | |
| 2016 } | |
| 2017 %} | |
| 2018 | |
| 2019 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ | |
| 2020 { // MOVD $dst.lo,$src | |
| 2021 emit_opcode(cbuf,0x66); | |
| 2022 emit_opcode(cbuf,0x0F); | |
| 2023 emit_opcode(cbuf,0x7E); | |
| 2024 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2025 } | |
| 2026 { // PSHUFLW $tmp,$src,0x4E (01001110b) | |
| 2027 emit_opcode(cbuf,0xF2); | |
| 2028 emit_opcode(cbuf,0x0F); | |
| 2029 emit_opcode(cbuf,0x70); | |
| 2030 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2031 emit_d8(cbuf, 0x4E); | |
| 2032 } | |
| 2033 { // MOVD $dst.hi,$tmp | |
| 2034 emit_opcode(cbuf,0x66); | |
| 2035 emit_opcode(cbuf,0x0F); | |
| 2036 emit_opcode(cbuf,0x7E); | |
| 2037 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2038 } | |
| 2039 %} | |
| 2040 | |
| 2041 | |
| 2042 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2043 enc_class enc_Copy( eRegI dst, eRegI src ) %{ | |
| 2044 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2045 %} | |
| 2046 | |
| 2047 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ | |
| 2048 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2049 %} | |
| 2050 | |
| 2051 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2052 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ | |
| 2053 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2054 %} | |
| 2055 | |
| 2056 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 2057 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2058 %} | |
| 2059 | |
| 2060 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2061 $$$emit8$primary; | |
| 2062 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2063 %} | |
| 2064 | |
| 2065 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2066 $$$emit8$secondary; | |
| 2067 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2068 %} | |
| 2069 | |
| 2070 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2071 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2072 %} | |
| 2073 | |
| 2074 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2075 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2076 %} | |
| 2077 | |
| 2078 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ | |
| 2079 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2080 %} | |
| 2081 | |
| 2082 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2083 // Output immediate | |
| 2084 $$$emit32$src$$constant; | |
| 2085 %} | |
| 2086 | |
| 2087 enc_class Con32F_as_bits(immF src) %{ // storeF_imm | |
| 2088 // Output Float immediate bits | |
| 2089 jfloat jf = $src$$constant; | |
| 2090 int jf_as_bits = jint_cast( jf ); | |
| 2091 emit_d32(cbuf, jf_as_bits); | |
| 2092 %} | |
| 2093 | |
| 2094 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm | |
| 2095 // Output Float immediate bits | |
| 2096 jfloat jf = $src$$constant; | |
| 2097 int jf_as_bits = jint_cast( jf ); | |
| 2098 emit_d32(cbuf, jf_as_bits); | |
| 2099 %} | |
| 2100 | |
| 2101 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2102 // Output immediate | |
| 2103 $$$emit16$src$$constant; | |
| 2104 %} | |
| 2105 | |
| 2106 enc_class Con_d32(immI src) %{ | |
| 2107 emit_d32(cbuf,$src$$constant); | |
| 2108 %} | |
| 2109 | |
| 2110 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2111 // Output immediate memory reference | |
| 2112 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2113 emit_d32(cbuf, 0x00); | |
| 2114 %} | |
| 2115 | |
| 2116 enc_class lock_prefix( ) %{ | |
| 2117 if( os::is_MP() ) | |
| 2118 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2119 %} | |
| 2120 | |
| 2121 // Cmp-xchg long value. | |
| 2122 // Note: we need to swap rbx, and rcx before and after the | |
| 2123 // cmpxchg8 instruction because the instruction uses | |
| 2124 // rcx as the high order word of the new value to store but | |
| 2125 // our register encoding uses rbx,. | |
| 2126 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2127 | |
| 2128 // XCHG rbx,ecx | |
| 2129 emit_opcode(cbuf,0x87); | |
| 2130 emit_opcode(cbuf,0xD9); | |
| 2131 // [Lock] | |
| 2132 if( os::is_MP() ) | |
| 2133 emit_opcode(cbuf,0xF0); | |
| 2134 // CMPXCHG8 [Eptr] | |
| 2135 emit_opcode(cbuf,0x0F); | |
| 2136 emit_opcode(cbuf,0xC7); | |
| 2137 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2138 // XCHG rbx,ecx | |
| 2139 emit_opcode(cbuf,0x87); | |
| 2140 emit_opcode(cbuf,0xD9); | |
| 2141 %} | |
| 2142 | |
| 2143 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2144 // [Lock] | |
| 2145 if( os::is_MP() ) | |
| 2146 emit_opcode(cbuf,0xF0); | |
| 2147 | |
| 2148 // CMPXCHG [Eptr] | |
| 2149 emit_opcode(cbuf,0x0F); | |
| 2150 emit_opcode(cbuf,0xB1); | |
| 2151 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2152 %} | |
| 2153 | |
| 2154 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2155 int res_encoding = $res$$reg; | |
| 2156 | |
| 2157 // MOV res,0 | |
| 2158 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2159 emit_d32( cbuf, 0 ); | |
| 2160 // JNE,s fail | |
| 2161 emit_opcode(cbuf,0x75); | |
| 2162 emit_d8(cbuf, 5 ); | |
| 2163 // MOV res,1 | |
| 2164 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2165 emit_d32( cbuf, 1 ); | |
| 2166 // fail: | |
| 2167 %} | |
| 2168 | |
| 2169 enc_class set_instruction_start( ) %{ | |
| 2170 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2171 %} | |
| 2172 | |
| 2173 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 2174 int reg_encoding = $ereg$$reg; | |
| 2175 int base = $mem$$base; | |
| 2176 int index = $mem$$index; | |
| 2177 int scale = $mem$$scale; | |
| 2178 int displace = $mem$$disp; | |
| 2179 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2181 %} | |
| 2182 | |
| 2183 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2184 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2185 int base = $mem$$base; | |
| 2186 int index = $mem$$index; | |
| 2187 int scale = $mem$$scale; | |
| 2188 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
| 2189 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); | |
| 2190 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); | |
| 2191 %} | |
| 2192 | |
| 2193 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2194 int r1, r2; | |
| 2195 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2196 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2197 emit_opcode(cbuf,0x0F); | |
| 2198 emit_opcode(cbuf,$tertiary); | |
| 2199 emit_rm(cbuf, 0x3, r1, r2); | |
| 2200 emit_d8(cbuf,$cnt$$constant); | |
| 2201 emit_d8(cbuf,$primary); | |
| 2202 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2203 emit_d8(cbuf,$cnt$$constant); | |
| 2204 %} | |
| 2205 | |
| 2206 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2207 emit_opcode( cbuf, 0x8B ); // Move | |
| 2208 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2209 emit_d8(cbuf,$primary); | |
| 2210 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 2211 emit_d8(cbuf,$cnt$$constant-32); | |
| 2212 emit_d8(cbuf,$primary); | |
| 2213 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2214 emit_d8(cbuf,31); | |
| 2215 %} | |
| 2216 | |
| 2217 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2218 int r1, r2; | |
| 2219 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2220 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2221 | |
| 2222 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2223 emit_rm(cbuf, 0x3, r1, r2); | |
| 2224 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2225 emit_opcode(cbuf,$primary); | |
| 2226 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2227 emit_d8(cbuf,$cnt$$constant-32); | |
| 2228 } | |
| 2229 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2230 emit_rm(cbuf, 0x3, r2, r2); | |
| 2231 %} | |
| 2232 | |
| 2233 // Clone of RegMem but accepts an extra parameter to access each | |
| 2234 // half of a double in memory; it never needs relocation info. | |
| 2235 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ | |
| 2236 emit_opcode(cbuf,$opcode$$constant); | |
| 2237 int reg_encoding = $rm_reg$$reg; | |
| 2238 int base = $mem$$base; | |
| 2239 int index = $mem$$index; | |
| 2240 int scale = $mem$$scale; | |
| 2241 int displace = $mem$$disp + $disp_for_half$$constant; | |
| 2242 bool disp_is_oop = false; | |
| 2243 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2244 %} | |
| 2245 | |
| 2246 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2247 // | |
| 2248 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2249 // and it never needs relocation information. | |
| 2250 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2251 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2252 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2253 int base = $mem$$base; | |
| 2254 int index = $mem$$index; | |
| 2255 int scale = $mem$$scale; | |
| 2256 int displace = $mem$$disp; | |
| 2257 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); | |
| 2258 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); | |
| 2259 %} | |
| 2260 | |
| 2261 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2262 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2263 int base = $mem$$base; | |
| 2264 int index = $mem$$index; | |
| 2265 int scale = $mem$$scale; | |
| 2266 int displace = $mem$$disp; | |
| 2267 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2268 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 2269 %} | |
| 2270 | |
| 2271 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea | |
| 2272 int reg_encoding = $dst$$reg; | |
| 2273 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2274 int index = 0x04; // 0x04 indicates no index | |
| 2275 int scale = 0x00; // 0x00 indicates no scale | |
| 2276 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2277 bool disp_is_oop = false; | |
| 2278 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN | |
| 2282 // Compare dst,src | |
| 2283 emit_opcode(cbuf,0x3B); | |
| 2284 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2285 // jmp dst < src around move | |
| 2286 emit_opcode(cbuf,0x7C); | |
| 2287 emit_d8(cbuf,2); | |
| 2288 // move dst,src | |
| 2289 emit_opcode(cbuf,0x8B); | |
| 2290 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2291 %} | |
| 2292 | |
| 2293 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX | |
| 2294 // Compare dst,src | |
| 2295 emit_opcode(cbuf,0x3B); | |
| 2296 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2297 // jmp dst > src around move | |
| 2298 emit_opcode(cbuf,0x7F); | |
| 2299 emit_d8(cbuf,2); | |
| 2300 // move dst,src | |
| 2301 emit_opcode(cbuf,0x8B); | |
| 2302 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2303 %} | |
| 2304 | |
| 2305 enc_class enc_FP_store(memory mem, regD src) %{ | |
| 2306 // If src is FPR1, we can just FST to store it. | |
| 2307 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2308 int reg_encoding = 0x2; // Just store | |
| 2309 int base = $mem$$base; | |
| 2310 int index = $mem$$index; | |
| 2311 int scale = $mem$$scale; | |
| 2312 int displace = $mem$$disp; | |
| 2313 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2314 if( $src$$reg != FPR1L_enc ) { | |
| 2315 reg_encoding = 0x3; // Store & pop | |
| 2316 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2317 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2318 } | |
| 2319 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2320 emit_opcode(cbuf,$primary); | |
| 2321 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2322 %} | |
| 2323 | |
| 2324 enc_class neg_reg(eRegI dst) %{ | |
| 2325 // NEG $dst | |
| 2326 emit_opcode(cbuf,0xF7); | |
| 2327 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2328 %} | |
| 2329 | |
| 2330 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2331 // SETLT $dst | |
| 2332 emit_opcode(cbuf,0x0F); | |
| 2333 emit_opcode(cbuf,0x9C); | |
| 2334 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2335 %} | |
| 2336 | |
| 2337 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2338 int tmpReg = $tmp$$reg; | |
| 2339 | |
| 2340 // SUB $p,$q | |
| 2341 emit_opcode(cbuf,0x2B); | |
| 2342 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2343 // SBB $tmp,$tmp | |
| 2344 emit_opcode(cbuf,0x1B); | |
| 2345 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2346 // AND $tmp,$y | |
| 2347 emit_opcode(cbuf,0x23); | |
| 2348 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2349 // ADD $p,$tmp | |
| 2350 emit_opcode(cbuf,0x03); | |
| 2351 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2352 %} | |
| 2353 | |
| 2354 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2355 int tmpReg = $tmp$$reg; | |
| 2356 | |
| 2357 // SUB $p,$q | |
| 2358 emit_opcode(cbuf,0x2B); | |
| 2359 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2360 // SBB $tmp,$tmp | |
| 2361 emit_opcode(cbuf,0x1B); | |
| 2362 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2363 // AND $tmp,$y | |
| 2364 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2365 emit_opcode(cbuf,0x23); | |
| 2366 int reg_encoding = tmpReg; | |
| 2367 int base = $mem$$base; | |
| 2368 int index = $mem$$index; | |
| 2369 int scale = $mem$$scale; | |
| 2370 int displace = $mem$$disp; | |
| 2371 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2372 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2373 // ADD $p,$tmp | |
| 2374 emit_opcode(cbuf,0x03); | |
| 2375 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2376 %} | |
| 2377 | |
| 2378 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2379 // TEST shift,32 | |
| 2380 emit_opcode(cbuf,0xF7); | |
| 2381 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2382 emit_d32(cbuf,0x20); | |
| 2383 // JEQ,s small | |
| 2384 emit_opcode(cbuf, 0x74); | |
| 2385 emit_d8(cbuf, 0x04); | |
| 2386 // MOV $dst.hi,$dst.lo | |
| 2387 emit_opcode( cbuf, 0x8B ); | |
| 2388 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2389 // CLR $dst.lo | |
| 2390 emit_opcode(cbuf, 0x33); | |
| 2391 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2392 // small: | |
| 2393 // SHLD $dst.hi,$dst.lo,$shift | |
| 2394 emit_opcode(cbuf,0x0F); | |
| 2395 emit_opcode(cbuf,0xA5); | |
| 2396 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2397 // SHL $dst.lo,$shift" | |
| 2398 emit_opcode(cbuf,0xD3); | |
| 2399 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2400 %} | |
| 2401 | |
| 2402 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2403 // TEST shift,32 | |
| 2404 emit_opcode(cbuf,0xF7); | |
| 2405 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2406 emit_d32(cbuf,0x20); | |
| 2407 // JEQ,s small | |
| 2408 emit_opcode(cbuf, 0x74); | |
| 2409 emit_d8(cbuf, 0x04); | |
| 2410 // MOV $dst.lo,$dst.hi | |
| 2411 emit_opcode( cbuf, 0x8B ); | |
| 2412 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2413 // CLR $dst.hi | |
| 2414 emit_opcode(cbuf, 0x33); | |
| 2415 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2416 // small: | |
| 2417 // SHRD $dst.lo,$dst.hi,$shift | |
| 2418 emit_opcode(cbuf,0x0F); | |
| 2419 emit_opcode(cbuf,0xAD); | |
| 2420 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2421 // SHR $dst.hi,$shift" | |
| 2422 emit_opcode(cbuf,0xD3); | |
| 2423 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2424 %} | |
| 2425 | |
| 2426 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2427 // TEST shift,32 | |
| 2428 emit_opcode(cbuf,0xF7); | |
| 2429 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2430 emit_d32(cbuf,0x20); | |
| 2431 // JEQ,s small | |
| 2432 emit_opcode(cbuf, 0x74); | |
| 2433 emit_d8(cbuf, 0x05); | |
| 2434 // MOV $dst.lo,$dst.hi | |
| 2435 emit_opcode( cbuf, 0x8B ); | |
| 2436 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2437 // SAR $dst.hi,31 | |
| 2438 emit_opcode(cbuf, 0xC1); | |
| 2439 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2440 emit_d8(cbuf, 0x1F ); | |
| 2441 // small: | |
| 2442 // SHRD $dst.lo,$dst.hi,$shift | |
| 2443 emit_opcode(cbuf,0x0F); | |
| 2444 emit_opcode(cbuf,0xAD); | |
| 2445 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2446 // SAR $dst.hi,$shift" | |
| 2447 emit_opcode(cbuf,0xD3); | |
| 2448 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2449 %} | |
| 2450 | |
| 2451 | |
| 2452 // ----------------- Encodings for floating point unit ----------------- | |
| 2453 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
| 2454 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV | |
| 2455 $$$emit8$primary; | |
| 2456 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2457 %} | |
| 2458 | |
| 2459 // Pop argument in FPR0 with FSTP ST(0) | |
| 2460 enc_class PopFPU() %{ | |
| 2461 emit_opcode( cbuf, 0xDD ); | |
| 2462 emit_d8( cbuf, 0xD8 ); | |
| 2463 %} | |
| 2464 | |
| 2465 // !!!!! equivalent to Pop_Reg_F | |
| 2466 enc_class Pop_Reg_D( regD dst ) %{ | |
| 2467 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2468 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2469 %} | |
| 2470 | |
| 2471 enc_class Push_Reg_D( regD dst ) %{ | |
| 2472 emit_opcode( cbuf, 0xD9 ); | |
| 2473 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2474 %} | |
| 2475 | |
| 2476 enc_class strictfp_bias1( regD dst ) %{ | |
| 2477 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2478 emit_opcode( cbuf, 0x2D ); | |
| 2479 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2480 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2481 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2482 %} | |
| 2483 | |
| 2484 enc_class strictfp_bias2( regD dst ) %{ | |
| 2485 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2486 emit_opcode( cbuf, 0x2D ); | |
| 2487 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2488 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2489 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2490 %} | |
| 2491 | |
| 2492 // Special case for moving an integer register to a stack slot. | |
| 2493 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2494 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); | |
| 2495 %} | |
| 2496 | |
| 2497 // Special case for moving a register to a stack slot. | |
| 2498 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2499 // Opcode already emitted | |
| 2500 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2501 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2502 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2503 %} | |
| 2504 | |
| 2505 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2506 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2507 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2508 %} | |
| 2509 | |
| 2510 // Push the float in stackSlot 'src' onto FP-stack | |
| 2511 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] | |
| 2512 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); | |
| 2513 %} | |
| 2514 | |
| 2515 // Push the double in stackSlot 'src' onto FP-stack | |
| 2516 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] | |
| 2517 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); | |
| 2518 %} | |
| 2519 | |
| 2520 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
| 2521 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] | |
| 2522 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); | |
| 2523 %} | |
| 2524 | |
| 2525 // Same as Pop_Mem_F except for opcode | |
| 2526 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
| 2527 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] | |
| 2528 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); | |
| 2529 %} | |
| 2530 | |
| 2531 enc_class Pop_Reg_F( regF dst ) %{ | |
| 2532 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2533 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2534 %} | |
| 2535 | |
| 2536 enc_class Push_Reg_F( regF dst ) %{ | |
| 2537 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2538 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2539 %} | |
| 2540 | |
| 2541 // Push FPU's float to a stack-slot, and pop FPU-stack | |
| 2542 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ | |
| 2543 int pop = 0x02; | |
| 2544 if ($src$$reg != FPR1L_enc) { | |
| 2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2546 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2547 pop = 0x03; | |
| 2548 } | |
| 2549 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2550 %} | |
| 2551 | |
| 2552 // Push FPU's double to a stack-slot, and pop FPU-stack | |
| 2553 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ | |
| 2554 int pop = 0x02; | |
| 2555 if ($src$$reg != FPR1L_enc) { | |
| 2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2557 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2558 pop = 0x03; | |
| 2559 } | |
| 2560 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2561 %} | |
| 2562 | |
| 2563 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
| 2564 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ | |
| 2565 int pop = 0xD0 - 1; // -1 since we skip FLD | |
| 2566 if ($src$$reg != FPR1L_enc) { | |
| 2567 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2568 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2569 pop = 0xD8; | |
| 2570 } | |
| 2571 emit_opcode( cbuf, 0xDD ); | |
| 2572 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2573 %} | |
| 2574 | |
| 2575 | |
| 2576 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ | |
| 2577 MacroAssembler masm(&cbuf); | |
| 2578 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg | |
| 2579 masm.fmul( $src2$$reg+0); // value at TOS | |
| 2580 masm.fadd( $src$$reg+0); // value at TOS | |
| 2581 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store | |
| 2582 %} | |
| 2583 | |
| 2584 | |
| 2585 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ | |
| 2586 // load dst in FPR0 | |
| 2587 emit_opcode( cbuf, 0xD9 ); | |
| 2588 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2589 if ($src$$reg != FPR1L_enc) { | |
| 2590 // fincstp | |
| 2591 emit_opcode (cbuf, 0xD9); | |
| 2592 emit_opcode (cbuf, 0xF7); | |
| 2593 // swap src with FPR1: | |
| 2594 // FXCH FPR1 with src | |
| 2595 emit_opcode(cbuf, 0xD9); | |
| 2596 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2597 // fdecstp | |
| 2598 emit_opcode (cbuf, 0xD9); | |
| 2599 emit_opcode (cbuf, 0xF6); | |
| 2600 } | |
| 2601 %} | |
| 2602 | |
| 2603 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ | |
| 2604 // Allocate a word | |
| 2605 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2606 emit_opcode(cbuf,0xEC); | |
| 2607 emit_d8(cbuf,0x08); | |
| 2608 | |
| 2609 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 | |
| 2610 emit_opcode (cbuf, 0x0F ); | |
| 2611 emit_opcode (cbuf, 0x11 ); | |
| 2612 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2613 | |
| 2614 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2615 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2616 | |
| 2617 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 | |
| 2618 emit_opcode (cbuf, 0x0F ); | |
| 2619 emit_opcode (cbuf, 0x11 ); | |
| 2620 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2621 | |
| 2622 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2623 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2624 | |
| 2625 %} | |
| 2626 | |
| 2627 enc_class Push_ModX_encoding( regX src0, regX src1) %{ | |
| 2628 // Allocate a word | |
| 2629 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2630 emit_opcode(cbuf,0xEC); | |
| 2631 emit_d8(cbuf,0x04); | |
| 2632 | |
| 2633 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 | |
| 2634 emit_opcode (cbuf, 0x0F ); | |
| 2635 emit_opcode (cbuf, 0x11 ); | |
| 2636 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2637 | |
| 2638 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2639 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2640 | |
| 2641 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 | |
| 2642 emit_opcode (cbuf, 0x0F ); | |
| 2643 emit_opcode (cbuf, 0x11 ); | |
| 2644 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2645 | |
| 2646 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2647 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2648 | |
| 2649 %} | |
| 2650 | |
| 2651 enc_class Push_ResultXD(regXD dst) %{ | |
| 2652 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] | |
| 2653 | |
| 2654 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] | |
| 2655 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2656 emit_opcode (cbuf, 0x0F ); | |
| 2657 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2658 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2659 | |
| 2660 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2661 emit_opcode(cbuf,0xC4); | |
| 2662 emit_d8(cbuf,0x08); | |
| 2663 %} | |
| 2664 | |
| 2665 enc_class Push_ResultX(regX dst, immI d8) %{ | |
| 2666 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] | |
| 2667 | |
| 2668 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 2669 emit_opcode (cbuf, 0x0F ); | |
| 2670 emit_opcode (cbuf, 0x10 ); | |
| 2671 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2672 | |
| 2673 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) | |
| 2674 emit_opcode(cbuf,0xC4); | |
| 2675 emit_d8(cbuf,$d8$$constant); | |
| 2676 %} | |
| 2677 | |
| 2678 enc_class Push_SrcXD(regXD src) %{ | |
| 2679 // Allocate a word | |
| 2680 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2681 emit_opcode(cbuf,0xEC); | |
| 2682 emit_d8(cbuf,0x08); | |
| 2683 | |
| 2684 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 2685 emit_opcode (cbuf, 0x0F ); | |
| 2686 emit_opcode (cbuf, 0x11 ); | |
| 2687 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2688 | |
| 2689 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2690 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2691 %} | |
| 2692 | |
| 2693 enc_class push_stack_temp_qword() %{ | |
| 2694 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2695 emit_opcode(cbuf,0xEC); | |
| 2696 emit_d8 (cbuf,0x08); | |
| 2697 %} | |
| 2698 | |
| 2699 enc_class pop_stack_temp_qword() %{ | |
| 2700 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2701 emit_opcode(cbuf,0xC4); | |
| 2702 emit_d8 (cbuf,0x08); | |
| 2703 %} | |
| 2704 | |
| 2705 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ | |
| 2706 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src | |
| 2707 emit_opcode (cbuf, 0x0F ); | |
| 2708 emit_opcode (cbuf, 0x11 ); | |
| 2709 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2710 | |
| 2711 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2712 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2713 %} | |
| 2714 | |
| 2715 // Compute X^Y using Intel's fast hardware instructions, if possible. | |
| 2716 // Otherwise return a NaN. | |
| 2717 enc_class pow_exp_core_encoding %{ | |
| 2718 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) | |
| 2719 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q | |
| 2720 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q | |
| 2721 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) | |
| 2722 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) | |
| 2723 emit_opcode(cbuf,0x1C); | |
| 2724 emit_d8(cbuf,0x24); | |
| 2725 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 | |
| 2726 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 | |
| 2727 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) | |
| 2728 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) | |
| 2729 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); | |
| 2730 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask | |
| 2731 emit_rm(cbuf, 0x3, 0x0, ECX_enc); | |
| 2732 emit_d32(cbuf,0xFFFFF800); | |
| 2733 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias | |
| 2734 emit_rm(cbuf, 0x3, 0x0, EAX_enc); | |
| 2735 emit_d32(cbuf,1023); | |
| 2736 emit_opcode(cbuf,0x8B); // mov rbx,eax | |
| 2737 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); | |
| 2738 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position | |
| 2739 emit_rm(cbuf,0x3,0x4,EAX_enc); | |
| 2740 emit_d8(cbuf,20); | |
| 2741 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow | |
| 2742 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); | |
| 2743 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX | |
| 2744 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); | |
| 2745 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word | |
| 2746 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); | |
| 2747 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) | |
| 2748 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2749 emit_d32(cbuf,0); | |
| 2750 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q | |
| 2751 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); | |
| 2752 %} | |
| 2753 | |
| 2754 // enc_class Pop_Reg_Mod_D( regD dst, regD src) | |
| 2755 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() | |
| 2756 | |
| 2757 enc_class Push_Result_Mod_D( regD src) %{ | |
| 2758 if ($src$$reg != FPR1L_enc) { | |
| 2759 // fincstp | |
| 2760 emit_opcode (cbuf, 0xD9); | |
| 2761 emit_opcode (cbuf, 0xF7); | |
| 2762 // FXCH FPR1 with src | |
| 2763 emit_opcode(cbuf, 0xD9); | |
| 2764 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2765 // fdecstp | |
| 2766 emit_opcode (cbuf, 0xD9); | |
| 2767 emit_opcode (cbuf, 0xF6); | |
| 2768 } | |
| 2769 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2770 // // FSTP FPR$dst$$reg | |
| 2771 // emit_opcode( cbuf, 0xDD ); | |
| 2772 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2773 %} | |
| 2774 | |
| 2775 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2776 // fnstsw ax | |
| 2777 emit_opcode( cbuf, 0xDF ); | |
| 2778 emit_opcode( cbuf, 0xE0 ); | |
| 2779 // sahf | |
| 2780 emit_opcode( cbuf, 0x9E ); | |
| 2781 // jnp ::skip | |
| 2782 emit_opcode( cbuf, 0x7B ); | |
| 2783 emit_opcode( cbuf, 0x05 ); | |
| 2784 %} | |
| 2785 | |
| 2786 enc_class emitModD() %{ | |
| 2787 // fprem must be iterative | |
| 2788 // :: loop | |
| 2789 // fprem | |
| 2790 emit_opcode( cbuf, 0xD9 ); | |
| 2791 emit_opcode( cbuf, 0xF8 ); | |
| 2792 // wait | |
| 2793 emit_opcode( cbuf, 0x9b ); | |
| 2794 // fnstsw ax | |
| 2795 emit_opcode( cbuf, 0xDF ); | |
| 2796 emit_opcode( cbuf, 0xE0 ); | |
| 2797 // sahf | |
| 2798 emit_opcode( cbuf, 0x9E ); | |
| 2799 // jp ::loop | |
| 2800 emit_opcode( cbuf, 0x0F ); | |
| 2801 emit_opcode( cbuf, 0x8A ); | |
| 2802 emit_opcode( cbuf, 0xF4 ); | |
| 2803 emit_opcode( cbuf, 0xFF ); | |
| 2804 emit_opcode( cbuf, 0xFF ); | |
| 2805 emit_opcode( cbuf, 0xFF ); | |
| 2806 %} | |
| 2807 | |
| 2808 enc_class fpu_flags() %{ | |
| 2809 // fnstsw_ax | |
| 2810 emit_opcode( cbuf, 0xDF); | |
| 2811 emit_opcode( cbuf, 0xE0); | |
| 2812 // test ax,0x0400 | |
| 2813 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2814 emit_opcode( cbuf, 0xA9 ); | |
| 2815 emit_d16 ( cbuf, 0x0400 ); | |
| 2816 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2817 // // test rax,0x0400 | |
| 2818 // emit_opcode( cbuf, 0xA9 ); | |
| 2819 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2820 // | |
| 2821 // jz exit (no unordered comparison) | |
| 2822 emit_opcode( cbuf, 0x74 ); | |
| 2823 emit_d8 ( cbuf, 0x02 ); | |
| 2824 // mov ah,1 - treat as LT case (set carry flag) | |
| 2825 emit_opcode( cbuf, 0xB4 ); | |
| 2826 emit_d8 ( cbuf, 0x01 ); | |
| 2827 // sahf | |
| 2828 emit_opcode( cbuf, 0x9E); | |
| 2829 %} | |
| 2830 | |
| 2831 enc_class cmpF_P6_fixup() %{ | |
| 2832 // Fixup the integer flags in case comparison involved a NaN | |
| 2833 // | |
| 2834 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2835 emit_opcode( cbuf, 0x7B ); | |
| 2836 emit_d8 ( cbuf, 0x03 ); | |
| 2837 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2838 emit_opcode( cbuf, 0xB4 ); | |
| 2839 emit_d8 ( cbuf, 0x01 ); | |
| 2840 // SAHF | |
| 2841 emit_opcode( cbuf, 0x9E); | |
| 2842 // NOP // target for branch to avoid branch to branch | |
| 2843 emit_opcode( cbuf, 0x90); | |
| 2844 %} | |
| 2845 | |
| 2846 // fnstsw_ax(); | |
| 2847 // sahf(); | |
| 2848 // movl(dst, nan_result); | |
| 2849 // jcc(Assembler::parity, exit); | |
| 2850 // movl(dst, less_result); | |
| 2851 // jcc(Assembler::below, exit); | |
| 2852 // movl(dst, equal_result); | |
| 2853 // jcc(Assembler::equal, exit); | |
| 2854 // movl(dst, greater_result); | |
| 2855 | |
| 2856 // less_result = 1; | |
| 2857 // greater_result = -1; | |
| 2858 // equal_result = 0; | |
| 2859 // nan_result = -1; | |
| 2860 | |
| 2861 enc_class CmpF_Result(eRegI dst) %{ | |
| 2862 // fnstsw_ax(); | |
| 2863 emit_opcode( cbuf, 0xDF); | |
| 2864 emit_opcode( cbuf, 0xE0); | |
| 2865 // sahf | |
| 2866 emit_opcode( cbuf, 0x9E); | |
| 2867 // movl(dst, nan_result); | |
| 2868 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2869 emit_d32( cbuf, -1 ); | |
| 2870 // jcc(Assembler::parity, exit); | |
| 2871 emit_opcode( cbuf, 0x7A ); | |
| 2872 emit_d8 ( cbuf, 0x13 ); | |
| 2873 // movl(dst, less_result); | |
| 2874 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2875 emit_d32( cbuf, -1 ); | |
| 2876 // jcc(Assembler::below, exit); | |
| 2877 emit_opcode( cbuf, 0x72 ); | |
| 2878 emit_d8 ( cbuf, 0x0C ); | |
| 2879 // movl(dst, equal_result); | |
| 2880 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2881 emit_d32( cbuf, 0 ); | |
| 2882 // jcc(Assembler::equal, exit); | |
| 2883 emit_opcode( cbuf, 0x74 ); | |
| 2884 emit_d8 ( cbuf, 0x05 ); | |
| 2885 // movl(dst, greater_result); | |
| 2886 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2887 emit_d32( cbuf, 1 ); | |
| 2888 %} | |
| 2889 | |
| 2890 | |
| 2891 // XMM version of CmpF_Result. Because the XMM compare | |
| 2892 // instructions set the EFLAGS directly. It becomes simpler than | |
| 2893 // the float version above. | |
| 2894 enc_class CmpX_Result(eRegI dst) %{ | |
| 2895 MacroAssembler _masm(&cbuf); | |
| 2896 Label nan, inc, done; | |
| 2897 | |
| 2898 __ jccb(Assembler::parity, nan); | |
| 2899 __ jccb(Assembler::equal, done); | |
| 2900 __ jccb(Assembler::above, inc); | |
| 2901 __ bind(nan); | |
| 304 | 2902 __ decrement(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2903 __ jmpb(done); |
| 2904 __ bind(inc); | |
| 304 | 2905 __ increment(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2906 __ bind(done); |
| 2907 %} | |
| 2908 | |
| 2909 // Compare the longs and set flags | |
| 2910 // BROKEN! Do Not use as-is | |
| 2911 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2912 // CMP $src1.hi,$src2.hi | |
| 2913 emit_opcode( cbuf, 0x3B ); | |
| 2914 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2915 // JNE,s done | |
| 2916 emit_opcode(cbuf,0x75); | |
| 2917 emit_d8(cbuf, 2 ); | |
| 2918 // CMP $src1.lo,$src2.lo | |
| 2919 emit_opcode( cbuf, 0x3B ); | |
| 2920 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2921 // done: | |
| 2922 %} | |
| 2923 | |
| 2924 enc_class convert_int_long( regL dst, eRegI src ) %{ | |
| 2925 // mov $dst.lo,$src | |
| 2926 int dst_encoding = $dst$$reg; | |
| 2927 int src_encoding = $src$$reg; | |
| 2928 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2929 // mov $dst.hi,$src | |
| 2930 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2931 // sar $dst.hi,31 | |
| 2932 emit_opcode( cbuf, 0xC1 ); | |
| 2933 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2934 emit_d8(cbuf, 0x1F ); | |
| 2935 %} | |
| 2936 | |
| 2937 enc_class convert_long_double( eRegL src ) %{ | |
| 2938 // push $src.hi | |
| 2939 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2940 // push $src.lo | |
| 2941 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2942 // fild 64-bits at [SP] | |
| 2943 emit_opcode(cbuf,0xdf); | |
| 2944 emit_d8(cbuf, 0x6C); | |
| 2945 emit_d8(cbuf, 0x24); | |
| 2946 emit_d8(cbuf, 0x00); | |
| 2947 // pop stack | |
| 2948 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2949 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2950 emit_d8(cbuf, 0x8); | |
| 2951 %} | |
| 2952 | |
| 2953 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2954 // IMUL EDX:EAX,$src1 | |
| 2955 emit_opcode( cbuf, 0xF7 ); | |
| 2956 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2957 // SAR EDX,$cnt-32 | |
| 2958 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2959 if (shift_count > 0) { | |
| 2960 emit_opcode(cbuf, 0xC1); | |
| 2961 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2962 emit_d8(cbuf, shift_count); | |
| 2963 } | |
| 2964 %} | |
| 2965 | |
| 2966 // this version doesn't have add sp, 8 | |
| 2967 enc_class convert_long_double2( eRegL src ) %{ | |
| 2968 // push $src.hi | |
| 2969 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2970 // push $src.lo | |
| 2971 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2972 // fild 64-bits at [SP] | |
| 2973 emit_opcode(cbuf,0xdf); | |
| 2974 emit_d8(cbuf, 0x6C); | |
| 2975 emit_d8(cbuf, 0x24); | |
| 2976 emit_d8(cbuf, 0x00); | |
| 2977 %} | |
| 2978 | |
| 2979 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2980 // Basic idea: long = (long)int * (long)int | |
| 2981 // IMUL EDX:EAX, src | |
| 2982 emit_opcode( cbuf, 0xF7 ); | |
| 2983 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2984 %} | |
| 2985 | |
| 2986 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2987 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2988 // MUL EDX:EAX, src | |
| 2989 emit_opcode( cbuf, 0xF7 ); | |
| 2990 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2991 %} | |
| 2992 | |
| 2993 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ | |
| 2994 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 2995 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2996 // MOV $tmp,$src.lo | |
| 2997 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2998 // IMUL $tmp,EDX | |
| 2999 emit_opcode( cbuf, 0x0F ); | |
| 3000 emit_opcode( cbuf, 0xAF ); | |
| 3001 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3002 // MOV EDX,$src.hi | |
| 3003 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 3004 // IMUL EDX,EAX | |
| 3005 emit_opcode( cbuf, 0x0F ); | |
| 3006 emit_opcode( cbuf, 0xAF ); | |
| 3007 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 3008 // ADD $tmp,EDX | |
| 3009 emit_opcode( cbuf, 0x03 ); | |
| 3010 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3011 // MUL EDX:EAX,$src.lo | |
| 3012 emit_opcode( cbuf, 0xF7 ); | |
| 3013 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 3014 // ADD EDX,ESI | |
| 3015 emit_opcode( cbuf, 0x03 ); | |
| 3016 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 3017 %} | |
| 3018 | |
| 3019 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ | |
| 3020 // Basic idea: lo(result) = lo(src * y_lo) | |
| 3021 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 3022 // IMUL $tmp,EDX,$src | |
| 3023 emit_opcode( cbuf, 0x6B ); | |
| 3024 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3025 emit_d8( cbuf, (int)$src$$constant ); | |
| 3026 // MOV EDX,$src | |
| 3027 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 3028 emit_d32( cbuf, (int)$src$$constant ); | |
| 3029 // MUL EDX:EAX,EDX | |
| 3030 emit_opcode( cbuf, 0xF7 ); | |
| 3031 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 3032 // ADD EDX,ESI | |
| 3033 emit_opcode( cbuf, 0x03 ); | |
| 3034 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 3035 %} | |
| 3036 | |
| 3037 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 3038 // PUSH src1.hi | |
| 3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3040 // PUSH src1.lo | |
| 3041 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3042 // PUSH src2.hi | |
| 3043 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3044 // PUSH src2.lo | |
| 3045 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3046 // CALL directly to the runtime | |
| 3047 cbuf.set_inst_mark(); | |
| 3048 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3049 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3050 // Restore stack | |
| 3051 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3052 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3053 emit_d8(cbuf, 4*4); | |
| 3054 %} | |
| 3055 | |
| 3056 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 3057 // PUSH src1.hi | |
| 3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3059 // PUSH src1.lo | |
| 3060 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3061 // PUSH src2.hi | |
| 3062 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3063 // PUSH src2.lo | |
| 3064 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3065 // CALL directly to the runtime | |
| 3066 cbuf.set_inst_mark(); | |
| 3067 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3068 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3069 // Restore stack | |
| 3070 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3071 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3072 emit_d8(cbuf, 4*4); | |
| 3073 %} | |
| 3074 | |
| 3075 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ | |
| 3076 // MOV $tmp,$src.lo | |
| 3077 emit_opcode(cbuf, 0x8B); | |
| 3078 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 3079 // OR $tmp,$src.hi | |
| 3080 emit_opcode(cbuf, 0x0B); | |
| 3081 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 3082 %} | |
| 3083 | |
| 3084 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 3085 // CMP $src1.lo,$src2.lo | |
| 3086 emit_opcode( cbuf, 0x3B ); | |
| 3087 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3088 // JNE,s skip | |
| 3089 emit_cc(cbuf, 0x70, 0x5); | |
| 3090 emit_d8(cbuf,2); | |
| 3091 // CMP $src1.hi,$src2.hi | |
| 3092 emit_opcode( cbuf, 0x3B ); | |
| 3093 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 3094 %} | |
| 3095 | |
| 3096 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 3097 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits | |
| 3098 emit_opcode( cbuf, 0x3B ); | |
| 3099 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3100 // MOV $tmp,$src1.hi | |
| 3101 emit_opcode( cbuf, 0x8B ); | |
| 3102 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 3103 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 3104 emit_opcode( cbuf, 0x1B ); | |
| 3105 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 3106 %} | |
| 3107 | |
| 3108 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ | |
| 3109 // XOR $tmp,$tmp | |
| 3110 emit_opcode(cbuf,0x33); // XOR | |
| 3111 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 3112 // CMP $tmp,$src.lo | |
| 3113 emit_opcode( cbuf, 0x3B ); | |
| 3114 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 3115 // SBB $tmp,$src.hi | |
| 3116 emit_opcode( cbuf, 0x1B ); | |
| 3117 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 3118 %} | |
| 3119 | |
| 3120 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 3121 enc_class neg_long( eRegL dst ) %{ | |
| 3122 emit_opcode(cbuf,0xF7); // NEG hi | |
| 3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3124 emit_opcode(cbuf,0xF7); // NEG lo | |
| 3125 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 3126 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 3127 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3128 emit_d8 (cbuf,0 ); | |
| 3129 %} | |
| 3130 | |
| 3131 enc_class movq_ld(regXD dst, memory mem) %{ | |
| 3132 MacroAssembler _masm(&cbuf); | |
| 624 | 3133 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3134 %} |
| 3135 | |
| 3136 enc_class movq_st(memory mem, regXD src) %{ | |
| 3137 MacroAssembler _masm(&cbuf); | |
| 624 | 3138 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3139 %} |
| 3140 | |
| 3141 enc_class pshufd_8x8(regX dst, regX src) %{ | |
| 3142 MacroAssembler _masm(&cbuf); | |
| 3143 | |
| 3144 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3145 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3146 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3147 %} | |
| 3148 | |
| 3149 enc_class pshufd_4x16(regX dst, regX src) %{ | |
| 3150 MacroAssembler _masm(&cbuf); | |
| 3151 | |
| 3152 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3153 %} | |
| 3154 | |
| 3155 enc_class pshufd(regXD dst, regXD src, int mode) %{ | |
| 3156 MacroAssembler _masm(&cbuf); | |
| 3157 | |
| 3158 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3159 %} | |
| 3160 | |
| 3161 enc_class pxor(regXD dst, regXD src) %{ | |
| 3162 MacroAssembler _masm(&cbuf); | |
| 3163 | |
| 3164 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3165 %} | |
| 3166 | |
| 3167 enc_class mov_i2x(regXD dst, eRegI src) %{ | |
| 3168 MacroAssembler _masm(&cbuf); | |
| 3169 | |
| 304 | 3170 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); |
| 0 | 3171 %} |
| 3172 | |
| 3173 | |
| 3174 // Because the transitions from emitted code to the runtime | |
| 3175 // monitorenter/exit helper stubs are so slow it's critical that | |
| 3176 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 3177 // | |
| 3178 // See also: cmpFastLock and cmpFastUnlock. | |
| 3179 // | |
| 3180 // What follows is a specialized inline transliteration of the code | |
| 3181 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 3182 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 3183 // at startup-time. These methods would accept arguments as | |
| 3184 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 3185 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 3186 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 3187 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 3188 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 3189 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 3190 // Since the helper routines would be called from multiple synchronization | |
| 3191 // sites. | |
| 3192 // | |
| 3193 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 3194 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 3195 // to those specialized methods. That'd give us a mostly platform-independent | |
| 3196 // implementation that the JITs could optimize and inline at their pleasure. | |
| 3197 // Done correctly, the only time we'd need to cross to native could would be | |
| 3198 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 3199 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 3200 // (b) explicit barriers or fence operations. | |
| 3201 // | |
| 3202 // TODO: | |
| 3203 // | |
| 3204 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 3205 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 3206 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 3207 // the lock operators would typically be faster than reifying Self. | |
| 3208 // | |
| 3209 // * Ideally I'd define the primitives as: | |
| 3210 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 3211 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 3212 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 3213 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 3214 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 3215 // sub-optimal code near the synchronization site. | |
| 3216 // | |
| 3217 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 3218 // Alternately, use a better sp-proximity test. | |
| 3219 // | |
| 3220 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 3221 // Either one is sufficient to uniquely identify a thread. | |
| 3222 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 3223 // | |
| 3224 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 3225 // object is locked by the calling thread but the waitlist is empty. | |
| 3226 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 3227 // | |
| 3228 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 3229 // But beware of excessive branch density on AMD Opterons. | |
| 3230 // | |
| 3231 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 3232 // or failure of the fast-path. If the fast-path fails then we pass | |
| 3233 // control to the slow-path, typically in C. In Fast_Lock and | |
| 3234 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 3235 // will emit a conditional branch immediately after the node. | |
| 3236 // So we have branches to branches and lots of ICC.ZF games. | |
| 3237 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3238 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3239 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3240 // In the case of failure, the node will branch directly to the | |
| 3241 // FailureLabel | |
| 3242 | |
| 3243 | |
| 3244 // obj: object to lock | |
| 3245 // box: on-stack box address (displaced header location) - KILLED | |
| 3246 // rax,: tmp -- KILLED | |
| 3247 // scr: tmp -- KILLED | |
| 3248 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3249 | |
| 3250 Register objReg = as_Register($obj$$reg); | |
| 3251 Register boxReg = as_Register($box$$reg); | |
| 3252 Register tmpReg = as_Register($tmp$$reg); | |
| 3253 Register scrReg = as_Register($scr$$reg); | |
| 3254 | |
| 3255 // Ensure the register assignents are disjoint | |
| 3256 guarantee (objReg != boxReg, "") ; | |
| 3257 guarantee (objReg != tmpReg, "") ; | |
| 3258 guarantee (objReg != scrReg, "") ; | |
| 3259 guarantee (boxReg != tmpReg, "") ; | |
| 3260 guarantee (boxReg != scrReg, "") ; | |
| 3261 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3262 | |
| 3263 MacroAssembler masm(&cbuf); | |
| 3264 | |
| 3265 if (_counters != NULL) { | |
| 3266 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3267 } | |
| 3268 if (EmitSync & 1) { | |
| 3269 // set box->dhw = unused_mark (3) | |
| 304 | 3270 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3271 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3272 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3273 } else | |
| 3274 if (EmitSync & 2) { | |
| 3275 Label DONE_LABEL ; | |
| 0 | 3276 if (UseBiasedLocking) { |
| 3277 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3278 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3279 } | |
| 3280 | |
| 304 | 3281 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3282 masm.orptr (tmpReg, 0x1); | |
| 3283 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3284 if (os::is_MP()) { masm.lock(); } |
| 304 | 3285 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3286 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3287 // Recursive locking | |
| 304 | 3288 masm.subptr(tmpReg, rsp); |
| 3289 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3290 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3291 masm.bind(DONE_LABEL) ; | |
| 3292 } else { | |
| 3293 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3294 // ------------------------------------------------ |
| 3295 // * Inflated | |
| 3296 // -- unlocked | |
| 3297 // -- Locked | |
| 3298 // = by self | |
| 3299 // = by other | |
| 3300 // * biased | |
| 3301 // -- by Self | |
| 3302 // -- by other | |
| 3303 // * neutral | |
| 3304 // * stack-locked | |
| 3305 // -- by self | |
| 3306 // = sp-proximity test hits | |
| 3307 // = sp-proximity test generates false-negative | |
| 3308 // -- by other | |
| 3309 // | |
| 3310 | |
| 3311 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3312 | |
| 3313 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3314 // order to reduce the number of conditional branches in the most common cases. | |
| 3315 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3316 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3317 // If this invariant is not held we risk exclusion (safety) failure. | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3318 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3319 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3320 } | |
| 3321 | |
| 304 | 3322 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3323 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3324 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3325 | |
| 3326 // Attempt stack-locking ... | |
| 304 | 3327 masm.orptr (tmpReg, 0x1); |
| 3328 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3329 if (os::is_MP()) { masm.lock(); } |
| 304 | 3330 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3331 if (_counters != NULL) { |
| 3332 masm.cond_inc32(Assembler::equal, | |
| 3333 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3334 } | |
| 3335 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3336 | |
| 3337 // Recursive locking | |
| 304 | 3338 masm.subptr(tmpReg, rsp); |
| 3339 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3340 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3341 if (_counters != NULL) { |
| 3342 masm.cond_inc32(Assembler::equal, | |
| 3343 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3344 } | |
| 3345 masm.jmp (DONE_LABEL) ; | |
| 3346 | |
| 3347 masm.bind (IsInflated) ; | |
| 3348 | |
| 3349 // The object is inflated. | |
| 3350 // | |
| 3351 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3352 // Use markOopDesc::monitor_value instead of "2". | |
| 3353 // use markOop::unused_mark() instead of "3". | |
| 3354 // The tmpReg value is an objectMonitor reference ORed with | |
| 3355 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3356 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3357 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3358 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3359 // | |
| 3360 // I use the latter as it avoids AGI stalls. | |
| 3361 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3362 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3363 // | |
| 3364 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3365 | |
| 3366 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3367 // We'd like to write: | |
| 3368 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3369 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3370 // additional latency as we have another ST in the store buffer that must drain. | |
| 3371 | |
| 304 | 3372 if (EmitSync & 8192) { |
| 3373 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3374 masm.get_thread (scrReg) ; | |
| 3375 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3376 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3377 if (os::is_MP()) { masm.lock(); } |
| 3378 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3379 } else | |
| 0 | 3380 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3381 masm.movptr(scrReg, boxReg) ; |
| 3382 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3383 |
| 3384 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3385 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3386 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3387 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3388 } |
| 3389 | |
| 3390 if ((EmitSync & 64) == 0) { | |
| 3391 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3392 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3393 } else { |
| 0 | 3394 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3395 // Test-And-CAS instead of CAS | |
| 304 | 3396 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3397 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3398 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3399 } |
| 3400 | |
| 3401 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3402 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3403 // to CAS the register containing Self into m->Owner. | |
| 3404 // But we don't have enough registers, so instead we can either try to CAS | |
| 3405 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3406 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3407 // (rsp or the address of the box) into m->owner is harmless. | |
| 3408 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3409 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3410 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3411 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3412 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3413 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3414 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3415 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3416 | |
| 3417 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3418 // We use the latter tactic. | |
| 0 | 3419 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3420 // If the CAS was successful ... | |
| 3421 // Self has acquired the lock | |
| 3422 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3423 // Intentional fall-through into DONE_LABEL ... | |
| 3424 } else { | |
| 304 | 3425 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3426 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3427 |
| 3428 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3429 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3430 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3431 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3432 } |
| 3433 | |
| 3434 if ((EmitSync & 64) == 0) { | |
| 3435 // Optimistic form | |
| 304 | 3436 masm.xorptr (tmpReg, tmpReg) ; |
| 3437 } else { | |
| 0 | 3438 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3439 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3440 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3441 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3442 } |
| 3443 | |
| 3444 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3445 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3446 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3447 masm.get_thread (scrReg) ; | |
| 3448 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3449 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3450 |
| 3451 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3452 // We use the latter tactic. | |
| 3453 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3454 // If the CAS was successful ... | |
| 3455 // Self has acquired the lock | |
| 3456 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3457 // Intentional fall-through into DONE_LABEL ... | |
| 3458 } | |
| 3459 | |
| 3460 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3461 // start of cache line by padding with NOPs. | |
| 3462 // See the AMD and Intel software optimization manuals for the | |
| 3463 // most efficient "long" NOP encodings. | |
| 3464 // Unfortunately none of our alignment mechanisms suffice. | |
| 3465 masm.bind(DONE_LABEL); | |
| 3466 | |
| 3467 // Avoid branch-to-branch on AMD processors | |
| 3468 // This appears to be superstition. | |
| 3469 if (EmitSync & 32) masm.nop() ; | |
| 3470 | |
| 3471 | |
| 3472 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3473 // Fast_Unlock uses the same protocol. | |
| 3474 // ZFlag == 1 -> Success | |
| 3475 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3476 } | |
| 3477 %} | |
| 3478 | |
| 3479 // obj: object to unlock | |
| 3480 // box: box address (displaced header location), killed. Must be EAX. | |
| 3481 // rbx,: killed tmp; cannot be obj nor box. | |
| 3482 // | |
| 3483 // Some commentary on balanced locking: | |
| 3484 // | |
| 3485 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3486 // Methods that don't have provably balanced locking are forced to run in the | |
| 3487 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3488 // The interpreter provides two properties: | |
| 3489 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3490 // objects acquired the current activation (frame). Recall that the | |
| 3491 // interpreter maintains an on-stack list of locks currently held by | |
| 3492 // a frame. | |
| 3493 // I2: If a method attempts to unlock an object that is not held by the | |
| 3494 // the frame the interpreter throws IMSX. | |
| 3495 // | |
| 3496 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3497 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3498 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3499 // is still locked by A(). | |
| 3500 // | |
| 3501 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3502 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3503 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3504 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3505 | |
| 3506 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3507 | |
| 3508 Register objReg = as_Register($obj$$reg); | |
| 3509 Register boxReg = as_Register($box$$reg); | |
| 3510 Register tmpReg = as_Register($tmp$$reg); | |
| 3511 | |
| 3512 guarantee (objReg != boxReg, "") ; | |
| 3513 guarantee (objReg != tmpReg, "") ; | |
| 3514 guarantee (boxReg != tmpReg, "") ; | |
| 3515 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3516 MacroAssembler masm(&cbuf); | |
| 3517 | |
| 3518 if (EmitSync & 4) { | |
| 3519 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3520 masm.cmpptr (rsp, 0) ; |
| 3521 } else | |
| 0 | 3522 if (EmitSync & 8) { |
| 3523 Label DONE_LABEL ; | |
| 3524 if (UseBiasedLocking) { | |
| 3525 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3526 } | |
| 3527 // classic stack-locking code ... | |
| 304 | 3528 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3529 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3530 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3531 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3532 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3533 masm.bind(DONE_LABEL); |
| 3534 } else { | |
| 3535 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3536 | |
| 3537 // Critically, the biased locking test must have precedence over | |
| 3538 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3539 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3540 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3541 } | |
| 304 | 3542 |
| 3543 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3544 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3545 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3546 | |
| 304 | 3547 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3548 masm.jccb (Assembler::zero, Stacked) ; |
| 3549 | |
| 3550 masm.bind (Inflated) ; | |
| 3551 // It's inflated. | |
| 3552 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3553 // as java routines or native JNI code called by this thread might | |
| 3554 // have released the lock. | |
| 3555 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3556 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3557 // | |
| 3558 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3559 // such as recursive enter and exit -- but we have to be wary of | |
| 3560 // I$ bloat, T$ effects and BP$ effects. | |
| 3561 // | |
| 3562 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3563 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3564 // we detect and recover from the race that the 1-0 exit admits. | |
| 3565 // | |
| 3566 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3567 // before it STs null into _owner, releasing the lock. Updates | |
| 3568 // to data protected by the critical section must be visible before | |
| 3569 // we drop the lock (and thus before any other thread could acquire | |
| 3570 // the lock and observe the fields protected by the lock). | |
| 3571 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3572 // each other and there's no need for an explicit barrier (fence). | |
| 3573 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3574 | |
| 3575 masm.get_thread (boxReg) ; | |
| 3576 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 304 | 3577 // prefetchw [ebx + Offset(_owner)-2] |
| 3578 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3579 } |
| 3580 | |
| 3581 // Note that we could employ various encoding schemes to reduce | |
| 3582 // the number of loads below (currently 4) to just 2 or 3. | |
| 3583 // Refer to the comments in synchronizer.cpp. | |
| 3584 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3585 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3586 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3587 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3589 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3590 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3591 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3592 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3593 masm.jmpb (DONE_LABEL) ; |
| 3594 } else { | |
| 3595 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3596 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3597 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3598 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3599 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3600 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3601 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3602 masm.jmpb (DONE_LABEL) ; |
| 0 | 3603 } |
| 3604 | |
| 3605 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3606 // contended applications and contended synchronization microbenchmarks. | |
| 3607 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3608 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3609 // with an equal number of never-executed NOPs results in the same regression. | |
| 3610 // We leave it off by default. | |
| 3611 | |
| 3612 if ((EmitSync & 65536) != 0) { | |
| 3613 Label LSuccess, LGoSlowPath ; | |
| 3614 | |
| 3615 masm.bind (CheckSucc) ; | |
| 3616 | |
| 3617 // Optional pre-test ... it's safe to elide this | |
| 304 | 3618 if ((EmitSync & 16) == 0) { |
| 3619 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3620 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3621 } |
| 3622 | |
| 3623 // We have a classic Dekker-style idiom: | |
| 3624 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3625 // There are a number of ways to implement the barrier: | |
| 3626 // (1) lock:andl &m->_owner, 0 | |
| 3627 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3628 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3629 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3630 // (2) If supported, an explicit MFENCE is appealing. | |
| 3631 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3632 // particularly if the write-buffer is full as might be the case if | |
| 3633 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3634 // In more modern implementations MFENCE appears faster, however. | |
| 3635 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3636 // The $lines underlying the top-of-stack should be in M-state. | |
| 3637 // The locked add instruction is serializing, of course. | |
| 3638 // (4) Use xchg, which is serializing | |
| 3639 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3640 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3641 // The integer condition codes will tell us if succ was 0. | |
| 3642 // Since _succ and _owner should reside in the same $line and | |
| 3643 // we just stored into _owner, it's likely that the $line | |
| 3644 // remains in M-state for the lock:orl. | |
| 3645 // | |
| 3646 // We currently use (3), although it's likely that switching to (2) | |
| 3647 // is correct for the future. | |
| 304 | 3648 |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
3649 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3650 if (os::is_MP()) { |
| 3651 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3652 masm.mfence(); | |
| 3653 } else { | |
| 3654 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3655 } |
| 3656 } | |
| 3657 // Ratify _succ remains non-null | |
| 304 | 3658 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3659 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3660 | |
| 3661 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3662 if (os::is_MP()) { masm.lock(); } |
| 304 | 3663 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3664 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3665 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3666 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3667 // non-null to non=null | |
| 3668 masm.get_thread (boxReg) ; | |
| 304 | 3669 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3670 // Intentional fall-through into LGoSlowPath ... |
| 3671 | |
| 304 | 3672 masm.bind (LGoSlowPath) ; |
| 3673 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3674 masm.jmpb (DONE_LABEL) ; | |
| 3675 | |
| 3676 masm.bind (LSuccess) ; | |
| 3677 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3678 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3679 } |
| 3680 | |
| 3681 masm.bind (Stacked) ; | |
| 3682 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3683 // It must be stack-locked. | |
| 3684 // Try to reset the header to displaced header. | |
| 3685 // The "box" value on the stack is stable, so we can reload | |
| 3686 // and be assured we observe the same value as above. | |
| 304 | 3687 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3688 if (os::is_MP()) { masm.lock(); } |
| 304 | 3689 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3690 // Intention fall-thru into DONE_LABEL |
| 3691 | |
| 3692 | |
| 3693 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3694 // start of cache line by padding with NOPs. | |
| 3695 // See the AMD and Intel software optimization manuals for the | |
| 3696 // most efficient "long" NOP encodings. | |
| 3697 // Unfortunately none of our alignment mechanisms suffice. | |
| 3698 if ((EmitSync & 65536) == 0) { | |
| 3699 masm.bind (CheckSucc) ; | |
| 3700 } | |
| 3701 masm.bind(DONE_LABEL); | |
| 3702 | |
| 3703 // Avoid branch to branch on AMD processors | |
| 3704 if (EmitSync & 32768) { masm.nop() ; } | |
| 3705 } | |
| 3706 %} | |
| 3707 | |
| 3708 enc_class enc_String_Compare() %{ | |
| 3709 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL, | |
| 3710 POP_LABEL, DONE_LABEL, CONT_LABEL, | |
| 3711 WHILE_HEAD_LABEL; | |
| 3712 MacroAssembler masm(&cbuf); | |
| 3713 | |
| 3714 // Get the first character position in both strings | |
| 3715 // [8] char array, [12] offset, [16] count | |
| 3716 int value_offset = java_lang_String::value_offset_in_bytes(); | |
| 3717 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
| 3718 int count_offset = java_lang_String::count_offset_in_bytes(); | |
| 3719 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3720 | |
| 304 | 3721 masm.movptr(rax, Address(rsi, value_offset)); |
| 0 | 3722 masm.movl(rcx, Address(rsi, offset_offset)); |
| 304 | 3723 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset)); |
| 3724 masm.movptr(rbx, Address(rdi, value_offset)); | |
| 0 | 3725 masm.movl(rcx, Address(rdi, offset_offset)); |
| 304 | 3726 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset)); |
| 0 | 3727 |
| 3728 // Compute the minimum of the string lengths(rsi) and the | |
| 3729 // difference of the string lengths (stack) | |
| 3730 | |
| 3731 | |
| 3732 if (VM_Version::supports_cmov()) { | |
| 3733 masm.movl(rdi, Address(rdi, count_offset)); | |
| 3734 masm.movl(rsi, Address(rsi, count_offset)); | |
| 3735 masm.movl(rcx, rdi); | |
| 3736 masm.subl(rdi, rsi); | |
| 304 | 3737 masm.push(rdi); |
| 0 | 3738 masm.cmovl(Assembler::lessEqual, rsi, rcx); |
| 3739 } else { | |
| 3740 masm.movl(rdi, Address(rdi, count_offset)); | |
| 3741 masm.movl(rcx, Address(rsi, count_offset)); | |
| 3742 masm.movl(rsi, rdi); | |
| 3743 masm.subl(rdi, rcx); | |
| 304 | 3744 masm.push(rdi); |
| 0 | 3745 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL); |
| 3746 masm.movl(rsi, rcx); | |
| 3747 // rsi holds min, rcx is unused | |
| 3748 } | |
| 3749 | |
| 3750 // Is the minimum length zero? | |
| 3751 masm.bind(ECX_GOOD_LABEL); | |
| 3752 masm.testl(rsi, rsi); | |
| 3753 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 3754 | |
| 3755 // Load first characters | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3756 masm.load_unsigned_short(rcx, Address(rbx, 0)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3757 masm.load_unsigned_short(rdi, Address(rax, 0)); |
| 0 | 3758 |
| 3759 // Compare first characters | |
| 3760 masm.subl(rcx, rdi); | |
| 3761 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 304 | 3762 masm.decrementl(rsi); |
| 0 | 3763 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
| 3764 | |
| 3765 { | |
| 3766 // Check after comparing first character to see if strings are equivalent | |
| 3767 Label LSkip2; | |
| 3768 // Check if the strings start at same location | |
| 304 | 3769 masm.cmpptr(rbx,rax); |
| 0 | 3770 masm.jcc(Assembler::notEqual, LSkip2); |
| 3771 | |
| 3772 // Check if the length difference is zero (from stack) | |
| 3773 masm.cmpl(Address(rsp, 0), 0x0); | |
| 3774 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); | |
| 3775 | |
| 3776 // Strings might not be equivalent | |
| 3777 masm.bind(LSkip2); | |
| 3778 } | |
| 3779 | |
| 3780 // Shift rax, and rbx, to the end of the arrays, negate min | |
| 304 | 3781 masm.lea(rax, Address(rax, rsi, Address::times_2, 2)); |
| 3782 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2)); | |
| 0 | 3783 masm.negl(rsi); |
| 3784 | |
| 3785 // Compare the rest of the characters | |
| 3786 masm.bind(WHILE_HEAD_LABEL); | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3787 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3788 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0)); |
| 0 | 3789 masm.subl(rcx, rdi); |
| 3790 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 304 | 3791 masm.incrementl(rsi); |
| 0 | 3792 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
| 3793 | |
| 3794 // Strings are equal up to min length. Return the length difference. | |
| 3795 masm.bind(LENGTH_DIFF_LABEL); | |
| 304 | 3796 masm.pop(rcx); |
| 0 | 3797 masm.jmp(DONE_LABEL); |
| 3798 | |
| 3799 // Discard the stored length difference | |
| 3800 masm.bind(POP_LABEL); | |
| 304 | 3801 masm.addptr(rsp, 4); |
| 3802 | |
| 0 | 3803 // That's it |
| 3804 masm.bind(DONE_LABEL); | |
| 3805 %} | |
| 3806 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3807 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{ |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3808 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP; |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3809 MacroAssembler masm(&cbuf); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3810 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3811 Register ary1Reg = as_Register($ary1$$reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3812 Register ary2Reg = as_Register($ary2$$reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3813 Register tmp1Reg = as_Register($tmp1$$reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3814 Register tmp2Reg = as_Register($tmp2$$reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3815 Register resultReg = as_Register($result$$reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3816 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3817 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3818 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3819 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3820 // Check the input args |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3821 masm.cmpl(ary1Reg, ary2Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3822 masm.jcc(Assembler::equal, TRUE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3823 masm.testl(ary1Reg, ary1Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3824 masm.jcc(Assembler::zero, FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3825 masm.testl(ary2Reg, ary2Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3826 masm.jcc(Assembler::zero, FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3827 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3828 // Check the lengths |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3829 masm.movl(tmp2Reg, Address(ary1Reg, length_offset)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3830 masm.movl(resultReg, Address(ary2Reg, length_offset)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3831 masm.cmpl(tmp2Reg, resultReg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3832 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3833 masm.testl(resultReg, resultReg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3834 masm.jcc(Assembler::zero, TRUE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3835 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3836 // Get the number of 4 byte vectors to compare |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3837 masm.shrl(resultReg, 1); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3838 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3839 // Check for odd-length arrays |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3840 masm.andl(tmp2Reg, 1); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3841 masm.testl(tmp2Reg, tmp2Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3842 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3843 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3844 // Compare 2-byte "tail" at end of arrays |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3845 masm.load_unsigned_short(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
605
diff
changeset
|
3846 masm.load_unsigned_short(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3847 masm.cmpl(tmp1Reg, tmp2Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3848 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3849 masm.testl(resultReg, resultReg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3850 masm.jcc(Assembler::zero, TRUE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3851 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3852 // Setup compare loop |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3853 masm.bind(COMPARE_LOOP_HDR); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3854 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3855 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3856 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3857 masm.negl(resultReg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3858 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3859 // 4-byte-wide compare loop |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3860 masm.bind(COMPARE_LOOP); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3861 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3862 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3863 masm.cmpl(ary1Reg, ary2Reg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3864 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3865 masm.increment(resultReg); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3866 masm.jcc(Assembler::notZero, COMPARE_LOOP); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3867 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3868 masm.bind(TRUE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3869 masm.movl(resultReg, 1); // return true |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3870 masm.jmp(DONE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3871 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3872 masm.bind(FALSE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3873 masm.xorl(resultReg, resultReg); // return false |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3874 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3875 // That's it |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3876 masm.bind(DONE_LABEL); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3877 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
3878 |
| 0 | 3879 enc_class enc_pop_rdx() %{ |
| 3880 emit_opcode(cbuf,0x5A); | |
| 3881 %} | |
| 3882 | |
| 3883 enc_class enc_rethrow() %{ | |
| 3884 cbuf.set_inst_mark(); | |
| 3885 emit_opcode(cbuf, 0xE9); // jmp entry | |
| 3886 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4, | |
| 3887 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3888 %} | |
| 3889 | |
| 3890 | |
| 3891 // Convert a double to an int. Java semantics require we do complex | |
| 3892 // manglelations in the corner cases. So we set the rounding mode to | |
| 3893 // 'zero', store the darned double down as an int, and reset the | |
| 3894 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3895 // patches up the correct value directly to the stack. | |
| 3896 enc_class D2I_encoding( regD src ) %{ | |
| 3897 // Flip to round-to-zero mode. We attempted to allow invalid-op | |
| 3898 // exceptions here, so that a NAN or other corner-case value will | |
| 3899 // thrown an exception (but normal values get converted at full speed). | |
| 3900 // However, I2C adapters and other float-stack manglers leave pending | |
| 3901 // invalid-op exceptions hanging. We would have to clear them before | |
| 3902 // enabling them and that is more expensive than just testing for the | |
| 3903 // invalid value Intel stores down in the corner cases. | |
| 3904 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3905 emit_opcode(cbuf,0x2D); | |
| 3906 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3907 // Allocate a word | |
| 3908 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3909 emit_opcode(cbuf,0xEC); | |
| 3910 emit_d8(cbuf,0x04); | |
| 3911 // Encoding assumes a double has been pushed into FPR0. | |
| 3912 // Store down the double as an int, popping the FPU stack | |
| 3913 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3914 emit_opcode(cbuf,0x1C); | |
| 3915 emit_d8(cbuf,0x24); | |
| 3916 // Restore the rounding mode; mask the exception | |
| 3917 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3918 emit_opcode(cbuf,0x2D); | |
| 3919 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3920 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3921 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3922 | |
| 3923 // Load the converted int; adjust CPU stack | |
| 3924 emit_opcode(cbuf,0x58); // POP EAX | |
| 3925 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3926 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3927 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3928 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3929 // Push src onto stack slow-path | |
| 3930 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3931 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3932 // CALL directly to the runtime | |
| 3933 cbuf.set_inst_mark(); | |
| 3934 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3935 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3936 // Carry on here... | |
| 3937 %} | |
| 3938 | |
| 3939 enc_class D2L_encoding( regD src ) %{ | |
| 3940 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3941 emit_opcode(cbuf,0x2D); | |
| 3942 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3943 // Allocate a word | |
| 3944 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3945 emit_opcode(cbuf,0xEC); | |
| 3946 emit_d8(cbuf,0x08); | |
| 3947 // Encoding assumes a double has been pushed into FPR0. | |
| 3948 // Store down the double as a long, popping the FPU stack | |
| 3949 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3950 emit_opcode(cbuf,0x3C); | |
| 3951 emit_d8(cbuf,0x24); | |
| 3952 // Restore the rounding mode; mask the exception | |
| 3953 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3954 emit_opcode(cbuf,0x2D); | |
| 3955 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3956 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3957 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3958 | |
| 3959 // Load the converted int; adjust CPU stack | |
| 3960 emit_opcode(cbuf,0x58); // POP EAX | |
| 3961 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3962 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3963 emit_d8 (cbuf,0xFA); // rdx | |
| 3964 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3965 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3966 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3967 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3968 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3969 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3970 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3971 // Push src onto stack slow-path | |
| 3972 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3973 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3974 // CALL directly to the runtime | |
| 3975 cbuf.set_inst_mark(); | |
| 3976 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3977 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3978 // Carry on here... | |
| 3979 %} | |
| 3980 | |
| 3981 enc_class X2L_encoding( regX src ) %{ | |
| 3982 // Allocate a word | |
| 3983 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3984 emit_opcode(cbuf,0xEC); | |
| 3985 emit_d8(cbuf,0x08); | |
| 3986 | |
| 3987 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3988 emit_opcode (cbuf, 0x0F ); | |
| 3989 emit_opcode (cbuf, 0x11 ); | |
| 3990 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3991 | |
| 3992 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3993 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3994 | |
| 3995 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3996 emit_opcode(cbuf,0x2D); | |
| 3997 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3998 | |
| 3999 // Encoding assumes a double has been pushed into FPR0. | |
| 4000 // Store down the double as a long, popping the FPU stack | |
| 4001 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 4002 emit_opcode(cbuf,0x3C); | |
| 4003 emit_d8(cbuf,0x24); | |
| 4004 | |
| 4005 // Restore the rounding mode; mask the exception | |
| 4006 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 4007 emit_opcode(cbuf,0x2D); | |
| 4008 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 4009 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 4010 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 4011 | |
| 4012 // Load the converted int; adjust CPU stack | |
| 4013 emit_opcode(cbuf,0x58); // POP EAX | |
| 4014 | |
| 4015 emit_opcode(cbuf,0x5A); // POP EDX | |
| 4016 | |
| 4017 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 4018 emit_d8 (cbuf,0xFA); // rdx | |
| 4019 emit_d32 (cbuf,0x80000000);// 0x80000000 | |
| 4020 | |
| 4021 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4022 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 4023 | |
| 4024 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 4025 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 4026 | |
| 4027 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4028 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4029 | |
| 4030 // Allocate a word | |
| 4031 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4032 emit_opcode(cbuf,0xEC); | |
| 4033 emit_d8(cbuf,0x04); | |
| 4034 | |
| 4035 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 4036 emit_opcode (cbuf, 0x0F ); | |
| 4037 emit_opcode (cbuf, 0x11 ); | |
| 4038 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4039 | |
| 4040 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 4041 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4042 | |
| 4043 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4044 emit_opcode(cbuf,0xC4); | |
| 4045 emit_d8(cbuf,0x04); | |
| 4046 | |
| 4047 // CALL directly to the runtime | |
| 4048 cbuf.set_inst_mark(); | |
| 4049 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 4050 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 4051 // Carry on here... | |
| 4052 %} | |
| 4053 | |
| 4054 enc_class XD2L_encoding( regXD src ) %{ | |
| 4055 // Allocate a word | |
| 4056 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 4057 emit_opcode(cbuf,0xEC); | |
| 4058 emit_d8(cbuf,0x08); | |
| 4059 | |
| 4060 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 4061 emit_opcode (cbuf, 0x0F ); | |
| 4062 emit_opcode (cbuf, 0x11 ); | |
| 4063 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4064 | |
| 4065 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 4066 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4067 | |
| 4068 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 4069 emit_opcode(cbuf,0x2D); | |
| 4070 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 4071 | |
| 4072 // Encoding assumes a double has been pushed into FPR0. | |
| 4073 // Store down the double as a long, popping the FPU stack | |
| 4074 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 4075 emit_opcode(cbuf,0x3C); | |
| 4076 emit_d8(cbuf,0x24); | |
| 4077 | |
| 4078 // Restore the rounding mode; mask the exception | |
| 4079 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 4080 emit_opcode(cbuf,0x2D); | |
| 4081 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 4082 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 4083 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 4084 | |
| 4085 // Load the converted int; adjust CPU stack | |
| 4086 emit_opcode(cbuf,0x58); // POP EAX | |
| 4087 | |
| 4088 emit_opcode(cbuf,0x5A); // POP EDX | |
| 4089 | |
| 4090 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 4091 emit_d8 (cbuf,0xFA); // rdx | |
| 4092 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 4093 | |
| 4094 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4095 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 4096 | |
| 4097 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 4098 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 4099 | |
| 4100 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4101 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4102 | |
| 4103 // Push src onto stack slow-path | |
| 4104 // Allocate a word | |
| 4105 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 4106 emit_opcode(cbuf,0xEC); | |
| 4107 emit_d8(cbuf,0x08); | |
| 4108 | |
| 4109 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 4110 emit_opcode (cbuf, 0x0F ); | |
| 4111 emit_opcode (cbuf, 0x11 ); | |
| 4112 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4113 | |
| 4114 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 4115 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4116 | |
| 4117 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 4118 emit_opcode(cbuf,0xC4); | |
| 4119 emit_d8(cbuf,0x08); | |
| 4120 | |
| 4121 // CALL directly to the runtime | |
| 4122 cbuf.set_inst_mark(); | |
| 4123 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 4124 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 4125 // Carry on here... | |
| 4126 %} | |
| 4127 | |
| 4128 enc_class D2X_encoding( regX dst, regD src ) %{ | |
| 4129 // Allocate a word | |
| 4130 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4131 emit_opcode(cbuf,0xEC); | |
| 4132 emit_d8(cbuf,0x04); | |
| 4133 int pop = 0x02; | |
| 4134 if ($src$$reg != FPR1L_enc) { | |
| 4135 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 4136 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 4137 pop = 0x03; | |
| 4138 } | |
| 4139 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] | |
| 4140 | |
| 4141 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 4142 emit_opcode (cbuf, 0x0F ); | |
| 4143 emit_opcode (cbuf, 0x10 ); | |
| 4144 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4145 | |
| 4146 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4147 emit_opcode(cbuf,0xC4); | |
| 4148 emit_d8(cbuf,0x04); | |
| 4149 // Carry on here... | |
| 4150 %} | |
| 4151 | |
| 4152 enc_class FX2I_encoding( regX src, eRegI dst ) %{ | |
| 4153 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 4154 | |
| 4155 // Compare the result to see if we need to go to the slow path | |
| 4156 emit_opcode(cbuf,0x81); // CMP dst,imm | |
| 4157 emit_rm (cbuf,0x3,0x7,$dst$$reg); | |
| 4158 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 4159 | |
| 4160 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4161 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4162 // Store xmm to a temp memory | |
| 4163 // location and push it onto stack. | |
| 4164 | |
| 4165 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4166 emit_opcode(cbuf,0xEC); | |
| 4167 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4168 | |
| 4169 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm | |
| 4170 emit_opcode (cbuf, 0x0F ); | |
| 4171 emit_opcode (cbuf, 0x11 ); | |
| 4172 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4173 | |
| 4174 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] | |
| 4175 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4176 | |
| 4177 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4178 emit_opcode(cbuf,0xC4); | |
| 4179 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4180 | |
| 4181 // CALL directly to the runtime | |
| 4182 cbuf.set_inst_mark(); | |
| 4183 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 4184 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 4185 | |
| 4186 // Carry on here... | |
| 4187 %} | |
| 4188 | |
| 4189 enc_class X2D_encoding( regD dst, regX src ) %{ | |
| 4190 // Allocate a word | |
| 4191 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4192 emit_opcode(cbuf,0xEC); | |
| 4193 emit_d8(cbuf,0x04); | |
| 4194 | |
| 4195 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm | |
| 4196 emit_opcode (cbuf, 0x0F ); | |
| 4197 emit_opcode (cbuf, 0x11 ); | |
| 4198 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4199 | |
| 4200 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 4201 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4202 | |
| 4203 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4204 emit_opcode(cbuf,0xC4); | |
| 4205 emit_d8(cbuf,0x04); | |
| 4206 | |
| 4207 // Carry on here... | |
| 4208 %} | |
| 4209 | |
| 4210 enc_class AbsXF_encoding(regX dst) %{ | |
| 4211 address signmask_address=(address)float_signmask_pool; | |
| 4212 // andpd:\tANDPS $dst,[signconst] | |
| 4213 emit_opcode(cbuf, 0x0F); | |
| 4214 emit_opcode(cbuf, 0x54); | |
| 4215 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4216 emit_d32(cbuf, (int)signmask_address); | |
| 4217 %} | |
| 4218 | |
| 4219 enc_class AbsXD_encoding(regXD dst) %{ | |
| 4220 address signmask_address=(address)double_signmask_pool; | |
| 4221 // andpd:\tANDPD $dst,[signconst] | |
| 4222 emit_opcode(cbuf, 0x66); | |
| 4223 emit_opcode(cbuf, 0x0F); | |
| 4224 emit_opcode(cbuf, 0x54); | |
| 4225 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4226 emit_d32(cbuf, (int)signmask_address); | |
| 4227 %} | |
| 4228 | |
| 4229 enc_class NegXF_encoding(regX dst) %{ | |
| 4230 address signmask_address=(address)float_signflip_pool; | |
| 4231 // andpd:\tXORPS $dst,[signconst] | |
| 4232 emit_opcode(cbuf, 0x0F); | |
| 4233 emit_opcode(cbuf, 0x57); | |
| 4234 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4235 emit_d32(cbuf, (int)signmask_address); | |
| 4236 %} | |
| 4237 | |
| 4238 enc_class NegXD_encoding(regXD dst) %{ | |
| 4239 address signmask_address=(address)double_signflip_pool; | |
| 4240 // andpd:\tXORPD $dst,[signconst] | |
| 4241 emit_opcode(cbuf, 0x66); | |
| 4242 emit_opcode(cbuf, 0x0F); | |
| 4243 emit_opcode(cbuf, 0x57); | |
| 4244 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4245 emit_d32(cbuf, (int)signmask_address); | |
| 4246 %} | |
| 4247 | |
| 4248 enc_class FMul_ST_reg( eRegF src1 ) %{ | |
| 4249 // Operand was loaded from memory into fp ST (stack top) | |
| 4250 // FMUL ST,$src /* D8 C8+i */ | |
| 4251 emit_opcode(cbuf, 0xD8); | |
| 4252 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 4253 %} | |
| 4254 | |
| 4255 enc_class FAdd_ST_reg( eRegF src2 ) %{ | |
| 4256 // FADDP ST,src2 /* D8 C0+i */ | |
| 4257 emit_opcode(cbuf, 0xD8); | |
| 4258 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4259 //could use FADDP src2,fpST /* DE C0+i */ | |
| 4260 %} | |
| 4261 | |
| 4262 enc_class FAddP_reg_ST( eRegF src2 ) %{ | |
| 4263 // FADDP src2,ST /* DE C0+i */ | |
| 4264 emit_opcode(cbuf, 0xDE); | |
| 4265 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4266 %} | |
| 4267 | |
| 4268 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ | |
| 4269 // Operand has been loaded into fp ST (stack top) | |
| 4270 // FSUB ST,$src1 | |
| 4271 emit_opcode(cbuf, 0xD8); | |
| 4272 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 4273 | |
| 4274 // FDIV | |
| 4275 emit_opcode(cbuf, 0xD8); | |
| 4276 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 4277 %} | |
| 4278 | |
| 4279 enc_class MulFAddF (eRegF src1, eRegF src2) %{ | |
| 4280 // Operand was loaded from memory into fp ST (stack top) | |
| 4281 // FADD ST,$src /* D8 C0+i */ | |
| 4282 emit_opcode(cbuf, 0xD8); | |
| 4283 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4284 | |
| 4285 // FMUL ST,src2 /* D8 C*+i */ | |
| 4286 emit_opcode(cbuf, 0xD8); | |
| 4287 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4288 %} | |
| 4289 | |
| 4290 | |
| 4291 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ | |
| 4292 // Operand was loaded from memory into fp ST (stack top) | |
| 4293 // FADD ST,$src /* D8 C0+i */ | |
| 4294 emit_opcode(cbuf, 0xD8); | |
| 4295 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4296 | |
| 4297 // FMULP src2,ST /* DE C8+i */ | |
| 4298 emit_opcode(cbuf, 0xDE); | |
| 4299 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4300 %} | |
| 4301 | |
| 4302 enc_class enc_membar_acquire %{ | |
| 4303 // Doug Lea believes this is not needed with current Sparcs and TSO. | |
| 4304 // MacroAssembler masm(&cbuf); | |
| 4305 // masm.membar(); | |
| 4306 %} | |
| 4307 | |
| 4308 enc_class enc_membar_release %{ | |
| 4309 // Doug Lea believes this is not needed with current Sparcs and TSO. | |
| 4310 // MacroAssembler masm(&cbuf); | |
| 4311 // masm.membar(); | |
| 4312 %} | |
| 4313 | |
| 4314 enc_class enc_membar_volatile %{ | |
| 4315 MacroAssembler masm(&cbuf); | |
| 304 | 4316 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad | |
| 4317 Assembler::StoreStore)); | |
| 0 | 4318 %} |
| 4319 | |
| 4320 // Atomically load the volatile long | |
| 4321 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 4322 emit_opcode(cbuf,0xDF); | |
| 4323 int rm_byte_opcode = 0x05; | |
| 4324 int base = $mem$$base; | |
| 4325 int index = $mem$$index; | |
| 4326 int scale = $mem$$scale; | |
| 4327 int displace = $mem$$disp; | |
| 4328 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4329 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4330 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); | |
| 4331 %} | |
| 4332 | |
| 4333 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ | |
| 4334 { // Atomic long load | |
| 4335 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4336 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4337 emit_opcode(cbuf,0x0F); | |
| 4338 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4339 int base = $mem$$base; | |
| 4340 int index = $mem$$index; | |
| 4341 int scale = $mem$$scale; | |
| 4342 int displace = $mem$$disp; | |
| 4343 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4344 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4345 } | |
| 4346 { // MOVSD $dst,$tmp ! atomic long store | |
| 4347 emit_opcode(cbuf,0xF2); | |
| 4348 emit_opcode(cbuf,0x0F); | |
| 4349 emit_opcode(cbuf,0x11); | |
| 4350 int base = $dst$$base; | |
| 4351 int index = $dst$$index; | |
| 4352 int scale = $dst$$scale; | |
| 4353 int displace = $dst$$disp; | |
| 4354 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4355 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4356 } | |
| 4357 %} | |
| 4358 | |
| 4359 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ | |
| 4360 { // Atomic long load | |
| 4361 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4362 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4363 emit_opcode(cbuf,0x0F); | |
| 4364 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4365 int base = $mem$$base; | |
| 4366 int index = $mem$$index; | |
| 4367 int scale = $mem$$scale; | |
| 4368 int displace = $mem$$disp; | |
| 4369 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4370 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4371 } | |
| 4372 { // MOVD $dst.lo,$tmp | |
| 4373 emit_opcode(cbuf,0x66); | |
| 4374 emit_opcode(cbuf,0x0F); | |
| 4375 emit_opcode(cbuf,0x7E); | |
| 4376 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); | |
| 4377 } | |
| 4378 { // PSRLQ $tmp,32 | |
| 4379 emit_opcode(cbuf,0x66); | |
| 4380 emit_opcode(cbuf,0x0F); | |
| 4381 emit_opcode(cbuf,0x73); | |
| 4382 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); | |
| 4383 emit_d8(cbuf, 0x20); | |
| 4384 } | |
| 4385 { // MOVD $dst.hi,$tmp | |
| 4386 emit_opcode(cbuf,0x66); | |
| 4387 emit_opcode(cbuf,0x0F); | |
| 4388 emit_opcode(cbuf,0x7E); | |
| 4389 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 4390 } | |
| 4391 %} | |
| 4392 | |
| 4393 // Volatile Store Long. Must be atomic, so move it into | |
| 4394 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 4395 // target address before the store (for null-ptr checks) | |
| 4396 // so the memory operand is used twice in the encoding. | |
| 4397 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 4398 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 4399 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop | |
| 4400 emit_opcode(cbuf,0xDF); | |
| 4401 int rm_byte_opcode = 0x07; | |
| 4402 int base = $mem$$base; | |
| 4403 int index = $mem$$index; | |
| 4404 int scale = $mem$$scale; | |
| 4405 int displace = $mem$$disp; | |
| 4406 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4407 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4408 %} | |
| 4409 | |
| 4410 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ | |
| 4411 { // Atomic long load | |
| 4412 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] | |
| 4413 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4414 emit_opcode(cbuf,0x0F); | |
| 4415 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4416 int base = $src$$base; | |
| 4417 int index = $src$$index; | |
| 4418 int scale = $src$$scale; | |
| 4419 int displace = $src$$disp; | |
| 4420 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4421 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4422 } | |
| 4423 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop | |
| 4424 { // MOVSD $mem,$tmp ! atomic long store | |
| 4425 emit_opcode(cbuf,0xF2); | |
| 4426 emit_opcode(cbuf,0x0F); | |
| 4427 emit_opcode(cbuf,0x11); | |
| 4428 int base = $mem$$base; | |
| 4429 int index = $mem$$index; | |
| 4430 int scale = $mem$$scale; | |
| 4431 int displace = $mem$$disp; | |
| 4432 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4433 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4434 } | |
| 4435 %} | |
| 4436 | |
| 4437 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ | |
| 4438 { // MOVD $tmp,$src.lo | |
| 4439 emit_opcode(cbuf,0x66); | |
| 4440 emit_opcode(cbuf,0x0F); | |
| 4441 emit_opcode(cbuf,0x6E); | |
| 4442 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 4443 } | |
| 4444 { // MOVD $tmp2,$src.hi | |
| 4445 emit_opcode(cbuf,0x66); | |
| 4446 emit_opcode(cbuf,0x0F); | |
| 4447 emit_opcode(cbuf,0x6E); | |
| 4448 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 4449 } | |
| 4450 { // PUNPCKLDQ $tmp,$tmp2 | |
| 4451 emit_opcode(cbuf,0x66); | |
| 4452 emit_opcode(cbuf,0x0F); | |
| 4453 emit_opcode(cbuf,0x62); | |
| 4454 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); | |
| 4455 } | |
| 4456 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop | |
| 4457 { // MOVSD $mem,$tmp ! atomic long store | |
| 4458 emit_opcode(cbuf,0xF2); | |
| 4459 emit_opcode(cbuf,0x0F); | |
| 4460 emit_opcode(cbuf,0x11); | |
| 4461 int base = $mem$$base; | |
| 4462 int index = $mem$$index; | |
| 4463 int scale = $mem$$scale; | |
| 4464 int displace = $mem$$disp; | |
| 4465 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4466 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4467 } | |
| 4468 %} | |
| 4469 | |
| 4470 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4471 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 4472 // in the process | |
| 4473 // We current use TESTL [spp],EDI | |
| 4474 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 4475 | |
| 4476 enc_class Safepoint_Poll() %{ | |
| 4477 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); | |
| 4478 emit_opcode(cbuf,0x85); | |
| 4479 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 4480 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 4481 %} | |
| 4482 %} | |
| 4483 | |
| 4484 | |
| 4485 //----------FRAME-------------------------------------------------------------- | |
| 4486 // Definition of frame structure and management information. | |
| 4487 // | |
| 4488 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4489 // | (to get allocators register number | |
| 4490 // G Owned by | | v add OptoReg::stack0()) | |
| 4491 // r CALLER | | | |
| 4492 // o | +--------+ pad to even-align allocators stack-slot | |
| 4493 // w V | pad0 | numbers; owned by CALLER | |
| 4494 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4495 // h ^ | in | 5 | |
| 4496 // | | args | 4 Holes in incoming args owned by SELF | |
| 4497 // | | | | 3 | |
| 4498 // | | +--------+ | |
| 4499 // V | | old out| Empty on Intel, window on Sparc | |
| 4500 // | old |preserve| Must be even aligned. | |
| 4501 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4502 // | | in | 3 area for Intel ret address | |
| 4503 // Owned by |preserve| Empty on Sparc. | |
| 4504 // SELF +--------+ | |
| 4505 // | | pad2 | 2 pad to align old SP | |
| 4506 // | +--------+ 1 | |
| 4507 // | | locks | 0 | |
| 4508 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4509 // | | pad1 | 11 pad to align new SP | |
| 4510 // | +--------+ | |
| 4511 // | | | 10 | |
| 4512 // | | spills | 9 spills | |
| 4513 // V | | 8 (pad0 slot for callee) | |
| 4514 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4515 // ^ | out | 7 | |
| 4516 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4517 // Owned by +--------+ | |
| 4518 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4519 // | new |preserve| Must be even-aligned. | |
| 4520 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4521 // | | | | |
| 4522 // | |
| 4523 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4524 // known from SELF's arguments and the Java calling convention. | |
| 4525 // Region 6-7 is determined per call site. | |
| 4526 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4527 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4528 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4529 // incoming area, as the Java calling convention is completely under | |
| 4530 // the control of the AD file. Doubles can be sorted and packed to | |
| 4531 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4532 // varargs C calling conventions. | |
| 4533 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4534 // even aligned with pad0 as needed. | |
| 4535 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4536 // region 6-11 is even aligned; it may be padded out more so that | |
| 4537 // the region from SP to FP meets the minimum stack alignment. | |
| 4538 | |
| 4539 frame %{ | |
| 4540 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4541 stack_direction(TOWARDS_LOW); | |
| 4542 | |
| 4543 // These three registers define part of the calling convention | |
| 4544 // between compiled code and the interpreter. | |
| 4545 inline_cache_reg(EAX); // Inline Cache Register | |
| 4546 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 4547 | |
| 4548 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 4549 cisc_spilling_operand_name(indOffset32); | |
| 4550 | |
| 4551 // Number of stack slots consumed by locking an object | |
| 4552 sync_stack_slots(1); | |
| 4553 | |
| 4554 // Compiled code's Frame Pointer | |
| 4555 frame_pointer(ESP); | |
| 4556 // Interpreter stores its frame pointer in a register which is | |
| 4557 // stored to the stack by I2CAdaptors. | |
| 4558 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4559 interpreter_frame_pointer(EBP); | |
| 4560 | |
| 4561 // Stack alignment requirement | |
| 4562 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4563 stack_alignment(StackAlignmentInBytes); | |
| 4564 | |
| 4565 // Number of stack slots between incoming argument block and the start of | |
| 4566 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4567 // EPILOG must remove this many slots. Intel needs one slot for | |
| 4568 // return address and one for rbp, (must save rbp) | |
| 4569 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 4570 | |
| 4571 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4572 // for calls to C. Supports the var-args backing area for register parms. | |
| 4573 varargs_C_out_slots_killed(0); | |
| 4574 | |
| 4575 // The after-PROLOG location of the return address. Location of | |
| 4576 // return address specifies a type (REG or STACK) and a number | |
| 4577 // representing the register number (i.e. - use a register name) or | |
| 4578 // stack slot. | |
| 4579 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4580 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4581 return_addr(STACK - 1 + | |
| 4582 round_to(1+VerifyStackAtCalls+ | |
| 4583 Compile::current()->fixed_slots(), | |
| 4584 (StackAlignmentInBytes/wordSize))); | |
| 4585 | |
| 4586 // Body of function which returns an integer array locating | |
| 4587 // arguments either in registers or in stack slots. Passed an array | |
| 4588 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4589 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4590 // arguments for a CALLEE. Incoming stack arguments are | |
| 4591 // automatically biased by the preserve_stack_slots field above. | |
| 4592 calling_convention %{ | |
| 4593 // No difference between ingoing/outgoing just pass false | |
| 4594 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4595 %} | |
| 4596 | |
| 4597 | |
| 4598 // Body of function which returns an integer array locating | |
| 4599 // arguments either in registers or in stack slots. Passed an array | |
| 4600 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4601 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4602 // arguments for a CALLEE. Incoming stack arguments are | |
| 4603 // automatically biased by the preserve_stack_slots field above. | |
| 4604 c_calling_convention %{ | |
| 4605 // This is obviously always outgoing | |
| 4606 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4607 %} | |
| 4608 | |
| 4609 // Location of C & interpreter return values | |
| 4610 c_return_value %{ | |
| 4611 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4612 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4613 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4614 |
| 4615 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 4616 // that C functions return float and double results in XMM0. | |
| 4617 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
| 4618 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4619 if( ideal_reg == Op_RegF && UseSSE>=2 ) | |
| 4620 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4621 | |
| 4622 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4623 %} | |
| 4624 | |
| 4625 // Location of return values | |
| 4626 return_value %{ | |
| 4627 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4628 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4629 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4630 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
| 4631 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4632 if( ideal_reg == Op_RegF && UseSSE>=1 ) | |
| 4633 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4634 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4635 %} | |
| 4636 | |
| 4637 %} | |
| 4638 | |
| 4639 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4640 //----------Operand Attributes------------------------------------------------- | |
| 4641 op_attrib op_cost(0); // Required cost attribute | |
| 4642 | |
| 4643 //----------Instruction Attributes--------------------------------------------- | |
| 4644 ins_attrib ins_cost(100); // Required cost attribute | |
| 4645 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4646 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4647 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 4648 // non-matching short branch variant of some | |
| 4649 // long branch? | |
| 4650 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 4651 // specifies the alignment that some part of the instruction (not | |
| 4652 // necessarily the start) requires. If > 1, a compute_padding() | |
| 4653 // function must be provided for the instruction | |
| 4654 | |
| 4655 //----------OPERANDS----------------------------------------------------------- | |
| 4656 // Operand definitions must precede instruction definitions for correct parsing | |
| 4657 // in the ADLC because operands constitute user defined types which are used in | |
| 4658 // instruction definitions. | |
| 4659 | |
| 4660 //----------Simple Operands---------------------------------------------------- | |
| 4661 // Immediate Operands | |
| 4662 // Integer Immediate | |
| 4663 operand immI() %{ | |
| 4664 match(ConI); | |
| 4665 | |
| 4666 op_cost(10); | |
| 4667 format %{ %} | |
| 4668 interface(CONST_INTER); | |
| 4669 %} | |
| 4670 | |
| 4671 // Constant for test vs zero | |
| 4672 operand immI0() %{ | |
| 4673 predicate(n->get_int() == 0); | |
| 4674 match(ConI); | |
| 4675 | |
| 4676 op_cost(0); | |
| 4677 format %{ %} | |
| 4678 interface(CONST_INTER); | |
| 4679 %} | |
| 4680 | |
| 4681 // Constant for increment | |
| 4682 operand immI1() %{ | |
| 4683 predicate(n->get_int() == 1); | |
| 4684 match(ConI); | |
| 4685 | |
| 4686 op_cost(0); | |
| 4687 format %{ %} | |
| 4688 interface(CONST_INTER); | |
| 4689 %} | |
| 4690 | |
| 4691 // Constant for decrement | |
| 4692 operand immI_M1() %{ | |
| 4693 predicate(n->get_int() == -1); | |
| 4694 match(ConI); | |
| 4695 | |
| 4696 op_cost(0); | |
| 4697 format %{ %} | |
| 4698 interface(CONST_INTER); | |
| 4699 %} | |
| 4700 | |
| 4701 // Valid scale values for addressing modes | |
| 4702 operand immI2() %{ | |
| 4703 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4704 match(ConI); | |
| 4705 | |
| 4706 format %{ %} | |
| 4707 interface(CONST_INTER); | |
| 4708 %} | |
| 4709 | |
| 4710 operand immI8() %{ | |
| 4711 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 4712 match(ConI); | |
| 4713 | |
| 4714 op_cost(5); | |
| 4715 format %{ %} | |
| 4716 interface(CONST_INTER); | |
| 4717 %} | |
| 4718 | |
| 4719 operand immI16() %{ | |
| 4720 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4721 match(ConI); | |
| 4722 | |
| 4723 op_cost(10); | |
| 4724 format %{ %} | |
| 4725 interface(CONST_INTER); | |
| 4726 %} | |
| 4727 | |
| 4728 // Constant for long shifts | |
| 4729 operand immI_32() %{ | |
| 4730 predicate( n->get_int() == 32 ); | |
| 4731 match(ConI); | |
| 4732 | |
| 4733 op_cost(0); | |
| 4734 format %{ %} | |
| 4735 interface(CONST_INTER); | |
| 4736 %} | |
| 4737 | |
| 4738 operand immI_1_31() %{ | |
| 4739 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 4740 match(ConI); | |
| 4741 | |
| 4742 op_cost(0); | |
| 4743 format %{ %} | |
| 4744 interface(CONST_INTER); | |
| 4745 %} | |
| 4746 | |
| 4747 operand immI_32_63() %{ | |
| 4748 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 4749 match(ConI); | |
| 4750 op_cost(0); | |
| 4751 | |
| 4752 format %{ %} | |
| 4753 interface(CONST_INTER); | |
| 4754 %} | |
| 4755 | |
| 219 | 4756 operand immI_1() %{ |
| 4757 predicate( n->get_int() == 1 ); | |
| 4758 match(ConI); | |
| 4759 | |
| 4760 op_cost(0); | |
| 4761 format %{ %} | |
| 4762 interface(CONST_INTER); | |
| 4763 %} | |
| 4764 | |
| 4765 operand immI_2() %{ | |
| 4766 predicate( n->get_int() == 2 ); | |
| 4767 match(ConI); | |
| 4768 | |
| 4769 op_cost(0); | |
| 4770 format %{ %} | |
| 4771 interface(CONST_INTER); | |
| 4772 %} | |
| 4773 | |
| 4774 operand immI_3() %{ | |
| 4775 predicate( n->get_int() == 3 ); | |
| 4776 match(ConI); | |
| 4777 | |
| 4778 op_cost(0); | |
| 4779 format %{ %} | |
| 4780 interface(CONST_INTER); | |
| 4781 %} | |
| 4782 | |
| 0 | 4783 // Pointer Immediate |
| 4784 operand immP() %{ | |
| 4785 match(ConP); | |
| 4786 | |
| 4787 op_cost(10); | |
| 4788 format %{ %} | |
| 4789 interface(CONST_INTER); | |
| 4790 %} | |
| 4791 | |
| 4792 // NULL Pointer Immediate | |
| 4793 operand immP0() %{ | |
| 4794 predicate( n->get_ptr() == 0 ); | |
| 4795 match(ConP); | |
| 4796 op_cost(0); | |
| 4797 | |
| 4798 format %{ %} | |
| 4799 interface(CONST_INTER); | |
| 4800 %} | |
| 4801 | |
| 4802 // Long Immediate | |
| 4803 operand immL() %{ | |
| 4804 match(ConL); | |
| 4805 | |
| 4806 op_cost(20); | |
| 4807 format %{ %} | |
| 4808 interface(CONST_INTER); | |
| 4809 %} | |
| 4810 | |
| 4811 // Long Immediate zero | |
| 4812 operand immL0() %{ | |
| 4813 predicate( n->get_long() == 0L ); | |
| 4814 match(ConL); | |
| 4815 op_cost(0); | |
| 4816 | |
| 4817 format %{ %} | |
| 4818 interface(CONST_INTER); | |
| 4819 %} | |
| 4820 | |
| 403 | 4821 // Long Immediate zero |
| 4822 operand immL_M1() %{ | |
| 4823 predicate( n->get_long() == -1L ); | |
| 4824 match(ConL); | |
| 4825 op_cost(0); | |
| 4826 | |
| 4827 format %{ %} | |
| 4828 interface(CONST_INTER); | |
| 4829 %} | |
| 4830 | |
| 0 | 4831 // Long immediate from 0 to 127. |
| 4832 // Used for a shorter form of long mul by 10. | |
| 4833 operand immL_127() %{ | |
| 4834 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4835 match(ConL); | |
| 4836 op_cost(0); | |
| 4837 | |
| 4838 format %{ %} | |
| 4839 interface(CONST_INTER); | |
| 4840 %} | |
| 4841 | |
| 4842 // Long Immediate: low 32-bit mask | |
| 4843 operand immL_32bits() %{ | |
| 4844 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4845 match(ConL); | |
| 4846 op_cost(0); | |
| 4847 | |
| 4848 format %{ %} | |
| 4849 interface(CONST_INTER); | |
| 4850 %} | |
| 4851 | |
| 4852 // Long Immediate: low 32-bit mask | |
| 4853 operand immL32() %{ | |
| 4854 predicate(n->get_long() == (int)(n->get_long())); | |
| 4855 match(ConL); | |
| 4856 op_cost(20); | |
| 4857 | |
| 4858 format %{ %} | |
| 4859 interface(CONST_INTER); | |
| 4860 %} | |
| 4861 | |
| 4862 //Double Immediate zero | |
| 4863 operand immD0() %{ | |
| 4864 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4865 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4866 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4867 match(ConD); | |
| 4868 | |
| 4869 op_cost(5); | |
| 4870 format %{ %} | |
| 4871 interface(CONST_INTER); | |
| 4872 %} | |
| 4873 | |
| 4874 // Double Immediate | |
| 4875 operand immD1() %{ | |
| 4876 predicate( UseSSE<=1 && n->getd() == 1.0 ); | |
| 4877 match(ConD); | |
| 4878 | |
| 4879 op_cost(5); | |
| 4880 format %{ %} | |
| 4881 interface(CONST_INTER); | |
| 4882 %} | |
| 4883 | |
| 4884 // Double Immediate | |
| 4885 operand immD() %{ | |
| 4886 predicate(UseSSE<=1); | |
| 4887 match(ConD); | |
| 4888 | |
| 4889 op_cost(5); | |
| 4890 format %{ %} | |
| 4891 interface(CONST_INTER); | |
| 4892 %} | |
| 4893 | |
| 4894 operand immXD() %{ | |
| 4895 predicate(UseSSE>=2); | |
| 4896 match(ConD); | |
| 4897 | |
| 4898 op_cost(5); | |
| 4899 format %{ %} | |
| 4900 interface(CONST_INTER); | |
| 4901 %} | |
| 4902 | |
| 4903 // Double Immediate zero | |
| 4904 operand immXD0() %{ | |
| 4905 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4906 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4907 // compare equal to -0.0. | |
| 4908 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4909 match(ConD); | |
| 4910 | |
| 4911 format %{ %} | |
| 4912 interface(CONST_INTER); | |
| 4913 %} | |
| 4914 | |
| 4915 // Float Immediate zero | |
| 4916 operand immF0() %{ | |
| 4917 predicate( UseSSE == 0 && n->getf() == 0.0 ); | |
| 4918 match(ConF); | |
| 4919 | |
| 4920 op_cost(5); | |
| 4921 format %{ %} | |
| 4922 interface(CONST_INTER); | |
| 4923 %} | |
| 4924 | |
| 4925 // Float Immediate | |
| 4926 operand immF() %{ | |
| 4927 predicate( UseSSE == 0 ); | |
| 4928 match(ConF); | |
| 4929 | |
| 4930 op_cost(5); | |
| 4931 format %{ %} | |
| 4932 interface(CONST_INTER); | |
| 4933 %} | |
| 4934 | |
| 4935 // Float Immediate | |
| 4936 operand immXF() %{ | |
| 4937 predicate(UseSSE >= 1); | |
| 4938 match(ConF); | |
| 4939 | |
| 4940 op_cost(5); | |
| 4941 format %{ %} | |
| 4942 interface(CONST_INTER); | |
| 4943 %} | |
| 4944 | |
| 4945 // Float Immediate zero. Zero and not -0.0 | |
| 4946 operand immXF0() %{ | |
| 4947 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); | |
| 4948 match(ConF); | |
| 4949 | |
| 4950 op_cost(5); | |
| 4951 format %{ %} | |
| 4952 interface(CONST_INTER); | |
| 4953 %} | |
| 4954 | |
| 4955 // Immediates for special shifts (sign extend) | |
| 4956 | |
| 4957 // Constants for increment | |
| 4958 operand immI_16() %{ | |
| 4959 predicate( n->get_int() == 16 ); | |
| 4960 match(ConI); | |
| 4961 | |
| 4962 format %{ %} | |
| 4963 interface(CONST_INTER); | |
| 4964 %} | |
| 4965 | |
| 4966 operand immI_24() %{ | |
| 4967 predicate( n->get_int() == 24 ); | |
| 4968 match(ConI); | |
| 4969 | |
| 4970 format %{ %} | |
| 4971 interface(CONST_INTER); | |
| 4972 %} | |
| 4973 | |
| 4974 // Constant for byte-wide masking | |
| 4975 operand immI_255() %{ | |
| 4976 predicate( n->get_int() == 255 ); | |
| 4977 match(ConI); | |
| 4978 | |
| 4979 format %{ %} | |
| 4980 interface(CONST_INTER); | |
| 4981 %} | |
| 4982 | |
| 4983 // Register Operands | |
| 4984 // Integer Register | |
| 4985 operand eRegI() %{ | |
| 4986 constraint(ALLOC_IN_RC(e_reg)); | |
| 4987 match(RegI); | |
| 4988 match(xRegI); | |
| 4989 match(eAXRegI); | |
| 4990 match(eBXRegI); | |
| 4991 match(eCXRegI); | |
| 4992 match(eDXRegI); | |
| 4993 match(eDIRegI); | |
| 4994 match(eSIRegI); | |
| 4995 | |
| 4996 format %{ %} | |
| 4997 interface(REG_INTER); | |
| 4998 %} | |
| 4999 | |
| 5000 // Subset of Integer Register | |
| 5001 operand xRegI(eRegI reg) %{ | |
| 5002 constraint(ALLOC_IN_RC(x_reg)); | |
| 5003 match(reg); | |
| 5004 match(eAXRegI); | |
| 5005 match(eBXRegI); | |
| 5006 match(eCXRegI); | |
| 5007 match(eDXRegI); | |
| 5008 | |
| 5009 format %{ %} | |
| 5010 interface(REG_INTER); | |
| 5011 %} | |
| 5012 | |
| 5013 // Special Registers | |
| 5014 operand eAXRegI(xRegI reg) %{ | |
| 5015 constraint(ALLOC_IN_RC(eax_reg)); | |
| 5016 match(reg); | |
| 5017 match(eRegI); | |
| 5018 | |
| 5019 format %{ "EAX" %} | |
| 5020 interface(REG_INTER); | |
| 5021 %} | |
| 5022 | |
| 5023 // Special Registers | |
| 5024 operand eBXRegI(xRegI reg) %{ | |
| 5025 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 5026 match(reg); | |
| 5027 match(eRegI); | |
| 5028 | |
| 5029 format %{ "EBX" %} | |
| 5030 interface(REG_INTER); | |
| 5031 %} | |
| 5032 | |
| 5033 operand eCXRegI(xRegI reg) %{ | |
| 5034 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 5035 match(reg); | |
| 5036 match(eRegI); | |
| 5037 | |
| 5038 format %{ "ECX" %} | |
| 5039 interface(REG_INTER); | |
| 5040 %} | |
| 5041 | |
| 5042 operand eDXRegI(xRegI reg) %{ | |
| 5043 constraint(ALLOC_IN_RC(edx_reg)); | |
| 5044 match(reg); | |
| 5045 match(eRegI); | |
| 5046 | |
| 5047 format %{ "EDX" %} | |
| 5048 interface(REG_INTER); | |
| 5049 %} | |
| 5050 | |
| 5051 operand eDIRegI(xRegI reg) %{ | |
| 5052 constraint(ALLOC_IN_RC(edi_reg)); | |
| 5053 match(reg); | |
| 5054 match(eRegI); | |
| 5055 | |
| 5056 format %{ "EDI" %} | |
| 5057 interface(REG_INTER); | |
| 5058 %} | |
| 5059 | |
| 5060 operand naxRegI() %{ | |
| 5061 constraint(ALLOC_IN_RC(nax_reg)); | |
| 5062 match(RegI); | |
| 5063 match(eCXRegI); | |
| 5064 match(eDXRegI); | |
| 5065 match(eSIRegI); | |
| 5066 match(eDIRegI); | |
| 5067 | |
| 5068 format %{ %} | |
| 5069 interface(REG_INTER); | |
| 5070 %} | |
| 5071 | |
| 5072 operand nadxRegI() %{ | |
| 5073 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 5074 match(RegI); | |
| 5075 match(eBXRegI); | |
| 5076 match(eCXRegI); | |
| 5077 match(eSIRegI); | |
| 5078 match(eDIRegI); | |
| 5079 | |
| 5080 format %{ %} | |
| 5081 interface(REG_INTER); | |
| 5082 %} | |
| 5083 | |
| 5084 operand ncxRegI() %{ | |
| 5085 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 5086 match(RegI); | |
| 5087 match(eAXRegI); | |
| 5088 match(eDXRegI); | |
| 5089 match(eSIRegI); | |
| 5090 match(eDIRegI); | |
| 5091 | |
| 5092 format %{ %} | |
| 5093 interface(REG_INTER); | |
| 5094 %} | |
| 5095 | |
| 5096 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 5097 // // | |
| 5098 operand eSIRegI(xRegI reg) %{ | |
| 5099 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5100 match(reg); | |
| 5101 match(eRegI); | |
| 5102 | |
| 5103 format %{ "ESI" %} | |
| 5104 interface(REG_INTER); | |
| 5105 %} | |
| 5106 | |
| 5107 // Pointer Register | |
| 5108 operand anyRegP() %{ | |
| 5109 constraint(ALLOC_IN_RC(any_reg)); | |
| 5110 match(RegP); | |
| 5111 match(eAXRegP); | |
| 5112 match(eBXRegP); | |
| 5113 match(eCXRegP); | |
| 5114 match(eDIRegP); | |
| 5115 match(eRegP); | |
| 5116 | |
| 5117 format %{ %} | |
| 5118 interface(REG_INTER); | |
| 5119 %} | |
| 5120 | |
| 5121 operand eRegP() %{ | |
| 5122 constraint(ALLOC_IN_RC(e_reg)); | |
| 5123 match(RegP); | |
| 5124 match(eAXRegP); | |
| 5125 match(eBXRegP); | |
| 5126 match(eCXRegP); | |
| 5127 match(eDIRegP); | |
| 5128 | |
| 5129 format %{ %} | |
| 5130 interface(REG_INTER); | |
| 5131 %} | |
| 5132 | |
| 5133 // On windows95, EBP is not safe to use for implicit null tests. | |
| 5134 operand eRegP_no_EBP() %{ | |
| 5135 constraint(ALLOC_IN_RC(e_reg_no_rbp)); | |
| 5136 match(RegP); | |
| 5137 match(eAXRegP); | |
| 5138 match(eBXRegP); | |
| 5139 match(eCXRegP); | |
| 5140 match(eDIRegP); | |
| 5141 | |
| 5142 op_cost(100); | |
| 5143 format %{ %} | |
| 5144 interface(REG_INTER); | |
| 5145 %} | |
| 5146 | |
| 5147 operand naxRegP() %{ | |
| 5148 constraint(ALLOC_IN_RC(nax_reg)); | |
| 5149 match(RegP); | |
| 5150 match(eBXRegP); | |
| 5151 match(eDXRegP); | |
| 5152 match(eCXRegP); | |
| 5153 match(eSIRegP); | |
| 5154 match(eDIRegP); | |
| 5155 | |
| 5156 format %{ %} | |
| 5157 interface(REG_INTER); | |
| 5158 %} | |
| 5159 | |
| 5160 operand nabxRegP() %{ | |
| 5161 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 5162 match(RegP); | |
| 5163 match(eCXRegP); | |
| 5164 match(eDXRegP); | |
| 5165 match(eSIRegP); | |
| 5166 match(eDIRegP); | |
| 5167 | |
| 5168 format %{ %} | |
| 5169 interface(REG_INTER); | |
| 5170 %} | |
| 5171 | |
| 5172 operand pRegP() %{ | |
| 5173 constraint(ALLOC_IN_RC(p_reg)); | |
| 5174 match(RegP); | |
| 5175 match(eBXRegP); | |
| 5176 match(eDXRegP); | |
| 5177 match(eSIRegP); | |
| 5178 match(eDIRegP); | |
| 5179 | |
| 5180 format %{ %} | |
| 5181 interface(REG_INTER); | |
| 5182 %} | |
| 5183 | |
| 5184 // Special Registers | |
| 5185 // Return a pointer value | |
| 5186 operand eAXRegP(eRegP reg) %{ | |
| 5187 constraint(ALLOC_IN_RC(eax_reg)); | |
| 5188 match(reg); | |
| 5189 format %{ "EAX" %} | |
| 5190 interface(REG_INTER); | |
| 5191 %} | |
| 5192 | |
| 5193 // Used in AtomicAdd | |
| 5194 operand eBXRegP(eRegP reg) %{ | |
| 5195 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 5196 match(reg); | |
| 5197 format %{ "EBX" %} | |
| 5198 interface(REG_INTER); | |
| 5199 %} | |
| 5200 | |
| 5201 // Tail-call (interprocedural jump) to interpreter | |
| 5202 operand eCXRegP(eRegP reg) %{ | |
| 5203 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 5204 match(reg); | |
| 5205 format %{ "ECX" %} | |
| 5206 interface(REG_INTER); | |
| 5207 %} | |
| 5208 | |
| 5209 operand eSIRegP(eRegP reg) %{ | |
| 5210 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5211 match(reg); | |
| 5212 format %{ "ESI" %} | |
| 5213 interface(REG_INTER); | |
| 5214 %} | |
| 5215 | |
| 5216 // Used in rep stosw | |
| 5217 operand eDIRegP(eRegP reg) %{ | |
| 5218 constraint(ALLOC_IN_RC(edi_reg)); | |
| 5219 match(reg); | |
| 5220 format %{ "EDI" %} | |
| 5221 interface(REG_INTER); | |
| 5222 %} | |
| 5223 | |
| 5224 operand eBPRegP() %{ | |
| 5225 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 5226 match(RegP); | |
| 5227 format %{ "EBP" %} | |
| 5228 interface(REG_INTER); | |
| 5229 %} | |
| 5230 | |
| 5231 operand eRegL() %{ | |
| 5232 constraint(ALLOC_IN_RC(long_reg)); | |
| 5233 match(RegL); | |
| 5234 match(eADXRegL); | |
| 5235 | |
| 5236 format %{ %} | |
| 5237 interface(REG_INTER); | |
| 5238 %} | |
| 5239 | |
| 5240 operand eADXRegL( eRegL reg ) %{ | |
| 5241 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5242 match(reg); | |
| 5243 | |
| 5244 format %{ "EDX:EAX" %} | |
| 5245 interface(REG_INTER); | |
| 5246 %} | |
| 5247 | |
| 5248 operand eBCXRegL( eRegL reg ) %{ | |
| 5249 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 5250 match(reg); | |
| 5251 | |
| 5252 format %{ "EBX:ECX" %} | |
| 5253 interface(REG_INTER); | |
| 5254 %} | |
| 5255 | |
| 5256 // Special case for integer high multiply | |
| 5257 operand eADXRegL_low_only() %{ | |
| 5258 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5259 match(RegL); | |
| 5260 | |
| 5261 format %{ "EAX" %} | |
| 5262 interface(REG_INTER); | |
| 5263 %} | |
| 5264 | |
| 5265 // Flags register, used as output of compare instructions | |
| 5266 operand eFlagsReg() %{ | |
| 5267 constraint(ALLOC_IN_RC(int_flags)); | |
| 5268 match(RegFlags); | |
| 5269 | |
| 5270 format %{ "EFLAGS" %} | |
| 5271 interface(REG_INTER); | |
| 5272 %} | |
| 5273 | |
| 5274 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5275 operand eFlagsRegU() %{ | |
| 5276 constraint(ALLOC_IN_RC(int_flags)); | |
| 5277 match(RegFlags); | |
| 5278 | |
| 5279 format %{ "EFLAGS_U" %} | |
| 5280 interface(REG_INTER); | |
| 5281 %} | |
| 5282 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5283 operand eFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5284 constraint(ALLOC_IN_RC(int_flags)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5285 match(RegFlags); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5286 predicate(false); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5287 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5288 format %{ "EFLAGS_U_CF" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5289 interface(REG_INTER); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5290 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5291 |
| 0 | 5292 // Condition Code Register used by long compare |
| 5293 operand flagsReg_long_LTGE() %{ | |
| 5294 constraint(ALLOC_IN_RC(int_flags)); | |
| 5295 match(RegFlags); | |
| 5296 format %{ "FLAGS_LTGE" %} | |
| 5297 interface(REG_INTER); | |
| 5298 %} | |
| 5299 operand flagsReg_long_EQNE() %{ | |
| 5300 constraint(ALLOC_IN_RC(int_flags)); | |
| 5301 match(RegFlags); | |
| 5302 format %{ "FLAGS_EQNE" %} | |
| 5303 interface(REG_INTER); | |
| 5304 %} | |
| 5305 operand flagsReg_long_LEGT() %{ | |
| 5306 constraint(ALLOC_IN_RC(int_flags)); | |
| 5307 match(RegFlags); | |
| 5308 format %{ "FLAGS_LEGT" %} | |
| 5309 interface(REG_INTER); | |
| 5310 %} | |
| 5311 | |
| 5312 // Float register operands | |
| 5313 operand regD() %{ | |
| 5314 predicate( UseSSE < 2 ); | |
| 5315 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 5316 match(RegD); | |
| 5317 match(regDPR1); | |
| 5318 match(regDPR2); | |
| 5319 format %{ %} | |
| 5320 interface(REG_INTER); | |
| 5321 %} | |
| 5322 | |
| 5323 operand regDPR1(regD reg) %{ | |
| 5324 predicate( UseSSE < 2 ); | |
| 5325 constraint(ALLOC_IN_RC(dbl_reg0)); | |
| 5326 match(reg); | |
| 5327 format %{ "FPR1" %} | |
| 5328 interface(REG_INTER); | |
| 5329 %} | |
| 5330 | |
| 5331 operand regDPR2(regD reg) %{ | |
| 5332 predicate( UseSSE < 2 ); | |
| 5333 constraint(ALLOC_IN_RC(dbl_reg1)); | |
| 5334 match(reg); | |
| 5335 format %{ "FPR2" %} | |
| 5336 interface(REG_INTER); | |
| 5337 %} | |
| 5338 | |
| 5339 operand regnotDPR1(regD reg) %{ | |
| 5340 predicate( UseSSE < 2 ); | |
| 5341 constraint(ALLOC_IN_RC(dbl_notreg0)); | |
| 5342 match(reg); | |
| 5343 format %{ %} | |
| 5344 interface(REG_INTER); | |
| 5345 %} | |
| 5346 | |
| 5347 // XMM Double register operands | |
| 5348 operand regXD() %{ | |
| 5349 predicate( UseSSE>=2 ); | |
| 5350 constraint(ALLOC_IN_RC(xdb_reg)); | |
| 5351 match(RegD); | |
| 5352 match(regXD6); | |
| 5353 match(regXD7); | |
| 5354 format %{ %} | |
| 5355 interface(REG_INTER); | |
| 5356 %} | |
| 5357 | |
| 5358 // XMM6 double register operands | |
| 5359 operand regXD6(regXD reg) %{ | |
| 5360 predicate( UseSSE>=2 ); | |
| 5361 constraint(ALLOC_IN_RC(xdb_reg6)); | |
| 5362 match(reg); | |
| 5363 format %{ "XMM6" %} | |
| 5364 interface(REG_INTER); | |
| 5365 %} | |
| 5366 | |
| 5367 // XMM7 double register operands | |
| 5368 operand regXD7(regXD reg) %{ | |
| 5369 predicate( UseSSE>=2 ); | |
| 5370 constraint(ALLOC_IN_RC(xdb_reg7)); | |
| 5371 match(reg); | |
| 5372 format %{ "XMM7" %} | |
| 5373 interface(REG_INTER); | |
| 5374 %} | |
| 5375 | |
| 5376 // Float register operands | |
| 5377 operand regF() %{ | |
| 5378 predicate( UseSSE < 2 ); | |
| 5379 constraint(ALLOC_IN_RC(flt_reg)); | |
| 5380 match(RegF); | |
| 5381 match(regFPR1); | |
| 5382 format %{ %} | |
| 5383 interface(REG_INTER); | |
| 5384 %} | |
| 5385 | |
| 5386 // Float register operands | |
| 5387 operand regFPR1(regF reg) %{ | |
| 5388 predicate( UseSSE < 2 ); | |
| 5389 constraint(ALLOC_IN_RC(flt_reg0)); | |
| 5390 match(reg); | |
| 5391 format %{ "FPR1" %} | |
| 5392 interface(REG_INTER); | |
| 5393 %} | |
| 5394 | |
| 5395 // XMM register operands | |
| 5396 operand regX() %{ | |
| 5397 predicate( UseSSE>=1 ); | |
| 5398 constraint(ALLOC_IN_RC(xmm_reg)); | |
| 5399 match(RegF); | |
| 5400 format %{ %} | |
| 5401 interface(REG_INTER); | |
| 5402 %} | |
| 5403 | |
| 5404 | |
| 5405 //----------Memory Operands---------------------------------------------------- | |
| 5406 // Direct Memory Operand | |
| 5407 operand direct(immP addr) %{ | |
| 5408 match(addr); | |
| 5409 | |
| 5410 format %{ "[$addr]" %} | |
| 5411 interface(MEMORY_INTER) %{ | |
| 5412 base(0xFFFFFFFF); | |
| 5413 index(0x4); | |
| 5414 scale(0x0); | |
| 5415 disp($addr); | |
| 5416 %} | |
| 5417 %} | |
| 5418 | |
| 5419 // Indirect Memory Operand | |
| 5420 operand indirect(eRegP reg) %{ | |
| 5421 constraint(ALLOC_IN_RC(e_reg)); | |
| 5422 match(reg); | |
| 5423 | |
| 5424 format %{ "[$reg]" %} | |
| 5425 interface(MEMORY_INTER) %{ | |
| 5426 base($reg); | |
| 5427 index(0x4); | |
| 5428 scale(0x0); | |
| 5429 disp(0x0); | |
| 5430 %} | |
| 5431 %} | |
| 5432 | |
| 5433 // Indirect Memory Plus Short Offset Operand | |
| 5434 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 5435 match(AddP reg off); | |
| 5436 | |
| 5437 format %{ "[$reg + $off]" %} | |
| 5438 interface(MEMORY_INTER) %{ | |
| 5439 base($reg); | |
| 5440 index(0x4); | |
| 5441 scale(0x0); | |
| 5442 disp($off); | |
| 5443 %} | |
| 5444 %} | |
| 5445 | |
| 5446 // Indirect Memory Plus Long Offset Operand | |
| 5447 operand indOffset32(eRegP reg, immI off) %{ | |
| 5448 match(AddP reg off); | |
| 5449 | |
| 5450 format %{ "[$reg + $off]" %} | |
| 5451 interface(MEMORY_INTER) %{ | |
| 5452 base($reg); | |
| 5453 index(0x4); | |
| 5454 scale(0x0); | |
| 5455 disp($off); | |
| 5456 %} | |
| 5457 %} | |
| 5458 | |
| 5459 // Indirect Memory Plus Long Offset Operand | |
| 5460 operand indOffset32X(eRegI reg, immP off) %{ | |
| 5461 match(AddP off reg); | |
| 5462 | |
| 5463 format %{ "[$reg + $off]" %} | |
| 5464 interface(MEMORY_INTER) %{ | |
| 5465 base($reg); | |
| 5466 index(0x4); | |
| 5467 scale(0x0); | |
| 5468 disp($off); | |
| 5469 %} | |
| 5470 %} | |
| 5471 | |
| 5472 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5473 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ | |
| 5474 match(AddP (AddP reg ireg) off); | |
| 5475 | |
| 5476 op_cost(10); | |
| 5477 format %{"[$reg + $off + $ireg]" %} | |
| 5478 interface(MEMORY_INTER) %{ | |
| 5479 base($reg); | |
| 5480 index($ireg); | |
| 5481 scale(0x0); | |
| 5482 disp($off); | |
| 5483 %} | |
| 5484 %} | |
| 5485 | |
| 5486 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5487 operand indIndex(eRegP reg, eRegI ireg) %{ | |
| 5488 match(AddP reg ireg); | |
| 5489 | |
| 5490 op_cost(10); | |
| 5491 format %{"[$reg + $ireg]" %} | |
| 5492 interface(MEMORY_INTER) %{ | |
| 5493 base($reg); | |
| 5494 index($ireg); | |
| 5495 scale(0x0); | |
| 5496 disp(0x0); | |
| 5497 %} | |
| 5498 %} | |
| 5499 | |
| 5500 // // ------------------------------------------------------------------------- | |
| 5501 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 5502 // // ------------------------------------------------------------------------- | |
| 5503 // // Scaled Memory Operands | |
| 5504 // // Indirect Memory Times Scale Plus Offset Operand | |
| 5505 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ | |
| 5506 // match(AddP off (LShiftI ireg scale)); | |
| 5507 // | |
| 5508 // op_cost(10); | |
| 5509 // format %{"[$off + $ireg << $scale]" %} | |
| 5510 // interface(MEMORY_INTER) %{ | |
| 5511 // base(0x4); | |
| 5512 // index($ireg); | |
| 5513 // scale($scale); | |
| 5514 // disp($off); | |
| 5515 // %} | |
| 5516 // %} | |
| 5517 | |
| 5518 // Indirect Memory Times Scale Plus Index Register | |
| 5519 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ | |
| 5520 match(AddP reg (LShiftI ireg scale)); | |
| 5521 | |
| 5522 op_cost(10); | |
| 5523 format %{"[$reg + $ireg << $scale]" %} | |
| 5524 interface(MEMORY_INTER) %{ | |
| 5525 base($reg); | |
| 5526 index($ireg); | |
| 5527 scale($scale); | |
| 5528 disp(0x0); | |
| 5529 %} | |
| 5530 %} | |
| 5531 | |
| 5532 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5533 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ | |
| 5534 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5535 | |
| 5536 op_cost(10); | |
| 5537 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5538 interface(MEMORY_INTER) %{ | |
| 5539 base($reg); | |
| 5540 index($ireg); | |
| 5541 scale($scale); | |
| 5542 disp($off); | |
| 5543 %} | |
| 5544 %} | |
| 5545 | |
| 5546 //----------Load Long Memory Operands------------------------------------------ | |
| 5547 // The load-long idiom will use it's address expression again after loading | |
| 5548 // the first word of the long. If the load-long destination overlaps with | |
| 5549 // registers used in the addressing expression, the 2nd half will be loaded | |
| 5550 // from a clobbered address. Fix this by requiring that load-long use | |
| 5551 // address registers that do not overlap with the load-long target. | |
| 5552 | |
| 5553 // load-long support | |
| 5554 operand load_long_RegP() %{ | |
| 5555 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5556 match(RegP); | |
| 5557 match(eSIRegP); | |
| 5558 op_cost(100); | |
| 5559 format %{ %} | |
| 5560 interface(REG_INTER); | |
| 5561 %} | |
| 5562 | |
| 5563 // Indirect Memory Operand Long | |
| 5564 operand load_long_indirect(load_long_RegP reg) %{ | |
| 5565 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5566 match(reg); | |
| 5567 | |
| 5568 format %{ "[$reg]" %} | |
| 5569 interface(MEMORY_INTER) %{ | |
| 5570 base($reg); | |
| 5571 index(0x4); | |
| 5572 scale(0x0); | |
| 5573 disp(0x0); | |
| 5574 %} | |
| 5575 %} | |
| 5576 | |
| 5577 // Indirect Memory Plus Long Offset Operand | |
| 5578 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 5579 match(AddP reg off); | |
| 5580 | |
| 5581 format %{ "[$reg + $off]" %} | |
| 5582 interface(MEMORY_INTER) %{ | |
| 5583 base($reg); | |
| 5584 index(0x4); | |
| 5585 scale(0x0); | |
| 5586 disp($off); | |
| 5587 %} | |
| 5588 %} | |
| 5589 | |
| 5590 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 5591 | |
| 5592 | |
| 5593 //----------Special Memory Operands-------------------------------------------- | |
| 5594 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5595 // values on the stack where a match requires a value to | |
| 5596 // flow through memory. | |
| 5597 operand stackSlotP(sRegP reg) %{ | |
| 5598 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5599 // No match rule because this operand is only generated in matching | |
| 5600 format %{ "[$reg]" %} | |
| 5601 interface(MEMORY_INTER) %{ | |
| 5602 base(0x4); // ESP | |
| 5603 index(0x4); // No Index | |
| 5604 scale(0x0); // No Scale | |
| 5605 disp($reg); // Stack Offset | |
| 5606 %} | |
| 5607 %} | |
| 5608 | |
| 5609 operand stackSlotI(sRegI reg) %{ | |
| 5610 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5611 // No match rule because this operand is only generated in matching | |
| 5612 format %{ "[$reg]" %} | |
| 5613 interface(MEMORY_INTER) %{ | |
| 5614 base(0x4); // ESP | |
| 5615 index(0x4); // No Index | |
| 5616 scale(0x0); // No Scale | |
| 5617 disp($reg); // Stack Offset | |
| 5618 %} | |
| 5619 %} | |
| 5620 | |
| 5621 operand stackSlotF(sRegF reg) %{ | |
| 5622 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5623 // No match rule because this operand is only generated in matching | |
| 5624 format %{ "[$reg]" %} | |
| 5625 interface(MEMORY_INTER) %{ | |
| 5626 base(0x4); // ESP | |
| 5627 index(0x4); // No Index | |
| 5628 scale(0x0); // No Scale | |
| 5629 disp($reg); // Stack Offset | |
| 5630 %} | |
| 5631 %} | |
| 5632 | |
| 5633 operand stackSlotD(sRegD reg) %{ | |
| 5634 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5635 // No match rule because this operand is only generated in matching | |
| 5636 format %{ "[$reg]" %} | |
| 5637 interface(MEMORY_INTER) %{ | |
| 5638 base(0x4); // ESP | |
| 5639 index(0x4); // No Index | |
| 5640 scale(0x0); // No Scale | |
| 5641 disp($reg); // Stack Offset | |
| 5642 %} | |
| 5643 %} | |
| 5644 | |
| 5645 operand stackSlotL(sRegL reg) %{ | |
| 5646 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5647 // No match rule because this operand is only generated in matching | |
| 5648 format %{ "[$reg]" %} | |
| 5649 interface(MEMORY_INTER) %{ | |
| 5650 base(0x4); // ESP | |
| 5651 index(0x4); // No Index | |
| 5652 scale(0x0); // No Scale | |
| 5653 disp($reg); // Stack Offset | |
| 5654 %} | |
| 5655 %} | |
| 5656 | |
| 5657 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 5658 // Indirect Memory Operand | |
| 5659 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 5660 %{ | |
| 5661 constraint(ALLOC_IN_RC(e_reg)); | |
| 5662 match(reg); | |
| 5663 | |
| 5664 op_cost(100); | |
| 5665 format %{ "[$reg]" %} | |
| 5666 interface(MEMORY_INTER) %{ | |
| 5667 base($reg); | |
| 5668 index(0x4); | |
| 5669 scale(0x0); | |
| 5670 disp(0x0); | |
| 5671 %} | |
| 5672 %} | |
| 5673 | |
| 5674 // Indirect Memory Plus Short Offset Operand | |
| 5675 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 5676 %{ | |
| 5677 match(AddP reg off); | |
| 5678 | |
| 5679 op_cost(100); | |
| 5680 format %{ "[$reg + $off]" %} | |
| 5681 interface(MEMORY_INTER) %{ | |
| 5682 base($reg); | |
| 5683 index(0x4); | |
| 5684 scale(0x0); | |
| 5685 disp($off); | |
| 5686 %} | |
| 5687 %} | |
| 5688 | |
| 5689 // Indirect Memory Plus Long Offset Operand | |
| 5690 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 5691 %{ | |
| 5692 match(AddP reg off); | |
| 5693 | |
| 5694 op_cost(100); | |
| 5695 format %{ "[$reg + $off]" %} | |
| 5696 interface(MEMORY_INTER) %{ | |
| 5697 base($reg); | |
| 5698 index(0x4); | |
| 5699 scale(0x0); | |
| 5700 disp($off); | |
| 5701 %} | |
| 5702 %} | |
| 5703 | |
| 5704 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5705 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) | |
| 5706 %{ | |
| 5707 match(AddP (AddP reg ireg) off); | |
| 5708 | |
| 5709 op_cost(100); | |
| 5710 format %{"[$reg + $off + $ireg]" %} | |
| 5711 interface(MEMORY_INTER) %{ | |
| 5712 base($reg); | |
| 5713 index($ireg); | |
| 5714 scale(0x0); | |
| 5715 disp($off); | |
| 5716 %} | |
| 5717 %} | |
| 5718 | |
| 5719 // Indirect Memory Times Scale Plus Index Register | |
| 5720 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) | |
| 5721 %{ | |
| 5722 match(AddP reg (LShiftI ireg scale)); | |
| 5723 | |
| 5724 op_cost(100); | |
| 5725 format %{"[$reg + $ireg << $scale]" %} | |
| 5726 interface(MEMORY_INTER) %{ | |
| 5727 base($reg); | |
| 5728 index($ireg); | |
| 5729 scale($scale); | |
| 5730 disp(0x0); | |
| 5731 %} | |
| 5732 %} | |
| 5733 | |
| 5734 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5735 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) | |
| 5736 %{ | |
| 5737 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5738 | |
| 5739 op_cost(100); | |
| 5740 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5741 interface(MEMORY_INTER) %{ | |
| 5742 base($reg); | |
| 5743 index($ireg); | |
| 5744 scale($scale); | |
| 5745 disp($off); | |
| 5746 %} | |
| 5747 %} | |
| 5748 | |
| 5749 //----------Conditional Branch Operands---------------------------------------- | |
| 5750 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5751 // the following set of codes: | |
| 5752 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5753 // | |
| 5754 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5755 // by the comparison instruction that sets a condition code flags register. | |
| 5756 // That result is represented by a flags operand whose subtype is appropriate | |
| 5757 // to the unsignedness (etc.) of the comparison. | |
| 5758 // | |
| 5759 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5760 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5761 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5762 | |
| 5763 // Comparision Code | |
| 5764 operand cmpOp() %{ | |
| 5765 match(Bool); | |
| 5766 | |
| 5767 format %{ "" %} | |
| 5768 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5769 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5770 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5771 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5772 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5773 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5774 greater(0xF, "g"); |
| 0 | 5775 %} |
| 5776 %} | |
| 5777 | |
| 5778 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5779 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5780 // C0 and C3 are turned into Carry & Zero flags. | |
| 5781 operand cmpOpU() %{ | |
| 5782 match(Bool); | |
| 5783 | |
| 5784 format %{ "" %} | |
| 5785 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5786 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5787 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5788 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5789 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5790 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5791 greater(0x7, "nbe"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5792 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5793 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5794 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5795 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5796 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5797 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5798 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5799 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5800 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5801 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5802 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5803 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5804 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5805 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5806 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5807 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5808 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5809 greater(0x7, "nbe"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5810 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5811 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5812 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5813 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5814 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5815 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5816 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5817 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5818 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5819 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5820 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5821 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5822 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5823 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5824 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5825 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5826 greater(0x7, "nbe"); |
| 0 | 5827 %} |
| 5828 %} | |
| 5829 | |
| 5830 // Comparison Code for FP conditional move | |
| 5831 operand cmpOp_fcmov() %{ | |
| 5832 match(Bool); | |
| 5833 | |
| 5834 format %{ "" %} | |
| 5835 interface(COND_INTER) %{ | |
| 5836 equal (0x0C8); | |
| 5837 not_equal (0x1C8); | |
| 5838 less (0x0C0); | |
| 5839 greater_equal(0x1C0); | |
| 5840 less_equal (0x0D0); | |
| 5841 greater (0x1D0); | |
| 5842 %} | |
| 5843 %} | |
| 5844 | |
| 5845 // Comparision Code used in long compares | |
| 5846 operand cmpOp_commute() %{ | |
| 5847 match(Bool); | |
| 5848 | |
| 5849 format %{ "" %} | |
| 5850 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5851 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5852 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5853 less(0xF, "g"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5854 greater_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5855 less_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5856 greater(0xC, "l"); |
| 0 | 5857 %} |
| 5858 %} | |
| 5859 | |
| 5860 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5861 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5862 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5863 // instructions for every form of operand when the instruction accepts |
| 5864 // multiple operand types with the same basic encoding and format. The classic | |
| 5865 // case of this is memory operands. | |
| 5866 | |
| 5867 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5868 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5869 | |
| 5870 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5871 // This means some kind of offset is always required and you cannot use | |
| 5872 // an oop as the offset (done when working on static globals). | |
| 5873 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5874 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5875 | |
| 5876 | |
| 5877 //----------PIPELINE----------------------------------------------------------- | |
| 5878 // Rules which define the behavior of the target architectures pipeline. | |
| 5879 pipeline %{ | |
| 5880 | |
| 5881 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5882 attributes %{ | |
| 5883 variable_size_instructions; // Fixed size instructions | |
| 5884 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5885 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5886 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5887 instruction_fetch_units = 1; // of 16 bytes | |
| 5888 | |
| 5889 // List of nop instructions | |
| 5890 nops( MachNop ); | |
| 5891 %} | |
| 5892 | |
| 5893 //----------RESOURCES---------------------------------------------------------- | |
| 5894 // Resources are the functional units available to the machine | |
| 5895 | |
| 5896 // Generic P2/P3 pipeline | |
| 5897 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5898 // 3 instructions decoded per cycle. | |
| 5899 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5900 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5901 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5902 MS0, MS1, MEM = MS0 | MS1, | |
| 5903 BR, FPU, | |
| 5904 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5905 | |
| 5906 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5907 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5908 | |
| 5909 // Generic P2/P3 pipeline | |
| 5910 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5911 | |
| 5912 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5913 // Pipeline Classes describe the stages in which input and output are | |
| 5914 // referenced by the hardware pipeline. | |
| 5915 | |
| 5916 // Naming convention: ialu or fpu | |
| 5917 // Then: _reg | |
| 5918 // Then: _reg if there is a 2nd register | |
| 5919 // Then: _long if it's a pair of instructions implementing a long | |
| 5920 // Then: _fat if it requires the big decoder | |
| 5921 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5922 | |
| 5923 // Integer ALU reg operation | |
| 5924 pipe_class ialu_reg(eRegI dst) %{ | |
| 5925 single_instruction; | |
| 5926 dst : S4(write); | |
| 5927 dst : S3(read); | |
| 5928 DECODE : S0; // any decoder | |
| 5929 ALU : S3; // any alu | |
| 5930 %} | |
| 5931 | |
| 5932 // Long ALU reg operation | |
| 5933 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5934 instruction_count(2); | |
| 5935 dst : S4(write); | |
| 5936 dst : S3(read); | |
| 5937 DECODE : S0(2); // any 2 decoders | |
| 5938 ALU : S3(2); // both alus | |
| 5939 %} | |
| 5940 | |
| 5941 // Integer ALU reg operation using big decoder | |
| 5942 pipe_class ialu_reg_fat(eRegI dst) %{ | |
| 5943 single_instruction; | |
| 5944 dst : S4(write); | |
| 5945 dst : S3(read); | |
| 5946 D0 : S0; // big decoder only | |
| 5947 ALU : S3; // any alu | |
| 5948 %} | |
| 5949 | |
| 5950 // Long ALU reg operation using big decoder | |
| 5951 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5952 instruction_count(2); | |
| 5953 dst : S4(write); | |
| 5954 dst : S3(read); | |
| 5955 D0 : S0(2); // big decoder only; twice | |
| 5956 ALU : S3(2); // any 2 alus | |
| 5957 %} | |
| 5958 | |
| 5959 // Integer ALU reg-reg operation | |
| 5960 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ | |
| 5961 single_instruction; | |
| 5962 dst : S4(write); | |
| 5963 src : S3(read); | |
| 5964 DECODE : S0; // any decoder | |
| 5965 ALU : S3; // any alu | |
| 5966 %} | |
| 5967 | |
| 5968 // Long ALU reg-reg operation | |
| 5969 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5970 instruction_count(2); | |
| 5971 dst : S4(write); | |
| 5972 src : S3(read); | |
| 5973 DECODE : S0(2); // any 2 decoders | |
| 5974 ALU : S3(2); // both alus | |
| 5975 %} | |
| 5976 | |
| 5977 // Integer ALU reg-reg operation | |
| 5978 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ | |
| 5979 single_instruction; | |
| 5980 dst : S4(write); | |
| 5981 src : S3(read); | |
| 5982 D0 : S0; // big decoder only | |
| 5983 ALU : S3; // any alu | |
| 5984 %} | |
| 5985 | |
| 5986 // Long ALU reg-reg operation | |
| 5987 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5988 instruction_count(2); | |
| 5989 dst : S4(write); | |
| 5990 src : S3(read); | |
| 5991 D0 : S0(2); // big decoder only; twice | |
| 5992 ALU : S3(2); // both alus | |
| 5993 %} | |
| 5994 | |
| 5995 // Integer ALU reg-mem operation | |
| 5996 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ | |
| 5997 single_instruction; | |
| 5998 dst : S5(write); | |
| 5999 mem : S3(read); | |
| 6000 D0 : S0; // big decoder only | |
| 6001 ALU : S4; // any alu | |
| 6002 MEM : S3; // any mem | |
| 6003 %} | |
| 6004 | |
| 6005 // Long ALU reg-mem operation | |
| 6006 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 6007 instruction_count(2); | |
| 6008 dst : S5(write); | |
| 6009 mem : S3(read); | |
| 6010 D0 : S0(2); // big decoder only; twice | |
| 6011 ALU : S4(2); // any 2 alus | |
| 6012 MEM : S3(2); // both mems | |
| 6013 %} | |
| 6014 | |
| 6015 // Integer mem operation (prefetch) | |
| 6016 pipe_class ialu_mem(memory mem) | |
| 6017 %{ | |
| 6018 single_instruction; | |
| 6019 mem : S3(read); | |
| 6020 D0 : S0; // big decoder only | |
| 6021 MEM : S3; // any mem | |
| 6022 %} | |
| 6023 | |
| 6024 // Integer Store to Memory | |
| 6025 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ | |
| 6026 single_instruction; | |
| 6027 mem : S3(read); | |
| 6028 src : S5(read); | |
| 6029 D0 : S0; // big decoder only | |
| 6030 ALU : S4; // any alu | |
| 6031 MEM : S3; | |
| 6032 %} | |
| 6033 | |
| 6034 // Long Store to Memory | |
| 6035 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 6036 instruction_count(2); | |
| 6037 mem : S3(read); | |
| 6038 src : S5(read); | |
| 6039 D0 : S0(2); // big decoder only; twice | |
| 6040 ALU : S4(2); // any 2 alus | |
| 6041 MEM : S3(2); // Both mems | |
| 6042 %} | |
| 6043 | |
| 6044 // Integer Store to Memory | |
| 6045 pipe_class ialu_mem_imm(memory mem) %{ | |
| 6046 single_instruction; | |
| 6047 mem : S3(read); | |
| 6048 D0 : S0; // big decoder only | |
| 6049 ALU : S4; // any alu | |
| 6050 MEM : S3; | |
| 6051 %} | |
| 6052 | |
| 6053 // Integer ALU0 reg-reg operation | |
| 6054 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ | |
| 6055 single_instruction; | |
| 6056 dst : S4(write); | |
| 6057 src : S3(read); | |
| 6058 D0 : S0; // Big decoder only | |
| 6059 ALU0 : S3; // only alu0 | |
| 6060 %} | |
| 6061 | |
| 6062 // Integer ALU0 reg-mem operation | |
| 6063 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ | |
| 6064 single_instruction; | |
| 6065 dst : S5(write); | |
| 6066 mem : S3(read); | |
| 6067 D0 : S0; // big decoder only | |
| 6068 ALU0 : S4; // ALU0 only | |
| 6069 MEM : S3; // any mem | |
| 6070 %} | |
| 6071 | |
| 6072 // Integer ALU reg-reg operation | |
| 6073 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ | |
| 6074 single_instruction; | |
| 6075 cr : S4(write); | |
| 6076 src1 : S3(read); | |
| 6077 src2 : S3(read); | |
| 6078 DECODE : S0; // any decoder | |
| 6079 ALU : S3; // any alu | |
| 6080 %} | |
| 6081 | |
| 6082 // Integer ALU reg-imm operation | |
| 6083 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ | |
| 6084 single_instruction; | |
| 6085 cr : S4(write); | |
| 6086 src1 : S3(read); | |
| 6087 DECODE : S0; // any decoder | |
| 6088 ALU : S3; // any alu | |
| 6089 %} | |
| 6090 | |
| 6091 // Integer ALU reg-mem operation | |
| 6092 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ | |
| 6093 single_instruction; | |
| 6094 cr : S4(write); | |
| 6095 src1 : S3(read); | |
| 6096 src2 : S3(read); | |
| 6097 D0 : S0; // big decoder only | |
| 6098 ALU : S4; // any alu | |
| 6099 MEM : S3; | |
| 6100 %} | |
| 6101 | |
| 6102 // Conditional move reg-reg | |
| 6103 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ | |
| 6104 instruction_count(4); | |
| 6105 y : S4(read); | |
| 6106 q : S3(read); | |
| 6107 p : S3(read); | |
| 6108 DECODE : S0(4); // any decoder | |
| 6109 %} | |
| 6110 | |
| 6111 // Conditional move reg-reg | |
| 6112 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 6113 single_instruction; | |
| 6114 dst : S4(write); | |
| 6115 src : S3(read); | |
| 6116 cr : S3(read); | |
| 6117 DECODE : S0; // any decoder | |
| 6118 %} | |
| 6119 | |
| 6120 // Conditional move reg-mem | |
| 6121 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ | |
| 6122 single_instruction; | |
| 6123 dst : S4(write); | |
| 6124 src : S3(read); | |
| 6125 cr : S3(read); | |
| 6126 DECODE : S0; // any decoder | |
| 6127 MEM : S3; | |
| 6128 %} | |
| 6129 | |
| 6130 // Conditional move reg-reg long | |
| 6131 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 6132 single_instruction; | |
| 6133 dst : S4(write); | |
| 6134 src : S3(read); | |
| 6135 cr : S3(read); | |
| 6136 DECODE : S0(2); // any 2 decoders | |
| 6137 %} | |
| 6138 | |
| 6139 // Conditional move double reg-reg | |
| 6140 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ | |
| 6141 single_instruction; | |
| 6142 dst : S4(write); | |
| 6143 src : S3(read); | |
| 6144 cr : S3(read); | |
| 6145 DECODE : S0; // any decoder | |
| 6146 %} | |
| 6147 | |
| 6148 // Float reg-reg operation | |
| 6149 pipe_class fpu_reg(regD dst) %{ | |
| 6150 instruction_count(2); | |
| 6151 dst : S3(read); | |
| 6152 DECODE : S0(2); // any 2 decoders | |
| 6153 FPU : S3; | |
| 6154 %} | |
| 6155 | |
| 6156 // Float reg-reg operation | |
| 6157 pipe_class fpu_reg_reg(regD dst, regD src) %{ | |
| 6158 instruction_count(2); | |
| 6159 dst : S4(write); | |
| 6160 src : S3(read); | |
| 6161 DECODE : S0(2); // any 2 decoders | |
| 6162 FPU : S3; | |
| 6163 %} | |
| 6164 | |
| 6165 // Float reg-reg operation | |
| 6166 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 6167 instruction_count(3); | |
| 6168 dst : S4(write); | |
| 6169 src1 : S3(read); | |
| 6170 src2 : S3(read); | |
| 6171 DECODE : S0(3); // any 3 decoders | |
| 6172 FPU : S3(2); | |
| 6173 %} | |
| 6174 | |
| 6175 // Float reg-reg operation | |
| 6176 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ | |
| 6177 instruction_count(4); | |
| 6178 dst : S4(write); | |
| 6179 src1 : S3(read); | |
| 6180 src2 : S3(read); | |
| 6181 src3 : S3(read); | |
| 6182 DECODE : S0(4); // any 3 decoders | |
| 6183 FPU : S3(2); | |
| 6184 %} | |
| 6185 | |
| 6186 // Float reg-reg operation | |
| 6187 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ | |
| 6188 instruction_count(4); | |
| 6189 dst : S4(write); | |
| 6190 src1 : S3(read); | |
| 6191 src2 : S3(read); | |
| 6192 src3 : S3(read); | |
| 6193 DECODE : S1(3); // any 3 decoders | |
| 6194 D0 : S0; // Big decoder only | |
| 6195 FPU : S3(2); | |
| 6196 MEM : S3; | |
| 6197 %} | |
| 6198 | |
| 6199 // Float reg-mem operation | |
| 6200 pipe_class fpu_reg_mem(regD dst, memory mem) %{ | |
| 6201 instruction_count(2); | |
| 6202 dst : S5(write); | |
| 6203 mem : S3(read); | |
| 6204 D0 : S0; // big decoder only | |
| 6205 DECODE : S1; // any decoder for FPU POP | |
| 6206 FPU : S4; | |
| 6207 MEM : S3; // any mem | |
| 6208 %} | |
| 6209 | |
| 6210 // Float reg-mem operation | |
| 6211 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ | |
| 6212 instruction_count(3); | |
| 6213 dst : S5(write); | |
| 6214 src1 : S3(read); | |
| 6215 mem : S3(read); | |
| 6216 D0 : S0; // big decoder only | |
| 6217 DECODE : S1(2); // any decoder for FPU POP | |
| 6218 FPU : S4; | |
| 6219 MEM : S3; // any mem | |
| 6220 %} | |
| 6221 | |
| 6222 // Float mem-reg operation | |
| 6223 pipe_class fpu_mem_reg(memory mem, regD src) %{ | |
| 6224 instruction_count(2); | |
| 6225 src : S5(read); | |
| 6226 mem : S3(read); | |
| 6227 DECODE : S0; // any decoder for FPU PUSH | |
| 6228 D0 : S1; // big decoder only | |
| 6229 FPU : S4; | |
| 6230 MEM : S3; // any mem | |
| 6231 %} | |
| 6232 | |
| 6233 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ | |
| 6234 instruction_count(3); | |
| 6235 src1 : S3(read); | |
| 6236 src2 : S3(read); | |
| 6237 mem : S3(read); | |
| 6238 DECODE : S0(2); // any decoder for FPU PUSH | |
| 6239 D0 : S1; // big decoder only | |
| 6240 FPU : S4; | |
| 6241 MEM : S3; // any mem | |
| 6242 %} | |
| 6243 | |
| 6244 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ | |
| 6245 instruction_count(3); | |
| 6246 src1 : S3(read); | |
| 6247 src2 : S3(read); | |
| 6248 mem : S4(read); | |
| 6249 DECODE : S0; // any decoder for FPU PUSH | |
| 6250 D0 : S0(2); // big decoder only | |
| 6251 FPU : S4; | |
| 6252 MEM : S3(2); // any mem | |
| 6253 %} | |
| 6254 | |
| 6255 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 6256 instruction_count(2); | |
| 6257 src1 : S3(read); | |
| 6258 dst : S4(read); | |
| 6259 D0 : S0(2); // big decoder only | |
| 6260 MEM : S3(2); // any mem | |
| 6261 %} | |
| 6262 | |
| 6263 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 6264 instruction_count(3); | |
| 6265 src1 : S3(read); | |
| 6266 src2 : S3(read); | |
| 6267 dst : S4(read); | |
| 6268 D0 : S0(3); // big decoder only | |
| 6269 FPU : S4; | |
| 6270 MEM : S3(3); // any mem | |
| 6271 %} | |
| 6272 | |
| 6273 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ | |
| 6274 instruction_count(3); | |
| 6275 src1 : S4(read); | |
| 6276 mem : S4(read); | |
| 6277 DECODE : S0; // any decoder for FPU PUSH | |
| 6278 D0 : S0(2); // big decoder only | |
| 6279 FPU : S4; | |
| 6280 MEM : S3(2); // any mem | |
| 6281 %} | |
| 6282 | |
| 6283 // Float load constant | |
| 6284 pipe_class fpu_reg_con(regD dst) %{ | |
| 6285 instruction_count(2); | |
| 6286 dst : S5(write); | |
| 6287 D0 : S0; // big decoder only for the load | |
| 6288 DECODE : S1; // any decoder for FPU POP | |
| 6289 FPU : S4; | |
| 6290 MEM : S3; // any mem | |
| 6291 %} | |
| 6292 | |
| 6293 // Float load constant | |
| 6294 pipe_class fpu_reg_reg_con(regD dst, regD src) %{ | |
| 6295 instruction_count(3); | |
| 6296 dst : S5(write); | |
| 6297 src : S3(read); | |
| 6298 D0 : S0; // big decoder only for the load | |
| 6299 DECODE : S1(2); // any decoder for FPU POP | |
| 6300 FPU : S4; | |
| 6301 MEM : S3; // any mem | |
| 6302 %} | |
| 6303 | |
| 6304 // UnConditional branch | |
| 6305 pipe_class pipe_jmp( label labl ) %{ | |
| 6306 single_instruction; | |
| 6307 BR : S3; | |
| 6308 %} | |
| 6309 | |
| 6310 // Conditional branch | |
| 6311 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 6312 single_instruction; | |
| 6313 cr : S1(read); | |
| 6314 BR : S3; | |
| 6315 %} | |
| 6316 | |
| 6317 // Allocation idiom | |
| 6318 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 6319 instruction_count(1); force_serialization; | |
| 6320 fixed_latency(6); | |
| 6321 heap_ptr : S3(read); | |
| 6322 DECODE : S0(3); | |
| 6323 D0 : S2; | |
| 6324 MEM : S3; | |
| 6325 ALU : S3(2); | |
| 6326 dst : S5(write); | |
| 6327 BR : S5; | |
| 6328 %} | |
| 6329 | |
| 6330 // Generic big/slow expanded idiom | |
| 6331 pipe_class pipe_slow( ) %{ | |
| 6332 instruction_count(10); multiple_bundles; force_serialization; | |
| 6333 fixed_latency(100); | |
| 6334 D0 : S0(2); | |
| 6335 MEM : S3(2); | |
| 6336 %} | |
| 6337 | |
| 6338 // The real do-nothing guy | |
| 6339 pipe_class empty( ) %{ | |
| 6340 instruction_count(0); | |
| 6341 %} | |
| 6342 | |
| 6343 // Define the class for the Nop node | |
| 6344 define %{ | |
| 6345 MachNop = empty; | |
| 6346 %} | |
| 6347 | |
| 6348 %} | |
| 6349 | |
| 6350 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6351 // | |
| 6352 // match -- States which machine-independent subtree may be replaced | |
| 6353 // by this instruction. | |
| 6354 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6355 // selection to identify a minimum cost tree of machine | |
| 6356 // instructions that matches a tree of machine-independent | |
| 6357 // instructions. | |
| 6358 // format -- A string providing the disassembly for this instruction. | |
| 6359 // The value of an instruction's operand may be inserted | |
| 6360 // by referring to it with a '$' prefix. | |
| 6361 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6362 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6363 // respectively. The primary opcode is commonly used to | |
| 6364 // indicate the type of machine instruction, while secondary | |
| 6365 // and tertiary are often used for prefix options or addressing | |
| 6366 // modes. | |
| 6367 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6368 // name must have been defined in an 'enc_class' specification | |
| 6369 // in the encode section of the architecture description. | |
| 6370 | |
| 6371 //----------BSWAP-Instruction-------------------------------------------------- | |
| 6372 instruct bytes_reverse_int(eRegI dst) %{ | |
| 6373 match(Set dst (ReverseBytesI dst)); | |
| 6374 | |
| 6375 format %{ "BSWAP $dst" %} | |
| 6376 opcode(0x0F, 0xC8); | |
| 6377 ins_encode( OpcP, OpcSReg(dst) ); | |
| 6378 ins_pipe( ialu_reg ); | |
| 6379 %} | |
| 6380 | |
| 6381 instruct bytes_reverse_long(eRegL dst) %{ | |
| 6382 match(Set dst (ReverseBytesL dst)); | |
| 6383 | |
| 6384 format %{ "BSWAP $dst.lo\n\t" | |
| 6385 "BSWAP $dst.hi\n\t" | |
| 6386 "XCHG $dst.lo $dst.hi" %} | |
| 6387 | |
| 6388 ins_cost(125); | |
| 6389 ins_encode( bswap_long_bytes(dst) ); | |
| 6390 ins_pipe( ialu_reg_reg); | |
| 6391 %} | |
| 6392 | |
| 6393 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6394 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6395 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6396 instruct popCountI(eRegI dst, eRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6397 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6398 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6399 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6400 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6401 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6402 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6403 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6404 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6405 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6406 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6407 instruct popCountI_mem(eRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6408 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6409 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6410 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6411 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6412 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6413 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6414 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6415 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6416 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6417 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6418 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6419 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6420 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6421 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6422 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6423 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6424 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6425 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6426 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6427 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6428 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6429 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6430 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6431 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6432 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6433 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6434 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6435 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6436 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6437 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6438 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6439 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6440 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6441 format %{ "POPCNT $dst, $mem\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6442 "POPCNT $tmp, $mem+4\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6443 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6444 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6445 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6446 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6447 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6448 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6449 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6450 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6451 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6452 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6453 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6454 |
| 0 | 6455 //----------Load/Store/Move Instructions--------------------------------------- |
| 6456 //----------Load Instructions-------------------------------------------------- | |
| 6457 // Load Byte (8bit signed) | |
| 6458 instruct loadB(xRegI dst, memory mem) %{ | |
| 6459 match(Set dst (LoadB mem)); | |
| 6460 | |
| 6461 ins_cost(125); | |
| 624 | 6462 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 6463 | |
| 6464 ins_encode %{ | |
| 6465 __ movsbl($dst$$Register, $mem$$Address); | |
| 6466 %} | |
| 6467 | |
| 6468 ins_pipe(ialu_reg_mem); | |
| 6469 %} | |
| 6470 | |
| 6471 // Load Byte (8bit signed) into Long Register | |
| 6472 instruct loadB2L(eRegL dst, memory mem) %{ | |
| 6473 match(Set dst (ConvI2L (LoadB mem))); | |
| 6474 | |
| 6475 ins_cost(375); | |
| 6476 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 6477 "MOV $dst.hi,$dst.lo\n\t" | |
| 6478 "SAR $dst.hi,7" %} | |
| 6479 | |
| 6480 ins_encode %{ | |
| 6481 __ movsbl($dst$$Register, $mem$$Address); | |
| 6482 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6483 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 6484 %} | |
| 6485 | |
| 6486 ins_pipe(ialu_reg_mem); | |
| 6487 %} | |
| 6488 | |
| 6489 // Load Unsigned Byte (8bit UNsigned) | |
| 6490 instruct loadUB(xRegI dst, memory mem) %{ | |
| 6491 match(Set dst (LoadUB mem)); | |
| 0 | 6492 |
| 6493 ins_cost(125); | |
| 624 | 6494 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 6495 | |
| 6496 ins_encode %{ | |
| 6497 __ movzbl($dst$$Register, $mem$$Address); | |
| 6498 %} | |
| 6499 | |
| 6500 ins_pipe(ialu_reg_mem); | |
| 6501 %} | |
| 6502 | |
| 6503 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 6504 instruct loadUB2L(eRegL dst, memory mem) | |
| 6505 %{ | |
| 6506 match(Set dst (ConvI2L (LoadUB mem))); | |
| 6507 | |
| 6508 ins_cost(250); | |
| 6509 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 6510 "XOR $dst.hi,$dst.hi" %} | |
| 6511 | |
| 6512 ins_encode %{ | |
| 6513 __ movzbl($dst$$Register, $mem$$Address); | |
| 6514 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6515 %} | |
| 6516 | |
| 6517 ins_pipe(ialu_reg_mem); | |
| 6518 %} | |
| 6519 | |
| 6520 // Load Short (16bit signed) | |
| 6521 instruct loadS(eRegI dst, memory mem) %{ | |
| 6522 match(Set dst (LoadS mem)); | |
| 6523 | |
| 6524 ins_cost(125); | |
| 6525 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 6526 | |
| 6527 ins_encode %{ | |
| 6528 __ movswl($dst$$Register, $mem$$Address); | |
| 6529 %} | |
| 6530 | |
| 6531 ins_pipe(ialu_reg_mem); | |
| 6532 %} | |
| 6533 | |
| 6534 // Load Short (16bit signed) into Long Register | |
| 6535 instruct loadS2L(eRegL dst, memory mem) %{ | |
| 6536 match(Set dst (ConvI2L (LoadS mem))); | |
| 6537 | |
| 6538 ins_cost(375); | |
| 6539 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 6540 "MOV $dst.hi,$dst.lo\n\t" | |
| 6541 "SAR $dst.hi,15" %} | |
| 6542 | |
| 6543 ins_encode %{ | |
| 6544 __ movswl($dst$$Register, $mem$$Address); | |
| 6545 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6546 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 6547 %} | |
| 6548 | |
| 6549 ins_pipe(ialu_reg_mem); | |
| 0 | 6550 %} |
| 6551 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6552 // Load Unsigned Short/Char (16bit unsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6553 instruct loadUS(eRegI dst, memory mem) %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6554 match(Set dst (LoadUS mem)); |
| 0 | 6555 |
| 6556 ins_cost(125); | |
| 624 | 6557 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 6558 | |
| 6559 ins_encode %{ | |
| 6560 __ movzwl($dst$$Register, $mem$$Address); | |
| 6561 %} | |
| 6562 | |
| 6563 ins_pipe(ialu_reg_mem); | |
| 6564 %} | |
| 6565 | |
| 6566 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register | |
| 6567 instruct loadUS2L(eRegL dst, memory mem) | |
| 6568 %{ | |
| 6569 match(Set dst (ConvI2L (LoadUS mem))); | |
| 6570 | |
| 6571 ins_cost(250); | |
| 6572 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 6573 "XOR $dst.hi,$dst.hi" %} | |
| 6574 | |
| 6575 ins_encode %{ | |
| 6576 __ movzwl($dst$$Register, $mem$$Address); | |
| 6577 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6578 %} | |
| 6579 | |
| 6580 ins_pipe(ialu_reg_mem); | |
| 0 | 6581 %} |
| 6582 | |
| 6583 // Load Integer | |
| 6584 instruct loadI(eRegI dst, memory mem) %{ | |
| 6585 match(Set dst (LoadI mem)); | |
| 6586 | |
| 6587 ins_cost(125); | |
| 624 | 6588 format %{ "MOV $dst,$mem\t# int" %} |
| 6589 | |
| 6590 ins_encode %{ | |
| 6591 __ movl($dst$$Register, $mem$$Address); | |
| 6592 %} | |
| 6593 | |
| 6594 ins_pipe(ialu_reg_mem); | |
| 6595 %} | |
| 6596 | |
| 6597 // Load Integer into Long Register | |
| 6598 instruct loadI2L(eRegL dst, memory mem) %{ | |
| 6599 match(Set dst (ConvI2L (LoadI mem))); | |
| 6600 | |
| 6601 ins_cost(375); | |
| 6602 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6603 "MOV $dst.hi,$dst.lo\n\t" | |
| 6604 "SAR $dst.hi,31" %} | |
| 6605 | |
| 6606 ins_encode %{ | |
| 6607 __ movl($dst$$Register, $mem$$Address); | |
| 6608 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6609 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6610 %} | |
| 6611 | |
| 6612 ins_pipe(ialu_reg_mem); | |
| 6613 %} | |
| 6614 | |
| 6615 // Load Unsigned Integer into Long Register | |
| 6616 instruct loadUI2L(eRegL dst, memory mem) %{ | |
| 6617 match(Set dst (LoadUI2L mem)); | |
| 6618 | |
| 6619 ins_cost(250); | |
| 6620 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6621 "XOR $dst.hi,$dst.hi" %} | |
| 6622 | |
| 6623 ins_encode %{ | |
| 6624 __ movl($dst$$Register, $mem$$Address); | |
| 6625 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6626 %} | |
| 6627 | |
| 6628 ins_pipe(ialu_reg_mem); | |
| 0 | 6629 %} |
| 6630 | |
| 6631 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6632 // register to ESI | |
| 6633 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6634 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6635 match(Set dst (LoadL mem)); | |
| 6636 | |
| 6637 ins_cost(250); | |
| 624 | 6638 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6639 "MOV $dst.hi,$mem+4" %} |
| 624 | 6640 |
| 6641 ins_encode %{ | |
| 6642 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); | |
| 6643 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); | |
| 6644 __ movl($dst$$Register, Amemlo); | |
| 6645 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6646 %} | |
| 6647 | |
| 6648 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6649 %} |
| 6650 | |
| 6651 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6652 // then store it down to the stack and reload on the int | |
| 6653 // side. | |
| 6654 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6655 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6656 match(Set dst (LoadL mem)); | |
| 6657 | |
| 6658 ins_cost(200); | |
| 6659 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6660 "FISTp $dst" %} | |
| 6661 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6662 ins_pipe( fpu_reg_mem ); | |
| 6663 %} | |
| 6664 | |
| 6665 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ | |
| 6666 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6667 match(Set dst (LoadL mem)); | |
| 6668 effect(TEMP tmp); | |
| 6669 ins_cost(180); | |
| 6670 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6671 "MOVSD $dst,$tmp" %} | |
| 6672 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 6673 ins_pipe( pipe_slow ); | |
| 6674 %} | |
| 6675 | |
| 6676 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ | |
| 6677 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6678 match(Set dst (LoadL mem)); | |
| 6679 effect(TEMP tmp); | |
| 6680 ins_cost(160); | |
| 6681 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6682 "MOVD $dst.lo,$tmp\n\t" | |
| 6683 "PSRLQ $tmp,32\n\t" | |
| 6684 "MOVD $dst.hi,$tmp" %} | |
| 6685 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 6686 ins_pipe( pipe_slow ); | |
| 6687 %} | |
| 6688 | |
| 6689 // Load Range | |
| 6690 instruct loadRange(eRegI dst, memory mem) %{ | |
| 6691 match(Set dst (LoadRange mem)); | |
| 6692 | |
| 6693 ins_cost(125); | |
| 6694 format %{ "MOV $dst,$mem" %} | |
| 6695 opcode(0x8B); | |
| 6696 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6697 ins_pipe( ialu_reg_mem ); | |
| 6698 %} | |
| 6699 | |
| 6700 | |
| 6701 // Load Pointer | |
| 6702 instruct loadP(eRegP dst, memory mem) %{ | |
| 6703 match(Set dst (LoadP mem)); | |
| 6704 | |
| 6705 ins_cost(125); | |
| 6706 format %{ "MOV $dst,$mem" %} | |
| 6707 opcode(0x8B); | |
| 6708 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6709 ins_pipe( ialu_reg_mem ); | |
| 6710 %} | |
| 6711 | |
| 6712 // Load Klass Pointer | |
| 6713 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6714 match(Set dst (LoadKlass mem)); | |
| 6715 | |
| 6716 ins_cost(125); | |
| 6717 format %{ "MOV $dst,$mem" %} | |
| 6718 opcode(0x8B); | |
| 6719 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6720 ins_pipe( ialu_reg_mem ); | |
| 6721 %} | |
| 6722 | |
| 6723 // Load Double | |
| 6724 instruct loadD(regD dst, memory mem) %{ | |
| 6725 predicate(UseSSE<=1); | |
| 6726 match(Set dst (LoadD mem)); | |
| 6727 | |
| 6728 ins_cost(150); | |
| 6729 format %{ "FLD_D ST,$mem\n\t" | |
| 6730 "FSTP $dst" %} | |
| 6731 opcode(0xDD); /* DD /0 */ | |
| 6732 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6733 Pop_Reg_D(dst) ); | |
| 6734 ins_pipe( fpu_reg_mem ); | |
| 6735 %} | |
| 6736 | |
| 6737 // Load Double to XMM | |
| 6738 instruct loadXD(regXD dst, memory mem) %{ | |
| 6739 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 6740 match(Set dst (LoadD mem)); | |
| 6741 ins_cost(145); | |
| 6742 format %{ "MOVSD $dst,$mem" %} | |
| 6743 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6744 ins_pipe( pipe_slow ); | |
| 6745 %} | |
| 6746 | |
| 6747 instruct loadXD_partial(regXD dst, memory mem) %{ | |
| 6748 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 6749 match(Set dst (LoadD mem)); | |
| 6750 ins_cost(145); | |
| 6751 format %{ "MOVLPD $dst,$mem" %} | |
| 6752 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); | |
| 6753 ins_pipe( pipe_slow ); | |
| 6754 %} | |
| 6755 | |
| 6756 // Load to XMM register (single-precision floating point) | |
| 6757 // MOVSS instruction | |
| 6758 instruct loadX(regX dst, memory mem) %{ | |
| 6759 predicate(UseSSE>=1); | |
| 6760 match(Set dst (LoadF mem)); | |
| 6761 ins_cost(145); | |
| 6762 format %{ "MOVSS $dst,$mem" %} | |
| 6763 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6764 ins_pipe( pipe_slow ); | |
| 6765 %} | |
| 6766 | |
| 6767 // Load Float | |
| 6768 instruct loadF(regF dst, memory mem) %{ | |
| 6769 predicate(UseSSE==0); | |
| 6770 match(Set dst (LoadF mem)); | |
| 6771 | |
| 6772 ins_cost(150); | |
| 6773 format %{ "FLD_S ST,$mem\n\t" | |
| 6774 "FSTP $dst" %} | |
| 6775 opcode(0xD9); /* D9 /0 */ | |
| 6776 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6777 Pop_Reg_F(dst) ); | |
| 6778 ins_pipe( fpu_reg_mem ); | |
| 6779 %} | |
| 6780 | |
| 6781 // Load Aligned Packed Byte to XMM register | |
| 6782 instruct loadA8B(regXD dst, memory mem) %{ | |
| 6783 predicate(UseSSE>=1); | |
| 6784 match(Set dst (Load8B mem)); | |
| 6785 ins_cost(125); | |
| 6786 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6787 ins_encode( movq_ld(dst, mem)); | |
| 6788 ins_pipe( pipe_slow ); | |
| 6789 %} | |
| 6790 | |
| 6791 // Load Aligned Packed Short to XMM register | |
| 6792 instruct loadA4S(regXD dst, memory mem) %{ | |
| 6793 predicate(UseSSE>=1); | |
| 6794 match(Set dst (Load4S mem)); | |
| 6795 ins_cost(125); | |
| 6796 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 6797 ins_encode( movq_ld(dst, mem)); | |
| 6798 ins_pipe( pipe_slow ); | |
| 6799 %} | |
| 6800 | |
| 6801 // Load Aligned Packed Char to XMM register | |
| 6802 instruct loadA4C(regXD dst, memory mem) %{ | |
| 6803 predicate(UseSSE>=1); | |
| 6804 match(Set dst (Load4C mem)); | |
| 6805 ins_cost(125); | |
| 6806 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 6807 ins_encode( movq_ld(dst, mem)); | |
| 6808 ins_pipe( pipe_slow ); | |
| 6809 %} | |
| 6810 | |
| 6811 // Load Aligned Packed Integer to XMM register | |
| 6812 instruct load2IU(regXD dst, memory mem) %{ | |
| 6813 predicate(UseSSE>=1); | |
| 6814 match(Set dst (Load2I mem)); | |
| 6815 ins_cost(125); | |
| 6816 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 6817 ins_encode( movq_ld(dst, mem)); | |
| 6818 ins_pipe( pipe_slow ); | |
| 6819 %} | |
| 6820 | |
| 6821 // Load Aligned Packed Single to XMM | |
| 6822 instruct loadA2F(regXD dst, memory mem) %{ | |
| 6823 predicate(UseSSE>=1); | |
| 6824 match(Set dst (Load2F mem)); | |
| 6825 ins_cost(145); | |
| 6826 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 6827 ins_encode( movq_ld(dst, mem)); | |
| 6828 ins_pipe( pipe_slow ); | |
| 6829 %} | |
| 6830 | |
| 6831 // Load Effective Address | |
| 6832 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 6833 match(Set dst mem); | |
| 6834 | |
| 6835 ins_cost(110); | |
| 6836 format %{ "LEA $dst,$mem" %} | |
| 6837 opcode(0x8D); | |
| 6838 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6839 ins_pipe( ialu_reg_reg_fat ); | |
| 6840 %} | |
| 6841 | |
| 6842 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 6843 match(Set dst mem); | |
| 6844 | |
| 6845 ins_cost(110); | |
| 6846 format %{ "LEA $dst,$mem" %} | |
| 6847 opcode(0x8D); | |
| 6848 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6849 ins_pipe( ialu_reg_reg_fat ); | |
| 6850 %} | |
| 6851 | |
| 6852 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 6853 match(Set dst mem); | |
| 6854 | |
| 6855 ins_cost(110); | |
| 6856 format %{ "LEA $dst,$mem" %} | |
| 6857 opcode(0x8D); | |
| 6858 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6859 ins_pipe( ialu_reg_reg_fat ); | |
| 6860 %} | |
| 6861 | |
| 6862 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 6863 match(Set dst mem); | |
| 6864 | |
| 6865 ins_cost(110); | |
| 6866 format %{ "LEA $dst,$mem" %} | |
| 6867 opcode(0x8D); | |
| 6868 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6869 ins_pipe( ialu_reg_reg_fat ); | |
| 6870 %} | |
| 6871 | |
| 6872 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 6873 match(Set dst mem); | |
| 6874 | |
| 6875 ins_cost(110); | |
| 6876 format %{ "LEA $dst,$mem" %} | |
| 6877 opcode(0x8D); | |
| 6878 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6879 ins_pipe( ialu_reg_reg_fat ); | |
| 6880 %} | |
| 6881 | |
| 6882 // Load Constant | |
| 6883 instruct loadConI(eRegI dst, immI src) %{ | |
| 6884 match(Set dst src); | |
| 6885 | |
| 6886 format %{ "MOV $dst,$src" %} | |
| 6887 ins_encode( LdImmI(dst, src) ); | |
| 6888 ins_pipe( ialu_reg_fat ); | |
| 6889 %} | |
| 6890 | |
| 6891 // Load Constant zero | |
| 6892 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ | |
| 6893 match(Set dst src); | |
| 6894 effect(KILL cr); | |
| 6895 | |
| 6896 ins_cost(50); | |
| 6897 format %{ "XOR $dst,$dst" %} | |
| 6898 opcode(0x33); /* + rd */ | |
| 6899 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 6900 ins_pipe( ialu_reg ); | |
| 6901 %} | |
| 6902 | |
| 6903 instruct loadConP(eRegP dst, immP src) %{ | |
| 6904 match(Set dst src); | |
| 6905 | |
| 6906 format %{ "MOV $dst,$src" %} | |
| 6907 opcode(0xB8); /* + rd */ | |
| 6908 ins_encode( LdImmP(dst, src) ); | |
| 6909 ins_pipe( ialu_reg_fat ); | |
| 6910 %} | |
| 6911 | |
| 6912 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 6913 match(Set dst src); | |
| 6914 effect(KILL cr); | |
| 6915 ins_cost(200); | |
| 6916 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 6917 "MOV $dst.hi,$src.hi" %} | |
| 6918 opcode(0xB8); | |
| 6919 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 6920 ins_pipe( ialu_reg_long_fat ); | |
| 6921 %} | |
| 6922 | |
| 6923 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 6924 match(Set dst src); | |
| 6925 effect(KILL cr); | |
| 6926 ins_cost(150); | |
| 6927 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 6928 "XOR $dst.hi,$dst.hi" %} | |
| 6929 opcode(0x33,0x33); | |
| 6930 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 6931 ins_pipe( ialu_reg_long ); | |
| 6932 %} | |
| 6933 | |
| 6934 // The instruction usage is guarded by predicate in operand immF(). | |
| 6935 instruct loadConF(regF dst, immF src) %{ | |
| 6936 match(Set dst src); | |
| 6937 ins_cost(125); | |
| 6938 | |
| 6939 format %{ "FLD_S ST,$src\n\t" | |
| 6940 "FSTP $dst" %} | |
| 6941 opcode(0xD9, 0x00); /* D9 /0 */ | |
| 6942 ins_encode(LdImmF(src), Pop_Reg_F(dst) ); | |
| 6943 ins_pipe( fpu_reg_con ); | |
| 6944 %} | |
| 6945 | |
| 6946 // The instruction usage is guarded by predicate in operand immXF(). | |
| 6947 instruct loadConX(regX dst, immXF con) %{ | |
| 6948 match(Set dst con); | |
| 6949 ins_cost(125); | |
| 6950 format %{ "MOVSS $dst,[$con]" %} | |
| 6951 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con)); | |
| 6952 ins_pipe( pipe_slow ); | |
| 6953 %} | |
| 6954 | |
| 6955 // The instruction usage is guarded by predicate in operand immXF0(). | |
| 6956 instruct loadConX0(regX dst, immXF0 src) %{ | |
| 6957 match(Set dst src); | |
| 6958 ins_cost(100); | |
| 6959 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 6960 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 6961 ins_pipe( pipe_slow ); | |
| 6962 %} | |
| 6963 | |
| 6964 // The instruction usage is guarded by predicate in operand immD(). | |
| 6965 instruct loadConD(regD dst, immD src) %{ | |
| 6966 match(Set dst src); | |
| 6967 ins_cost(125); | |
| 6968 | |
| 6969 format %{ "FLD_D ST,$src\n\t" | |
| 6970 "FSTP $dst" %} | |
| 6971 ins_encode(LdImmD(src), Pop_Reg_D(dst) ); | |
| 6972 ins_pipe( fpu_reg_con ); | |
| 6973 %} | |
| 6974 | |
| 6975 // The instruction usage is guarded by predicate in operand immXD(). | |
| 6976 instruct loadConXD(regXD dst, immXD con) %{ | |
| 6977 match(Set dst con); | |
| 6978 ins_cost(125); | |
| 6979 format %{ "MOVSD $dst,[$con]" %} | |
| 6980 ins_encode(load_conXD(dst, con)); | |
| 6981 ins_pipe( pipe_slow ); | |
| 6982 %} | |
| 6983 | |
| 6984 // The instruction usage is guarded by predicate in operand immXD0(). | |
| 6985 instruct loadConXD0(regXD dst, immXD0 src) %{ | |
| 6986 match(Set dst src); | |
| 6987 ins_cost(100); | |
| 6988 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 6989 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 6990 ins_pipe( pipe_slow ); | |
| 6991 %} | |
| 6992 | |
| 6993 // Load Stack Slot | |
| 6994 instruct loadSSI(eRegI dst, stackSlotI src) %{ | |
| 6995 match(Set dst src); | |
| 6996 ins_cost(125); | |
| 6997 | |
| 6998 format %{ "MOV $dst,$src" %} | |
| 6999 opcode(0x8B); | |
| 7000 ins_encode( OpcP, RegMem(dst,src)); | |
| 7001 ins_pipe( ialu_reg_mem ); | |
| 7002 %} | |
| 7003 | |
| 7004 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 7005 match(Set dst src); | |
| 7006 | |
| 7007 ins_cost(200); | |
| 7008 format %{ "MOV $dst,$src.lo\n\t" | |
| 7009 "MOV $dst+4,$src.hi" %} | |
| 7010 opcode(0x8B, 0x8B); | |
| 7011 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 7012 ins_pipe( ialu_mem_long_reg ); | |
| 7013 %} | |
| 7014 | |
| 7015 // Load Stack Slot | |
| 7016 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 7017 match(Set dst src); | |
| 7018 ins_cost(125); | |
| 7019 | |
| 7020 format %{ "MOV $dst,$src" %} | |
| 7021 opcode(0x8B); | |
| 7022 ins_encode( OpcP, RegMem(dst,src)); | |
| 7023 ins_pipe( ialu_reg_mem ); | |
| 7024 %} | |
| 7025 | |
| 7026 // Load Stack Slot | |
| 7027 instruct loadSSF(regF dst, stackSlotF src) %{ | |
| 7028 match(Set dst src); | |
| 7029 ins_cost(125); | |
| 7030 | |
| 7031 format %{ "FLD_S $src\n\t" | |
| 7032 "FSTP $dst" %} | |
| 7033 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 7034 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7035 Pop_Reg_F(dst) ); | |
| 7036 ins_pipe( fpu_reg_mem ); | |
| 7037 %} | |
| 7038 | |
| 7039 // Load Stack Slot | |
| 7040 instruct loadSSD(regD dst, stackSlotD src) %{ | |
| 7041 match(Set dst src); | |
| 7042 ins_cost(125); | |
| 7043 | |
| 7044 format %{ "FLD_D $src\n\t" | |
| 7045 "FSTP $dst" %} | |
| 7046 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 7047 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7048 Pop_Reg_D(dst) ); | |
| 7049 ins_pipe( fpu_reg_mem ); | |
| 7050 %} | |
| 7051 | |
| 7052 // Prefetch instructions. | |
| 7053 // Must be safe to execute with invalid address (cannot fault). | |
| 7054 | |
| 7055 instruct prefetchr0( memory mem ) %{ | |
| 7056 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7057 match(PrefetchRead mem); | |
| 7058 ins_cost(0); | |
| 7059 size(0); | |
| 7060 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 7061 ins_encode(); | |
| 7062 ins_pipe(empty); | |
| 7063 %} | |
| 7064 | |
| 7065 instruct prefetchr( memory mem ) %{ | |
| 7066 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); | |
| 7067 match(PrefetchRead mem); | |
| 7068 ins_cost(100); | |
| 7069 | |
| 7070 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 7071 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ | |
| 7072 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7073 ins_pipe(ialu_mem); | |
| 7074 %} | |
| 7075 | |
| 7076 instruct prefetchrNTA( memory mem ) %{ | |
| 7077 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 7078 match(PrefetchRead mem); | |
| 7079 ins_cost(100); | |
| 7080 | |
| 7081 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 7082 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7083 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7084 ins_pipe(ialu_mem); | |
| 7085 %} | |
| 7086 | |
| 7087 instruct prefetchrT0( memory mem ) %{ | |
| 7088 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 7089 match(PrefetchRead mem); | |
| 7090 ins_cost(100); | |
| 7091 | |
| 7092 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 7093 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7094 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7095 ins_pipe(ialu_mem); | |
| 7096 %} | |
| 7097 | |
| 7098 instruct prefetchrT2( memory mem ) %{ | |
| 7099 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 7100 match(PrefetchRead mem); | |
| 7101 ins_cost(100); | |
| 7102 | |
| 7103 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 7104 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7105 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7106 ins_pipe(ialu_mem); | |
| 7107 %} | |
| 7108 | |
| 7109 instruct prefetchw0( memory mem ) %{ | |
| 7110 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7111 match(PrefetchWrite mem); | |
| 7112 ins_cost(0); | |
| 7113 size(0); | |
| 7114 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 7115 ins_encode(); | |
| 7116 ins_pipe(empty); | |
| 7117 %} | |
| 7118 | |
| 7119 instruct prefetchw( memory mem ) %{ | |
| 7120 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); | |
| 7121 match( PrefetchWrite mem ); | |
| 7122 ins_cost(100); | |
| 7123 | |
| 7124 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 7125 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 7126 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7127 ins_pipe(ialu_mem); | |
| 7128 %} | |
| 7129 | |
| 7130 instruct prefetchwNTA( memory mem ) %{ | |
| 7131 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 7132 match(PrefetchWrite mem); | |
| 7133 ins_cost(100); | |
| 7134 | |
| 7135 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 7136 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7137 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7138 ins_pipe(ialu_mem); | |
| 7139 %} | |
| 7140 | |
| 7141 instruct prefetchwT0( memory mem ) %{ | |
| 7142 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 7143 match(PrefetchWrite mem); | |
| 7144 ins_cost(100); | |
| 7145 | |
| 7146 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} | |
| 7147 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7148 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7149 ins_pipe(ialu_mem); | |
| 7150 %} | |
| 7151 | |
| 7152 instruct prefetchwT2( memory mem ) %{ | |
| 7153 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 7154 match(PrefetchWrite mem); | |
| 7155 ins_cost(100); | |
| 7156 | |
| 7157 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} | |
| 7158 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7159 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7160 ins_pipe(ialu_mem); | |
| 7161 %} | |
| 7162 | |
| 7163 //----------Store Instructions------------------------------------------------- | |
| 7164 | |
| 7165 // Store Byte | |
| 7166 instruct storeB(memory mem, xRegI src) %{ | |
| 7167 match(Set mem (StoreB mem src)); | |
| 7168 | |
| 7169 ins_cost(125); | |
| 7170 format %{ "MOV8 $mem,$src" %} | |
| 7171 opcode(0x88); | |
| 7172 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7173 ins_pipe( ialu_mem_reg ); | |
| 7174 %} | |
| 7175 | |
| 7176 // Store Char/Short | |
| 7177 instruct storeC(memory mem, eRegI src) %{ | |
| 7178 match(Set mem (StoreC mem src)); | |
| 7179 | |
| 7180 ins_cost(125); | |
| 7181 format %{ "MOV16 $mem,$src" %} | |
| 7182 opcode(0x89, 0x66); | |
| 7183 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 7184 ins_pipe( ialu_mem_reg ); | |
| 7185 %} | |
| 7186 | |
| 7187 // Store Integer | |
| 7188 instruct storeI(memory mem, eRegI src) %{ | |
| 7189 match(Set mem (StoreI mem src)); | |
| 7190 | |
| 7191 ins_cost(125); | |
| 7192 format %{ "MOV $mem,$src" %} | |
| 7193 opcode(0x89); | |
| 7194 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7195 ins_pipe( ialu_mem_reg ); | |
| 7196 %} | |
| 7197 | |
| 7198 // Store Long | |
| 7199 instruct storeL(long_memory mem, eRegL src) %{ | |
| 7200 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 7201 match(Set mem (StoreL mem src)); | |
| 7202 | |
| 7203 ins_cost(200); | |
| 7204 format %{ "MOV $mem,$src.lo\n\t" | |
| 7205 "MOV $mem+4,$src.hi" %} | |
| 7206 opcode(0x89, 0x89); | |
| 7207 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 7208 ins_pipe( ialu_mem_long_reg ); | |
| 7209 %} | |
| 7210 | |
| 7211 // Volatile Store Long. Must be atomic, so move it into | |
| 7212 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 7213 // target address before the store (for null-ptr checks) | |
| 7214 // so the memory operand is used twice in the encoding. | |
| 7215 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 7216 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7217 match(Set mem (StoreL mem src)); | |
| 7218 effect( KILL cr ); | |
| 7219 ins_cost(400); | |
| 7220 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7221 "FILD $src\n\t" | |
| 7222 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 7223 opcode(0x3B); | |
| 7224 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 7225 ins_pipe( fpu_reg_mem ); | |
| 7226 %} | |
| 7227 | |
| 7228 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ | |
| 7229 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7230 match(Set mem (StoreL mem src)); | |
| 7231 effect( TEMP tmp, KILL cr ); | |
| 7232 ins_cost(380); | |
| 7233 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7234 "MOVSD $tmp,$src\n\t" | |
| 7235 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7236 opcode(0x3B); | |
| 7237 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); | |
| 7238 ins_pipe( pipe_slow ); | |
| 7239 %} | |
| 7240 | |
| 7241 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ | |
| 7242 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7243 match(Set mem (StoreL mem src)); | |
| 7244 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 7245 ins_cost(360); | |
| 7246 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7247 "MOVD $tmp,$src.lo\n\t" | |
| 7248 "MOVD $tmp2,$src.hi\n\t" | |
| 7249 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 7250 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7251 opcode(0x3B); | |
| 7252 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); | |
| 7253 ins_pipe( pipe_slow ); | |
| 7254 %} | |
| 7255 | |
| 7256 // Store Pointer; for storing unknown oops and raw pointers | |
| 7257 instruct storeP(memory mem, anyRegP src) %{ | |
| 7258 match(Set mem (StoreP mem src)); | |
| 7259 | |
| 7260 ins_cost(125); | |
| 7261 format %{ "MOV $mem,$src" %} | |
| 7262 opcode(0x89); | |
| 7263 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7264 ins_pipe( ialu_mem_reg ); | |
| 7265 %} | |
| 7266 | |
| 7267 // Store Integer Immediate | |
| 7268 instruct storeImmI(memory mem, immI src) %{ | |
| 7269 match(Set mem (StoreI mem src)); | |
| 7270 | |
| 7271 ins_cost(150); | |
| 7272 format %{ "MOV $mem,$src" %} | |
| 7273 opcode(0xC7); /* C7 /0 */ | |
| 7274 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7275 ins_pipe( ialu_mem_imm ); | |
| 7276 %} | |
| 7277 | |
| 7278 // Store Short/Char Immediate | |
| 7279 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 7280 predicate(UseStoreImmI16); | |
| 7281 match(Set mem (StoreC mem src)); | |
| 7282 | |
| 7283 ins_cost(150); | |
| 7284 format %{ "MOV16 $mem,$src" %} | |
| 7285 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7286 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 7287 ins_pipe( ialu_mem_imm ); | |
| 7288 %} | |
| 7289 | |
| 7290 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 7291 // need card-mark barriers. | |
| 7292 instruct storeImmP(memory mem, immP src) %{ | |
| 7293 match(Set mem (StoreP mem src)); | |
| 7294 | |
| 7295 ins_cost(150); | |
| 7296 format %{ "MOV $mem,$src" %} | |
| 7297 opcode(0xC7); /* C7 /0 */ | |
| 7298 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7299 ins_pipe( ialu_mem_imm ); | |
| 7300 %} | |
| 7301 | |
| 7302 // Store Byte Immediate | |
| 7303 instruct storeImmB(memory mem, immI8 src) %{ | |
| 7304 match(Set mem (StoreB mem src)); | |
| 7305 | |
| 7306 ins_cost(150); | |
| 7307 format %{ "MOV8 $mem,$src" %} | |
| 7308 opcode(0xC6); /* C6 /0 */ | |
| 7309 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7310 ins_pipe( ialu_mem_imm ); | |
| 7311 %} | |
| 7312 | |
| 7313 // Store Aligned Packed Byte XMM register to memory | |
| 7314 instruct storeA8B(memory mem, regXD src) %{ | |
| 7315 predicate(UseSSE>=1); | |
| 7316 match(Set mem (Store8B mem src)); | |
| 7317 ins_cost(145); | |
| 7318 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7319 ins_encode( movq_st(mem, src)); | |
| 7320 ins_pipe( pipe_slow ); | |
| 7321 %} | |
| 7322 | |
| 7323 // Store Aligned Packed Char/Short XMM register to memory | |
| 7324 instruct storeA4C(memory mem, regXD src) %{ | |
| 7325 predicate(UseSSE>=1); | |
| 7326 match(Set mem (Store4C mem src)); | |
| 7327 ins_cost(145); | |
| 7328 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7329 ins_encode( movq_st(mem, src)); | |
| 7330 ins_pipe( pipe_slow ); | |
| 7331 %} | |
| 7332 | |
| 7333 // Store Aligned Packed Integer XMM register to memory | |
| 7334 instruct storeA2I(memory mem, regXD src) %{ | |
| 7335 predicate(UseSSE>=1); | |
| 7336 match(Set mem (Store2I mem src)); | |
| 7337 ins_cost(145); | |
| 7338 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7339 ins_encode( movq_st(mem, src)); | |
| 7340 ins_pipe( pipe_slow ); | |
| 7341 %} | |
| 7342 | |
| 7343 // Store CMS card-mark Immediate | |
| 7344 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 7345 match(Set mem (StoreCM mem src)); | |
| 7346 | |
| 7347 ins_cost(150); | |
| 7348 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 7349 opcode(0xC6); /* C6 /0 */ | |
| 7350 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7351 ins_pipe( ialu_mem_imm ); | |
| 7352 %} | |
| 7353 | |
| 7354 // Store Double | |
| 7355 instruct storeD( memory mem, regDPR1 src) %{ | |
| 7356 predicate(UseSSE<=1); | |
| 7357 match(Set mem (StoreD mem src)); | |
| 7358 | |
| 7359 ins_cost(100); | |
| 7360 format %{ "FST_D $mem,$src" %} | |
| 7361 opcode(0xDD); /* DD /2 */ | |
| 7362 ins_encode( enc_FP_store(mem,src) ); | |
| 7363 ins_pipe( fpu_mem_reg ); | |
| 7364 %} | |
| 7365 | |
| 7366 // Store double does rounding on x86 | |
| 7367 instruct storeD_rounded( memory mem, regDPR1 src) %{ | |
| 7368 predicate(UseSSE<=1); | |
| 7369 match(Set mem (StoreD mem (RoundDouble src))); | |
| 7370 | |
| 7371 ins_cost(100); | |
| 7372 format %{ "FST_D $mem,$src\t# round" %} | |
| 7373 opcode(0xDD); /* DD /2 */ | |
| 7374 ins_encode( enc_FP_store(mem,src) ); | |
| 7375 ins_pipe( fpu_mem_reg ); | |
| 7376 %} | |
| 7377 | |
| 7378 // Store XMM register to memory (double-precision floating points) | |
| 7379 // MOVSD instruction | |
| 7380 instruct storeXD(memory mem, regXD src) %{ | |
| 7381 predicate(UseSSE>=2); | |
| 7382 match(Set mem (StoreD mem src)); | |
| 7383 ins_cost(95); | |
| 7384 format %{ "MOVSD $mem,$src" %} | |
| 7385 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7386 ins_pipe( pipe_slow ); | |
| 7387 %} | |
| 7388 | |
| 7389 // Store XMM register to memory (single-precision floating point) | |
| 7390 // MOVSS instruction | |
| 7391 instruct storeX(memory mem, regX src) %{ | |
| 7392 predicate(UseSSE>=1); | |
| 7393 match(Set mem (StoreF mem src)); | |
| 7394 ins_cost(95); | |
| 7395 format %{ "MOVSS $mem,$src" %} | |
| 7396 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7397 ins_pipe( pipe_slow ); | |
| 7398 %} | |
| 7399 | |
| 7400 // Store Aligned Packed Single Float XMM register to memory | |
| 7401 instruct storeA2F(memory mem, regXD src) %{ | |
| 7402 predicate(UseSSE>=1); | |
| 7403 match(Set mem (Store2F mem src)); | |
| 7404 ins_cost(145); | |
| 7405 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7406 ins_encode( movq_st(mem, src)); | |
| 7407 ins_pipe( pipe_slow ); | |
| 7408 %} | |
| 7409 | |
| 7410 // Store Float | |
| 7411 instruct storeF( memory mem, regFPR1 src) %{ | |
| 7412 predicate(UseSSE==0); | |
| 7413 match(Set mem (StoreF mem src)); | |
| 7414 | |
| 7415 ins_cost(100); | |
| 7416 format %{ "FST_S $mem,$src" %} | |
| 7417 opcode(0xD9); /* D9 /2 */ | |
| 7418 ins_encode( enc_FP_store(mem,src) ); | |
| 7419 ins_pipe( fpu_mem_reg ); | |
| 7420 %} | |
| 7421 | |
| 7422 // Store Float does rounding on x86 | |
| 7423 instruct storeF_rounded( memory mem, regFPR1 src) %{ | |
| 7424 predicate(UseSSE==0); | |
| 7425 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7426 | |
| 7427 ins_cost(100); | |
| 7428 format %{ "FST_S $mem,$src\t# round" %} | |
| 7429 opcode(0xD9); /* D9 /2 */ | |
| 7430 ins_encode( enc_FP_store(mem,src) ); | |
| 7431 ins_pipe( fpu_mem_reg ); | |
| 7432 %} | |
| 7433 | |
| 7434 // Store Float does rounding on x86 | |
| 7435 instruct storeF_Drounded( memory mem, regDPR1 src) %{ | |
| 7436 predicate(UseSSE<=1); | |
| 7437 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7438 | |
| 7439 ins_cost(100); | |
| 7440 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7441 opcode(0xD9); /* D9 /2 */ | |
| 7442 ins_encode( enc_FP_store(mem,src) ); | |
| 7443 ins_pipe( fpu_mem_reg ); | |
| 7444 %} | |
| 7445 | |
| 7446 // Store immediate Float value (it is faster than store from FPU register) | |
| 7447 // The instruction usage is guarded by predicate in operand immF(). | |
| 7448 instruct storeF_imm( memory mem, immF src) %{ | |
| 7449 match(Set mem (StoreF mem src)); | |
| 7450 | |
| 7451 ins_cost(50); | |
| 7452 format %{ "MOV $mem,$src\t# store float" %} | |
| 7453 opcode(0xC7); /* C7 /0 */ | |
| 7454 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7455 ins_pipe( ialu_mem_imm ); | |
| 7456 %} | |
| 7457 | |
| 7458 // Store immediate Float value (it is faster than store from XMM register) | |
| 7459 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7460 instruct storeX_imm( memory mem, immXF src) %{ | |
| 7461 match(Set mem (StoreF mem src)); | |
| 7462 | |
| 7463 ins_cost(50); | |
| 7464 format %{ "MOV $mem,$src\t# store float" %} | |
| 7465 opcode(0xC7); /* C7 /0 */ | |
| 7466 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); | |
| 7467 ins_pipe( ialu_mem_imm ); | |
| 7468 %} | |
| 7469 | |
| 7470 // Store Integer to stack slot | |
| 7471 instruct storeSSI(stackSlotI dst, eRegI src) %{ | |
| 7472 match(Set dst src); | |
| 7473 | |
| 7474 ins_cost(100); | |
| 7475 format %{ "MOV $dst,$src" %} | |
| 7476 opcode(0x89); | |
| 7477 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7478 ins_pipe( ialu_mem_reg ); | |
| 7479 %} | |
| 7480 | |
| 7481 // Store Integer to stack slot | |
| 7482 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7483 match(Set dst src); | |
| 7484 | |
| 7485 ins_cost(100); | |
| 7486 format %{ "MOV $dst,$src" %} | |
| 7487 opcode(0x89); | |
| 7488 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7489 ins_pipe( ialu_mem_reg ); | |
| 7490 %} | |
| 7491 | |
| 7492 // Store Long to stack slot | |
| 7493 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7494 match(Set dst src); | |
| 7495 | |
| 7496 ins_cost(200); | |
| 7497 format %{ "MOV $dst,$src.lo\n\t" | |
| 7498 "MOV $dst+4,$src.hi" %} | |
| 7499 opcode(0x89, 0x89); | |
| 7500 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7501 ins_pipe( ialu_mem_long_reg ); | |
| 7502 %} | |
| 7503 | |
| 7504 //----------MemBar Instructions----------------------------------------------- | |
| 7505 // Memory barrier flavors | |
| 7506 | |
| 7507 instruct membar_acquire() %{ | |
| 7508 match(MemBarAcquire); | |
| 7509 ins_cost(400); | |
| 7510 | |
| 7511 size(0); | |
| 7512 format %{ "MEMBAR-acquire" %} | |
| 7513 ins_encode( enc_membar_acquire ); | |
| 7514 ins_pipe(pipe_slow); | |
| 7515 %} | |
| 7516 | |
| 7517 instruct membar_acquire_lock() %{ | |
| 7518 match(MemBarAcquire); | |
| 7519 predicate(Matcher::prior_fast_lock(n)); | |
| 7520 ins_cost(0); | |
| 7521 | |
| 7522 size(0); | |
| 7523 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7524 ins_encode( ); | |
| 7525 ins_pipe(empty); | |
| 7526 %} | |
| 7527 | |
| 7528 instruct membar_release() %{ | |
| 7529 match(MemBarRelease); | |
| 7530 ins_cost(400); | |
| 7531 | |
| 7532 size(0); | |
| 7533 format %{ "MEMBAR-release" %} | |
| 7534 ins_encode( enc_membar_release ); | |
| 7535 ins_pipe(pipe_slow); | |
| 7536 %} | |
| 7537 | |
| 7538 instruct membar_release_lock() %{ | |
| 7539 match(MemBarRelease); | |
| 7540 predicate(Matcher::post_fast_unlock(n)); | |
| 7541 ins_cost(0); | |
| 7542 | |
| 7543 size(0); | |
| 7544 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7545 ins_encode( ); | |
| 7546 ins_pipe(empty); | |
| 7547 %} | |
| 7548 | |
| 7549 instruct membar_volatile() %{ | |
| 7550 match(MemBarVolatile); | |
| 7551 ins_cost(400); | |
| 7552 | |
| 7553 format %{ "MEMBAR-volatile" %} | |
| 7554 ins_encode( enc_membar_volatile ); | |
| 7555 ins_pipe(pipe_slow); | |
| 7556 %} | |
| 7557 | |
| 7558 instruct unnecessary_membar_volatile() %{ | |
| 7559 match(MemBarVolatile); | |
| 7560 predicate(Matcher::post_store_load_barrier(n)); | |
| 7561 ins_cost(0); | |
| 7562 | |
| 7563 size(0); | |
| 7564 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7565 ins_encode( ); | |
| 7566 ins_pipe(empty); | |
| 7567 %} | |
| 7568 | |
| 7569 //----------Move Instructions-------------------------------------------------- | |
| 7570 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7571 match(Set dst (CastX2P src)); | |
| 7572 format %{ "# X2P $dst, $src" %} | |
| 7573 ins_encode( /*empty encoding*/ ); | |
| 7574 ins_cost(0); | |
| 7575 ins_pipe(empty); | |
| 7576 %} | |
| 7577 | |
| 7578 instruct castP2X(eRegI dst, eRegP src ) %{ | |
| 7579 match(Set dst (CastP2X src)); | |
| 7580 ins_cost(50); | |
| 7581 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7582 ins_encode( enc_Copy( dst, src) ); | |
| 7583 ins_pipe( ialu_reg_reg ); | |
| 7584 %} | |
| 7585 | |
| 7586 //----------Conditional Move--------------------------------------------------- | |
| 7587 // Conditional move | |
| 7588 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7589 predicate(VM_Version::supports_cmov() ); | |
| 7590 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7591 ins_cost(200); | |
| 7592 format %{ "CMOV$cop $dst,$src" %} | |
| 7593 opcode(0x0F,0x40); | |
| 7594 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7595 ins_pipe( pipe_cmov_reg ); | |
| 7596 %} | |
| 7597 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7598 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ |
| 0 | 7599 predicate(VM_Version::supports_cmov() ); |
| 7600 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7601 ins_cost(200); | |
| 7602 format %{ "CMOV$cop $dst,$src" %} | |
| 7603 opcode(0x0F,0x40); | |
| 7604 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7605 ins_pipe( pipe_cmov_reg ); | |
| 7606 %} | |
| 7607 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7608 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7609 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7610 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7611 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7612 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7613 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7614 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7615 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7616 |
| 0 | 7617 // Conditional move |
| 7618 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ | |
| 7619 predicate(VM_Version::supports_cmov() ); | |
| 7620 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7621 ins_cost(250); | |
| 7622 format %{ "CMOV$cop $dst,$src" %} | |
| 7623 opcode(0x0F,0x40); | |
| 7624 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7625 ins_pipe( pipe_cmov_mem ); | |
| 7626 %} | |
| 7627 | |
| 7628 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7629 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ |
| 0 | 7630 predicate(VM_Version::supports_cmov() ); |
| 7631 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7632 ins_cost(250); | |
| 7633 format %{ "CMOV$cop $dst,$src" %} | |
| 7634 opcode(0x0F,0x40); | |
| 7635 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7636 ins_pipe( pipe_cmov_mem ); | |
| 7637 %} | |
| 7638 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7639 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7640 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7641 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7642 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7643 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7644 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7645 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7646 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7647 |
| 0 | 7648 // Conditional move |
| 7649 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7650 predicate(VM_Version::supports_cmov() ); | |
| 7651 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7652 ins_cost(200); | |
| 7653 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7654 opcode(0x0F,0x40); | |
| 7655 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7656 ins_pipe( pipe_cmov_reg ); | |
| 7657 %} | |
| 7658 | |
| 7659 // Conditional move (non-P6 version) | |
| 7660 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7661 // regardless of whether we are on a P6, so we | |
| 7662 // emulate a cmov here | |
| 7663 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7664 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7665 ins_cost(300); | |
| 7666 format %{ "Jn$cop skip\n\t" | |
| 7667 "MOV $dst,$src\t# pointer\n" | |
| 7668 "skip:" %} | |
| 7669 opcode(0x8b); | |
| 7670 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7671 ins_pipe( pipe_cmov_reg ); | |
| 7672 %} | |
| 7673 | |
| 7674 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7675 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7676 predicate(VM_Version::supports_cmov() ); |
| 7677 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7678 ins_cost(200); | |
| 7679 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7680 opcode(0x0F,0x40); | |
| 7681 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7682 ins_pipe( pipe_cmov_reg ); | |
| 7683 %} | |
| 7684 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7685 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7686 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7687 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7688 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7689 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7690 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7691 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7692 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7693 |
| 0 | 7694 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7695 // correctly meets the two pointer arguments; one is an incoming | |
| 7696 // register but the other is a memory operand. ALSO appears to | |
| 7697 // be buggy with implicit null checks. | |
| 7698 // | |
| 7699 //// Conditional move | |
| 7700 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7701 // predicate(VM_Version::supports_cmov() ); | |
| 7702 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7703 // ins_cost(250); | |
| 7704 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7705 // opcode(0x0F,0x40); | |
| 7706 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7707 // ins_pipe( pipe_cmov_mem ); | |
| 7708 //%} | |
| 7709 // | |
| 7710 //// Conditional move | |
| 7711 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7712 // predicate(VM_Version::supports_cmov() ); | |
| 7713 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7714 // ins_cost(250); | |
| 7715 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7716 // opcode(0x0F,0x40); | |
| 7717 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7718 // ins_pipe( pipe_cmov_mem ); | |
| 7719 //%} | |
| 7720 | |
| 7721 // Conditional move | |
| 7722 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ | |
| 7723 predicate(UseSSE<=1); | |
| 7724 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7725 ins_cost(200); | |
| 7726 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7727 opcode(0xDA); | |
| 7728 ins_encode( enc_cmov_d(cop,src) ); | |
| 7729 ins_pipe( pipe_cmovD_reg ); | |
| 7730 %} | |
| 7731 | |
| 7732 // Conditional move | |
| 7733 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ | |
| 7734 predicate(UseSSE==0); | |
| 7735 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7736 ins_cost(200); | |
| 7737 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7738 opcode(0xDA); | |
| 7739 ins_encode( enc_cmov_d(cop,src) ); | |
| 7740 ins_pipe( pipe_cmovD_reg ); | |
| 7741 %} | |
| 7742 | |
| 7743 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 7744 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ | |
| 7745 predicate(UseSSE<=1); | |
| 7746 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7747 ins_cost(200); | |
| 7748 format %{ "Jn$cop skip\n\t" | |
| 7749 "MOV $dst,$src\t# double\n" | |
| 7750 "skip:" %} | |
| 7751 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 7752 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); | |
| 7753 ins_pipe( pipe_cmovD_reg ); | |
| 7754 %} | |
| 7755 | |
| 7756 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 7757 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ | |
| 7758 predicate(UseSSE==0); | |
| 7759 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7760 ins_cost(200); | |
| 7761 format %{ "Jn$cop skip\n\t" | |
| 7762 "MOV $dst,$src\t# float\n" | |
| 7763 "skip:" %} | |
| 7764 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 7765 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); | |
| 7766 ins_pipe( pipe_cmovD_reg ); | |
| 7767 %} | |
| 7768 | |
| 7769 // No CMOVE with SSE/SSE2 | |
| 7770 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ | |
| 7771 predicate (UseSSE>=1); | |
| 7772 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7773 ins_cost(200); | |
| 7774 format %{ "Jn$cop skip\n\t" | |
| 7775 "MOVSS $dst,$src\t# float\n" | |
| 7776 "skip:" %} | |
| 7777 ins_encode %{ | |
| 7778 Label skip; | |
| 7779 // Invert sense of branch from sense of CMOV | |
| 7780 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7781 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7782 __ bind(skip); | |
| 7783 %} | |
| 7784 ins_pipe( pipe_slow ); | |
| 7785 %} | |
| 7786 | |
| 7787 // No CMOVE with SSE/SSE2 | |
| 7788 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ | |
| 7789 predicate (UseSSE>=2); | |
| 7790 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7791 ins_cost(200); | |
| 7792 format %{ "Jn$cop skip\n\t" | |
| 7793 "MOVSD $dst,$src\t# float\n" | |
| 7794 "skip:" %} | |
| 7795 ins_encode %{ | |
| 7796 Label skip; | |
| 7797 // Invert sense of branch from sense of CMOV | |
| 7798 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7799 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7800 __ bind(skip); | |
| 7801 %} | |
| 7802 ins_pipe( pipe_slow ); | |
| 7803 %} | |
| 7804 | |
| 7805 // unsigned version | |
| 7806 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ | |
| 7807 predicate (UseSSE>=1); | |
| 7808 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7809 ins_cost(200); | |
| 7810 format %{ "Jn$cop skip\n\t" | |
| 7811 "MOVSS $dst,$src\t# float\n" | |
| 7812 "skip:" %} | |
| 7813 ins_encode %{ | |
| 7814 Label skip; | |
| 7815 // Invert sense of branch from sense of CMOV | |
| 7816 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7817 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7818 __ bind(skip); | |
| 7819 %} | |
| 7820 ins_pipe( pipe_slow ); | |
| 7821 %} | |
| 7822 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7823 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7824 predicate (UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7825 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7826 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7827 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7828 fcmovX_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7829 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7830 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7831 |
| 0 | 7832 // unsigned version |
| 7833 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ | |
| 7834 predicate (UseSSE>=2); | |
| 7835 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7836 ins_cost(200); | |
| 7837 format %{ "Jn$cop skip\n\t" | |
| 7838 "MOVSD $dst,$src\t# float\n" | |
| 7839 "skip:" %} | |
| 7840 ins_encode %{ | |
| 7841 Label skip; | |
| 7842 // Invert sense of branch from sense of CMOV | |
| 7843 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7844 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7845 __ bind(skip); | |
| 7846 %} | |
| 7847 ins_pipe( pipe_slow ); | |
| 7848 %} | |
| 7849 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7850 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7851 predicate (UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7852 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7853 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7854 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7855 fcmovXD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7856 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7857 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7858 |
| 0 | 7859 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7860 predicate(VM_Version::supports_cmov() ); | |
| 7861 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7862 ins_cost(200); | |
| 7863 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7864 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7865 opcode(0x0F,0x40); | |
| 7866 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7867 ins_pipe( pipe_cmov_reg_long ); | |
| 7868 %} | |
| 7869 | |
| 7870 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7871 predicate(VM_Version::supports_cmov() ); | |
| 7872 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7873 ins_cost(200); | |
| 7874 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7875 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7876 opcode(0x0F,0x40); | |
| 7877 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7878 ins_pipe( pipe_cmov_reg_long ); | |
| 7879 %} | |
| 7880 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7881 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7882 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7883 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7884 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7885 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7886 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7887 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7888 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7889 |
| 0 | 7890 //----------Arithmetic Instructions-------------------------------------------- |
| 7891 //----------Addition Instructions---------------------------------------------- | |
| 7892 // Integer Addition Instructions | |
| 7893 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 7894 match(Set dst (AddI dst src)); | |
| 7895 effect(KILL cr); | |
| 7896 | |
| 7897 size(2); | |
| 7898 format %{ "ADD $dst,$src" %} | |
| 7899 opcode(0x03); | |
| 7900 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7901 ins_pipe( ialu_reg_reg ); | |
| 7902 %} | |
| 7903 | |
| 7904 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 7905 match(Set dst (AddI dst src)); | |
| 7906 effect(KILL cr); | |
| 7907 | |
| 7908 format %{ "ADD $dst,$src" %} | |
| 7909 opcode(0x81, 0x00); /* /0 id */ | |
| 7910 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7911 ins_pipe( ialu_reg ); | |
| 7912 %} | |
| 7913 | |
| 7914 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 7915 predicate(UseIncDec); | |
| 7916 match(Set dst (AddI dst src)); | |
| 7917 effect(KILL cr); | |
| 7918 | |
| 7919 size(1); | |
| 7920 format %{ "INC $dst" %} | |
| 7921 opcode(0x40); /* */ | |
| 7922 ins_encode( Opc_plus( primary, dst ) ); | |
| 7923 ins_pipe( ialu_reg ); | |
| 7924 %} | |
| 7925 | |
| 7926 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ | |
| 7927 match(Set dst (AddI src0 src1)); | |
| 7928 ins_cost(110); | |
| 7929 | |
| 7930 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7931 opcode(0x8D); /* 0x8D /r */ | |
| 7932 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7933 ins_pipe( ialu_reg_reg ); | |
| 7934 %} | |
| 7935 | |
| 7936 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7937 match(Set dst (AddP src0 src1)); | |
| 7938 ins_cost(110); | |
| 7939 | |
| 7940 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7941 opcode(0x8D); /* 0x8D /r */ | |
| 7942 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7943 ins_pipe( ialu_reg_reg ); | |
| 7944 %} | |
| 7945 | |
| 7946 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7947 predicate(UseIncDec); | |
| 7948 match(Set dst (AddI dst src)); | |
| 7949 effect(KILL cr); | |
| 7950 | |
| 7951 size(1); | |
| 7952 format %{ "DEC $dst" %} | |
| 7953 opcode(0x48); /* */ | |
| 7954 ins_encode( Opc_plus( primary, dst ) ); | |
| 7955 ins_pipe( ialu_reg ); | |
| 7956 %} | |
| 7957 | |
| 7958 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ | |
| 7959 match(Set dst (AddP dst src)); | |
| 7960 effect(KILL cr); | |
| 7961 | |
| 7962 size(2); | |
| 7963 format %{ "ADD $dst,$src" %} | |
| 7964 opcode(0x03); | |
| 7965 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7966 ins_pipe( ialu_reg_reg ); | |
| 7967 %} | |
| 7968 | |
| 7969 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7970 match(Set dst (AddP dst src)); | |
| 7971 effect(KILL cr); | |
| 7972 | |
| 7973 format %{ "ADD $dst,$src" %} | |
| 7974 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7975 // ins_encode( RegImm( dst, src) ); | |
| 7976 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7977 ins_pipe( ialu_reg ); | |
| 7978 %} | |
| 7979 | |
| 7980 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 7981 match(Set dst (AddI dst (LoadI src))); | |
| 7982 effect(KILL cr); | |
| 7983 | |
| 7984 ins_cost(125); | |
| 7985 format %{ "ADD $dst,$src" %} | |
| 7986 opcode(0x03); | |
| 7987 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7988 ins_pipe( ialu_reg_mem ); | |
| 7989 %} | |
| 7990 | |
| 7991 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 7992 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7993 effect(KILL cr); | |
| 7994 | |
| 7995 ins_cost(150); | |
| 7996 format %{ "ADD $dst,$src" %} | |
| 7997 opcode(0x01); /* Opcode 01 /r */ | |
| 7998 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7999 ins_pipe( ialu_mem_reg ); | |
| 8000 %} | |
| 8001 | |
| 8002 // Add Memory with Immediate | |
| 8003 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8004 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8005 effect(KILL cr); | |
| 8006 | |
| 8007 ins_cost(125); | |
| 8008 format %{ "ADD $dst,$src" %} | |
| 8009 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8010 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 8011 ins_pipe( ialu_mem_imm ); | |
| 8012 %} | |
| 8013 | |
| 8014 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 8015 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8016 effect(KILL cr); | |
| 8017 | |
| 8018 ins_cost(125); | |
| 8019 format %{ "INC $dst" %} | |
| 8020 opcode(0xFF); /* Opcode FF /0 */ | |
| 8021 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 8022 ins_pipe( ialu_mem_imm ); | |
| 8023 %} | |
| 8024 | |
| 8025 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8026 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8027 effect(KILL cr); | |
| 8028 | |
| 8029 ins_cost(125); | |
| 8030 format %{ "DEC $dst" %} | |
| 8031 opcode(0xFF); /* Opcode FF /1 */ | |
| 8032 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 8033 ins_pipe( ialu_mem_imm ); | |
| 8034 %} | |
| 8035 | |
| 8036 | |
| 8037 instruct checkCastPP( eRegP dst ) %{ | |
| 8038 match(Set dst (CheckCastPP dst)); | |
| 8039 | |
| 8040 size(0); | |
| 8041 format %{ "#checkcastPP of $dst" %} | |
| 8042 ins_encode( /*empty encoding*/ ); | |
| 8043 ins_pipe( empty ); | |
| 8044 %} | |
| 8045 | |
| 8046 instruct castPP( eRegP dst ) %{ | |
| 8047 match(Set dst (CastPP dst)); | |
| 8048 format %{ "#castPP of $dst" %} | |
| 8049 ins_encode( /*empty encoding*/ ); | |
| 8050 ins_pipe( empty ); | |
| 8051 %} | |
| 8052 | |
| 8053 instruct castII( eRegI dst ) %{ | |
| 8054 match(Set dst (CastII dst)); | |
| 8055 format %{ "#castII of $dst" %} | |
| 8056 ins_encode( /*empty encoding*/ ); | |
| 8057 ins_cost(0); | |
| 8058 ins_pipe( empty ); | |
| 8059 %} | |
| 8060 | |
| 8061 | |
| 8062 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 8063 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 8064 match(Set dst (LoadPLocked mem)); | |
| 8065 | |
| 8066 ins_cost(125); | |
| 8067 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 8068 opcode(0x8B); | |
| 8069 ins_encode( OpcP, RegMem(dst,mem)); | |
| 8070 ins_pipe( ialu_reg_mem ); | |
| 8071 %} | |
| 8072 | |
| 8073 // LoadLong-locked - same as a volatile long load when used with compare-swap | |
| 8074 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ | |
| 8075 predicate(UseSSE<=1); | |
| 8076 match(Set dst (LoadLLocked mem)); | |
| 8077 | |
| 8078 ins_cost(200); | |
| 8079 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 8080 "FISTp $dst" %} | |
| 8081 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 8082 ins_pipe( fpu_reg_mem ); | |
| 8083 %} | |
| 8084 | |
| 8085 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ | |
| 8086 predicate(UseSSE>=2); | |
| 8087 match(Set dst (LoadLLocked mem)); | |
| 8088 effect(TEMP tmp); | |
| 8089 ins_cost(180); | |
| 8090 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8091 "MOVSD $dst,$tmp" %} | |
| 8092 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 8093 ins_pipe( pipe_slow ); | |
| 8094 %} | |
| 8095 | |
| 8096 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ | |
| 8097 predicate(UseSSE>=2); | |
| 8098 match(Set dst (LoadLLocked mem)); | |
| 8099 effect(TEMP tmp); | |
| 8100 ins_cost(160); | |
| 8101 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8102 "MOVD $dst.lo,$tmp\n\t" | |
| 8103 "PSRLQ $tmp,32\n\t" | |
| 8104 "MOVD $dst.hi,$tmp" %} | |
| 8105 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 8106 ins_pipe( pipe_slow ); | |
| 8107 %} | |
| 8108 | |
| 8109 // Conditional-store of the updated heap-top. | |
| 8110 // Used during allocation of the shared heap. | |
| 8111 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8112 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 8113 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 8114 // EAX is killed if there is contention, but then it's also unused. | |
| 8115 // In the common case of no contention, EAX holds the new oop address. | |
| 8116 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 8117 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 8118 ins_pipe( pipe_cmpxchg ); | |
| 8119 %} | |
| 8120 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8121 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8122 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8123 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8124 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8125 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8126 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8127 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 8128 ins_pipe( pipe_cmpxchg ); |
| 8129 %} | |
| 8130 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8131 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8132 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8133 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8134 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8135 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8136 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8137 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8138 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8139 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8140 ins_encode %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8141 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8142 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8143 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8144 // our register encoding uses rbx. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8145 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8146 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8147 __ lock(); |
| 624 | 8148 __ cmpxchg8($mem$$Address); |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8149 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8150 %} |
| 0 | 8151 ins_pipe( pipe_cmpxchg ); |
| 8152 %} | |
| 8153 | |
| 8154 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 8155 | |
| 8156 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ | |
| 8157 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8158 effect(KILL cr, KILL oldval); | |
| 8159 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8160 "MOV $res,0\n\t" | |
| 8161 "JNE,s fail\n\t" | |
| 8162 "MOV $res,1\n" | |
| 8163 "fail:" %} | |
| 8164 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 8165 enc_flags_ne_to_boolean(res) ); | |
| 8166 ins_pipe( pipe_cmpxchg ); | |
| 8167 %} | |
| 8168 | |
| 8169 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ | |
| 8170 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8171 effect(KILL cr, KILL oldval); | |
| 8172 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8173 "MOV $res,0\n\t" | |
| 8174 "JNE,s fail\n\t" | |
| 8175 "MOV $res,1\n" | |
| 8176 "fail:" %} | |
| 8177 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8178 ins_pipe( pipe_cmpxchg ); | |
| 8179 %} | |
| 8180 | |
| 8181 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ | |
| 8182 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8183 effect(KILL cr, KILL oldval); | |
| 8184 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8185 "MOV $res,0\n\t" | |
| 8186 "JNE,s fail\n\t" | |
| 8187 "MOV $res,1\n" | |
| 8188 "fail:" %} | |
| 8189 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8190 ins_pipe( pipe_cmpxchg ); | |
| 8191 %} | |
| 8192 | |
| 8193 //----------Subtraction Instructions------------------------------------------- | |
| 8194 // Integer Subtraction Instructions | |
| 8195 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8196 match(Set dst (SubI dst src)); | |
| 8197 effect(KILL cr); | |
| 8198 | |
| 8199 size(2); | |
| 8200 format %{ "SUB $dst,$src" %} | |
| 8201 opcode(0x2B); | |
| 8202 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8203 ins_pipe( ialu_reg_reg ); | |
| 8204 %} | |
| 8205 | |
| 8206 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8207 match(Set dst (SubI dst src)); | |
| 8208 effect(KILL cr); | |
| 8209 | |
| 8210 format %{ "SUB $dst,$src" %} | |
| 8211 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 8212 // ins_encode( RegImm( dst, src) ); | |
| 8213 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8214 ins_pipe( ialu_reg ); | |
| 8215 %} | |
| 8216 | |
| 8217 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8218 match(Set dst (SubI dst (LoadI src))); | |
| 8219 effect(KILL cr); | |
| 8220 | |
| 8221 ins_cost(125); | |
| 8222 format %{ "SUB $dst,$src" %} | |
| 8223 opcode(0x2B); | |
| 8224 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8225 ins_pipe( ialu_reg_mem ); | |
| 8226 %} | |
| 8227 | |
| 8228 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8229 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8230 effect(KILL cr); | |
| 8231 | |
| 8232 ins_cost(150); | |
| 8233 format %{ "SUB $dst,$src" %} | |
| 8234 opcode(0x29); /* Opcode 29 /r */ | |
| 8235 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8236 ins_pipe( ialu_mem_reg ); | |
| 8237 %} | |
| 8238 | |
| 8239 // Subtract from a pointer | |
| 8240 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ | |
| 8241 match(Set dst (AddP dst (SubI zero src))); | |
| 8242 effect(KILL cr); | |
| 8243 | |
| 8244 size(2); | |
| 8245 format %{ "SUB $dst,$src" %} | |
| 8246 opcode(0x2B); | |
| 8247 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8248 ins_pipe( ialu_reg_reg ); | |
| 8249 %} | |
| 8250 | |
| 8251 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 8252 match(Set dst (SubI zero dst)); | |
| 8253 effect(KILL cr); | |
| 8254 | |
| 8255 size(2); | |
| 8256 format %{ "NEG $dst" %} | |
| 8257 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 8258 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8259 ins_pipe( ialu_reg ); | |
| 8260 %} | |
| 8261 | |
| 8262 | |
| 8263 //----------Multiplication/Division Instructions------------------------------- | |
| 8264 // Integer Multiplication Instructions | |
| 8265 // Multiply Register | |
| 8266 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8267 match(Set dst (MulI dst src)); | |
| 8268 effect(KILL cr); | |
| 8269 | |
| 8270 size(3); | |
| 8271 ins_cost(300); | |
| 8272 format %{ "IMUL $dst,$src" %} | |
| 8273 opcode(0xAF, 0x0F); | |
| 8274 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 8275 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8276 %} | |
| 8277 | |
| 8278 // Multiply 32-bit Immediate | |
| 8279 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ | |
| 8280 match(Set dst (MulI src imm)); | |
| 8281 effect(KILL cr); | |
| 8282 | |
| 8283 ins_cost(300); | |
| 8284 format %{ "IMUL $dst,$src,$imm" %} | |
| 8285 opcode(0x69); /* 69 /r id */ | |
| 8286 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 8287 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8288 %} | |
| 8289 | |
| 8290 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 8291 match(Set dst src); | |
| 8292 effect(KILL cr); | |
| 8293 | |
| 8294 // Note that this is artificially increased to make it more expensive than loadConL | |
| 8295 ins_cost(250); | |
| 8296 format %{ "MOV EAX,$src\t// low word only" %} | |
| 8297 opcode(0xB8); | |
| 8298 ins_encode( LdImmL_Lo(dst, src) ); | |
| 8299 ins_pipe( ialu_reg_fat ); | |
| 8300 %} | |
| 8301 | |
| 8302 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8303 // (special case for shift by 32) | |
| 8304 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8305 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8306 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8307 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8308 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8309 effect(USE src1, KILL cr); | |
| 8310 | |
| 8311 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8312 ins_cost(0*100 + 1*400 - 150); | |
| 8313 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8314 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8315 ins_pipe( pipe_slow ); | |
| 8316 %} | |
| 8317 | |
| 8318 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8319 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8320 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8321 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8322 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8323 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8324 effect(USE src1, KILL cr); | |
| 8325 | |
| 8326 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8327 ins_cost(1*100 + 1*400 - 150); | |
| 8328 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8329 "SAR EDX,$cnt-32" %} | |
| 8330 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8331 ins_pipe( pipe_slow ); | |
| 8332 %} | |
| 8333 | |
| 8334 // Multiply Memory 32-bit Immediate | |
| 8335 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ | |
| 8336 match(Set dst (MulI (LoadI src) imm)); | |
| 8337 effect(KILL cr); | |
| 8338 | |
| 8339 ins_cost(300); | |
| 8340 format %{ "IMUL $dst,$src,$imm" %} | |
| 8341 opcode(0x69); /* 69 /r id */ | |
| 8342 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8343 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8344 %} | |
| 8345 | |
| 8346 // Multiply Memory | |
| 8347 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8348 match(Set dst (MulI dst (LoadI src))); | |
| 8349 effect(KILL cr); | |
| 8350 | |
| 8351 ins_cost(350); | |
| 8352 format %{ "IMUL $dst,$src" %} | |
| 8353 opcode(0xAF, 0x0F); | |
| 8354 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8355 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8356 %} | |
| 8357 | |
| 8358 // Multiply Register Int to Long | |
| 8359 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8360 // Basic Idea: long = (long)int * (long)int | |
| 8361 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8362 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8363 | |
| 8364 ins_cost(300); | |
| 8365 format %{ "IMUL $dst,$src1" %} | |
| 8366 | |
| 8367 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8368 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8369 %} | |
| 8370 | |
| 8371 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8372 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8373 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8374 effect(KILL flags); | |
| 8375 | |
| 8376 ins_cost(300); | |
| 8377 format %{ "MUL $dst,$src1" %} | |
| 8378 | |
| 8379 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8380 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8381 %} | |
| 8382 | |
| 8383 // Multiply Register Long | |
| 8384 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ | |
| 8385 match(Set dst (MulL dst src)); | |
| 8386 effect(KILL cr, TEMP tmp); | |
| 8387 ins_cost(4*100+3*400); | |
| 8388 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8389 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8390 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8391 "IMUL $tmp,EDX\n\t" | |
| 8392 "MOV EDX,$src.hi\n\t" | |
| 8393 "IMUL EDX,EAX\n\t" | |
| 8394 "ADD $tmp,EDX\n\t" | |
| 8395 "MUL EDX:EAX,$src.lo\n\t" | |
| 8396 "ADD EDX,$tmp" %} | |
| 8397 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8398 ins_pipe( pipe_slow ); | |
| 8399 %} | |
| 8400 | |
| 8401 // Multiply Register Long by small constant | |
| 8402 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ | |
| 8403 match(Set dst (MulL dst src)); | |
| 8404 effect(KILL cr, TEMP tmp); | |
| 8405 ins_cost(2*100+2*400); | |
| 8406 size(12); | |
| 8407 // Basic idea: lo(result) = lo(src * EAX) | |
| 8408 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8409 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8410 "MOV EDX,$src\n\t" | |
| 8411 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8412 "ADD EDX,$tmp" %} | |
| 8413 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8414 ins_pipe( pipe_slow ); | |
| 8415 %} | |
| 8416 | |
| 8417 // Integer DIV with Register | |
| 8418 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8419 match(Set rax (DivI rax div)); | |
| 8420 effect(KILL rdx, KILL cr); | |
| 8421 size(26); | |
| 8422 ins_cost(30*100+10*100); | |
| 8423 format %{ "CMP EAX,0x80000000\n\t" | |
| 8424 "JNE,s normal\n\t" | |
| 8425 "XOR EDX,EDX\n\t" | |
| 8426 "CMP ECX,-1\n\t" | |
| 8427 "JE,s done\n" | |
| 8428 "normal: CDQ\n\t" | |
| 8429 "IDIV $div\n\t" | |
| 8430 "done:" %} | |
| 8431 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8432 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8433 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8434 %} | |
| 8435 | |
| 8436 // Divide Register Long | |
| 8437 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8438 match(Set dst (DivL src1 src2)); | |
| 8439 effect( KILL cr, KILL cx, KILL bx ); | |
| 8440 ins_cost(10000); | |
| 8441 format %{ "PUSH $src1.hi\n\t" | |
| 8442 "PUSH $src1.lo\n\t" | |
| 8443 "PUSH $src2.hi\n\t" | |
| 8444 "PUSH $src2.lo\n\t" | |
| 8445 "CALL SharedRuntime::ldiv\n\t" | |
| 8446 "ADD ESP,16" %} | |
| 8447 ins_encode( long_div(src1,src2) ); | |
| 8448 ins_pipe( pipe_slow ); | |
| 8449 %} | |
| 8450 | |
| 8451 // Integer DIVMOD with Register, both quotient and mod results | |
| 8452 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8453 match(DivModI rax div); | |
| 8454 effect(KILL cr); | |
| 8455 size(26); | |
| 8456 ins_cost(30*100+10*100); | |
| 8457 format %{ "CMP EAX,0x80000000\n\t" | |
| 8458 "JNE,s normal\n\t" | |
| 8459 "XOR EDX,EDX\n\t" | |
| 8460 "CMP ECX,-1\n\t" | |
| 8461 "JE,s done\n" | |
| 8462 "normal: CDQ\n\t" | |
| 8463 "IDIV $div\n\t" | |
| 8464 "done:" %} | |
| 8465 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8466 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8467 ins_pipe( pipe_slow ); | |
| 8468 %} | |
| 8469 | |
| 8470 // Integer MOD with Register | |
| 8471 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8472 match(Set rdx (ModI rax div)); | |
| 8473 effect(KILL rax, KILL cr); | |
| 8474 | |
| 8475 size(26); | |
| 8476 ins_cost(300); | |
| 8477 format %{ "CDQ\n\t" | |
| 8478 "IDIV $div" %} | |
| 8479 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8480 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8481 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8482 %} | |
| 8483 | |
| 8484 // Remainder Register Long | |
| 8485 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8486 match(Set dst (ModL src1 src2)); | |
| 8487 effect( KILL cr, KILL cx, KILL bx ); | |
| 8488 ins_cost(10000); | |
| 8489 format %{ "PUSH $src1.hi\n\t" | |
| 8490 "PUSH $src1.lo\n\t" | |
| 8491 "PUSH $src2.hi\n\t" | |
| 8492 "PUSH $src2.lo\n\t" | |
| 8493 "CALL SharedRuntime::lrem\n\t" | |
| 8494 "ADD ESP,16" %} | |
| 8495 ins_encode( long_mod(src1,src2) ); | |
| 8496 ins_pipe( pipe_slow ); | |
| 8497 %} | |
| 8498 | |
| 8499 // Integer Shift Instructions | |
| 8500 // Shift Left by one | |
| 8501 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8502 match(Set dst (LShiftI dst shift)); | |
| 8503 effect(KILL cr); | |
| 8504 | |
| 8505 size(2); | |
| 8506 format %{ "SHL $dst,$shift" %} | |
| 8507 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8508 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8509 ins_pipe( ialu_reg ); | |
| 8510 %} | |
| 8511 | |
| 8512 // Shift Left by 8-bit immediate | |
| 8513 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8514 match(Set dst (LShiftI dst shift)); | |
| 8515 effect(KILL cr); | |
| 8516 | |
| 8517 size(3); | |
| 8518 format %{ "SHL $dst,$shift" %} | |
| 8519 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8520 ins_encode( RegOpcImm( dst, shift) ); | |
| 8521 ins_pipe( ialu_reg ); | |
| 8522 %} | |
| 8523 | |
| 8524 // Shift Left by variable | |
| 8525 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8526 match(Set dst (LShiftI dst shift)); | |
| 8527 effect(KILL cr); | |
| 8528 | |
| 8529 size(2); | |
| 8530 format %{ "SHL $dst,$shift" %} | |
| 8531 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8532 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8533 ins_pipe( ialu_reg_reg ); | |
| 8534 %} | |
| 8535 | |
| 8536 // Arithmetic shift right by one | |
| 8537 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8538 match(Set dst (RShiftI dst shift)); | |
| 8539 effect(KILL cr); | |
| 8540 | |
| 8541 size(2); | |
| 8542 format %{ "SAR $dst,$shift" %} | |
| 8543 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8544 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8545 ins_pipe( ialu_reg ); | |
| 8546 %} | |
| 8547 | |
| 8548 // Arithmetic shift right by one | |
| 8549 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8550 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8551 effect(KILL cr); | |
| 8552 format %{ "SAR $dst,$shift" %} | |
| 8553 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8554 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8555 ins_pipe( ialu_mem_imm ); | |
| 8556 %} | |
| 8557 | |
| 8558 // Arithmetic Shift Right by 8-bit immediate | |
| 8559 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8560 match(Set dst (RShiftI dst shift)); | |
| 8561 effect(KILL cr); | |
| 8562 | |
| 8563 size(3); | |
| 8564 format %{ "SAR $dst,$shift" %} | |
| 8565 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8566 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8567 ins_pipe( ialu_mem_imm ); | |
| 8568 %} | |
| 8569 | |
| 8570 // Arithmetic Shift Right by 8-bit immediate | |
| 8571 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8572 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8573 effect(KILL cr); | |
| 8574 | |
| 8575 format %{ "SAR $dst,$shift" %} | |
| 8576 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8577 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8578 ins_pipe( ialu_mem_imm ); | |
| 8579 %} | |
| 8580 | |
| 8581 // Arithmetic Shift Right by variable | |
| 8582 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8583 match(Set dst (RShiftI dst shift)); | |
| 8584 effect(KILL cr); | |
| 8585 | |
| 8586 size(2); | |
| 8587 format %{ "SAR $dst,$shift" %} | |
| 8588 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8589 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8590 ins_pipe( ialu_reg_reg ); | |
| 8591 %} | |
| 8592 | |
| 8593 // Logical shift right by one | |
| 8594 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8595 match(Set dst (URShiftI dst shift)); | |
| 8596 effect(KILL cr); | |
| 8597 | |
| 8598 size(2); | |
| 8599 format %{ "SHR $dst,$shift" %} | |
| 8600 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8601 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8602 ins_pipe( ialu_reg ); | |
| 8603 %} | |
| 8604 | |
| 8605 // Logical Shift Right by 8-bit immediate | |
| 8606 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8607 match(Set dst (URShiftI dst shift)); | |
| 8608 effect(KILL cr); | |
| 8609 | |
| 8610 size(3); | |
| 8611 format %{ "SHR $dst,$shift" %} | |
| 8612 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8613 ins_encode( RegOpcImm( dst, shift) ); | |
| 8614 ins_pipe( ialu_reg ); | |
| 8615 %} | |
| 8616 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8617 |
| 0 | 8618 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8619 // This idiom is used by the compiler for the i2b bytecode. | |
| 8620 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{ | |
| 8621 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8622 effect(KILL cr); | |
| 8623 | |
| 8624 size(3); | |
| 8625 format %{ "MOVSX $dst,$src :8" %} | |
| 8626 opcode(0xBE, 0x0F); | |
| 8627 ins_encode( OpcS, OpcP, RegReg( dst, src)); | |
| 8628 ins_pipe( ialu_reg_reg ); | |
| 8629 %} | |
| 8630 | |
| 8631 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8632 // This idiom is used by the compiler the i2s bytecode. | |
| 8633 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{ | |
| 8634 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8635 effect(KILL cr); | |
| 8636 | |
| 8637 size(3); | |
| 8638 format %{ "MOVSX $dst,$src :16" %} | |
| 8639 opcode(0xBF, 0x0F); | |
| 8640 ins_encode( OpcS, OpcP, RegReg( dst, src)); | |
| 8641 ins_pipe( ialu_reg_reg ); | |
| 8642 %} | |
| 8643 | |
| 8644 | |
| 8645 // Logical Shift Right by variable | |
| 8646 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8647 match(Set dst (URShiftI dst shift)); | |
| 8648 effect(KILL cr); | |
| 8649 | |
| 8650 size(2); | |
| 8651 format %{ "SHR $dst,$shift" %} | |
| 8652 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8653 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8654 ins_pipe( ialu_reg_reg ); | |
| 8655 %} | |
| 8656 | |
| 8657 | |
| 8658 //----------Logical Instructions----------------------------------------------- | |
| 8659 //----------Integer Logical Instructions--------------------------------------- | |
| 8660 // And Instructions | |
| 8661 // And Register with Register | |
| 8662 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8663 match(Set dst (AndI dst src)); | |
| 8664 effect(KILL cr); | |
| 8665 | |
| 8666 size(2); | |
| 8667 format %{ "AND $dst,$src" %} | |
| 8668 opcode(0x23); | |
| 8669 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8670 ins_pipe( ialu_reg_reg ); | |
| 8671 %} | |
| 8672 | |
| 8673 // And Register with Immediate | |
| 8674 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8675 match(Set dst (AndI dst src)); | |
| 8676 effect(KILL cr); | |
| 8677 | |
| 8678 format %{ "AND $dst,$src" %} | |
| 8679 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8680 // ins_encode( RegImm( dst, src) ); | |
| 8681 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8682 ins_pipe( ialu_reg ); | |
| 8683 %} | |
| 8684 | |
| 8685 // And Register with Memory | |
| 8686 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8687 match(Set dst (AndI dst (LoadI src))); | |
| 8688 effect(KILL cr); | |
| 8689 | |
| 8690 ins_cost(125); | |
| 8691 format %{ "AND $dst,$src" %} | |
| 8692 opcode(0x23); | |
| 8693 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8694 ins_pipe( ialu_reg_mem ); | |
| 8695 %} | |
| 8696 | |
| 8697 // And Memory with Register | |
| 8698 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8699 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8700 effect(KILL cr); | |
| 8701 | |
| 8702 ins_cost(150); | |
| 8703 format %{ "AND $dst,$src" %} | |
| 8704 opcode(0x21); /* Opcode 21 /r */ | |
| 8705 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8706 ins_pipe( ialu_mem_reg ); | |
| 8707 %} | |
| 8708 | |
| 8709 // And Memory with Immediate | |
| 8710 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8711 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8712 effect(KILL cr); | |
| 8713 | |
| 8714 ins_cost(125); | |
| 8715 format %{ "AND $dst,$src" %} | |
| 8716 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8717 // ins_encode( MemImm( dst, src) ); | |
| 8718 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8719 ins_pipe( ialu_mem_imm ); | |
| 8720 %} | |
| 8721 | |
| 8722 // Or Instructions | |
| 8723 // Or Register with Register | |
| 8724 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8725 match(Set dst (OrI dst src)); | |
| 8726 effect(KILL cr); | |
| 8727 | |
| 8728 size(2); | |
| 8729 format %{ "OR $dst,$src" %} | |
| 8730 opcode(0x0B); | |
| 8731 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8732 ins_pipe( ialu_reg_reg ); | |
| 8733 %} | |
| 8734 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8735 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8736 match(Set dst (OrI dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8737 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8738 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8739 size(2); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8740 format %{ "OR $dst,$src" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8741 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8742 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8743 ins_pipe( ialu_reg_reg ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8744 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8745 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8746 |
| 0 | 8747 // Or Register with Immediate |
| 8748 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8749 match(Set dst (OrI dst src)); | |
| 8750 effect(KILL cr); | |
| 8751 | |
| 8752 format %{ "OR $dst,$src" %} | |
| 8753 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8754 // ins_encode( RegImm( dst, src) ); | |
| 8755 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8756 ins_pipe( ialu_reg ); | |
| 8757 %} | |
| 8758 | |
| 8759 // Or Register with Memory | |
| 8760 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8761 match(Set dst (OrI dst (LoadI src))); | |
| 8762 effect(KILL cr); | |
| 8763 | |
| 8764 ins_cost(125); | |
| 8765 format %{ "OR $dst,$src" %} | |
| 8766 opcode(0x0B); | |
| 8767 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8768 ins_pipe( ialu_reg_mem ); | |
| 8769 %} | |
| 8770 | |
| 8771 // Or Memory with Register | |
| 8772 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8773 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8774 effect(KILL cr); | |
| 8775 | |
| 8776 ins_cost(150); | |
| 8777 format %{ "OR $dst,$src" %} | |
| 8778 opcode(0x09); /* Opcode 09 /r */ | |
| 8779 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8780 ins_pipe( ialu_mem_reg ); | |
| 8781 %} | |
| 8782 | |
| 8783 // Or Memory with Immediate | |
| 8784 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8785 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8786 effect(KILL cr); | |
| 8787 | |
| 8788 ins_cost(125); | |
| 8789 format %{ "OR $dst,$src" %} | |
| 8790 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8791 // ins_encode( MemImm( dst, src) ); | |
| 8792 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8793 ins_pipe( ialu_mem_imm ); | |
| 8794 %} | |
| 8795 | |
| 8796 // ROL/ROR | |
| 8797 // ROL expand | |
| 8798 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8799 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8800 | |
| 8801 format %{ "ROL $dst, $shift" %} | |
| 8802 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8803 ins_encode( OpcP, RegOpc( dst )); | |
| 8804 ins_pipe( ialu_reg ); | |
| 8805 %} | |
| 8806 | |
| 8807 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8808 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8809 | |
| 8810 format %{ "ROL $dst, $shift" %} | |
| 8811 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8812 ins_encode( RegOpcImm(dst, shift) ); | |
| 8813 ins_pipe(ialu_reg); | |
| 8814 %} | |
| 8815 | |
| 8816 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8817 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8818 | |
| 8819 format %{ "ROL $dst, $shift" %} | |
| 8820 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8821 ins_encode(OpcP, RegOpc(dst)); | |
| 8822 ins_pipe( ialu_reg_reg ); | |
| 8823 %} | |
| 8824 // end of ROL expand | |
| 8825 | |
| 8826 // ROL 32bit by one once | |
| 8827 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ | |
| 8828 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8829 | |
| 8830 expand %{ | |
| 8831 rolI_eReg_imm1(dst, lshift, cr); | |
| 8832 %} | |
| 8833 %} | |
| 8834 | |
| 8835 // ROL 32bit var by imm8 once | |
| 8836 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ | |
| 8837 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8838 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8839 | |
| 8840 expand %{ | |
| 8841 rolI_eReg_imm8(dst, lshift, cr); | |
| 8842 %} | |
| 8843 %} | |
| 8844 | |
| 8845 // ROL 32bit var by var once | |
| 8846 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8847 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8848 | |
| 8849 expand %{ | |
| 8850 rolI_eReg_CL(dst, shift, cr); | |
| 8851 %} | |
| 8852 %} | |
| 8853 | |
| 8854 // ROL 32bit var by var once | |
| 8855 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8856 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8857 | |
| 8858 expand %{ | |
| 8859 rolI_eReg_CL(dst, shift, cr); | |
| 8860 %} | |
| 8861 %} | |
| 8862 | |
| 8863 // ROR expand | |
| 8864 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8865 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8866 | |
| 8867 format %{ "ROR $dst, $shift" %} | |
| 8868 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8869 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8870 ins_pipe( ialu_reg ); | |
| 8871 %} | |
| 8872 | |
| 8873 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8874 effect (USE_DEF dst, USE shift, KILL cr); | |
| 8875 | |
| 8876 format %{ "ROR $dst, $shift" %} | |
| 8877 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8878 ins_encode( RegOpcImm(dst, shift) ); | |
| 8879 ins_pipe( ialu_reg ); | |
| 8880 %} | |
| 8881 | |
| 8882 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8883 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8884 | |
| 8885 format %{ "ROR $dst, $shift" %} | |
| 8886 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8887 ins_encode(OpcP, RegOpc(dst)); | |
| 8888 ins_pipe( ialu_reg_reg ); | |
| 8889 %} | |
| 8890 // end of ROR expand | |
| 8891 | |
| 8892 // ROR right once | |
| 8893 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ | |
| 8894 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8895 | |
| 8896 expand %{ | |
| 8897 rorI_eReg_imm1(dst, rshift, cr); | |
| 8898 %} | |
| 8899 %} | |
| 8900 | |
| 8901 // ROR 32bit by immI8 once | |
| 8902 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ | |
| 8903 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8904 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8905 | |
| 8906 expand %{ | |
| 8907 rorI_eReg_imm8(dst, rshift, cr); | |
| 8908 %} | |
| 8909 %} | |
| 8910 | |
| 8911 // ROR 32bit var by var once | |
| 8912 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8913 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8914 | |
| 8915 expand %{ | |
| 8916 rorI_eReg_CL(dst, shift, cr); | |
| 8917 %} | |
| 8918 %} | |
| 8919 | |
| 8920 // ROR 32bit var by var once | |
| 8921 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8922 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8923 | |
| 8924 expand %{ | |
| 8925 rorI_eReg_CL(dst, shift, cr); | |
| 8926 %} | |
| 8927 %} | |
| 8928 | |
| 8929 // Xor Instructions | |
| 8930 // Xor Register with Register | |
| 8931 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8932 match(Set dst (XorI dst src)); | |
| 8933 effect(KILL cr); | |
| 8934 | |
| 8935 size(2); | |
| 8936 format %{ "XOR $dst,$src" %} | |
| 8937 opcode(0x33); | |
| 8938 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8939 ins_pipe( ialu_reg_reg ); | |
| 8940 %} | |
| 8941 | |
| 403 | 8942 // Xor Register with Immediate -1 |
| 8943 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ | |
| 8944 match(Set dst (XorI dst imm)); | |
| 8945 | |
| 8946 size(2); | |
| 8947 format %{ "NOT $dst" %} | |
| 8948 ins_encode %{ | |
| 8949 __ notl($dst$$Register); | |
| 8950 %} | |
| 8951 ins_pipe( ialu_reg ); | |
| 8952 %} | |
| 8953 | |
| 0 | 8954 // Xor Register with Immediate |
| 8955 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8956 match(Set dst (XorI dst src)); | |
| 8957 effect(KILL cr); | |
| 8958 | |
| 8959 format %{ "XOR $dst,$src" %} | |
| 8960 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8961 // ins_encode( RegImm( dst, src) ); | |
| 8962 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8963 ins_pipe( ialu_reg ); | |
| 8964 %} | |
| 8965 | |
| 8966 // Xor Register with Memory | |
| 8967 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8968 match(Set dst (XorI dst (LoadI src))); | |
| 8969 effect(KILL cr); | |
| 8970 | |
| 8971 ins_cost(125); | |
| 8972 format %{ "XOR $dst,$src" %} | |
| 8973 opcode(0x33); | |
| 8974 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8975 ins_pipe( ialu_reg_mem ); | |
| 8976 %} | |
| 8977 | |
| 8978 // Xor Memory with Register | |
| 8979 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8980 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8981 effect(KILL cr); | |
| 8982 | |
| 8983 ins_cost(150); | |
| 8984 format %{ "XOR $dst,$src" %} | |
| 8985 opcode(0x31); /* Opcode 31 /r */ | |
| 8986 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8987 ins_pipe( ialu_mem_reg ); | |
| 8988 %} | |
| 8989 | |
| 8990 // Xor Memory with Immediate | |
| 8991 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8992 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8993 effect(KILL cr); | |
| 8994 | |
| 8995 ins_cost(125); | |
| 8996 format %{ "XOR $dst,$src" %} | |
| 8997 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8998 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8999 ins_pipe( ialu_mem_imm ); | |
| 9000 %} | |
| 9001 | |
| 9002 //----------Convert Int to Boolean--------------------------------------------- | |
| 9003 | |
| 9004 instruct movI_nocopy(eRegI dst, eRegI src) %{ | |
| 9005 effect( DEF dst, USE src ); | |
| 9006 format %{ "MOV $dst,$src" %} | |
| 9007 ins_encode( enc_Copy( dst, src) ); | |
| 9008 ins_pipe( ialu_reg_reg ); | |
| 9009 %} | |
| 9010 | |
| 9011 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9012 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9013 | |
| 9014 size(4); | |
| 9015 format %{ "NEG $dst\n\t" | |
| 9016 "ADC $dst,$src" %} | |
| 9017 ins_encode( neg_reg(dst), | |
| 9018 OpcRegReg(0x13,dst,src) ); | |
| 9019 ins_pipe( ialu_reg_reg_long ); | |
| 9020 %} | |
| 9021 | |
| 9022 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9023 match(Set dst (Conv2B src)); | |
| 9024 | |
| 9025 expand %{ | |
| 9026 movI_nocopy(dst,src); | |
| 9027 ci2b(dst,src,cr); | |
| 9028 %} | |
| 9029 %} | |
| 9030 | |
| 9031 instruct movP_nocopy(eRegI dst, eRegP src) %{ | |
| 9032 effect( DEF dst, USE src ); | |
| 9033 format %{ "MOV $dst,$src" %} | |
| 9034 ins_encode( enc_Copy( dst, src) ); | |
| 9035 ins_pipe( ialu_reg_reg ); | |
| 9036 %} | |
| 9037 | |
| 9038 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9039 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9040 format %{ "NEG $dst\n\t" | |
| 9041 "ADC $dst,$src" %} | |
| 9042 ins_encode( neg_reg(dst), | |
| 9043 OpcRegReg(0x13,dst,src) ); | |
| 9044 ins_pipe( ialu_reg_reg_long ); | |
| 9045 %} | |
| 9046 | |
| 9047 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9048 match(Set dst (Conv2B src)); | |
| 9049 | |
| 9050 expand %{ | |
| 9051 movP_nocopy(dst,src); | |
| 9052 cp2b(dst,src,cr); | |
| 9053 %} | |
| 9054 %} | |
| 9055 | |
| 9056 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 9057 match(Set dst (CmpLTMask p q)); | |
| 9058 effect( KILL cr ); | |
| 9059 ins_cost(400); | |
| 9060 | |
| 9061 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 9062 format %{ "XOR $dst,$dst\n\t" | |
| 9063 "CMP $p,$q\n\t" | |
| 9064 "SETlt $dst\n\t" | |
| 9065 "NEG $dst" %} | |
| 9066 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 9067 OpcRegReg(0x3B,p,q), | |
| 9068 setLT_reg(dst), neg_reg(dst) ); | |
| 9069 ins_pipe( pipe_slow ); | |
| 9070 %} | |
| 9071 | |
| 9072 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ | |
| 9073 match(Set dst (CmpLTMask dst zero)); | |
| 9074 effect( DEF dst, KILL cr ); | |
| 9075 ins_cost(100); | |
| 9076 | |
| 9077 format %{ "SAR $dst,31" %} | |
| 9078 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9079 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 9080 ins_pipe( ialu_reg ); | |
| 9081 %} | |
| 9082 | |
| 9083 | |
| 9084 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9085 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9086 effect( KILL tmp, KILL cr ); | |
| 9087 ins_cost(400); | |
| 9088 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 9089 // any format or encoding | |
| 9090 format %{ "SUB $p,$q\n\t" | |
| 9091 "SBB ECX,ECX\n\t" | |
| 9092 "AND ECX,$y\n\t" | |
| 9093 "ADD $p,ECX" %} | |
| 9094 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 9095 ins_pipe( pipe_cmplt ); | |
| 9096 %} | |
| 9097 | |
| 9098 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9099 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9100 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9101 effect( USE_KILL tmp, KILL cr ); | |
| 9102 ins_cost(400); | |
| 9103 | |
| 9104 format %{ "SUB $p,$q\n\t" | |
| 9105 "SBB ECX,ECX\n\t" | |
| 9106 "AND ECX,$y\n\t" | |
| 9107 "ADD $p,ECX" %} | |
| 9108 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9109 %} | |
| 9110 */ | |
| 9111 | |
| 9112 //----------Long Instructions------------------------------------------------ | |
| 9113 // Add Long Register with Register | |
| 9114 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9115 match(Set dst (AddL dst src)); | |
| 9116 effect(KILL cr); | |
| 9117 ins_cost(200); | |
| 9118 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9119 "ADC $dst.hi,$src.hi" %} | |
| 9120 opcode(0x03, 0x13); | |
| 9121 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9122 ins_pipe( ialu_reg_reg_long ); | |
| 9123 %} | |
| 9124 | |
| 9125 // Add Long Register with Immediate | |
| 9126 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9127 match(Set dst (AddL dst src)); | |
| 9128 effect(KILL cr); | |
| 9129 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9130 "ADC $dst.hi,$src.hi" %} | |
| 9131 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9132 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9133 ins_pipe( ialu_reg_long ); | |
| 9134 %} | |
| 9135 | |
| 9136 // Add Long Register with Memory | |
| 9137 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9138 match(Set dst (AddL dst (LoadL mem))); | |
| 9139 effect(KILL cr); | |
| 9140 ins_cost(125); | |
| 9141 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9142 "ADC $dst.hi,$mem+4" %} | |
| 9143 opcode(0x03, 0x13); | |
| 9144 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9145 ins_pipe( ialu_reg_long_mem ); | |
| 9146 %} | |
| 9147 | |
| 9148 // Subtract Long Register with Register. | |
| 9149 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9150 match(Set dst (SubL dst src)); | |
| 9151 effect(KILL cr); | |
| 9152 ins_cost(200); | |
| 9153 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9154 "SBB $dst.hi,$src.hi" %} | |
| 9155 opcode(0x2B, 0x1B); | |
| 9156 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9157 ins_pipe( ialu_reg_reg_long ); | |
| 9158 %} | |
| 9159 | |
| 9160 // Subtract Long Register with Immediate | |
| 9161 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9162 match(Set dst (SubL dst src)); | |
| 9163 effect(KILL cr); | |
| 9164 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9165 "SBB $dst.hi,$src.hi" %} | |
| 9166 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9167 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9168 ins_pipe( ialu_reg_long ); | |
| 9169 %} | |
| 9170 | |
| 9171 // Subtract Long Register with Memory | |
| 9172 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9173 match(Set dst (SubL dst (LoadL mem))); | |
| 9174 effect(KILL cr); | |
| 9175 ins_cost(125); | |
| 9176 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9177 "SBB $dst.hi,$mem+4" %} | |
| 9178 opcode(0x2B, 0x1B); | |
| 9179 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9180 ins_pipe( ialu_reg_long_mem ); | |
| 9181 %} | |
| 9182 | |
| 9183 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9184 match(Set dst (SubL zero dst)); | |
| 9185 effect(KILL cr); | |
| 9186 ins_cost(300); | |
| 9187 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9188 ins_encode( neg_long(dst) ); | |
| 9189 ins_pipe( ialu_reg_reg_long ); | |
| 9190 %} | |
| 9191 | |
| 9192 // And Long Register with Register | |
| 9193 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9194 match(Set dst (AndL dst src)); | |
| 9195 effect(KILL cr); | |
| 9196 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9197 "AND $dst.hi,$src.hi" %} | |
| 9198 opcode(0x23,0x23); | |
| 9199 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9200 ins_pipe( ialu_reg_reg_long ); | |
| 9201 %} | |
| 9202 | |
| 9203 // And Long Register with Immediate | |
| 9204 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9205 match(Set dst (AndL dst src)); | |
| 9206 effect(KILL cr); | |
| 9207 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9208 "AND $dst.hi,$src.hi" %} | |
| 9209 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9210 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9211 ins_pipe( ialu_reg_long ); | |
| 9212 %} | |
| 9213 | |
| 9214 // And Long Register with Memory | |
| 9215 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9216 match(Set dst (AndL dst (LoadL mem))); | |
| 9217 effect(KILL cr); | |
| 9218 ins_cost(125); | |
| 9219 format %{ "AND $dst.lo,$mem\n\t" | |
| 9220 "AND $dst.hi,$mem+4" %} | |
| 9221 opcode(0x23, 0x23); | |
| 9222 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9223 ins_pipe( ialu_reg_long_mem ); | |
| 9224 %} | |
| 9225 | |
| 9226 // Or Long Register with Register | |
| 9227 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9228 match(Set dst (OrL dst src)); | |
| 9229 effect(KILL cr); | |
| 9230 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9231 "OR $dst.hi,$src.hi" %} | |
| 9232 opcode(0x0B,0x0B); | |
| 9233 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9234 ins_pipe( ialu_reg_reg_long ); | |
| 9235 %} | |
| 9236 | |
| 9237 // Or Long Register with Immediate | |
| 9238 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9239 match(Set dst (OrL dst src)); | |
| 9240 effect(KILL cr); | |
| 9241 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9242 "OR $dst.hi,$src.hi" %} | |
| 9243 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9244 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9245 ins_pipe( ialu_reg_long ); | |
| 9246 %} | |
| 9247 | |
| 9248 // Or Long Register with Memory | |
| 9249 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9250 match(Set dst (OrL dst (LoadL mem))); | |
| 9251 effect(KILL cr); | |
| 9252 ins_cost(125); | |
| 9253 format %{ "OR $dst.lo,$mem\n\t" | |
| 9254 "OR $dst.hi,$mem+4" %} | |
| 9255 opcode(0x0B,0x0B); | |
| 9256 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9257 ins_pipe( ialu_reg_long_mem ); | |
| 9258 %} | |
| 9259 | |
| 9260 // Xor Long Register with Register | |
| 9261 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9262 match(Set dst (XorL dst src)); | |
| 9263 effect(KILL cr); | |
| 9264 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9265 "XOR $dst.hi,$src.hi" %} | |
| 9266 opcode(0x33,0x33); | |
| 9267 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9268 ins_pipe( ialu_reg_reg_long ); | |
| 9269 %} | |
| 9270 | |
| 403 | 9271 // Xor Long Register with Immediate -1 |
| 9272 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9273 match(Set dst (XorL dst imm)); | |
| 9274 format %{ "NOT $dst.lo\n\t" | |
| 9275 "NOT $dst.hi" %} | |
| 9276 ins_encode %{ | |
| 9277 __ notl($dst$$Register); | |
| 9278 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9279 %} | |
| 9280 ins_pipe( ialu_reg_long ); | |
| 9281 %} | |
| 9282 | |
| 0 | 9283 // Xor Long Register with Immediate |
| 9284 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9285 match(Set dst (XorL dst src)); | |
| 9286 effect(KILL cr); | |
| 9287 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9288 "XOR $dst.hi,$src.hi" %} | |
| 9289 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9290 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9291 ins_pipe( ialu_reg_long ); | |
| 9292 %} | |
| 9293 | |
| 9294 // Xor Long Register with Memory | |
| 9295 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9296 match(Set dst (XorL dst (LoadL mem))); | |
| 9297 effect(KILL cr); | |
| 9298 ins_cost(125); | |
| 9299 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9300 "XOR $dst.hi,$mem+4" %} | |
| 9301 opcode(0x33,0x33); | |
| 9302 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9303 ins_pipe( ialu_reg_long_mem ); | |
| 9304 %} | |
| 9305 | |
| 219 | 9306 // Shift Left Long by 1 |
| 9307 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9308 predicate(UseNewLongLShift); | |
| 9309 match(Set dst (LShiftL dst cnt)); | |
| 9310 effect(KILL cr); | |
| 9311 ins_cost(100); | |
| 9312 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9313 "ADC $dst.hi,$dst.hi" %} | |
| 9314 ins_encode %{ | |
| 9315 __ addl($dst$$Register,$dst$$Register); | |
| 9316 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9317 %} | |
| 9318 ins_pipe( ialu_reg_long ); | |
| 9319 %} | |
| 9320 | |
| 9321 // Shift Left Long by 2 | |
| 9322 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9323 predicate(UseNewLongLShift); | |
| 9324 match(Set dst (LShiftL dst cnt)); | |
| 9325 effect(KILL cr); | |
| 9326 ins_cost(100); | |
| 9327 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9328 "ADC $dst.hi,$dst.hi\n\t" | |
| 9329 "ADD $dst.lo,$dst.lo\n\t" | |
| 9330 "ADC $dst.hi,$dst.hi" %} | |
| 9331 ins_encode %{ | |
| 9332 __ addl($dst$$Register,$dst$$Register); | |
| 9333 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9334 __ addl($dst$$Register,$dst$$Register); | |
| 9335 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9336 %} | |
| 9337 ins_pipe( ialu_reg_long ); | |
| 9338 %} | |
| 9339 | |
| 9340 // Shift Left Long by 3 | |
| 9341 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9342 predicate(UseNewLongLShift); | |
| 9343 match(Set dst (LShiftL dst cnt)); | |
| 9344 effect(KILL cr); | |
| 9345 ins_cost(100); | |
| 9346 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9347 "ADC $dst.hi,$dst.hi\n\t" | |
| 9348 "ADD $dst.lo,$dst.lo\n\t" | |
| 9349 "ADC $dst.hi,$dst.hi\n\t" | |
| 9350 "ADD $dst.lo,$dst.lo\n\t" | |
| 9351 "ADC $dst.hi,$dst.hi" %} | |
| 9352 ins_encode %{ | |
| 9353 __ addl($dst$$Register,$dst$$Register); | |
| 9354 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9355 __ addl($dst$$Register,$dst$$Register); | |
| 9356 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9357 __ addl($dst$$Register,$dst$$Register); | |
| 9358 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9359 %} | |
| 9360 ins_pipe( ialu_reg_long ); | |
| 9361 %} | |
| 9362 | |
| 0 | 9363 // Shift Left Long by 1-31 |
| 9364 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9365 match(Set dst (LShiftL dst cnt)); | |
| 9366 effect(KILL cr); | |
| 9367 ins_cost(200); | |
| 9368 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9369 "SHL $dst.lo,$cnt" %} | |
| 9370 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9371 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9372 ins_pipe( ialu_reg_long ); | |
| 9373 %} | |
| 9374 | |
| 9375 // Shift Left Long by 32-63 | |
| 9376 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9377 match(Set dst (LShiftL dst cnt)); | |
| 9378 effect(KILL cr); | |
| 9379 ins_cost(300); | |
| 9380 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9381 "\tSHL $dst.hi,$cnt-32\n" | |
| 9382 "\tXOR $dst.lo,$dst.lo" %} | |
| 9383 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9384 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9385 ins_pipe( ialu_reg_long ); | |
| 9386 %} | |
| 9387 | |
| 9388 // Shift Left Long by variable | |
| 9389 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9390 match(Set dst (LShiftL dst shift)); | |
| 9391 effect(KILL cr); | |
| 9392 ins_cost(500+200); | |
| 9393 size(17); | |
| 9394 format %{ "TEST $shift,32\n\t" | |
| 9395 "JEQ,s small\n\t" | |
| 9396 "MOV $dst.hi,$dst.lo\n\t" | |
| 9397 "XOR $dst.lo,$dst.lo\n" | |
| 9398 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9399 "SHL $dst.lo,$shift" %} | |
| 9400 ins_encode( shift_left_long( dst, shift ) ); | |
| 9401 ins_pipe( pipe_slow ); | |
| 9402 %} | |
| 9403 | |
| 9404 // Shift Right Long by 1-31 | |
| 9405 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9406 match(Set dst (URShiftL dst cnt)); | |
| 9407 effect(KILL cr); | |
| 9408 ins_cost(200); | |
| 9409 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9410 "SHR $dst.hi,$cnt" %} | |
| 9411 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9412 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9413 ins_pipe( ialu_reg_long ); | |
| 9414 %} | |
| 9415 | |
| 9416 // Shift Right Long by 32-63 | |
| 9417 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9418 match(Set dst (URShiftL dst cnt)); | |
| 9419 effect(KILL cr); | |
| 9420 ins_cost(300); | |
| 9421 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9422 "\tSHR $dst.lo,$cnt-32\n" | |
| 9423 "\tXOR $dst.hi,$dst.hi" %} | |
| 9424 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9425 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9426 ins_pipe( ialu_reg_long ); | |
| 9427 %} | |
| 9428 | |
| 9429 // Shift Right Long by variable | |
| 9430 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9431 match(Set dst (URShiftL dst shift)); | |
| 9432 effect(KILL cr); | |
| 9433 ins_cost(600); | |
| 9434 size(17); | |
| 9435 format %{ "TEST $shift,32\n\t" | |
| 9436 "JEQ,s small\n\t" | |
| 9437 "MOV $dst.lo,$dst.hi\n\t" | |
| 9438 "XOR $dst.hi,$dst.hi\n" | |
| 9439 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9440 "SHR $dst.hi,$shift" %} | |
| 9441 ins_encode( shift_right_long( dst, shift ) ); | |
| 9442 ins_pipe( pipe_slow ); | |
| 9443 %} | |
| 9444 | |
| 9445 // Shift Right Long by 1-31 | |
| 9446 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9447 match(Set dst (RShiftL dst cnt)); | |
| 9448 effect(KILL cr); | |
| 9449 ins_cost(200); | |
| 9450 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9451 "SAR $dst.hi,$cnt" %} | |
| 9452 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9453 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9454 ins_pipe( ialu_reg_long ); | |
| 9455 %} | |
| 9456 | |
| 9457 // Shift Right Long by 32-63 | |
| 9458 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9459 match(Set dst (RShiftL dst cnt)); | |
| 9460 effect(KILL cr); | |
| 9461 ins_cost(300); | |
| 9462 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9463 "\tSAR $dst.lo,$cnt-32\n" | |
| 9464 "\tSAR $dst.hi,31" %} | |
| 9465 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9466 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9467 ins_pipe( ialu_reg_long ); | |
| 9468 %} | |
| 9469 | |
| 9470 // Shift Right arithmetic Long by variable | |
| 9471 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9472 match(Set dst (RShiftL dst shift)); | |
| 9473 effect(KILL cr); | |
| 9474 ins_cost(600); | |
| 9475 size(18); | |
| 9476 format %{ "TEST $shift,32\n\t" | |
| 9477 "JEQ,s small\n\t" | |
| 9478 "MOV $dst.lo,$dst.hi\n\t" | |
| 9479 "SAR $dst.hi,31\n" | |
| 9480 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9481 "SAR $dst.hi,$shift" %} | |
| 9482 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9483 ins_pipe( pipe_slow ); | |
| 9484 %} | |
| 9485 | |
| 9486 | |
| 9487 //----------Double Instructions------------------------------------------------ | |
| 9488 // Double Math | |
| 9489 | |
| 9490 // Compare & branch | |
| 9491 | |
| 9492 // P6 version of float compare, sets condition codes in EFLAGS | |
| 9493 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9494 predicate(VM_Version::supports_cmov() && UseSSE <=1); | |
| 9495 match(Set cr (CmpD src1 src2)); | |
| 9496 effect(KILL rax); | |
| 9497 ins_cost(150); | |
| 9498 format %{ "FLD $src1\n\t" | |
| 9499 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9500 "JNP exit\n\t" | |
| 9501 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9502 "SAHF\n" | |
| 9503 "exit:\tNOP // avoid branch to branch" %} | |
| 9504 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 9505 ins_encode( Push_Reg_D(src1), | |
| 9506 OpcP, RegOpc(src2), | |
| 9507 cmpF_P6_fixup ); | |
| 9508 ins_pipe( pipe_slow ); | |
| 9509 %} | |
| 9510 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9511 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9512 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9513 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9514 ins_cost(150); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9515 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9516 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9517 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9518 ins_encode( Push_Reg_D(src1), |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9519 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9520 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9521 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9522 |
| 0 | 9523 // Compare & branch |
| 9524 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9525 predicate(UseSSE<=1); | |
| 9526 match(Set cr (CmpD src1 src2)); | |
| 9527 effect(KILL rax); | |
| 9528 ins_cost(200); | |
| 9529 format %{ "FLD $src1\n\t" | |
| 9530 "FCOMp $src2\n\t" | |
| 9531 "FNSTSW AX\n\t" | |
| 9532 "TEST AX,0x400\n\t" | |
| 9533 "JZ,s flags\n\t" | |
| 9534 "MOV AH,1\t# unordered treat as LT\n" | |
| 9535 "flags:\tSAHF" %} | |
| 9536 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 9537 ins_encode( Push_Reg_D(src1), | |
| 9538 OpcP, RegOpc(src2), | |
| 9539 fpu_flags); | |
| 9540 ins_pipe( pipe_slow ); | |
| 9541 %} | |
| 9542 | |
| 9543 // Compare vs zero into -1,0,1 | |
| 9544 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 9545 predicate(UseSSE<=1); | |
| 9546 match(Set dst (CmpD3 src1 zero)); | |
| 9547 effect(KILL cr, KILL rax); | |
| 9548 ins_cost(280); | |
| 9549 format %{ "FTSTD $dst,$src1" %} | |
| 9550 opcode(0xE4, 0xD9); | |
| 9551 ins_encode( Push_Reg_D(src1), | |
| 9552 OpcS, OpcP, PopFPU, | |
| 9553 CmpF_Result(dst)); | |
| 9554 ins_pipe( pipe_slow ); | |
| 9555 %} | |
| 9556 | |
| 9557 // Compare into -1,0,1 | |
| 9558 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 9559 predicate(UseSSE<=1); | |
| 9560 match(Set dst (CmpD3 src1 src2)); | |
| 9561 effect(KILL cr, KILL rax); | |
| 9562 ins_cost(300); | |
| 9563 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9564 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 9565 ins_encode( Push_Reg_D(src1), | |
| 9566 OpcP, RegOpc(src2), | |
| 9567 CmpF_Result(dst)); | |
| 9568 ins_pipe( pipe_slow ); | |
| 9569 %} | |
| 9570 | |
| 9571 // float compare and set condition codes in EFLAGS by XMM regs | |
| 9572 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ | |
| 9573 predicate(UseSSE>=2); | |
| 9574 match(Set cr (CmpD dst src)); | |
| 9575 effect(KILL rax); | |
| 9576 ins_cost(125); | |
| 9577 format %{ "COMISD $dst,$src\n" | |
| 9578 "\tJNP exit\n" | |
| 9579 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 9580 "\tSAHF\n" | |
| 9581 "exit:\tNOP // avoid branch to branch" %} | |
| 9582 opcode(0x66, 0x0F, 0x2F); | |
| 9583 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); | |
| 9584 ins_pipe( pipe_slow ); | |
| 9585 %} | |
| 9586 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9587 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9588 predicate(UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9589 match(Set cr (CmpD dst src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9590 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9591 format %{ "COMISD $dst,$src" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9592 opcode(0x66, 0x0F, 0x2F); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9593 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9594 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9595 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9596 |
| 0 | 9597 // float compare and set condition codes in EFLAGS by XMM regs |
| 9598 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ | |
| 9599 predicate(UseSSE>=2); | |
| 9600 match(Set cr (CmpD dst (LoadD src))); | |
| 9601 effect(KILL rax); | |
| 9602 ins_cost(145); | |
| 9603 format %{ "COMISD $dst,$src\n" | |
| 9604 "\tJNP exit\n" | |
| 9605 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 9606 "\tSAHF\n" | |
| 9607 "exit:\tNOP // avoid branch to branch" %} | |
| 9608 opcode(0x66, 0x0F, 0x2F); | |
| 9609 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); | |
| 9610 ins_pipe( pipe_slow ); | |
| 9611 %} | |
| 9612 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9613 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9614 predicate(UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9615 match(Set cr (CmpD dst (LoadD src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9616 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9617 format %{ "COMISD $dst,$src" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9618 opcode(0x66, 0x0F, 0x2F); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9619 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9620 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9621 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9622 |
| 0 | 9623 // Compare into -1,0,1 in XMM |
| 9624 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ | |
| 9625 predicate(UseSSE>=2); | |
| 9626 match(Set dst (CmpD3 src1 src2)); | |
| 9627 effect(KILL cr); | |
| 9628 ins_cost(255); | |
| 9629 format %{ "XOR $dst,$dst\n" | |
| 9630 "\tCOMISD $src1,$src2\n" | |
| 9631 "\tJP,s nan\n" | |
| 9632 "\tJEQ,s exit\n" | |
| 9633 "\tJA,s inc\n" | |
| 9634 "nan:\tDEC $dst\n" | |
| 9635 "\tJMP,s exit\n" | |
| 9636 "inc:\tINC $dst\n" | |
| 9637 "exit:" | |
| 9638 %} | |
| 9639 opcode(0x66, 0x0F, 0x2F); | |
| 9640 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), | |
| 9641 CmpX_Result(dst)); | |
| 9642 ins_pipe( pipe_slow ); | |
| 9643 %} | |
| 9644 | |
| 9645 // Compare into -1,0,1 in XMM and memory | |
| 9646 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ | |
| 9647 predicate(UseSSE>=2); | |
| 9648 match(Set dst (CmpD3 src1 (LoadD mem))); | |
| 9649 effect(KILL cr); | |
| 9650 ins_cost(275); | |
| 9651 format %{ "COMISD $src1,$mem\n" | |
| 9652 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 9653 "\tJP,s nan\n" | |
| 9654 "\tJEQ,s exit\n" | |
| 9655 "\tJA,s inc\n" | |
| 9656 "nan:\tDEC $dst\n" | |
| 9657 "\tJMP,s exit\n" | |
| 9658 "inc:\tINC $dst\n" | |
| 9659 "exit:" | |
| 9660 %} | |
| 9661 opcode(0x66, 0x0F, 0x2F); | |
| 9662 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), | |
| 9663 LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 9664 ins_pipe( pipe_slow ); | |
| 9665 %} | |
| 9666 | |
| 9667 | |
| 9668 instruct subD_reg(regD dst, regD src) %{ | |
| 9669 predicate (UseSSE <=1); | |
| 9670 match(Set dst (SubD dst src)); | |
| 9671 | |
| 9672 format %{ "FLD $src\n\t" | |
| 9673 "DSUBp $dst,ST" %} | |
| 9674 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9675 ins_cost(150); | |
| 9676 ins_encode( Push_Reg_D(src), | |
| 9677 OpcP, RegOpc(dst) ); | |
| 9678 ins_pipe( fpu_reg_reg ); | |
| 9679 %} | |
| 9680 | |
| 9681 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 9682 predicate (UseSSE <=1); | |
| 9683 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9684 ins_cost(250); | |
| 9685 | |
| 9686 format %{ "FLD $src2\n\t" | |
| 9687 "DSUB ST,$src1\n\t" | |
| 9688 "FSTP_D $dst\t# D-round" %} | |
| 9689 opcode(0xD8, 0x5); | |
| 9690 ins_encode( Push_Reg_D(src2), | |
| 9691 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 9692 ins_pipe( fpu_mem_reg_reg ); | |
| 9693 %} | |
| 9694 | |
| 9695 | |
| 9696 instruct subD_reg_mem(regD dst, memory src) %{ | |
| 9697 predicate (UseSSE <=1); | |
| 9698 match(Set dst (SubD dst (LoadD src))); | |
| 9699 ins_cost(150); | |
| 9700 | |
| 9701 format %{ "FLD $src\n\t" | |
| 9702 "DSUBp $dst,ST" %} | |
| 9703 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9704 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9705 OpcP, RegOpc(dst) ); | |
| 9706 ins_pipe( fpu_reg_mem ); | |
| 9707 %} | |
| 9708 | |
| 9709 instruct absD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 9710 predicate (UseSSE<=1); | |
| 9711 match(Set dst (AbsD src)); | |
| 9712 ins_cost(100); | |
| 9713 format %{ "FABS" %} | |
| 9714 opcode(0xE1, 0xD9); | |
| 9715 ins_encode( OpcS, OpcP ); | |
| 9716 ins_pipe( fpu_reg_reg ); | |
| 9717 %} | |
| 9718 | |
| 9719 instruct absXD_reg( regXD dst ) %{ | |
| 9720 predicate(UseSSE>=2); | |
| 9721 match(Set dst (AbsD dst)); | |
| 9722 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} | |
| 9723 ins_encode( AbsXD_encoding(dst)); | |
| 9724 ins_pipe( pipe_slow ); | |
| 9725 %} | |
| 9726 | |
| 9727 instruct negD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 9728 predicate(UseSSE<=1); | |
| 9729 match(Set dst (NegD src)); | |
| 9730 ins_cost(100); | |
| 9731 format %{ "FCHS" %} | |
| 9732 opcode(0xE0, 0xD9); | |
| 9733 ins_encode( OpcS, OpcP ); | |
| 9734 ins_pipe( fpu_reg_reg ); | |
| 9735 %} | |
| 9736 | |
| 9737 instruct negXD_reg( regXD dst ) %{ | |
| 9738 predicate(UseSSE>=2); | |
| 9739 match(Set dst (NegD dst)); | |
| 9740 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} | |
| 9741 ins_encode %{ | |
| 9742 __ xorpd($dst$$XMMRegister, | |
| 9743 ExternalAddress((address)double_signflip_pool)); | |
| 9744 %} | |
| 9745 ins_pipe( pipe_slow ); | |
| 9746 %} | |
| 9747 | |
| 9748 instruct addD_reg(regD dst, regD src) %{ | |
| 9749 predicate(UseSSE<=1); | |
| 9750 match(Set dst (AddD dst src)); | |
| 9751 format %{ "FLD $src\n\t" | |
| 9752 "DADD $dst,ST" %} | |
| 9753 size(4); | |
| 9754 ins_cost(150); | |
| 9755 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 9756 ins_encode( Push_Reg_D(src), | |
| 9757 OpcP, RegOpc(dst) ); | |
| 9758 ins_pipe( fpu_reg_reg ); | |
| 9759 %} | |
| 9760 | |
| 9761 | |
| 9762 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 9763 predicate(UseSSE<=1); | |
| 9764 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9765 ins_cost(250); | |
| 9766 | |
| 9767 format %{ "FLD $src2\n\t" | |
| 9768 "DADD ST,$src1\n\t" | |
| 9769 "FSTP_D $dst\t# D-round" %} | |
| 9770 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
| 9771 ins_encode( Push_Reg_D(src2), | |
| 9772 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 9773 ins_pipe( fpu_mem_reg_reg ); | |
| 9774 %} | |
| 9775 | |
| 9776 | |
| 9777 instruct addD_reg_mem(regD dst, memory src) %{ | |
| 9778 predicate(UseSSE<=1); | |
| 9779 match(Set dst (AddD dst (LoadD src))); | |
| 9780 ins_cost(150); | |
| 9781 | |
| 9782 format %{ "FLD $src\n\t" | |
| 9783 "DADDp $dst,ST" %} | |
| 9784 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9785 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9786 OpcP, RegOpc(dst) ); | |
| 9787 ins_pipe( fpu_reg_mem ); | |
| 9788 %} | |
| 9789 | |
| 9790 // add-to-memory | |
| 9791 instruct addD_mem_reg(memory dst, regD src) %{ | |
| 9792 predicate(UseSSE<=1); | |
| 9793 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9794 ins_cost(150); | |
| 9795 | |
| 9796 format %{ "FLD_D $dst\n\t" | |
| 9797 "DADD ST,$src\n\t" | |
| 9798 "FST_D $dst" %} | |
| 9799 opcode(0xDD, 0x0); | |
| 9800 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9801 Opcode(0xD8), RegOpc(src), | |
| 9802 set_instruction_start, | |
| 9803 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9804 ins_pipe( fpu_reg_mem ); | |
| 9805 %} | |
| 9806 | |
| 9807 instruct addD_reg_imm1(regD dst, immD1 src) %{ | |
| 9808 predicate(UseSSE<=1); | |
| 9809 match(Set dst (AddD dst src)); | |
| 9810 ins_cost(125); | |
| 9811 format %{ "FLD1\n\t" | |
| 9812 "DADDp $dst,ST" %} | |
| 9813 opcode(0xDE, 0x00); | |
| 9814 ins_encode( LdImmD(src), | |
| 9815 OpcP, RegOpc(dst) ); | |
| 9816 ins_pipe( fpu_reg ); | |
| 9817 %} | |
| 9818 | |
| 9819 instruct addD_reg_imm(regD dst, immD src) %{ | |
| 9820 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); | |
| 9821 match(Set dst (AddD dst src)); | |
| 9822 ins_cost(200); | |
| 9823 format %{ "FLD_D [$src]\n\t" | |
| 9824 "DADDp $dst,ST" %} | |
| 9825 opcode(0xDE, 0x00); /* DE /0 */ | |
| 9826 ins_encode( LdImmD(src), | |
| 9827 OpcP, RegOpc(dst)); | |
| 9828 ins_pipe( fpu_reg_mem ); | |
| 9829 %} | |
| 9830 | |
| 9831 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ | |
| 9832 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); | |
| 9833 match(Set dst (RoundDouble (AddD src con))); | |
| 9834 ins_cost(200); | |
| 9835 format %{ "FLD_D [$con]\n\t" | |
| 9836 "DADD ST,$src\n\t" | |
| 9837 "FSTP_D $dst\t# D-round" %} | |
| 9838 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 9839 ins_encode( LdImmD(con), | |
| 9840 OpcP, RegOpc(src), Pop_Mem_D(dst)); | |
| 9841 ins_pipe( fpu_mem_reg_con ); | |
| 9842 %} | |
| 9843 | |
| 9844 // Add two double precision floating point values in xmm | |
| 9845 instruct addXD_reg(regXD dst, regXD src) %{ | |
| 9846 predicate(UseSSE>=2); | |
| 9847 match(Set dst (AddD dst src)); | |
| 9848 format %{ "ADDSD $dst,$src" %} | |
| 9849 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 9850 ins_pipe( pipe_slow ); | |
| 9851 %} | |
| 9852 | |
| 9853 instruct addXD_imm(regXD dst, immXD con) %{ | |
| 9854 predicate(UseSSE>=2); | |
| 9855 match(Set dst (AddD dst con)); | |
| 9856 format %{ "ADDSD $dst,[$con]" %} | |
| 9857 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) ); | |
| 9858 ins_pipe( pipe_slow ); | |
| 9859 %} | |
| 9860 | |
| 9861 instruct addXD_mem(regXD dst, memory mem) %{ | |
| 9862 predicate(UseSSE>=2); | |
| 9863 match(Set dst (AddD dst (LoadD mem))); | |
| 9864 format %{ "ADDSD $dst,$mem" %} | |
| 9865 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); | |
| 9866 ins_pipe( pipe_slow ); | |
| 9867 %} | |
| 9868 | |
| 9869 // Sub two double precision floating point values in xmm | |
| 9870 instruct subXD_reg(regXD dst, regXD src) %{ | |
| 9871 predicate(UseSSE>=2); | |
| 9872 match(Set dst (SubD dst src)); | |
| 9873 format %{ "SUBSD $dst,$src" %} | |
| 9874 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 9875 ins_pipe( pipe_slow ); | |
| 9876 %} | |
| 9877 | |
| 9878 instruct subXD_imm(regXD dst, immXD con) %{ | |
| 9879 predicate(UseSSE>=2); | |
| 9880 match(Set dst (SubD dst con)); | |
| 9881 format %{ "SUBSD $dst,[$con]" %} | |
| 9882 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) ); | |
| 9883 ins_pipe( pipe_slow ); | |
| 9884 %} | |
| 9885 | |
| 9886 instruct subXD_mem(regXD dst, memory mem) %{ | |
| 9887 predicate(UseSSE>=2); | |
| 9888 match(Set dst (SubD dst (LoadD mem))); | |
| 9889 format %{ "SUBSD $dst,$mem" %} | |
| 9890 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 9891 ins_pipe( pipe_slow ); | |
| 9892 %} | |
| 9893 | |
| 9894 // Mul two double precision floating point values in xmm | |
| 9895 instruct mulXD_reg(regXD dst, regXD src) %{ | |
| 9896 predicate(UseSSE>=2); | |
| 9897 match(Set dst (MulD dst src)); | |
| 9898 format %{ "MULSD $dst,$src" %} | |
| 9899 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 9900 ins_pipe( pipe_slow ); | |
| 9901 %} | |
| 9902 | |
| 9903 instruct mulXD_imm(regXD dst, immXD con) %{ | |
| 9904 predicate(UseSSE>=2); | |
| 9905 match(Set dst (MulD dst con)); | |
| 9906 format %{ "MULSD $dst,[$con]" %} | |
| 9907 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) ); | |
| 9908 ins_pipe( pipe_slow ); | |
| 9909 %} | |
| 9910 | |
| 9911 instruct mulXD_mem(regXD dst, memory mem) %{ | |
| 9912 predicate(UseSSE>=2); | |
| 9913 match(Set dst (MulD dst (LoadD mem))); | |
| 9914 format %{ "MULSD $dst,$mem" %} | |
| 9915 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 9916 ins_pipe( pipe_slow ); | |
| 9917 %} | |
| 9918 | |
| 9919 // Div two double precision floating point values in xmm | |
| 9920 instruct divXD_reg(regXD dst, regXD src) %{ | |
| 9921 predicate(UseSSE>=2); | |
| 9922 match(Set dst (DivD dst src)); | |
| 9923 format %{ "DIVSD $dst,$src" %} | |
| 9924 opcode(0xF2, 0x0F, 0x5E); | |
| 9925 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 9926 ins_pipe( pipe_slow ); | |
| 9927 %} | |
| 9928 | |
| 9929 instruct divXD_imm(regXD dst, immXD con) %{ | |
| 9930 predicate(UseSSE>=2); | |
| 9931 match(Set dst (DivD dst con)); | |
| 9932 format %{ "DIVSD $dst,[$con]" %} | |
| 9933 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con)); | |
| 9934 ins_pipe( pipe_slow ); | |
| 9935 %} | |
| 9936 | |
| 9937 instruct divXD_mem(regXD dst, memory mem) %{ | |
| 9938 predicate(UseSSE>=2); | |
| 9939 match(Set dst (DivD dst (LoadD mem))); | |
| 9940 format %{ "DIVSD $dst,$mem" %} | |
| 9941 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 9942 ins_pipe( pipe_slow ); | |
| 9943 %} | |
| 9944 | |
| 9945 | |
| 9946 instruct mulD_reg(regD dst, regD src) %{ | |
| 9947 predicate(UseSSE<=1); | |
| 9948 match(Set dst (MulD dst src)); | |
| 9949 format %{ "FLD $src\n\t" | |
| 9950 "DMULp $dst,ST" %} | |
| 9951 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9952 ins_cost(150); | |
| 9953 ins_encode( Push_Reg_D(src), | |
| 9954 OpcP, RegOpc(dst) ); | |
| 9955 ins_pipe( fpu_reg_reg ); | |
| 9956 %} | |
| 9957 | |
| 9958 // Strict FP instruction biases argument before multiply then | |
| 9959 // biases result to avoid double rounding of subnormals. | |
| 9960 // | |
| 9961 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9962 // load arg2 | |
| 9963 // multiply scaled arg1 by arg2 | |
| 9964 // rescale product by 2^(15360) | |
| 9965 // | |
| 9966 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 9967 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9968 match(Set dst (MulD dst src)); | |
| 9969 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9970 | |
| 9971 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9972 "DMULp $dst,ST\n\t" | |
| 9973 "FLD $src\n\t" | |
| 9974 "DMULp $dst,ST\n\t" | |
| 9975 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9976 "DMULp $dst,ST\n\t" %} | |
| 9977 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9978 ins_encode( strictfp_bias1(dst), | |
| 9979 Push_Reg_D(src), | |
| 9980 OpcP, RegOpc(dst), | |
| 9981 strictfp_bias2(dst) ); | |
| 9982 ins_pipe( fpu_reg_reg ); | |
| 9983 %} | |
| 9984 | |
| 9985 instruct mulD_reg_imm(regD dst, immD src) %{ | |
| 9986 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); | |
| 9987 match(Set dst (MulD dst src)); | |
| 9988 ins_cost(200); | |
| 9989 format %{ "FLD_D [$src]\n\t" | |
| 9990 "DMULp $dst,ST" %} | |
| 9991 opcode(0xDE, 0x1); /* DE /1 */ | |
| 9992 ins_encode( LdImmD(src), | |
| 9993 OpcP, RegOpc(dst) ); | |
| 9994 ins_pipe( fpu_reg_mem ); | |
| 9995 %} | |
| 9996 | |
| 9997 | |
| 9998 instruct mulD_reg_mem(regD dst, memory src) %{ | |
| 9999 predicate( UseSSE<=1 ); | |
| 10000 match(Set dst (MulD dst (LoadD src))); | |
| 10001 ins_cost(200); | |
| 10002 format %{ "FLD_D $src\n\t" | |
| 10003 "DMULp $dst,ST" %} | |
| 10004 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 10005 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10006 OpcP, RegOpc(dst) ); | |
| 10007 ins_pipe( fpu_reg_mem ); | |
| 10008 %} | |
| 10009 | |
| 10010 // | |
| 10011 // Cisc-alternate to reg-reg multiply | |
| 10012 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ | |
| 10013 predicate( UseSSE<=1 ); | |
| 10014 match(Set dst (MulD src (LoadD mem))); | |
| 10015 ins_cost(250); | |
| 10016 format %{ "FLD_D $mem\n\t" | |
| 10017 "DMUL ST,$src\n\t" | |
| 10018 "FSTP_D $dst" %} | |
| 10019 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 10020 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
| 10021 OpcReg_F(src), | |
| 10022 Pop_Reg_D(dst) ); | |
| 10023 ins_pipe( fpu_reg_reg_mem ); | |
| 10024 %} | |
| 10025 | |
| 10026 | |
| 10027 // MACRO3 -- addD a mulD | |
| 10028 // This instruction is a '2-address' instruction in that the result goes | |
| 10029 // back to src2. This eliminates a move from the macro; possibly the | |
| 10030 // register allocator will have to add it back (and maybe not). | |
| 10031 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10032 predicate( UseSSE<=1 ); | |
| 10033 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 10034 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10035 "DMUL ST,$src1\n\t" | |
| 10036 "DADDp $src2,ST" %} | |
| 10037 ins_cost(250); | |
| 10038 opcode(0xDD); /* LoadD DD /0 */ | |
| 10039 ins_encode( Push_Reg_F(src0), | |
| 10040 FMul_ST_reg(src1), | |
| 10041 FAddP_reg_ST(src2) ); | |
| 10042 ins_pipe( fpu_reg_reg_reg ); | |
| 10043 %} | |
| 10044 | |
| 10045 | |
| 10046 // MACRO3 -- subD a mulD | |
| 10047 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10048 predicate( UseSSE<=1 ); | |
| 10049 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 10050 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10051 "DMUL ST,$src1\n\t" | |
| 10052 "DSUBRp $src2,ST" %} | |
| 10053 ins_cost(250); | |
| 10054 ins_encode( Push_Reg_F(src0), | |
| 10055 FMul_ST_reg(src1), | |
| 10056 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 10057 ins_pipe( fpu_reg_reg_reg ); | |
| 10058 %} | |
| 10059 | |
| 10060 | |
| 10061 instruct divD_reg(regD dst, regD src) %{ | |
| 10062 predicate( UseSSE<=1 ); | |
| 10063 match(Set dst (DivD dst src)); | |
| 10064 | |
| 10065 format %{ "FLD $src\n\t" | |
| 10066 "FDIVp $dst,ST" %} | |
| 10067 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10068 ins_cost(150); | |
| 10069 ins_encode( Push_Reg_D(src), | |
| 10070 OpcP, RegOpc(dst) ); | |
| 10071 ins_pipe( fpu_reg_reg ); | |
| 10072 %} | |
| 10073 | |
| 10074 // Strict FP instruction biases argument before division then | |
| 10075 // biases result, to avoid double rounding of subnormals. | |
| 10076 // | |
| 10077 // scale dividend by multiplying dividend by 2^(-15360) | |
| 10078 // load divisor | |
| 10079 // divide scaled dividend by divisor | |
| 10080 // rescale quotient by 2^(15360) | |
| 10081 // | |
| 10082 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10083 predicate (UseSSE<=1); | |
| 10084 match(Set dst (DivD dst src)); | |
| 10085 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10086 ins_cost(01); | |
| 10087 | |
| 10088 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10089 "DMULp $dst,ST\n\t" | |
| 10090 "FLD $src\n\t" | |
| 10091 "FDIVp $dst,ST\n\t" | |
| 10092 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10093 "DMULp $dst,ST\n\t" %} | |
| 10094 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10095 ins_encode( strictfp_bias1(dst), | |
| 10096 Push_Reg_D(src), | |
| 10097 OpcP, RegOpc(dst), | |
| 10098 strictfp_bias2(dst) ); | |
| 10099 ins_pipe( fpu_reg_reg ); | |
| 10100 %} | |
| 10101 | |
| 10102 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10103 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); | |
| 10104 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 10105 | |
| 10106 format %{ "FLD $src1\n\t" | |
| 10107 "FDIV ST,$src2\n\t" | |
| 10108 "FSTP_D $dst\t# D-round" %} | |
| 10109 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
| 10110 ins_encode( Push_Reg_D(src1), | |
| 10111 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); | |
| 10112 ins_pipe( fpu_mem_reg_reg ); | |
| 10113 %} | |
| 10114 | |
| 10115 | |
| 10116 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ | |
| 10117 predicate(UseSSE<=1); | |
| 10118 match(Set dst (ModD dst src)); | |
| 10119 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 10120 | |
| 10121 format %{ "DMOD $dst,$src" %} | |
| 10122 ins_cost(250); | |
| 10123 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 10124 emitModD(), | |
| 10125 Push_Result_Mod_D(src), | |
| 10126 Pop_Reg_D(dst)); | |
| 10127 ins_pipe( pipe_slow ); | |
| 10128 %} | |
| 10129 | |
| 10130 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 10131 predicate(UseSSE>=2); | |
| 10132 match(Set dst (ModD src0 src1)); | |
| 10133 effect(KILL rax, KILL cr); | |
| 10134 | |
| 10135 format %{ "SUB ESP,8\t # DMOD\n" | |
| 10136 "\tMOVSD [ESP+0],$src1\n" | |
| 10137 "\tFLD_D [ESP+0]\n" | |
| 10138 "\tMOVSD [ESP+0],$src0\n" | |
| 10139 "\tFLD_D [ESP+0]\n" | |
| 10140 "loop:\tFPREM\n" | |
| 10141 "\tFWAIT\n" | |
| 10142 "\tFNSTSW AX\n" | |
| 10143 "\tSAHF\n" | |
| 10144 "\tJP loop\n" | |
| 10145 "\tFSTP_D [ESP+0]\n" | |
| 10146 "\tMOVSD $dst,[ESP+0]\n" | |
| 10147 "\tADD ESP,8\n" | |
| 10148 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10149 %} | |
| 10150 ins_cost(250); | |
| 10151 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); | |
| 10152 ins_pipe( pipe_slow ); | |
| 10153 %} | |
| 10154 | |
| 10155 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10156 predicate (UseSSE<=1); | |
| 10157 match(Set dst (SinD src)); | |
| 10158 ins_cost(1800); | |
| 10159 format %{ "DSIN $dst" %} | |
| 10160 opcode(0xD9, 0xFE); | |
| 10161 ins_encode( OpcP, OpcS ); | |
| 10162 ins_pipe( pipe_slow ); | |
| 10163 %} | |
| 10164 | |
| 10165 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10166 predicate (UseSSE>=2); | |
| 10167 match(Set dst (SinD dst)); | |
| 10168 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10169 ins_cost(1800); | |
| 10170 format %{ "DSIN $dst" %} | |
| 10171 opcode(0xD9, 0xFE); | |
| 10172 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10173 ins_pipe( pipe_slow ); | |
| 10174 %} | |
| 10175 | |
| 10176 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10177 predicate (UseSSE<=1); | |
| 10178 match(Set dst (CosD src)); | |
| 10179 ins_cost(1800); | |
| 10180 format %{ "DCOS $dst" %} | |
| 10181 opcode(0xD9, 0xFF); | |
| 10182 ins_encode( OpcP, OpcS ); | |
| 10183 ins_pipe( pipe_slow ); | |
| 10184 %} | |
| 10185 | |
| 10186 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10187 predicate (UseSSE>=2); | |
| 10188 match(Set dst (CosD dst)); | |
| 10189 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10190 ins_cost(1800); | |
| 10191 format %{ "DCOS $dst" %} | |
| 10192 opcode(0xD9, 0xFF); | |
| 10193 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10194 ins_pipe( pipe_slow ); | |
| 10195 %} | |
| 10196 | |
| 10197 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10198 predicate (UseSSE<=1); | |
| 10199 match(Set dst(TanD src)); | |
| 10200 format %{ "DTAN $dst" %} | |
| 10201 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10202 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10203 ins_pipe( pipe_slow ); | |
| 10204 %} | |
| 10205 | |
| 10206 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10207 predicate (UseSSE>=2); | |
| 10208 match(Set dst(TanD dst)); | |
| 10209 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10210 format %{ "DTAN $dst" %} | |
| 10211 ins_encode( Push_SrcXD(dst), | |
| 10212 Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10213 Opcode(0xDD), Opcode(0xD8), // fstp st | |
| 10214 Push_ResultXD(dst) ); | |
| 10215 ins_pipe( pipe_slow ); | |
| 10216 %} | |
| 10217 | |
| 10218 instruct atanD_reg(regD dst, regD src) %{ | |
| 10219 predicate (UseSSE<=1); | |
| 10220 match(Set dst(AtanD dst src)); | |
| 10221 format %{ "DATA $dst,$src" %} | |
| 10222 opcode(0xD9, 0xF3); | |
| 10223 ins_encode( Push_Reg_D(src), | |
| 10224 OpcP, OpcS, RegOpc(dst) ); | |
| 10225 ins_pipe( pipe_slow ); | |
| 10226 %} | |
| 10227 | |
| 10228 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10229 predicate (UseSSE>=2); | |
| 10230 match(Set dst(AtanD dst src)); | |
| 10231 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10232 format %{ "DATA $dst,$src" %} | |
| 10233 opcode(0xD9, 0xF3); | |
| 10234 ins_encode( Push_SrcXD(src), | |
| 10235 OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10236 ins_pipe( pipe_slow ); | |
| 10237 %} | |
| 10238 | |
| 10239 instruct sqrtD_reg(regD dst, regD src) %{ | |
| 10240 predicate (UseSSE<=1); | |
| 10241 match(Set dst (SqrtD src)); | |
| 10242 format %{ "DSQRT $dst,$src" %} | |
| 10243 opcode(0xFA, 0xD9); | |
| 10244 ins_encode( Push_Reg_D(src), | |
| 10245 OpcS, OpcP, Pop_Reg_D(dst) ); | |
| 10246 ins_pipe( pipe_slow ); | |
| 10247 %} | |
| 10248 | |
| 10249 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10250 predicate (UseSSE<=1); | |
| 10251 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
| 10252 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10253 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10254 "FLD_D $X\n\t" | |
| 10255 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10256 | |
| 10257 "FDUP \t\t\t# Q Q\n\t" | |
| 10258 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10259 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10260 "FISTP dword [ESP]\n\t" | |
| 10261 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10262 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10263 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10264 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10265 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10266 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10267 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10268 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10269 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10270 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10271 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10272 "MOV [ESP+0],0\n\t" | |
| 10273 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10274 | |
| 10275 "ADD ESP,8" | |
| 10276 %} | |
| 10277 ins_encode( push_stack_temp_qword, | |
| 10278 Push_Reg_D(X), | |
| 10279 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10280 pow_exp_core_encoding, | |
| 10281 pop_stack_temp_qword); | |
| 10282 ins_pipe( pipe_slow ); | |
| 10283 %} | |
| 10284 | |
| 10285 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ | |
| 10286 predicate (UseSSE>=2); | |
| 10287 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
| 10288 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); | |
| 10289 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10290 "MOVSD [ESP],$src1\n\t" | |
| 10291 "FLD FPR1,$src1\n\t" | |
| 10292 "MOVSD [ESP],$src0\n\t" | |
| 10293 "FLD FPR1,$src0\n\t" | |
| 10294 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10295 | |
| 10296 "FDUP \t\t\t# Q Q\n\t" | |
| 10297 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10298 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10299 "FISTP dword [ESP]\n\t" | |
| 10300 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10301 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10302 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10303 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10304 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10305 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10306 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10307 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10308 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10309 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10310 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10311 "MOV [ESP+0],0\n\t" | |
| 10312 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10313 | |
| 10314 "FST_D [ESP]\n\t" | |
| 10315 "MOVSD $dst,[ESP]\n\t" | |
| 10316 "ADD ESP,8" | |
| 10317 %} | |
| 10318 ins_encode( push_stack_temp_qword, | |
| 10319 push_xmm_to_fpr1(src1), | |
| 10320 push_xmm_to_fpr1(src0), | |
| 10321 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10322 pow_exp_core_encoding, | |
| 10323 Push_ResultXD(dst) ); | |
| 10324 ins_pipe( pipe_slow ); | |
| 10325 %} | |
| 10326 | |
| 10327 | |
| 10328 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10329 predicate (UseSSE<=1); | |
| 10330 match(Set dpr1 (ExpD dpr1)); | |
| 10331 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10332 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" | |
| 10333 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10334 "FMULP \t\t\t# Q=X*log2(e)\n\t" | |
| 10335 | |
| 10336 "FDUP \t\t\t# Q Q\n\t" | |
| 10337 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10338 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10339 "FISTP dword [ESP]\n\t" | |
| 10340 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10341 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10342 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10343 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10344 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10345 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10346 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10347 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10348 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10349 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10350 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10351 "MOV [ESP+0],0\n\t" | |
| 10352 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10353 | |
| 10354 "ADD ESP,8" | |
| 10355 %} | |
| 10356 ins_encode( push_stack_temp_qword, | |
| 10357 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10358 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10359 pow_exp_core_encoding, | |
| 10360 pop_stack_temp_qword); | |
| 10361 ins_pipe( pipe_slow ); | |
| 10362 %} | |
| 10363 | |
| 10364 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10365 predicate (UseSSE>=2); | |
| 10366 match(Set dst (ExpD src)); | |
| 10367 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); | |
| 10368 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" | |
| 10369 "MOVSD [ESP],$src\n\t" | |
| 10370 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10371 "FMULP \t\t\t# Q=X*log2(e) X\n\t" | |
| 10372 | |
| 10373 "FDUP \t\t\t# Q Q\n\t" | |
| 10374 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10375 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10376 "FISTP dword [ESP]\n\t" | |
| 10377 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10378 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10379 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10380 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10381 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10382 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10383 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10384 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10385 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10386 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10387 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10388 "MOV [ESP+0],0\n\t" | |
| 10389 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10390 | |
| 10391 "FST_D [ESP]\n\t" | |
| 10392 "MOVSD $dst,[ESP]\n\t" | |
| 10393 "ADD ESP,8" | |
| 10394 %} | |
| 10395 ins_encode( Push_SrcXD(src), | |
| 10396 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10397 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10398 pow_exp_core_encoding, | |
| 10399 Push_ResultXD(dst) ); | |
| 10400 ins_pipe( pipe_slow ); | |
| 10401 %} | |
| 10402 | |
| 10403 | |
| 10404 | |
| 10405 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10406 predicate (UseSSE<=1); | |
| 10407 // The source Double operand on FPU stack | |
| 10408 match(Set dst (Log10D src)); | |
| 10409 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10410 // fxch ; swap ST(0) with ST(1) | |
| 10411 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10412 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10413 "FXCH \n\t" | |
| 10414 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10415 %} | |
| 10416 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10417 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10418 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10419 | |
| 10420 ins_pipe( pipe_slow ); | |
| 10421 %} | |
| 10422 | |
| 10423 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10424 predicate (UseSSE>=2); | |
| 10425 effect(KILL cr); | |
| 10426 match(Set dst (Log10D src)); | |
| 10427 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10428 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10429 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10430 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10431 %} | |
| 10432 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10433 Push_SrcXD(src), | |
| 10434 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10435 Push_ResultXD(dst)); | |
| 10436 | |
| 10437 ins_pipe( pipe_slow ); | |
| 10438 %} | |
| 10439 | |
| 10440 instruct logD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10441 predicate (UseSSE<=1); | |
| 10442 // The source Double operand on FPU stack | |
| 10443 match(Set dst (LogD src)); | |
| 10444 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10445 // fxch ; swap ST(0) with ST(1) | |
| 10446 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10447 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10448 "FXCH \n\t" | |
| 10449 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10450 %} | |
| 10451 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10452 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10453 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10454 | |
| 10455 ins_pipe( pipe_slow ); | |
| 10456 %} | |
| 10457 | |
| 10458 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10459 predicate (UseSSE>=2); | |
| 10460 effect(KILL cr); | |
| 10461 // The source and result Double operands in XMM registers | |
| 10462 match(Set dst (LogD src)); | |
| 10463 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10464 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10465 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10466 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10467 %} | |
| 10468 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10469 Push_SrcXD(src), | |
| 10470 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10471 Push_ResultXD(dst)); | |
| 10472 ins_pipe( pipe_slow ); | |
| 10473 %} | |
| 10474 | |
| 10475 //-------------Float Instructions------------------------------- | |
| 10476 // Float Math | |
| 10477 | |
| 10478 // Code for float compare: | |
| 10479 // fcompp(); | |
| 10480 // fwait(); fnstsw_ax(); | |
| 10481 // sahf(); | |
| 10482 // movl(dst, unordered_result); | |
| 10483 // jcc(Assembler::parity, exit); | |
| 10484 // movl(dst, less_result); | |
| 10485 // jcc(Assembler::below, exit); | |
| 10486 // movl(dst, equal_result); | |
| 10487 // jcc(Assembler::equal, exit); | |
| 10488 // movl(dst, greater_result); | |
| 10489 // exit: | |
| 10490 | |
| 10491 // P6 version of float compare, sets condition codes in EFLAGS | |
| 10492 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 10493 predicate(VM_Version::supports_cmov() && UseSSE == 0); | |
| 10494 match(Set cr (CmpF src1 src2)); | |
| 10495 effect(KILL rax); | |
| 10496 ins_cost(150); | |
| 10497 format %{ "FLD $src1\n\t" | |
| 10498 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10499 "JNP exit\n\t" | |
| 10500 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10501 "SAHF\n" | |
| 10502 "exit:\tNOP // avoid branch to branch" %} | |
| 10503 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 10504 ins_encode( Push_Reg_D(src1), | |
| 10505 OpcP, RegOpc(src2), | |
| 10506 cmpF_P6_fixup ); | |
| 10507 ins_pipe( pipe_slow ); | |
| 10508 %} | |
| 10509 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10510 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10511 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10512 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10513 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10514 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10515 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10516 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10517 ins_encode( Push_Reg_D(src1), |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10518 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10519 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10520 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10521 |
| 0 | 10522 |
| 10523 // Compare & branch | |
| 10524 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 10525 predicate(UseSSE == 0); | |
| 10526 match(Set cr (CmpF src1 src2)); | |
| 10527 effect(KILL rax); | |
| 10528 ins_cost(200); | |
| 10529 format %{ "FLD $src1\n\t" | |
| 10530 "FCOMp $src2\n\t" | |
| 10531 "FNSTSW AX\n\t" | |
| 10532 "TEST AX,0x400\n\t" | |
| 10533 "JZ,s flags\n\t" | |
| 10534 "MOV AH,1\t# unordered treat as LT\n" | |
| 10535 "flags:\tSAHF" %} | |
| 10536 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10537 ins_encode( Push_Reg_D(src1), | |
| 10538 OpcP, RegOpc(src2), | |
| 10539 fpu_flags); | |
| 10540 ins_pipe( pipe_slow ); | |
| 10541 %} | |
| 10542 | |
| 10543 // Compare vs zero into -1,0,1 | |
| 10544 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 10545 predicate(UseSSE == 0); | |
| 10546 match(Set dst (CmpF3 src1 zero)); | |
| 10547 effect(KILL cr, KILL rax); | |
| 10548 ins_cost(280); | |
| 10549 format %{ "FTSTF $dst,$src1" %} | |
| 10550 opcode(0xE4, 0xD9); | |
| 10551 ins_encode( Push_Reg_D(src1), | |
| 10552 OpcS, OpcP, PopFPU, | |
| 10553 CmpF_Result(dst)); | |
| 10554 ins_pipe( pipe_slow ); | |
| 10555 %} | |
| 10556 | |
| 10557 // Compare into -1,0,1 | |
| 10558 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 10559 predicate(UseSSE == 0); | |
| 10560 match(Set dst (CmpF3 src1 src2)); | |
| 10561 effect(KILL cr, KILL rax); | |
| 10562 ins_cost(300); | |
| 10563 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10564 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10565 ins_encode( Push_Reg_D(src1), | |
| 10566 OpcP, RegOpc(src2), | |
| 10567 CmpF_Result(dst)); | |
| 10568 ins_pipe( pipe_slow ); | |
| 10569 %} | |
| 10570 | |
| 10571 // float compare and set condition codes in EFLAGS by XMM regs | |
| 10572 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ | |
| 10573 predicate(UseSSE>=1); | |
| 10574 match(Set cr (CmpF dst src)); | |
| 10575 effect(KILL rax); | |
| 10576 ins_cost(145); | |
| 10577 format %{ "COMISS $dst,$src\n" | |
| 10578 "\tJNP exit\n" | |
| 10579 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10580 "\tSAHF\n" | |
| 10581 "exit:\tNOP // avoid branch to branch" %} | |
| 10582 opcode(0x0F, 0x2F); | |
| 10583 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); | |
| 10584 ins_pipe( pipe_slow ); | |
| 10585 %} | |
| 10586 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10587 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10588 predicate(UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10589 match(Set cr (CmpF dst src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10590 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10591 format %{ "COMISS $dst,$src" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10592 opcode(0x0F, 0x2F); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10593 ins_encode(OpcP, OpcS, RegReg(dst, src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10594 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10595 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10596 |
| 0 | 10597 // float compare and set condition codes in EFLAGS by XMM regs |
| 10598 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ | |
| 10599 predicate(UseSSE>=1); | |
| 10600 match(Set cr (CmpF dst (LoadF src))); | |
| 10601 effect(KILL rax); | |
| 10602 ins_cost(165); | |
| 10603 format %{ "COMISS $dst,$src\n" | |
| 10604 "\tJNP exit\n" | |
| 10605 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10606 "\tSAHF\n" | |
| 10607 "exit:\tNOP // avoid branch to branch" %} | |
| 10608 opcode(0x0F, 0x2F); | |
| 10609 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); | |
| 10610 ins_pipe( pipe_slow ); | |
| 10611 %} | |
| 10612 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10613 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10614 predicate(UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10615 match(Set cr (CmpF dst (LoadF src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10616 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10617 format %{ "COMISS $dst,$src" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10618 opcode(0x0F, 0x2F); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10619 ins_encode(OpcP, OpcS, RegMem(dst, src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10620 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10621 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10622 |
| 0 | 10623 // Compare into -1,0,1 in XMM |
| 10624 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ | |
| 10625 predicate(UseSSE>=1); | |
| 10626 match(Set dst (CmpF3 src1 src2)); | |
| 10627 effect(KILL cr); | |
| 10628 ins_cost(255); | |
| 10629 format %{ "XOR $dst,$dst\n" | |
| 10630 "\tCOMISS $src1,$src2\n" | |
| 10631 "\tJP,s nan\n" | |
| 10632 "\tJEQ,s exit\n" | |
| 10633 "\tJA,s inc\n" | |
| 10634 "nan:\tDEC $dst\n" | |
| 10635 "\tJMP,s exit\n" | |
| 10636 "inc:\tINC $dst\n" | |
| 10637 "exit:" | |
| 10638 %} | |
| 10639 opcode(0x0F, 0x2F); | |
| 10640 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); | |
| 10641 ins_pipe( pipe_slow ); | |
| 10642 %} | |
| 10643 | |
| 10644 // Compare into -1,0,1 in XMM and memory | |
| 10645 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ | |
| 10646 predicate(UseSSE>=1); | |
| 10647 match(Set dst (CmpF3 src1 (LoadF mem))); | |
| 10648 effect(KILL cr); | |
| 10649 ins_cost(275); | |
| 10650 format %{ "COMISS $src1,$mem\n" | |
| 10651 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 10652 "\tJP,s nan\n" | |
| 10653 "\tJEQ,s exit\n" | |
| 10654 "\tJA,s inc\n" | |
| 10655 "nan:\tDEC $dst\n" | |
| 10656 "\tJMP,s exit\n" | |
| 10657 "inc:\tINC $dst\n" | |
| 10658 "exit:" | |
| 10659 %} | |
| 10660 opcode(0x0F, 0x2F); | |
| 10661 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 10662 ins_pipe( pipe_slow ); | |
| 10663 %} | |
| 10664 | |
| 10665 // Spill to obtain 24-bit precision | |
| 10666 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 10667 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10668 match(Set dst (SubF src1 src2)); | |
| 10669 | |
| 10670 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10671 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
| 10672 ins_encode( Push_Reg_F(src1), | |
| 10673 OpcReg_F(src2), | |
| 10674 Pop_Mem_F(dst) ); | |
| 10675 ins_pipe( fpu_mem_reg_reg ); | |
| 10676 %} | |
| 10677 // | |
| 10678 // This instruction does not round to 24-bits | |
| 10679 instruct subF_reg(regF dst, regF src) %{ | |
| 10680 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 10681 match(Set dst (SubF dst src)); | |
| 10682 | |
| 10683 format %{ "FSUB $dst,$src" %} | |
| 10684 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 10685 ins_encode( Push_Reg_F(src), | |
| 10686 OpcP, RegOpc(dst) ); | |
| 10687 ins_pipe( fpu_reg_reg ); | |
| 10688 %} | |
| 10689 | |
| 10690 // Spill to obtain 24-bit precision | |
| 10691 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 10692 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10693 match(Set dst (AddF src1 src2)); | |
| 10694 | |
| 10695 format %{ "FADD $dst,$src1,$src2" %} | |
| 10696 opcode(0xD8, 0x0); /* D8 C0+i */ | |
| 10697 ins_encode( Push_Reg_F(src2), | |
| 10698 OpcReg_F(src1), | |
| 10699 Pop_Mem_F(dst) ); | |
| 10700 ins_pipe( fpu_mem_reg_reg ); | |
| 10701 %} | |
| 10702 // | |
| 10703 // This instruction does not round to 24-bits | |
| 10704 instruct addF_reg(regF dst, regF src) %{ | |
| 10705 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 10706 match(Set dst (AddF dst src)); | |
| 10707 | |
| 10708 format %{ "FLD $src\n\t" | |
| 10709 "FADDp $dst,ST" %} | |
| 10710 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 10711 ins_encode( Push_Reg_F(src), | |
| 10712 OpcP, RegOpc(dst) ); | |
| 10713 ins_pipe( fpu_reg_reg ); | |
| 10714 %} | |
| 10715 | |
| 10716 // Add two single precision floating point values in xmm | |
| 10717 instruct addX_reg(regX dst, regX src) %{ | |
| 10718 predicate(UseSSE>=1); | |
| 10719 match(Set dst (AddF dst src)); | |
| 10720 format %{ "ADDSS $dst,$src" %} | |
| 10721 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 10722 ins_pipe( pipe_slow ); | |
| 10723 %} | |
| 10724 | |
| 10725 instruct addX_imm(regX dst, immXF con) %{ | |
| 10726 predicate(UseSSE>=1); | |
| 10727 match(Set dst (AddF dst con)); | |
| 10728 format %{ "ADDSS $dst,[$con]" %} | |
| 10729 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) ); | |
| 10730 ins_pipe( pipe_slow ); | |
| 10731 %} | |
| 10732 | |
| 10733 instruct addX_mem(regX dst, memory mem) %{ | |
| 10734 predicate(UseSSE>=1); | |
| 10735 match(Set dst (AddF dst (LoadF mem))); | |
| 10736 format %{ "ADDSS $dst,$mem" %} | |
| 10737 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); | |
| 10738 ins_pipe( pipe_slow ); | |
| 10739 %} | |
| 10740 | |
| 10741 // Subtract two single precision floating point values in xmm | |
| 10742 instruct subX_reg(regX dst, regX src) %{ | |
| 10743 predicate(UseSSE>=1); | |
| 10744 match(Set dst (SubF dst src)); | |
| 10745 format %{ "SUBSS $dst,$src" %} | |
| 10746 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 10747 ins_pipe( pipe_slow ); | |
| 10748 %} | |
| 10749 | |
| 10750 instruct subX_imm(regX dst, immXF con) %{ | |
| 10751 predicate(UseSSE>=1); | |
| 10752 match(Set dst (SubF dst con)); | |
| 10753 format %{ "SUBSS $dst,[$con]" %} | |
| 10754 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) ); | |
| 10755 ins_pipe( pipe_slow ); | |
| 10756 %} | |
| 10757 | |
| 10758 instruct subX_mem(regX dst, memory mem) %{ | |
| 10759 predicate(UseSSE>=1); | |
| 10760 match(Set dst (SubF dst (LoadF mem))); | |
| 10761 format %{ "SUBSS $dst,$mem" %} | |
| 10762 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 10763 ins_pipe( pipe_slow ); | |
| 10764 %} | |
| 10765 | |
| 10766 // Multiply two single precision floating point values in xmm | |
| 10767 instruct mulX_reg(regX dst, regX src) %{ | |
| 10768 predicate(UseSSE>=1); | |
| 10769 match(Set dst (MulF dst src)); | |
| 10770 format %{ "MULSS $dst,$src" %} | |
| 10771 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 10772 ins_pipe( pipe_slow ); | |
| 10773 %} | |
| 10774 | |
| 10775 instruct mulX_imm(regX dst, immXF con) %{ | |
| 10776 predicate(UseSSE>=1); | |
| 10777 match(Set dst (MulF dst con)); | |
| 10778 format %{ "MULSS $dst,[$con]" %} | |
| 10779 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) ); | |
| 10780 ins_pipe( pipe_slow ); | |
| 10781 %} | |
| 10782 | |
| 10783 instruct mulX_mem(regX dst, memory mem) %{ | |
| 10784 predicate(UseSSE>=1); | |
| 10785 match(Set dst (MulF dst (LoadF mem))); | |
| 10786 format %{ "MULSS $dst,$mem" %} | |
| 10787 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 10788 ins_pipe( pipe_slow ); | |
| 10789 %} | |
| 10790 | |
| 10791 // Divide two single precision floating point values in xmm | |
| 10792 instruct divX_reg(regX dst, regX src) %{ | |
| 10793 predicate(UseSSE>=1); | |
| 10794 match(Set dst (DivF dst src)); | |
| 10795 format %{ "DIVSS $dst,$src" %} | |
| 10796 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 10797 ins_pipe( pipe_slow ); | |
| 10798 %} | |
| 10799 | |
| 10800 instruct divX_imm(regX dst, immXF con) %{ | |
| 10801 predicate(UseSSE>=1); | |
| 10802 match(Set dst (DivF dst con)); | |
| 10803 format %{ "DIVSS $dst,[$con]" %} | |
| 10804 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) ); | |
| 10805 ins_pipe( pipe_slow ); | |
| 10806 %} | |
| 10807 | |
| 10808 instruct divX_mem(regX dst, memory mem) %{ | |
| 10809 predicate(UseSSE>=1); | |
| 10810 match(Set dst (DivF dst (LoadF mem))); | |
| 10811 format %{ "DIVSS $dst,$mem" %} | |
| 10812 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 10813 ins_pipe( pipe_slow ); | |
| 10814 %} | |
| 10815 | |
| 10816 // Get the square root of a single precision floating point values in xmm | |
| 10817 instruct sqrtX_reg(regX dst, regX src) %{ | |
| 10818 predicate(UseSSE>=1); | |
| 10819 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10820 format %{ "SQRTSS $dst,$src" %} | |
| 10821 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 10822 ins_pipe( pipe_slow ); | |
| 10823 %} | |
| 10824 | |
| 10825 instruct sqrtX_mem(regX dst, memory mem) %{ | |
| 10826 predicate(UseSSE>=1); | |
| 10827 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); | |
| 10828 format %{ "SQRTSS $dst,$mem" %} | |
| 10829 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 10830 ins_pipe( pipe_slow ); | |
| 10831 %} | |
| 10832 | |
| 10833 // Get the square root of a double precision floating point values in xmm | |
| 10834 instruct sqrtXD_reg(regXD dst, regXD src) %{ | |
| 10835 predicate(UseSSE>=2); | |
| 10836 match(Set dst (SqrtD src)); | |
| 10837 format %{ "SQRTSD $dst,$src" %} | |
| 10838 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 10839 ins_pipe( pipe_slow ); | |
| 10840 %} | |
| 10841 | |
| 10842 instruct sqrtXD_mem(regXD dst, memory mem) %{ | |
| 10843 predicate(UseSSE>=2); | |
| 10844 match(Set dst (SqrtD (LoadD mem))); | |
| 10845 format %{ "SQRTSD $dst,$mem" %} | |
| 10846 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 10847 ins_pipe( pipe_slow ); | |
| 10848 %} | |
| 10849 | |
| 10850 instruct absF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 10851 predicate(UseSSE==0); | |
| 10852 match(Set dst (AbsF src)); | |
| 10853 ins_cost(100); | |
| 10854 format %{ "FABS" %} | |
| 10855 opcode(0xE1, 0xD9); | |
| 10856 ins_encode( OpcS, OpcP ); | |
| 10857 ins_pipe( fpu_reg_reg ); | |
| 10858 %} | |
| 10859 | |
| 10860 instruct absX_reg(regX dst ) %{ | |
| 10861 predicate(UseSSE>=1); | |
| 10862 match(Set dst (AbsF dst)); | |
| 10863 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} | |
| 10864 ins_encode( AbsXF_encoding(dst)); | |
| 10865 ins_pipe( pipe_slow ); | |
| 10866 %} | |
| 10867 | |
| 10868 instruct negF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 10869 predicate(UseSSE==0); | |
| 10870 match(Set dst (NegF src)); | |
| 10871 ins_cost(100); | |
| 10872 format %{ "FCHS" %} | |
| 10873 opcode(0xE0, 0xD9); | |
| 10874 ins_encode( OpcS, OpcP ); | |
| 10875 ins_pipe( fpu_reg_reg ); | |
| 10876 %} | |
| 10877 | |
| 10878 instruct negX_reg( regX dst ) %{ | |
| 10879 predicate(UseSSE>=1); | |
| 10880 match(Set dst (NegF dst)); | |
| 10881 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} | |
| 10882 ins_encode( NegXF_encoding(dst)); | |
| 10883 ins_pipe( pipe_slow ); | |
| 10884 %} | |
| 10885 | |
| 10886 // Cisc-alternate to addF_reg | |
| 10887 // Spill to obtain 24-bit precision | |
| 10888 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 10889 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10890 match(Set dst (AddF src1 (LoadF src2))); | |
| 10891 | |
| 10892 format %{ "FLD $src2\n\t" | |
| 10893 "FADD ST,$src1\n\t" | |
| 10894 "FSTP_S $dst" %} | |
| 10895 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10896 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10897 OpcReg_F(src1), | |
| 10898 Pop_Mem_F(dst) ); | |
| 10899 ins_pipe( fpu_mem_reg_mem ); | |
| 10900 %} | |
| 10901 // | |
| 10902 // Cisc-alternate to addF_reg | |
| 10903 // This instruction does not round to 24-bits | |
| 10904 instruct addF_reg_mem(regF dst, memory src) %{ | |
| 10905 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 10906 match(Set dst (AddF dst (LoadF src))); | |
| 10907 | |
| 10908 format %{ "FADD $dst,$src" %} | |
| 10909 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10910 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10911 OpcP, RegOpc(dst) ); | |
| 10912 ins_pipe( fpu_reg_mem ); | |
| 10913 %} | |
| 10914 | |
| 10915 // // Following two instructions for _222_mpegaudio | |
| 10916 // Spill to obtain 24-bit precision | |
| 10917 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ | |
| 10918 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10919 match(Set dst (AddF src1 src2)); | |
| 10920 | |
| 10921 format %{ "FADD $dst,$src1,$src2" %} | |
| 10922 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10923 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
| 10924 OpcReg_F(src2), | |
| 10925 Pop_Mem_F(dst) ); | |
| 10926 ins_pipe( fpu_mem_reg_mem ); | |
| 10927 %} | |
| 10928 | |
| 10929 // Cisc-spill variant | |
| 10930 // Spill to obtain 24-bit precision | |
| 10931 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ | |
| 10932 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10933 match(Set dst (AddF src1 (LoadF src2))); | |
| 10934 | |
| 10935 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10936 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10937 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10938 set_instruction_start, | |
| 10939 OpcP, RMopc_Mem(secondary,src1), | |
| 10940 Pop_Mem_F(dst) ); | |
| 10941 ins_pipe( fpu_mem_mem_mem ); | |
| 10942 %} | |
| 10943 | |
| 10944 // Spill to obtain 24-bit precision | |
| 10945 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 10946 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10947 match(Set dst (AddF src1 src2)); | |
| 10948 | |
| 10949 format %{ "FADD $dst,$src1,$src2" %} | |
| 10950 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10951 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10952 set_instruction_start, | |
| 10953 OpcP, RMopc_Mem(secondary,src1), | |
| 10954 Pop_Mem_F(dst) ); | |
| 10955 ins_pipe( fpu_mem_mem_mem ); | |
| 10956 %} | |
| 10957 | |
| 10958 | |
| 10959 // Spill to obtain 24-bit precision | |
| 10960 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ | |
| 10961 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10962 match(Set dst (AddF src1 src2)); | |
| 10963 format %{ "FLD $src1\n\t" | |
| 10964 "FADD $src2\n\t" | |
| 10965 "FSTP_S $dst" %} | |
| 10966 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 10967 ins_encode( Push_Reg_F(src1), | |
| 10968 Opc_MemImm_F(src2), | |
| 10969 Pop_Mem_F(dst)); | |
| 10970 ins_pipe( fpu_mem_reg_con ); | |
| 10971 %} | |
| 10972 // | |
| 10973 // This instruction does not round to 24-bits | |
| 10974 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{ | |
| 10975 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 10976 match(Set dst (AddF src1 src2)); | |
| 10977 format %{ "FLD $src1\n\t" | |
| 10978 "FADD $src2\n\t" | |
| 10979 "FSTP_S $dst" %} | |
| 10980 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 10981 ins_encode( Push_Reg_F(src1), | |
| 10982 Opc_MemImm_F(src2), | |
| 10983 Pop_Reg_F(dst)); | |
| 10984 ins_pipe( fpu_reg_reg_con ); | |
| 10985 %} | |
| 10986 | |
| 10987 // Spill to obtain 24-bit precision | |
| 10988 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 10989 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10990 match(Set dst (MulF src1 src2)); | |
| 10991 | |
| 10992 format %{ "FLD $src1\n\t" | |
| 10993 "FMUL $src2\n\t" | |
| 10994 "FSTP_S $dst" %} | |
| 10995 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
| 10996 ins_encode( Push_Reg_F(src1), | |
| 10997 OpcReg_F(src2), | |
| 10998 Pop_Mem_F(dst) ); | |
| 10999 ins_pipe( fpu_mem_reg_reg ); | |
| 11000 %} | |
| 11001 // | |
| 11002 // This instruction does not round to 24-bits | |
| 11003 instruct mulF_reg(regF dst, regF src1, regF src2) %{ | |
| 11004 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11005 match(Set dst (MulF src1 src2)); | |
| 11006 | |
| 11007 format %{ "FLD $src1\n\t" | |
| 11008 "FMUL $src2\n\t" | |
| 11009 "FSTP_S $dst" %} | |
| 11010 opcode(0xD8, 0x1); /* D8 C8+i */ | |
| 11011 ins_encode( Push_Reg_F(src2), | |
| 11012 OpcReg_F(src1), | |
| 11013 Pop_Reg_F(dst) ); | |
| 11014 ins_pipe( fpu_reg_reg_reg ); | |
| 11015 %} | |
| 11016 | |
| 11017 | |
| 11018 // Spill to obtain 24-bit precision | |
| 11019 // Cisc-alternate to reg-reg multiply | |
| 11020 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11021 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11022 match(Set dst (MulF src1 (LoadF src2))); | |
| 11023 | |
| 11024 format %{ "FLD_S $src2\n\t" | |
| 11025 "FMUL $src1\n\t" | |
| 11026 "FSTP_S $dst" %} | |
| 11027 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 11028 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11029 OpcReg_F(src1), | |
| 11030 Pop_Mem_F(dst) ); | |
| 11031 ins_pipe( fpu_mem_reg_mem ); | |
| 11032 %} | |
| 11033 // | |
| 11034 // This instruction does not round to 24-bits | |
| 11035 // Cisc-alternate to reg-reg multiply | |
| 11036 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ | |
| 11037 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11038 match(Set dst (MulF src1 (LoadF src2))); | |
| 11039 | |
| 11040 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11041 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 11042 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11043 OpcReg_F(src1), | |
| 11044 Pop_Reg_F(dst) ); | |
| 11045 ins_pipe( fpu_reg_reg_mem ); | |
| 11046 %} | |
| 11047 | |
| 11048 // Spill to obtain 24-bit precision | |
| 11049 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11050 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11051 match(Set dst (MulF src1 src2)); | |
| 11052 | |
| 11053 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11054 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 11055 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11056 set_instruction_start, | |
| 11057 OpcP, RMopc_Mem(secondary,src1), | |
| 11058 Pop_Mem_F(dst) ); | |
| 11059 ins_pipe( fpu_mem_mem_mem ); | |
| 11060 %} | |
| 11061 | |
| 11062 // Spill to obtain 24-bit precision | |
| 11063 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ | |
| 11064 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11065 match(Set dst (MulF src1 src2)); | |
| 11066 | |
| 11067 format %{ "FMULc $dst,$src1,$src2" %} | |
| 11068 opcode(0xD8, 0x1); /* D8 /1*/ | |
| 11069 ins_encode( Push_Reg_F(src1), | |
| 11070 Opc_MemImm_F(src2), | |
| 11071 Pop_Mem_F(dst)); | |
| 11072 ins_pipe( fpu_mem_reg_con ); | |
| 11073 %} | |
| 11074 // | |
| 11075 // This instruction does not round to 24-bits | |
| 11076 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{ | |
| 11077 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11078 match(Set dst (MulF src1 src2)); | |
| 11079 | |
| 11080 format %{ "FMULc $dst. $src1, $src2" %} | |
| 11081 opcode(0xD8, 0x1); /* D8 /1*/ | |
| 11082 ins_encode( Push_Reg_F(src1), | |
| 11083 Opc_MemImm_F(src2), | |
| 11084 Pop_Reg_F(dst)); | |
| 11085 ins_pipe( fpu_reg_reg_con ); | |
| 11086 %} | |
| 11087 | |
| 11088 | |
| 11089 // | |
| 11090 // MACRO1 -- subsume unshared load into mulF | |
| 11091 // This instruction does not round to 24-bits | |
| 11092 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ | |
| 11093 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11094 match(Set dst (MulF (LoadF mem1) src)); | |
| 11095 | |
| 11096 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 11097 "FMUL ST,$src\n\t" | |
| 11098 "FSTP $dst" %} | |
| 11099 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 11100 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
| 11101 OpcReg_F(src), | |
| 11102 Pop_Reg_F(dst) ); | |
| 11103 ins_pipe( fpu_reg_reg_mem ); | |
| 11104 %} | |
| 11105 // | |
| 11106 // MACRO2 -- addF a mulF which subsumed an unshared load | |
| 11107 // This instruction does not round to 24-bits | |
| 11108 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ | |
| 11109 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11110 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 11111 ins_cost(95); | |
| 11112 | |
| 11113 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
| 11114 "FMUL ST,$src1 subsume mulF left load\n\t" | |
| 11115 "FADD ST,$src2\n\t" | |
| 11116 "FSTP $dst" %} | |
| 11117 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11118 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 11119 FMul_ST_reg(src1), | |
| 11120 FAdd_ST_reg(src2), | |
| 11121 Pop_Reg_F(dst) ); | |
| 11122 ins_pipe( fpu_reg_mem_reg_reg ); | |
| 11123 %} | |
| 11124 | |
| 11125 // MACRO3 -- addF a mulF | |
| 11126 // This instruction does not round to 24-bits. It is a '2-address' | |
| 11127 // instruction in that the result goes back to src2. This eliminates | |
| 11128 // a move from the macro; possibly the register allocator will have | |
| 11129 // to add it back (and maybe not). | |
| 11130 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ | |
| 11131 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11132 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 11133 | |
| 11134 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 11135 "FMUL ST,$src1\n\t" | |
| 11136 "FADDP $src2,ST" %} | |
| 11137 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11138 ins_encode( Push_Reg_F(src0), | |
| 11139 FMul_ST_reg(src1), | |
| 11140 FAddP_reg_ST(src2) ); | |
| 11141 ins_pipe( fpu_reg_reg_reg ); | |
| 11142 %} | |
| 11143 | |
| 11144 // MACRO4 -- divF subF | |
| 11145 // This instruction does not round to 24-bits | |
| 11146 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ | |
| 11147 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11148 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 11149 | |
| 11150 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 11151 "FSUB ST,$src1\n\t" | |
| 11152 "FDIV ST,$src3\n\t" | |
| 11153 "FSTP $dst" %} | |
| 11154 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11155 ins_encode( Push_Reg_F(src2), | |
| 11156 subF_divF_encode(src1,src3), | |
| 11157 Pop_Reg_F(dst) ); | |
| 11158 ins_pipe( fpu_reg_reg_reg_reg ); | |
| 11159 %} | |
| 11160 | |
| 11161 // Spill to obtain 24-bit precision | |
| 11162 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11163 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11164 match(Set dst (DivF src1 src2)); | |
| 11165 | |
| 11166 format %{ "FDIV $dst,$src1,$src2" %} | |
| 11167 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
| 11168 ins_encode( Push_Reg_F(src1), | |
| 11169 OpcReg_F(src2), | |
| 11170 Pop_Mem_F(dst) ); | |
| 11171 ins_pipe( fpu_mem_reg_reg ); | |
| 11172 %} | |
| 11173 // | |
| 11174 // This instruction does not round to 24-bits | |
| 11175 instruct divF_reg(regF dst, regF src) %{ | |
| 11176 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11177 match(Set dst (DivF dst src)); | |
| 11178 | |
| 11179 format %{ "FDIV $dst,$src" %} | |
| 11180 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11181 ins_encode( Push_Reg_F(src), | |
| 11182 OpcP, RegOpc(dst) ); | |
| 11183 ins_pipe( fpu_reg_reg ); | |
| 11184 %} | |
| 11185 | |
| 11186 | |
| 11187 // Spill to obtain 24-bit precision | |
| 11188 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11189 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11190 match(Set dst (ModF src1 src2)); | |
| 11191 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11192 | |
| 11193 format %{ "FMOD $dst,$src1,$src2" %} | |
| 11194 ins_encode( Push_Reg_Mod_D(src1, src2), | |
| 11195 emitModD(), | |
| 11196 Push_Result_Mod_D(src2), | |
| 11197 Pop_Mem_F(dst)); | |
| 11198 ins_pipe( pipe_slow ); | |
| 11199 %} | |
| 11200 // | |
| 11201 // This instruction does not round to 24-bits | |
| 11202 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ | |
| 11203 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11204 match(Set dst (ModF dst src)); | |
| 11205 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11206 | |
| 11207 format %{ "FMOD $dst,$src" %} | |
| 11208 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 11209 emitModD(), | |
| 11210 Push_Result_Mod_D(src), | |
| 11211 Pop_Reg_F(dst)); | |
| 11212 ins_pipe( pipe_slow ); | |
| 11213 %} | |
| 11214 | |
| 11215 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 11216 predicate(UseSSE>=1); | |
| 11217 match(Set dst (ModF src0 src1)); | |
| 11218 effect(KILL rax, KILL cr); | |
| 11219 format %{ "SUB ESP,4\t # FMOD\n" | |
| 11220 "\tMOVSS [ESP+0],$src1\n" | |
| 11221 "\tFLD_S [ESP+0]\n" | |
| 11222 "\tMOVSS [ESP+0],$src0\n" | |
| 11223 "\tFLD_S [ESP+0]\n" | |
| 11224 "loop:\tFPREM\n" | |
| 11225 "\tFWAIT\n" | |
| 11226 "\tFNSTSW AX\n" | |
| 11227 "\tSAHF\n" | |
| 11228 "\tJP loop\n" | |
| 11229 "\tFSTP_S [ESP+0]\n" | |
| 11230 "\tMOVSS $dst,[ESP+0]\n" | |
| 11231 "\tADD ESP,4\n" | |
| 11232 "\tFSTP ST0\t # Restore FPU Stack" | |
| 11233 %} | |
| 11234 ins_cost(250); | |
| 11235 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); | |
| 11236 ins_pipe( pipe_slow ); | |
| 11237 %} | |
| 11238 | |
| 11239 | |
| 11240 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 11241 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 11242 | |
| 11243 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ | |
| 11244 predicate(UseSSE==0); | |
| 11245 match(Set dst (RoundFloat src)); | |
| 11246 ins_cost(125); | |
| 11247 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11248 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 11249 ins_pipe( fpu_mem_reg ); | |
| 11250 %} | |
| 11251 | |
| 11252 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ | |
| 11253 predicate(UseSSE<=1); | |
| 11254 match(Set dst (RoundDouble src)); | |
| 11255 ins_cost(125); | |
| 11256 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11257 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 11258 ins_pipe( fpu_mem_reg ); | |
| 11259 %} | |
| 11260 | |
| 11261 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11262 instruct convD2F_reg(stackSlotF dst, regD src) %{ | |
| 11263 predicate(UseSSE==0); | |
| 11264 match(Set dst (ConvD2F src)); | |
| 11265 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11266 expand %{ | |
| 11267 roundFloat_mem_reg(dst,src); | |
| 11268 %} | |
| 11269 %} | |
| 11270 | |
| 11271 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11272 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ | |
| 11273 predicate(UseSSE==1); | |
| 11274 match(Set dst (ConvD2F src)); | |
| 11275 effect( KILL cr ); | |
| 11276 format %{ "SUB ESP,4\n\t" | |
| 11277 "FST_S [ESP],$src\t# F-round\n\t" | |
| 11278 "MOVSS $dst,[ESP]\n\t" | |
| 11279 "ADD ESP,4" %} | |
| 11280 ins_encode( D2X_encoding(dst, src) ); | |
| 11281 ins_pipe( pipe_slow ); | |
| 11282 %} | |
| 11283 | |
| 11284 // Force rounding double precision to single precision | |
| 11285 instruct convXD2X_reg(regX dst, regXD src) %{ | |
| 11286 predicate(UseSSE>=2); | |
| 11287 match(Set dst (ConvD2F src)); | |
| 11288 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 11289 opcode(0xF2, 0x0F, 0x5A); | |
| 11290 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11291 ins_pipe( pipe_slow ); | |
| 11292 %} | |
| 11293 | |
| 11294 instruct convF2D_reg_reg(regD dst, regF src) %{ | |
| 11295 predicate(UseSSE==0); | |
| 11296 match(Set dst (ConvF2D src)); | |
| 11297 format %{ "FST_S $dst,$src\t# D-round" %} | |
| 11298 ins_encode( Pop_Reg_Reg_D(dst, src)); | |
| 11299 ins_pipe( fpu_reg_reg ); | |
| 11300 %} | |
| 11301 | |
| 11302 instruct convF2D_reg(stackSlotD dst, regF src) %{ | |
| 11303 predicate(UseSSE==1); | |
| 11304 match(Set dst (ConvF2D src)); | |
| 11305 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11306 expand %{ | |
| 11307 roundDouble_mem_reg(dst,src); | |
| 11308 %} | |
| 11309 %} | |
| 11310 | |
| 11311 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ | |
| 11312 predicate(UseSSE==1); | |
| 11313 match(Set dst (ConvF2D src)); | |
| 11314 effect( KILL cr ); | |
| 11315 format %{ "SUB ESP,4\n\t" | |
| 11316 "MOVSS [ESP] $src\n\t" | |
| 11317 "FLD_S [ESP]\n\t" | |
| 11318 "ADD ESP,4\n\t" | |
| 11319 "FSTP $dst\t# D-round" %} | |
| 11320 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); | |
| 11321 ins_pipe( pipe_slow ); | |
| 11322 %} | |
| 11323 | |
| 11324 instruct convX2XD_reg(regXD dst, regX src) %{ | |
| 11325 predicate(UseSSE>=2); | |
| 11326 match(Set dst (ConvF2D src)); | |
| 11327 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 11328 opcode(0xF3, 0x0F, 0x5A); | |
| 11329 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11330 ins_pipe( pipe_slow ); | |
| 11331 %} | |
| 11332 | |
| 11333 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11334 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ | |
| 11335 predicate(UseSSE<=1); | |
| 11336 match(Set dst (ConvD2I src)); | |
| 11337 effect( KILL tmp, KILL cr ); | |
| 11338 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 11339 "FLDCW trunc mode\n\t" | |
| 11340 "SUB ESP,4\n\t" | |
| 11341 "FISTp [ESP + #0]\n\t" | |
| 11342 "FLDCW std/24-bit mode\n\t" | |
| 11343 "POP EAX\n\t" | |
| 11344 "CMP EAX,0x80000000\n\t" | |
| 11345 "JNE,s fast\n\t" | |
| 11346 "FLD_D $src\n\t" | |
| 11347 "CALL d2i_wrapper\n" | |
| 11348 "fast:" %} | |
| 11349 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); | |
| 11350 ins_pipe( pipe_slow ); | |
| 11351 %} | |
| 11352 | |
| 11353 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11354 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ | |
| 11355 predicate(UseSSE>=2); | |
| 11356 match(Set dst (ConvD2I src)); | |
| 11357 effect( KILL tmp, KILL cr ); | |
| 11358 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 11359 "CMP $dst,0x80000000\n\t" | |
| 11360 "JNE,s fast\n\t" | |
| 11361 "SUB ESP, 8\n\t" | |
| 11362 "MOVSD [ESP], $src\n\t" | |
| 11363 "FLD_D [ESP]\n\t" | |
| 11364 "ADD ESP, 8\n\t" | |
| 11365 "CALL d2i_wrapper\n" | |
| 11366 "fast:" %} | |
| 11367 opcode(0x1); // double-precision conversion | |
| 11368 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11369 ins_pipe( pipe_slow ); | |
| 11370 %} | |
| 11371 | |
| 11372 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ | |
| 11373 predicate(UseSSE<=1); | |
| 11374 match(Set dst (ConvD2L src)); | |
| 11375 effect( KILL cr ); | |
| 11376 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 11377 "FLDCW trunc mode\n\t" | |
| 11378 "SUB ESP,8\n\t" | |
| 11379 "FISTp [ESP + #0]\n\t" | |
| 11380 "FLDCW std/24-bit mode\n\t" | |
| 11381 "POP EAX\n\t" | |
| 11382 "POP EDX\n\t" | |
| 11383 "CMP EDX,0x80000000\n\t" | |
| 11384 "JNE,s fast\n\t" | |
| 11385 "TEST EAX,EAX\n\t" | |
| 11386 "JNE,s fast\n\t" | |
| 11387 "FLD $src\n\t" | |
| 11388 "CALL d2l_wrapper\n" | |
| 11389 "fast:" %} | |
| 11390 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); | |
| 11391 ins_pipe( pipe_slow ); | |
| 11392 %} | |
| 11393 | |
| 11394 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11395 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ | |
| 11396 predicate (UseSSE>=2); | |
| 11397 match(Set dst (ConvD2L src)); | |
| 11398 effect( KILL cr ); | |
| 11399 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11400 "MOVSD [ESP],$src\n\t" | |
| 11401 "FLD_D [ESP]\n\t" | |
| 11402 "FLDCW trunc mode\n\t" | |
| 11403 "FISTp [ESP + #0]\n\t" | |
| 11404 "FLDCW std/24-bit mode\n\t" | |
| 11405 "POP EAX\n\t" | |
| 11406 "POP EDX\n\t" | |
| 11407 "CMP EDX,0x80000000\n\t" | |
| 11408 "JNE,s fast\n\t" | |
| 11409 "TEST EAX,EAX\n\t" | |
| 11410 "JNE,s fast\n\t" | |
| 11411 "SUB ESP,8\n\t" | |
| 11412 "MOVSD [ESP],$src\n\t" | |
| 11413 "FLD_D [ESP]\n\t" | |
| 11414 "CALL d2l_wrapper\n" | |
| 11415 "fast:" %} | |
| 11416 ins_encode( XD2L_encoding(src) ); | |
| 11417 ins_pipe( pipe_slow ); | |
| 11418 %} | |
| 11419 | |
| 11420 // Convert a double to an int. Java semantics require we do complex | |
| 11421 // manglations in the corner cases. So we set the rounding mode to | |
| 11422 // 'zero', store the darned double down as an int, and reset the | |
| 11423 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11424 // if we would overflow or converted a NAN; we check for this and | |
| 11425 // and go the slow path if needed. | |
| 11426 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ | |
| 11427 predicate(UseSSE==0); | |
| 11428 match(Set dst (ConvF2I src)); | |
| 11429 effect( KILL tmp, KILL cr ); | |
| 11430 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11431 "FLDCW trunc mode\n\t" | |
| 11432 "SUB ESP,4\n\t" | |
| 11433 "FISTp [ESP + #0]\n\t" | |
| 11434 "FLDCW std/24-bit mode\n\t" | |
| 11435 "POP EAX\n\t" | |
| 11436 "CMP EAX,0x80000000\n\t" | |
| 11437 "JNE,s fast\n\t" | |
| 11438 "FLD $src\n\t" | |
| 11439 "CALL d2i_wrapper\n" | |
| 11440 "fast:" %} | |
| 11441 // D2I_encoding works for F2I | |
| 11442 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); | |
| 11443 ins_pipe( pipe_slow ); | |
| 11444 %} | |
| 11445 | |
| 11446 // Convert a float in xmm to an int reg. | |
| 11447 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ | |
| 11448 predicate(UseSSE>=1); | |
| 11449 match(Set dst (ConvF2I src)); | |
| 11450 effect( KILL tmp, KILL cr ); | |
| 11451 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11452 "CMP $dst,0x80000000\n\t" | |
| 11453 "JNE,s fast\n\t" | |
| 11454 "SUB ESP, 4\n\t" | |
| 11455 "MOVSS [ESP], $src\n\t" | |
| 11456 "FLD [ESP]\n\t" | |
| 11457 "ADD ESP, 4\n\t" | |
| 11458 "CALL d2i_wrapper\n" | |
| 11459 "fast:" %} | |
| 11460 opcode(0x0); // single-precision conversion | |
| 11461 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11462 ins_pipe( pipe_slow ); | |
| 11463 %} | |
| 11464 | |
| 11465 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ | |
| 11466 predicate(UseSSE==0); | |
| 11467 match(Set dst (ConvF2L src)); | |
| 11468 effect( KILL cr ); | |
| 11469 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11470 "FLDCW trunc mode\n\t" | |
| 11471 "SUB ESP,8\n\t" | |
| 11472 "FISTp [ESP + #0]\n\t" | |
| 11473 "FLDCW std/24-bit mode\n\t" | |
| 11474 "POP EAX\n\t" | |
| 11475 "POP EDX\n\t" | |
| 11476 "CMP EDX,0x80000000\n\t" | |
| 11477 "JNE,s fast\n\t" | |
| 11478 "TEST EAX,EAX\n\t" | |
| 11479 "JNE,s fast\n\t" | |
| 11480 "FLD $src\n\t" | |
| 11481 "CALL d2l_wrapper\n" | |
| 11482 "fast:" %} | |
| 11483 // D2L_encoding works for F2L | |
| 11484 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); | |
| 11485 ins_pipe( pipe_slow ); | |
| 11486 %} | |
| 11487 | |
| 11488 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11489 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ | |
| 11490 predicate (UseSSE>=1); | |
| 11491 match(Set dst (ConvF2L src)); | |
| 11492 effect( KILL cr ); | |
| 11493 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11494 "MOVSS [ESP],$src\n\t" | |
| 11495 "FLD_S [ESP]\n\t" | |
| 11496 "FLDCW trunc mode\n\t" | |
| 11497 "FISTp [ESP + #0]\n\t" | |
| 11498 "FLDCW std/24-bit mode\n\t" | |
| 11499 "POP EAX\n\t" | |
| 11500 "POP EDX\n\t" | |
| 11501 "CMP EDX,0x80000000\n\t" | |
| 11502 "JNE,s fast\n\t" | |
| 11503 "TEST EAX,EAX\n\t" | |
| 11504 "JNE,s fast\n\t" | |
| 11505 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11506 "MOVSS [ESP],$src\n\t" | |
| 11507 "FLD_S [ESP]\n\t" | |
| 11508 "ADD ESP,4\n\t" | |
| 11509 "CALL d2l_wrapper\n" | |
| 11510 "fast:" %} | |
| 11511 ins_encode( X2L_encoding(src) ); | |
| 11512 ins_pipe( pipe_slow ); | |
| 11513 %} | |
| 11514 | |
| 11515 instruct convI2D_reg(regD dst, stackSlotI src) %{ | |
| 11516 predicate( UseSSE<=1 ); | |
| 11517 match(Set dst (ConvI2D src)); | |
| 11518 format %{ "FILD $src\n\t" | |
| 11519 "FSTP $dst" %} | |
| 11520 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11521 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); | |
| 11522 ins_pipe( fpu_reg_mem ); | |
| 11523 %} | |
| 11524 | |
| 11525 instruct convI2XD_reg(regXD dst, eRegI src) %{ | |
| 71 | 11526 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11527 match(Set dst (ConvI2D src)); |
| 11528 format %{ "CVTSI2SD $dst,$src" %} | |
| 11529 opcode(0xF2, 0x0F, 0x2A); | |
| 11530 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11531 ins_pipe( pipe_slow ); | |
| 11532 %} | |
| 11533 | |
| 11534 instruct convI2XD_mem(regXD dst, memory mem) %{ | |
| 11535 predicate( UseSSE>=2 ); | |
| 11536 match(Set dst (ConvI2D (LoadI mem))); | |
| 11537 format %{ "CVTSI2SD $dst,$mem" %} | |
| 11538 opcode(0xF2, 0x0F, 0x2A); | |
| 11539 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); | |
| 11540 ins_pipe( pipe_slow ); | |
| 11541 %} | |
| 11542 | |
| 71 | 11543 instruct convXI2XD_reg(regXD dst, eRegI src) |
| 11544 %{ | |
| 11545 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11546 match(Set dst (ConvI2D src)); | |
| 11547 | |
| 11548 format %{ "MOVD $dst,$src\n\t" | |
| 11549 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11550 ins_encode %{ | |
| 304 | 11551 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11552 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11553 %} | |
| 11554 ins_pipe(pipe_slow); // XXX | |
| 11555 %} | |
| 11556 | |
| 0 | 11557 instruct convI2D_mem(regD dst, memory mem) %{ |
| 11558 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); | |
| 11559 match(Set dst (ConvI2D (LoadI mem))); | |
| 11560 format %{ "FILD $mem\n\t" | |
| 11561 "FSTP $dst" %} | |
| 11562 opcode(0xDB); /* DB /0 */ | |
| 11563 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11564 Pop_Reg_D(dst)); | |
| 11565 ins_pipe( fpu_reg_mem ); | |
| 11566 %} | |
| 11567 | |
| 11568 // Convert a byte to a float; no rounding step needed. | |
| 11569 instruct conv24I2F_reg(regF dst, stackSlotI src) %{ | |
| 11570 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); | |
| 11571 match(Set dst (ConvI2F src)); | |
| 11572 format %{ "FILD $src\n\t" | |
| 11573 "FSTP $dst" %} | |
| 11574 | |
| 11575 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11576 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); | |
| 11577 ins_pipe( fpu_reg_mem ); | |
| 11578 %} | |
| 11579 | |
| 11580 // In 24-bit mode, force exponent rounding by storing back out | |
| 11581 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ | |
| 11582 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11583 match(Set dst (ConvI2F src)); | |
| 11584 ins_cost(200); | |
| 11585 format %{ "FILD $src\n\t" | |
| 11586 "FSTP_S $dst" %} | |
| 11587 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11588 ins_encode( Push_Mem_I(src), | |
| 11589 Pop_Mem_F(dst)); | |
| 11590 ins_pipe( fpu_mem_mem ); | |
| 11591 %} | |
| 11592 | |
| 11593 // In 24-bit mode, force exponent rounding by storing back out | |
| 11594 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ | |
| 11595 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11596 match(Set dst (ConvI2F (LoadI mem))); | |
| 11597 ins_cost(200); | |
| 11598 format %{ "FILD $mem\n\t" | |
| 11599 "FSTP_S $dst" %} | |
| 11600 opcode(0xDB); /* DB /0 */ | |
| 11601 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11602 Pop_Mem_F(dst)); | |
| 11603 ins_pipe( fpu_mem_mem ); | |
| 11604 %} | |
| 11605 | |
| 11606 // This instruction does not round to 24-bits | |
| 11607 instruct convI2F_reg(regF dst, stackSlotI src) %{ | |
| 11608 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11609 match(Set dst (ConvI2F src)); | |
| 11610 format %{ "FILD $src\n\t" | |
| 11611 "FSTP $dst" %} | |
| 11612 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11613 ins_encode( Push_Mem_I(src), | |
| 11614 Pop_Reg_F(dst)); | |
| 11615 ins_pipe( fpu_reg_mem ); | |
| 11616 %} | |
| 11617 | |
| 11618 // This instruction does not round to 24-bits | |
| 11619 instruct convI2F_mem(regF dst, memory mem) %{ | |
| 11620 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11621 match(Set dst (ConvI2F (LoadI mem))); | |
| 11622 format %{ "FILD $mem\n\t" | |
| 11623 "FSTP $dst" %} | |
| 11624 opcode(0xDB); /* DB /0 */ | |
| 11625 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11626 Pop_Reg_F(dst)); | |
| 11627 ins_pipe( fpu_reg_mem ); | |
| 11628 %} | |
| 11629 | |
| 11630 // Convert an int to a float in xmm; no rounding step needed. | |
| 11631 instruct convI2X_reg(regX dst, eRegI src) %{ | |
| 71 | 11632 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11633 match(Set dst (ConvI2F src)); |
| 11634 format %{ "CVTSI2SS $dst, $src" %} | |
| 11635 | |
| 11636 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ | |
| 11637 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11638 ins_pipe( pipe_slow ); | |
| 11639 %} | |
| 11640 | |
| 71 | 11641 instruct convXI2X_reg(regX dst, eRegI src) |
| 11642 %{ | |
| 11643 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11644 match(Set dst (ConvI2F src)); | |
| 11645 | |
| 11646 format %{ "MOVD $dst,$src\n\t" | |
| 11647 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11648 ins_encode %{ | |
| 304 | 11649 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11650 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11651 %} | |
| 11652 ins_pipe(pipe_slow); // XXX | |
| 11653 %} | |
| 11654 | |
| 0 | 11655 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ |
| 11656 match(Set dst (ConvI2L src)); | |
| 11657 effect(KILL cr); | |
| 624 | 11658 ins_cost(375); |
| 0 | 11659 format %{ "MOV $dst.lo,$src\n\t" |
| 11660 "MOV $dst.hi,$src\n\t" | |
| 11661 "SAR $dst.hi,31" %} | |
| 11662 ins_encode(convert_int_long(dst,src)); | |
| 11663 ins_pipe( ialu_reg_reg_long ); | |
| 11664 %} | |
| 11665 | |
| 11666 // Zero-extend convert int to long | |
| 11667 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11668 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 11669 effect( KILL flags ); | |
| 624 | 11670 ins_cost(250); |
| 0 | 11671 format %{ "MOV $dst.lo,$src\n\t" |
| 11672 "XOR $dst.hi,$dst.hi" %} | |
| 11673 opcode(0x33); // XOR | |
| 11674 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11675 ins_pipe( ialu_reg_reg_long ); | |
| 11676 %} | |
| 11677 | |
| 11678 // Zero-extend long | |
| 11679 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11680 match(Set dst (AndL src mask) ); | |
| 11681 effect( KILL flags ); | |
| 624 | 11682 ins_cost(250); |
| 0 | 11683 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11684 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11685 opcode(0x33); // XOR | |
| 11686 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11687 ins_pipe( ialu_reg_reg_long ); | |
| 11688 %} | |
| 11689 | |
| 11690 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ | |
| 11691 predicate (UseSSE<=1); | |
| 11692 match(Set dst (ConvL2D src)); | |
| 11693 effect( KILL cr ); | |
| 11694 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11695 "PUSH $src.lo\n\t" | |
| 11696 "FILD ST,[ESP + #0]\n\t" | |
| 11697 "ADD ESP,8\n\t" | |
| 11698 "FSTP_D $dst\t# D-round" %} | |
| 11699 opcode(0xDF, 0x5); /* DF /5 */ | |
| 11700 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); | |
| 11701 ins_pipe( pipe_slow ); | |
| 11702 %} | |
| 11703 | |
| 11704 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ | |
| 11705 predicate (UseSSE>=2); | |
| 11706 match(Set dst (ConvL2D src)); | |
| 11707 effect( KILL cr ); | |
| 11708 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11709 "PUSH $src.lo\n\t" | |
| 11710 "FILD_D [ESP]\n\t" | |
| 11711 "FSTP_D [ESP]\n\t" | |
| 11712 "MOVSD $dst,[ESP]\n\t" | |
| 11713 "ADD ESP,8" %} | |
| 11714 opcode(0xDF, 0x5); /* DF /5 */ | |
| 11715 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); | |
| 11716 ins_pipe( pipe_slow ); | |
| 11717 %} | |
| 11718 | |
| 11719 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ | |
| 11720 predicate (UseSSE>=1); | |
| 11721 match(Set dst (ConvL2F src)); | |
| 11722 effect( KILL cr ); | |
| 11723 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11724 "PUSH $src.lo\n\t" | |
| 11725 "FILD_D [ESP]\n\t" | |
| 11726 "FSTP_S [ESP]\n\t" | |
| 11727 "MOVSS $dst,[ESP]\n\t" | |
| 11728 "ADD ESP,8" %} | |
| 11729 opcode(0xDF, 0x5); /* DF /5 */ | |
| 11730 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); | |
| 11731 ins_pipe( pipe_slow ); | |
| 11732 %} | |
| 11733 | |
| 11734 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ | |
| 11735 match(Set dst (ConvL2F src)); | |
| 11736 effect( KILL cr ); | |
| 11737 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11738 "PUSH $src.lo\n\t" | |
| 11739 "FILD ST,[ESP + #0]\n\t" | |
| 11740 "ADD ESP,8\n\t" | |
| 11741 "FSTP_S $dst\t# F-round" %} | |
| 11742 opcode(0xDF, 0x5); /* DF /5 */ | |
| 11743 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); | |
| 11744 ins_pipe( pipe_slow ); | |
| 11745 %} | |
| 11746 | |
| 11747 instruct convL2I_reg( eRegI dst, eRegL src ) %{ | |
| 11748 match(Set dst (ConvL2I src)); | |
| 11749 effect( DEF dst, USE src ); | |
| 11750 format %{ "MOV $dst,$src.lo" %} | |
| 11751 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11752 ins_pipe( ialu_reg_reg ); | |
| 11753 %} | |
| 11754 | |
| 11755 | |
| 11756 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ | |
| 11757 match(Set dst (MoveF2I src)); | |
| 11758 effect( DEF dst, USE src ); | |
| 11759 ins_cost(100); | |
| 11760 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 11761 opcode(0x8B); | |
| 11762 ins_encode( OpcP, RegMem(dst,src)); | |
| 11763 ins_pipe( ialu_reg_mem ); | |
| 11764 %} | |
| 11765 | |
| 11766 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 11767 predicate(UseSSE==0); | |
| 11768 match(Set dst (MoveF2I src)); | |
| 11769 effect( DEF dst, USE src ); | |
| 11770 | |
| 11771 ins_cost(125); | |
| 11772 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
| 11773 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 11774 ins_pipe( fpu_mem_reg ); | |
| 11775 %} | |
| 11776 | |
| 11777 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ | |
| 11778 predicate(UseSSE>=1); | |
| 11779 match(Set dst (MoveF2I src)); | |
| 11780 effect( DEF dst, USE src ); | |
| 11781 | |
| 11782 ins_cost(95); | |
| 11783 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 11784 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); | |
| 11785 ins_pipe( pipe_slow ); | |
| 11786 %} | |
| 11787 | |
| 11788 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ | |
| 11789 predicate(UseSSE>=2); | |
| 11790 match(Set dst (MoveF2I src)); | |
| 11791 effect( DEF dst, USE src ); | |
| 11792 ins_cost(85); | |
| 11793 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 11794 ins_encode( MovX2I_reg(dst, src)); | |
| 11795 ins_pipe( pipe_slow ); | |
| 11796 %} | |
| 11797 | |
| 11798 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ | |
| 11799 match(Set dst (MoveI2F src)); | |
| 11800 effect( DEF dst, USE src ); | |
| 11801 | |
| 11802 ins_cost(100); | |
| 11803 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 11804 opcode(0x89); | |
| 11805 ins_encode( OpcPRegSS( dst, src ) ); | |
| 11806 ins_pipe( ialu_mem_reg ); | |
| 11807 %} | |
| 11808 | |
| 11809 | |
| 11810 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 11811 predicate(UseSSE==0); | |
| 11812 match(Set dst (MoveI2F src)); | |
| 11813 effect(DEF dst, USE src); | |
| 11814 | |
| 11815 ins_cost(125); | |
| 11816 format %{ "FLD_S $src\n\t" | |
| 11817 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11818 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11819 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 11820 Pop_Reg_F(dst) ); | |
| 11821 ins_pipe( fpu_reg_mem ); | |
| 11822 %} | |
| 11823 | |
| 11824 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ | |
| 11825 predicate(UseSSE>=1); | |
| 11826 match(Set dst (MoveI2F src)); | |
| 11827 effect( DEF dst, USE src ); | |
| 11828 | |
| 11829 ins_cost(95); | |
| 11830 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 11831 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 11832 ins_pipe( pipe_slow ); | |
| 11833 %} | |
| 11834 | |
| 11835 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ | |
| 11836 predicate(UseSSE>=2); | |
| 11837 match(Set dst (MoveI2F src)); | |
| 11838 effect( DEF dst, USE src ); | |
| 11839 | |
| 11840 ins_cost(85); | |
| 11841 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 11842 ins_encode( MovI2X_reg(dst, src) ); | |
| 11843 ins_pipe( pipe_slow ); | |
| 11844 %} | |
| 11845 | |
| 11846 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11847 match(Set dst (MoveD2L src)); | |
| 11848 effect(DEF dst, USE src); | |
| 11849 | |
| 11850 ins_cost(250); | |
| 11851 format %{ "MOV $dst.lo,$src\n\t" | |
| 11852 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11853 opcode(0x8B, 0x8B); | |
| 11854 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11855 ins_pipe( ialu_mem_long_reg ); | |
| 11856 %} | |
| 11857 | |
| 11858 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 11859 predicate(UseSSE<=1); | |
| 11860 match(Set dst (MoveD2L src)); | |
| 11861 effect(DEF dst, USE src); | |
| 11862 | |
| 11863 ins_cost(125); | |
| 11864 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
| 11865 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 11866 ins_pipe( fpu_mem_reg ); | |
| 11867 %} | |
| 11868 | |
| 11869 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ | |
| 11870 predicate(UseSSE>=2); | |
| 11871 match(Set dst (MoveD2L src)); | |
| 11872 effect(DEF dst, USE src); | |
| 11873 ins_cost(95); | |
| 11874 | |
| 11875 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 11876 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); | |
| 11877 ins_pipe( pipe_slow ); | |
| 11878 %} | |
| 11879 | |
| 11880 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ | |
| 11881 predicate(UseSSE>=2); | |
| 11882 match(Set dst (MoveD2L src)); | |
| 11883 effect(DEF dst, USE src, TEMP tmp); | |
| 11884 ins_cost(85); | |
| 11885 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11886 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11887 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 11888 ins_encode( MovXD2L_reg(dst, src, tmp) ); | |
| 11889 ins_pipe( pipe_slow ); | |
| 11890 %} | |
| 11891 | |
| 11892 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11893 match(Set dst (MoveL2D src)); | |
| 11894 effect(DEF dst, USE src); | |
| 11895 | |
| 11896 ins_cost(200); | |
| 11897 format %{ "MOV $dst,$src.lo\n\t" | |
| 11898 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11899 opcode(0x89, 0x89); | |
| 11900 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11901 ins_pipe( ialu_mem_long_reg ); | |
| 11902 %} | |
| 11903 | |
| 11904 | |
| 11905 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 11906 predicate(UseSSE<=1); | |
| 11907 match(Set dst (MoveL2D src)); | |
| 11908 effect(DEF dst, USE src); | |
| 11909 ins_cost(125); | |
| 11910 | |
| 11911 format %{ "FLD_D $src\n\t" | |
| 11912 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11913 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11914 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 11915 Pop_Reg_D(dst) ); | |
| 11916 ins_pipe( fpu_reg_mem ); | |
| 11917 %} | |
| 11918 | |
| 11919 | |
| 11920 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ | |
| 11921 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 11922 match(Set dst (MoveL2D src)); | |
| 11923 effect(DEF dst, USE src); | |
| 11924 | |
| 11925 ins_cost(95); | |
| 11926 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 11927 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 11928 ins_pipe( pipe_slow ); | |
| 11929 %} | |
| 11930 | |
| 11931 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ | |
| 11932 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 11933 match(Set dst (MoveL2D src)); | |
| 11934 effect(DEF dst, USE src); | |
| 11935 | |
| 11936 ins_cost(95); | |
| 11937 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 11938 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); | |
| 11939 ins_pipe( pipe_slow ); | |
| 11940 %} | |
| 11941 | |
| 11942 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ | |
| 11943 predicate(UseSSE>=2); | |
| 11944 match(Set dst (MoveL2D src)); | |
| 11945 effect(TEMP dst, USE src, TEMP tmp); | |
| 11946 ins_cost(85); | |
| 11947 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11948 "MOVD $tmp,$src.hi\n\t" | |
| 11949 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 11950 ins_encode( MovL2XD_reg(dst, src, tmp) ); | |
| 11951 ins_pipe( pipe_slow ); | |
| 11952 %} | |
| 11953 | |
| 11954 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11955 instruct Repl8B_reg(regXD dst, regXD src) %{ | |
| 11956 predicate(UseSSE>=2); | |
| 11957 match(Set dst (Replicate8B src)); | |
| 11958 format %{ "MOVDQA $dst,$src\n\t" | |
| 11959 "PUNPCKLBW $dst,$dst\n\t" | |
| 11960 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11961 ins_encode( pshufd_8x8(dst, src)); | |
| 11962 ins_pipe( pipe_slow ); | |
| 11963 %} | |
| 11964 | |
| 11965 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11966 instruct Repl8B_eRegI(regXD dst, eRegI src) %{ | |
| 11967 predicate(UseSSE>=2); | |
| 11968 match(Set dst (Replicate8B src)); | |
| 11969 format %{ "MOVD $dst,$src\n\t" | |
| 11970 "PUNPCKLBW $dst,$dst\n\t" | |
| 11971 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11972 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 11973 ins_pipe( pipe_slow ); | |
| 11974 %} | |
| 11975 | |
| 11976 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 11977 instruct Repl8B_immI0(regXD dst, immI0 zero) %{ | |
| 11978 predicate(UseSSE>=2); | |
| 11979 match(Set dst (Replicate8B zero)); | |
| 11980 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 11981 ins_encode( pxor(dst, dst)); | |
| 11982 ins_pipe( fpu_reg_reg ); | |
| 11983 %} | |
| 11984 | |
| 11985 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11986 instruct Repl4S_reg(regXD dst, regXD src) %{ | |
| 11987 predicate(UseSSE>=2); | |
| 11988 match(Set dst (Replicate4S src)); | |
| 11989 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 11990 ins_encode( pshufd_4x16(dst, src)); | |
| 11991 ins_pipe( fpu_reg_reg ); | |
| 11992 %} | |
| 11993 | |
| 11994 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11995 instruct Repl4S_eRegI(regXD dst, eRegI src) %{ | |
| 11996 predicate(UseSSE>=2); | |
| 11997 match(Set dst (Replicate4S src)); | |
| 11998 format %{ "MOVD $dst,$src\n\t" | |
| 11999 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 12000 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12001 ins_pipe( fpu_reg_reg ); | |
| 12002 %} | |
| 12003 | |
| 12004 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 12005 instruct Repl4S_immI0(regXD dst, immI0 zero) %{ | |
| 12006 predicate(UseSSE>=2); | |
| 12007 match(Set dst (Replicate4S zero)); | |
| 12008 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 12009 ins_encode( pxor(dst, dst)); | |
| 12010 ins_pipe( fpu_reg_reg ); | |
| 12011 %} | |
| 12012 | |
| 12013 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12014 instruct Repl4C_reg(regXD dst, regXD src) %{ | |
| 12015 predicate(UseSSE>=2); | |
| 12016 match(Set dst (Replicate4C src)); | |
| 12017 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 12018 ins_encode( pshufd_4x16(dst, src)); | |
| 12019 ins_pipe( fpu_reg_reg ); | |
| 12020 %} | |
| 12021 | |
| 12022 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12023 instruct Repl4C_eRegI(regXD dst, eRegI src) %{ | |
| 12024 predicate(UseSSE>=2); | |
| 12025 match(Set dst (Replicate4C src)); | |
| 12026 format %{ "MOVD $dst,$src\n\t" | |
| 12027 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 12028 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12029 ins_pipe( fpu_reg_reg ); | |
| 12030 %} | |
| 12031 | |
| 12032 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 12033 instruct Repl4C_immI0(regXD dst, immI0 zero) %{ | |
| 12034 predicate(UseSSE>=2); | |
| 12035 match(Set dst (Replicate4C zero)); | |
| 12036 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 12037 ins_encode( pxor(dst, dst)); | |
| 12038 ins_pipe( fpu_reg_reg ); | |
| 12039 %} | |
| 12040 | |
| 12041 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12042 instruct Repl2I_reg(regXD dst, regXD src) %{ | |
| 12043 predicate(UseSSE>=2); | |
| 12044 match(Set dst (Replicate2I src)); | |
| 12045 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 12046 ins_encode( pshufd(dst, src, 0x00)); | |
| 12047 ins_pipe( fpu_reg_reg ); | |
| 12048 %} | |
| 12049 | |
| 12050 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12051 instruct Repl2I_eRegI(regXD dst, eRegI src) %{ | |
| 12052 predicate(UseSSE>=2); | |
| 12053 match(Set dst (Replicate2I src)); | |
| 12054 format %{ "MOVD $dst,$src\n\t" | |
| 12055 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 12056 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 12057 ins_pipe( fpu_reg_reg ); | |
| 12058 %} | |
| 12059 | |
| 12060 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 12061 instruct Repl2I_immI0(regXD dst, immI0 zero) %{ | |
| 12062 predicate(UseSSE>=2); | |
| 12063 match(Set dst (Replicate2I zero)); | |
| 12064 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 12065 ins_encode( pxor(dst, dst)); | |
| 12066 ins_pipe( fpu_reg_reg ); | |
| 12067 %} | |
| 12068 | |
| 12069 // Replicate scalar to packed single precision floating point values in xmm | |
| 12070 instruct Repl2F_reg(regXD dst, regXD src) %{ | |
| 12071 predicate(UseSSE>=2); | |
| 12072 match(Set dst (Replicate2F src)); | |
| 12073 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12074 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12075 ins_pipe( fpu_reg_reg ); | |
| 12076 %} | |
| 12077 | |
| 12078 // Replicate scalar to packed single precision floating point values in xmm | |
| 12079 instruct Repl2F_regX(regXD dst, regX src) %{ | |
| 12080 predicate(UseSSE>=2); | |
| 12081 match(Set dst (Replicate2F src)); | |
| 12082 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12083 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12084 ins_pipe( fpu_reg_reg ); | |
| 12085 %} | |
| 12086 | |
| 12087 // Replicate scalar to packed single precision floating point values in xmm | |
| 12088 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ | |
| 12089 predicate(UseSSE>=2); | |
| 12090 match(Set dst (Replicate2F zero)); | |
| 12091 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 12092 ins_encode( pxor(dst, dst)); | |
| 12093 ins_pipe( fpu_reg_reg ); | |
| 12094 %} | |
| 12095 | |
| 12096 | |
| 12097 | |
| 12098 // ======================================================================= | |
| 12099 // fast clearing of an array | |
| 12100 | |
| 12101 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 12102 match(Set dummy (ClearArray cnt base)); | |
| 12103 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 12104 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 12105 "XOR EAX,EAX\n\t" | |
| 12106 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 12107 opcode(0,0x4); | |
| 12108 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 12109 OpcRegReg(0x33,EAX,EAX), | |
| 12110 Opcode(0xF3), Opcode(0xAB) ); | |
| 12111 ins_pipe( pipe_slow ); | |
| 12112 %} | |
| 12113 | |
| 12114 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{ | |
| 12115 match(Set result (StrComp str1 str2)); | |
| 12116 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); | |
| 12117 //ins_cost(300); | |
| 12118 | |
| 12119 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %} | |
| 12120 ins_encode( enc_String_Compare() ); | |
| 12121 ins_pipe( pipe_slow ); | |
| 12122 %} | |
| 12123 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12124 // fast array equals |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12125 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{ |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12126 match(Set result (AryEq ary1 ary2)); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12127 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12128 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12129 |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12130 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12131 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12132 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12133 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
12134 |
| 0 | 12135 //----------Control Flow Instructions------------------------------------------ |
| 12136 // Signed compare Instructions | |
| 12137 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ | |
| 12138 match(Set cr (CmpI op1 op2)); | |
| 12139 effect( DEF cr, USE op1, USE op2 ); | |
| 12140 format %{ "CMP $op1,$op2" %} | |
| 12141 opcode(0x3B); /* Opcode 3B /r */ | |
| 12142 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12143 ins_pipe( ialu_cr_reg_reg ); | |
| 12144 %} | |
| 12145 | |
| 12146 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ | |
| 12147 match(Set cr (CmpI op1 op2)); | |
| 12148 effect( DEF cr, USE op1 ); | |
| 12149 format %{ "CMP $op1,$op2" %} | |
| 12150 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12151 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 12152 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12153 ins_pipe( ialu_cr_reg_imm ); | |
| 12154 %} | |
| 12155 | |
| 12156 // Cisc-spilled version of cmpI_eReg | |
| 12157 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ | |
| 12158 match(Set cr (CmpI op1 (LoadI op2))); | |
| 12159 | |
| 12160 format %{ "CMP $op1,$op2" %} | |
| 12161 ins_cost(500); | |
| 12162 opcode(0x3B); /* Opcode 3B /r */ | |
| 12163 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12164 ins_pipe( ialu_cr_reg_mem ); | |
| 12165 %} | |
| 12166 | |
| 12167 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ | |
| 12168 match(Set cr (CmpI src zero)); | |
| 12169 effect( DEF cr, USE src ); | |
| 12170 | |
| 12171 format %{ "TEST $src,$src" %} | |
| 12172 opcode(0x85); | |
| 12173 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12174 ins_pipe( ialu_cr_reg_imm ); | |
| 12175 %} | |
| 12176 | |
| 12177 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ | |
| 12178 match(Set cr (CmpI (AndI src con) zero)); | |
| 12179 | |
| 12180 format %{ "TEST $src,$con" %} | |
| 12181 opcode(0xF7,0x00); | |
| 12182 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 12183 ins_pipe( ialu_cr_reg_imm ); | |
| 12184 %} | |
| 12185 | |
| 12186 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ | |
| 12187 match(Set cr (CmpI (AndI src mem) zero)); | |
| 12188 | |
| 12189 format %{ "TEST $src,$mem" %} | |
| 12190 opcode(0x85); | |
| 12191 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 12192 ins_pipe( ialu_cr_reg_mem ); | |
| 12193 %} | |
| 12194 | |
| 12195 // Unsigned compare Instructions; really, same as signed except they | |
| 12196 // produce an eFlagsRegU instead of eFlagsReg. | |
| 12197 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ | |
| 12198 match(Set cr (CmpU op1 op2)); | |
| 12199 | |
| 12200 format %{ "CMPu $op1,$op2" %} | |
| 12201 opcode(0x3B); /* Opcode 3B /r */ | |
| 12202 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12203 ins_pipe( ialu_cr_reg_reg ); | |
| 12204 %} | |
| 12205 | |
| 12206 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ | |
| 12207 match(Set cr (CmpU op1 op2)); | |
| 12208 | |
| 12209 format %{ "CMPu $op1,$op2" %} | |
| 12210 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12211 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12212 ins_pipe( ialu_cr_reg_imm ); | |
| 12213 %} | |
| 12214 | |
| 12215 // // Cisc-spilled version of cmpU_eReg | |
| 12216 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ | |
| 12217 match(Set cr (CmpU op1 (LoadI op2))); | |
| 12218 | |
| 12219 format %{ "CMPu $op1,$op2" %} | |
| 12220 ins_cost(500); | |
| 12221 opcode(0x3B); /* Opcode 3B /r */ | |
| 12222 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12223 ins_pipe( ialu_cr_reg_mem ); | |
| 12224 %} | |
| 12225 | |
| 12226 // // Cisc-spilled version of cmpU_eReg | |
| 12227 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ | |
| 12228 // match(Set cr (CmpU (LoadI op1) op2)); | |
| 12229 // | |
| 12230 // format %{ "CMPu $op1,$op2" %} | |
| 12231 // ins_cost(500); | |
| 12232 // opcode(0x39); /* Opcode 39 /r */ | |
| 12233 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12234 //%} | |
| 12235 | |
| 12236 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ | |
| 12237 match(Set cr (CmpU src zero)); | |
| 12238 | |
| 12239 format %{ "TESTu $src,$src" %} | |
| 12240 opcode(0x85); | |
| 12241 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12242 ins_pipe( ialu_cr_reg_imm ); | |
| 12243 %} | |
| 12244 | |
| 12245 // Unsigned pointer compare Instructions | |
| 12246 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 12247 match(Set cr (CmpP op1 op2)); | |
| 12248 | |
| 12249 format %{ "CMPu $op1,$op2" %} | |
| 12250 opcode(0x3B); /* Opcode 3B /r */ | |
| 12251 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12252 ins_pipe( ialu_cr_reg_reg ); | |
| 12253 %} | |
| 12254 | |
| 12255 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 12256 match(Set cr (CmpP op1 op2)); | |
| 12257 | |
| 12258 format %{ "CMPu $op1,$op2" %} | |
| 12259 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12260 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12261 ins_pipe( ialu_cr_reg_imm ); | |
| 12262 %} | |
| 12263 | |
| 12264 // // Cisc-spilled version of cmpP_eReg | |
| 12265 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 12266 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12267 | |
| 12268 format %{ "CMPu $op1,$op2" %} | |
| 12269 ins_cost(500); | |
| 12270 opcode(0x3B); /* Opcode 3B /r */ | |
| 12271 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12272 ins_pipe( ialu_cr_reg_mem ); | |
| 12273 %} | |
| 12274 | |
| 12275 // // Cisc-spilled version of cmpP_eReg | |
| 12276 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 12277 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 12278 // | |
| 12279 // format %{ "CMPu $op1,$op2" %} | |
| 12280 // ins_cost(500); | |
| 12281 // opcode(0x39); /* Opcode 39 /r */ | |
| 12282 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12283 //%} | |
| 12284 | |
| 12285 // Compare raw pointer (used in out-of-heap check). | |
| 12286 // Only works because non-oop pointers must be raw pointers | |
| 12287 // and raw pointers have no anti-dependencies. | |
| 12288 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
| 12289 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); | |
| 12290 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12291 | |
| 12292 format %{ "CMPu $op1,$op2" %} | |
| 12293 opcode(0x3B); /* Opcode 3B /r */ | |
| 12294 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12295 ins_pipe( ialu_cr_reg_mem ); | |
| 12296 %} | |
| 12297 | |
| 12298 // | |
| 12299 // This will generate a signed flags result. This should be ok | |
| 12300 // since any compare to a zero should be eq/neq. | |
| 12301 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 12302 match(Set cr (CmpP src zero)); | |
| 12303 | |
| 12304 format %{ "TEST $src,$src" %} | |
| 12305 opcode(0x85); | |
| 12306 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12307 ins_pipe( ialu_cr_reg_imm ); | |
| 12308 %} | |
| 12309 | |
| 12310 // Cisc-spilled version of testP_reg | |
| 12311 // This will generate a signed flags result. This should be ok | |
| 12312 // since any compare to a zero should be eq/neq. | |
| 12313 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12314 match(Set cr (CmpP (LoadP op) zero)); | |
| 12315 | |
| 12316 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12317 ins_cost(500); | |
| 12318 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12319 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12320 ins_pipe( ialu_cr_reg_imm ); | |
| 12321 %} | |
| 12322 | |
| 12323 // Yanked all unsigned pointer compare operations. | |
| 12324 // Pointer compares are done with CmpP which is already unsigned. | |
| 12325 | |
| 12326 //----------Max and Min-------------------------------------------------------- | |
| 12327 // Min Instructions | |
| 12328 //// | |
| 12329 // *** Min and Max using the conditional move are slower than the | |
| 12330 // *** branch version on a Pentium III. | |
| 12331 // // Conditional move for min | |
| 12332 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12333 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12334 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12335 // opcode(0x4C,0x0F); | |
| 12336 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12337 // ins_pipe( pipe_cmov_reg ); | |
| 12338 //%} | |
| 12339 // | |
| 12340 //// Min Register with Register (P6 version) | |
| 12341 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12342 // predicate(VM_Version::supports_cmov() ); | |
| 12343 // match(Set op2 (MinI op1 op2)); | |
| 12344 // ins_cost(200); | |
| 12345 // expand %{ | |
| 12346 // eFlagsReg cr; | |
| 12347 // compI_eReg(cr,op1,op2); | |
| 12348 // cmovI_reg_lt(op2,op1,cr); | |
| 12349 // %} | |
| 12350 //%} | |
| 12351 | |
| 12352 // Min Register with Register (generic version) | |
| 12353 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12354 match(Set dst (MinI dst src)); | |
| 12355 effect(KILL flags); | |
| 12356 ins_cost(300); | |
| 12357 | |
| 12358 format %{ "MIN $dst,$src" %} | |
| 12359 opcode(0xCC); | |
| 12360 ins_encode( min_enc(dst,src) ); | |
| 12361 ins_pipe( pipe_slow ); | |
| 12362 %} | |
| 12363 | |
| 12364 // Max Register with Register | |
| 12365 // *** Min and Max using the conditional move are slower than the | |
| 12366 // *** branch version on a Pentium III. | |
| 12367 // // Conditional move for max | |
| 12368 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12369 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12370 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12371 // opcode(0x4F,0x0F); | |
| 12372 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12373 // ins_pipe( pipe_cmov_reg ); | |
| 12374 //%} | |
| 12375 // | |
| 12376 // // Max Register with Register (P6 version) | |
| 12377 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12378 // predicate(VM_Version::supports_cmov() ); | |
| 12379 // match(Set op2 (MaxI op1 op2)); | |
| 12380 // ins_cost(200); | |
| 12381 // expand %{ | |
| 12382 // eFlagsReg cr; | |
| 12383 // compI_eReg(cr,op1,op2); | |
| 12384 // cmovI_reg_gt(op2,op1,cr); | |
| 12385 // %} | |
| 12386 //%} | |
| 12387 | |
| 12388 // Max Register with Register (generic version) | |
| 12389 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12390 match(Set dst (MaxI dst src)); | |
| 12391 effect(KILL flags); | |
| 12392 ins_cost(300); | |
| 12393 | |
| 12394 format %{ "MAX $dst,$src" %} | |
| 12395 opcode(0xCC); | |
| 12396 ins_encode( max_enc(dst,src) ); | |
| 12397 ins_pipe( pipe_slow ); | |
| 12398 %} | |
| 12399 | |
| 12400 // ============================================================================ | |
| 12401 // Branch Instructions | |
| 12402 // Jump Table | |
| 12403 instruct jumpXtnd(eRegI switch_val) %{ | |
| 12404 match(Jump switch_val); | |
| 12405 ins_cost(350); | |
| 12406 | |
| 12407 format %{ "JMP [table_base](,$switch_val,1)\n\t" %} | |
| 12408 | |
| 12409 ins_encode %{ | |
| 12410 address table_base = __ address_table_constant(_index2label); | |
| 12411 | |
| 12412 // Jump to Address(table_base + switch_reg) | |
| 12413 InternalAddress table(table_base); | |
| 12414 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 12415 __ jump(ArrayAddress(table, index)); | |
| 12416 %} | |
| 12417 ins_pc_relative(1); | |
| 12418 ins_pipe(pipe_jmp); | |
| 12419 %} | |
| 12420 | |
| 12421 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12422 instruct jmpDir(label labl) %{ | |
| 12423 match(Goto); | |
| 12424 effect(USE labl); | |
| 12425 | |
| 12426 ins_cost(300); | |
| 12427 format %{ "JMP $labl" %} | |
| 12428 size(5); | |
| 12429 opcode(0xE9); | |
| 12430 ins_encode( OpcP, Lbl( labl ) ); | |
| 12431 ins_pipe( pipe_jmp ); | |
| 12432 ins_pc_relative(1); | |
| 12433 %} | |
| 12434 | |
| 12435 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12436 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12437 match(If cop cr); | |
| 12438 effect(USE labl); | |
| 12439 | |
| 12440 ins_cost(300); | |
| 12441 format %{ "J$cop $labl" %} | |
| 12442 size(6); | |
| 12443 opcode(0x0F, 0x80); | |
| 12444 ins_encode( Jcc( cop, labl) ); | |
| 12445 ins_pipe( pipe_jcc ); | |
| 12446 ins_pc_relative(1); | |
| 12447 %} | |
| 12448 | |
| 12449 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12450 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12451 match(CountedLoopEnd cop cr); | |
| 12452 effect(USE labl); | |
| 12453 | |
| 12454 ins_cost(300); | |
| 12455 format %{ "J$cop $labl\t# Loop end" %} | |
| 12456 size(6); | |
| 12457 opcode(0x0F, 0x80); | |
| 12458 ins_encode( Jcc( cop, labl) ); | |
| 12459 ins_pipe( pipe_jcc ); | |
| 12460 ins_pc_relative(1); | |
| 12461 %} | |
| 12462 | |
| 12463 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12464 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12465 match(CountedLoopEnd cop cmp); | |
| 12466 effect(USE labl); | |
| 12467 | |
| 12468 ins_cost(300); | |
| 12469 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12470 size(6); | |
| 12471 opcode(0x0F, 0x80); | |
| 12472 ins_encode( Jcc( cop, labl) ); | |
| 12473 ins_pipe( pipe_jcc ); | |
| 12474 ins_pc_relative(1); | |
| 12475 %} | |
| 12476 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12477 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12478 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12479 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12480 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12481 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12482 format %{ "J$cop,u $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12483 size(6); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12484 opcode(0x0F, 0x80); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12485 ins_encode( Jcc( cop, labl) ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12486 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12487 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12488 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12489 |
| 0 | 12490 // Jump Direct Conditional - using unsigned comparison |
| 12491 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12492 match(If cop cmp); | |
| 12493 effect(USE labl); | |
| 12494 | |
| 12495 ins_cost(300); | |
| 12496 format %{ "J$cop,u $labl" %} | |
| 12497 size(6); | |
| 12498 opcode(0x0F, 0x80); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12499 ins_encode(Jcc(cop, labl)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12500 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12501 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12502 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12503 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12504 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12505 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12506 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12507 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12508 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12509 format %{ "J$cop,u $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12510 size(6); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12511 opcode(0x0F, 0x80); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12512 ins_encode(Jcc(cop, labl)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12513 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12514 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12515 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12516 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12517 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12518 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12519 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12520 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12521 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12522 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12523 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12524 $$emit$$"JP,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12525 $$emit$$"J$cop,u $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12526 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12527 $$emit$$"JP,u done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12528 $$emit$$"J$cop,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12529 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12530 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12531 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12532 size(12); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12533 opcode(0x0F, 0x80); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12534 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12535 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12536 $$$emit8$primary; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12537 emit_cc(cbuf, $secondary, Assembler::parity); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12538 int parity_disp = -1; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12539 bool ok = false; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12540 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12541 // the two jumps 6 bytes apart so the jump distances are too |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12542 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12543 } else if ($cop$$cmpcode == Assembler::equal) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12544 parity_disp = 6; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12545 ok = true; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12546 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12547 ShouldNotReachHere(); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12548 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12549 emit_d32(cbuf, parity_disp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12550 $$$emit8$primary; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12551 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12552 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12553 emit_d32(cbuf, disp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12554 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12555 ins_pipe(pipe_jcc); |
| 0 | 12556 ins_pc_relative(1); |
| 12557 %} | |
| 12558 | |
| 12559 // ============================================================================ | |
| 12560 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12561 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12562 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12563 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12564 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12565 match(Set result (PartialSubtypeCheck sub super)); | |
| 12566 effect( KILL rcx, KILL cr ); | |
| 12567 | |
| 12568 ins_cost(1100); // slightly larger than the next version | |
| 12569 format %{ "CMPL EAX,ESI\n\t" | |
| 12570 "JEQ,s hit\n\t" | |
| 12571 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" | |
| 12572 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" | |
| 12573 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12574 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12575 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12576 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12577 "hit:\n\t" | |
| 12578 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12579 "miss:\t" %} | |
| 12580 | |
| 12581 opcode(0x1); // Force a XOR of EDI | |
| 12582 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12583 ins_pipe( pipe_slow ); | |
| 12584 %} | |
| 12585 | |
| 12586 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12587 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12588 effect( KILL rcx, KILL result ); | |
| 12589 | |
| 12590 ins_cost(1000); | |
| 12591 format %{ "CMPL EAX,ESI\n\t" | |
| 12592 "JEQ,s miss\t# Actually a hit; we are done.\n\t" | |
| 12593 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" | |
| 12594 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" | |
| 12595 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12596 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12597 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12598 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12599 "miss:\t" %} | |
| 12600 | |
| 12601 opcode(0x0); // No need to XOR EDI | |
| 12602 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12603 ins_pipe( pipe_slow ); | |
| 12604 %} | |
| 12605 | |
| 12606 // ============================================================================ | |
| 12607 // Branch Instructions -- short offset versions | |
| 12608 // | |
| 12609 // These instructions are used to replace jumps of a long offset (the default | |
| 12610 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12611 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12612 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12613 // method in the MachNode which can be used to do in-place replacement of the | |
| 12614 // long variant with the shorter variant. The compiler will determine if a | |
| 12615 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12616 // specific code section of the file. | |
| 12617 | |
| 12618 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12619 instruct jmpDir_short(label labl) %{ | |
| 12620 match(Goto); | |
| 12621 effect(USE labl); | |
| 12622 | |
| 12623 ins_cost(300); | |
| 12624 format %{ "JMP,s $labl" %} | |
| 12625 size(2); | |
| 12626 opcode(0xEB); | |
| 12627 ins_encode( OpcP, LblShort( labl ) ); | |
| 12628 ins_pipe( pipe_jmp ); | |
| 12629 ins_pc_relative(1); | |
| 12630 ins_short_branch(1); | |
| 12631 %} | |
| 12632 | |
| 12633 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12634 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12635 match(If cop cr); | |
| 12636 effect(USE labl); | |
| 12637 | |
| 12638 ins_cost(300); | |
| 12639 format %{ "J$cop,s $labl" %} | |
| 12640 size(2); | |
| 12641 opcode(0x70); | |
| 12642 ins_encode( JccShort( cop, labl) ); | |
| 12643 ins_pipe( pipe_jcc ); | |
| 12644 ins_pc_relative(1); | |
| 12645 ins_short_branch(1); | |
| 12646 %} | |
| 12647 | |
| 12648 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12649 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12650 match(CountedLoopEnd cop cr); | |
| 12651 effect(USE labl); | |
| 12652 | |
| 12653 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12654 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12655 size(2); |
| 12656 opcode(0x70); | |
| 12657 ins_encode( JccShort( cop, labl) ); | |
| 12658 ins_pipe( pipe_jcc ); | |
| 12659 ins_pc_relative(1); | |
| 12660 ins_short_branch(1); | |
| 12661 %} | |
| 12662 | |
| 12663 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12664 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12665 match(CountedLoopEnd cop cmp); | |
| 12666 effect(USE labl); | |
| 12667 | |
| 12668 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12669 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12670 size(2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12671 opcode(0x70); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12672 ins_encode( JccShort( cop, labl) ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12673 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12674 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12675 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12676 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12677 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12678 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12679 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12680 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12681 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12682 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12683 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12684 size(2); |
| 12685 opcode(0x70); | |
| 12686 ins_encode( JccShort( cop, labl) ); | |
| 12687 ins_pipe( pipe_jcc ); | |
| 12688 ins_pc_relative(1); | |
| 12689 ins_short_branch(1); | |
| 12690 %} | |
| 12691 | |
| 12692 // Jump Direct Conditional - using unsigned comparison | |
| 12693 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12694 match(If cop cmp); | |
| 12695 effect(USE labl); | |
| 12696 | |
| 12697 ins_cost(300); | |
| 12698 format %{ "J$cop,us $labl" %} | |
| 12699 size(2); | |
| 12700 opcode(0x70); | |
| 12701 ins_encode( JccShort( cop, labl) ); | |
| 12702 ins_pipe( pipe_jcc ); | |
| 12703 ins_pc_relative(1); | |
| 12704 ins_short_branch(1); | |
| 12705 %} | |
| 12706 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12707 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12708 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12709 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12710 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12711 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12712 format %{ "J$cop,us $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12713 size(2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12714 opcode(0x70); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12715 ins_encode( JccShort( cop, labl) ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12716 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12717 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12718 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12719 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12720 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12721 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12722 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12723 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12724 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12725 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12726 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12727 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12728 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12729 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12730 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12731 $$emit$$"JP,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12732 $$emit$$"J$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12733 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12734 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12735 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12736 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12737 opcode(0x70); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12738 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12739 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12740 emit_cc(cbuf, $primary, Assembler::parity); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12741 int parity_disp = -1; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12742 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12743 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12744 } else if ($cop$$cmpcode == Assembler::equal) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12745 parity_disp = 2; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12746 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12747 ShouldNotReachHere(); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12748 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12749 emit_d8(cbuf, parity_disp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12750 emit_cc(cbuf, $primary, $cop$$cmpcode); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12751 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12752 emit_d8(cbuf, disp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12753 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12754 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12755 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12756 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12757 ins_pc_relative(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12758 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12759 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12760 |
| 0 | 12761 // ============================================================================ |
| 12762 // Long Compare | |
| 12763 // | |
| 12764 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12765 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12766 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12767 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12768 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12769 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12770 // NE test is negated from that. | |
| 12771 | |
| 12772 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12773 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12774 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12775 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12776 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12777 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12778 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12779 // both forms beat the trinary form of long-compare and both are very useful | |
| 12780 // on Intel which has so few registers. | |
| 12781 | |
| 12782 // Manifest a CmpL result in an integer register. Very painful. | |
| 12783 // This is the test to avoid. | |
| 12784 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12785 match(Set dst (CmpL3 src1 src2)); | |
| 12786 effect( KILL flags ); | |
| 12787 ins_cost(1000); | |
| 12788 format %{ "XOR $dst,$dst\n\t" | |
| 12789 "CMP $src1.hi,$src2.hi\n\t" | |
| 12790 "JLT,s m_one\n\t" | |
| 12791 "JGT,s p_one\n\t" | |
| 12792 "CMP $src1.lo,$src2.lo\n\t" | |
| 12793 "JB,s m_one\n\t" | |
| 12794 "JEQ,s done\n" | |
| 12795 "p_one:\tINC $dst\n\t" | |
| 12796 "JMP,s done\n" | |
| 12797 "m_one:\tDEC $dst\n" | |
| 12798 "done:" %} | |
| 12799 ins_encode %{ | |
| 12800 Label p_one, m_one, done; | |
| 304 | 12801 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12802 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12803 __ jccb(Assembler::less, m_one); | |
| 12804 __ jccb(Assembler::greater, p_one); | |
| 12805 __ cmpl($src1$$Register, $src2$$Register); | |
| 12806 __ jccb(Assembler::below, m_one); | |
| 12807 __ jccb(Assembler::equal, done); | |
| 12808 __ bind(p_one); | |
| 304 | 12809 __ incrementl($dst$$Register); |
| 0 | 12810 __ jmpb(done); |
| 12811 __ bind(m_one); | |
| 304 | 12812 __ decrementl($dst$$Register); |
| 0 | 12813 __ bind(done); |
| 12814 %} | |
| 12815 ins_pipe( pipe_slow ); | |
| 12816 %} | |
| 12817 | |
| 12818 //====== | |
| 12819 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12820 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12821 // NOT GOOD FOR EQ/NE tests. | |
| 12822 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12823 match( Set flags (CmpL src zero )); | |
| 12824 ins_cost(100); | |
| 12825 format %{ "TEST $src.hi,$src.hi" %} | |
| 12826 opcode(0x85); | |
| 12827 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12828 ins_pipe( ialu_cr_reg_reg ); | |
| 12829 %} | |
| 12830 | |
| 12831 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12832 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12833 // NOT GOOD FOR EQ/NE tests. | |
| 12834 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 12835 match( Set flags (CmpL src1 src2 )); | |
| 12836 effect( TEMP tmp ); | |
| 12837 ins_cost(300); | |
| 12838 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12839 "MOV $tmp,$src1.hi\n\t" | |
| 12840 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12841 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12842 ins_pipe( ialu_cr_reg_reg ); | |
| 12843 %} | |
| 12844 | |
| 12845 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12846 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12847 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12848 match(If cmp flags); | |
| 12849 effect(USE labl); | |
| 12850 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12851 expand %{ | |
| 12852 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12853 %} | |
| 12854 %} | |
| 12855 | |
| 12856 // Compare 2 longs and CMOVE longs. | |
| 12857 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12858 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12859 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12860 ins_cost(400); | |
| 12861 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12862 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12863 opcode(0x0F,0x40); | |
| 12864 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12865 ins_pipe( pipe_cmov_reg_long ); | |
| 12866 %} | |
| 12867 | |
| 12868 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12869 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12870 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12871 ins_cost(500); | |
| 12872 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12873 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12874 opcode(0x0F,0x40); | |
| 12875 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12876 ins_pipe( pipe_cmov_reg_long ); | |
| 12877 %} | |
| 12878 | |
| 12879 // Compare 2 longs and CMOVE ints. | |
| 12880 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ | |
| 12881 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12882 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12883 ins_cost(200); | |
| 12884 format %{ "CMOV$cmp $dst,$src" %} | |
| 12885 opcode(0x0F,0x40); | |
| 12886 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12887 ins_pipe( pipe_cmov_reg ); | |
| 12888 %} | |
| 12889 | |
| 12890 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ | |
| 12891 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12892 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12893 ins_cost(250); | |
| 12894 format %{ "CMOV$cmp $dst,$src" %} | |
| 12895 opcode(0x0F,0x40); | |
| 12896 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12897 ins_pipe( pipe_cmov_mem ); | |
| 12898 %} | |
| 12899 | |
| 12900 // Compare 2 longs and CMOVE ints. | |
| 12901 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12902 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12903 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12904 ins_cost(200); | |
| 12905 format %{ "CMOV$cmp $dst,$src" %} | |
| 12906 opcode(0x0F,0x40); | |
| 12907 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12908 ins_pipe( pipe_cmov_reg ); | |
| 12909 %} | |
| 12910 | |
| 12911 // Compare 2 longs and CMOVE doubles | |
| 12912 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ | |
| 12913 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12914 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12915 ins_cost(200); | |
| 12916 expand %{ | |
| 12917 fcmovD_regS(cmp,flags,dst,src); | |
| 12918 %} | |
| 12919 %} | |
| 12920 | |
| 12921 // Compare 2 longs and CMOVE doubles | |
| 12922 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ | |
| 12923 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12924 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12925 ins_cost(200); | |
| 12926 expand %{ | |
| 12927 fcmovXD_regS(cmp,flags,dst,src); | |
| 12928 %} | |
| 12929 %} | |
| 12930 | |
| 12931 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
| 12932 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12933 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 12934 ins_cost(200); | |
| 12935 expand %{ | |
| 12936 fcmovF_regS(cmp,flags,dst,src); | |
| 12937 %} | |
| 12938 %} | |
| 12939 | |
| 12940 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ | |
| 12941 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12942 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 12943 ins_cost(200); | |
| 12944 expand %{ | |
| 12945 fcmovX_regS(cmp,flags,dst,src); | |
| 12946 %} | |
| 12947 %} | |
| 12948 | |
| 12949 //====== | |
| 12950 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12951 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 12952 match( Set flags (CmpL src zero )); | |
| 12953 effect(TEMP tmp); | |
| 12954 ins_cost(200); | |
| 12955 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12956 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12957 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12958 ins_pipe( ialu_reg_reg_long ); | |
| 12959 %} | |
| 12960 | |
| 12961 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12962 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12963 match( Set flags (CmpL src1 src2 )); | |
| 12964 ins_cost(200+300); | |
| 12965 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12966 "JNE,s skip\n\t" | |
| 12967 "CMP $src1.hi,$src2.hi\n\t" | |
| 12968 "skip:\t" %} | |
| 12969 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12970 ins_pipe( ialu_cr_reg_reg ); | |
| 12971 %} | |
| 12972 | |
| 12973 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12974 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12975 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12976 match(If cmp flags); | |
| 12977 effect(USE labl); | |
| 12978 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12979 expand %{ | |
| 12980 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12981 %} | |
| 12982 %} | |
| 12983 | |
| 12984 // Compare 2 longs and CMOVE longs. | |
| 12985 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12986 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12987 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12988 ins_cost(400); | |
| 12989 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12990 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12991 opcode(0x0F,0x40); | |
| 12992 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12993 ins_pipe( pipe_cmov_reg_long ); | |
| 12994 %} | |
| 12995 | |
| 12996 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12997 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12998 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12999 ins_cost(500); | |
| 13000 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13001 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13002 opcode(0x0F,0x40); | |
| 13003 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13004 ins_pipe( pipe_cmov_reg_long ); | |
| 13005 %} | |
| 13006 | |
| 13007 // Compare 2 longs and CMOVE ints. | |
| 13008 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ | |
| 13009 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13010 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13011 ins_cost(200); | |
| 13012 format %{ "CMOV$cmp $dst,$src" %} | |
| 13013 opcode(0x0F,0x40); | |
| 13014 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13015 ins_pipe( pipe_cmov_reg ); | |
| 13016 %} | |
| 13017 | |
| 13018 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ | |
| 13019 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13020 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13021 ins_cost(250); | |
| 13022 format %{ "CMOV$cmp $dst,$src" %} | |
| 13023 opcode(0x0F,0x40); | |
| 13024 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13025 ins_pipe( pipe_cmov_mem ); | |
| 13026 %} | |
| 13027 | |
| 13028 // Compare 2 longs and CMOVE ints. | |
| 13029 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 13030 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13031 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13032 ins_cost(200); | |
| 13033 format %{ "CMOV$cmp $dst,$src" %} | |
| 13034 opcode(0x0F,0x40); | |
| 13035 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13036 ins_pipe( pipe_cmov_reg ); | |
| 13037 %} | |
| 13038 | |
| 13039 // Compare 2 longs and CMOVE doubles | |
| 13040 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ | |
| 13041 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13042 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13043 ins_cost(200); | |
| 13044 expand %{ | |
| 13045 fcmovD_regS(cmp,flags,dst,src); | |
| 13046 %} | |
| 13047 %} | |
| 13048 | |
| 13049 // Compare 2 longs and CMOVE doubles | |
| 13050 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ | |
| 13051 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13052 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13053 ins_cost(200); | |
| 13054 expand %{ | |
| 13055 fcmovXD_regS(cmp,flags,dst,src); | |
| 13056 %} | |
| 13057 %} | |
| 13058 | |
| 13059 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
| 13060 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13061 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13062 ins_cost(200); | |
| 13063 expand %{ | |
| 13064 fcmovF_regS(cmp,flags,dst,src); | |
| 13065 %} | |
| 13066 %} | |
| 13067 | |
| 13068 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ | |
| 13069 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13070 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13071 ins_cost(200); | |
| 13072 expand %{ | |
| 13073 fcmovX_regS(cmp,flags,dst,src); | |
| 13074 %} | |
| 13075 %} | |
| 13076 | |
| 13077 //====== | |
| 13078 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13079 // Same as cmpL_reg_flags_LEGT except must negate src | |
| 13080 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13081 match( Set flags (CmpL src zero )); | |
| 13082 effect( TEMP tmp ); | |
| 13083 ins_cost(300); | |
| 13084 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 13085 "CMP $tmp,$src.lo\n\t" | |
| 13086 "SBB $tmp,$src.hi\n\t" %} | |
| 13087 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 13088 ins_pipe( ialu_reg_reg_long ); | |
| 13089 %} | |
| 13090 | |
| 13091 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13092 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 13093 // requires a commuted test to get the same result. | |
| 13094 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13095 match( Set flags (CmpL src1 src2 )); | |
| 13096 effect( TEMP tmp ); | |
| 13097 ins_cost(300); | |
| 13098 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 13099 "MOV $tmp,$src2.hi\n\t" | |
| 13100 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 13101 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 13102 ins_pipe( ialu_cr_reg_reg ); | |
| 13103 %} | |
| 13104 | |
| 13105 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13106 // Just a wrapper for a normal branch, plus the predicate test | |
| 13107 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 13108 match(If cmp flags); | |
| 13109 effect(USE labl); | |
| 13110 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 13111 ins_cost(300); | |
| 13112 expand %{ | |
| 13113 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 13114 %} | |
| 13115 %} | |
| 13116 | |
| 13117 // Compare 2 longs and CMOVE longs. | |
| 13118 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 13119 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13120 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13121 ins_cost(400); | |
| 13122 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13123 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13124 opcode(0x0F,0x40); | |
| 13125 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13126 ins_pipe( pipe_cmov_reg_long ); | |
| 13127 %} | |
| 13128 | |
| 13129 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 13130 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13131 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13132 ins_cost(500); | |
| 13133 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13134 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 13135 opcode(0x0F,0x40); | |
| 13136 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13137 ins_pipe( pipe_cmov_reg_long ); | |
| 13138 %} | |
| 13139 | |
| 13140 // Compare 2 longs and CMOVE ints. | |
| 13141 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ | |
| 13142 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13143 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13144 ins_cost(200); | |
| 13145 format %{ "CMOV$cmp $dst,$src" %} | |
| 13146 opcode(0x0F,0x40); | |
| 13147 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13148 ins_pipe( pipe_cmov_reg ); | |
| 13149 %} | |
| 13150 | |
| 13151 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ | |
| 13152 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13153 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13154 ins_cost(250); | |
| 13155 format %{ "CMOV$cmp $dst,$src" %} | |
| 13156 opcode(0x0F,0x40); | |
| 13157 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13158 ins_pipe( pipe_cmov_mem ); | |
| 13159 %} | |
| 13160 | |
| 13161 // Compare 2 longs and CMOVE ptrs. | |
| 13162 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 13163 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13164 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13165 ins_cost(200); | |
| 13166 format %{ "CMOV$cmp $dst,$src" %} | |
| 13167 opcode(0x0F,0x40); | |
| 13168 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13169 ins_pipe( pipe_cmov_reg ); | |
| 13170 %} | |
| 13171 | |
| 13172 // Compare 2 longs and CMOVE doubles | |
| 13173 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ | |
| 13174 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13175 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13176 ins_cost(200); | |
| 13177 expand %{ | |
| 13178 fcmovD_regS(cmp,flags,dst,src); | |
| 13179 %} | |
| 13180 %} | |
| 13181 | |
| 13182 // Compare 2 longs and CMOVE doubles | |
| 13183 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ | |
| 13184 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13185 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13186 ins_cost(200); | |
| 13187 expand %{ | |
| 13188 fcmovXD_regS(cmp,flags,dst,src); | |
| 13189 %} | |
| 13190 %} | |
| 13191 | |
| 13192 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
| 13193 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13194 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13195 ins_cost(200); | |
| 13196 expand %{ | |
| 13197 fcmovF_regS(cmp,flags,dst,src); | |
| 13198 %} | |
| 13199 %} | |
| 13200 | |
| 13201 | |
| 13202 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ | |
| 13203 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13204 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13205 ins_cost(200); | |
| 13206 expand %{ | |
| 13207 fcmovX_regS(cmp,flags,dst,src); | |
| 13208 %} | |
| 13209 %} | |
| 13210 | |
| 13211 | |
| 13212 // ============================================================================ | |
| 13213 // Procedure Call/Return Instructions | |
| 13214 // Call Java Static Instruction | |
| 13215 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13216 // compute_padding() functions will have to be adjusted. | |
| 13217 instruct CallStaticJavaDirect(method meth) %{ | |
| 13218 match(CallStaticJava); | |
| 13219 effect(USE meth); | |
| 13220 | |
| 13221 ins_cost(300); | |
| 13222 format %{ "CALL,static " %} | |
| 13223 opcode(0xE8); /* E8 cd */ | |
| 13224 ins_encode( pre_call_FPU, | |
| 13225 Java_Static_Call( meth ), | |
| 13226 call_epilog, | |
| 13227 post_call_FPU ); | |
| 13228 ins_pipe( pipe_slow ); | |
| 13229 ins_pc_relative(1); | |
| 13230 ins_alignment(4); | |
| 13231 %} | |
| 13232 | |
| 13233 // Call Java Dynamic Instruction | |
| 13234 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13235 // compute_padding() functions will have to be adjusted. | |
| 13236 instruct CallDynamicJavaDirect(method meth) %{ | |
| 13237 match(CallDynamicJava); | |
| 13238 effect(USE meth); | |
| 13239 | |
| 13240 ins_cost(300); | |
| 13241 format %{ "MOV EAX,(oop)-1\n\t" | |
| 13242 "CALL,dynamic" %} | |
| 13243 opcode(0xE8); /* E8 cd */ | |
| 13244 ins_encode( pre_call_FPU, | |
| 13245 Java_Dynamic_Call( meth ), | |
| 13246 call_epilog, | |
| 13247 post_call_FPU ); | |
| 13248 ins_pipe( pipe_slow ); | |
| 13249 ins_pc_relative(1); | |
| 13250 ins_alignment(4); | |
| 13251 %} | |
| 13252 | |
| 13253 // Call Runtime Instruction | |
| 13254 instruct CallRuntimeDirect(method meth) %{ | |
| 13255 match(CallRuntime ); | |
| 13256 effect(USE meth); | |
| 13257 | |
| 13258 ins_cost(300); | |
| 13259 format %{ "CALL,runtime " %} | |
| 13260 opcode(0xE8); /* E8 cd */ | |
| 13261 // Use FFREEs to clear entries in float stack | |
| 13262 ins_encode( pre_call_FPU, | |
| 13263 FFree_Float_Stack_All, | |
| 13264 Java_To_Runtime( meth ), | |
| 13265 post_call_FPU ); | |
| 13266 ins_pipe( pipe_slow ); | |
| 13267 ins_pc_relative(1); | |
| 13268 %} | |
| 13269 | |
| 13270 // Call runtime without safepoint | |
| 13271 instruct CallLeafDirect(method meth) %{ | |
| 13272 match(CallLeaf); | |
| 13273 effect(USE meth); | |
| 13274 | |
| 13275 ins_cost(300); | |
| 13276 format %{ "CALL_LEAF,runtime " %} | |
| 13277 opcode(0xE8); /* E8 cd */ | |
| 13278 ins_encode( pre_call_FPU, | |
| 13279 FFree_Float_Stack_All, | |
| 13280 Java_To_Runtime( meth ), | |
| 13281 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13282 ins_pipe( pipe_slow ); | |
| 13283 ins_pc_relative(1); | |
| 13284 %} | |
| 13285 | |
| 13286 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13287 match(CallLeafNoFP); | |
| 13288 effect(USE meth); | |
| 13289 | |
| 13290 ins_cost(300); | |
| 13291 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13292 opcode(0xE8); /* E8 cd */ | |
| 13293 ins_encode(Java_To_Runtime(meth)); | |
| 13294 ins_pipe( pipe_slow ); | |
| 13295 ins_pc_relative(1); | |
| 13296 %} | |
| 13297 | |
| 13298 | |
| 13299 // Return Instruction | |
| 13300 // Remove the return address & jump to it. | |
| 13301 instruct Ret() %{ | |
| 13302 match(Return); | |
| 13303 format %{ "RET" %} | |
| 13304 opcode(0xC3); | |
| 13305 ins_encode(OpcP); | |
| 13306 ins_pipe( pipe_jmp ); | |
| 13307 %} | |
| 13308 | |
| 13309 // Tail Call; Jump from runtime stub to Java code. | |
| 13310 // Also known as an 'interprocedural jump'. | |
| 13311 // Target of jump will eventually return to caller. | |
| 13312 // TailJump below removes the return address. | |
| 13313 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13314 match(TailCall jump_target method_oop ); | |
| 13315 ins_cost(300); | |
| 13316 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13317 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13318 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13319 ins_pipe( pipe_jmp ); | |
| 13320 %} | |
| 13321 | |
| 13322 | |
| 13323 // Tail Jump; remove the return address; jump to target. | |
| 13324 // TailCall above leaves the return address around. | |
| 13325 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13326 match( TailJump jump_target ex_oop ); | |
| 13327 ins_cost(300); | |
| 13328 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13329 "JMP $jump_target " %} | |
| 13330 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13331 ins_encode( enc_pop_rdx, | |
| 13332 OpcP, RegOpc(jump_target) ); | |
| 13333 ins_pipe( pipe_jmp ); | |
| 13334 %} | |
| 13335 | |
| 13336 // Create exception oop: created by stack-crawling runtime code. | |
| 13337 // Created exception is now available to this handler, and is setup | |
| 13338 // just prior to jumping to this handler. No code emitted. | |
| 13339 instruct CreateException( eAXRegP ex_oop ) | |
| 13340 %{ | |
| 13341 match(Set ex_oop (CreateEx)); | |
| 13342 | |
| 13343 size(0); | |
| 13344 // use the following format syntax | |
| 13345 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13346 ins_encode(); | |
| 13347 ins_pipe( empty ); | |
| 13348 %} | |
| 13349 | |
| 13350 | |
| 13351 // Rethrow exception: | |
| 13352 // The exception oop will come in the first argument position. | |
| 13353 // Then JUMP (not call) to the rethrow stub code. | |
| 13354 instruct RethrowException() | |
| 13355 %{ | |
| 13356 match(Rethrow); | |
| 13357 | |
| 13358 // use the following format syntax | |
| 13359 format %{ "JMP rethrow_stub" %} | |
| 13360 ins_encode(enc_rethrow); | |
| 13361 ins_pipe( pipe_jmp ); | |
| 13362 %} | |
| 13363 | |
| 13364 // inlined locking and unlocking | |
| 13365 | |
| 13366 | |
| 13367 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ | |
| 13368 match( Set cr (FastLock object box) ); | |
| 13369 effect( TEMP tmp, TEMP scr ); | |
| 13370 ins_cost(300); | |
| 13371 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} | |
| 13372 ins_encode( Fast_Lock(object,box,tmp,scr) ); | |
| 13373 ins_pipe( pipe_slow ); | |
| 13374 ins_pc_relative(1); | |
| 13375 %} | |
| 13376 | |
| 13377 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 13378 match( Set cr (FastUnlock object box) ); | |
| 13379 effect( TEMP tmp ); | |
| 13380 ins_cost(300); | |
| 13381 format %{ "FASTUNLOCK $object, $box, $tmp" %} | |
| 13382 ins_encode( Fast_Unlock(object,box,tmp) ); | |
| 13383 ins_pipe( pipe_slow ); | |
| 13384 ins_pc_relative(1); | |
| 13385 %} | |
| 13386 | |
| 13387 | |
| 13388 | |
| 13389 // ============================================================================ | |
| 13390 // Safepoint Instruction | |
| 13391 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13392 match(SafePoint); | |
| 13393 effect(KILL cr); | |
| 13394 | |
| 13395 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13396 // On SPARC that might be acceptable as we can generate the address with | |
| 13397 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13398 // putting additional pressure on the index-0 in the D$. Because of | |
| 13399 // alignment (just like the situation at hand) the lower indices tend | |
| 13400 // to see more traffic. It'd be better to change the polling address | |
| 13401 // to offset 0 of the last $line in the polling page. | |
| 13402 | |
| 13403 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13404 ins_cost(125); | |
| 13405 size(6) ; | |
| 13406 ins_encode( Safepoint_Poll() ); | |
| 13407 ins_pipe( ialu_reg_mem ); | |
| 13408 %} | |
| 13409 | |
| 13410 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 13411 // These must follow all instruction definitions as they use the names | |
| 13412 // defined in the instructions definitions. | |
| 13413 // | |
| 605 | 13414 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13415 // |
| 13416 // peepconstraint %{ | |
| 13417 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13418 // [, ...] ); | |
| 13419 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13420 // | |
| 13421 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13422 // // provide an instruction_number.operand_name for each operand that appears | |
| 13423 // // in the replacement instruction's match rule | |
| 13424 // | |
| 13425 // ---------VM FLAGS--------------------------------------------------------- | |
| 13426 // | |
| 13427 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13428 // | |
| 13429 // Each peephole rule is given an identifying number starting with zero and | |
| 13430 // increasing by one in the order seen by the parser. An individual peephole | |
| 13431 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13432 // on the command-line. | |
| 13433 // | |
| 13434 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13435 // | |
| 13436 // Only match adjacent instructions in same basic block | |
| 13437 // Only equality constraints | |
| 13438 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13439 // Only one replacement instruction | |
| 13440 // | |
| 13441 // ---------EXAMPLE---------------------------------------------------------- | |
| 13442 // | |
| 13443 // // pertinent parts of existing instructions in architecture description | |
| 13444 // instruct movI(eRegI dst, eRegI src) %{ | |
| 13445 // match(Set dst (CopyI src)); | |
| 13446 // %} | |
| 13447 // | |
| 13448 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 13449 // match(Set dst (AddI dst src)); | |
| 13450 // effect(KILL cr); | |
| 13451 // %} | |
| 13452 // | |
| 13453 // // Change (inc mov) to lea | |
| 13454 // peephole %{ | |
| 13455 // // increment preceeded by register-register move | |
| 13456 // peepmatch ( incI_eReg movI ); | |
| 13457 // // require that the destination register of the increment | |
| 13458 // // match the destination register of the move | |
| 13459 // peepconstraint ( 0.dst == 1.dst ); | |
| 13460 // // construct a replacement instruction that sets | |
| 13461 // // the destination to ( move's source register + one ) | |
| 13462 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13463 // %} | |
| 13464 // | |
| 13465 // Implementation no longer uses movX instructions since | |
| 13466 // machine-independent system no longer uses CopyX nodes. | |
| 13467 // | |
| 13468 // peephole %{ | |
| 13469 // peepmatch ( incI_eReg movI ); | |
| 13470 // peepconstraint ( 0.dst == 1.dst ); | |
| 13471 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13472 // %} | |
| 13473 // | |
| 13474 // peephole %{ | |
| 13475 // peepmatch ( decI_eReg movI ); | |
| 13476 // peepconstraint ( 0.dst == 1.dst ); | |
| 13477 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13478 // %} | |
| 13479 // | |
| 13480 // peephole %{ | |
| 13481 // peepmatch ( addI_eReg_imm movI ); | |
| 13482 // peepconstraint ( 0.dst == 1.dst ); | |
| 13483 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13484 // %} | |
| 13485 // | |
| 13486 // peephole %{ | |
| 13487 // peepmatch ( addP_eReg_imm movP ); | |
| 13488 // peepconstraint ( 0.dst == 1.dst ); | |
| 13489 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13490 // %} | |
| 13491 | |
| 13492 // // Change load of spilled value to only a spill | |
| 13493 // instruct storeI(memory mem, eRegI src) %{ | |
| 13494 // match(Set mem (StoreI mem src)); | |
| 13495 // %} | |
| 13496 // | |
| 13497 // instruct loadI(eRegI dst, memory mem) %{ | |
| 13498 // match(Set dst (LoadI mem)); | |
| 13499 // %} | |
| 13500 // | |
| 13501 peephole %{ | |
| 13502 peepmatch ( loadI storeI ); | |
| 13503 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13504 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13505 %} | |
| 13506 | |
| 13507 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13508 // These must follow all instruction definitions as they use the names | |
| 13509 // defined in the instructions definitions. |