Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 1579:e9ff18c4ace7
Merge
| author | jrose |
|---|---|
| date | Wed, 02 Jun 2010 22:45:42 -0700 |
| parents | c18cbe5936b8 3657cb01ffc5 |
| children | f55c4f82ab9d |
| rev | line source |
|---|---|
| 0 | 1 // |
|
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2 // Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Special Registers | |
| 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); | |
| 79 | |
| 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 81 // allocator, and only shows up in the encodings. | |
| 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 84 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 85 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 87 // the stack will not have this element so FPR1 == st(0) from the | |
| 88 // oopMap viewpoint. This same weirdness with numbering causes | |
| 89 // instruction encoding to have to play games with the register | |
| 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 91 // where it does flt->flt moves to see an example | |
| 92 // | |
| 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 107 | |
| 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. | |
| 109 // Word a in each register holds a Float, words ab hold a Double. | |
| 110 // We currently do not use the SIMD capabilities, so registers cd | |
| 111 // are unused at the moment. | |
| 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 128 | |
| 129 // Specify priority of register selection within phases of register | |
| 130 // allocation. Highest priority is first. A useful heuristic is to | |
| 131 // give registers a low priority when they are required by machine | |
| 132 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 134 // For the Intel integer registers, the equivalent Long pairs are |
| 135 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 139 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 140 | |
| 141 alloc_class chunk1( XMM0a, XMM0b, | |
| 142 XMM1a, XMM1b, | |
| 143 XMM2a, XMM2b, | |
| 144 XMM3a, XMM3b, | |
| 145 XMM4a, XMM4b, | |
| 146 XMM5a, XMM5b, | |
| 147 XMM6a, XMM6b, | |
| 148 XMM7a, XMM7b, EFLAGS); | |
| 149 | |
| 150 | |
| 151 //----------Architecture Description Register Classes-------------------------- | |
| 152 // Several register classes are automatically defined based upon information in | |
| 153 // this architecture description. | |
| 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 158 // | |
| 159 // Class for all registers | |
| 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 161 // Class for general registers | |
| 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); | |
| 163 // Class for general registers which may be used for implicit null checks on win95 | |
| 164 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
| 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); | |
| 166 // Class of "X" registers | |
| 167 reg_class x_reg(EBX, ECX, EDX, EAX); | |
| 168 // Class of registers that can appear in an address with no offset. | |
| 169 // EBP and ESP require an extra instruction byte for zero offset. | |
| 170 // Used in fast-unlock | |
| 171 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 172 // Class for general registers not including ECX | |
| 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 174 // Class for general registers not including EAX | |
| 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 176 // Class for general registers not including EAX or EBX. | |
| 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 178 // Class of EAX (for multiply and divide operations) | |
| 179 reg_class eax_reg(EAX); | |
| 180 // Class of EBX (for atomic add) | |
| 181 reg_class ebx_reg(EBX); | |
| 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 183 reg_class ecx_reg(ECX); | |
| 184 // Class of EDX (for multiply and divide operations) | |
| 185 reg_class edx_reg(EDX); | |
| 186 // Class of EDI (for synchronization) | |
| 187 reg_class edi_reg(EDI); | |
| 188 // Class of ESI (for synchronization) | |
| 189 reg_class esi_reg(ESI); | |
| 190 // Singleton class for interpreter's stack pointer | |
| 191 reg_class ebp_reg(EBP); | |
| 192 // Singleton class for stack pointer | |
| 193 reg_class sp_reg(ESP); | |
| 194 // Singleton class for instruction pointer | |
| 195 // reg_class ip_reg(EIP); | |
| 196 // Singleton class for condition codes | |
| 197 reg_class int_flags(EFLAGS); | |
| 198 // Class of integer register pairs | |
| 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 200 // Class of integer register pairs that aligns with calling convention | |
| 201 reg_class eadx_reg( EAX,EDX ); | |
| 202 reg_class ebcx_reg( ECX,EBX ); | |
| 203 // Not AX or DX, used in divides | |
| 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 205 | |
| 206 // Floating point registers. Notice FPR0 is not a choice. | |
| 207 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 208 // a 2-address instructions out of Intels FP stack. | |
| 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); | |
| 210 | |
| 211 // make a register class for SSE registers | |
| 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); | |
| 213 | |
| 214 // make a double register class for SSE2 registers | |
| 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, | |
| 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); | |
| 217 | |
| 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, | |
| 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, | |
| 220 FPR7L,FPR7H ); | |
| 221 | |
| 222 reg_class flt_reg0( FPR1L ); | |
| 223 reg_class dbl_reg0( FPR1L,FPR1H ); | |
| 224 reg_class dbl_reg1( FPR2L,FPR2H ); | |
| 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, | |
| 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); | |
| 227 | |
| 228 // XMM6 and XMM7 could be used as temporary registers for long, float and | |
| 229 // double values for SSE2. | |
| 230 reg_class xdb_reg6( XMM6a,XMM6b ); | |
| 231 reg_class xdb_reg7( XMM7a,XMM7b ); | |
| 232 %} | |
| 233 | |
| 234 | |
| 235 //----------SOURCE BLOCK------------------------------------------------------- | |
| 236 // This is a block of C++ code which provides values, functions, and | |
| 237 // definitions necessary in the rest of the architecture description | |
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238 source_hpp %{ |
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239 // Must be visible to the DFA in dfa_x86_32.cpp |
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240 extern bool is_operand_hi32_zero(Node* n); |
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241 %} |
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242 |
| 0 | 243 source %{ |
| 304 | 244 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 245 #define RELOC_DISP32 Assembler::disp32_operand |
| 246 | |
| 247 #define __ _masm. | |
| 248 | |
| 249 // How to find the high register of a Long pair, given the low register | |
| 250 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 251 | |
| 252 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 253 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 254 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 255 | |
| 256 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 259 // of 128-bits operands for SSE instructions. | |
| 260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 261 // Store the value to a 128-bits operand. | |
| 262 operand[0] = lo; | |
| 263 operand[1] = hi; | |
| 264 return operand; | |
| 265 } | |
| 266 | |
| 267 // Buffer for 128-bits masks used by SSE instructions. | |
| 268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 269 | |
| 270 // Static initialization during VM startup. | |
| 271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 275 | |
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276 // Offset hacking within calls. |
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277 static int pre_call_FPU_size() { |
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278 if (Compile::current()->in_24_bit_fp_mode()) |
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279 return 6; // fldcw |
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280 return 0; |
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281 } |
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282 |
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283 static int preserve_SP_size() { |
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284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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292 if (_method_handle_invoke) |
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293 offset += preserve_SP_size(); |
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294 return offset; |
| 0 | 295 } |
| 296 | |
| 297 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 299 } |
| 300 | |
| 301 static int sizeof_FFree_Float_Stack_All = -1; | |
| 302 | |
| 303 int MachCallRuntimeNode::ret_addr_offset() { | |
| 304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 306 } |
| 307 | |
| 308 // Indicate if the safepoint node needs the polling page as an input. | |
| 309 // Since x86 does have absolute addressing, it doesn't. | |
| 310 bool SafePointNode::needs_polling_address_input() { | |
| 311 return false; | |
| 312 } | |
| 313 | |
| 314 // | |
| 315 // Compute padding required for nodes which need alignment | |
| 316 // | |
| 317 | |
| 318 // The address of the call instruction needs to be 4-byte aligned to | |
| 319 // ensure that it does not span a cache line so that it can be patched. | |
| 320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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321 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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322 current_offset += 1; // skip call opcode byte |
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323 return round_to(current_offset, alignment_required()) - current_offset; |
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324 } |
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325 |
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326 // The address of the call instruction needs to be 4-byte aligned to |
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327 // ensure that it does not span a cache line so that it can be patched. |
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328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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329 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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330 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 331 current_offset += 1; // skip call opcode byte |
| 332 return round_to(current_offset, alignment_required()) - current_offset; | |
| 333 } | |
| 334 | |
| 335 // The address of the call instruction needs to be 4-byte aligned to | |
| 336 // ensure that it does not span a cache line so that it can be patched. | |
| 337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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338 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 339 current_offset += 5; // skip MOV instruction |
| 340 current_offset += 1; // skip call opcode byte | |
| 341 return round_to(current_offset, alignment_required()) - current_offset; | |
| 342 } | |
| 343 | |
| 344 #ifndef PRODUCT | |
| 345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 346 st->print("INT3"); | |
| 347 } | |
| 348 #endif | |
| 349 | |
| 350 // EMIT_RM() | |
| 351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 353 *(cbuf.code_end()) = c; | |
| 354 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 355 } | |
| 356 | |
| 357 // EMIT_CC() | |
| 358 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 359 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 360 *(cbuf.code_end()) = c; | |
| 361 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 362 } | |
| 363 | |
| 364 // EMIT_OPCODE() | |
| 365 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 366 *(cbuf.code_end()) = (unsigned char)code; | |
| 367 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 368 } | |
| 369 | |
| 370 // EMIT_OPCODE() w/ relocation information | |
| 371 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 372 cbuf.relocate(cbuf.inst_mark() + offset, reloc); | |
| 373 emit_opcode(cbuf, code); | |
| 374 } | |
| 375 | |
| 376 // EMIT_D8() | |
| 377 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 378 *(cbuf.code_end()) = (unsigned char)d8; | |
| 379 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 380 } | |
| 381 | |
| 382 // EMIT_D16() | |
| 383 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 384 *((short *)(cbuf.code_end())) = d16; | |
| 385 cbuf.set_code_end(cbuf.code_end() + 2); | |
| 386 } | |
| 387 | |
| 388 // EMIT_D32() | |
| 389 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 390 *((int *)(cbuf.code_end())) = d32; | |
| 391 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 392 } | |
| 393 | |
| 394 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 395 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 396 int format) { | |
| 397 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 398 | |
| 399 *((int *)(cbuf.code_end())) = d32; | |
| 400 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 401 } | |
| 402 | |
| 403 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 404 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 405 int format) { | |
| 406 #ifdef ASSERT | |
| 407 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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408 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 409 } |
| 410 #endif | |
| 411 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 412 | |
| 413 *((int *)(cbuf.code_end())) = d32; | |
| 414 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 415 } | |
| 416 | |
| 417 // Access stack slot for load or store | |
| 418 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 419 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 420 if( -128 <= disp && disp <= 127 ) { | |
| 421 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 422 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 423 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 424 } else { | |
| 425 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 426 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 427 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 428 } | |
| 429 } | |
| 430 | |
| 431 // eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 432 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { | |
| 433 // There is no index & no scale, use form without SIB byte | |
| 434 if ((index == 0x4) && | |
| 435 (scale == 0) && (base != ESP_enc)) { | |
| 436 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 437 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 438 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 439 } | |
| 440 else { // If 8-bit displacement, mode 0x1 | |
| 441 if ((displace >= -128) && (displace <= 127) | |
| 442 && !(displace_is_oop) ) { | |
| 443 emit_rm(cbuf, 0x1, reg_encoding, base); | |
| 444 emit_d8(cbuf, displace); | |
| 445 } | |
| 446 else { // If 32-bit displacement | |
| 447 if (base == -1) { // Special flag for absolute address | |
| 448 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 449 // (manual lies; no SIB needed here) | |
| 450 if ( displace_is_oop ) { | |
| 451 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 452 } else { | |
| 453 emit_d32 (cbuf, displace); | |
| 454 } | |
| 455 } | |
| 456 else { // Normal base + offset | |
| 457 emit_rm(cbuf, 0x2, reg_encoding, base); | |
| 458 if ( displace_is_oop ) { | |
| 459 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 460 } else { | |
| 461 emit_d32 (cbuf, displace); | |
| 462 } | |
| 463 } | |
| 464 } | |
| 465 } | |
| 466 } | |
| 467 else { // Else, encode with the SIB byte | |
| 468 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 469 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 470 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 471 emit_rm(cbuf, scale, index, base); | |
| 472 } | |
| 473 else { // If 8-bit displacement, mode 0x1 | |
| 474 if ((displace >= -128) && (displace <= 127) | |
| 475 && !(displace_is_oop) ) { | |
| 476 emit_rm(cbuf, 0x1, reg_encoding, 0x4); | |
| 477 emit_rm(cbuf, scale, index, base); | |
| 478 emit_d8(cbuf, displace); | |
| 479 } | |
| 480 else { // If 32-bit displacement | |
| 481 if (base == 0x04 ) { | |
| 482 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 483 emit_rm(cbuf, scale, index, 0x04); | |
| 484 } else { | |
| 485 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 486 emit_rm(cbuf, scale, index, base); | |
| 487 } | |
| 488 if ( displace_is_oop ) { | |
| 489 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 490 } else { | |
| 491 emit_d32 (cbuf, displace); | |
| 492 } | |
| 493 } | |
| 494 } | |
| 495 } | |
| 496 } | |
| 497 | |
| 498 | |
| 499 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 500 if( dst_encoding == src_encoding ) { | |
| 501 // reg-reg copy, use an empty encoding | |
| 502 } else { | |
| 503 emit_opcode( cbuf, 0x8B ); | |
| 504 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 505 } | |
| 506 } | |
| 507 | |
| 508 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 509 if( dst_encoding == src_encoding ) { | |
| 510 // reg-reg copy, use an empty encoding | |
| 511 } else { | |
| 512 MacroAssembler _masm(&cbuf); | |
| 513 | |
| 514 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 515 } | |
| 516 } | |
| 517 | |
| 518 | |
| 519 //============================================================================= | |
| 520 #ifndef PRODUCT | |
| 521 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 522 Compile* C = ra_->C; | |
| 523 if( C->in_24_bit_fp_mode() ) { | |
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524 st->print("FLDCW 24 bit fpu control word"); |
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525 st->print_cr(""); st->print("\t"); |
| 0 | 526 } |
| 527 | |
| 528 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 529 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 530 // Remove two words for return addr and rbp, | |
| 531 framesize -= 2*wordSize; | |
| 532 | |
| 533 // Calls to C2R adapters often do not accept exceptional returns. | |
| 534 // We require that their callers must bang for them. But be careful, because | |
| 535 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 536 // stack. But the stack safety zone should account for that. | |
| 537 // See bugs 4446381, 4468289, 4497237. | |
| 538 if (C->need_stack_bang(framesize)) { | |
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539 st->print_cr("# stack bang"); st->print("\t"); |
| 0 | 540 } |
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541 st->print_cr("PUSHL EBP"); st->print("\t"); |
| 0 | 542 |
| 543 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
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544 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); |
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545 st->print_cr(""); st->print("\t"); |
| 0 | 546 framesize -= wordSize; |
| 547 } | |
| 548 | |
| 549 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 550 if (framesize) { | |
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551 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 552 } |
| 553 } else { | |
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554 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 555 } |
| 556 } | |
| 557 #endif | |
| 558 | |
| 559 | |
| 560 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 561 Compile* C = ra_->C; | |
| 562 | |
| 563 if (UseSSE >= 2 && VerifyFPU) { | |
| 564 MacroAssembler masm(&cbuf); | |
| 565 masm.verify_FPU(0, "FPU stack must be clean on entry"); | |
| 566 } | |
| 567 | |
| 568 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 569 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 570 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 571 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 572 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 573 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 574 // If method sets FPU control word do it now | |
| 575 if( C->in_24_bit_fp_mode() ) { | |
| 576 MacroAssembler masm(&cbuf); | |
| 577 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 578 } | |
| 579 | |
| 580 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 581 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 582 // Remove two words for return addr and rbp, | |
| 583 framesize -= 2*wordSize; | |
| 584 | |
| 585 // Calls to C2R adapters often do not accept exceptional returns. | |
| 586 // We require that their callers must bang for them. But be careful, because | |
| 587 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 588 // stack. But the stack safety zone should account for that. | |
| 589 // See bugs 4446381, 4468289, 4497237. | |
| 590 if (C->need_stack_bang(framesize)) { | |
| 591 MacroAssembler masm(&cbuf); | |
| 592 masm.generate_stack_overflow_check(framesize); | |
| 593 } | |
| 594 | |
| 595 // We always push rbp, so that on return to interpreter rbp, will be | |
| 596 // restored correctly and we can correct the stack. | |
| 597 emit_opcode(cbuf, 0x50 | EBP_enc); | |
| 598 | |
| 599 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
| 600 emit_opcode(cbuf, 0x68); // push 0xbadb100d | |
| 601 emit_d32(cbuf, 0xbadb100d); | |
| 602 framesize -= wordSize; | |
| 603 } | |
| 604 | |
| 605 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 606 if (framesize) { | |
| 607 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 608 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 609 emit_d8(cbuf, framesize); | |
| 610 } | |
| 611 } else { | |
| 612 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 613 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 614 emit_d32(cbuf, framesize); | |
| 615 } | |
| 616 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); | |
| 617 | |
| 618 #ifdef ASSERT | |
| 619 if (VerifyStackAtCalls) { | |
| 620 Label L; | |
| 621 MacroAssembler masm(&cbuf); | |
| 304 | 622 masm.push(rax); |
| 623 masm.mov(rax, rsp); | |
| 624 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 625 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 626 masm.pop(rax); | |
| 0 | 627 masm.jcc(Assembler::equal, L); |
| 628 masm.stop("Stack is not properly aligned!"); | |
| 629 masm.bind(L); | |
| 630 } | |
| 631 #endif | |
| 632 | |
| 633 } | |
| 634 | |
| 635 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 636 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 637 } | |
| 638 | |
| 639 int MachPrologNode::reloc() const { | |
| 640 return 0; // a large enough number | |
| 641 } | |
| 642 | |
| 643 //============================================================================= | |
| 644 #ifndef PRODUCT | |
| 645 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 646 Compile *C = ra_->C; | |
| 647 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 648 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 649 // Remove two words for return addr and rbp, | |
| 650 framesize -= 2*wordSize; | |
| 651 | |
| 652 if( C->in_24_bit_fp_mode() ) { | |
| 653 st->print("FLDCW standard control word"); | |
| 654 st->cr(); st->print("\t"); | |
| 655 } | |
| 656 if( framesize ) { | |
| 657 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 658 st->cr(); st->print("\t"); | |
| 659 } | |
| 660 st->print_cr("POPL EBP"); st->print("\t"); | |
| 661 if( do_polling() && C->is_method_compilation() ) { | |
| 662 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 663 st->cr(); st->print("\t"); | |
| 664 } | |
| 665 } | |
| 666 #endif | |
| 667 | |
| 668 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 669 Compile *C = ra_->C; | |
| 670 | |
| 671 // If method set FPU control word, restore to standard control word | |
| 672 if( C->in_24_bit_fp_mode() ) { | |
| 673 MacroAssembler masm(&cbuf); | |
| 674 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 675 } | |
| 676 | |
| 677 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 678 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 679 // Remove two words for return addr and rbp, | |
| 680 framesize -= 2*wordSize; | |
| 681 | |
| 682 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 683 | |
| 684 if( framesize >= 128 ) { | |
| 685 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 686 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 687 emit_d32(cbuf, framesize); | |
| 688 } | |
| 689 else if( framesize ) { | |
| 690 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 691 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 692 emit_d8(cbuf, framesize); | |
| 693 } | |
| 694 | |
| 695 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 696 | |
| 697 if( do_polling() && C->is_method_compilation() ) { | |
| 698 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0); | |
| 699 emit_opcode(cbuf,0x85); | |
| 700 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 701 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 702 } | |
| 703 } | |
| 704 | |
| 705 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 706 Compile *C = ra_->C; | |
| 707 // If method set FPU control word, restore to standard control word | |
| 708 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 709 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 710 | |
| 711 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 713 // Remove two words for return addr and rbp, | |
| 714 framesize -= 2*wordSize; | |
| 715 | |
| 716 size++; // popl rbp, | |
| 717 | |
| 718 if( framesize >= 128 ) { | |
| 719 size += 6; | |
| 720 } else { | |
| 721 size += framesize ? 3 : 0; | |
| 722 } | |
| 723 return size; | |
| 724 } | |
| 725 | |
| 726 int MachEpilogNode::reloc() const { | |
| 727 return 0; // a large enough number | |
| 728 } | |
| 729 | |
| 730 const Pipeline * MachEpilogNode::pipeline() const { | |
| 731 return MachNode::pipeline_class(); | |
| 732 } | |
| 733 | |
| 734 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 735 | |
| 736 //============================================================================= | |
| 737 | |
| 738 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 739 static enum RC rc_class( OptoReg::Name reg ) { | |
| 740 | |
| 741 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 742 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 743 | |
| 744 VMReg r = OptoReg::as_VMReg(reg); | |
| 745 if (r->is_Register()) return rc_int; | |
| 746 if (r->is_FloatRegister()) { | |
| 747 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 748 return rc_float; | |
| 749 } | |
| 750 assert(r->is_XMMRegister(), "must be"); | |
| 751 return rc_xmm; | |
| 752 } | |
| 753 | |
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754 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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755 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 756 if( cbuf ) { |
| 757 emit_opcode (*cbuf, opcode ); | |
| 758 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); | |
| 759 #ifndef PRODUCT | |
| 760 } else if( !do_size ) { | |
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761 if( size != 0 ) st->print("\n\t"); |
| 0 | 762 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
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763 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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764 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 765 } else { // FLD, FST, PUSH, POP |
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766 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 767 } |
| 768 #endif | |
| 769 } | |
| 770 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 771 return size+3+offset_size; | |
| 772 } | |
| 773 | |
| 774 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 775 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
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776 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 0 | 777 if( cbuf ) { |
| 778 if( reg_lo+1 == reg_hi ) { // double move? | |
| 779 if( is_load && !UseXmmLoadAndClearUpper ) | |
| 780 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load | |
| 781 else | |
| 782 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise | |
| 783 } else { | |
| 784 emit_opcode(*cbuf, 0xF3 ); | |
| 785 } | |
| 786 emit_opcode(*cbuf, 0x0F ); | |
| 787 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) | |
| 788 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load | |
| 789 else | |
| 790 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); | |
| 791 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); | |
| 792 #ifndef PRODUCT | |
| 793 } else if( !do_size ) { | |
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794 if( size != 0 ) st->print("\n\t"); |
| 0 | 795 if( reg_lo+1 == reg_hi ) { // double move? |
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796 if( is_load ) st->print("%s %s,[ESP + #%d]", |
| 0 | 797 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", |
| 798 Matcher::regName[reg_lo], offset); | |
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799 else st->print("MOVSD [ESP + #%d],%s", |
| 0 | 800 offset, Matcher::regName[reg_lo]); |
| 801 } else { | |
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802 if( is_load ) st->print("MOVSS %s,[ESP + #%d]", |
| 0 | 803 Matcher::regName[reg_lo], offset); |
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804 else st->print("MOVSS [ESP + #%d],%s", |
| 0 | 805 offset, Matcher::regName[reg_lo]); |
| 806 } | |
| 807 #endif | |
| 808 } | |
| 809 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 810 return size+5+offset_size; | |
| 811 } | |
| 812 | |
| 813 | |
| 814 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
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815 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 0 | 816 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers |
| 817 if( cbuf ) { | |
| 818 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { | |
| 819 emit_opcode(*cbuf, 0x66 ); | |
| 820 } | |
| 821 emit_opcode(*cbuf, 0x0F ); | |
| 822 emit_opcode(*cbuf, 0x28 ); | |
| 823 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 824 #ifndef PRODUCT | |
| 825 } else if( !do_size ) { | |
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826 if( size != 0 ) st->print("\n\t"); |
| 0 | 827 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 829 } else { |
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830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 831 } |
| 832 #endif | |
| 833 } | |
| 834 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); | |
| 835 } else { | |
| 836 if( cbuf ) { | |
| 837 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); | |
| 838 emit_opcode(*cbuf, 0x0F ); | |
| 839 emit_opcode(*cbuf, 0x10 ); | |
| 840 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 841 #ifndef PRODUCT | |
| 842 } else if( !do_size ) { | |
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843 if( size != 0 ) st->print("\n\t"); |
| 0 | 844 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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845 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 846 } else { |
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847 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 848 } |
| 849 #endif | |
| 850 } | |
| 851 return size+4; | |
| 852 } | |
| 853 } | |
| 854 | |
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855 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 856 if( cbuf ) { |
| 857 emit_opcode(*cbuf, 0x8B ); | |
| 858 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 859 #ifndef PRODUCT | |
| 860 } else if( !do_size ) { | |
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861 if( size != 0 ) st->print("\n\t"); |
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862 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 863 #endif |
| 864 } | |
| 865 return size+2; | |
| 866 } | |
| 867 | |
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868 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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869 int offset, int size, outputStream* st ) { |
| 0 | 870 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 871 if( cbuf ) { | |
| 872 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 873 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 874 #ifndef PRODUCT | |
| 875 } else if( !do_size ) { | |
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876 if( size != 0 ) st->print("\n\t"); |
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877 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 878 #endif |
| 879 } | |
| 880 size += 2; | |
| 881 } | |
| 882 | |
| 883 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 884 const char *op_str; | |
| 885 int op; | |
| 886 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 887 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 888 op = 0xDD; | |
| 889 } else { // 32-bit store | |
| 890 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 891 op = 0xD9; | |
| 892 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 893 } | |
| 894 | |
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895 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 896 } |
| 897 | |
| 898 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { | |
| 899 // Get registers to move | |
| 900 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 901 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 902 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 903 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 904 | |
| 905 enum RC src_second_rc = rc_class(src_second); | |
| 906 enum RC src_first_rc = rc_class(src_first); | |
| 907 enum RC dst_second_rc = rc_class(dst_second); | |
| 908 enum RC dst_first_rc = rc_class(dst_first); | |
| 909 | |
| 910 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 911 | |
| 912 // Generate spill code! | |
| 913 int size = 0; | |
| 914 | |
| 915 if( src_first == dst_first && src_second == dst_second ) | |
| 916 return size; // Self copy, no move | |
| 917 | |
| 918 // -------------------------------------- | |
| 919 // Check for mem-mem move. push/pop to move. | |
| 920 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 921 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 922 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
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923 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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924 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 925 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 926 } | |
| 927 // move low bits | |
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928 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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929 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 930 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
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931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 933 } |
| 934 return size; | |
| 935 } | |
| 936 | |
| 937 // -------------------------------------- | |
| 938 // Check for integer reg-reg copy | |
| 939 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
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940 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 941 |
| 942 // Check for integer store | |
| 943 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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944 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 945 |
| 946 // Check for integer load | |
| 947 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
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948 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 949 |
| 950 // -------------------------------------- | |
| 951 // Check for float reg-reg copy | |
| 952 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 953 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 954 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 955 if( cbuf ) { | |
| 956 | |
| 957 // Note the mucking with the register encode to compensate for the 0/1 | |
| 958 // indexing issue mentioned in a comment in the reg_def sections | |
| 959 // for FPR registers many lines above here. | |
| 960 | |
| 961 if( src_first != FPR1L_num ) { | |
| 962 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 963 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 964 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 965 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 966 } else { | |
| 967 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 968 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 969 } | |
| 970 #ifndef PRODUCT | |
| 971 } else if( !do_size ) { | |
| 972 if( size != 0 ) st->print("\n\t"); | |
| 973 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 974 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 975 #endif | |
| 976 } | |
| 977 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 978 } | |
| 979 | |
| 980 // Check for float store | |
| 981 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
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982 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 983 } |
| 984 | |
| 985 // Check for float load | |
| 986 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 987 int offset = ra_->reg2offset(src_first); | |
| 988 const char *op_str; | |
| 989 int op; | |
| 990 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 991 op_str = "FLD_D"; | |
| 992 op = 0xDD; | |
| 993 } else { // 32-bit load | |
| 994 op_str = "FLD_S"; | |
| 995 op = 0xD9; | |
| 996 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 997 } | |
| 998 if( cbuf ) { | |
| 999 emit_opcode (*cbuf, op ); | |
| 1000 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); | |
| 1001 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1002 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1003 #ifndef PRODUCT | |
| 1004 } else if( !do_size ) { | |
| 1005 if( size != 0 ) st->print("\n\t"); | |
| 1006 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1007 #endif | |
| 1008 } | |
| 1009 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1010 return size + 3+offset_size+2; | |
| 1011 } | |
| 1012 | |
| 1013 // Check for xmm reg-reg copy | |
| 1014 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1015 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1016 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1017 "no non-adjacent float-moves" ); | |
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1018 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1019 } |
| 1020 | |
| 1021 // Check for xmm store | |
| 1022 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1023 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1024 } |
| 1025 | |
| 1026 // Check for float xmm load | |
| 1027 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1028 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1029 } |
| 1030 | |
| 1031 // Copy from float reg to xmm reg | |
| 1032 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1033 // copy to the top of stack from floating point reg | |
| 1034 // and use LEA to preserve flags | |
| 1035 if( cbuf ) { | |
| 1036 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1037 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1038 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1039 emit_d8(*cbuf,0xF8); | |
| 1040 #ifndef PRODUCT | |
| 1041 } else if( !do_size ) { | |
| 1042 if( size != 0 ) st->print("\n\t"); | |
| 1043 st->print("LEA ESP,[ESP-8]"); | |
| 1044 #endif | |
| 1045 } | |
| 1046 size += 4; | |
| 1047 | |
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1048 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1049 |
| 1050 // Copy from the temp memory to the xmm reg. | |
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1051 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1052 |
| 1053 if( cbuf ) { | |
| 1054 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1055 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1056 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1057 emit_d8(*cbuf,0x08); | |
| 1058 #ifndef PRODUCT | |
| 1059 } else if( !do_size ) { | |
| 1060 if( size != 0 ) st->print("\n\t"); | |
| 1061 st->print("LEA ESP,[ESP+8]"); | |
| 1062 #endif | |
| 1063 } | |
| 1064 size += 4; | |
| 1065 return size; | |
| 1066 } | |
| 1067 | |
| 1068 assert( size > 0, "missed a case" ); | |
| 1069 | |
| 1070 // -------------------------------------------------------------------- | |
| 1071 // Check for second bits still needing moving. | |
| 1072 if( src_second == dst_second ) | |
| 1073 return size; // Self copy; no move | |
| 1074 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1075 | |
| 1076 // Check for second word int-int move | |
| 1077 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
|
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1078 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1079 |
| 1080 // Check for second word integer store | |
| 1081 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
|
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1082 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1083 |
| 1084 // Check for second word integer load | |
| 1085 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
|
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1086 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1087 |
| 1088 | |
| 1089 Unimplemented(); | |
| 1090 } | |
| 1091 | |
| 1092 #ifndef PRODUCT | |
| 1093 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1094 implementation( NULL, ra_, false, st ); | |
| 1095 } | |
| 1096 #endif | |
| 1097 | |
| 1098 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1099 implementation( &cbuf, ra_, false, NULL ); | |
| 1100 } | |
| 1101 | |
| 1102 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1103 return implementation( NULL, ra_, true, NULL ); | |
| 1104 } | |
| 1105 | |
| 1106 //============================================================================= | |
| 1107 #ifndef PRODUCT | |
| 1108 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 1109 st->print("NOP \t# %d bytes pad for loops and calls", _count); | |
| 1110 } | |
| 1111 #endif | |
| 1112 | |
| 1113 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1114 MacroAssembler _masm(&cbuf); | |
| 1115 __ nop(_count); | |
| 1116 } | |
| 1117 | |
| 1118 uint MachNopNode::size(PhaseRegAlloc *) const { | |
| 1119 return _count; | |
| 1120 } | |
| 1121 | |
| 1122 | |
| 1123 //============================================================================= | |
| 1124 #ifndef PRODUCT | |
| 1125 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1126 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1127 int reg = ra_->get_reg_first(this); | |
| 1128 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1129 } | |
| 1130 #endif | |
| 1131 | |
| 1132 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1133 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1134 int reg = ra_->get_encode(this); | |
| 1135 if( offset >= 128 ) { | |
| 1136 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1137 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1138 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1139 emit_d32(cbuf, offset); | |
| 1140 } | |
| 1141 else { | |
| 1142 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1143 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1144 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1145 emit_d8(cbuf, offset); | |
| 1146 } | |
| 1147 } | |
| 1148 | |
| 1149 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1150 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1151 if( offset >= 128 ) { | |
| 1152 return 7; | |
| 1153 } | |
| 1154 else { | |
| 1155 return 4; | |
| 1156 } | |
| 1157 } | |
| 1158 | |
| 1159 //============================================================================= | |
| 1160 | |
| 1161 // emit call stub, compiled java to interpreter | |
| 1162 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1163 // Stub is fixed up when the corresponding call is converted from calling | |
| 1164 // compiled code to calling interpreted code. | |
| 1165 // mov rbx,0 | |
| 1166 // jmp -1 | |
| 1167 | |
| 1168 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1169 | |
| 1170 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1171 // That's why we must use the macroassembler to generate a stub. | |
| 1172 MacroAssembler _masm(&cbuf); | |
| 1173 | |
| 1174 address base = | |
| 1175 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1176 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1177 // static stub relocation stores the instruction address of the call | |
| 1178 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
| 1179 // static stub relocation also tags the methodOop in the code-stream. | |
| 1180 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time | |
| 304 | 1181 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1182 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1183 |
| 1184 __ end_a_stub(); | |
| 1185 // Update current stubs pointer and restore code_end. | |
| 1186 } | |
| 1187 // size of call stub, compiled java to interpretor | |
| 1188 uint size_java_to_interp() { | |
| 1189 return 10; // movl; jmp | |
| 1190 } | |
| 1191 // relocation entries for call stub, compiled java to interpretor | |
| 1192 uint reloc_java_to_interp() { | |
| 1193 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1194 } | |
| 1195 | |
| 1196 //============================================================================= | |
| 1197 #ifndef PRODUCT | |
| 1198 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1199 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1200 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1201 st->print_cr("\tNOP"); | |
| 1202 st->print_cr("\tNOP"); | |
| 1203 if( !OptoBreakpoint ) | |
| 1204 st->print_cr("\tNOP"); | |
| 1205 } | |
| 1206 #endif | |
| 1207 | |
| 1208 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1209 MacroAssembler masm(&cbuf); | |
| 1210 #ifdef ASSERT | |
| 1211 uint code_size = cbuf.code_size(); | |
| 1212 #endif | |
| 304 | 1213 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1214 masm.jump_cc(Assembler::notEqual, |
| 1215 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1216 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1217 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1218 int nops_cnt = 2; | |
| 1219 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1220 nops_cnt += 1; | |
| 1221 masm.nop(nops_cnt); | |
| 1222 | |
| 1223 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node"); | |
| 1224 } | |
| 1225 | |
| 1226 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1227 return OptoBreakpoint ? 11 : 12; | |
| 1228 } | |
| 1229 | |
| 1230 | |
| 1231 //============================================================================= | |
| 1232 uint size_exception_handler() { | |
| 1233 // NativeCall instruction size is the same as NativeJump. | |
| 1234 // exception handler starts out as jump and can be patched to | |
| 1235 // a call be deoptimization. (4932387) | |
| 1236 // Note that this value is also credited (in output.cpp) to | |
| 1237 // the size of the code section. | |
| 1238 return NativeJump::instruction_size; | |
| 1239 } | |
| 1240 | |
| 1241 // Emit exception handler code. Stuff framesize into a register | |
| 1242 // and call a VM stub routine. | |
| 1243 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1244 | |
| 1245 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1246 // That's why we must use the macroassembler to generate a handler. | |
| 1247 MacroAssembler _masm(&cbuf); | |
| 1248 address base = | |
| 1249 __ start_a_stub(size_exception_handler()); | |
| 1250 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1251 int offset = __ offset(); | |
| 1252 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); | |
| 1253 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1254 __ end_a_stub(); | |
| 1255 return offset; | |
| 1256 } | |
| 1257 | |
| 1258 uint size_deopt_handler() { | |
| 1259 // NativeCall instruction size is the same as NativeJump. | |
| 1260 // exception handler starts out as jump and can be patched to | |
| 1261 // a call be deoptimization. (4932387) | |
| 1262 // Note that this value is also credited (in output.cpp) to | |
| 1263 // the size of the code section. | |
| 1264 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1265 } | |
| 1266 | |
| 1267 // Emit deopt handler code. | |
| 1268 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1269 | |
| 1270 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1271 // That's why we must use the macroassembler to generate a handler. | |
| 1272 MacroAssembler _masm(&cbuf); | |
| 1273 address base = | |
| 1274 __ start_a_stub(size_exception_handler()); | |
| 1275 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1276 int offset = __ offset(); | |
| 1277 InternalAddress here(__ pc()); | |
| 1278 __ pushptr(here.addr()); | |
| 1279 | |
| 1280 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1281 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1282 __ end_a_stub(); | |
| 1283 return offset; | |
| 1284 } | |
| 1285 | |
| 1286 | |
| 1287 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
| 1288 int mark = cbuf.insts()->mark_off(); | |
| 1289 MacroAssembler _masm(&cbuf); | |
| 1290 address double_address = __ double_constant(x); | |
| 1291 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1292 emit_d32_reloc(cbuf, | |
| 1293 (int)double_address, | |
| 1294 internal_word_Relocation::spec(double_address), | |
| 1295 RELOC_DISP32); | |
| 1296 } | |
| 1297 | |
| 1298 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
| 1299 int mark = cbuf.insts()->mark_off(); | |
| 1300 MacroAssembler _masm(&cbuf); | |
| 1301 address float_address = __ float_constant(x); | |
| 1302 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1303 emit_d32_reloc(cbuf, | |
| 1304 (int)float_address, | |
| 1305 internal_word_Relocation::spec(float_address), | |
| 1306 RELOC_DISP32); | |
| 1307 } | |
| 1308 | |
| 1309 | |
|
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1310 const bool Matcher::match_rule_supported(int opcode) { |
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1311 if (!has_match_rule(opcode)) |
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1312 return false; |
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1313 |
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1314 return true; // Per default match rules are supported. |
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1315 } |
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1316 |
| 0 | 1317 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1318 return regnum - 32; // The FP registers are in the second chunk | |
| 1319 } | |
| 1320 | |
| 1321 bool is_positive_zero_float(jfloat f) { | |
| 1322 return jint_cast(f) == jint_cast(0.0F); | |
| 1323 } | |
| 1324 | |
| 1325 bool is_positive_one_float(jfloat f) { | |
| 1326 return jint_cast(f) == jint_cast(1.0F); | |
| 1327 } | |
| 1328 | |
| 1329 bool is_positive_zero_double(jdouble d) { | |
| 1330 return jlong_cast(d) == jlong_cast(0.0); | |
| 1331 } | |
| 1332 | |
| 1333 bool is_positive_one_double(jdouble d) { | |
| 1334 return jlong_cast(d) == jlong_cast(1.0); | |
| 1335 } | |
| 1336 | |
| 1337 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1338 const bool Matcher::convL2FSupported(void) { | |
| 1339 return true; | |
| 1340 } | |
| 1341 | |
| 1342 // Vector width in bytes | |
| 1343 const uint Matcher::vector_width_in_bytes(void) { | |
| 1344 return UseSSE >= 2 ? 8 : 0; | |
| 1345 } | |
| 1346 | |
| 1347 // Vector ideal reg | |
| 1348 const uint Matcher::vector_ideal_reg(void) { | |
| 1349 return Op_RegD; | |
| 1350 } | |
| 1351 | |
| 1352 // Is this branch offset short enough that a short branch can be used? | |
| 1353 // | |
| 1354 // NOTE: If the platform does not provide any short branch variants, then | |
| 1355 // this method should return false for offset 0. | |
|
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1356 bool Matcher::is_short_branch_offset(int rule, int offset) { |
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1357 // the short version of jmpConUCF2 contains multiple branches, |
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1358 // making the reach slightly less |
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1359 if (rule == jmpConUCF2_rule) |
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1360 return (-126 <= offset && offset <= 125); |
| 0 | 1361 return (-128 <= offset && offset <= 127); |
| 1362 } | |
| 1363 | |
| 1364 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1365 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1366 return false; | |
| 1367 } | |
| 1368 | |
| 1369 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1370 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1371 | |
| 1372 // Threshold size for cleararray. | |
| 1373 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1374 | |
| 1375 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1376 // be subsumed into complex addressing expressions or compute them into | |
| 1377 // registers? True for Intel but false for most RISCs | |
| 1378 const bool Matcher::clone_shift_expressions = true; | |
| 1379 | |
|
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1380 bool Matcher::narrow_oop_use_complex_address() { |
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1381 ShouldNotCallThis(); |
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1382 return true; |
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1383 } |
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1384 |
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1385 |
| 0 | 1386 // Is it better to copy float constants, or load them directly from memory? |
| 1387 // Intel can load a float constant from a direct address, requiring no | |
| 1388 // extra registers. Most RISCs will have to materialize an address into a | |
| 1389 // register first, so they would do better to copy the constant from stack. | |
| 1390 const bool Matcher::rematerialize_float_constants = true; | |
| 1391 | |
| 1392 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1393 // needed. Else we split the double into 2 integer pieces and move it | |
| 1394 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1395 // Java calling convention forces doubles to be aligned. | |
| 1396 const bool Matcher::misaligned_doubles_ok = true; | |
| 1397 | |
| 1398 | |
| 1399 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1400 // Get the memory operand from the node | |
| 1401 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1402 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1403 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1404 uint opcnt = 1; // First operand | |
| 1405 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1406 while( idx >= skipped+num_edges ) { | |
| 1407 skipped += num_edges; | |
| 1408 opcnt++; // Bump operand count | |
| 1409 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1410 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1411 } | |
| 1412 | |
| 1413 MachOper *memory = node->_opnds[opcnt]; | |
| 1414 MachOper *new_memory = NULL; | |
| 1415 switch (memory->opcode()) { | |
| 1416 case DIRECT: | |
| 1417 case INDOFFSET32X: | |
| 1418 // No transformation necessary. | |
| 1419 return; | |
| 1420 case INDIRECT: | |
| 1421 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1422 break; | |
| 1423 case INDOFFSET8: | |
| 1424 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1425 break; | |
| 1426 case INDOFFSET32: | |
| 1427 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1428 break; | |
| 1429 case INDINDEXOFFSET: | |
| 1430 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1431 break; | |
| 1432 case INDINDEXSCALE: | |
| 1433 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1434 break; | |
| 1435 case INDINDEXSCALEOFFSET: | |
| 1436 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1437 break; | |
| 1438 case LOAD_LONG_INDIRECT: | |
| 1439 case LOAD_LONG_INDOFFSET32: | |
| 1440 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1441 return; | |
| 1442 default: | |
| 1443 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1444 return; | |
| 1445 } | |
| 1446 node->_opnds[opcnt] = new_memory; | |
| 1447 } | |
| 1448 | |
| 1449 // Advertise here if the CPU requires explicit rounding operations | |
| 1450 // to implement the UseStrictFP mode. | |
| 1451 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1452 | |
|
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1453 // Are floats conerted to double when stored to stack during deoptimization? |
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1454 // On x32 it is stored with convertion only when FPU is used for floats. |
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1455 bool Matcher::float_in_double() { return (UseSSE == 0); } |
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1456 |
| 0 | 1457 // Do ints take an entire long register or just half? |
| 1458 const bool Matcher::int_in_long = false; | |
| 1459 | |
| 1460 // Return whether or not this register is ever used as an argument. This | |
| 1461 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1462 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1463 // arguments in those registers not be available to the callee. | |
| 1464 bool Matcher::can_be_java_arg( int reg ) { | |
| 1465 if( reg == ECX_num || reg == EDX_num ) return true; | |
| 1466 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; | |
| 1467 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; | |
| 1468 return false; | |
| 1469 } | |
| 1470 | |
| 1471 bool Matcher::is_spillable_arg( int reg ) { | |
| 1472 return can_be_java_arg(reg); | |
| 1473 } | |
| 1474 | |
| 1475 // Register for DIVI projection of divmodI | |
| 1476 RegMask Matcher::divI_proj_mask() { | |
| 1477 return EAX_REG_mask; | |
| 1478 } | |
| 1479 | |
| 1480 // Register for MODI projection of divmodI | |
| 1481 RegMask Matcher::modI_proj_mask() { | |
| 1482 return EDX_REG_mask; | |
| 1483 } | |
| 1484 | |
| 1485 // Register for DIVL projection of divmodL | |
| 1486 RegMask Matcher::divL_proj_mask() { | |
| 1487 ShouldNotReachHere(); | |
| 1488 return RegMask(); | |
| 1489 } | |
| 1490 | |
| 1491 // Register for MODL projection of divmodL | |
| 1492 RegMask Matcher::modL_proj_mask() { | |
| 1493 ShouldNotReachHere(); | |
| 1494 return RegMask(); | |
| 1495 } | |
| 1496 | |
|
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1497 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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1498 return EBP_REG_mask; |
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|
1499 } |
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1500 |
|
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|
1501 // Returns true if the high 32 bits of the value is known to be zero. |
|
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1502 bool is_operand_hi32_zero(Node* n) { |
|
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|
1503 int opc = n->Opcode(); |
|
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|
1504 if (opc == Op_LoadUI2L) { |
|
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|
1505 return true; |
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|
1506 } |
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|
1507 if (opc == Op_AndL) { |
|
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|
1508 Node* o2 = n->in(2); |
|
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1509 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1510 return true; |
|
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|
1511 } |
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|
1512 } |
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|
1513 return false; |
|
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|
1514 } |
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|
1515 |
| 0 | 1516 %} |
| 1517 | |
| 1518 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1519 // This block specifies the encoding classes used by the compiler to output | |
| 1520 // byte streams. Encoding classes generate functions which are called by | |
| 1521 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1522 // instruction. Operands specify their base encoding interface with the | |
| 1523 // interface keyword. There are currently supported four interfaces, | |
| 1524 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1525 // operand to generate a function which returns its register number when | |
| 1526 // queried. CONST_INTER causes an operand to generate a function which | |
| 1527 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1528 // operand to generate four functions which return the Base Register, the | |
| 1529 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1530 // queried. COND_INTER causes an operand to generate six functions which | |
| 1531 // return the encoding code (ie - encoding bits for the instruction) | |
| 1532 // associated with each basic boolean condition for a conditional instruction. | |
| 1533 // Instructions specify two basic values for encoding. They use the | |
| 1534 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1535 // the class names specified in the encoding block), and they use the | |
| 1536 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1537 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1538 // needs for encoding need to be specified. | |
| 1539 encode %{ | |
| 1540 // Build emit functions for each basic byte or larger field in the intel | |
| 1541 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1542 // code in the enc_class source block. Emit functions will live in the | |
| 1543 // main source block for now. In future, we can generalize this by | |
| 1544 // adding a syntax that specifies the sizes of fields in an order, | |
| 1545 // so that the adlc can build the emit functions automagically | |
|
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1546 |
|
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1547 // Emit primary opcode |
|
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1548 enc_class OpcP %{ |
|
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1549 emit_opcode(cbuf, $primary); |
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1550 %} |
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1551 |
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1552 // Emit secondary opcode |
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1553 enc_class OpcS %{ |
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1554 emit_opcode(cbuf, $secondary); |
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1555 %} |
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1556 |
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1557 // Emit opcode directly |
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1558 enc_class Opcode(immI d8) %{ |
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1559 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1560 %} |
| 1561 | |
| 1562 enc_class SizePrefix %{ | |
| 1563 emit_opcode(cbuf,0x66); | |
| 1564 %} | |
| 1565 | |
| 1566 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1567 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1568 %} | |
| 1569 | |
| 1570 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) | |
| 1571 emit_opcode(cbuf,$opcode$$constant); | |
| 1572 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1573 %} | |
| 1574 | |
| 1575 enc_class mov_r32_imm0( eRegI dst ) %{ | |
| 1576 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 | |
| 1577 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1578 %} | |
| 1579 | |
| 1580 enc_class cdq_enc %{ | |
| 1581 // Full implementation of Java idiv and irem; checks for | |
| 1582 // special case as described in JVM spec., p.243 & p.271. | |
| 1583 // | |
| 1584 // normal case special case | |
| 1585 // | |
| 1586 // input : rax,: dividend min_int | |
| 1587 // reg: divisor -1 | |
| 1588 // | |
| 1589 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1590 // rdx: remainder (= rax, irem reg) 0 | |
| 1591 // | |
| 1592 // Code sequnce: | |
| 1593 // | |
| 1594 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1595 // 0F 85 0B 00 00 00 jne normal_case | |
| 1596 // 33 D2 xor rdx,edx | |
| 1597 // 83 F9 FF cmp rcx,0FFh | |
| 1598 // 0F 84 03 00 00 00 je done | |
| 1599 // normal_case: | |
| 1600 // 99 cdq | |
| 1601 // F7 F9 idiv rax,ecx | |
| 1602 // done: | |
| 1603 // | |
| 1604 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1605 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1606 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1607 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1608 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1609 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1610 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1611 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1612 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1613 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1614 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1615 // normal_case: | |
| 1616 emit_opcode(cbuf,0x99); // cdq | |
| 1617 // idiv (note: must be emitted by the user of this rule) | |
| 1618 // normal: | |
| 1619 %} | |
| 1620 | |
| 1621 // Dense encoding for older common ops | |
| 1622 enc_class Opc_plus(immI opcode, eRegI reg) %{ | |
| 1623 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); | |
| 1624 %} | |
| 1625 | |
| 1626 | |
| 1627 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1628 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1629 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1630 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1631 emit_opcode(cbuf, $primary | 0x02); | |
| 1632 } | |
| 1633 else { // If 32-bit immediate | |
| 1634 emit_opcode(cbuf, $primary); | |
| 1635 } | |
| 1636 %} | |
| 1637 | |
| 1638 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m | |
| 1639 // Emit primary opcode and set sign-extend bit | |
| 1640 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1641 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1642 emit_opcode(cbuf, $primary | 0x02); } | |
| 1643 else { // If 32-bit immediate | |
| 1644 emit_opcode(cbuf, $primary); | |
| 1645 } | |
| 1646 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1647 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1648 %} | |
| 1649 | |
| 1650 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1651 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1652 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1653 $$$emit8$imm$$constant; | |
| 1654 } | |
| 1655 else { // If 32-bit immediate | |
| 1656 // Output immediate | |
| 1657 $$$emit32$imm$$constant; | |
| 1658 } | |
| 1659 %} | |
| 1660 | |
| 1661 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1662 // Emit primary opcode and set sign-extend bit | |
| 1663 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1664 int con = (int)$imm$$constant; // Throw away top bits | |
| 1665 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1666 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1667 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1668 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1669 else emit_d32(cbuf,con); | |
| 1670 %} | |
| 1671 | |
| 1672 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1673 // Emit primary opcode and set sign-extend bit | |
| 1674 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1675 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1676 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1677 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1678 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1679 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1680 else emit_d32(cbuf,con); | |
| 1681 %} | |
| 1682 | |
| 1683 enc_class Lbl (label labl) %{ // JMP, CALL | |
| 1684 Label *l = $labl$$label; | |
| 1685 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); | |
| 1686 %} | |
| 1687 | |
| 1688 enc_class LblShort (label labl) %{ // JMP, CALL | |
| 1689 Label *l = $labl$$label; | |
| 1690 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; | |
| 1691 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 1692 emit_d8(cbuf, disp); | |
| 1693 %} | |
| 1694 | |
| 1695 enc_class OpcSReg (eRegI dst) %{ // BSWAP | |
| 1696 emit_cc(cbuf, $secondary, $dst$$reg ); | |
| 1697 %} | |
| 1698 | |
| 1699 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1700 int destlo = $dst$$reg; | |
| 1701 int desthi = HIGH_FROM_LOW(destlo); | |
| 1702 // bswap lo | |
| 1703 emit_opcode(cbuf, 0x0F); | |
| 1704 emit_cc(cbuf, 0xC8, destlo); | |
| 1705 // bswap hi | |
| 1706 emit_opcode(cbuf, 0x0F); | |
| 1707 emit_cc(cbuf, 0xC8, desthi); | |
| 1708 // xchg lo and hi | |
| 1709 emit_opcode(cbuf, 0x87); | |
| 1710 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1711 %} | |
| 1712 | |
| 1713 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... | |
| 1714 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); | |
| 1715 %} | |
| 1716 | |
| 1717 enc_class Jcc (cmpOp cop, label labl) %{ // JCC | |
| 1718 Label *l = $labl$$label; | |
| 1719 $$$emit8$primary; | |
| 1720 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1721 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); | |
| 1722 %} | |
| 1723 | |
| 1724 enc_class JccShort (cmpOp cop, label labl) %{ // JCC | |
| 1725 Label *l = $labl$$label; | |
| 1726 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 1727 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; | |
| 1728 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 1729 emit_d8(cbuf, disp); | |
| 1730 %} | |
| 1731 | |
| 1732 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1733 $$$emit8$primary; | |
| 1734 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1735 %} | |
| 1736 | |
| 1737 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV | |
| 1738 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); | |
| 1739 emit_d8(cbuf, op >> 8 ); | |
| 1740 emit_d8(cbuf, op & 255); | |
| 1741 %} | |
| 1742 | |
| 1743 // emulate a CMOV with a conditional branch around a MOV | |
| 1744 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1745 // Invert sense of branch from sense of CMOV | |
| 1746 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1747 emit_d8( cbuf, $brOffs$$constant ); | |
| 1748 %} | |
| 1749 | |
| 1750 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1751 Register Redi = as_Register(EDI_enc); // result register | |
| 1752 Register Reax = as_Register(EAX_enc); // super class | |
| 1753 Register Recx = as_Register(ECX_enc); // killed | |
| 1754 Register Resi = as_Register(ESI_enc); // sub class | |
|
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|
1755 Label miss; |
| 0 | 1756 |
| 1757 MacroAssembler _masm(&cbuf); | |
|
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|
1758 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
|
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|
1759 NULL, &miss, |
|
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|
1760 /*set_cond_codes:*/ true); |
|
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|
1761 if ($primary) { |
|
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|
1762 __ xorptr(Redi, Redi); |
|
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|
1763 } |
| 0 | 1764 __ bind(miss); |
| 1765 %} | |
| 1766 | |
| 1767 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1768 MacroAssembler masm(&cbuf); | |
| 1769 int start = masm.offset(); | |
| 1770 if (UseSSE >= 2) { | |
| 1771 if (VerifyFPU) { | |
| 1772 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1773 } | |
| 1774 } else { | |
| 1775 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1776 // Compiled code leaves it dirty. Do cleanup now. | |
| 1777 masm.empty_FPU_stack(); | |
| 1778 } | |
| 1779 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1780 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1781 } else { | |
| 1782 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1783 } | |
| 1784 %} | |
| 1785 | |
| 1786 enc_class Verify_FPU_For_Leaf %{ | |
| 1787 if( VerifyFPU ) { | |
| 1788 MacroAssembler masm(&cbuf); | |
| 1789 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1790 } | |
| 1791 %} | |
| 1792 | |
| 1793 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1794 // This is the instruction starting address for relocation info. | |
| 1795 cbuf.set_inst_mark(); | |
| 1796 $$$emit8$primary; | |
| 1797 // CALL directly to the runtime | |
| 1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1799 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1800 | |
| 1801 if (UseSSE >= 2) { | |
| 1802 MacroAssembler _masm(&cbuf); | |
| 1803 BasicType rt = tf()->return_type(); | |
| 1804 | |
| 1805 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1806 // A C runtime call where the return value is unused. In SSE2+ | |
| 1807 // mode the result needs to be removed from the FPU stack. It's | |
| 1808 // likely that this function call could be removed by the | |
| 1809 // optimizer if the C function is a pure function. | |
| 1810 __ ffree(0); | |
| 1811 } else if (rt == T_FLOAT) { | |
| 304 | 1812 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1813 __ fstp_s(Address(rsp, 0)); |
| 1814 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1815 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1816 } else if (rt == T_DOUBLE) { |
| 304 | 1817 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1818 __ fstp_d(Address(rsp, 0)); |
| 1819 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1820 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1821 } |
| 1822 } | |
| 1823 %} | |
| 1824 | |
| 1825 | |
| 1826 enc_class pre_call_FPU %{ | |
| 1827 // If method sets FPU control word restore it here | |
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1828 debug_only(int off0 = cbuf.code_size()); |
| 0 | 1829 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1830 MacroAssembler masm(&cbuf); | |
| 1831 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1832 } | |
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1833 debug_only(int off1 = cbuf.code_size()); |
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1834 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1835 %} |
| 1836 | |
| 1837 enc_class post_call_FPU %{ | |
| 1838 // If method sets FPU control word do it here also | |
| 1839 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1840 MacroAssembler masm(&cbuf); | |
| 1841 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1842 } | |
| 1843 %} | |
| 1844 | |
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1845 enc_class preserve_SP %{ |
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1846 debug_only(int off0 = cbuf.code_size()); |
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1847 MacroAssembler _masm(&cbuf); |
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1848 // RBP is preserved across all calls, even compiled calls. |
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1849 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 1850 __ movptr(rbp_mh_SP_save, rsp); |
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1851 debug_only(int off1 = cbuf.code_size()); |
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1852 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
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1853 %} |
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1854 |
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1855 enc_class restore_SP %{ |
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1856 MacroAssembler _masm(&cbuf); |
| 1567 | 1857 __ movptr(rsp, rbp_mh_SP_save); |
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1858 %} |
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1859 |
| 0 | 1860 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 1861 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1862 // who we intended to call. | |
| 1863 cbuf.set_inst_mark(); | |
| 1864 $$$emit8$primary; | |
| 1865 if ( !_method ) { | |
| 1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1867 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1868 } else if(_optimized_virtual) { | |
| 1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1870 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1871 } else { | |
| 1872 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1873 static_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1874 } | |
| 1875 if( _method ) { // Emit stub for static call | |
| 1876 emit_java_to_interp(cbuf); | |
| 1877 } | |
| 1878 %} | |
| 1879 | |
| 1880 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 1881 // !!!!! | |
| 1882 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info | |
| 1883 // emit_call_dynamic_prologue( cbuf ); | |
| 1884 cbuf.set_inst_mark(); | |
| 1885 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 | |
| 1886 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); | |
| 1887 address virtual_call_oop_addr = cbuf.inst_mark(); | |
| 1888 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1889 // who we intended to call. | |
| 1890 cbuf.set_inst_mark(); | |
| 1891 $$$emit8$primary; | |
| 1892 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), | |
| 1893 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); | |
| 1894 %} | |
| 1895 | |
| 1896 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 1897 int disp = in_bytes(methodOopDesc::from_compiled_offset()); | |
| 1898 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); | |
| 1899 | |
| 1900 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] | |
| 1901 cbuf.set_inst_mark(); | |
| 1902 $$$emit8$primary; | |
| 1903 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1904 emit_d8(cbuf, disp); // Displacement | |
| 1905 | |
| 1906 %} | |
| 1907 | |
| 1908 enc_class Xor_Reg (eRegI dst) %{ | |
| 1909 emit_opcode(cbuf, 0x33); | |
| 1910 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 1911 %} | |
| 1912 | |
| 1913 // Following encoding is no longer used, but may be restored if calling | |
| 1914 // convention changes significantly. | |
| 1915 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1916 // | |
| 1917 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1918 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1919 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1920 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1921 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1922 // | |
| 1923 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1924 // // // so we load it immediately before the call | |
| 1925 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1926 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1927 // | |
| 1928 // // xor rbp,ebp | |
| 1929 // emit_opcode(cbuf, 0x33); | |
| 1930 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1931 // | |
| 1932 // // CALL to interpreter. | |
| 1933 // cbuf.set_inst_mark(); | |
| 1934 // $$$emit8$primary; | |
| 1935 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4), | |
| 1936 // runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 1937 // %} | |
| 1938 | |
| 1939 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR | |
| 1940 $$$emit8$primary; | |
| 1941 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1942 $$$emit8$shift$$constant; | |
| 1943 %} | |
| 1944 | |
| 1945 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate | |
| 1946 // Load immediate does not have a zero or sign extended version | |
| 1947 // for 8-bit immediates | |
| 1948 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1949 $$$emit32$src$$constant; | |
| 1950 %} | |
| 1951 | |
| 1952 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate | |
| 1953 // Load immediate does not have a zero or sign extended version | |
| 1954 // for 8-bit immediates | |
| 1955 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1956 $$$emit32$src$$constant; | |
| 1957 %} | |
| 1958 | |
| 1959 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1960 // Load immediate does not have a zero or sign extended version | |
| 1961 // for 8-bit immediates | |
| 1962 int dst_enc = $dst$$reg; | |
| 1963 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1964 if (src_con == 0) { | |
| 1965 // xor dst, dst | |
| 1966 emit_opcode(cbuf, 0x33); | |
| 1967 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1968 } else { | |
| 1969 emit_opcode(cbuf, $primary + dst_enc); | |
| 1970 emit_d32(cbuf, src_con); | |
| 1971 } | |
| 1972 %} | |
| 1973 | |
| 1974 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1975 // Load immediate does not have a zero or sign extended version | |
| 1976 // for 8-bit immediates | |
| 1977 int dst_enc = $dst$$reg + 2; | |
| 1978 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1979 if (src_con == 0) { | |
| 1980 // xor dst, dst | |
| 1981 emit_opcode(cbuf, 0x33); | |
| 1982 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1983 } else { | |
| 1984 emit_opcode(cbuf, $primary + dst_enc); | |
| 1985 emit_d32(cbuf, src_con); | |
| 1986 } | |
| 1987 %} | |
| 1988 | |
| 1989 | |
| 1990 enc_class LdImmD (immD src) %{ // Load Immediate | |
| 1991 if( is_positive_zero_double($src$$constant)) { | |
| 1992 // FLDZ | |
| 1993 emit_opcode(cbuf,0xD9); | |
| 1994 emit_opcode(cbuf,0xEE); | |
| 1995 } else if( is_positive_one_double($src$$constant)) { | |
| 1996 // FLD1 | |
| 1997 emit_opcode(cbuf,0xD9); | |
| 1998 emit_opcode(cbuf,0xE8); | |
| 1999 } else { | |
| 2000 emit_opcode(cbuf,0xDD); | |
| 2001 emit_rm(cbuf, 0x0, 0x0, 0x5); | |
| 2002 emit_double_constant(cbuf, $src$$constant); | |
| 2003 } | |
| 2004 %} | |
| 2005 | |
| 2006 | |
| 2007 enc_class LdImmF (immF src) %{ // Load Immediate | |
| 2008 if( is_positive_zero_float($src$$constant)) { | |
| 2009 emit_opcode(cbuf,0xD9); | |
| 2010 emit_opcode(cbuf,0xEE); | |
| 2011 } else if( is_positive_one_float($src$$constant)) { | |
| 2012 emit_opcode(cbuf,0xD9); | |
| 2013 emit_opcode(cbuf,0xE8); | |
| 2014 } else { | |
| 2015 $$$emit8$primary; | |
| 2016 // Load immediate does not have a zero or sign extended version | |
| 2017 // for 8-bit immediates | |
| 2018 // First load to TOS, then move to dst | |
| 2019 emit_rm(cbuf, 0x0, 0x0, 0x5); | |
| 2020 emit_float_constant(cbuf, $src$$constant); | |
| 2021 } | |
| 2022 %} | |
| 2023 | |
| 2024 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate | |
| 2025 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 2026 emit_float_constant(cbuf, $con$$constant); | |
| 2027 %} | |
| 2028 | |
| 2029 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate | |
| 2030 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 2031 emit_double_constant(cbuf, $con$$constant); | |
| 2032 %} | |
| 2033 | |
| 2034 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant | |
| 2035 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
| 2036 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2037 emit_opcode(cbuf, 0x0F); | |
| 2038 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2039 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 2040 emit_double_constant(cbuf, $con$$constant); | |
| 2041 %} | |
| 2042 | |
| 2043 enc_class Opc_MemImm_F(immF src) %{ | |
| 2044 cbuf.set_inst_mark(); | |
| 2045 $$$emit8$primary; | |
| 2046 emit_rm(cbuf, 0x0, $secondary, 0x5); | |
| 2047 emit_float_constant(cbuf, $src$$constant); | |
| 2048 %} | |
| 2049 | |
| 2050 | |
| 2051 enc_class MovI2X_reg(regX dst, eRegI src) %{ | |
| 2052 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2053 emit_opcode(cbuf, 0x0F ); | |
| 2054 emit_opcode(cbuf, 0x6E ); | |
| 2055 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2056 %} | |
| 2057 | |
| 2058 enc_class MovX2I_reg(eRegI dst, regX src) %{ | |
| 2059 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2060 emit_opcode(cbuf, 0x0F ); | |
| 2061 emit_opcode(cbuf, 0x7E ); | |
| 2062 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2063 %} | |
| 2064 | |
| 2065 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ | |
| 2066 { // MOVD $dst,$src.lo | |
| 2067 emit_opcode(cbuf,0x66); | |
| 2068 emit_opcode(cbuf,0x0F); | |
| 2069 emit_opcode(cbuf,0x6E); | |
| 2070 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2071 } | |
| 2072 { // MOVD $tmp,$src.hi | |
| 2073 emit_opcode(cbuf,0x66); | |
| 2074 emit_opcode(cbuf,0x0F); | |
| 2075 emit_opcode(cbuf,0x6E); | |
| 2076 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2077 } | |
| 2078 { // PUNPCKLDQ $dst,$tmp | |
| 2079 emit_opcode(cbuf,0x66); | |
| 2080 emit_opcode(cbuf,0x0F); | |
| 2081 emit_opcode(cbuf,0x62); | |
| 2082 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); | |
| 2083 } | |
| 2084 %} | |
| 2085 | |
| 2086 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ | |
| 2087 { // MOVD $dst.lo,$src | |
| 2088 emit_opcode(cbuf,0x66); | |
| 2089 emit_opcode(cbuf,0x0F); | |
| 2090 emit_opcode(cbuf,0x7E); | |
| 2091 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2092 } | |
| 2093 { // PSHUFLW $tmp,$src,0x4E (01001110b) | |
| 2094 emit_opcode(cbuf,0xF2); | |
| 2095 emit_opcode(cbuf,0x0F); | |
| 2096 emit_opcode(cbuf,0x70); | |
| 2097 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2098 emit_d8(cbuf, 0x4E); | |
| 2099 } | |
| 2100 { // MOVD $dst.hi,$tmp | |
| 2101 emit_opcode(cbuf,0x66); | |
| 2102 emit_opcode(cbuf,0x0F); | |
| 2103 emit_opcode(cbuf,0x7E); | |
| 2104 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2105 } | |
| 2106 %} | |
| 2107 | |
| 2108 | |
| 2109 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2110 enc_class enc_Copy( eRegI dst, eRegI src ) %{ | |
| 2111 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2112 %} | |
| 2113 | |
| 2114 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ | |
| 2115 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2116 %} | |
| 2117 | |
| 2118 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2119 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ | |
| 2120 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2121 %} | |
| 2122 | |
| 2123 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 2124 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2125 %} | |
| 2126 | |
| 2127 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2128 $$$emit8$primary; | |
| 2129 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2130 %} | |
| 2131 | |
| 2132 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2133 $$$emit8$secondary; | |
| 2134 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2135 %} | |
| 2136 | |
| 2137 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2138 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2139 %} | |
| 2140 | |
| 2141 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2142 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ | |
| 2146 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2147 %} | |
| 2148 | |
| 2149 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2150 // Output immediate | |
| 2151 $$$emit32$src$$constant; | |
| 2152 %} | |
| 2153 | |
| 2154 enc_class Con32F_as_bits(immF src) %{ // storeF_imm | |
| 2155 // Output Float immediate bits | |
| 2156 jfloat jf = $src$$constant; | |
| 2157 int jf_as_bits = jint_cast( jf ); | |
| 2158 emit_d32(cbuf, jf_as_bits); | |
| 2159 %} | |
| 2160 | |
| 2161 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm | |
| 2162 // Output Float immediate bits | |
| 2163 jfloat jf = $src$$constant; | |
| 2164 int jf_as_bits = jint_cast( jf ); | |
| 2165 emit_d32(cbuf, jf_as_bits); | |
| 2166 %} | |
| 2167 | |
| 2168 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2169 // Output immediate | |
| 2170 $$$emit16$src$$constant; | |
| 2171 %} | |
| 2172 | |
| 2173 enc_class Con_d32(immI src) %{ | |
| 2174 emit_d32(cbuf,$src$$constant); | |
| 2175 %} | |
| 2176 | |
| 2177 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2178 // Output immediate memory reference | |
| 2179 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2180 emit_d32(cbuf, 0x00); | |
| 2181 %} | |
| 2182 | |
| 2183 enc_class lock_prefix( ) %{ | |
| 2184 if( os::is_MP() ) | |
| 2185 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2186 %} | |
| 2187 | |
| 2188 // Cmp-xchg long value. | |
| 2189 // Note: we need to swap rbx, and rcx before and after the | |
| 2190 // cmpxchg8 instruction because the instruction uses | |
| 2191 // rcx as the high order word of the new value to store but | |
| 2192 // our register encoding uses rbx,. | |
| 2193 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2194 | |
| 2195 // XCHG rbx,ecx | |
| 2196 emit_opcode(cbuf,0x87); | |
| 2197 emit_opcode(cbuf,0xD9); | |
| 2198 // [Lock] | |
| 2199 if( os::is_MP() ) | |
| 2200 emit_opcode(cbuf,0xF0); | |
| 2201 // CMPXCHG8 [Eptr] | |
| 2202 emit_opcode(cbuf,0x0F); | |
| 2203 emit_opcode(cbuf,0xC7); | |
| 2204 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2205 // XCHG rbx,ecx | |
| 2206 emit_opcode(cbuf,0x87); | |
| 2207 emit_opcode(cbuf,0xD9); | |
| 2208 %} | |
| 2209 | |
| 2210 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2211 // [Lock] | |
| 2212 if( os::is_MP() ) | |
| 2213 emit_opcode(cbuf,0xF0); | |
| 2214 | |
| 2215 // CMPXCHG [Eptr] | |
| 2216 emit_opcode(cbuf,0x0F); | |
| 2217 emit_opcode(cbuf,0xB1); | |
| 2218 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2219 %} | |
| 2220 | |
| 2221 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2222 int res_encoding = $res$$reg; | |
| 2223 | |
| 2224 // MOV res,0 | |
| 2225 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2226 emit_d32( cbuf, 0 ); | |
| 2227 // JNE,s fail | |
| 2228 emit_opcode(cbuf,0x75); | |
| 2229 emit_d8(cbuf, 5 ); | |
| 2230 // MOV res,1 | |
| 2231 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2232 emit_d32( cbuf, 1 ); | |
| 2233 // fail: | |
| 2234 %} | |
| 2235 | |
| 2236 enc_class set_instruction_start( ) %{ | |
| 2237 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2238 %} | |
| 2239 | |
| 2240 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 2241 int reg_encoding = $ereg$$reg; | |
| 2242 int base = $mem$$base; | |
| 2243 int index = $mem$$index; | |
| 2244 int scale = $mem$$scale; | |
| 2245 int displace = $mem$$disp; | |
| 2246 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2247 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2248 %} | |
| 2249 | |
| 2250 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2251 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2252 int base = $mem$$base; | |
| 2253 int index = $mem$$index; | |
| 2254 int scale = $mem$$scale; | |
| 2255 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
| 2256 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); | |
| 2257 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); | |
| 2258 %} | |
| 2259 | |
| 2260 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2261 int r1, r2; | |
| 2262 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2263 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2264 emit_opcode(cbuf,0x0F); | |
| 2265 emit_opcode(cbuf,$tertiary); | |
| 2266 emit_rm(cbuf, 0x3, r1, r2); | |
| 2267 emit_d8(cbuf,$cnt$$constant); | |
| 2268 emit_d8(cbuf,$primary); | |
| 2269 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2270 emit_d8(cbuf,$cnt$$constant); | |
| 2271 %} | |
| 2272 | |
| 2273 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2274 emit_opcode( cbuf, 0x8B ); // Move | |
| 2275 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2276 emit_d8(cbuf,$primary); | |
| 2277 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 2278 emit_d8(cbuf,$cnt$$constant-32); | |
| 2279 emit_d8(cbuf,$primary); | |
| 2280 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2281 emit_d8(cbuf,31); | |
| 2282 %} | |
| 2283 | |
| 2284 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2285 int r1, r2; | |
| 2286 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2287 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2288 | |
| 2289 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2290 emit_rm(cbuf, 0x3, r1, r2); | |
| 2291 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2292 emit_opcode(cbuf,$primary); | |
| 2293 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2294 emit_d8(cbuf,$cnt$$constant-32); | |
| 2295 } | |
| 2296 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2297 emit_rm(cbuf, 0x3, r2, r2); | |
| 2298 %} | |
| 2299 | |
| 2300 // Clone of RegMem but accepts an extra parameter to access each | |
| 2301 // half of a double in memory; it never needs relocation info. | |
| 2302 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ | |
| 2303 emit_opcode(cbuf,$opcode$$constant); | |
| 2304 int reg_encoding = $rm_reg$$reg; | |
| 2305 int base = $mem$$base; | |
| 2306 int index = $mem$$index; | |
| 2307 int scale = $mem$$scale; | |
| 2308 int displace = $mem$$disp + $disp_for_half$$constant; | |
| 2309 bool disp_is_oop = false; | |
| 2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2311 %} | |
| 2312 | |
| 2313 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2314 // | |
| 2315 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2316 // and it never needs relocation information. | |
| 2317 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2318 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2319 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2320 int base = $mem$$base; | |
| 2321 int index = $mem$$index; | |
| 2322 int scale = $mem$$scale; | |
| 2323 int displace = $mem$$disp; | |
| 2324 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); | |
| 2325 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); | |
| 2326 %} | |
| 2327 | |
| 2328 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2329 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2330 int base = $mem$$base; | |
| 2331 int index = $mem$$index; | |
| 2332 int scale = $mem$$scale; | |
| 2333 int displace = $mem$$disp; | |
| 2334 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2335 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 2336 %} | |
| 2337 | |
| 2338 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea | |
| 2339 int reg_encoding = $dst$$reg; | |
| 2340 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2341 int index = 0x04; // 0x04 indicates no index | |
| 2342 int scale = 0x00; // 0x00 indicates no scale | |
| 2343 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2344 bool disp_is_oop = false; | |
| 2345 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN | |
| 2349 // Compare dst,src | |
| 2350 emit_opcode(cbuf,0x3B); | |
| 2351 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2352 // jmp dst < src around move | |
| 2353 emit_opcode(cbuf,0x7C); | |
| 2354 emit_d8(cbuf,2); | |
| 2355 // move dst,src | |
| 2356 emit_opcode(cbuf,0x8B); | |
| 2357 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2358 %} | |
| 2359 | |
| 2360 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX | |
| 2361 // Compare dst,src | |
| 2362 emit_opcode(cbuf,0x3B); | |
| 2363 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2364 // jmp dst > src around move | |
| 2365 emit_opcode(cbuf,0x7F); | |
| 2366 emit_d8(cbuf,2); | |
| 2367 // move dst,src | |
| 2368 emit_opcode(cbuf,0x8B); | |
| 2369 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2370 %} | |
| 2371 | |
| 2372 enc_class enc_FP_store(memory mem, regD src) %{ | |
| 2373 // If src is FPR1, we can just FST to store it. | |
| 2374 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2375 int reg_encoding = 0x2; // Just store | |
| 2376 int base = $mem$$base; | |
| 2377 int index = $mem$$index; | |
| 2378 int scale = $mem$$scale; | |
| 2379 int displace = $mem$$disp; | |
| 2380 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2381 if( $src$$reg != FPR1L_enc ) { | |
| 2382 reg_encoding = 0x3; // Store & pop | |
| 2383 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2384 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2385 } | |
| 2386 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2387 emit_opcode(cbuf,$primary); | |
| 2388 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2389 %} | |
| 2390 | |
| 2391 enc_class neg_reg(eRegI dst) %{ | |
| 2392 // NEG $dst | |
| 2393 emit_opcode(cbuf,0xF7); | |
| 2394 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2395 %} | |
| 2396 | |
| 2397 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2398 // SETLT $dst | |
| 2399 emit_opcode(cbuf,0x0F); | |
| 2400 emit_opcode(cbuf,0x9C); | |
| 2401 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2402 %} | |
| 2403 | |
| 2404 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2405 int tmpReg = $tmp$$reg; | |
| 2406 | |
| 2407 // SUB $p,$q | |
| 2408 emit_opcode(cbuf,0x2B); | |
| 2409 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2410 // SBB $tmp,$tmp | |
| 2411 emit_opcode(cbuf,0x1B); | |
| 2412 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2413 // AND $tmp,$y | |
| 2414 emit_opcode(cbuf,0x23); | |
| 2415 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2416 // ADD $p,$tmp | |
| 2417 emit_opcode(cbuf,0x03); | |
| 2418 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2419 %} | |
| 2420 | |
| 2421 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2422 int tmpReg = $tmp$$reg; | |
| 2423 | |
| 2424 // SUB $p,$q | |
| 2425 emit_opcode(cbuf,0x2B); | |
| 2426 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2427 // SBB $tmp,$tmp | |
| 2428 emit_opcode(cbuf,0x1B); | |
| 2429 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2430 // AND $tmp,$y | |
| 2431 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand | |
| 2432 emit_opcode(cbuf,0x23); | |
| 2433 int reg_encoding = tmpReg; | |
| 2434 int base = $mem$$base; | |
| 2435 int index = $mem$$index; | |
| 2436 int scale = $mem$$scale; | |
| 2437 int displace = $mem$$disp; | |
| 2438 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2439 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2440 // ADD $p,$tmp | |
| 2441 emit_opcode(cbuf,0x03); | |
| 2442 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2443 %} | |
| 2444 | |
| 2445 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2446 // TEST shift,32 | |
| 2447 emit_opcode(cbuf,0xF7); | |
| 2448 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2449 emit_d32(cbuf,0x20); | |
| 2450 // JEQ,s small | |
| 2451 emit_opcode(cbuf, 0x74); | |
| 2452 emit_d8(cbuf, 0x04); | |
| 2453 // MOV $dst.hi,$dst.lo | |
| 2454 emit_opcode( cbuf, 0x8B ); | |
| 2455 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2456 // CLR $dst.lo | |
| 2457 emit_opcode(cbuf, 0x33); | |
| 2458 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2459 // small: | |
| 2460 // SHLD $dst.hi,$dst.lo,$shift | |
| 2461 emit_opcode(cbuf,0x0F); | |
| 2462 emit_opcode(cbuf,0xA5); | |
| 2463 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2464 // SHL $dst.lo,$shift" | |
| 2465 emit_opcode(cbuf,0xD3); | |
| 2466 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2467 %} | |
| 2468 | |
| 2469 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2470 // TEST shift,32 | |
| 2471 emit_opcode(cbuf,0xF7); | |
| 2472 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2473 emit_d32(cbuf,0x20); | |
| 2474 // JEQ,s small | |
| 2475 emit_opcode(cbuf, 0x74); | |
| 2476 emit_d8(cbuf, 0x04); | |
| 2477 // MOV $dst.lo,$dst.hi | |
| 2478 emit_opcode( cbuf, 0x8B ); | |
| 2479 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2480 // CLR $dst.hi | |
| 2481 emit_opcode(cbuf, 0x33); | |
| 2482 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2483 // small: | |
| 2484 // SHRD $dst.lo,$dst.hi,$shift | |
| 2485 emit_opcode(cbuf,0x0F); | |
| 2486 emit_opcode(cbuf,0xAD); | |
| 2487 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2488 // SHR $dst.hi,$shift" | |
| 2489 emit_opcode(cbuf,0xD3); | |
| 2490 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2491 %} | |
| 2492 | |
| 2493 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2494 // TEST shift,32 | |
| 2495 emit_opcode(cbuf,0xF7); | |
| 2496 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2497 emit_d32(cbuf,0x20); | |
| 2498 // JEQ,s small | |
| 2499 emit_opcode(cbuf, 0x74); | |
| 2500 emit_d8(cbuf, 0x05); | |
| 2501 // MOV $dst.lo,$dst.hi | |
| 2502 emit_opcode( cbuf, 0x8B ); | |
| 2503 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2504 // SAR $dst.hi,31 | |
| 2505 emit_opcode(cbuf, 0xC1); | |
| 2506 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2507 emit_d8(cbuf, 0x1F ); | |
| 2508 // small: | |
| 2509 // SHRD $dst.lo,$dst.hi,$shift | |
| 2510 emit_opcode(cbuf,0x0F); | |
| 2511 emit_opcode(cbuf,0xAD); | |
| 2512 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2513 // SAR $dst.hi,$shift" | |
| 2514 emit_opcode(cbuf,0xD3); | |
| 2515 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2516 %} | |
| 2517 | |
| 2518 | |
| 2519 // ----------------- Encodings for floating point unit ----------------- | |
| 2520 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
| 2521 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV | |
| 2522 $$$emit8$primary; | |
| 2523 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2524 %} | |
| 2525 | |
| 2526 // Pop argument in FPR0 with FSTP ST(0) | |
| 2527 enc_class PopFPU() %{ | |
| 2528 emit_opcode( cbuf, 0xDD ); | |
| 2529 emit_d8( cbuf, 0xD8 ); | |
| 2530 %} | |
| 2531 | |
| 2532 // !!!!! equivalent to Pop_Reg_F | |
| 2533 enc_class Pop_Reg_D( regD dst ) %{ | |
| 2534 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2535 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2536 %} | |
| 2537 | |
| 2538 enc_class Push_Reg_D( regD dst ) %{ | |
| 2539 emit_opcode( cbuf, 0xD9 ); | |
| 2540 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2541 %} | |
| 2542 | |
| 2543 enc_class strictfp_bias1( regD dst ) %{ | |
| 2544 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2545 emit_opcode( cbuf, 0x2D ); | |
| 2546 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2547 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2548 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2549 %} | |
| 2550 | |
| 2551 enc_class strictfp_bias2( regD dst ) %{ | |
| 2552 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2553 emit_opcode( cbuf, 0x2D ); | |
| 2554 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2555 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2556 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2557 %} | |
| 2558 | |
| 2559 // Special case for moving an integer register to a stack slot. | |
| 2560 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2561 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); | |
| 2562 %} | |
| 2563 | |
| 2564 // Special case for moving a register to a stack slot. | |
| 2565 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2566 // Opcode already emitted | |
| 2567 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2568 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2569 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2570 %} | |
| 2571 | |
| 2572 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2573 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2574 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2575 %} | |
| 2576 | |
| 2577 // Push the float in stackSlot 'src' onto FP-stack | |
| 2578 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] | |
| 2579 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); | |
| 2580 %} | |
| 2581 | |
| 2582 // Push the double in stackSlot 'src' onto FP-stack | |
| 2583 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] | |
| 2584 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); | |
| 2585 %} | |
| 2586 | |
| 2587 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
| 2588 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] | |
| 2589 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); | |
| 2590 %} | |
| 2591 | |
| 2592 // Same as Pop_Mem_F except for opcode | |
| 2593 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
| 2594 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] | |
| 2595 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); | |
| 2596 %} | |
| 2597 | |
| 2598 enc_class Pop_Reg_F( regF dst ) %{ | |
| 2599 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2600 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2601 %} | |
| 2602 | |
| 2603 enc_class Push_Reg_F( regF dst ) %{ | |
| 2604 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2605 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2606 %} | |
| 2607 | |
| 2608 // Push FPU's float to a stack-slot, and pop FPU-stack | |
| 2609 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ | |
| 2610 int pop = 0x02; | |
| 2611 if ($src$$reg != FPR1L_enc) { | |
| 2612 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2613 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2614 pop = 0x03; | |
| 2615 } | |
| 2616 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2617 %} | |
| 2618 | |
| 2619 // Push FPU's double to a stack-slot, and pop FPU-stack | |
| 2620 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ | |
| 2621 int pop = 0x02; | |
| 2622 if ($src$$reg != FPR1L_enc) { | |
| 2623 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2624 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2625 pop = 0x03; | |
| 2626 } | |
| 2627 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2628 %} | |
| 2629 | |
| 2630 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
| 2631 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ | |
| 2632 int pop = 0xD0 - 1; // -1 since we skip FLD | |
| 2633 if ($src$$reg != FPR1L_enc) { | |
| 2634 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2635 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2636 pop = 0xD8; | |
| 2637 } | |
| 2638 emit_opcode( cbuf, 0xDD ); | |
| 2639 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2640 %} | |
| 2641 | |
| 2642 | |
| 2643 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ | |
| 2644 MacroAssembler masm(&cbuf); | |
| 2645 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg | |
| 2646 masm.fmul( $src2$$reg+0); // value at TOS | |
| 2647 masm.fadd( $src$$reg+0); // value at TOS | |
| 2648 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store | |
| 2649 %} | |
| 2650 | |
| 2651 | |
| 2652 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ | |
| 2653 // load dst in FPR0 | |
| 2654 emit_opcode( cbuf, 0xD9 ); | |
| 2655 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2656 if ($src$$reg != FPR1L_enc) { | |
| 2657 // fincstp | |
| 2658 emit_opcode (cbuf, 0xD9); | |
| 2659 emit_opcode (cbuf, 0xF7); | |
| 2660 // swap src with FPR1: | |
| 2661 // FXCH FPR1 with src | |
| 2662 emit_opcode(cbuf, 0xD9); | |
| 2663 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2664 // fdecstp | |
| 2665 emit_opcode (cbuf, 0xD9); | |
| 2666 emit_opcode (cbuf, 0xF6); | |
| 2667 } | |
| 2668 %} | |
| 2669 | |
| 2670 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ | |
| 2671 // Allocate a word | |
| 2672 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2673 emit_opcode(cbuf,0xEC); | |
| 2674 emit_d8(cbuf,0x08); | |
| 2675 | |
| 2676 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 | |
| 2677 emit_opcode (cbuf, 0x0F ); | |
| 2678 emit_opcode (cbuf, 0x11 ); | |
| 2679 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2680 | |
| 2681 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2682 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2683 | |
| 2684 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 | |
| 2685 emit_opcode (cbuf, 0x0F ); | |
| 2686 emit_opcode (cbuf, 0x11 ); | |
| 2687 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2688 | |
| 2689 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2690 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2691 | |
| 2692 %} | |
| 2693 | |
| 2694 enc_class Push_ModX_encoding( regX src0, regX src1) %{ | |
| 2695 // Allocate a word | |
| 2696 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2697 emit_opcode(cbuf,0xEC); | |
| 2698 emit_d8(cbuf,0x04); | |
| 2699 | |
| 2700 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 | |
| 2701 emit_opcode (cbuf, 0x0F ); | |
| 2702 emit_opcode (cbuf, 0x11 ); | |
| 2703 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2704 | |
| 2705 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2706 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2707 | |
| 2708 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 | |
| 2709 emit_opcode (cbuf, 0x0F ); | |
| 2710 emit_opcode (cbuf, 0x11 ); | |
| 2711 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2712 | |
| 2713 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2714 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2715 | |
| 2716 %} | |
| 2717 | |
| 2718 enc_class Push_ResultXD(regXD dst) %{ | |
| 2719 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] | |
| 2720 | |
| 2721 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] | |
| 2722 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2723 emit_opcode (cbuf, 0x0F ); | |
| 2724 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2725 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2726 | |
| 2727 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2728 emit_opcode(cbuf,0xC4); | |
| 2729 emit_d8(cbuf,0x08); | |
| 2730 %} | |
| 2731 | |
| 2732 enc_class Push_ResultX(regX dst, immI d8) %{ | |
| 2733 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] | |
| 2734 | |
| 2735 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 2736 emit_opcode (cbuf, 0x0F ); | |
| 2737 emit_opcode (cbuf, 0x10 ); | |
| 2738 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2739 | |
| 2740 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) | |
| 2741 emit_opcode(cbuf,0xC4); | |
| 2742 emit_d8(cbuf,$d8$$constant); | |
| 2743 %} | |
| 2744 | |
| 2745 enc_class Push_SrcXD(regXD src) %{ | |
| 2746 // Allocate a word | |
| 2747 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2748 emit_opcode(cbuf,0xEC); | |
| 2749 emit_d8(cbuf,0x08); | |
| 2750 | |
| 2751 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 2752 emit_opcode (cbuf, 0x0F ); | |
| 2753 emit_opcode (cbuf, 0x11 ); | |
| 2754 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2755 | |
| 2756 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2757 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2758 %} | |
| 2759 | |
| 2760 enc_class push_stack_temp_qword() %{ | |
| 2761 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2762 emit_opcode(cbuf,0xEC); | |
| 2763 emit_d8 (cbuf,0x08); | |
| 2764 %} | |
| 2765 | |
| 2766 enc_class pop_stack_temp_qword() %{ | |
| 2767 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2768 emit_opcode(cbuf,0xC4); | |
| 2769 emit_d8 (cbuf,0x08); | |
| 2770 %} | |
| 2771 | |
| 2772 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ | |
| 2773 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src | |
| 2774 emit_opcode (cbuf, 0x0F ); | |
| 2775 emit_opcode (cbuf, 0x11 ); | |
| 2776 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2777 | |
| 2778 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2779 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2780 %} | |
| 2781 | |
| 2782 // Compute X^Y using Intel's fast hardware instructions, if possible. | |
| 2783 // Otherwise return a NaN. | |
| 2784 enc_class pow_exp_core_encoding %{ | |
| 2785 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) | |
| 2786 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q | |
| 2787 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q | |
| 2788 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) | |
| 2789 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) | |
| 2790 emit_opcode(cbuf,0x1C); | |
| 2791 emit_d8(cbuf,0x24); | |
| 2792 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 | |
| 2793 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 | |
| 2794 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) | |
| 2795 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) | |
| 2796 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); | |
| 2797 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask | |
| 2798 emit_rm(cbuf, 0x3, 0x0, ECX_enc); | |
| 2799 emit_d32(cbuf,0xFFFFF800); | |
| 2800 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias | |
| 2801 emit_rm(cbuf, 0x3, 0x0, EAX_enc); | |
| 2802 emit_d32(cbuf,1023); | |
| 2803 emit_opcode(cbuf,0x8B); // mov rbx,eax | |
| 2804 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); | |
| 2805 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position | |
| 2806 emit_rm(cbuf,0x3,0x4,EAX_enc); | |
| 2807 emit_d8(cbuf,20); | |
| 2808 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow | |
| 2809 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); | |
| 2810 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX | |
| 2811 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); | |
| 2812 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word | |
| 2813 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); | |
| 2814 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) | |
| 2815 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2816 emit_d32(cbuf,0); | |
| 2817 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q | |
| 2818 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); | |
| 2819 %} | |
| 2820 | |
| 2821 // enc_class Pop_Reg_Mod_D( regD dst, regD src) | |
| 2822 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() | |
| 2823 | |
| 2824 enc_class Push_Result_Mod_D( regD src) %{ | |
| 2825 if ($src$$reg != FPR1L_enc) { | |
| 2826 // fincstp | |
| 2827 emit_opcode (cbuf, 0xD9); | |
| 2828 emit_opcode (cbuf, 0xF7); | |
| 2829 // FXCH FPR1 with src | |
| 2830 emit_opcode(cbuf, 0xD9); | |
| 2831 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2832 // fdecstp | |
| 2833 emit_opcode (cbuf, 0xD9); | |
| 2834 emit_opcode (cbuf, 0xF6); | |
| 2835 } | |
| 2836 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2837 // // FSTP FPR$dst$$reg | |
| 2838 // emit_opcode( cbuf, 0xDD ); | |
| 2839 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2840 %} | |
| 2841 | |
| 2842 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2843 // fnstsw ax | |
| 2844 emit_opcode( cbuf, 0xDF ); | |
| 2845 emit_opcode( cbuf, 0xE0 ); | |
| 2846 // sahf | |
| 2847 emit_opcode( cbuf, 0x9E ); | |
| 2848 // jnp ::skip | |
| 2849 emit_opcode( cbuf, 0x7B ); | |
| 2850 emit_opcode( cbuf, 0x05 ); | |
| 2851 %} | |
| 2852 | |
| 2853 enc_class emitModD() %{ | |
| 2854 // fprem must be iterative | |
| 2855 // :: loop | |
| 2856 // fprem | |
| 2857 emit_opcode( cbuf, 0xD9 ); | |
| 2858 emit_opcode( cbuf, 0xF8 ); | |
| 2859 // wait | |
| 2860 emit_opcode( cbuf, 0x9b ); | |
| 2861 // fnstsw ax | |
| 2862 emit_opcode( cbuf, 0xDF ); | |
| 2863 emit_opcode( cbuf, 0xE0 ); | |
| 2864 // sahf | |
| 2865 emit_opcode( cbuf, 0x9E ); | |
| 2866 // jp ::loop | |
| 2867 emit_opcode( cbuf, 0x0F ); | |
| 2868 emit_opcode( cbuf, 0x8A ); | |
| 2869 emit_opcode( cbuf, 0xF4 ); | |
| 2870 emit_opcode( cbuf, 0xFF ); | |
| 2871 emit_opcode( cbuf, 0xFF ); | |
| 2872 emit_opcode( cbuf, 0xFF ); | |
| 2873 %} | |
| 2874 | |
| 2875 enc_class fpu_flags() %{ | |
| 2876 // fnstsw_ax | |
| 2877 emit_opcode( cbuf, 0xDF); | |
| 2878 emit_opcode( cbuf, 0xE0); | |
| 2879 // test ax,0x0400 | |
| 2880 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2881 emit_opcode( cbuf, 0xA9 ); | |
| 2882 emit_d16 ( cbuf, 0x0400 ); | |
| 2883 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2884 // // test rax,0x0400 | |
| 2885 // emit_opcode( cbuf, 0xA9 ); | |
| 2886 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2887 // | |
| 2888 // jz exit (no unordered comparison) | |
| 2889 emit_opcode( cbuf, 0x74 ); | |
| 2890 emit_d8 ( cbuf, 0x02 ); | |
| 2891 // mov ah,1 - treat as LT case (set carry flag) | |
| 2892 emit_opcode( cbuf, 0xB4 ); | |
| 2893 emit_d8 ( cbuf, 0x01 ); | |
| 2894 // sahf | |
| 2895 emit_opcode( cbuf, 0x9E); | |
| 2896 %} | |
| 2897 | |
| 2898 enc_class cmpF_P6_fixup() %{ | |
| 2899 // Fixup the integer flags in case comparison involved a NaN | |
| 2900 // | |
| 2901 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2902 emit_opcode( cbuf, 0x7B ); | |
| 2903 emit_d8 ( cbuf, 0x03 ); | |
| 2904 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2905 emit_opcode( cbuf, 0xB4 ); | |
| 2906 emit_d8 ( cbuf, 0x01 ); | |
| 2907 // SAHF | |
| 2908 emit_opcode( cbuf, 0x9E); | |
| 2909 // NOP // target for branch to avoid branch to branch | |
| 2910 emit_opcode( cbuf, 0x90); | |
| 2911 %} | |
| 2912 | |
| 2913 // fnstsw_ax(); | |
| 2914 // sahf(); | |
| 2915 // movl(dst, nan_result); | |
| 2916 // jcc(Assembler::parity, exit); | |
| 2917 // movl(dst, less_result); | |
| 2918 // jcc(Assembler::below, exit); | |
| 2919 // movl(dst, equal_result); | |
| 2920 // jcc(Assembler::equal, exit); | |
| 2921 // movl(dst, greater_result); | |
| 2922 | |
| 2923 // less_result = 1; | |
| 2924 // greater_result = -1; | |
| 2925 // equal_result = 0; | |
| 2926 // nan_result = -1; | |
| 2927 | |
| 2928 enc_class CmpF_Result(eRegI dst) %{ | |
| 2929 // fnstsw_ax(); | |
| 2930 emit_opcode( cbuf, 0xDF); | |
| 2931 emit_opcode( cbuf, 0xE0); | |
| 2932 // sahf | |
| 2933 emit_opcode( cbuf, 0x9E); | |
| 2934 // movl(dst, nan_result); | |
| 2935 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2936 emit_d32( cbuf, -1 ); | |
| 2937 // jcc(Assembler::parity, exit); | |
| 2938 emit_opcode( cbuf, 0x7A ); | |
| 2939 emit_d8 ( cbuf, 0x13 ); | |
| 2940 // movl(dst, less_result); | |
| 2941 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2942 emit_d32( cbuf, -1 ); | |
| 2943 // jcc(Assembler::below, exit); | |
| 2944 emit_opcode( cbuf, 0x72 ); | |
| 2945 emit_d8 ( cbuf, 0x0C ); | |
| 2946 // movl(dst, equal_result); | |
| 2947 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2948 emit_d32( cbuf, 0 ); | |
| 2949 // jcc(Assembler::equal, exit); | |
| 2950 emit_opcode( cbuf, 0x74 ); | |
| 2951 emit_d8 ( cbuf, 0x05 ); | |
| 2952 // movl(dst, greater_result); | |
| 2953 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2954 emit_d32( cbuf, 1 ); | |
| 2955 %} | |
| 2956 | |
| 2957 | |
| 2958 // XMM version of CmpF_Result. Because the XMM compare | |
| 2959 // instructions set the EFLAGS directly. It becomes simpler than | |
| 2960 // the float version above. | |
| 2961 enc_class CmpX_Result(eRegI dst) %{ | |
| 2962 MacroAssembler _masm(&cbuf); | |
| 2963 Label nan, inc, done; | |
| 2964 | |
| 2965 __ jccb(Assembler::parity, nan); | |
| 2966 __ jccb(Assembler::equal, done); | |
| 2967 __ jccb(Assembler::above, inc); | |
| 2968 __ bind(nan); | |
| 304 | 2969 __ decrement(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2970 __ jmpb(done); |
| 2971 __ bind(inc); | |
| 304 | 2972 __ increment(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2973 __ bind(done); |
| 2974 %} | |
| 2975 | |
| 2976 // Compare the longs and set flags | |
| 2977 // BROKEN! Do Not use as-is | |
| 2978 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2979 // CMP $src1.hi,$src2.hi | |
| 2980 emit_opcode( cbuf, 0x3B ); | |
| 2981 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2982 // JNE,s done | |
| 2983 emit_opcode(cbuf,0x75); | |
| 2984 emit_d8(cbuf, 2 ); | |
| 2985 // CMP $src1.lo,$src2.lo | |
| 2986 emit_opcode( cbuf, 0x3B ); | |
| 2987 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2988 // done: | |
| 2989 %} | |
| 2990 | |
| 2991 enc_class convert_int_long( regL dst, eRegI src ) %{ | |
| 2992 // mov $dst.lo,$src | |
| 2993 int dst_encoding = $dst$$reg; | |
| 2994 int src_encoding = $src$$reg; | |
| 2995 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2996 // mov $dst.hi,$src | |
| 2997 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2998 // sar $dst.hi,31 | |
| 2999 emit_opcode( cbuf, 0xC1 ); | |
| 3000 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 3001 emit_d8(cbuf, 0x1F ); | |
| 3002 %} | |
| 3003 | |
| 3004 enc_class convert_long_double( eRegL src ) %{ | |
| 3005 // push $src.hi | |
| 3006 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 3007 // push $src.lo | |
| 3008 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 3009 // fild 64-bits at [SP] | |
| 3010 emit_opcode(cbuf,0xdf); | |
| 3011 emit_d8(cbuf, 0x6C); | |
| 3012 emit_d8(cbuf, 0x24); | |
| 3013 emit_d8(cbuf, 0x00); | |
| 3014 // pop stack | |
| 3015 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 3016 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3017 emit_d8(cbuf, 0x8); | |
| 3018 %} | |
| 3019 | |
| 3020 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 3021 // IMUL EDX:EAX,$src1 | |
| 3022 emit_opcode( cbuf, 0xF7 ); | |
| 3023 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 3024 // SAR EDX,$cnt-32 | |
| 3025 int shift_count = ((int)$cnt$$constant) - 32; | |
| 3026 if (shift_count > 0) { | |
| 3027 emit_opcode(cbuf, 0xC1); | |
| 3028 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 3029 emit_d8(cbuf, shift_count); | |
| 3030 } | |
| 3031 %} | |
| 3032 | |
| 3033 // this version doesn't have add sp, 8 | |
| 3034 enc_class convert_long_double2( eRegL src ) %{ | |
| 3035 // push $src.hi | |
| 3036 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 3037 // push $src.lo | |
| 3038 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 3039 // fild 64-bits at [SP] | |
| 3040 emit_opcode(cbuf,0xdf); | |
| 3041 emit_d8(cbuf, 0x6C); | |
| 3042 emit_d8(cbuf, 0x24); | |
| 3043 emit_d8(cbuf, 0x00); | |
| 3044 %} | |
| 3045 | |
| 3046 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3047 // Basic idea: long = (long)int * (long)int | |
| 3048 // IMUL EDX:EAX, src | |
| 3049 emit_opcode( cbuf, 0xF7 ); | |
| 3050 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 3051 %} | |
| 3052 | |
| 3053 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3054 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 3055 // MUL EDX:EAX, src | |
| 3056 emit_opcode( cbuf, 0xF7 ); | |
| 3057 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 3058 %} | |
| 3059 | |
| 3060 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ | |
| 3061 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 3062 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 3063 // MOV $tmp,$src.lo | |
| 3064 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 3065 // IMUL $tmp,EDX | |
| 3066 emit_opcode( cbuf, 0x0F ); | |
| 3067 emit_opcode( cbuf, 0xAF ); | |
| 3068 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3069 // MOV EDX,$src.hi | |
| 3070 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 3071 // IMUL EDX,EAX | |
| 3072 emit_opcode( cbuf, 0x0F ); | |
| 3073 emit_opcode( cbuf, 0xAF ); | |
| 3074 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 3075 // ADD $tmp,EDX | |
| 3076 emit_opcode( cbuf, 0x03 ); | |
| 3077 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3078 // MUL EDX:EAX,$src.lo | |
| 3079 emit_opcode( cbuf, 0xF7 ); | |
| 3080 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 3081 // ADD EDX,ESI | |
| 3082 emit_opcode( cbuf, 0x03 ); | |
| 3083 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 3084 %} | |
| 3085 | |
| 3086 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ | |
| 3087 // Basic idea: lo(result) = lo(src * y_lo) | |
| 3088 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 3089 // IMUL $tmp,EDX,$src | |
| 3090 emit_opcode( cbuf, 0x6B ); | |
| 3091 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3092 emit_d8( cbuf, (int)$src$$constant ); | |
| 3093 // MOV EDX,$src | |
| 3094 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 3095 emit_d32( cbuf, (int)$src$$constant ); | |
| 3096 // MUL EDX:EAX,EDX | |
| 3097 emit_opcode( cbuf, 0xF7 ); | |
| 3098 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 3099 // ADD EDX,ESI | |
| 3100 emit_opcode( cbuf, 0x03 ); | |
| 3101 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 3102 %} | |
| 3103 | |
| 3104 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 3105 // PUSH src1.hi | |
| 3106 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3107 // PUSH src1.lo | |
| 3108 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3109 // PUSH src2.hi | |
| 3110 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3111 // PUSH src2.lo | |
| 3112 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3113 // CALL directly to the runtime | |
| 3114 cbuf.set_inst_mark(); | |
| 3115 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3116 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3117 // Restore stack | |
| 3118 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3119 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3120 emit_d8(cbuf, 4*4); | |
| 3121 %} | |
| 3122 | |
| 3123 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 3124 // PUSH src1.hi | |
| 3125 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3126 // PUSH src1.lo | |
| 3127 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3128 // PUSH src2.hi | |
| 3129 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3130 // PUSH src2.lo | |
| 3131 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3132 // CALL directly to the runtime | |
| 3133 cbuf.set_inst_mark(); | |
| 3134 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3135 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3136 // Restore stack | |
| 3137 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3138 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3139 emit_d8(cbuf, 4*4); | |
| 3140 %} | |
| 3141 | |
| 3142 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ | |
| 3143 // MOV $tmp,$src.lo | |
| 3144 emit_opcode(cbuf, 0x8B); | |
| 3145 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 3146 // OR $tmp,$src.hi | |
| 3147 emit_opcode(cbuf, 0x0B); | |
| 3148 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 3149 %} | |
| 3150 | |
| 3151 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 3152 // CMP $src1.lo,$src2.lo | |
| 3153 emit_opcode( cbuf, 0x3B ); | |
| 3154 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3155 // JNE,s skip | |
| 3156 emit_cc(cbuf, 0x70, 0x5); | |
| 3157 emit_d8(cbuf,2); | |
| 3158 // CMP $src1.hi,$src2.hi | |
| 3159 emit_opcode( cbuf, 0x3B ); | |
| 3160 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 3161 %} | |
| 3162 | |
| 3163 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 3164 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits | |
| 3165 emit_opcode( cbuf, 0x3B ); | |
| 3166 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3167 // MOV $tmp,$src1.hi | |
| 3168 emit_opcode( cbuf, 0x8B ); | |
| 3169 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 3170 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 3171 emit_opcode( cbuf, 0x1B ); | |
| 3172 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 3173 %} | |
| 3174 | |
| 3175 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ | |
| 3176 // XOR $tmp,$tmp | |
| 3177 emit_opcode(cbuf,0x33); // XOR | |
| 3178 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 3179 // CMP $tmp,$src.lo | |
| 3180 emit_opcode( cbuf, 0x3B ); | |
| 3181 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 3182 // SBB $tmp,$src.hi | |
| 3183 emit_opcode( cbuf, 0x1B ); | |
| 3184 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 3185 %} | |
| 3186 | |
| 3187 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 3188 enc_class neg_long( eRegL dst ) %{ | |
| 3189 emit_opcode(cbuf,0xF7); // NEG hi | |
| 3190 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3191 emit_opcode(cbuf,0xF7); // NEG lo | |
| 3192 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 3193 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 3194 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3195 emit_d8 (cbuf,0 ); | |
| 3196 %} | |
| 3197 | |
| 3198 enc_class movq_ld(regXD dst, memory mem) %{ | |
| 3199 MacroAssembler _masm(&cbuf); | |
| 624 | 3200 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3201 %} |
| 3202 | |
| 3203 enc_class movq_st(memory mem, regXD src) %{ | |
| 3204 MacroAssembler _masm(&cbuf); | |
| 624 | 3205 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3206 %} |
| 3207 | |
| 3208 enc_class pshufd_8x8(regX dst, regX src) %{ | |
| 3209 MacroAssembler _masm(&cbuf); | |
| 3210 | |
| 3211 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3212 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3213 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3214 %} | |
| 3215 | |
| 3216 enc_class pshufd_4x16(regX dst, regX src) %{ | |
| 3217 MacroAssembler _masm(&cbuf); | |
| 3218 | |
| 3219 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3220 %} | |
| 3221 | |
| 3222 enc_class pshufd(regXD dst, regXD src, int mode) %{ | |
| 3223 MacroAssembler _masm(&cbuf); | |
| 3224 | |
| 3225 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3226 %} | |
| 3227 | |
| 3228 enc_class pxor(regXD dst, regXD src) %{ | |
| 3229 MacroAssembler _masm(&cbuf); | |
| 3230 | |
| 3231 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3232 %} | |
| 3233 | |
| 3234 enc_class mov_i2x(regXD dst, eRegI src) %{ | |
| 3235 MacroAssembler _masm(&cbuf); | |
| 3236 | |
| 304 | 3237 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); |
| 0 | 3238 %} |
| 3239 | |
| 3240 | |
| 3241 // Because the transitions from emitted code to the runtime | |
| 3242 // monitorenter/exit helper stubs are so slow it's critical that | |
| 3243 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 3244 // | |
| 3245 // See also: cmpFastLock and cmpFastUnlock. | |
| 3246 // | |
| 3247 // What follows is a specialized inline transliteration of the code | |
| 3248 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 3249 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 3250 // at startup-time. These methods would accept arguments as | |
| 3251 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 3252 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 3253 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 3254 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 3255 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 3256 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 3257 // Since the helper routines would be called from multiple synchronization | |
| 3258 // sites. | |
| 3259 // | |
| 3260 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 3261 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 3262 // to those specialized methods. That'd give us a mostly platform-independent | |
| 3263 // implementation that the JITs could optimize and inline at their pleasure. | |
| 3264 // Done correctly, the only time we'd need to cross to native could would be | |
| 3265 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 3266 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 3267 // (b) explicit barriers or fence operations. | |
| 3268 // | |
| 3269 // TODO: | |
| 3270 // | |
| 3271 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 3272 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 3273 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 3274 // the lock operators would typically be faster than reifying Self. | |
| 3275 // | |
| 3276 // * Ideally I'd define the primitives as: | |
| 3277 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 3278 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 3279 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 3280 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 3281 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 3282 // sub-optimal code near the synchronization site. | |
| 3283 // | |
| 3284 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 3285 // Alternately, use a better sp-proximity test. | |
| 3286 // | |
| 3287 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 3288 // Either one is sufficient to uniquely identify a thread. | |
| 3289 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 3290 // | |
| 3291 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 3292 // object is locked by the calling thread but the waitlist is empty. | |
| 3293 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 3294 // | |
| 3295 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 3296 // But beware of excessive branch density on AMD Opterons. | |
| 3297 // | |
| 3298 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 3299 // or failure of the fast-path. If the fast-path fails then we pass | |
| 3300 // control to the slow-path, typically in C. In Fast_Lock and | |
| 3301 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 3302 // will emit a conditional branch immediately after the node. | |
| 3303 // So we have branches to branches and lots of ICC.ZF games. | |
| 3304 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3305 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3306 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3307 // In the case of failure, the node will branch directly to the | |
| 3308 // FailureLabel | |
| 3309 | |
| 3310 | |
| 3311 // obj: object to lock | |
| 3312 // box: on-stack box address (displaced header location) - KILLED | |
| 3313 // rax,: tmp -- KILLED | |
| 3314 // scr: tmp -- KILLED | |
| 3315 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3316 | |
| 3317 Register objReg = as_Register($obj$$reg); | |
| 3318 Register boxReg = as_Register($box$$reg); | |
| 3319 Register tmpReg = as_Register($tmp$$reg); | |
| 3320 Register scrReg = as_Register($scr$$reg); | |
| 3321 | |
| 3322 // Ensure the register assignents are disjoint | |
| 3323 guarantee (objReg != boxReg, "") ; | |
| 3324 guarantee (objReg != tmpReg, "") ; | |
| 3325 guarantee (objReg != scrReg, "") ; | |
| 3326 guarantee (boxReg != tmpReg, "") ; | |
| 3327 guarantee (boxReg != scrReg, "") ; | |
| 3328 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3329 | |
| 3330 MacroAssembler masm(&cbuf); | |
| 3331 | |
| 3332 if (_counters != NULL) { | |
| 3333 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3334 } | |
| 3335 if (EmitSync & 1) { | |
| 3336 // set box->dhw = unused_mark (3) | |
| 304 | 3337 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3338 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3339 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3340 } else | |
| 3341 if (EmitSync & 2) { | |
| 3342 Label DONE_LABEL ; | |
| 0 | 3343 if (UseBiasedLocking) { |
| 3344 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3345 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3346 } | |
| 3347 | |
| 304 | 3348 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3349 masm.orptr (tmpReg, 0x1); | |
| 3350 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3351 if (os::is_MP()) { masm.lock(); } |
| 304 | 3352 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3353 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3354 // Recursive locking | |
| 304 | 3355 masm.subptr(tmpReg, rsp); |
| 3356 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3357 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3358 masm.bind(DONE_LABEL) ; | |
| 3359 } else { | |
| 3360 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3361 // ------------------------------------------------ |
| 3362 // * Inflated | |
| 3363 // -- unlocked | |
| 3364 // -- Locked | |
| 3365 // = by self | |
| 3366 // = by other | |
| 3367 // * biased | |
| 3368 // -- by Self | |
| 3369 // -- by other | |
| 3370 // * neutral | |
| 3371 // * stack-locked | |
| 3372 // -- by self | |
| 3373 // = sp-proximity test hits | |
| 3374 // = sp-proximity test generates false-negative | |
| 3375 // -- by other | |
| 3376 // | |
| 3377 | |
| 3378 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3379 | |
| 3380 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3381 // order to reduce the number of conditional branches in the most common cases. | |
| 3382 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3383 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3384 // If this invariant is not held we risk exclusion (safety) failure. | |
|
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415
diff
changeset
|
3385 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3386 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3387 } | |
| 3388 | |
| 304 | 3389 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3390 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3391 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3392 | |
| 3393 // Attempt stack-locking ... | |
| 304 | 3394 masm.orptr (tmpReg, 0x1); |
| 3395 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3396 if (os::is_MP()) { masm.lock(); } |
| 304 | 3397 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3398 if (_counters != NULL) { |
| 3399 masm.cond_inc32(Assembler::equal, | |
| 3400 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3401 } | |
| 3402 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3403 | |
| 3404 // Recursive locking | |
| 304 | 3405 masm.subptr(tmpReg, rsp); |
| 3406 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3407 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3408 if (_counters != NULL) { |
| 3409 masm.cond_inc32(Assembler::equal, | |
| 3410 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3411 } | |
| 3412 masm.jmp (DONE_LABEL) ; | |
| 3413 | |
| 3414 masm.bind (IsInflated) ; | |
| 3415 | |
| 3416 // The object is inflated. | |
| 3417 // | |
| 3418 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3419 // Use markOopDesc::monitor_value instead of "2". | |
| 3420 // use markOop::unused_mark() instead of "3". | |
| 3421 // The tmpReg value is an objectMonitor reference ORed with | |
| 3422 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3423 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3424 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3425 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3426 // | |
| 3427 // I use the latter as it avoids AGI stalls. | |
| 3428 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3429 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3430 // | |
| 3431 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3432 | |
| 3433 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3434 // We'd like to write: | |
| 3435 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3436 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3437 // additional latency as we have another ST in the store buffer that must drain. | |
| 3438 | |
| 304 | 3439 if (EmitSync & 8192) { |
| 3440 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3441 masm.get_thread (scrReg) ; | |
| 3442 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
512
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420
diff
changeset
|
3443 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3444 if (os::is_MP()) { masm.lock(); } |
| 3445 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3446 } else | |
| 0 | 3447 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3448 masm.movptr(scrReg, boxReg) ; |
| 3449 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3450 |
| 3451 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3452 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3453 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3454 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3455 } |
| 3456 | |
| 3457 if ((EmitSync & 64) == 0) { | |
| 3458 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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420
diff
changeset
|
3459 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3460 } else { |
| 0 | 3461 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3462 // Test-And-CAS instead of CAS | |
| 304 | 3463 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3464 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3465 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3466 } |
| 3467 | |
| 3468 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3469 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3470 // to CAS the register containing Self into m->Owner. | |
| 3471 // But we don't have enough registers, so instead we can either try to CAS | |
| 3472 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3473 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3474 // (rsp or the address of the box) into m->owner is harmless. | |
| 3475 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3476 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3477 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3478 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3479 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3480 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3481 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3482 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3483 | |
| 3484 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3485 // We use the latter tactic. | |
| 0 | 3486 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3487 // If the CAS was successful ... | |
| 3488 // Self has acquired the lock | |
| 3489 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3490 // Intentional fall-through into DONE_LABEL ... | |
| 3491 } else { | |
| 304 | 3492 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3493 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3494 |
| 3495 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3496 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3497 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3498 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3499 } |
| 3500 | |
| 3501 if ((EmitSync & 64) == 0) { | |
| 3502 // Optimistic form | |
| 304 | 3503 masm.xorptr (tmpReg, tmpReg) ; |
| 3504 } else { | |
| 0 | 3505 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3506 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3507 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3508 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3509 } |
| 3510 | |
| 3511 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3512 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3513 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3514 masm.get_thread (scrReg) ; | |
| 3515 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3516 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3517 |
| 3518 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3519 // We use the latter tactic. | |
| 3520 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3521 // If the CAS was successful ... | |
| 3522 // Self has acquired the lock | |
| 3523 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3524 // Intentional fall-through into DONE_LABEL ... | |
| 3525 } | |
| 3526 | |
| 3527 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3528 // start of cache line by padding with NOPs. | |
| 3529 // See the AMD and Intel software optimization manuals for the | |
| 3530 // most efficient "long" NOP encodings. | |
| 3531 // Unfortunately none of our alignment mechanisms suffice. | |
| 3532 masm.bind(DONE_LABEL); | |
| 3533 | |
| 3534 // Avoid branch-to-branch on AMD processors | |
| 3535 // This appears to be superstition. | |
| 3536 if (EmitSync & 32) masm.nop() ; | |
| 3537 | |
| 3538 | |
| 3539 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3540 // Fast_Unlock uses the same protocol. | |
| 3541 // ZFlag == 1 -> Success | |
| 3542 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3543 } | |
| 3544 %} | |
| 3545 | |
| 3546 // obj: object to unlock | |
| 3547 // box: box address (displaced header location), killed. Must be EAX. | |
| 3548 // rbx,: killed tmp; cannot be obj nor box. | |
| 3549 // | |
| 3550 // Some commentary on balanced locking: | |
| 3551 // | |
| 3552 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3553 // Methods that don't have provably balanced locking are forced to run in the | |
| 3554 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3555 // The interpreter provides two properties: | |
| 3556 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3557 // objects acquired the current activation (frame). Recall that the | |
| 3558 // interpreter maintains an on-stack list of locks currently held by | |
| 3559 // a frame. | |
| 3560 // I2: If a method attempts to unlock an object that is not held by the | |
| 3561 // the frame the interpreter throws IMSX. | |
| 3562 // | |
| 3563 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3564 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3565 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3566 // is still locked by A(). | |
| 3567 // | |
| 3568 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3569 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3570 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3571 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3572 | |
| 3573 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3574 | |
| 3575 Register objReg = as_Register($obj$$reg); | |
| 3576 Register boxReg = as_Register($box$$reg); | |
| 3577 Register tmpReg = as_Register($tmp$$reg); | |
| 3578 | |
| 3579 guarantee (objReg != boxReg, "") ; | |
| 3580 guarantee (objReg != tmpReg, "") ; | |
| 3581 guarantee (boxReg != tmpReg, "") ; | |
| 3582 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3583 MacroAssembler masm(&cbuf); | |
| 3584 | |
| 3585 if (EmitSync & 4) { | |
| 3586 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3587 masm.cmpptr (rsp, 0) ; |
| 3588 } else | |
| 0 | 3589 if (EmitSync & 8) { |
| 3590 Label DONE_LABEL ; | |
| 3591 if (UseBiasedLocking) { | |
| 3592 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3593 } | |
| 3594 // classic stack-locking code ... | |
| 304 | 3595 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3596 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3597 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3598 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3599 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3600 masm.bind(DONE_LABEL); |
| 3601 } else { | |
| 3602 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3603 | |
| 3604 // Critically, the biased locking test must have precedence over | |
| 3605 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3606 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3607 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3608 } | |
| 304 | 3609 |
| 3610 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3611 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3612 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3613 | |
| 304 | 3614 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3615 masm.jccb (Assembler::zero, Stacked) ; |
| 3616 | |
| 3617 masm.bind (Inflated) ; | |
| 3618 // It's inflated. | |
| 3619 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3620 // as java routines or native JNI code called by this thread might | |
| 3621 // have released the lock. | |
| 3622 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3623 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3624 // | |
| 3625 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3626 // such as recursive enter and exit -- but we have to be wary of | |
| 3627 // I$ bloat, T$ effects and BP$ effects. | |
| 3628 // | |
| 3629 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3630 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3631 // we detect and recover from the race that the 1-0 exit admits. | |
| 3632 // | |
| 3633 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3634 // before it STs null into _owner, releasing the lock. Updates | |
| 3635 // to data protected by the critical section must be visible before | |
| 3636 // we drop the lock (and thus before any other thread could acquire | |
| 3637 // the lock and observe the fields protected by the lock). | |
| 3638 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3639 // each other and there's no need for an explicit barrier (fence). | |
| 3640 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3641 | |
| 3642 masm.get_thread (boxReg) ; | |
| 3643 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 304 | 3644 // prefetchw [ebx + Offset(_owner)-2] |
| 3645 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3646 } |
| 3647 | |
| 3648 // Note that we could employ various encoding schemes to reduce | |
| 3649 // the number of loads below (currently 4) to just 2 or 3. | |
| 3650 // Refer to the comments in synchronizer.cpp. | |
| 3651 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3652 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3653 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3654 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3655 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3656 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3657 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3658 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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|
3659 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3660 masm.jmpb (DONE_LABEL) ; |
| 3661 } else { | |
| 3662 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3663 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3664 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3665 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3666 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3667 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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|
3668 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3669 masm.jmpb (DONE_LABEL) ; |
| 0 | 3670 } |
| 3671 | |
| 3672 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3673 // contended applications and contended synchronization microbenchmarks. | |
| 3674 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3675 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3676 // with an equal number of never-executed NOPs results in the same regression. | |
| 3677 // We leave it off by default. | |
| 3678 | |
| 3679 if ((EmitSync & 65536) != 0) { | |
| 3680 Label LSuccess, LGoSlowPath ; | |
| 3681 | |
| 3682 masm.bind (CheckSucc) ; | |
| 3683 | |
| 3684 // Optional pre-test ... it's safe to elide this | |
| 304 | 3685 if ((EmitSync & 16) == 0) { |
| 3686 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3687 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3688 } |
| 3689 | |
| 3690 // We have a classic Dekker-style idiom: | |
| 3691 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3692 // There are a number of ways to implement the barrier: | |
| 3693 // (1) lock:andl &m->_owner, 0 | |
| 3694 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3695 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3696 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3697 // (2) If supported, an explicit MFENCE is appealing. | |
| 3698 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3699 // particularly if the write-buffer is full as might be the case if | |
| 3700 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3701 // In more modern implementations MFENCE appears faster, however. | |
| 3702 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3703 // The $lines underlying the top-of-stack should be in M-state. | |
| 3704 // The locked add instruction is serializing, of course. | |
| 3705 // (4) Use xchg, which is serializing | |
| 3706 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3707 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3708 // The integer condition codes will tell us if succ was 0. | |
| 3709 // Since _succ and _owner should reside in the same $line and | |
| 3710 // we just stored into _owner, it's likely that the $line | |
| 3711 // remains in M-state for the lock:orl. | |
| 3712 // | |
| 3713 // We currently use (3), although it's likely that switching to (2) | |
| 3714 // is correct for the future. | |
| 304 | 3715 |
|
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|
3716 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3717 if (os::is_MP()) { |
| 3718 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3719 masm.mfence(); | |
| 3720 } else { | |
| 3721 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3722 } |
| 3723 } | |
| 3724 // Ratify _succ remains non-null | |
| 304 | 3725 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3726 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3727 | |
| 3728 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3729 if (os::is_MP()) { masm.lock(); } |
| 304 | 3730 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3731 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3732 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3733 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3734 // non-null to non=null | |
| 3735 masm.get_thread (boxReg) ; | |
| 304 | 3736 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3737 // Intentional fall-through into LGoSlowPath ... |
| 3738 | |
| 304 | 3739 masm.bind (LGoSlowPath) ; |
| 3740 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3741 masm.jmpb (DONE_LABEL) ; | |
| 3742 | |
| 3743 masm.bind (LSuccess) ; | |
| 3744 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3745 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3746 } |
| 3747 | |
| 3748 masm.bind (Stacked) ; | |
| 3749 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3750 // It must be stack-locked. | |
| 3751 // Try to reset the header to displaced header. | |
| 3752 // The "box" value on the stack is stable, so we can reload | |
| 3753 // and be assured we observe the same value as above. | |
| 304 | 3754 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3755 if (os::is_MP()) { masm.lock(); } |
| 304 | 3756 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3757 // Intention fall-thru into DONE_LABEL |
| 3758 | |
| 3759 | |
| 3760 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3761 // start of cache line by padding with NOPs. | |
| 3762 // See the AMD and Intel software optimization manuals for the | |
| 3763 // most efficient "long" NOP encodings. | |
| 3764 // Unfortunately none of our alignment mechanisms suffice. | |
| 3765 if ((EmitSync & 65536) == 0) { | |
| 3766 masm.bind (CheckSucc) ; | |
| 3767 } | |
| 3768 masm.bind(DONE_LABEL); | |
| 3769 | |
| 3770 // Avoid branch to branch on AMD processors | |
| 3771 if (EmitSync & 32768) { masm.nop() ; } | |
| 3772 } | |
| 3773 %} | |
| 3774 | |
|
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|
3775 |
| 0 | 3776 enc_class enc_pop_rdx() %{ |
| 3777 emit_opcode(cbuf,0x5A); | |
| 3778 %} | |
| 3779 | |
| 3780 enc_class enc_rethrow() %{ | |
| 3781 cbuf.set_inst_mark(); | |
| 3782 emit_opcode(cbuf, 0xE9); // jmp entry | |
| 3783 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4, | |
| 3784 runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3785 %} | |
| 3786 | |
| 3787 | |
| 3788 // Convert a double to an int. Java semantics require we do complex | |
| 3789 // manglelations in the corner cases. So we set the rounding mode to | |
| 3790 // 'zero', store the darned double down as an int, and reset the | |
| 3791 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3792 // patches up the correct value directly to the stack. | |
| 3793 enc_class D2I_encoding( regD src ) %{ | |
| 3794 // Flip to round-to-zero mode. We attempted to allow invalid-op | |
| 3795 // exceptions here, so that a NAN or other corner-case value will | |
| 3796 // thrown an exception (but normal values get converted at full speed). | |
| 3797 // However, I2C adapters and other float-stack manglers leave pending | |
| 3798 // invalid-op exceptions hanging. We would have to clear them before | |
| 3799 // enabling them and that is more expensive than just testing for the | |
| 3800 // invalid value Intel stores down in the corner cases. | |
| 3801 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3802 emit_opcode(cbuf,0x2D); | |
| 3803 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3804 // Allocate a word | |
| 3805 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3806 emit_opcode(cbuf,0xEC); | |
| 3807 emit_d8(cbuf,0x04); | |
| 3808 // Encoding assumes a double has been pushed into FPR0. | |
| 3809 // Store down the double as an int, popping the FPU stack | |
| 3810 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3811 emit_opcode(cbuf,0x1C); | |
| 3812 emit_d8(cbuf,0x24); | |
| 3813 // Restore the rounding mode; mask the exception | |
| 3814 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3815 emit_opcode(cbuf,0x2D); | |
| 3816 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3817 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3818 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3819 | |
| 3820 // Load the converted int; adjust CPU stack | |
| 3821 emit_opcode(cbuf,0x58); // POP EAX | |
| 3822 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3823 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3824 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3825 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3826 // Push src onto stack slow-path | |
| 3827 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3828 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3829 // CALL directly to the runtime | |
| 3830 cbuf.set_inst_mark(); | |
| 3831 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3832 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3833 // Carry on here... | |
| 3834 %} | |
| 3835 | |
| 3836 enc_class D2L_encoding( regD src ) %{ | |
| 3837 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3838 emit_opcode(cbuf,0x2D); | |
| 3839 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3840 // Allocate a word | |
| 3841 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3842 emit_opcode(cbuf,0xEC); | |
| 3843 emit_d8(cbuf,0x08); | |
| 3844 // Encoding assumes a double has been pushed into FPR0. | |
| 3845 // Store down the double as a long, popping the FPU stack | |
| 3846 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3847 emit_opcode(cbuf,0x3C); | |
| 3848 emit_d8(cbuf,0x24); | |
| 3849 // Restore the rounding mode; mask the exception | |
| 3850 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3851 emit_opcode(cbuf,0x2D); | |
| 3852 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3853 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3854 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3855 | |
| 3856 // Load the converted int; adjust CPU stack | |
| 3857 emit_opcode(cbuf,0x58); // POP EAX | |
| 3858 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3859 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3860 emit_d8 (cbuf,0xFA); // rdx | |
| 3861 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3862 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3863 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3864 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3865 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3866 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3867 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3868 // Push src onto stack slow-path | |
| 3869 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3870 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3871 // CALL directly to the runtime | |
| 3872 cbuf.set_inst_mark(); | |
| 3873 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3874 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3875 // Carry on here... | |
| 3876 %} | |
| 3877 | |
| 3878 enc_class X2L_encoding( regX src ) %{ | |
| 3879 // Allocate a word | |
| 3880 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3881 emit_opcode(cbuf,0xEC); | |
| 3882 emit_d8(cbuf,0x08); | |
| 3883 | |
| 3884 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3885 emit_opcode (cbuf, 0x0F ); | |
| 3886 emit_opcode (cbuf, 0x11 ); | |
| 3887 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3888 | |
| 3889 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3890 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3891 | |
| 3892 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3893 emit_opcode(cbuf,0x2D); | |
| 3894 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3895 | |
| 3896 // Encoding assumes a double has been pushed into FPR0. | |
| 3897 // Store down the double as a long, popping the FPU stack | |
| 3898 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3899 emit_opcode(cbuf,0x3C); | |
| 3900 emit_d8(cbuf,0x24); | |
| 3901 | |
| 3902 // Restore the rounding mode; mask the exception | |
| 3903 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3904 emit_opcode(cbuf,0x2D); | |
| 3905 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3906 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3907 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3908 | |
| 3909 // Load the converted int; adjust CPU stack | |
| 3910 emit_opcode(cbuf,0x58); // POP EAX | |
| 3911 | |
| 3912 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3913 | |
| 3914 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3915 emit_d8 (cbuf,0xFA); // rdx | |
| 3916 emit_d32 (cbuf,0x80000000);// 0x80000000 | |
| 3917 | |
| 3918 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3919 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3920 | |
| 3921 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3922 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3923 | |
| 3924 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3925 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3926 | |
| 3927 // Allocate a word | |
| 3928 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3929 emit_opcode(cbuf,0xEC); | |
| 3930 emit_d8(cbuf,0x04); | |
| 3931 | |
| 3932 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3933 emit_opcode (cbuf, 0x0F ); | |
| 3934 emit_opcode (cbuf, 0x11 ); | |
| 3935 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3936 | |
| 3937 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3938 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3939 | |
| 3940 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 3941 emit_opcode(cbuf,0xC4); | |
| 3942 emit_d8(cbuf,0x04); | |
| 3943 | |
| 3944 // CALL directly to the runtime | |
| 3945 cbuf.set_inst_mark(); | |
| 3946 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 3947 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 3948 // Carry on here... | |
| 3949 %} | |
| 3950 | |
| 3951 enc_class XD2L_encoding( regXD src ) %{ | |
| 3952 // Allocate a word | |
| 3953 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3954 emit_opcode(cbuf,0xEC); | |
| 3955 emit_d8(cbuf,0x08); | |
| 3956 | |
| 3957 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 3958 emit_opcode (cbuf, 0x0F ); | |
| 3959 emit_opcode (cbuf, 0x11 ); | |
| 3960 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3961 | |
| 3962 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 3963 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3964 | |
| 3965 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3966 emit_opcode(cbuf,0x2D); | |
| 3967 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3968 | |
| 3969 // Encoding assumes a double has been pushed into FPR0. | |
| 3970 // Store down the double as a long, popping the FPU stack | |
| 3971 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3972 emit_opcode(cbuf,0x3C); | |
| 3973 emit_d8(cbuf,0x24); | |
| 3974 | |
| 3975 // Restore the rounding mode; mask the exception | |
| 3976 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3977 emit_opcode(cbuf,0x2D); | |
| 3978 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3979 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3980 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3981 | |
| 3982 // Load the converted int; adjust CPU stack | |
| 3983 emit_opcode(cbuf,0x58); // POP EAX | |
| 3984 | |
| 3985 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3986 | |
| 3987 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3988 emit_d8 (cbuf,0xFA); // rdx | |
| 3989 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3990 | |
| 3991 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3992 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3993 | |
| 3994 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3995 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3996 | |
| 3997 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3998 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3999 | |
| 4000 // Push src onto stack slow-path | |
| 4001 // Allocate a word | |
| 4002 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 4003 emit_opcode(cbuf,0xEC); | |
| 4004 emit_d8(cbuf,0x08); | |
| 4005 | |
| 4006 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 4007 emit_opcode (cbuf, 0x0F ); | |
| 4008 emit_opcode (cbuf, 0x11 ); | |
| 4009 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4010 | |
| 4011 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 4012 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4013 | |
| 4014 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 4015 emit_opcode(cbuf,0xC4); | |
| 4016 emit_d8(cbuf,0x08); | |
| 4017 | |
| 4018 // CALL directly to the runtime | |
| 4019 cbuf.set_inst_mark(); | |
| 4020 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 4021 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 4022 // Carry on here... | |
| 4023 %} | |
| 4024 | |
| 4025 enc_class D2X_encoding( regX dst, regD src ) %{ | |
| 4026 // Allocate a word | |
| 4027 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4028 emit_opcode(cbuf,0xEC); | |
| 4029 emit_d8(cbuf,0x04); | |
| 4030 int pop = 0x02; | |
| 4031 if ($src$$reg != FPR1L_enc) { | |
| 4032 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 4033 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 4034 pop = 0x03; | |
| 4035 } | |
| 4036 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] | |
| 4037 | |
| 4038 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 4039 emit_opcode (cbuf, 0x0F ); | |
| 4040 emit_opcode (cbuf, 0x10 ); | |
| 4041 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4042 | |
| 4043 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4044 emit_opcode(cbuf,0xC4); | |
| 4045 emit_d8(cbuf,0x04); | |
| 4046 // Carry on here... | |
| 4047 %} | |
| 4048 | |
| 4049 enc_class FX2I_encoding( regX src, eRegI dst ) %{ | |
| 4050 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 4051 | |
| 4052 // Compare the result to see if we need to go to the slow path | |
| 4053 emit_opcode(cbuf,0x81); // CMP dst,imm | |
| 4054 emit_rm (cbuf,0x3,0x7,$dst$$reg); | |
| 4055 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 4056 | |
| 4057 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4058 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4059 // Store xmm to a temp memory | |
| 4060 // location and push it onto stack. | |
| 4061 | |
| 4062 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4063 emit_opcode(cbuf,0xEC); | |
| 4064 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4065 | |
| 4066 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm | |
| 4067 emit_opcode (cbuf, 0x0F ); | |
| 4068 emit_opcode (cbuf, 0x11 ); | |
| 4069 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4070 | |
| 4071 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] | |
| 4072 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4073 | |
| 4074 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4075 emit_opcode(cbuf,0xC4); | |
| 4076 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4077 | |
| 4078 // CALL directly to the runtime | |
| 4079 cbuf.set_inst_mark(); | |
| 4080 emit_opcode(cbuf,0xE8); // Call into runtime | |
| 4081 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); | |
| 4082 | |
| 4083 // Carry on here... | |
| 4084 %} | |
| 4085 | |
| 4086 enc_class X2D_encoding( regD dst, regX src ) %{ | |
| 4087 // Allocate a word | |
| 4088 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4089 emit_opcode(cbuf,0xEC); | |
| 4090 emit_d8(cbuf,0x04); | |
| 4091 | |
| 4092 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm | |
| 4093 emit_opcode (cbuf, 0x0F ); | |
| 4094 emit_opcode (cbuf, 0x11 ); | |
| 4095 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4096 | |
| 4097 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 4098 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4099 | |
| 4100 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4101 emit_opcode(cbuf,0xC4); | |
| 4102 emit_d8(cbuf,0x04); | |
| 4103 | |
| 4104 // Carry on here... | |
| 4105 %} | |
| 4106 | |
| 4107 enc_class AbsXF_encoding(regX dst) %{ | |
| 4108 address signmask_address=(address)float_signmask_pool; | |
| 4109 // andpd:\tANDPS $dst,[signconst] | |
| 4110 emit_opcode(cbuf, 0x0F); | |
| 4111 emit_opcode(cbuf, 0x54); | |
| 4112 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4113 emit_d32(cbuf, (int)signmask_address); | |
| 4114 %} | |
| 4115 | |
| 4116 enc_class AbsXD_encoding(regXD dst) %{ | |
| 4117 address signmask_address=(address)double_signmask_pool; | |
| 4118 // andpd:\tANDPD $dst,[signconst] | |
| 4119 emit_opcode(cbuf, 0x66); | |
| 4120 emit_opcode(cbuf, 0x0F); | |
| 4121 emit_opcode(cbuf, 0x54); | |
| 4122 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4123 emit_d32(cbuf, (int)signmask_address); | |
| 4124 %} | |
| 4125 | |
| 4126 enc_class NegXF_encoding(regX dst) %{ | |
| 4127 address signmask_address=(address)float_signflip_pool; | |
| 4128 // andpd:\tXORPS $dst,[signconst] | |
| 4129 emit_opcode(cbuf, 0x0F); | |
| 4130 emit_opcode(cbuf, 0x57); | |
| 4131 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4132 emit_d32(cbuf, (int)signmask_address); | |
| 4133 %} | |
| 4134 | |
| 4135 enc_class NegXD_encoding(regXD dst) %{ | |
| 4136 address signmask_address=(address)double_signflip_pool; | |
| 4137 // andpd:\tXORPD $dst,[signconst] | |
| 4138 emit_opcode(cbuf, 0x66); | |
| 4139 emit_opcode(cbuf, 0x0F); | |
| 4140 emit_opcode(cbuf, 0x57); | |
| 4141 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4142 emit_d32(cbuf, (int)signmask_address); | |
| 4143 %} | |
| 4144 | |
| 4145 enc_class FMul_ST_reg( eRegF src1 ) %{ | |
| 4146 // Operand was loaded from memory into fp ST (stack top) | |
| 4147 // FMUL ST,$src /* D8 C8+i */ | |
| 4148 emit_opcode(cbuf, 0xD8); | |
| 4149 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 4150 %} | |
| 4151 | |
| 4152 enc_class FAdd_ST_reg( eRegF src2 ) %{ | |
| 4153 // FADDP ST,src2 /* D8 C0+i */ | |
| 4154 emit_opcode(cbuf, 0xD8); | |
| 4155 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4156 //could use FADDP src2,fpST /* DE C0+i */ | |
| 4157 %} | |
| 4158 | |
| 4159 enc_class FAddP_reg_ST( eRegF src2 ) %{ | |
| 4160 // FADDP src2,ST /* DE C0+i */ | |
| 4161 emit_opcode(cbuf, 0xDE); | |
| 4162 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4163 %} | |
| 4164 | |
| 4165 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ | |
| 4166 // Operand has been loaded into fp ST (stack top) | |
| 4167 // FSUB ST,$src1 | |
| 4168 emit_opcode(cbuf, 0xD8); | |
| 4169 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 4170 | |
| 4171 // FDIV | |
| 4172 emit_opcode(cbuf, 0xD8); | |
| 4173 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 4174 %} | |
| 4175 | |
| 4176 enc_class MulFAddF (eRegF src1, eRegF src2) %{ | |
| 4177 // Operand was loaded from memory into fp ST (stack top) | |
| 4178 // FADD ST,$src /* D8 C0+i */ | |
| 4179 emit_opcode(cbuf, 0xD8); | |
| 4180 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4181 | |
| 4182 // FMUL ST,src2 /* D8 C*+i */ | |
| 4183 emit_opcode(cbuf, 0xD8); | |
| 4184 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4185 %} | |
| 4186 | |
| 4187 | |
| 4188 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ | |
| 4189 // Operand was loaded from memory into fp ST (stack top) | |
| 4190 // FADD ST,$src /* D8 C0+i */ | |
| 4191 emit_opcode(cbuf, 0xD8); | |
| 4192 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4193 | |
| 4194 // FMULP src2,ST /* DE C8+i */ | |
| 4195 emit_opcode(cbuf, 0xDE); | |
| 4196 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4197 %} | |
| 4198 | |
| 4199 // Atomically load the volatile long | |
| 4200 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 4201 emit_opcode(cbuf,0xDF); | |
| 4202 int rm_byte_opcode = 0x05; | |
| 4203 int base = $mem$$base; | |
| 4204 int index = $mem$$index; | |
| 4205 int scale = $mem$$scale; | |
| 4206 int displace = $mem$$disp; | |
| 4207 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4208 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4209 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); | |
| 4210 %} | |
| 4211 | |
| 4212 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ | |
| 4213 { // Atomic long load | |
| 4214 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4215 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4216 emit_opcode(cbuf,0x0F); | |
| 4217 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4218 int base = $mem$$base; | |
| 4219 int index = $mem$$index; | |
| 4220 int scale = $mem$$scale; | |
| 4221 int displace = $mem$$disp; | |
| 4222 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4223 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4224 } | |
| 4225 { // MOVSD $dst,$tmp ! atomic long store | |
| 4226 emit_opcode(cbuf,0xF2); | |
| 4227 emit_opcode(cbuf,0x0F); | |
| 4228 emit_opcode(cbuf,0x11); | |
| 4229 int base = $dst$$base; | |
| 4230 int index = $dst$$index; | |
| 4231 int scale = $dst$$scale; | |
| 4232 int displace = $dst$$disp; | |
| 4233 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4234 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4235 } | |
| 4236 %} | |
| 4237 | |
| 4238 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ | |
| 4239 { // Atomic long load | |
| 4240 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4241 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4242 emit_opcode(cbuf,0x0F); | |
| 4243 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4244 int base = $mem$$base; | |
| 4245 int index = $mem$$index; | |
| 4246 int scale = $mem$$scale; | |
| 4247 int displace = $mem$$disp; | |
| 4248 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4249 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4250 } | |
| 4251 { // MOVD $dst.lo,$tmp | |
| 4252 emit_opcode(cbuf,0x66); | |
| 4253 emit_opcode(cbuf,0x0F); | |
| 4254 emit_opcode(cbuf,0x7E); | |
| 4255 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); | |
| 4256 } | |
| 4257 { // PSRLQ $tmp,32 | |
| 4258 emit_opcode(cbuf,0x66); | |
| 4259 emit_opcode(cbuf,0x0F); | |
| 4260 emit_opcode(cbuf,0x73); | |
| 4261 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); | |
| 4262 emit_d8(cbuf, 0x20); | |
| 4263 } | |
| 4264 { // MOVD $dst.hi,$tmp | |
| 4265 emit_opcode(cbuf,0x66); | |
| 4266 emit_opcode(cbuf,0x0F); | |
| 4267 emit_opcode(cbuf,0x7E); | |
| 4268 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 4269 } | |
| 4270 %} | |
| 4271 | |
| 4272 // Volatile Store Long. Must be atomic, so move it into | |
| 4273 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 4274 // target address before the store (for null-ptr checks) | |
| 4275 // so the memory operand is used twice in the encoding. | |
| 4276 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 4277 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 4278 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop | |
| 4279 emit_opcode(cbuf,0xDF); | |
| 4280 int rm_byte_opcode = 0x07; | |
| 4281 int base = $mem$$base; | |
| 4282 int index = $mem$$index; | |
| 4283 int scale = $mem$$scale; | |
| 4284 int displace = $mem$$disp; | |
| 4285 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4286 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4287 %} | |
| 4288 | |
| 4289 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ | |
| 4290 { // Atomic long load | |
| 4291 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] | |
| 4292 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4293 emit_opcode(cbuf,0x0F); | |
| 4294 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4295 int base = $src$$base; | |
| 4296 int index = $src$$index; | |
| 4297 int scale = $src$$scale; | |
| 4298 int displace = $src$$disp; | |
| 4299 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4300 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4301 } | |
| 4302 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop | |
| 4303 { // MOVSD $mem,$tmp ! atomic long store | |
| 4304 emit_opcode(cbuf,0xF2); | |
| 4305 emit_opcode(cbuf,0x0F); | |
| 4306 emit_opcode(cbuf,0x11); | |
| 4307 int base = $mem$$base; | |
| 4308 int index = $mem$$index; | |
| 4309 int scale = $mem$$scale; | |
| 4310 int displace = $mem$$disp; | |
| 4311 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4312 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4313 } | |
| 4314 %} | |
| 4315 | |
| 4316 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ | |
| 4317 { // MOVD $tmp,$src.lo | |
| 4318 emit_opcode(cbuf,0x66); | |
| 4319 emit_opcode(cbuf,0x0F); | |
| 4320 emit_opcode(cbuf,0x6E); | |
| 4321 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 4322 } | |
| 4323 { // MOVD $tmp2,$src.hi | |
| 4324 emit_opcode(cbuf,0x66); | |
| 4325 emit_opcode(cbuf,0x0F); | |
| 4326 emit_opcode(cbuf,0x6E); | |
| 4327 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 4328 } | |
| 4329 { // PUNPCKLDQ $tmp,$tmp2 | |
| 4330 emit_opcode(cbuf,0x66); | |
| 4331 emit_opcode(cbuf,0x0F); | |
| 4332 emit_opcode(cbuf,0x62); | |
| 4333 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); | |
| 4334 } | |
| 4335 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop | |
| 4336 { // MOVSD $mem,$tmp ! atomic long store | |
| 4337 emit_opcode(cbuf,0xF2); | |
| 4338 emit_opcode(cbuf,0x0F); | |
| 4339 emit_opcode(cbuf,0x11); | |
| 4340 int base = $mem$$base; | |
| 4341 int index = $mem$$index; | |
| 4342 int scale = $mem$$scale; | |
| 4343 int displace = $mem$$disp; | |
| 4344 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4345 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4346 } | |
| 4347 %} | |
| 4348 | |
| 4349 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4350 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 4351 // in the process | |
| 4352 // We current use TESTL [spp],EDI | |
| 4353 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 4354 | |
| 4355 enc_class Safepoint_Poll() %{ | |
| 4356 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); | |
| 4357 emit_opcode(cbuf,0x85); | |
| 4358 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 4359 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 4360 %} | |
| 4361 %} | |
| 4362 | |
| 4363 | |
| 4364 //----------FRAME-------------------------------------------------------------- | |
| 4365 // Definition of frame structure and management information. | |
| 4366 // | |
| 4367 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4368 // | (to get allocators register number | |
| 4369 // G Owned by | | v add OptoReg::stack0()) | |
| 4370 // r CALLER | | | |
| 4371 // o | +--------+ pad to even-align allocators stack-slot | |
| 4372 // w V | pad0 | numbers; owned by CALLER | |
| 4373 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4374 // h ^ | in | 5 | |
| 4375 // | | args | 4 Holes in incoming args owned by SELF | |
| 4376 // | | | | 3 | |
| 4377 // | | +--------+ | |
| 4378 // V | | old out| Empty on Intel, window on Sparc | |
| 4379 // | old |preserve| Must be even aligned. | |
| 4380 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4381 // | | in | 3 area for Intel ret address | |
| 4382 // Owned by |preserve| Empty on Sparc. | |
| 4383 // SELF +--------+ | |
| 4384 // | | pad2 | 2 pad to align old SP | |
| 4385 // | +--------+ 1 | |
| 4386 // | | locks | 0 | |
| 4387 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4388 // | | pad1 | 11 pad to align new SP | |
| 4389 // | +--------+ | |
| 4390 // | | | 10 | |
| 4391 // | | spills | 9 spills | |
| 4392 // V | | 8 (pad0 slot for callee) | |
| 4393 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4394 // ^ | out | 7 | |
| 4395 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4396 // Owned by +--------+ | |
| 4397 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4398 // | new |preserve| Must be even-aligned. | |
| 4399 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4400 // | | | | |
| 4401 // | |
| 4402 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4403 // known from SELF's arguments and the Java calling convention. | |
| 4404 // Region 6-7 is determined per call site. | |
| 4405 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4406 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4407 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4408 // incoming area, as the Java calling convention is completely under | |
| 4409 // the control of the AD file. Doubles can be sorted and packed to | |
| 4410 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4411 // varargs C calling conventions. | |
| 4412 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4413 // even aligned with pad0 as needed. | |
| 4414 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4415 // region 6-11 is even aligned; it may be padded out more so that | |
| 4416 // the region from SP to FP meets the minimum stack alignment. | |
| 4417 | |
| 4418 frame %{ | |
| 4419 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4420 stack_direction(TOWARDS_LOW); | |
| 4421 | |
| 4422 // These three registers define part of the calling convention | |
| 4423 // between compiled code and the interpreter. | |
| 4424 inline_cache_reg(EAX); // Inline Cache Register | |
| 4425 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 4426 | |
| 4427 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 4428 cisc_spilling_operand_name(indOffset32); | |
| 4429 | |
| 4430 // Number of stack slots consumed by locking an object | |
| 4431 sync_stack_slots(1); | |
| 4432 | |
| 4433 // Compiled code's Frame Pointer | |
| 4434 frame_pointer(ESP); | |
| 4435 // Interpreter stores its frame pointer in a register which is | |
| 4436 // stored to the stack by I2CAdaptors. | |
| 4437 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4438 interpreter_frame_pointer(EBP); | |
| 4439 | |
| 4440 // Stack alignment requirement | |
| 4441 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4442 stack_alignment(StackAlignmentInBytes); | |
| 4443 | |
| 4444 // Number of stack slots between incoming argument block and the start of | |
| 4445 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4446 // EPILOG must remove this many slots. Intel needs one slot for | |
| 4447 // return address and one for rbp, (must save rbp) | |
| 4448 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 4449 | |
| 4450 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4451 // for calls to C. Supports the var-args backing area for register parms. | |
| 4452 varargs_C_out_slots_killed(0); | |
| 4453 | |
| 4454 // The after-PROLOG location of the return address. Location of | |
| 4455 // return address specifies a type (REG or STACK) and a number | |
| 4456 // representing the register number (i.e. - use a register name) or | |
| 4457 // stack slot. | |
| 4458 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4459 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4460 return_addr(STACK - 1 + | |
| 4461 round_to(1+VerifyStackAtCalls+ | |
| 4462 Compile::current()->fixed_slots(), | |
| 4463 (StackAlignmentInBytes/wordSize))); | |
| 4464 | |
| 4465 // Body of function which returns an integer array locating | |
| 4466 // arguments either in registers or in stack slots. Passed an array | |
| 4467 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4468 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4469 // arguments for a CALLEE. Incoming stack arguments are | |
| 4470 // automatically biased by the preserve_stack_slots field above. | |
| 4471 calling_convention %{ | |
| 4472 // No difference between ingoing/outgoing just pass false | |
| 4473 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4474 %} | |
| 4475 | |
| 4476 | |
| 4477 // Body of function which returns an integer array locating | |
| 4478 // arguments either in registers or in stack slots. Passed an array | |
| 4479 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4480 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4481 // arguments for a CALLEE. Incoming stack arguments are | |
| 4482 // automatically biased by the preserve_stack_slots field above. | |
| 4483 c_calling_convention %{ | |
| 4484 // This is obviously always outgoing | |
| 4485 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4486 %} | |
| 4487 | |
| 4488 // Location of C & interpreter return values | |
| 4489 c_return_value %{ | |
| 4490 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4491 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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4492 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4493 |
| 4494 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 4495 // that C functions return float and double results in XMM0. | |
| 4496 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
| 4497 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4498 if( ideal_reg == Op_RegF && UseSSE>=2 ) | |
| 4499 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4500 | |
| 4501 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4502 %} | |
| 4503 | |
| 4504 // Location of return values | |
| 4505 return_value %{ | |
| 4506 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4507 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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4508 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4509 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
| 4510 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4511 if( ideal_reg == Op_RegF && UseSSE>=1 ) | |
| 4512 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4513 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4514 %} | |
| 4515 | |
| 4516 %} | |
| 4517 | |
| 4518 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4519 //----------Operand Attributes------------------------------------------------- | |
| 4520 op_attrib op_cost(0); // Required cost attribute | |
| 4521 | |
| 4522 //----------Instruction Attributes--------------------------------------------- | |
| 4523 ins_attrib ins_cost(100); // Required cost attribute | |
| 4524 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4525 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4526 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 4527 // non-matching short branch variant of some | |
| 4528 // long branch? | |
| 4529 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 4530 // specifies the alignment that some part of the instruction (not | |
| 4531 // necessarily the start) requires. If > 1, a compute_padding() | |
| 4532 // function must be provided for the instruction | |
| 4533 | |
| 4534 //----------OPERANDS----------------------------------------------------------- | |
| 4535 // Operand definitions must precede instruction definitions for correct parsing | |
| 4536 // in the ADLC because operands constitute user defined types which are used in | |
| 4537 // instruction definitions. | |
| 4538 | |
| 4539 //----------Simple Operands---------------------------------------------------- | |
| 4540 // Immediate Operands | |
| 4541 // Integer Immediate | |
| 4542 operand immI() %{ | |
| 4543 match(ConI); | |
| 4544 | |
| 4545 op_cost(10); | |
| 4546 format %{ %} | |
| 4547 interface(CONST_INTER); | |
| 4548 %} | |
| 4549 | |
| 4550 // Constant for test vs zero | |
| 4551 operand immI0() %{ | |
| 4552 predicate(n->get_int() == 0); | |
| 4553 match(ConI); | |
| 4554 | |
| 4555 op_cost(0); | |
| 4556 format %{ %} | |
| 4557 interface(CONST_INTER); | |
| 4558 %} | |
| 4559 | |
| 4560 // Constant for increment | |
| 4561 operand immI1() %{ | |
| 4562 predicate(n->get_int() == 1); | |
| 4563 match(ConI); | |
| 4564 | |
| 4565 op_cost(0); | |
| 4566 format %{ %} | |
| 4567 interface(CONST_INTER); | |
| 4568 %} | |
| 4569 | |
| 4570 // Constant for decrement | |
| 4571 operand immI_M1() %{ | |
| 4572 predicate(n->get_int() == -1); | |
| 4573 match(ConI); | |
| 4574 | |
| 4575 op_cost(0); | |
| 4576 format %{ %} | |
| 4577 interface(CONST_INTER); | |
| 4578 %} | |
| 4579 | |
| 4580 // Valid scale values for addressing modes | |
| 4581 operand immI2() %{ | |
| 4582 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4583 match(ConI); | |
| 4584 | |
| 4585 format %{ %} | |
| 4586 interface(CONST_INTER); | |
| 4587 %} | |
| 4588 | |
| 4589 operand immI8() %{ | |
| 4590 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 4591 match(ConI); | |
| 4592 | |
| 4593 op_cost(5); | |
| 4594 format %{ %} | |
| 4595 interface(CONST_INTER); | |
| 4596 %} | |
| 4597 | |
| 4598 operand immI16() %{ | |
| 4599 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4600 match(ConI); | |
| 4601 | |
| 4602 op_cost(10); | |
| 4603 format %{ %} | |
| 4604 interface(CONST_INTER); | |
| 4605 %} | |
| 4606 | |
| 4607 // Constant for long shifts | |
| 4608 operand immI_32() %{ | |
| 4609 predicate( n->get_int() == 32 ); | |
| 4610 match(ConI); | |
| 4611 | |
| 4612 op_cost(0); | |
| 4613 format %{ %} | |
| 4614 interface(CONST_INTER); | |
| 4615 %} | |
| 4616 | |
| 4617 operand immI_1_31() %{ | |
| 4618 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 4619 match(ConI); | |
| 4620 | |
| 4621 op_cost(0); | |
| 4622 format %{ %} | |
| 4623 interface(CONST_INTER); | |
| 4624 %} | |
| 4625 | |
| 4626 operand immI_32_63() %{ | |
| 4627 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 4628 match(ConI); | |
| 4629 op_cost(0); | |
| 4630 | |
| 4631 format %{ %} | |
| 4632 interface(CONST_INTER); | |
| 4633 %} | |
| 4634 | |
| 219 | 4635 operand immI_1() %{ |
| 4636 predicate( n->get_int() == 1 ); | |
| 4637 match(ConI); | |
| 4638 | |
| 4639 op_cost(0); | |
| 4640 format %{ %} | |
| 4641 interface(CONST_INTER); | |
| 4642 %} | |
| 4643 | |
| 4644 operand immI_2() %{ | |
| 4645 predicate( n->get_int() == 2 ); | |
| 4646 match(ConI); | |
| 4647 | |
| 4648 op_cost(0); | |
| 4649 format %{ %} | |
| 4650 interface(CONST_INTER); | |
| 4651 %} | |
| 4652 | |
| 4653 operand immI_3() %{ | |
| 4654 predicate( n->get_int() == 3 ); | |
| 4655 match(ConI); | |
| 4656 | |
| 4657 op_cost(0); | |
| 4658 format %{ %} | |
| 4659 interface(CONST_INTER); | |
| 4660 %} | |
| 4661 | |
| 0 | 4662 // Pointer Immediate |
| 4663 operand immP() %{ | |
| 4664 match(ConP); | |
| 4665 | |
| 4666 op_cost(10); | |
| 4667 format %{ %} | |
| 4668 interface(CONST_INTER); | |
| 4669 %} | |
| 4670 | |
| 4671 // NULL Pointer Immediate | |
| 4672 operand immP0() %{ | |
| 4673 predicate( n->get_ptr() == 0 ); | |
| 4674 match(ConP); | |
| 4675 op_cost(0); | |
| 4676 | |
| 4677 format %{ %} | |
| 4678 interface(CONST_INTER); | |
| 4679 %} | |
| 4680 | |
| 4681 // Long Immediate | |
| 4682 operand immL() %{ | |
| 4683 match(ConL); | |
| 4684 | |
| 4685 op_cost(20); | |
| 4686 format %{ %} | |
| 4687 interface(CONST_INTER); | |
| 4688 %} | |
| 4689 | |
| 4690 // Long Immediate zero | |
| 4691 operand immL0() %{ | |
| 4692 predicate( n->get_long() == 0L ); | |
| 4693 match(ConL); | |
| 4694 op_cost(0); | |
| 4695 | |
| 4696 format %{ %} | |
| 4697 interface(CONST_INTER); | |
| 4698 %} | |
| 4699 | |
| 403 | 4700 // Long Immediate zero |
| 4701 operand immL_M1() %{ | |
| 4702 predicate( n->get_long() == -1L ); | |
| 4703 match(ConL); | |
| 4704 op_cost(0); | |
| 4705 | |
| 4706 format %{ %} | |
| 4707 interface(CONST_INTER); | |
| 4708 %} | |
| 4709 | |
| 0 | 4710 // Long immediate from 0 to 127. |
| 4711 // Used for a shorter form of long mul by 10. | |
| 4712 operand immL_127() %{ | |
| 4713 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4714 match(ConL); | |
| 4715 op_cost(0); | |
| 4716 | |
| 4717 format %{ %} | |
| 4718 interface(CONST_INTER); | |
| 4719 %} | |
| 4720 | |
| 4721 // Long Immediate: low 32-bit mask | |
| 4722 operand immL_32bits() %{ | |
| 4723 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4724 match(ConL); | |
| 4725 op_cost(0); | |
| 4726 | |
| 4727 format %{ %} | |
| 4728 interface(CONST_INTER); | |
| 4729 %} | |
| 4730 | |
| 4731 // Long Immediate: low 32-bit mask | |
| 4732 operand immL32() %{ | |
| 4733 predicate(n->get_long() == (int)(n->get_long())); | |
| 4734 match(ConL); | |
| 4735 op_cost(20); | |
| 4736 | |
| 4737 format %{ %} | |
| 4738 interface(CONST_INTER); | |
| 4739 %} | |
| 4740 | |
| 4741 //Double Immediate zero | |
| 4742 operand immD0() %{ | |
| 4743 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4744 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4745 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4746 match(ConD); | |
| 4747 | |
| 4748 op_cost(5); | |
| 4749 format %{ %} | |
| 4750 interface(CONST_INTER); | |
| 4751 %} | |
| 4752 | |
| 4753 // Double Immediate | |
| 4754 operand immD1() %{ | |
| 4755 predicate( UseSSE<=1 && n->getd() == 1.0 ); | |
| 4756 match(ConD); | |
| 4757 | |
| 4758 op_cost(5); | |
| 4759 format %{ %} | |
| 4760 interface(CONST_INTER); | |
| 4761 %} | |
| 4762 | |
| 4763 // Double Immediate | |
| 4764 operand immD() %{ | |
| 4765 predicate(UseSSE<=1); | |
| 4766 match(ConD); | |
| 4767 | |
| 4768 op_cost(5); | |
| 4769 format %{ %} | |
| 4770 interface(CONST_INTER); | |
| 4771 %} | |
| 4772 | |
| 4773 operand immXD() %{ | |
| 4774 predicate(UseSSE>=2); | |
| 4775 match(ConD); | |
| 4776 | |
| 4777 op_cost(5); | |
| 4778 format %{ %} | |
| 4779 interface(CONST_INTER); | |
| 4780 %} | |
| 4781 | |
| 4782 // Double Immediate zero | |
| 4783 operand immXD0() %{ | |
| 4784 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4785 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4786 // compare equal to -0.0. | |
| 4787 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4788 match(ConD); | |
| 4789 | |
| 4790 format %{ %} | |
| 4791 interface(CONST_INTER); | |
| 4792 %} | |
| 4793 | |
| 4794 // Float Immediate zero | |
| 4795 operand immF0() %{ | |
| 4796 predicate( UseSSE == 0 && n->getf() == 0.0 ); | |
| 4797 match(ConF); | |
| 4798 | |
| 4799 op_cost(5); | |
| 4800 format %{ %} | |
| 4801 interface(CONST_INTER); | |
| 4802 %} | |
| 4803 | |
| 4804 // Float Immediate | |
| 4805 operand immF() %{ | |
| 4806 predicate( UseSSE == 0 ); | |
| 4807 match(ConF); | |
| 4808 | |
| 4809 op_cost(5); | |
| 4810 format %{ %} | |
| 4811 interface(CONST_INTER); | |
| 4812 %} | |
| 4813 | |
| 4814 // Float Immediate | |
| 4815 operand immXF() %{ | |
| 4816 predicate(UseSSE >= 1); | |
| 4817 match(ConF); | |
| 4818 | |
| 4819 op_cost(5); | |
| 4820 format %{ %} | |
| 4821 interface(CONST_INTER); | |
| 4822 %} | |
| 4823 | |
| 4824 // Float Immediate zero. Zero and not -0.0 | |
| 4825 operand immXF0() %{ | |
| 4826 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); | |
| 4827 match(ConF); | |
| 4828 | |
| 4829 op_cost(5); | |
| 4830 format %{ %} | |
| 4831 interface(CONST_INTER); | |
| 4832 %} | |
| 4833 | |
| 4834 // Immediates for special shifts (sign extend) | |
| 4835 | |
| 4836 // Constants for increment | |
| 4837 operand immI_16() %{ | |
| 4838 predicate( n->get_int() == 16 ); | |
| 4839 match(ConI); | |
| 4840 | |
| 4841 format %{ %} | |
| 4842 interface(CONST_INTER); | |
| 4843 %} | |
| 4844 | |
| 4845 operand immI_24() %{ | |
| 4846 predicate( n->get_int() == 24 ); | |
| 4847 match(ConI); | |
| 4848 | |
| 4849 format %{ %} | |
| 4850 interface(CONST_INTER); | |
| 4851 %} | |
| 4852 | |
| 4853 // Constant for byte-wide masking | |
| 4854 operand immI_255() %{ | |
| 4855 predicate( n->get_int() == 255 ); | |
| 4856 match(ConI); | |
| 4857 | |
| 4858 format %{ %} | |
| 4859 interface(CONST_INTER); | |
| 4860 %} | |
| 4861 | |
| 785 | 4862 // Constant for short-wide masking |
| 4863 operand immI_65535() %{ | |
| 4864 predicate(n->get_int() == 65535); | |
| 4865 match(ConI); | |
| 4866 | |
| 4867 format %{ %} | |
| 4868 interface(CONST_INTER); | |
| 4869 %} | |
| 4870 | |
| 0 | 4871 // Register Operands |
| 4872 // Integer Register | |
| 4873 operand eRegI() %{ | |
| 4874 constraint(ALLOC_IN_RC(e_reg)); | |
| 4875 match(RegI); | |
| 4876 match(xRegI); | |
| 4877 match(eAXRegI); | |
| 4878 match(eBXRegI); | |
| 4879 match(eCXRegI); | |
| 4880 match(eDXRegI); | |
| 4881 match(eDIRegI); | |
| 4882 match(eSIRegI); | |
| 4883 | |
| 4884 format %{ %} | |
| 4885 interface(REG_INTER); | |
| 4886 %} | |
| 4887 | |
| 4888 // Subset of Integer Register | |
| 4889 operand xRegI(eRegI reg) %{ | |
| 4890 constraint(ALLOC_IN_RC(x_reg)); | |
| 4891 match(reg); | |
| 4892 match(eAXRegI); | |
| 4893 match(eBXRegI); | |
| 4894 match(eCXRegI); | |
| 4895 match(eDXRegI); | |
| 4896 | |
| 4897 format %{ %} | |
| 4898 interface(REG_INTER); | |
| 4899 %} | |
| 4900 | |
| 4901 // Special Registers | |
| 4902 operand eAXRegI(xRegI reg) %{ | |
| 4903 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4904 match(reg); | |
| 4905 match(eRegI); | |
| 4906 | |
| 4907 format %{ "EAX" %} | |
| 4908 interface(REG_INTER); | |
| 4909 %} | |
| 4910 | |
| 4911 // Special Registers | |
| 4912 operand eBXRegI(xRegI reg) %{ | |
| 4913 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4914 match(reg); | |
| 4915 match(eRegI); | |
| 4916 | |
| 4917 format %{ "EBX" %} | |
| 4918 interface(REG_INTER); | |
| 4919 %} | |
| 4920 | |
| 4921 operand eCXRegI(xRegI reg) %{ | |
| 4922 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4923 match(reg); | |
| 4924 match(eRegI); | |
| 4925 | |
| 4926 format %{ "ECX" %} | |
| 4927 interface(REG_INTER); | |
| 4928 %} | |
| 4929 | |
| 4930 operand eDXRegI(xRegI reg) %{ | |
| 4931 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4932 match(reg); | |
| 4933 match(eRegI); | |
| 4934 | |
| 4935 format %{ "EDX" %} | |
| 4936 interface(REG_INTER); | |
| 4937 %} | |
| 4938 | |
| 4939 operand eDIRegI(xRegI reg) %{ | |
| 4940 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4941 match(reg); | |
| 4942 match(eRegI); | |
| 4943 | |
| 4944 format %{ "EDI" %} | |
| 4945 interface(REG_INTER); | |
| 4946 %} | |
| 4947 | |
| 4948 operand naxRegI() %{ | |
| 4949 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4950 match(RegI); | |
| 4951 match(eCXRegI); | |
| 4952 match(eDXRegI); | |
| 4953 match(eSIRegI); | |
| 4954 match(eDIRegI); | |
| 4955 | |
| 4956 format %{ %} | |
| 4957 interface(REG_INTER); | |
| 4958 %} | |
| 4959 | |
| 4960 operand nadxRegI() %{ | |
| 4961 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4962 match(RegI); | |
| 4963 match(eBXRegI); | |
| 4964 match(eCXRegI); | |
| 4965 match(eSIRegI); | |
| 4966 match(eDIRegI); | |
| 4967 | |
| 4968 format %{ %} | |
| 4969 interface(REG_INTER); | |
| 4970 %} | |
| 4971 | |
| 4972 operand ncxRegI() %{ | |
| 4973 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4974 match(RegI); | |
| 4975 match(eAXRegI); | |
| 4976 match(eDXRegI); | |
| 4977 match(eSIRegI); | |
| 4978 match(eDIRegI); | |
| 4979 | |
| 4980 format %{ %} | |
| 4981 interface(REG_INTER); | |
| 4982 %} | |
| 4983 | |
| 4984 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4985 // // | |
| 4986 operand eSIRegI(xRegI reg) %{ | |
| 4987 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4988 match(reg); | |
| 4989 match(eRegI); | |
| 4990 | |
| 4991 format %{ "ESI" %} | |
| 4992 interface(REG_INTER); | |
| 4993 %} | |
| 4994 | |
| 4995 // Pointer Register | |
| 4996 operand anyRegP() %{ | |
| 4997 constraint(ALLOC_IN_RC(any_reg)); | |
| 4998 match(RegP); | |
| 4999 match(eAXRegP); | |
| 5000 match(eBXRegP); | |
| 5001 match(eCXRegP); | |
| 5002 match(eDIRegP); | |
| 5003 match(eRegP); | |
| 5004 | |
| 5005 format %{ %} | |
| 5006 interface(REG_INTER); | |
| 5007 %} | |
| 5008 | |
| 5009 operand eRegP() %{ | |
| 5010 constraint(ALLOC_IN_RC(e_reg)); | |
| 5011 match(RegP); | |
| 5012 match(eAXRegP); | |
| 5013 match(eBXRegP); | |
| 5014 match(eCXRegP); | |
| 5015 match(eDIRegP); | |
| 5016 | |
| 5017 format %{ %} | |
| 5018 interface(REG_INTER); | |
| 5019 %} | |
| 5020 | |
| 5021 // On windows95, EBP is not safe to use for implicit null tests. | |
| 5022 operand eRegP_no_EBP() %{ | |
| 5023 constraint(ALLOC_IN_RC(e_reg_no_rbp)); | |
| 5024 match(RegP); | |
| 5025 match(eAXRegP); | |
| 5026 match(eBXRegP); | |
| 5027 match(eCXRegP); | |
| 5028 match(eDIRegP); | |
| 5029 | |
| 5030 op_cost(100); | |
| 5031 format %{ %} | |
| 5032 interface(REG_INTER); | |
| 5033 %} | |
| 5034 | |
| 5035 operand naxRegP() %{ | |
| 5036 constraint(ALLOC_IN_RC(nax_reg)); | |
| 5037 match(RegP); | |
| 5038 match(eBXRegP); | |
| 5039 match(eDXRegP); | |
| 5040 match(eCXRegP); | |
| 5041 match(eSIRegP); | |
| 5042 match(eDIRegP); | |
| 5043 | |
| 5044 format %{ %} | |
| 5045 interface(REG_INTER); | |
| 5046 %} | |
| 5047 | |
| 5048 operand nabxRegP() %{ | |
| 5049 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 5050 match(RegP); | |
| 5051 match(eCXRegP); | |
| 5052 match(eDXRegP); | |
| 5053 match(eSIRegP); | |
| 5054 match(eDIRegP); | |
| 5055 | |
| 5056 format %{ %} | |
| 5057 interface(REG_INTER); | |
| 5058 %} | |
| 5059 | |
| 5060 operand pRegP() %{ | |
| 5061 constraint(ALLOC_IN_RC(p_reg)); | |
| 5062 match(RegP); | |
| 5063 match(eBXRegP); | |
| 5064 match(eDXRegP); | |
| 5065 match(eSIRegP); | |
| 5066 match(eDIRegP); | |
| 5067 | |
| 5068 format %{ %} | |
| 5069 interface(REG_INTER); | |
| 5070 %} | |
| 5071 | |
| 5072 // Special Registers | |
| 5073 // Return a pointer value | |
| 5074 operand eAXRegP(eRegP reg) %{ | |
| 5075 constraint(ALLOC_IN_RC(eax_reg)); | |
| 5076 match(reg); | |
| 5077 format %{ "EAX" %} | |
| 5078 interface(REG_INTER); | |
| 5079 %} | |
| 5080 | |
| 5081 // Used in AtomicAdd | |
| 5082 operand eBXRegP(eRegP reg) %{ | |
| 5083 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 5084 match(reg); | |
| 5085 format %{ "EBX" %} | |
| 5086 interface(REG_INTER); | |
| 5087 %} | |
| 5088 | |
| 5089 // Tail-call (interprocedural jump) to interpreter | |
| 5090 operand eCXRegP(eRegP reg) %{ | |
| 5091 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 5092 match(reg); | |
| 5093 format %{ "ECX" %} | |
| 5094 interface(REG_INTER); | |
| 5095 %} | |
| 5096 | |
| 5097 operand eSIRegP(eRegP reg) %{ | |
| 5098 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5099 match(reg); | |
| 5100 format %{ "ESI" %} | |
| 5101 interface(REG_INTER); | |
| 5102 %} | |
| 5103 | |
| 5104 // Used in rep stosw | |
| 5105 operand eDIRegP(eRegP reg) %{ | |
| 5106 constraint(ALLOC_IN_RC(edi_reg)); | |
| 5107 match(reg); | |
| 5108 format %{ "EDI" %} | |
| 5109 interface(REG_INTER); | |
| 5110 %} | |
| 5111 | |
| 5112 operand eBPRegP() %{ | |
| 5113 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 5114 match(RegP); | |
| 5115 format %{ "EBP" %} | |
| 5116 interface(REG_INTER); | |
| 5117 %} | |
| 5118 | |
| 5119 operand eRegL() %{ | |
| 5120 constraint(ALLOC_IN_RC(long_reg)); | |
| 5121 match(RegL); | |
| 5122 match(eADXRegL); | |
| 5123 | |
| 5124 format %{ %} | |
| 5125 interface(REG_INTER); | |
| 5126 %} | |
| 5127 | |
| 5128 operand eADXRegL( eRegL reg ) %{ | |
| 5129 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5130 match(reg); | |
| 5131 | |
| 5132 format %{ "EDX:EAX" %} | |
| 5133 interface(REG_INTER); | |
| 5134 %} | |
| 5135 | |
| 5136 operand eBCXRegL( eRegL reg ) %{ | |
| 5137 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 5138 match(reg); | |
| 5139 | |
| 5140 format %{ "EBX:ECX" %} | |
| 5141 interface(REG_INTER); | |
| 5142 %} | |
| 5143 | |
| 5144 // Special case for integer high multiply | |
| 5145 operand eADXRegL_low_only() %{ | |
| 5146 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5147 match(RegL); | |
| 5148 | |
| 5149 format %{ "EAX" %} | |
| 5150 interface(REG_INTER); | |
| 5151 %} | |
| 5152 | |
| 5153 // Flags register, used as output of compare instructions | |
| 5154 operand eFlagsReg() %{ | |
| 5155 constraint(ALLOC_IN_RC(int_flags)); | |
| 5156 match(RegFlags); | |
| 5157 | |
| 5158 format %{ "EFLAGS" %} | |
| 5159 interface(REG_INTER); | |
| 5160 %} | |
| 5161 | |
| 5162 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5163 operand eFlagsRegU() %{ | |
| 5164 constraint(ALLOC_IN_RC(int_flags)); | |
| 5165 match(RegFlags); | |
| 5166 | |
| 5167 format %{ "EFLAGS_U" %} | |
| 5168 interface(REG_INTER); | |
| 5169 %} | |
| 5170 | |
|
415
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|
5171 operand eFlagsRegUCF() %{ |
|
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|
5172 constraint(ALLOC_IN_RC(int_flags)); |
|
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parents:
403
diff
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|
5173 match(RegFlags); |
|
4d9884b01ba6
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403
diff
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|
5174 predicate(false); |
|
4d9884b01ba6
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never
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diff
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|
5175 |
|
4d9884b01ba6
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403
diff
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|
5176 format %{ "EFLAGS_U_CF" %} |
|
4d9884b01ba6
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diff
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|
5177 interface(REG_INTER); |
|
4d9884b01ba6
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|
5178 %} |
|
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|
5179 |
| 0 | 5180 // Condition Code Register used by long compare |
| 5181 operand flagsReg_long_LTGE() %{ | |
| 5182 constraint(ALLOC_IN_RC(int_flags)); | |
| 5183 match(RegFlags); | |
| 5184 format %{ "FLAGS_LTGE" %} | |
| 5185 interface(REG_INTER); | |
| 5186 %} | |
| 5187 operand flagsReg_long_EQNE() %{ | |
| 5188 constraint(ALLOC_IN_RC(int_flags)); | |
| 5189 match(RegFlags); | |
| 5190 format %{ "FLAGS_EQNE" %} | |
| 5191 interface(REG_INTER); | |
| 5192 %} | |
| 5193 operand flagsReg_long_LEGT() %{ | |
| 5194 constraint(ALLOC_IN_RC(int_flags)); | |
| 5195 match(RegFlags); | |
| 5196 format %{ "FLAGS_LEGT" %} | |
| 5197 interface(REG_INTER); | |
| 5198 %} | |
| 5199 | |
| 5200 // Float register operands | |
| 5201 operand regD() %{ | |
| 5202 predicate( UseSSE < 2 ); | |
| 5203 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 5204 match(RegD); | |
| 5205 match(regDPR1); | |
| 5206 match(regDPR2); | |
| 5207 format %{ %} | |
| 5208 interface(REG_INTER); | |
| 5209 %} | |
| 5210 | |
| 5211 operand regDPR1(regD reg) %{ | |
| 5212 predicate( UseSSE < 2 ); | |
| 5213 constraint(ALLOC_IN_RC(dbl_reg0)); | |
| 5214 match(reg); | |
| 5215 format %{ "FPR1" %} | |
| 5216 interface(REG_INTER); | |
| 5217 %} | |
| 5218 | |
| 5219 operand regDPR2(regD reg) %{ | |
| 5220 predicate( UseSSE < 2 ); | |
| 5221 constraint(ALLOC_IN_RC(dbl_reg1)); | |
| 5222 match(reg); | |
| 5223 format %{ "FPR2" %} | |
| 5224 interface(REG_INTER); | |
| 5225 %} | |
| 5226 | |
| 5227 operand regnotDPR1(regD reg) %{ | |
| 5228 predicate( UseSSE < 2 ); | |
| 5229 constraint(ALLOC_IN_RC(dbl_notreg0)); | |
| 5230 match(reg); | |
| 5231 format %{ %} | |
| 5232 interface(REG_INTER); | |
| 5233 %} | |
| 5234 | |
| 5235 // XMM Double register operands | |
| 5236 operand regXD() %{ | |
| 5237 predicate( UseSSE>=2 ); | |
| 5238 constraint(ALLOC_IN_RC(xdb_reg)); | |
| 5239 match(RegD); | |
| 5240 match(regXD6); | |
| 5241 match(regXD7); | |
| 5242 format %{ %} | |
| 5243 interface(REG_INTER); | |
| 5244 %} | |
| 5245 | |
| 5246 // XMM6 double register operands | |
| 5247 operand regXD6(regXD reg) %{ | |
| 5248 predicate( UseSSE>=2 ); | |
| 5249 constraint(ALLOC_IN_RC(xdb_reg6)); | |
| 5250 match(reg); | |
| 5251 format %{ "XMM6" %} | |
| 5252 interface(REG_INTER); | |
| 5253 %} | |
| 5254 | |
| 5255 // XMM7 double register operands | |
| 5256 operand regXD7(regXD reg) %{ | |
| 5257 predicate( UseSSE>=2 ); | |
| 5258 constraint(ALLOC_IN_RC(xdb_reg7)); | |
| 5259 match(reg); | |
| 5260 format %{ "XMM7" %} | |
| 5261 interface(REG_INTER); | |
| 5262 %} | |
| 5263 | |
| 5264 // Float register operands | |
| 5265 operand regF() %{ | |
| 5266 predicate( UseSSE < 2 ); | |
| 5267 constraint(ALLOC_IN_RC(flt_reg)); | |
| 5268 match(RegF); | |
| 5269 match(regFPR1); | |
| 5270 format %{ %} | |
| 5271 interface(REG_INTER); | |
| 5272 %} | |
| 5273 | |
| 5274 // Float register operands | |
| 5275 operand regFPR1(regF reg) %{ | |
| 5276 predicate( UseSSE < 2 ); | |
| 5277 constraint(ALLOC_IN_RC(flt_reg0)); | |
| 5278 match(reg); | |
| 5279 format %{ "FPR1" %} | |
| 5280 interface(REG_INTER); | |
| 5281 %} | |
| 5282 | |
| 5283 // XMM register operands | |
| 5284 operand regX() %{ | |
| 5285 predicate( UseSSE>=1 ); | |
| 5286 constraint(ALLOC_IN_RC(xmm_reg)); | |
| 5287 match(RegF); | |
| 5288 format %{ %} | |
| 5289 interface(REG_INTER); | |
| 5290 %} | |
| 5291 | |
| 5292 | |
| 5293 //----------Memory Operands---------------------------------------------------- | |
| 5294 // Direct Memory Operand | |
| 5295 operand direct(immP addr) %{ | |
| 5296 match(addr); | |
| 5297 | |
| 5298 format %{ "[$addr]" %} | |
| 5299 interface(MEMORY_INTER) %{ | |
| 5300 base(0xFFFFFFFF); | |
| 5301 index(0x4); | |
| 5302 scale(0x0); | |
| 5303 disp($addr); | |
| 5304 %} | |
| 5305 %} | |
| 5306 | |
| 5307 // Indirect Memory Operand | |
| 5308 operand indirect(eRegP reg) %{ | |
| 5309 constraint(ALLOC_IN_RC(e_reg)); | |
| 5310 match(reg); | |
| 5311 | |
| 5312 format %{ "[$reg]" %} | |
| 5313 interface(MEMORY_INTER) %{ | |
| 5314 base($reg); | |
| 5315 index(0x4); | |
| 5316 scale(0x0); | |
| 5317 disp(0x0); | |
| 5318 %} | |
| 5319 %} | |
| 5320 | |
| 5321 // Indirect Memory Plus Short Offset Operand | |
| 5322 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 5323 match(AddP reg off); | |
| 5324 | |
| 5325 format %{ "[$reg + $off]" %} | |
| 5326 interface(MEMORY_INTER) %{ | |
| 5327 base($reg); | |
| 5328 index(0x4); | |
| 5329 scale(0x0); | |
| 5330 disp($off); | |
| 5331 %} | |
| 5332 %} | |
| 5333 | |
| 5334 // Indirect Memory Plus Long Offset Operand | |
| 5335 operand indOffset32(eRegP reg, immI off) %{ | |
| 5336 match(AddP reg off); | |
| 5337 | |
| 5338 format %{ "[$reg + $off]" %} | |
| 5339 interface(MEMORY_INTER) %{ | |
| 5340 base($reg); | |
| 5341 index(0x4); | |
| 5342 scale(0x0); | |
| 5343 disp($off); | |
| 5344 %} | |
| 5345 %} | |
| 5346 | |
| 5347 // Indirect Memory Plus Long Offset Operand | |
| 5348 operand indOffset32X(eRegI reg, immP off) %{ | |
| 5349 match(AddP off reg); | |
| 5350 | |
| 5351 format %{ "[$reg + $off]" %} | |
| 5352 interface(MEMORY_INTER) %{ | |
| 5353 base($reg); | |
| 5354 index(0x4); | |
| 5355 scale(0x0); | |
| 5356 disp($off); | |
| 5357 %} | |
| 5358 %} | |
| 5359 | |
| 5360 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5361 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ | |
| 5362 match(AddP (AddP reg ireg) off); | |
| 5363 | |
| 5364 op_cost(10); | |
| 5365 format %{"[$reg + $off + $ireg]" %} | |
| 5366 interface(MEMORY_INTER) %{ | |
| 5367 base($reg); | |
| 5368 index($ireg); | |
| 5369 scale(0x0); | |
| 5370 disp($off); | |
| 5371 %} | |
| 5372 %} | |
| 5373 | |
| 5374 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5375 operand indIndex(eRegP reg, eRegI ireg) %{ | |
| 5376 match(AddP reg ireg); | |
| 5377 | |
| 5378 op_cost(10); | |
| 5379 format %{"[$reg + $ireg]" %} | |
| 5380 interface(MEMORY_INTER) %{ | |
| 5381 base($reg); | |
| 5382 index($ireg); | |
| 5383 scale(0x0); | |
| 5384 disp(0x0); | |
| 5385 %} | |
| 5386 %} | |
| 5387 | |
| 5388 // // ------------------------------------------------------------------------- | |
| 5389 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 5390 // // ------------------------------------------------------------------------- | |
| 5391 // // Scaled Memory Operands | |
| 5392 // // Indirect Memory Times Scale Plus Offset Operand | |
| 5393 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ | |
| 5394 // match(AddP off (LShiftI ireg scale)); | |
| 5395 // | |
| 5396 // op_cost(10); | |
| 5397 // format %{"[$off + $ireg << $scale]" %} | |
| 5398 // interface(MEMORY_INTER) %{ | |
| 5399 // base(0x4); | |
| 5400 // index($ireg); | |
| 5401 // scale($scale); | |
| 5402 // disp($off); | |
| 5403 // %} | |
| 5404 // %} | |
| 5405 | |
| 5406 // Indirect Memory Times Scale Plus Index Register | |
| 5407 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ | |
| 5408 match(AddP reg (LShiftI ireg scale)); | |
| 5409 | |
| 5410 op_cost(10); | |
| 5411 format %{"[$reg + $ireg << $scale]" %} | |
| 5412 interface(MEMORY_INTER) %{ | |
| 5413 base($reg); | |
| 5414 index($ireg); | |
| 5415 scale($scale); | |
| 5416 disp(0x0); | |
| 5417 %} | |
| 5418 %} | |
| 5419 | |
| 5420 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5421 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ | |
| 5422 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5423 | |
| 5424 op_cost(10); | |
| 5425 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5426 interface(MEMORY_INTER) %{ | |
| 5427 base($reg); | |
| 5428 index($ireg); | |
| 5429 scale($scale); | |
| 5430 disp($off); | |
| 5431 %} | |
| 5432 %} | |
| 5433 | |
| 5434 //----------Load Long Memory Operands------------------------------------------ | |
| 5435 // The load-long idiom will use it's address expression again after loading | |
| 5436 // the first word of the long. If the load-long destination overlaps with | |
| 5437 // registers used in the addressing expression, the 2nd half will be loaded | |
| 5438 // from a clobbered address. Fix this by requiring that load-long use | |
| 5439 // address registers that do not overlap with the load-long target. | |
| 5440 | |
| 5441 // load-long support | |
| 5442 operand load_long_RegP() %{ | |
| 5443 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5444 match(RegP); | |
| 5445 match(eSIRegP); | |
| 5446 op_cost(100); | |
| 5447 format %{ %} | |
| 5448 interface(REG_INTER); | |
| 5449 %} | |
| 5450 | |
| 5451 // Indirect Memory Operand Long | |
| 5452 operand load_long_indirect(load_long_RegP reg) %{ | |
| 5453 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5454 match(reg); | |
| 5455 | |
| 5456 format %{ "[$reg]" %} | |
| 5457 interface(MEMORY_INTER) %{ | |
| 5458 base($reg); | |
| 5459 index(0x4); | |
| 5460 scale(0x0); | |
| 5461 disp(0x0); | |
| 5462 %} | |
| 5463 %} | |
| 5464 | |
| 5465 // Indirect Memory Plus Long Offset Operand | |
| 5466 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 5467 match(AddP reg off); | |
| 5468 | |
| 5469 format %{ "[$reg + $off]" %} | |
| 5470 interface(MEMORY_INTER) %{ | |
| 5471 base($reg); | |
| 5472 index(0x4); | |
| 5473 scale(0x0); | |
| 5474 disp($off); | |
| 5475 %} | |
| 5476 %} | |
| 5477 | |
| 5478 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 5479 | |
| 5480 | |
| 5481 //----------Special Memory Operands-------------------------------------------- | |
| 5482 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5483 // values on the stack where a match requires a value to | |
| 5484 // flow through memory. | |
| 5485 operand stackSlotP(sRegP reg) %{ | |
| 5486 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5487 // No match rule because this operand is only generated in matching | |
| 5488 format %{ "[$reg]" %} | |
| 5489 interface(MEMORY_INTER) %{ | |
| 5490 base(0x4); // ESP | |
| 5491 index(0x4); // No Index | |
| 5492 scale(0x0); // No Scale | |
| 5493 disp($reg); // Stack Offset | |
| 5494 %} | |
| 5495 %} | |
| 5496 | |
| 5497 operand stackSlotI(sRegI reg) %{ | |
| 5498 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5499 // No match rule because this operand is only generated in matching | |
| 5500 format %{ "[$reg]" %} | |
| 5501 interface(MEMORY_INTER) %{ | |
| 5502 base(0x4); // ESP | |
| 5503 index(0x4); // No Index | |
| 5504 scale(0x0); // No Scale | |
| 5505 disp($reg); // Stack Offset | |
| 5506 %} | |
| 5507 %} | |
| 5508 | |
| 5509 operand stackSlotF(sRegF reg) %{ | |
| 5510 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5511 // No match rule because this operand is only generated in matching | |
| 5512 format %{ "[$reg]" %} | |
| 5513 interface(MEMORY_INTER) %{ | |
| 5514 base(0x4); // ESP | |
| 5515 index(0x4); // No Index | |
| 5516 scale(0x0); // No Scale | |
| 5517 disp($reg); // Stack Offset | |
| 5518 %} | |
| 5519 %} | |
| 5520 | |
| 5521 operand stackSlotD(sRegD reg) %{ | |
| 5522 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5523 // No match rule because this operand is only generated in matching | |
| 5524 format %{ "[$reg]" %} | |
| 5525 interface(MEMORY_INTER) %{ | |
| 5526 base(0x4); // ESP | |
| 5527 index(0x4); // No Index | |
| 5528 scale(0x0); // No Scale | |
| 5529 disp($reg); // Stack Offset | |
| 5530 %} | |
| 5531 %} | |
| 5532 | |
| 5533 operand stackSlotL(sRegL reg) %{ | |
| 5534 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5535 // No match rule because this operand is only generated in matching | |
| 5536 format %{ "[$reg]" %} | |
| 5537 interface(MEMORY_INTER) %{ | |
| 5538 base(0x4); // ESP | |
| 5539 index(0x4); // No Index | |
| 5540 scale(0x0); // No Scale | |
| 5541 disp($reg); // Stack Offset | |
| 5542 %} | |
| 5543 %} | |
| 5544 | |
| 5545 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 5546 // Indirect Memory Operand | |
| 5547 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 5548 %{ | |
| 5549 constraint(ALLOC_IN_RC(e_reg)); | |
| 5550 match(reg); | |
| 5551 | |
| 5552 op_cost(100); | |
| 5553 format %{ "[$reg]" %} | |
| 5554 interface(MEMORY_INTER) %{ | |
| 5555 base($reg); | |
| 5556 index(0x4); | |
| 5557 scale(0x0); | |
| 5558 disp(0x0); | |
| 5559 %} | |
| 5560 %} | |
| 5561 | |
| 5562 // Indirect Memory Plus Short Offset Operand | |
| 5563 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 5564 %{ | |
| 5565 match(AddP reg off); | |
| 5566 | |
| 5567 op_cost(100); | |
| 5568 format %{ "[$reg + $off]" %} | |
| 5569 interface(MEMORY_INTER) %{ | |
| 5570 base($reg); | |
| 5571 index(0x4); | |
| 5572 scale(0x0); | |
| 5573 disp($off); | |
| 5574 %} | |
| 5575 %} | |
| 5576 | |
| 5577 // Indirect Memory Plus Long Offset Operand | |
| 5578 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 5579 %{ | |
| 5580 match(AddP reg off); | |
| 5581 | |
| 5582 op_cost(100); | |
| 5583 format %{ "[$reg + $off]" %} | |
| 5584 interface(MEMORY_INTER) %{ | |
| 5585 base($reg); | |
| 5586 index(0x4); | |
| 5587 scale(0x0); | |
| 5588 disp($off); | |
| 5589 %} | |
| 5590 %} | |
| 5591 | |
| 5592 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5593 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) | |
| 5594 %{ | |
| 5595 match(AddP (AddP reg ireg) off); | |
| 5596 | |
| 5597 op_cost(100); | |
| 5598 format %{"[$reg + $off + $ireg]" %} | |
| 5599 interface(MEMORY_INTER) %{ | |
| 5600 base($reg); | |
| 5601 index($ireg); | |
| 5602 scale(0x0); | |
| 5603 disp($off); | |
| 5604 %} | |
| 5605 %} | |
| 5606 | |
| 5607 // Indirect Memory Times Scale Plus Index Register | |
| 5608 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) | |
| 5609 %{ | |
| 5610 match(AddP reg (LShiftI ireg scale)); | |
| 5611 | |
| 5612 op_cost(100); | |
| 5613 format %{"[$reg + $ireg << $scale]" %} | |
| 5614 interface(MEMORY_INTER) %{ | |
| 5615 base($reg); | |
| 5616 index($ireg); | |
| 5617 scale($scale); | |
| 5618 disp(0x0); | |
| 5619 %} | |
| 5620 %} | |
| 5621 | |
| 5622 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5623 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) | |
| 5624 %{ | |
| 5625 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5626 | |
| 5627 op_cost(100); | |
| 5628 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5629 interface(MEMORY_INTER) %{ | |
| 5630 base($reg); | |
| 5631 index($ireg); | |
| 5632 scale($scale); | |
| 5633 disp($off); | |
| 5634 %} | |
| 5635 %} | |
| 5636 | |
| 5637 //----------Conditional Branch Operands---------------------------------------- | |
| 5638 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5639 // the following set of codes: | |
| 5640 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5641 // | |
| 5642 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5643 // by the comparison instruction that sets a condition code flags register. | |
| 5644 // That result is represented by a flags operand whose subtype is appropriate | |
| 5645 // to the unsignedness (etc.) of the comparison. | |
| 5646 // | |
| 5647 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5648 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5649 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5650 | |
| 5651 // Comparision Code | |
| 5652 operand cmpOp() %{ | |
| 5653 match(Bool); | |
| 5654 | |
| 5655 format %{ "" %} | |
| 5656 interface(COND_INTER) %{ | |
|
415
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403
diff
changeset
|
5657 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
5658 not_equal(0x5, "ne"); |
|
4d9884b01ba6
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403
diff
changeset
|
5659 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5660 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
5661 less_equal(0xE, "le"); |
|
4d9884b01ba6
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diff
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|
5662 greater(0xF, "g"); |
| 0 | 5663 %} |
| 5664 %} | |
| 5665 | |
| 5666 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5667 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5668 // C0 and C3 are turned into Carry & Zero flags. | |
| 5669 operand cmpOpU() %{ | |
| 5670 match(Bool); | |
| 5671 | |
| 5672 format %{ "" %} | |
| 5673 interface(COND_INTER) %{ | |
|
415
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parents:
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diff
changeset
|
5674 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5675 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5676 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5677 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5678 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5679 greater(0x7, "nbe"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5680 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5681 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5682 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5683 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
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|
5684 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5685 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5686 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5687 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5688 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5689 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
5690 format %{ "" %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
5691 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5692 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5693 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5694 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5695 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5696 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5697 greater(0x7, "nbe"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5698 %} |
|
4d9884b01ba6
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diff
changeset
|
5699 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5700 |
|
4d9884b01ba6
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diff
changeset
|
5701 |
|
4d9884b01ba6
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403
diff
changeset
|
5702 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
5703 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
5704 match(Bool); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5705 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
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403
diff
changeset
|
5706 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5707 format %{ "" %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
5708 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5709 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5710 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
5711 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5712 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5713 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5714 greater(0x7, "nbe"); |
| 0 | 5715 %} |
| 5716 %} | |
| 5717 | |
| 5718 // Comparison Code for FP conditional move | |
| 5719 operand cmpOp_fcmov() %{ | |
| 5720 match(Bool); | |
| 5721 | |
| 5722 format %{ "" %} | |
| 5723 interface(COND_INTER) %{ | |
| 5724 equal (0x0C8); | |
| 5725 not_equal (0x1C8); | |
| 5726 less (0x0C0); | |
| 5727 greater_equal(0x1C0); | |
| 5728 less_equal (0x0D0); | |
| 5729 greater (0x1D0); | |
| 5730 %} | |
| 5731 %} | |
| 5732 | |
| 5733 // Comparision Code used in long compares | |
| 5734 operand cmpOp_commute() %{ | |
| 5735 match(Bool); | |
| 5736 | |
| 5737 format %{ "" %} | |
| 5738 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
5739 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5740 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5741 less(0xF, "g"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5742 greater_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5743 less_equal(0xD, "ge"); |
|
4d9884b01ba6
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diff
changeset
|
5744 greater(0xC, "l"); |
| 0 | 5745 %} |
| 5746 %} | |
| 5747 | |
| 5748 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5749 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5750 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5751 // instructions for every form of operand when the instruction accepts |
| 5752 // multiple operand types with the same basic encoding and format. The classic | |
| 5753 // case of this is memory operands. | |
| 5754 | |
| 5755 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5756 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5757 | |
| 5758 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5759 // This means some kind of offset is always required and you cannot use | |
| 5760 // an oop as the offset (done when working on static globals). | |
| 5761 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5762 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5763 | |
| 5764 | |
| 5765 //----------PIPELINE----------------------------------------------------------- | |
| 5766 // Rules which define the behavior of the target architectures pipeline. | |
| 5767 pipeline %{ | |
| 5768 | |
| 5769 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5770 attributes %{ | |
| 5771 variable_size_instructions; // Fixed size instructions | |
| 5772 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5773 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5774 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5775 instruction_fetch_units = 1; // of 16 bytes | |
| 5776 | |
| 5777 // List of nop instructions | |
| 5778 nops( MachNop ); | |
| 5779 %} | |
| 5780 | |
| 5781 //----------RESOURCES---------------------------------------------------------- | |
| 5782 // Resources are the functional units available to the machine | |
| 5783 | |
| 5784 // Generic P2/P3 pipeline | |
| 5785 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5786 // 3 instructions decoded per cycle. | |
| 5787 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5788 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5789 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5790 MS0, MS1, MEM = MS0 | MS1, | |
| 5791 BR, FPU, | |
| 5792 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5793 | |
| 5794 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5795 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5796 | |
| 5797 // Generic P2/P3 pipeline | |
| 5798 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5799 | |
| 5800 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5801 // Pipeline Classes describe the stages in which input and output are | |
| 5802 // referenced by the hardware pipeline. | |
| 5803 | |
| 5804 // Naming convention: ialu or fpu | |
| 5805 // Then: _reg | |
| 5806 // Then: _reg if there is a 2nd register | |
| 5807 // Then: _long if it's a pair of instructions implementing a long | |
| 5808 // Then: _fat if it requires the big decoder | |
| 5809 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5810 | |
| 5811 // Integer ALU reg operation | |
| 5812 pipe_class ialu_reg(eRegI dst) %{ | |
| 5813 single_instruction; | |
| 5814 dst : S4(write); | |
| 5815 dst : S3(read); | |
| 5816 DECODE : S0; // any decoder | |
| 5817 ALU : S3; // any alu | |
| 5818 %} | |
| 5819 | |
| 5820 // Long ALU reg operation | |
| 5821 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5822 instruction_count(2); | |
| 5823 dst : S4(write); | |
| 5824 dst : S3(read); | |
| 5825 DECODE : S0(2); // any 2 decoders | |
| 5826 ALU : S3(2); // both alus | |
| 5827 %} | |
| 5828 | |
| 5829 // Integer ALU reg operation using big decoder | |
| 5830 pipe_class ialu_reg_fat(eRegI dst) %{ | |
| 5831 single_instruction; | |
| 5832 dst : S4(write); | |
| 5833 dst : S3(read); | |
| 5834 D0 : S0; // big decoder only | |
| 5835 ALU : S3; // any alu | |
| 5836 %} | |
| 5837 | |
| 5838 // Long ALU reg operation using big decoder | |
| 5839 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5840 instruction_count(2); | |
| 5841 dst : S4(write); | |
| 5842 dst : S3(read); | |
| 5843 D0 : S0(2); // big decoder only; twice | |
| 5844 ALU : S3(2); // any 2 alus | |
| 5845 %} | |
| 5846 | |
| 5847 // Integer ALU reg-reg operation | |
| 5848 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ | |
| 5849 single_instruction; | |
| 5850 dst : S4(write); | |
| 5851 src : S3(read); | |
| 5852 DECODE : S0; // any decoder | |
| 5853 ALU : S3; // any alu | |
| 5854 %} | |
| 5855 | |
| 5856 // Long ALU reg-reg operation | |
| 5857 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5858 instruction_count(2); | |
| 5859 dst : S4(write); | |
| 5860 src : S3(read); | |
| 5861 DECODE : S0(2); // any 2 decoders | |
| 5862 ALU : S3(2); // both alus | |
| 5863 %} | |
| 5864 | |
| 5865 // Integer ALU reg-reg operation | |
| 5866 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ | |
| 5867 single_instruction; | |
| 5868 dst : S4(write); | |
| 5869 src : S3(read); | |
| 5870 D0 : S0; // big decoder only | |
| 5871 ALU : S3; // any alu | |
| 5872 %} | |
| 5873 | |
| 5874 // Long ALU reg-reg operation | |
| 5875 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5876 instruction_count(2); | |
| 5877 dst : S4(write); | |
| 5878 src : S3(read); | |
| 5879 D0 : S0(2); // big decoder only; twice | |
| 5880 ALU : S3(2); // both alus | |
| 5881 %} | |
| 5882 | |
| 5883 // Integer ALU reg-mem operation | |
| 5884 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ | |
| 5885 single_instruction; | |
| 5886 dst : S5(write); | |
| 5887 mem : S3(read); | |
| 5888 D0 : S0; // big decoder only | |
| 5889 ALU : S4; // any alu | |
| 5890 MEM : S3; // any mem | |
| 5891 %} | |
| 5892 | |
| 5893 // Long ALU reg-mem operation | |
| 5894 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5895 instruction_count(2); | |
| 5896 dst : S5(write); | |
| 5897 mem : S3(read); | |
| 5898 D0 : S0(2); // big decoder only; twice | |
| 5899 ALU : S4(2); // any 2 alus | |
| 5900 MEM : S3(2); // both mems | |
| 5901 %} | |
| 5902 | |
| 5903 // Integer mem operation (prefetch) | |
| 5904 pipe_class ialu_mem(memory mem) | |
| 5905 %{ | |
| 5906 single_instruction; | |
| 5907 mem : S3(read); | |
| 5908 D0 : S0; // big decoder only | |
| 5909 MEM : S3; // any mem | |
| 5910 %} | |
| 5911 | |
| 5912 // Integer Store to Memory | |
| 5913 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ | |
| 5914 single_instruction; | |
| 5915 mem : S3(read); | |
| 5916 src : S5(read); | |
| 5917 D0 : S0; // big decoder only | |
| 5918 ALU : S4; // any alu | |
| 5919 MEM : S3; | |
| 5920 %} | |
| 5921 | |
| 5922 // Long Store to Memory | |
| 5923 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5924 instruction_count(2); | |
| 5925 mem : S3(read); | |
| 5926 src : S5(read); | |
| 5927 D0 : S0(2); // big decoder only; twice | |
| 5928 ALU : S4(2); // any 2 alus | |
| 5929 MEM : S3(2); // Both mems | |
| 5930 %} | |
| 5931 | |
| 5932 // Integer Store to Memory | |
| 5933 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5934 single_instruction; | |
| 5935 mem : S3(read); | |
| 5936 D0 : S0; // big decoder only | |
| 5937 ALU : S4; // any alu | |
| 5938 MEM : S3; | |
| 5939 %} | |
| 5940 | |
| 5941 // Integer ALU0 reg-reg operation | |
| 5942 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ | |
| 5943 single_instruction; | |
| 5944 dst : S4(write); | |
| 5945 src : S3(read); | |
| 5946 D0 : S0; // Big decoder only | |
| 5947 ALU0 : S3; // only alu0 | |
| 5948 %} | |
| 5949 | |
| 5950 // Integer ALU0 reg-mem operation | |
| 5951 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ | |
| 5952 single_instruction; | |
| 5953 dst : S5(write); | |
| 5954 mem : S3(read); | |
| 5955 D0 : S0; // big decoder only | |
| 5956 ALU0 : S4; // ALU0 only | |
| 5957 MEM : S3; // any mem | |
| 5958 %} | |
| 5959 | |
| 5960 // Integer ALU reg-reg operation | |
| 5961 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ | |
| 5962 single_instruction; | |
| 5963 cr : S4(write); | |
| 5964 src1 : S3(read); | |
| 5965 src2 : S3(read); | |
| 5966 DECODE : S0; // any decoder | |
| 5967 ALU : S3; // any alu | |
| 5968 %} | |
| 5969 | |
| 5970 // Integer ALU reg-imm operation | |
| 5971 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ | |
| 5972 single_instruction; | |
| 5973 cr : S4(write); | |
| 5974 src1 : S3(read); | |
| 5975 DECODE : S0; // any decoder | |
| 5976 ALU : S3; // any alu | |
| 5977 %} | |
| 5978 | |
| 5979 // Integer ALU reg-mem operation | |
| 5980 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ | |
| 5981 single_instruction; | |
| 5982 cr : S4(write); | |
| 5983 src1 : S3(read); | |
| 5984 src2 : S3(read); | |
| 5985 D0 : S0; // big decoder only | |
| 5986 ALU : S4; // any alu | |
| 5987 MEM : S3; | |
| 5988 %} | |
| 5989 | |
| 5990 // Conditional move reg-reg | |
| 5991 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ | |
| 5992 instruction_count(4); | |
| 5993 y : S4(read); | |
| 5994 q : S3(read); | |
| 5995 p : S3(read); | |
| 5996 DECODE : S0(4); // any decoder | |
| 5997 %} | |
| 5998 | |
| 5999 // Conditional move reg-reg | |
| 6000 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 6001 single_instruction; | |
| 6002 dst : S4(write); | |
| 6003 src : S3(read); | |
| 6004 cr : S3(read); | |
| 6005 DECODE : S0; // any decoder | |
| 6006 %} | |
| 6007 | |
| 6008 // Conditional move reg-mem | |
| 6009 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ | |
| 6010 single_instruction; | |
| 6011 dst : S4(write); | |
| 6012 src : S3(read); | |
| 6013 cr : S3(read); | |
| 6014 DECODE : S0; // any decoder | |
| 6015 MEM : S3; | |
| 6016 %} | |
| 6017 | |
| 6018 // Conditional move reg-reg long | |
| 6019 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 6020 single_instruction; | |
| 6021 dst : S4(write); | |
| 6022 src : S3(read); | |
| 6023 cr : S3(read); | |
| 6024 DECODE : S0(2); // any 2 decoders | |
| 6025 %} | |
| 6026 | |
| 6027 // Conditional move double reg-reg | |
| 6028 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ | |
| 6029 single_instruction; | |
| 6030 dst : S4(write); | |
| 6031 src : S3(read); | |
| 6032 cr : S3(read); | |
| 6033 DECODE : S0; // any decoder | |
| 6034 %} | |
| 6035 | |
| 6036 // Float reg-reg operation | |
| 6037 pipe_class fpu_reg(regD dst) %{ | |
| 6038 instruction_count(2); | |
| 6039 dst : S3(read); | |
| 6040 DECODE : S0(2); // any 2 decoders | |
| 6041 FPU : S3; | |
| 6042 %} | |
| 6043 | |
| 6044 // Float reg-reg operation | |
| 6045 pipe_class fpu_reg_reg(regD dst, regD src) %{ | |
| 6046 instruction_count(2); | |
| 6047 dst : S4(write); | |
| 6048 src : S3(read); | |
| 6049 DECODE : S0(2); // any 2 decoders | |
| 6050 FPU : S3; | |
| 6051 %} | |
| 6052 | |
| 6053 // Float reg-reg operation | |
| 6054 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 6055 instruction_count(3); | |
| 6056 dst : S4(write); | |
| 6057 src1 : S3(read); | |
| 6058 src2 : S3(read); | |
| 6059 DECODE : S0(3); // any 3 decoders | |
| 6060 FPU : S3(2); | |
| 6061 %} | |
| 6062 | |
| 6063 // Float reg-reg operation | |
| 6064 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ | |
| 6065 instruction_count(4); | |
| 6066 dst : S4(write); | |
| 6067 src1 : S3(read); | |
| 6068 src2 : S3(read); | |
| 6069 src3 : S3(read); | |
| 6070 DECODE : S0(4); // any 3 decoders | |
| 6071 FPU : S3(2); | |
| 6072 %} | |
| 6073 | |
| 6074 // Float reg-reg operation | |
| 6075 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ | |
| 6076 instruction_count(4); | |
| 6077 dst : S4(write); | |
| 6078 src1 : S3(read); | |
| 6079 src2 : S3(read); | |
| 6080 src3 : S3(read); | |
| 6081 DECODE : S1(3); // any 3 decoders | |
| 6082 D0 : S0; // Big decoder only | |
| 6083 FPU : S3(2); | |
| 6084 MEM : S3; | |
| 6085 %} | |
| 6086 | |
| 6087 // Float reg-mem operation | |
| 6088 pipe_class fpu_reg_mem(regD dst, memory mem) %{ | |
| 6089 instruction_count(2); | |
| 6090 dst : S5(write); | |
| 6091 mem : S3(read); | |
| 6092 D0 : S0; // big decoder only | |
| 6093 DECODE : S1; // any decoder for FPU POP | |
| 6094 FPU : S4; | |
| 6095 MEM : S3; // any mem | |
| 6096 %} | |
| 6097 | |
| 6098 // Float reg-mem operation | |
| 6099 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ | |
| 6100 instruction_count(3); | |
| 6101 dst : S5(write); | |
| 6102 src1 : S3(read); | |
| 6103 mem : S3(read); | |
| 6104 D0 : S0; // big decoder only | |
| 6105 DECODE : S1(2); // any decoder for FPU POP | |
| 6106 FPU : S4; | |
| 6107 MEM : S3; // any mem | |
| 6108 %} | |
| 6109 | |
| 6110 // Float mem-reg operation | |
| 6111 pipe_class fpu_mem_reg(memory mem, regD src) %{ | |
| 6112 instruction_count(2); | |
| 6113 src : S5(read); | |
| 6114 mem : S3(read); | |
| 6115 DECODE : S0; // any decoder for FPU PUSH | |
| 6116 D0 : S1; // big decoder only | |
| 6117 FPU : S4; | |
| 6118 MEM : S3; // any mem | |
| 6119 %} | |
| 6120 | |
| 6121 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ | |
| 6122 instruction_count(3); | |
| 6123 src1 : S3(read); | |
| 6124 src2 : S3(read); | |
| 6125 mem : S3(read); | |
| 6126 DECODE : S0(2); // any decoder for FPU PUSH | |
| 6127 D0 : S1; // big decoder only | |
| 6128 FPU : S4; | |
| 6129 MEM : S3; // any mem | |
| 6130 %} | |
| 6131 | |
| 6132 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ | |
| 6133 instruction_count(3); | |
| 6134 src1 : S3(read); | |
| 6135 src2 : S3(read); | |
| 6136 mem : S4(read); | |
| 6137 DECODE : S0; // any decoder for FPU PUSH | |
| 6138 D0 : S0(2); // big decoder only | |
| 6139 FPU : S4; | |
| 6140 MEM : S3(2); // any mem | |
| 6141 %} | |
| 6142 | |
| 6143 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 6144 instruction_count(2); | |
| 6145 src1 : S3(read); | |
| 6146 dst : S4(read); | |
| 6147 D0 : S0(2); // big decoder only | |
| 6148 MEM : S3(2); // any mem | |
| 6149 %} | |
| 6150 | |
| 6151 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 6152 instruction_count(3); | |
| 6153 src1 : S3(read); | |
| 6154 src2 : S3(read); | |
| 6155 dst : S4(read); | |
| 6156 D0 : S0(3); // big decoder only | |
| 6157 FPU : S4; | |
| 6158 MEM : S3(3); // any mem | |
| 6159 %} | |
| 6160 | |
| 6161 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ | |
| 6162 instruction_count(3); | |
| 6163 src1 : S4(read); | |
| 6164 mem : S4(read); | |
| 6165 DECODE : S0; // any decoder for FPU PUSH | |
| 6166 D0 : S0(2); // big decoder only | |
| 6167 FPU : S4; | |
| 6168 MEM : S3(2); // any mem | |
| 6169 %} | |
| 6170 | |
| 6171 // Float load constant | |
| 6172 pipe_class fpu_reg_con(regD dst) %{ | |
| 6173 instruction_count(2); | |
| 6174 dst : S5(write); | |
| 6175 D0 : S0; // big decoder only for the load | |
| 6176 DECODE : S1; // any decoder for FPU POP | |
| 6177 FPU : S4; | |
| 6178 MEM : S3; // any mem | |
| 6179 %} | |
| 6180 | |
| 6181 // Float load constant | |
| 6182 pipe_class fpu_reg_reg_con(regD dst, regD src) %{ | |
| 6183 instruction_count(3); | |
| 6184 dst : S5(write); | |
| 6185 src : S3(read); | |
| 6186 D0 : S0; // big decoder only for the load | |
| 6187 DECODE : S1(2); // any decoder for FPU POP | |
| 6188 FPU : S4; | |
| 6189 MEM : S3; // any mem | |
| 6190 %} | |
| 6191 | |
| 6192 // UnConditional branch | |
| 6193 pipe_class pipe_jmp( label labl ) %{ | |
| 6194 single_instruction; | |
| 6195 BR : S3; | |
| 6196 %} | |
| 6197 | |
| 6198 // Conditional branch | |
| 6199 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 6200 single_instruction; | |
| 6201 cr : S1(read); | |
| 6202 BR : S3; | |
| 6203 %} | |
| 6204 | |
| 6205 // Allocation idiom | |
| 6206 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 6207 instruction_count(1); force_serialization; | |
| 6208 fixed_latency(6); | |
| 6209 heap_ptr : S3(read); | |
| 6210 DECODE : S0(3); | |
| 6211 D0 : S2; | |
| 6212 MEM : S3; | |
| 6213 ALU : S3(2); | |
| 6214 dst : S5(write); | |
| 6215 BR : S5; | |
| 6216 %} | |
| 6217 | |
| 6218 // Generic big/slow expanded idiom | |
| 6219 pipe_class pipe_slow( ) %{ | |
| 6220 instruction_count(10); multiple_bundles; force_serialization; | |
| 6221 fixed_latency(100); | |
| 6222 D0 : S0(2); | |
| 6223 MEM : S3(2); | |
| 6224 %} | |
| 6225 | |
| 6226 // The real do-nothing guy | |
| 6227 pipe_class empty( ) %{ | |
| 6228 instruction_count(0); | |
| 6229 %} | |
| 6230 | |
| 6231 // Define the class for the Nop node | |
| 6232 define %{ | |
| 6233 MachNop = empty; | |
| 6234 %} | |
| 6235 | |
| 6236 %} | |
| 6237 | |
| 6238 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6239 // | |
| 6240 // match -- States which machine-independent subtree may be replaced | |
| 6241 // by this instruction. | |
| 6242 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6243 // selection to identify a minimum cost tree of machine | |
| 6244 // instructions that matches a tree of machine-independent | |
| 6245 // instructions. | |
| 6246 // format -- A string providing the disassembly for this instruction. | |
| 6247 // The value of an instruction's operand may be inserted | |
| 6248 // by referring to it with a '$' prefix. | |
| 6249 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6250 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6251 // respectively. The primary opcode is commonly used to | |
| 6252 // indicate the type of machine instruction, while secondary | |
| 6253 // and tertiary are often used for prefix options or addressing | |
| 6254 // modes. | |
| 6255 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6256 // name must have been defined in an 'enc_class' specification | |
| 6257 // in the encode section of the architecture description. | |
| 6258 | |
| 6259 //----------BSWAP-Instruction-------------------------------------------------- | |
| 6260 instruct bytes_reverse_int(eRegI dst) %{ | |
| 6261 match(Set dst (ReverseBytesI dst)); | |
| 6262 | |
| 6263 format %{ "BSWAP $dst" %} | |
| 6264 opcode(0x0F, 0xC8); | |
| 6265 ins_encode( OpcP, OpcSReg(dst) ); | |
| 6266 ins_pipe( ialu_reg ); | |
| 6267 %} | |
| 6268 | |
| 6269 instruct bytes_reverse_long(eRegL dst) %{ | |
| 6270 match(Set dst (ReverseBytesL dst)); | |
| 6271 | |
| 6272 format %{ "BSWAP $dst.lo\n\t" | |
| 6273 "BSWAP $dst.hi\n\t" | |
| 6274 "XCHG $dst.lo $dst.hi" %} | |
| 6275 | |
| 6276 ins_cost(125); | |
| 6277 ins_encode( bswap_long_bytes(dst) ); | |
| 6278 ins_pipe( ialu_reg_reg); | |
| 6279 %} | |
| 6280 | |
|
1396
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6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6281 instruct bytes_reverse_unsigned_short(eRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
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parents:
1274
diff
changeset
|
6282 match(Set dst (ReverseBytesUS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6283 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6284 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6285 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6286 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6287 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6288 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6289 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6290 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6291 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6292 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6293 instruct bytes_reverse_short(eRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6294 match(Set dst (ReverseBytesS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6295 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6296 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6297 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6298 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6299 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6300 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6301 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6302 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6303 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6304 |
| 0 | 6305 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6306 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6307 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6308 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6309 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6310 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6311 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6312 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6313 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6314 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6315 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6316 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6317 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6318 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6319 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6320 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6321 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6322 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6323 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6324 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6325 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6326 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6327 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6328 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6329 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6330 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6331 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6332 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6333 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6334 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6335 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6336 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6337 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6338 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6339 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6340 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6341 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6342 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6343 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6344 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6345 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6346 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6347 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6348 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6349 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6350 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6351 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6352 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6353 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6354 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6355 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6356 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6357 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6358 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6359 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6360 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6361 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6362 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6363 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6364 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6365 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6366 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6367 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6368 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6369 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6370 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6371 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6372 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6373 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6374 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6375 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6376 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6377 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6378 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6379 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6380 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6381 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6382 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6383 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6384 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6385 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6386 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6387 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6388 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6389 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6390 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6391 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6392 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6393 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6394 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6395 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6396 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6397 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6398 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6399 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6400 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6401 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6402 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6403 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6404 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6405 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6406 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6407 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6408 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6409 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6410 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6411 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6412 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6413 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6414 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6415 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6416 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6417 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6418 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6419 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6420 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6421 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6422 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6423 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6424 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6425 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6426 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6427 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6428 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6429 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6430 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6431 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6432 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6433 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6434 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6435 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6436 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6437 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6438 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6439 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6440 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6441 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6442 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6443 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6444 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6445 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6446 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6447 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6448 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6449 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6450 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6451 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6452 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6453 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6454 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6455 instruct popCountI(eRegI dst, eRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6456 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6457 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6458 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6459 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6460 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6461 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6462 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6463 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6464 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6465 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6466 instruct popCountI_mem(eRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6467 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6468 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6469 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6470 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6471 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6472 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6473 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6474 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6475 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6476 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6477 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6478 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6479 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6480 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6481 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6482 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6483 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6484 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6485 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6486 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6487 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6488 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6489 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6490 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6491 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6492 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6493 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6494 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6495 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6496 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6497 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6498 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6499 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6500 format %{ "POPCNT $dst, $mem\n\t" |
|
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|
6501 "POPCNT $tmp, $mem+4\n\t" |
|
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|
6502 "ADD $dst, $tmp" %} |
|
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|
6503 ins_encode %{ |
|
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|
6504 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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|
6505 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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|
6506 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); |
|
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|
6507 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); |
|
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|
6508 __ addl($dst$$Register, $tmp$$Register); |
|
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|
6509 %} |
|
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|
6510 ins_pipe(ialu_reg); |
|
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|
6511 %} |
|
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|
6512 |
|
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|
6513 |
| 0 | 6514 //----------Load/Store/Move Instructions--------------------------------------- |
| 6515 //----------Load Instructions-------------------------------------------------- | |
| 6516 // Load Byte (8bit signed) | |
| 6517 instruct loadB(xRegI dst, memory mem) %{ | |
| 6518 match(Set dst (LoadB mem)); | |
| 6519 | |
| 6520 ins_cost(125); | |
| 624 | 6521 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 6522 | |
| 6523 ins_encode %{ | |
| 6524 __ movsbl($dst$$Register, $mem$$Address); | |
| 6525 %} | |
| 6526 | |
| 6527 ins_pipe(ialu_reg_mem); | |
| 6528 %} | |
| 6529 | |
| 6530 // Load Byte (8bit signed) into Long Register | |
| 824 | 6531 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6532 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 6533 effect(KILL cr); |
| 624 | 6534 |
| 6535 ins_cost(375); | |
| 6536 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 6537 "MOV $dst.hi,$dst.lo\n\t" | |
| 6538 "SAR $dst.hi,7" %} | |
| 6539 | |
| 6540 ins_encode %{ | |
| 6541 __ movsbl($dst$$Register, $mem$$Address); | |
| 6542 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6543 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 6544 %} | |
| 6545 | |
| 6546 ins_pipe(ialu_reg_mem); | |
| 6547 %} | |
| 6548 | |
| 6549 // Load Unsigned Byte (8bit UNsigned) | |
| 6550 instruct loadUB(xRegI dst, memory mem) %{ | |
| 6551 match(Set dst (LoadUB mem)); | |
| 0 | 6552 |
| 6553 ins_cost(125); | |
| 624 | 6554 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 6555 | |
| 6556 ins_encode %{ | |
| 6557 __ movzbl($dst$$Register, $mem$$Address); | |
| 6558 %} | |
| 6559 | |
| 6560 ins_pipe(ialu_reg_mem); | |
| 6561 %} | |
| 6562 | |
| 6563 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 6564 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6565 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 6566 effect(KILL cr); |
| 624 | 6567 |
| 6568 ins_cost(250); | |
| 6569 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 6570 "XOR $dst.hi,$dst.hi" %} | |
| 6571 | |
| 6572 ins_encode %{ | |
| 824 | 6573 Register Rdst = $dst$$Register; |
| 6574 __ movzbl(Rdst, $mem$$Address); | |
| 6575 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6576 %} | |
| 6577 | |
| 6578 ins_pipe(ialu_reg_mem); | |
| 6579 %} | |
| 6580 | |
| 6581 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 6582 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 6583 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 6584 effect(KILL cr); | |
| 6585 | |
| 6586 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 6587 "XOR $dst.hi,$dst.hi\n\t" | |
| 6588 "AND $dst.lo,$mask" %} | |
| 6589 ins_encode %{ | |
| 6590 Register Rdst = $dst$$Register; | |
| 6591 __ movzbl(Rdst, $mem$$Address); | |
| 6592 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6593 __ andl(Rdst, $mask$$constant); | |
| 6594 %} | |
| 624 | 6595 ins_pipe(ialu_reg_mem); |
| 6596 %} | |
| 6597 | |
| 6598 // Load Short (16bit signed) | |
| 6599 instruct loadS(eRegI dst, memory mem) %{ | |
| 6600 match(Set dst (LoadS mem)); | |
| 6601 | |
| 6602 ins_cost(125); | |
| 6603 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 6604 | |
| 6605 ins_encode %{ | |
| 6606 __ movswl($dst$$Register, $mem$$Address); | |
| 6607 %} | |
| 6608 | |
| 6609 ins_pipe(ialu_reg_mem); | |
| 6610 %} | |
| 6611 | |
| 785 | 6612 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 6613 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6614 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 6615 | |
| 6616 ins_cost(125); | |
| 6617 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 6618 ins_encode %{ | |
| 6619 __ movsbl($dst$$Register, $mem$$Address); | |
| 6620 %} | |
| 6621 ins_pipe(ialu_reg_mem); | |
| 6622 %} | |
| 6623 | |
| 624 | 6624 // Load Short (16bit signed) into Long Register |
| 824 | 6625 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6626 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 6627 effect(KILL cr); |
| 624 | 6628 |
| 6629 ins_cost(375); | |
| 6630 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 6631 "MOV $dst.hi,$dst.lo\n\t" | |
| 6632 "SAR $dst.hi,15" %} | |
| 6633 | |
| 6634 ins_encode %{ | |
| 6635 __ movswl($dst$$Register, $mem$$Address); | |
| 6636 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6637 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 6638 %} | |
| 6639 | |
| 6640 ins_pipe(ialu_reg_mem); | |
| 0 | 6641 %} |
| 6642 | |
|
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|
6643 // Load Unsigned Short/Char (16bit unsigned) |
|
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|
6644 instruct loadUS(eRegI dst, memory mem) %{ |
|
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|
6645 match(Set dst (LoadUS mem)); |
| 0 | 6646 |
| 6647 ins_cost(125); | |
| 624 | 6648 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 6649 | |
| 6650 ins_encode %{ | |
| 6651 __ movzwl($dst$$Register, $mem$$Address); | |
| 6652 %} | |
| 6653 | |
| 6654 ins_pipe(ialu_reg_mem); | |
| 6655 %} | |
| 6656 | |
| 785 | 6657 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 6658 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6659 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 6660 | |
| 6661 ins_cost(125); | |
| 6662 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 6663 ins_encode %{ | |
| 6664 __ movsbl($dst$$Register, $mem$$Address); | |
| 6665 %} | |
| 6666 ins_pipe(ialu_reg_mem); | |
| 6667 %} | |
| 6668 | |
| 624 | 6669 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 6670 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6671 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 6672 effect(KILL cr); |
| 624 | 6673 |
| 6674 ins_cost(250); | |
| 6675 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 6676 "XOR $dst.hi,$dst.hi" %} | |
| 6677 | |
| 6678 ins_encode %{ | |
| 6679 __ movzwl($dst$$Register, $mem$$Address); | |
| 6680 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6681 %} | |
| 6682 | |
| 6683 ins_pipe(ialu_reg_mem); | |
| 0 | 6684 %} |
| 6685 | |
| 824 | 6686 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 6687 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6688 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6689 effect(KILL cr); | |
| 6690 | |
| 6691 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 6692 "XOR $dst.hi,$dst.hi" %} | |
| 6693 ins_encode %{ | |
| 6694 Register Rdst = $dst$$Register; | |
| 6695 __ movzbl(Rdst, $mem$$Address); | |
| 6696 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6697 %} | |
| 6698 ins_pipe(ialu_reg_mem); | |
| 6699 %} | |
| 6700 | |
| 6701 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 6702 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 6703 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6704 effect(KILL cr); | |
| 6705 | |
| 6706 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6707 "XOR $dst.hi,$dst.hi\n\t" | |
| 6708 "AND $dst.lo,$mask" %} | |
| 6709 ins_encode %{ | |
| 6710 Register Rdst = $dst$$Register; | |
| 6711 __ movzwl(Rdst, $mem$$Address); | |
| 6712 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6713 __ andl(Rdst, $mask$$constant); | |
| 6714 %} | |
| 6715 ins_pipe(ialu_reg_mem); | |
| 6716 %} | |
| 6717 | |
| 0 | 6718 // Load Integer |
| 6719 instruct loadI(eRegI dst, memory mem) %{ | |
| 6720 match(Set dst (LoadI mem)); | |
| 6721 | |
| 6722 ins_cost(125); | |
| 624 | 6723 format %{ "MOV $dst,$mem\t# int" %} |
| 6724 | |
| 6725 ins_encode %{ | |
| 6726 __ movl($dst$$Register, $mem$$Address); | |
| 6727 %} | |
| 6728 | |
| 6729 ins_pipe(ialu_reg_mem); | |
| 6730 %} | |
| 6731 | |
| 785 | 6732 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6733 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6734 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6735 | |
| 6736 ins_cost(125); | |
| 6737 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6738 ins_encode %{ | |
| 6739 __ movsbl($dst$$Register, $mem$$Address); | |
| 6740 %} | |
| 6741 ins_pipe(ialu_reg_mem); | |
| 6742 %} | |
| 6743 | |
| 6744 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6745 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ | |
| 6746 match(Set dst (AndI (LoadI mem) mask)); | |
| 6747 | |
| 6748 ins_cost(125); | |
| 6749 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6750 ins_encode %{ | |
| 6751 __ movzbl($dst$$Register, $mem$$Address); | |
| 6752 %} | |
| 6753 ins_pipe(ialu_reg_mem); | |
| 6754 %} | |
| 6755 | |
| 6756 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6757 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6758 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6759 | |
| 6760 ins_cost(125); | |
| 6761 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6762 ins_encode %{ | |
| 6763 __ movswl($dst$$Register, $mem$$Address); | |
| 6764 %} | |
| 6765 ins_pipe(ialu_reg_mem); | |
| 6766 %} | |
| 6767 | |
| 6768 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6769 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ | |
| 6770 match(Set dst (AndI (LoadI mem) mask)); | |
| 6771 | |
| 6772 ins_cost(125); | |
| 6773 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6774 ins_encode %{ | |
| 6775 __ movzwl($dst$$Register, $mem$$Address); | |
| 6776 %} | |
| 6777 ins_pipe(ialu_reg_mem); | |
| 6778 %} | |
| 6779 | |
| 624 | 6780 // Load Integer into Long Register |
| 824 | 6781 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6782 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6783 effect(KILL cr); |
| 624 | 6784 |
| 6785 ins_cost(375); | |
| 6786 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6787 "MOV $dst.hi,$dst.lo\n\t" | |
| 6788 "SAR $dst.hi,31" %} | |
| 6789 | |
| 6790 ins_encode %{ | |
| 6791 __ movl($dst$$Register, $mem$$Address); | |
| 6792 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6793 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6794 %} | |
| 6795 | |
| 6796 ins_pipe(ialu_reg_mem); | |
| 6797 %} | |
| 6798 | |
| 824 | 6799 // Load Integer with mask 0xFF into Long Register |
| 6800 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6801 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6802 effect(KILL cr); | |
| 6803 | |
| 6804 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6805 "XOR $dst.hi,$dst.hi" %} | |
| 6806 ins_encode %{ | |
| 6807 Register Rdst = $dst$$Register; | |
| 6808 __ movzbl(Rdst, $mem$$Address); | |
| 6809 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6810 %} | |
| 6811 ins_pipe(ialu_reg_mem); | |
| 6812 %} | |
| 6813 | |
| 6814 // Load Integer with mask 0xFFFF into Long Register | |
| 6815 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6816 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6817 effect(KILL cr); | |
| 6818 | |
| 6819 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6820 "XOR $dst.hi,$dst.hi" %} | |
| 6821 ins_encode %{ | |
| 6822 Register Rdst = $dst$$Register; | |
| 6823 __ movzwl(Rdst, $mem$$Address); | |
| 6824 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6825 %} | |
| 6826 ins_pipe(ialu_reg_mem); | |
| 6827 %} | |
| 6828 | |
| 6829 // Load Integer with 32-bit mask into Long Register | |
| 6830 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6831 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6832 effect(KILL cr); | |
| 6833 | |
| 6834 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6835 "XOR $dst.hi,$dst.hi\n\t" | |
| 6836 "AND $dst.lo,$mask" %} | |
| 6837 ins_encode %{ | |
| 6838 Register Rdst = $dst$$Register; | |
| 6839 __ movl(Rdst, $mem$$Address); | |
| 6840 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6841 __ andl(Rdst, $mask$$constant); | |
| 6842 %} | |
| 6843 ins_pipe(ialu_reg_mem); | |
| 6844 %} | |
| 6845 | |
| 624 | 6846 // Load Unsigned Integer into Long Register |
| 824 | 6847 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6848 match(Set dst (LoadUI2L mem)); |
| 824 | 6849 effect(KILL cr); |
| 624 | 6850 |
| 6851 ins_cost(250); | |
| 6852 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6853 "XOR $dst.hi,$dst.hi" %} | |
| 6854 | |
| 6855 ins_encode %{ | |
| 6856 __ movl($dst$$Register, $mem$$Address); | |
| 6857 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6858 %} | |
| 6859 | |
| 6860 ins_pipe(ialu_reg_mem); | |
| 0 | 6861 %} |
| 6862 | |
| 6863 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6864 // register to ESI | |
| 6865 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6866 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6867 match(Set dst (LoadL mem)); | |
| 6868 | |
| 6869 ins_cost(250); | |
| 624 | 6870 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6871 "MOV $dst.hi,$mem+4" %} |
| 624 | 6872 |
| 6873 ins_encode %{ | |
| 6874 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); | |
| 6875 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); | |
| 6876 __ movl($dst$$Register, Amemlo); | |
| 6877 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6878 %} | |
| 6879 | |
| 6880 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6881 %} |
| 6882 | |
| 6883 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6884 // then store it down to the stack and reload on the int | |
| 6885 // side. | |
| 6886 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6887 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6888 match(Set dst (LoadL mem)); | |
| 6889 | |
| 6890 ins_cost(200); | |
| 6891 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6892 "FISTp $dst" %} | |
| 6893 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6894 ins_pipe( fpu_reg_mem ); | |
| 6895 %} | |
| 6896 | |
| 6897 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ | |
| 6898 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6899 match(Set dst (LoadL mem)); | |
| 6900 effect(TEMP tmp); | |
| 6901 ins_cost(180); | |
| 6902 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6903 "MOVSD $dst,$tmp" %} | |
| 6904 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 6905 ins_pipe( pipe_slow ); | |
| 6906 %} | |
| 6907 | |
| 6908 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ | |
| 6909 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6910 match(Set dst (LoadL mem)); | |
| 6911 effect(TEMP tmp); | |
| 6912 ins_cost(160); | |
| 6913 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6914 "MOVD $dst.lo,$tmp\n\t" | |
| 6915 "PSRLQ $tmp,32\n\t" | |
| 6916 "MOVD $dst.hi,$tmp" %} | |
| 6917 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 6918 ins_pipe( pipe_slow ); | |
| 6919 %} | |
| 6920 | |
| 6921 // Load Range | |
| 6922 instruct loadRange(eRegI dst, memory mem) %{ | |
| 6923 match(Set dst (LoadRange mem)); | |
| 6924 | |
| 6925 ins_cost(125); | |
| 6926 format %{ "MOV $dst,$mem" %} | |
| 6927 opcode(0x8B); | |
| 6928 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6929 ins_pipe( ialu_reg_mem ); | |
| 6930 %} | |
| 6931 | |
| 6932 | |
| 6933 // Load Pointer | |
| 6934 instruct loadP(eRegP dst, memory mem) %{ | |
| 6935 match(Set dst (LoadP mem)); | |
| 6936 | |
| 6937 ins_cost(125); | |
| 6938 format %{ "MOV $dst,$mem" %} | |
| 6939 opcode(0x8B); | |
| 6940 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6941 ins_pipe( ialu_reg_mem ); | |
| 6942 %} | |
| 6943 | |
| 6944 // Load Klass Pointer | |
| 6945 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6946 match(Set dst (LoadKlass mem)); | |
| 6947 | |
| 6948 ins_cost(125); | |
| 6949 format %{ "MOV $dst,$mem" %} | |
| 6950 opcode(0x8B); | |
| 6951 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6952 ins_pipe( ialu_reg_mem ); | |
| 6953 %} | |
| 6954 | |
| 6955 // Load Double | |
| 6956 instruct loadD(regD dst, memory mem) %{ | |
| 6957 predicate(UseSSE<=1); | |
| 6958 match(Set dst (LoadD mem)); | |
| 6959 | |
| 6960 ins_cost(150); | |
| 6961 format %{ "FLD_D ST,$mem\n\t" | |
| 6962 "FSTP $dst" %} | |
| 6963 opcode(0xDD); /* DD /0 */ | |
| 6964 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6965 Pop_Reg_D(dst) ); | |
| 6966 ins_pipe( fpu_reg_mem ); | |
| 6967 %} | |
| 6968 | |
| 6969 // Load Double to XMM | |
| 6970 instruct loadXD(regXD dst, memory mem) %{ | |
| 6971 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 6972 match(Set dst (LoadD mem)); | |
| 6973 ins_cost(145); | |
| 6974 format %{ "MOVSD $dst,$mem" %} | |
| 6975 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6976 ins_pipe( pipe_slow ); | |
| 6977 %} | |
| 6978 | |
| 6979 instruct loadXD_partial(regXD dst, memory mem) %{ | |
| 6980 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 6981 match(Set dst (LoadD mem)); | |
| 6982 ins_cost(145); | |
| 6983 format %{ "MOVLPD $dst,$mem" %} | |
| 6984 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); | |
| 6985 ins_pipe( pipe_slow ); | |
| 6986 %} | |
| 6987 | |
| 6988 // Load to XMM register (single-precision floating point) | |
| 6989 // MOVSS instruction | |
| 6990 instruct loadX(regX dst, memory mem) %{ | |
| 6991 predicate(UseSSE>=1); | |
| 6992 match(Set dst (LoadF mem)); | |
| 6993 ins_cost(145); | |
| 6994 format %{ "MOVSS $dst,$mem" %} | |
| 6995 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6996 ins_pipe( pipe_slow ); | |
| 6997 %} | |
| 6998 | |
| 6999 // Load Float | |
| 7000 instruct loadF(regF dst, memory mem) %{ | |
| 7001 predicate(UseSSE==0); | |
| 7002 match(Set dst (LoadF mem)); | |
| 7003 | |
| 7004 ins_cost(150); | |
| 7005 format %{ "FLD_S ST,$mem\n\t" | |
| 7006 "FSTP $dst" %} | |
| 7007 opcode(0xD9); /* D9 /0 */ | |
| 7008 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 7009 Pop_Reg_F(dst) ); | |
| 7010 ins_pipe( fpu_reg_mem ); | |
| 7011 %} | |
| 7012 | |
| 7013 // Load Aligned Packed Byte to XMM register | |
| 7014 instruct loadA8B(regXD dst, memory mem) %{ | |
| 7015 predicate(UseSSE>=1); | |
| 7016 match(Set dst (Load8B mem)); | |
| 7017 ins_cost(125); | |
| 7018 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 7019 ins_encode( movq_ld(dst, mem)); | |
| 7020 ins_pipe( pipe_slow ); | |
| 7021 %} | |
| 7022 | |
| 7023 // Load Aligned Packed Short to XMM register | |
| 7024 instruct loadA4S(regXD dst, memory mem) %{ | |
| 7025 predicate(UseSSE>=1); | |
| 7026 match(Set dst (Load4S mem)); | |
| 7027 ins_cost(125); | |
| 7028 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 7029 ins_encode( movq_ld(dst, mem)); | |
| 7030 ins_pipe( pipe_slow ); | |
| 7031 %} | |
| 7032 | |
| 7033 // Load Aligned Packed Char to XMM register | |
| 7034 instruct loadA4C(regXD dst, memory mem) %{ | |
| 7035 predicate(UseSSE>=1); | |
| 7036 match(Set dst (Load4C mem)); | |
| 7037 ins_cost(125); | |
| 7038 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 7039 ins_encode( movq_ld(dst, mem)); | |
| 7040 ins_pipe( pipe_slow ); | |
| 7041 %} | |
| 7042 | |
| 7043 // Load Aligned Packed Integer to XMM register | |
| 7044 instruct load2IU(regXD dst, memory mem) %{ | |
| 7045 predicate(UseSSE>=1); | |
| 7046 match(Set dst (Load2I mem)); | |
| 7047 ins_cost(125); | |
| 7048 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 7049 ins_encode( movq_ld(dst, mem)); | |
| 7050 ins_pipe( pipe_slow ); | |
| 7051 %} | |
| 7052 | |
| 7053 // Load Aligned Packed Single to XMM | |
| 7054 instruct loadA2F(regXD dst, memory mem) %{ | |
| 7055 predicate(UseSSE>=1); | |
| 7056 match(Set dst (Load2F mem)); | |
| 7057 ins_cost(145); | |
| 7058 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 7059 ins_encode( movq_ld(dst, mem)); | |
| 7060 ins_pipe( pipe_slow ); | |
| 7061 %} | |
| 7062 | |
| 7063 // Load Effective Address | |
| 7064 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 7065 match(Set dst mem); | |
| 7066 | |
| 7067 ins_cost(110); | |
| 7068 format %{ "LEA $dst,$mem" %} | |
| 7069 opcode(0x8D); | |
| 7070 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7071 ins_pipe( ialu_reg_reg_fat ); | |
| 7072 %} | |
| 7073 | |
| 7074 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 7075 match(Set dst mem); | |
| 7076 | |
| 7077 ins_cost(110); | |
| 7078 format %{ "LEA $dst,$mem" %} | |
| 7079 opcode(0x8D); | |
| 7080 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7081 ins_pipe( ialu_reg_reg_fat ); | |
| 7082 %} | |
| 7083 | |
| 7084 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 7085 match(Set dst mem); | |
| 7086 | |
| 7087 ins_cost(110); | |
| 7088 format %{ "LEA $dst,$mem" %} | |
| 7089 opcode(0x8D); | |
| 7090 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7091 ins_pipe( ialu_reg_reg_fat ); | |
| 7092 %} | |
| 7093 | |
| 7094 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 7095 match(Set dst mem); | |
| 7096 | |
| 7097 ins_cost(110); | |
| 7098 format %{ "LEA $dst,$mem" %} | |
| 7099 opcode(0x8D); | |
| 7100 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7101 ins_pipe( ialu_reg_reg_fat ); | |
| 7102 %} | |
| 7103 | |
| 7104 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 7105 match(Set dst mem); | |
| 7106 | |
| 7107 ins_cost(110); | |
| 7108 format %{ "LEA $dst,$mem" %} | |
| 7109 opcode(0x8D); | |
| 7110 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7111 ins_pipe( ialu_reg_reg_fat ); | |
| 7112 %} | |
| 7113 | |
| 7114 // Load Constant | |
| 7115 instruct loadConI(eRegI dst, immI src) %{ | |
| 7116 match(Set dst src); | |
| 7117 | |
| 7118 format %{ "MOV $dst,$src" %} | |
| 7119 ins_encode( LdImmI(dst, src) ); | |
| 7120 ins_pipe( ialu_reg_fat ); | |
| 7121 %} | |
| 7122 | |
| 7123 // Load Constant zero | |
| 7124 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ | |
| 7125 match(Set dst src); | |
| 7126 effect(KILL cr); | |
| 7127 | |
| 7128 ins_cost(50); | |
| 7129 format %{ "XOR $dst,$dst" %} | |
| 7130 opcode(0x33); /* + rd */ | |
| 7131 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 7132 ins_pipe( ialu_reg ); | |
| 7133 %} | |
| 7134 | |
| 7135 instruct loadConP(eRegP dst, immP src) %{ | |
| 7136 match(Set dst src); | |
| 7137 | |
| 7138 format %{ "MOV $dst,$src" %} | |
| 7139 opcode(0xB8); /* + rd */ | |
| 7140 ins_encode( LdImmP(dst, src) ); | |
| 7141 ins_pipe( ialu_reg_fat ); | |
| 7142 %} | |
| 7143 | |
| 7144 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 7145 match(Set dst src); | |
| 7146 effect(KILL cr); | |
| 7147 ins_cost(200); | |
| 7148 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 7149 "MOV $dst.hi,$src.hi" %} | |
| 7150 opcode(0xB8); | |
| 7151 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 7152 ins_pipe( ialu_reg_long_fat ); | |
| 7153 %} | |
| 7154 | |
| 7155 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 7156 match(Set dst src); | |
| 7157 effect(KILL cr); | |
| 7158 ins_cost(150); | |
| 7159 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 7160 "XOR $dst.hi,$dst.hi" %} | |
| 7161 opcode(0x33,0x33); | |
| 7162 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 7163 ins_pipe( ialu_reg_long ); | |
| 7164 %} | |
| 7165 | |
| 7166 // The instruction usage is guarded by predicate in operand immF(). | |
| 7167 instruct loadConF(regF dst, immF src) %{ | |
| 7168 match(Set dst src); | |
| 7169 ins_cost(125); | |
| 7170 | |
| 7171 format %{ "FLD_S ST,$src\n\t" | |
| 7172 "FSTP $dst" %} | |
| 7173 opcode(0xD9, 0x00); /* D9 /0 */ | |
| 7174 ins_encode(LdImmF(src), Pop_Reg_F(dst) ); | |
| 7175 ins_pipe( fpu_reg_con ); | |
| 7176 %} | |
| 7177 | |
| 7178 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7179 instruct loadConX(regX dst, immXF con) %{ | |
| 7180 match(Set dst con); | |
| 7181 ins_cost(125); | |
| 7182 format %{ "MOVSS $dst,[$con]" %} | |
| 7183 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con)); | |
| 7184 ins_pipe( pipe_slow ); | |
| 7185 %} | |
| 7186 | |
| 7187 // The instruction usage is guarded by predicate in operand immXF0(). | |
| 7188 instruct loadConX0(regX dst, immXF0 src) %{ | |
| 7189 match(Set dst src); | |
| 7190 ins_cost(100); | |
| 7191 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 7192 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 7193 ins_pipe( pipe_slow ); | |
| 7194 %} | |
| 7195 | |
| 7196 // The instruction usage is guarded by predicate in operand immD(). | |
| 7197 instruct loadConD(regD dst, immD src) %{ | |
| 7198 match(Set dst src); | |
| 7199 ins_cost(125); | |
| 7200 | |
| 7201 format %{ "FLD_D ST,$src\n\t" | |
| 7202 "FSTP $dst" %} | |
| 7203 ins_encode(LdImmD(src), Pop_Reg_D(dst) ); | |
| 7204 ins_pipe( fpu_reg_con ); | |
| 7205 %} | |
| 7206 | |
| 7207 // The instruction usage is guarded by predicate in operand immXD(). | |
| 7208 instruct loadConXD(regXD dst, immXD con) %{ | |
| 7209 match(Set dst con); | |
| 7210 ins_cost(125); | |
| 7211 format %{ "MOVSD $dst,[$con]" %} | |
| 7212 ins_encode(load_conXD(dst, con)); | |
| 7213 ins_pipe( pipe_slow ); | |
| 7214 %} | |
| 7215 | |
| 7216 // The instruction usage is guarded by predicate in operand immXD0(). | |
| 7217 instruct loadConXD0(regXD dst, immXD0 src) %{ | |
| 7218 match(Set dst src); | |
| 7219 ins_cost(100); | |
| 7220 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 7221 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 7222 ins_pipe( pipe_slow ); | |
| 7223 %} | |
| 7224 | |
| 7225 // Load Stack Slot | |
| 7226 instruct loadSSI(eRegI dst, stackSlotI src) %{ | |
| 7227 match(Set dst src); | |
| 7228 ins_cost(125); | |
| 7229 | |
| 7230 format %{ "MOV $dst,$src" %} | |
| 7231 opcode(0x8B); | |
| 7232 ins_encode( OpcP, RegMem(dst,src)); | |
| 7233 ins_pipe( ialu_reg_mem ); | |
| 7234 %} | |
| 7235 | |
| 7236 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 7237 match(Set dst src); | |
| 7238 | |
| 7239 ins_cost(200); | |
| 7240 format %{ "MOV $dst,$src.lo\n\t" | |
| 7241 "MOV $dst+4,$src.hi" %} | |
| 7242 opcode(0x8B, 0x8B); | |
| 7243 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 7244 ins_pipe( ialu_mem_long_reg ); | |
| 7245 %} | |
| 7246 | |
| 7247 // Load Stack Slot | |
| 7248 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 7249 match(Set dst src); | |
| 7250 ins_cost(125); | |
| 7251 | |
| 7252 format %{ "MOV $dst,$src" %} | |
| 7253 opcode(0x8B); | |
| 7254 ins_encode( OpcP, RegMem(dst,src)); | |
| 7255 ins_pipe( ialu_reg_mem ); | |
| 7256 %} | |
| 7257 | |
| 7258 // Load Stack Slot | |
| 7259 instruct loadSSF(regF dst, stackSlotF src) %{ | |
| 7260 match(Set dst src); | |
| 7261 ins_cost(125); | |
| 7262 | |
| 7263 format %{ "FLD_S $src\n\t" | |
| 7264 "FSTP $dst" %} | |
| 7265 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 7266 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7267 Pop_Reg_F(dst) ); | |
| 7268 ins_pipe( fpu_reg_mem ); | |
| 7269 %} | |
| 7270 | |
| 7271 // Load Stack Slot | |
| 7272 instruct loadSSD(regD dst, stackSlotD src) %{ | |
| 7273 match(Set dst src); | |
| 7274 ins_cost(125); | |
| 7275 | |
| 7276 format %{ "FLD_D $src\n\t" | |
| 7277 "FSTP $dst" %} | |
| 7278 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 7279 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7280 Pop_Reg_D(dst) ); | |
| 7281 ins_pipe( fpu_reg_mem ); | |
| 7282 %} | |
| 7283 | |
| 7284 // Prefetch instructions. | |
| 7285 // Must be safe to execute with invalid address (cannot fault). | |
| 7286 | |
| 7287 instruct prefetchr0( memory mem ) %{ | |
| 7288 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7289 match(PrefetchRead mem); | |
| 7290 ins_cost(0); | |
| 7291 size(0); | |
| 7292 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 7293 ins_encode(); | |
| 7294 ins_pipe(empty); | |
| 7295 %} | |
| 7296 | |
| 7297 instruct prefetchr( memory mem ) %{ | |
| 7298 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); | |
| 7299 match(PrefetchRead mem); | |
| 7300 ins_cost(100); | |
| 7301 | |
| 7302 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 7303 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ | |
| 7304 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7305 ins_pipe(ialu_mem); | |
| 7306 %} | |
| 7307 | |
| 7308 instruct prefetchrNTA( memory mem ) %{ | |
| 7309 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 7310 match(PrefetchRead mem); | |
| 7311 ins_cost(100); | |
| 7312 | |
| 7313 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 7314 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7315 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7316 ins_pipe(ialu_mem); | |
| 7317 %} | |
| 7318 | |
| 7319 instruct prefetchrT0( memory mem ) %{ | |
| 7320 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 7321 match(PrefetchRead mem); | |
| 7322 ins_cost(100); | |
| 7323 | |
| 7324 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 7325 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7326 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7327 ins_pipe(ialu_mem); | |
| 7328 %} | |
| 7329 | |
| 7330 instruct prefetchrT2( memory mem ) %{ | |
| 7331 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 7332 match(PrefetchRead mem); | |
| 7333 ins_cost(100); | |
| 7334 | |
| 7335 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 7336 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7337 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7338 ins_pipe(ialu_mem); | |
| 7339 %} | |
| 7340 | |
| 7341 instruct prefetchw0( memory mem ) %{ | |
| 7342 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7343 match(PrefetchWrite mem); | |
| 7344 ins_cost(0); | |
| 7345 size(0); | |
| 7346 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 7347 ins_encode(); | |
| 7348 ins_pipe(empty); | |
| 7349 %} | |
| 7350 | |
| 7351 instruct prefetchw( memory mem ) %{ | |
| 7352 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); | |
| 7353 match( PrefetchWrite mem ); | |
| 7354 ins_cost(100); | |
| 7355 | |
| 7356 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 7357 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 7358 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7359 ins_pipe(ialu_mem); | |
| 7360 %} | |
| 7361 | |
| 7362 instruct prefetchwNTA( memory mem ) %{ | |
| 7363 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 7364 match(PrefetchWrite mem); | |
| 7365 ins_cost(100); | |
| 7366 | |
| 7367 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 7368 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7369 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7370 ins_pipe(ialu_mem); | |
| 7371 %} | |
| 7372 | |
| 7373 instruct prefetchwT0( memory mem ) %{ | |
| 7374 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 7375 match(PrefetchWrite mem); | |
| 7376 ins_cost(100); | |
| 7377 | |
| 7378 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} | |
| 7379 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7380 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7381 ins_pipe(ialu_mem); | |
| 7382 %} | |
| 7383 | |
| 7384 instruct prefetchwT2( memory mem ) %{ | |
| 7385 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 7386 match(PrefetchWrite mem); | |
| 7387 ins_cost(100); | |
| 7388 | |
| 7389 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} | |
| 7390 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7391 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7392 ins_pipe(ialu_mem); | |
| 7393 %} | |
| 7394 | |
| 7395 //----------Store Instructions------------------------------------------------- | |
| 7396 | |
| 7397 // Store Byte | |
| 7398 instruct storeB(memory mem, xRegI src) %{ | |
| 7399 match(Set mem (StoreB mem src)); | |
| 7400 | |
| 7401 ins_cost(125); | |
| 7402 format %{ "MOV8 $mem,$src" %} | |
| 7403 opcode(0x88); | |
| 7404 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7405 ins_pipe( ialu_mem_reg ); | |
| 7406 %} | |
| 7407 | |
| 7408 // Store Char/Short | |
| 7409 instruct storeC(memory mem, eRegI src) %{ | |
| 7410 match(Set mem (StoreC mem src)); | |
| 7411 | |
| 7412 ins_cost(125); | |
| 7413 format %{ "MOV16 $mem,$src" %} | |
| 7414 opcode(0x89, 0x66); | |
| 7415 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 7416 ins_pipe( ialu_mem_reg ); | |
| 7417 %} | |
| 7418 | |
| 7419 // Store Integer | |
| 7420 instruct storeI(memory mem, eRegI src) %{ | |
| 7421 match(Set mem (StoreI mem src)); | |
| 7422 | |
| 7423 ins_cost(125); | |
| 7424 format %{ "MOV $mem,$src" %} | |
| 7425 opcode(0x89); | |
| 7426 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7427 ins_pipe( ialu_mem_reg ); | |
| 7428 %} | |
| 7429 | |
| 7430 // Store Long | |
| 7431 instruct storeL(long_memory mem, eRegL src) %{ | |
| 7432 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 7433 match(Set mem (StoreL mem src)); | |
| 7434 | |
| 7435 ins_cost(200); | |
| 7436 format %{ "MOV $mem,$src.lo\n\t" | |
| 7437 "MOV $mem+4,$src.hi" %} | |
| 7438 opcode(0x89, 0x89); | |
| 7439 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 7440 ins_pipe( ialu_mem_long_reg ); | |
| 7441 %} | |
| 7442 | |
| 824 | 7443 // Store Long to Integer |
| 7444 instruct storeL2I(memory mem, eRegL src) %{ | |
| 7445 match(Set mem (StoreI mem (ConvL2I src))); | |
| 7446 | |
| 7447 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 7448 ins_encode %{ | |
| 7449 __ movl($mem$$Address, $src$$Register); | |
| 7450 %} | |
| 7451 ins_pipe(ialu_mem_reg); | |
| 7452 %} | |
| 7453 | |
| 0 | 7454 // Volatile Store Long. Must be atomic, so move it into |
| 7455 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 7456 // target address before the store (for null-ptr checks) | |
| 7457 // so the memory operand is used twice in the encoding. | |
| 7458 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 7459 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7460 match(Set mem (StoreL mem src)); | |
| 7461 effect( KILL cr ); | |
| 7462 ins_cost(400); | |
| 7463 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7464 "FILD $src\n\t" | |
| 7465 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 7466 opcode(0x3B); | |
| 7467 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 7468 ins_pipe( fpu_reg_mem ); | |
| 7469 %} | |
| 7470 | |
| 7471 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ | |
| 7472 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7473 match(Set mem (StoreL mem src)); | |
| 7474 effect( TEMP tmp, KILL cr ); | |
| 7475 ins_cost(380); | |
| 7476 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7477 "MOVSD $tmp,$src\n\t" | |
| 7478 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7479 opcode(0x3B); | |
| 7480 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); | |
| 7481 ins_pipe( pipe_slow ); | |
| 7482 %} | |
| 7483 | |
| 7484 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ | |
| 7485 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7486 match(Set mem (StoreL mem src)); | |
| 7487 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 7488 ins_cost(360); | |
| 7489 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7490 "MOVD $tmp,$src.lo\n\t" | |
| 7491 "MOVD $tmp2,$src.hi\n\t" | |
| 7492 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 7493 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7494 opcode(0x3B); | |
| 7495 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); | |
| 7496 ins_pipe( pipe_slow ); | |
| 7497 %} | |
| 7498 | |
| 7499 // Store Pointer; for storing unknown oops and raw pointers | |
| 7500 instruct storeP(memory mem, anyRegP src) %{ | |
| 7501 match(Set mem (StoreP mem src)); | |
| 7502 | |
| 7503 ins_cost(125); | |
| 7504 format %{ "MOV $mem,$src" %} | |
| 7505 opcode(0x89); | |
| 7506 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7507 ins_pipe( ialu_mem_reg ); | |
| 7508 %} | |
| 7509 | |
| 7510 // Store Integer Immediate | |
| 7511 instruct storeImmI(memory mem, immI src) %{ | |
| 7512 match(Set mem (StoreI mem src)); | |
| 7513 | |
| 7514 ins_cost(150); | |
| 7515 format %{ "MOV $mem,$src" %} | |
| 7516 opcode(0xC7); /* C7 /0 */ | |
| 7517 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7518 ins_pipe( ialu_mem_imm ); | |
| 7519 %} | |
| 7520 | |
| 7521 // Store Short/Char Immediate | |
| 7522 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 7523 predicate(UseStoreImmI16); | |
| 7524 match(Set mem (StoreC mem src)); | |
| 7525 | |
| 7526 ins_cost(150); | |
| 7527 format %{ "MOV16 $mem,$src" %} | |
| 7528 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7529 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 7530 ins_pipe( ialu_mem_imm ); | |
| 7531 %} | |
| 7532 | |
| 7533 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 7534 // need card-mark barriers. | |
| 7535 instruct storeImmP(memory mem, immP src) %{ | |
| 7536 match(Set mem (StoreP mem src)); | |
| 7537 | |
| 7538 ins_cost(150); | |
| 7539 format %{ "MOV $mem,$src" %} | |
| 7540 opcode(0xC7); /* C7 /0 */ | |
| 7541 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7542 ins_pipe( ialu_mem_imm ); | |
| 7543 %} | |
| 7544 | |
| 7545 // Store Byte Immediate | |
| 7546 instruct storeImmB(memory mem, immI8 src) %{ | |
| 7547 match(Set mem (StoreB mem src)); | |
| 7548 | |
| 7549 ins_cost(150); | |
| 7550 format %{ "MOV8 $mem,$src" %} | |
| 7551 opcode(0xC6); /* C6 /0 */ | |
| 7552 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7553 ins_pipe( ialu_mem_imm ); | |
| 7554 %} | |
| 7555 | |
| 7556 // Store Aligned Packed Byte XMM register to memory | |
| 7557 instruct storeA8B(memory mem, regXD src) %{ | |
| 7558 predicate(UseSSE>=1); | |
| 7559 match(Set mem (Store8B mem src)); | |
| 7560 ins_cost(145); | |
| 7561 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7562 ins_encode( movq_st(mem, src)); | |
| 7563 ins_pipe( pipe_slow ); | |
| 7564 %} | |
| 7565 | |
| 7566 // Store Aligned Packed Char/Short XMM register to memory | |
| 7567 instruct storeA4C(memory mem, regXD src) %{ | |
| 7568 predicate(UseSSE>=1); | |
| 7569 match(Set mem (Store4C mem src)); | |
| 7570 ins_cost(145); | |
| 7571 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7572 ins_encode( movq_st(mem, src)); | |
| 7573 ins_pipe( pipe_slow ); | |
| 7574 %} | |
| 7575 | |
| 7576 // Store Aligned Packed Integer XMM register to memory | |
| 7577 instruct storeA2I(memory mem, regXD src) %{ | |
| 7578 predicate(UseSSE>=1); | |
| 7579 match(Set mem (Store2I mem src)); | |
| 7580 ins_cost(145); | |
| 7581 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7582 ins_encode( movq_st(mem, src)); | |
| 7583 ins_pipe( pipe_slow ); | |
| 7584 %} | |
| 7585 | |
| 7586 // Store CMS card-mark Immediate | |
| 7587 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 7588 match(Set mem (StoreCM mem src)); | |
| 7589 | |
| 7590 ins_cost(150); | |
| 7591 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 7592 opcode(0xC6); /* C6 /0 */ | |
| 7593 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7594 ins_pipe( ialu_mem_imm ); | |
| 7595 %} | |
| 7596 | |
| 7597 // Store Double | |
| 7598 instruct storeD( memory mem, regDPR1 src) %{ | |
| 7599 predicate(UseSSE<=1); | |
| 7600 match(Set mem (StoreD mem src)); | |
| 7601 | |
| 7602 ins_cost(100); | |
| 7603 format %{ "FST_D $mem,$src" %} | |
| 7604 opcode(0xDD); /* DD /2 */ | |
| 7605 ins_encode( enc_FP_store(mem,src) ); | |
| 7606 ins_pipe( fpu_mem_reg ); | |
| 7607 %} | |
| 7608 | |
| 7609 // Store double does rounding on x86 | |
| 7610 instruct storeD_rounded( memory mem, regDPR1 src) %{ | |
| 7611 predicate(UseSSE<=1); | |
| 7612 match(Set mem (StoreD mem (RoundDouble src))); | |
| 7613 | |
| 7614 ins_cost(100); | |
| 7615 format %{ "FST_D $mem,$src\t# round" %} | |
| 7616 opcode(0xDD); /* DD /2 */ | |
| 7617 ins_encode( enc_FP_store(mem,src) ); | |
| 7618 ins_pipe( fpu_mem_reg ); | |
| 7619 %} | |
| 7620 | |
| 7621 // Store XMM register to memory (double-precision floating points) | |
| 7622 // MOVSD instruction | |
| 7623 instruct storeXD(memory mem, regXD src) %{ | |
| 7624 predicate(UseSSE>=2); | |
| 7625 match(Set mem (StoreD mem src)); | |
| 7626 ins_cost(95); | |
| 7627 format %{ "MOVSD $mem,$src" %} | |
| 7628 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7629 ins_pipe( pipe_slow ); | |
| 7630 %} | |
| 7631 | |
| 7632 // Store XMM register to memory (single-precision floating point) | |
| 7633 // MOVSS instruction | |
| 7634 instruct storeX(memory mem, regX src) %{ | |
| 7635 predicate(UseSSE>=1); | |
| 7636 match(Set mem (StoreF mem src)); | |
| 7637 ins_cost(95); | |
| 7638 format %{ "MOVSS $mem,$src" %} | |
| 7639 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7640 ins_pipe( pipe_slow ); | |
| 7641 %} | |
| 7642 | |
| 7643 // Store Aligned Packed Single Float XMM register to memory | |
| 7644 instruct storeA2F(memory mem, regXD src) %{ | |
| 7645 predicate(UseSSE>=1); | |
| 7646 match(Set mem (Store2F mem src)); | |
| 7647 ins_cost(145); | |
| 7648 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7649 ins_encode( movq_st(mem, src)); | |
| 7650 ins_pipe( pipe_slow ); | |
| 7651 %} | |
| 7652 | |
| 7653 // Store Float | |
| 7654 instruct storeF( memory mem, regFPR1 src) %{ | |
| 7655 predicate(UseSSE==0); | |
| 7656 match(Set mem (StoreF mem src)); | |
| 7657 | |
| 7658 ins_cost(100); | |
| 7659 format %{ "FST_S $mem,$src" %} | |
| 7660 opcode(0xD9); /* D9 /2 */ | |
| 7661 ins_encode( enc_FP_store(mem,src) ); | |
| 7662 ins_pipe( fpu_mem_reg ); | |
| 7663 %} | |
| 7664 | |
| 7665 // Store Float does rounding on x86 | |
| 7666 instruct storeF_rounded( memory mem, regFPR1 src) %{ | |
| 7667 predicate(UseSSE==0); | |
| 7668 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7669 | |
| 7670 ins_cost(100); | |
| 7671 format %{ "FST_S $mem,$src\t# round" %} | |
| 7672 opcode(0xD9); /* D9 /2 */ | |
| 7673 ins_encode( enc_FP_store(mem,src) ); | |
| 7674 ins_pipe( fpu_mem_reg ); | |
| 7675 %} | |
| 7676 | |
| 7677 // Store Float does rounding on x86 | |
| 7678 instruct storeF_Drounded( memory mem, regDPR1 src) %{ | |
| 7679 predicate(UseSSE<=1); | |
| 7680 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7681 | |
| 7682 ins_cost(100); | |
| 7683 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7684 opcode(0xD9); /* D9 /2 */ | |
| 7685 ins_encode( enc_FP_store(mem,src) ); | |
| 7686 ins_pipe( fpu_mem_reg ); | |
| 7687 %} | |
| 7688 | |
| 7689 // Store immediate Float value (it is faster than store from FPU register) | |
| 7690 // The instruction usage is guarded by predicate in operand immF(). | |
| 7691 instruct storeF_imm( memory mem, immF src) %{ | |
| 7692 match(Set mem (StoreF mem src)); | |
| 7693 | |
| 7694 ins_cost(50); | |
| 7695 format %{ "MOV $mem,$src\t# store float" %} | |
| 7696 opcode(0xC7); /* C7 /0 */ | |
| 7697 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7698 ins_pipe( ialu_mem_imm ); | |
| 7699 %} | |
| 7700 | |
| 7701 // Store immediate Float value (it is faster than store from XMM register) | |
| 7702 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7703 instruct storeX_imm( memory mem, immXF src) %{ | |
| 7704 match(Set mem (StoreF mem src)); | |
| 7705 | |
| 7706 ins_cost(50); | |
| 7707 format %{ "MOV $mem,$src\t# store float" %} | |
| 7708 opcode(0xC7); /* C7 /0 */ | |
| 7709 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); | |
| 7710 ins_pipe( ialu_mem_imm ); | |
| 7711 %} | |
| 7712 | |
| 7713 // Store Integer to stack slot | |
| 7714 instruct storeSSI(stackSlotI dst, eRegI src) %{ | |
| 7715 match(Set dst src); | |
| 7716 | |
| 7717 ins_cost(100); | |
| 7718 format %{ "MOV $dst,$src" %} | |
| 7719 opcode(0x89); | |
| 7720 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7721 ins_pipe( ialu_mem_reg ); | |
| 7722 %} | |
| 7723 | |
| 7724 // Store Integer to stack slot | |
| 7725 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7726 match(Set dst src); | |
| 7727 | |
| 7728 ins_cost(100); | |
| 7729 format %{ "MOV $dst,$src" %} | |
| 7730 opcode(0x89); | |
| 7731 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7732 ins_pipe( ialu_mem_reg ); | |
| 7733 %} | |
| 7734 | |
| 7735 // Store Long to stack slot | |
| 7736 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7737 match(Set dst src); | |
| 7738 | |
| 7739 ins_cost(200); | |
| 7740 format %{ "MOV $dst,$src.lo\n\t" | |
| 7741 "MOV $dst+4,$src.hi" %} | |
| 7742 opcode(0x89, 0x89); | |
| 7743 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7744 ins_pipe( ialu_mem_long_reg ); | |
| 7745 %} | |
| 7746 | |
| 7747 //----------MemBar Instructions----------------------------------------------- | |
| 7748 // Memory barrier flavors | |
| 7749 | |
| 7750 instruct membar_acquire() %{ | |
| 7751 match(MemBarAcquire); | |
| 7752 ins_cost(400); | |
| 7753 | |
| 7754 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7755 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7756 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7757 ins_pipe(empty); |
| 0 | 7758 %} |
| 7759 | |
| 7760 instruct membar_acquire_lock() %{ | |
| 7761 match(MemBarAcquire); | |
| 7762 predicate(Matcher::prior_fast_lock(n)); | |
| 7763 ins_cost(0); | |
| 7764 | |
| 7765 size(0); | |
| 7766 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7767 ins_encode( ); | |
| 7768 ins_pipe(empty); | |
| 7769 %} | |
| 7770 | |
| 7771 instruct membar_release() %{ | |
| 7772 match(MemBarRelease); | |
| 7773 ins_cost(400); | |
| 7774 | |
| 7775 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7776 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7777 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7778 ins_pipe(empty); |
| 0 | 7779 %} |
| 7780 | |
| 7781 instruct membar_release_lock() %{ | |
| 7782 match(MemBarRelease); | |
| 7783 predicate(Matcher::post_fast_unlock(n)); | |
| 7784 ins_cost(0); | |
| 7785 | |
| 7786 size(0); | |
| 7787 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7788 ins_encode( ); | |
| 7789 ins_pipe(empty); | |
| 7790 %} | |
| 7791 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7792 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7793 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7794 effect(KILL cr); |
| 0 | 7795 ins_cost(400); |
| 7796 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7797 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7798 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7799 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7800 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7801 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7802 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7803 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7804 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7805 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7806 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7807 %} |
| 0 | 7808 ins_pipe(pipe_slow); |
| 7809 %} | |
| 7810 | |
| 7811 instruct unnecessary_membar_volatile() %{ | |
| 7812 match(MemBarVolatile); | |
| 7813 predicate(Matcher::post_store_load_barrier(n)); | |
| 7814 ins_cost(0); | |
| 7815 | |
| 7816 size(0); | |
| 7817 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7818 ins_encode( ); | |
| 7819 ins_pipe(empty); | |
| 7820 %} | |
| 7821 | |
| 7822 //----------Move Instructions-------------------------------------------------- | |
| 7823 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7824 match(Set dst (CastX2P src)); | |
| 7825 format %{ "# X2P $dst, $src" %} | |
| 7826 ins_encode( /*empty encoding*/ ); | |
| 7827 ins_cost(0); | |
| 7828 ins_pipe(empty); | |
| 7829 %} | |
| 7830 | |
| 7831 instruct castP2X(eRegI dst, eRegP src ) %{ | |
| 7832 match(Set dst (CastP2X src)); | |
| 7833 ins_cost(50); | |
| 7834 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7835 ins_encode( enc_Copy( dst, src) ); | |
| 7836 ins_pipe( ialu_reg_reg ); | |
| 7837 %} | |
| 7838 | |
| 7839 //----------Conditional Move--------------------------------------------------- | |
| 7840 // Conditional move | |
| 7841 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7842 predicate(VM_Version::supports_cmov() ); | |
| 7843 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7844 ins_cost(200); | |
| 7845 format %{ "CMOV$cop $dst,$src" %} | |
| 7846 opcode(0x0F,0x40); | |
| 7847 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7848 ins_pipe( pipe_cmov_reg ); | |
| 7849 %} | |
| 7850 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7851 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ |
| 0 | 7852 predicate(VM_Version::supports_cmov() ); |
| 7853 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7854 ins_cost(200); | |
| 7855 format %{ "CMOV$cop $dst,$src" %} | |
| 7856 opcode(0x0F,0x40); | |
| 7857 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7858 ins_pipe( pipe_cmov_reg ); | |
| 7859 %} | |
| 7860 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7861 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7862 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7863 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7864 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7865 expand %{ |
|
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|
7866 cmovI_regU(cop, cr, dst, src); |
|
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diff
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|
7867 %} |
|
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diff
changeset
|
7868 %} |
|
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diff
changeset
|
7869 |
| 0 | 7870 // Conditional move |
| 7871 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ | |
| 7872 predicate(VM_Version::supports_cmov() ); | |
| 7873 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7874 ins_cost(250); | |
| 7875 format %{ "CMOV$cop $dst,$src" %} | |
| 7876 opcode(0x0F,0x40); | |
| 7877 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7878 ins_pipe( pipe_cmov_mem ); | |
| 7879 %} | |
| 7880 | |
| 7881 // Conditional move | |
|
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|
7882 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ |
| 0 | 7883 predicate(VM_Version::supports_cmov() ); |
| 7884 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7885 ins_cost(250); | |
| 7886 format %{ "CMOV$cop $dst,$src" %} | |
| 7887 opcode(0x0F,0x40); | |
| 7888 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7889 ins_pipe( pipe_cmov_mem ); | |
| 7890 %} | |
| 7891 | |
|
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|
7892 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ |
|
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changeset
|
7893 predicate(VM_Version::supports_cmov() ); |
|
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|
7894 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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|
7895 ins_cost(250); |
|
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diff
changeset
|
7896 expand %{ |
|
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diff
changeset
|
7897 cmovI_memU(cop, cr, dst, src); |
|
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|
7898 %} |
|
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|
7899 %} |
|
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|
7900 |
| 0 | 7901 // Conditional move |
| 7902 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7903 predicate(VM_Version::supports_cmov() ); | |
| 7904 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7905 ins_cost(200); | |
| 7906 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7907 opcode(0x0F,0x40); | |
| 7908 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7909 ins_pipe( pipe_cmov_reg ); | |
| 7910 %} | |
| 7911 | |
| 7912 // Conditional move (non-P6 version) | |
| 7913 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7914 // regardless of whether we are on a P6, so we | |
| 7915 // emulate a cmov here | |
| 7916 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7917 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7918 ins_cost(300); | |
| 7919 format %{ "Jn$cop skip\n\t" | |
| 7920 "MOV $dst,$src\t# pointer\n" | |
| 7921 "skip:" %} | |
| 7922 opcode(0x8b); | |
| 7923 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7924 ins_pipe( pipe_cmov_reg ); | |
| 7925 %} | |
| 7926 | |
| 7927 // Conditional move | |
|
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|
7928 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7929 predicate(VM_Version::supports_cmov() ); |
| 7930 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7931 ins_cost(200); | |
| 7932 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7933 opcode(0x0F,0x40); | |
| 7934 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7935 ins_pipe( pipe_cmov_reg ); | |
| 7936 %} | |
| 7937 | |
|
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|
7938 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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|
7939 predicate(VM_Version::supports_cmov() ); |
|
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|
7940 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
7941 ins_cost(200); |
|
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|
7942 expand %{ |
|
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changeset
|
7943 cmovP_regU(cop, cr, dst, src); |
|
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|
7944 %} |
|
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|
7945 %} |
|
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|
7946 |
| 0 | 7947 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7948 // correctly meets the two pointer arguments; one is an incoming | |
| 7949 // register but the other is a memory operand. ALSO appears to | |
| 7950 // be buggy with implicit null checks. | |
| 7951 // | |
| 7952 //// Conditional move | |
| 7953 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7954 // predicate(VM_Version::supports_cmov() ); | |
| 7955 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7956 // ins_cost(250); | |
| 7957 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7958 // opcode(0x0F,0x40); | |
| 7959 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7960 // ins_pipe( pipe_cmov_mem ); | |
| 7961 //%} | |
| 7962 // | |
| 7963 //// Conditional move | |
| 7964 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7965 // predicate(VM_Version::supports_cmov() ); | |
| 7966 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7967 // ins_cost(250); | |
| 7968 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7969 // opcode(0x0F,0x40); | |
| 7970 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7971 // ins_pipe( pipe_cmov_mem ); | |
| 7972 //%} | |
| 7973 | |
| 7974 // Conditional move | |
| 7975 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ | |
| 7976 predicate(UseSSE<=1); | |
| 7977 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7978 ins_cost(200); | |
| 7979 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7980 opcode(0xDA); | |
| 7981 ins_encode( enc_cmov_d(cop,src) ); | |
| 7982 ins_pipe( pipe_cmovD_reg ); | |
| 7983 %} | |
| 7984 | |
| 7985 // Conditional move | |
| 7986 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ | |
| 7987 predicate(UseSSE==0); | |
| 7988 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7989 ins_cost(200); | |
| 7990 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7991 opcode(0xDA); | |
| 7992 ins_encode( enc_cmov_d(cop,src) ); | |
| 7993 ins_pipe( pipe_cmovD_reg ); | |
| 7994 %} | |
| 7995 | |
| 7996 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 7997 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ | |
| 7998 predicate(UseSSE<=1); | |
| 7999 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8000 ins_cost(200); | |
| 8001 format %{ "Jn$cop skip\n\t" | |
| 8002 "MOV $dst,$src\t# double\n" | |
| 8003 "skip:" %} | |
| 8004 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8005 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); | |
| 8006 ins_pipe( pipe_cmovD_reg ); | |
| 8007 %} | |
| 8008 | |
| 8009 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 8010 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ | |
| 8011 predicate(UseSSE==0); | |
| 8012 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8013 ins_cost(200); | |
| 8014 format %{ "Jn$cop skip\n\t" | |
| 8015 "MOV $dst,$src\t# float\n" | |
| 8016 "skip:" %} | |
| 8017 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8018 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); | |
| 8019 ins_pipe( pipe_cmovD_reg ); | |
| 8020 %} | |
| 8021 | |
| 8022 // No CMOVE with SSE/SSE2 | |
| 8023 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ | |
| 8024 predicate (UseSSE>=1); | |
| 8025 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8026 ins_cost(200); | |
| 8027 format %{ "Jn$cop skip\n\t" | |
| 8028 "MOVSS $dst,$src\t# float\n" | |
| 8029 "skip:" %} | |
| 8030 ins_encode %{ | |
| 8031 Label skip; | |
| 8032 // Invert sense of branch from sense of CMOV | |
| 8033 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8034 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8035 __ bind(skip); | |
| 8036 %} | |
| 8037 ins_pipe( pipe_slow ); | |
| 8038 %} | |
| 8039 | |
| 8040 // No CMOVE with SSE/SSE2 | |
| 8041 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ | |
| 8042 predicate (UseSSE>=2); | |
| 8043 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8044 ins_cost(200); | |
| 8045 format %{ "Jn$cop skip\n\t" | |
| 8046 "MOVSD $dst,$src\t# float\n" | |
| 8047 "skip:" %} | |
| 8048 ins_encode %{ | |
| 8049 Label skip; | |
| 8050 // Invert sense of branch from sense of CMOV | |
| 8051 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8052 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8053 __ bind(skip); | |
| 8054 %} | |
| 8055 ins_pipe( pipe_slow ); | |
| 8056 %} | |
| 8057 | |
| 8058 // unsigned version | |
| 8059 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ | |
| 8060 predicate (UseSSE>=1); | |
| 8061 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8062 ins_cost(200); | |
| 8063 format %{ "Jn$cop skip\n\t" | |
| 8064 "MOVSS $dst,$src\t# float\n" | |
| 8065 "skip:" %} | |
| 8066 ins_encode %{ | |
| 8067 Label skip; | |
| 8068 // Invert sense of branch from sense of CMOV | |
| 8069 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8070 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8071 __ bind(skip); | |
| 8072 %} | |
| 8073 ins_pipe( pipe_slow ); | |
| 8074 %} | |
| 8075 | |
|
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|
8076 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{ |
|
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changeset
|
8077 predicate (UseSSE>=1); |
|
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diff
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|
8078 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
8079 ins_cost(200); |
|
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diff
changeset
|
8080 expand %{ |
|
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changeset
|
8081 fcmovX_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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|
8082 %} |
|
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diff
changeset
|
8083 %} |
|
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|
8084 |
| 0 | 8085 // unsigned version |
| 8086 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ | |
| 8087 predicate (UseSSE>=2); | |
| 8088 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8089 ins_cost(200); | |
| 8090 format %{ "Jn$cop skip\n\t" | |
| 8091 "MOVSD $dst,$src\t# float\n" | |
| 8092 "skip:" %} | |
| 8093 ins_encode %{ | |
| 8094 Label skip; | |
| 8095 // Invert sense of branch from sense of CMOV | |
| 8096 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8097 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8098 __ bind(skip); | |
| 8099 %} | |
| 8100 ins_pipe( pipe_slow ); | |
| 8101 %} | |
| 8102 | |
|
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|
8103 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
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changeset
|
8104 predicate (UseSSE>=2); |
|
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diff
changeset
|
8105 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
8106 ins_cost(200); |
|
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diff
changeset
|
8107 expand %{ |
|
4d9884b01ba6
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changeset
|
8108 fcmovXD_regU(cop, cr, dst, src); |
|
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changeset
|
8109 %} |
|
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diff
changeset
|
8110 %} |
|
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|
8111 |
| 0 | 8112 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 8113 predicate(VM_Version::supports_cmov() ); | |
| 8114 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8115 ins_cost(200); | |
| 8116 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8117 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8118 opcode(0x0F,0x40); | |
| 8119 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8120 ins_pipe( pipe_cmov_reg_long ); | |
| 8121 %} | |
| 8122 | |
| 8123 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 8124 predicate(VM_Version::supports_cmov() ); | |
| 8125 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8126 ins_cost(200); | |
| 8127 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8128 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8129 opcode(0x0F,0x40); | |
| 8130 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8131 ins_pipe( pipe_cmov_reg_long ); | |
| 8132 %} | |
| 8133 | |
|
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changeset
|
8134 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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diff
changeset
|
8135 predicate(VM_Version::supports_cmov() ); |
|
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diff
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|
8136 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
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|
8137 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
8138 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
8139 cmovL_regU(cop, cr, dst, src); |
|
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diff
changeset
|
8140 %} |
|
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diff
changeset
|
8141 %} |
|
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diff
changeset
|
8142 |
| 0 | 8143 //----------Arithmetic Instructions-------------------------------------------- |
| 8144 //----------Addition Instructions---------------------------------------------- | |
| 8145 // Integer Addition Instructions | |
| 8146 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8147 match(Set dst (AddI dst src)); | |
| 8148 effect(KILL cr); | |
| 8149 | |
| 8150 size(2); | |
| 8151 format %{ "ADD $dst,$src" %} | |
| 8152 opcode(0x03); | |
| 8153 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8154 ins_pipe( ialu_reg_reg ); | |
| 8155 %} | |
| 8156 | |
| 8157 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8158 match(Set dst (AddI dst src)); | |
| 8159 effect(KILL cr); | |
| 8160 | |
| 8161 format %{ "ADD $dst,$src" %} | |
| 8162 opcode(0x81, 0x00); /* /0 id */ | |
| 8163 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8164 ins_pipe( ialu_reg ); | |
| 8165 %} | |
| 8166 | |
| 8167 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 8168 predicate(UseIncDec); | |
| 8169 match(Set dst (AddI dst src)); | |
| 8170 effect(KILL cr); | |
| 8171 | |
| 8172 size(1); | |
| 8173 format %{ "INC $dst" %} | |
| 8174 opcode(0x40); /* */ | |
| 8175 ins_encode( Opc_plus( primary, dst ) ); | |
| 8176 ins_pipe( ialu_reg ); | |
| 8177 %} | |
| 8178 | |
| 8179 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ | |
| 8180 match(Set dst (AddI src0 src1)); | |
| 8181 ins_cost(110); | |
| 8182 | |
| 8183 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 8184 opcode(0x8D); /* 0x8D /r */ | |
| 8185 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8186 ins_pipe( ialu_reg_reg ); | |
| 8187 %} | |
| 8188 | |
| 8189 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 8190 match(Set dst (AddP src0 src1)); | |
| 8191 ins_cost(110); | |
| 8192 | |
| 8193 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 8194 opcode(0x8D); /* 0x8D /r */ | |
| 8195 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8196 ins_pipe( ialu_reg_reg ); | |
| 8197 %} | |
| 8198 | |
| 8199 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8200 predicate(UseIncDec); | |
| 8201 match(Set dst (AddI dst src)); | |
| 8202 effect(KILL cr); | |
| 8203 | |
| 8204 size(1); | |
| 8205 format %{ "DEC $dst" %} | |
| 8206 opcode(0x48); /* */ | |
| 8207 ins_encode( Opc_plus( primary, dst ) ); | |
| 8208 ins_pipe( ialu_reg ); | |
| 8209 %} | |
| 8210 | |
| 8211 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ | |
| 8212 match(Set dst (AddP dst src)); | |
| 8213 effect(KILL cr); | |
| 8214 | |
| 8215 size(2); | |
| 8216 format %{ "ADD $dst,$src" %} | |
| 8217 opcode(0x03); | |
| 8218 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8219 ins_pipe( ialu_reg_reg ); | |
| 8220 %} | |
| 8221 | |
| 8222 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 8223 match(Set dst (AddP dst src)); | |
| 8224 effect(KILL cr); | |
| 8225 | |
| 8226 format %{ "ADD $dst,$src" %} | |
| 8227 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 8228 // ins_encode( RegImm( dst, src) ); | |
| 8229 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8230 ins_pipe( ialu_reg ); | |
| 8231 %} | |
| 8232 | |
| 8233 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8234 match(Set dst (AddI dst (LoadI src))); | |
| 8235 effect(KILL cr); | |
| 8236 | |
| 8237 ins_cost(125); | |
| 8238 format %{ "ADD $dst,$src" %} | |
| 8239 opcode(0x03); | |
| 8240 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8241 ins_pipe( ialu_reg_mem ); | |
| 8242 %} | |
| 8243 | |
| 8244 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8245 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8246 effect(KILL cr); | |
| 8247 | |
| 8248 ins_cost(150); | |
| 8249 format %{ "ADD $dst,$src" %} | |
| 8250 opcode(0x01); /* Opcode 01 /r */ | |
| 8251 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8252 ins_pipe( ialu_mem_reg ); | |
| 8253 %} | |
| 8254 | |
| 8255 // Add Memory with Immediate | |
| 8256 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8257 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8258 effect(KILL cr); | |
| 8259 | |
| 8260 ins_cost(125); | |
| 8261 format %{ "ADD $dst,$src" %} | |
| 8262 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8263 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 8264 ins_pipe( ialu_mem_imm ); | |
| 8265 %} | |
| 8266 | |
| 8267 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 8268 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8269 effect(KILL cr); | |
| 8270 | |
| 8271 ins_cost(125); | |
| 8272 format %{ "INC $dst" %} | |
| 8273 opcode(0xFF); /* Opcode FF /0 */ | |
| 8274 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 8275 ins_pipe( ialu_mem_imm ); | |
| 8276 %} | |
| 8277 | |
| 8278 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8279 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8280 effect(KILL cr); | |
| 8281 | |
| 8282 ins_cost(125); | |
| 8283 format %{ "DEC $dst" %} | |
| 8284 opcode(0xFF); /* Opcode FF /1 */ | |
| 8285 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 8286 ins_pipe( ialu_mem_imm ); | |
| 8287 %} | |
| 8288 | |
| 8289 | |
| 8290 instruct checkCastPP( eRegP dst ) %{ | |
| 8291 match(Set dst (CheckCastPP dst)); | |
| 8292 | |
| 8293 size(0); | |
| 8294 format %{ "#checkcastPP of $dst" %} | |
| 8295 ins_encode( /*empty encoding*/ ); | |
| 8296 ins_pipe( empty ); | |
| 8297 %} | |
| 8298 | |
| 8299 instruct castPP( eRegP dst ) %{ | |
| 8300 match(Set dst (CastPP dst)); | |
| 8301 format %{ "#castPP of $dst" %} | |
| 8302 ins_encode( /*empty encoding*/ ); | |
| 8303 ins_pipe( empty ); | |
| 8304 %} | |
| 8305 | |
| 8306 instruct castII( eRegI dst ) %{ | |
| 8307 match(Set dst (CastII dst)); | |
| 8308 format %{ "#castII of $dst" %} | |
| 8309 ins_encode( /*empty encoding*/ ); | |
| 8310 ins_cost(0); | |
| 8311 ins_pipe( empty ); | |
| 8312 %} | |
| 8313 | |
| 8314 | |
| 8315 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 8316 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 8317 match(Set dst (LoadPLocked mem)); | |
| 8318 | |
| 8319 ins_cost(125); | |
| 8320 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 8321 opcode(0x8B); | |
| 8322 ins_encode( OpcP, RegMem(dst,mem)); | |
| 8323 ins_pipe( ialu_reg_mem ); | |
| 8324 %} | |
| 8325 | |
| 8326 // LoadLong-locked - same as a volatile long load when used with compare-swap | |
| 8327 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ | |
| 8328 predicate(UseSSE<=1); | |
| 8329 match(Set dst (LoadLLocked mem)); | |
| 8330 | |
| 8331 ins_cost(200); | |
| 8332 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 8333 "FISTp $dst" %} | |
| 8334 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 8335 ins_pipe( fpu_reg_mem ); | |
| 8336 %} | |
| 8337 | |
| 8338 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ | |
| 8339 predicate(UseSSE>=2); | |
| 8340 match(Set dst (LoadLLocked mem)); | |
| 8341 effect(TEMP tmp); | |
| 8342 ins_cost(180); | |
| 8343 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8344 "MOVSD $dst,$tmp" %} | |
| 8345 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 8346 ins_pipe( pipe_slow ); | |
| 8347 %} | |
| 8348 | |
| 8349 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ | |
| 8350 predicate(UseSSE>=2); | |
| 8351 match(Set dst (LoadLLocked mem)); | |
| 8352 effect(TEMP tmp); | |
| 8353 ins_cost(160); | |
| 8354 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8355 "MOVD $dst.lo,$tmp\n\t" | |
| 8356 "PSRLQ $tmp,32\n\t" | |
| 8357 "MOVD $dst.hi,$tmp" %} | |
| 8358 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 8359 ins_pipe( pipe_slow ); | |
| 8360 %} | |
| 8361 | |
| 8362 // Conditional-store of the updated heap-top. | |
| 8363 // Used during allocation of the shared heap. | |
| 8364 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8365 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 8366 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 8367 // EAX is killed if there is contention, but then it's also unused. | |
| 8368 // In the common case of no contention, EAX holds the new oop address. | |
| 8369 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 8370 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 8371 ins_pipe( pipe_cmpxchg ); | |
| 8372 %} | |
| 8373 | |
|
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8374 // Conditional-store of an int value. |
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8375 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
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8376 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ |
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8377 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
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8378 effect(KILL oldval); |
|
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8379 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
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8380 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 8381 ins_pipe( pipe_cmpxchg ); |
| 8382 %} | |
| 8383 | |
|
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8384 // Conditional-store of a long value. |
|
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8385 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
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8386 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
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8387 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
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8388 effect(KILL oldval); |
|
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8389 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
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8390 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
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8391 "XCHG EBX,ECX" |
|
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8392 %} |
|
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8393 ins_encode %{ |
|
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8394 // Note: we need to swap rbx, and rcx before and after the |
|
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8395 // cmpxchg8 instruction because the instruction uses |
|
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8396 // rcx as the high order word of the new value to store but |
|
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8397 // our register encoding uses rbx. |
|
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8398 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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8399 if( os::is_MP() ) |
|
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8400 __ lock(); |
| 624 | 8401 __ cmpxchg8($mem$$Address); |
|
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8402 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
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|
8403 %} |
| 0 | 8404 ins_pipe( pipe_cmpxchg ); |
| 8405 %} | |
| 8406 | |
| 8407 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 8408 | |
| 8409 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ | |
| 8410 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8411 effect(KILL cr, KILL oldval); | |
| 8412 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8413 "MOV $res,0\n\t" | |
| 8414 "JNE,s fail\n\t" | |
| 8415 "MOV $res,1\n" | |
| 8416 "fail:" %} | |
| 8417 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 8418 enc_flags_ne_to_boolean(res) ); | |
| 8419 ins_pipe( pipe_cmpxchg ); | |
| 8420 %} | |
| 8421 | |
| 8422 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ | |
| 8423 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8424 effect(KILL cr, KILL oldval); | |
| 8425 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8426 "MOV $res,0\n\t" | |
| 8427 "JNE,s fail\n\t" | |
| 8428 "MOV $res,1\n" | |
| 8429 "fail:" %} | |
| 8430 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8431 ins_pipe( pipe_cmpxchg ); | |
| 8432 %} | |
| 8433 | |
| 8434 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ | |
| 8435 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8436 effect(KILL cr, KILL oldval); | |
| 8437 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8438 "MOV $res,0\n\t" | |
| 8439 "JNE,s fail\n\t" | |
| 8440 "MOV $res,1\n" | |
| 8441 "fail:" %} | |
| 8442 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8443 ins_pipe( pipe_cmpxchg ); | |
| 8444 %} | |
| 8445 | |
| 8446 //----------Subtraction Instructions------------------------------------------- | |
| 8447 // Integer Subtraction Instructions | |
| 8448 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8449 match(Set dst (SubI dst src)); | |
| 8450 effect(KILL cr); | |
| 8451 | |
| 8452 size(2); | |
| 8453 format %{ "SUB $dst,$src" %} | |
| 8454 opcode(0x2B); | |
| 8455 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8456 ins_pipe( ialu_reg_reg ); | |
| 8457 %} | |
| 8458 | |
| 8459 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8460 match(Set dst (SubI dst src)); | |
| 8461 effect(KILL cr); | |
| 8462 | |
| 8463 format %{ "SUB $dst,$src" %} | |
| 8464 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 8465 // ins_encode( RegImm( dst, src) ); | |
| 8466 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8467 ins_pipe( ialu_reg ); | |
| 8468 %} | |
| 8469 | |
| 8470 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8471 match(Set dst (SubI dst (LoadI src))); | |
| 8472 effect(KILL cr); | |
| 8473 | |
| 8474 ins_cost(125); | |
| 8475 format %{ "SUB $dst,$src" %} | |
| 8476 opcode(0x2B); | |
| 8477 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8478 ins_pipe( ialu_reg_mem ); | |
| 8479 %} | |
| 8480 | |
| 8481 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8482 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8483 effect(KILL cr); | |
| 8484 | |
| 8485 ins_cost(150); | |
| 8486 format %{ "SUB $dst,$src" %} | |
| 8487 opcode(0x29); /* Opcode 29 /r */ | |
| 8488 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8489 ins_pipe( ialu_mem_reg ); | |
| 8490 %} | |
| 8491 | |
| 8492 // Subtract from a pointer | |
| 8493 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ | |
| 8494 match(Set dst (AddP dst (SubI zero src))); | |
| 8495 effect(KILL cr); | |
| 8496 | |
| 8497 size(2); | |
| 8498 format %{ "SUB $dst,$src" %} | |
| 8499 opcode(0x2B); | |
| 8500 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8501 ins_pipe( ialu_reg_reg ); | |
| 8502 %} | |
| 8503 | |
| 8504 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 8505 match(Set dst (SubI zero dst)); | |
| 8506 effect(KILL cr); | |
| 8507 | |
| 8508 size(2); | |
| 8509 format %{ "NEG $dst" %} | |
| 8510 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 8511 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8512 ins_pipe( ialu_reg ); | |
| 8513 %} | |
| 8514 | |
| 8515 | |
| 8516 //----------Multiplication/Division Instructions------------------------------- | |
| 8517 // Integer Multiplication Instructions | |
| 8518 // Multiply Register | |
| 8519 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8520 match(Set dst (MulI dst src)); | |
| 8521 effect(KILL cr); | |
| 8522 | |
| 8523 size(3); | |
| 8524 ins_cost(300); | |
| 8525 format %{ "IMUL $dst,$src" %} | |
| 8526 opcode(0xAF, 0x0F); | |
| 8527 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 8528 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8529 %} | |
| 8530 | |
| 8531 // Multiply 32-bit Immediate | |
| 8532 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ | |
| 8533 match(Set dst (MulI src imm)); | |
| 8534 effect(KILL cr); | |
| 8535 | |
| 8536 ins_cost(300); | |
| 8537 format %{ "IMUL $dst,$src,$imm" %} | |
| 8538 opcode(0x69); /* 69 /r id */ | |
| 8539 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 8540 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8541 %} | |
| 8542 | |
| 8543 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 8544 match(Set dst src); | |
| 8545 effect(KILL cr); | |
| 8546 | |
| 8547 // Note that this is artificially increased to make it more expensive than loadConL | |
| 8548 ins_cost(250); | |
| 8549 format %{ "MOV EAX,$src\t// low word only" %} | |
| 8550 opcode(0xB8); | |
| 8551 ins_encode( LdImmL_Lo(dst, src) ); | |
| 8552 ins_pipe( ialu_reg_fat ); | |
| 8553 %} | |
| 8554 | |
| 8555 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8556 // (special case for shift by 32) | |
| 8557 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8558 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8559 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8560 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8561 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8562 effect(USE src1, KILL cr); | |
| 8563 | |
| 8564 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8565 ins_cost(0*100 + 1*400 - 150); | |
| 8566 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8567 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8568 ins_pipe( pipe_slow ); | |
| 8569 %} | |
| 8570 | |
| 8571 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8572 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8573 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8574 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8575 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8576 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8577 effect(USE src1, KILL cr); | |
| 8578 | |
| 8579 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8580 ins_cost(1*100 + 1*400 - 150); | |
| 8581 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8582 "SAR EDX,$cnt-32" %} | |
| 8583 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8584 ins_pipe( pipe_slow ); | |
| 8585 %} | |
| 8586 | |
| 8587 // Multiply Memory 32-bit Immediate | |
| 8588 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ | |
| 8589 match(Set dst (MulI (LoadI src) imm)); | |
| 8590 effect(KILL cr); | |
| 8591 | |
| 8592 ins_cost(300); | |
| 8593 format %{ "IMUL $dst,$src,$imm" %} | |
| 8594 opcode(0x69); /* 69 /r id */ | |
| 8595 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8596 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8597 %} | |
| 8598 | |
| 8599 // Multiply Memory | |
| 8600 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8601 match(Set dst (MulI dst (LoadI src))); | |
| 8602 effect(KILL cr); | |
| 8603 | |
| 8604 ins_cost(350); | |
| 8605 format %{ "IMUL $dst,$src" %} | |
| 8606 opcode(0xAF, 0x0F); | |
| 8607 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8608 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8609 %} | |
| 8610 | |
| 8611 // Multiply Register Int to Long | |
| 8612 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8613 // Basic Idea: long = (long)int * (long)int | |
| 8614 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8615 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8616 | |
| 8617 ins_cost(300); | |
| 8618 format %{ "IMUL $dst,$src1" %} | |
| 8619 | |
| 8620 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8621 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8622 %} | |
| 8623 | |
| 8624 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8625 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8626 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8627 effect(KILL flags); | |
| 8628 | |
| 8629 ins_cost(300); | |
| 8630 format %{ "MUL $dst,$src1" %} | |
| 8631 | |
| 8632 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8633 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8634 %} | |
| 8635 | |
| 8636 // Multiply Register Long | |
| 8637 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ | |
| 8638 match(Set dst (MulL dst src)); | |
| 8639 effect(KILL cr, TEMP tmp); | |
| 8640 ins_cost(4*100+3*400); | |
| 8641 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8642 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8643 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8644 "IMUL $tmp,EDX\n\t" | |
| 8645 "MOV EDX,$src.hi\n\t" | |
| 8646 "IMUL EDX,EAX\n\t" | |
| 8647 "ADD $tmp,EDX\n\t" | |
| 8648 "MUL EDX:EAX,$src.lo\n\t" | |
| 8649 "ADD EDX,$tmp" %} | |
| 8650 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8651 ins_pipe( pipe_slow ); | |
| 8652 %} | |
| 8653 | |
|
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8654 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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8655 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8656 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
8657 match(Set dst (MulL dst src)); |
|
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|
8658 effect(KILL cr, TEMP tmp); |
|
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|
8659 ins_cost(2*100+2*400); |
|
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8660 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8661 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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8662 format %{ "MOV $tmp,$src.hi\n\t" |
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|
8663 "IMUL $tmp,EAX\n\t" |
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8664 "MUL EDX:EAX,$src.lo\n\t" |
|
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8665 "ADD EDX,$tmp" %} |
|
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|
8666 ins_encode %{ |
|
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|
8667 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
8668 __ imull($tmp$$Register, rax); |
|
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|
8669 __ mull($src$$Register); |
|
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|
8670 __ addl(rdx, $tmp$$Register); |
|
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|
8671 %} |
|
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|
8672 ins_pipe( pipe_slow ); |
|
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|
8673 %} |
|
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|
8674 |
|
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|
8675 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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8676 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8677 predicate(is_operand_hi32_zero(n->in(2))); |
|
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8678 match(Set dst (MulL dst src)); |
|
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|
8679 effect(KILL cr, TEMP tmp); |
|
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|
8680 ins_cost(2*100+2*400); |
|
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|
8681 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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8682 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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|
8683 format %{ "MOV $tmp,$src.lo\n\t" |
|
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|
8684 "IMUL $tmp,EDX\n\t" |
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8685 "MUL EDX:EAX,$src.lo\n\t" |
|
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8686 "ADD EDX,$tmp" %} |
|
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|
8687 ins_encode %{ |
|
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|
8688 __ movl($tmp$$Register, $src$$Register); |
|
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|
8689 __ imull($tmp$$Register, rdx); |
|
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|
8690 __ mull($src$$Register); |
|
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|
8691 __ addl(rdx, $tmp$$Register); |
|
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|
8692 %} |
|
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|
8693 ins_pipe( pipe_slow ); |
|
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|
8694 %} |
|
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|
8695 |
|
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|
8696 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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|
8697 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
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|
8698 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
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|
8699 match(Set dst (MulL dst src)); |
|
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|
8700 effect(KILL cr); |
|
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|
8701 ins_cost(1*400); |
|
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|
8702 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8703 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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|
8704 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
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|
8705 ins_encode %{ |
|
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|
8706 __ mull($src$$Register); |
|
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|
8707 %} |
|
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|
8708 ins_pipe( pipe_slow ); |
|
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|
8709 %} |
|
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|
8710 |
| 0 | 8711 // Multiply Register Long by small constant |
| 8712 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ | |
| 8713 match(Set dst (MulL dst src)); | |
| 8714 effect(KILL cr, TEMP tmp); | |
| 8715 ins_cost(2*100+2*400); | |
| 8716 size(12); | |
| 8717 // Basic idea: lo(result) = lo(src * EAX) | |
| 8718 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8719 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8720 "MOV EDX,$src\n\t" | |
| 8721 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8722 "ADD EDX,$tmp" %} | |
| 8723 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8724 ins_pipe( pipe_slow ); | |
| 8725 %} | |
| 8726 | |
| 8727 // Integer DIV with Register | |
| 8728 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8729 match(Set rax (DivI rax div)); | |
| 8730 effect(KILL rdx, KILL cr); | |
| 8731 size(26); | |
| 8732 ins_cost(30*100+10*100); | |
| 8733 format %{ "CMP EAX,0x80000000\n\t" | |
| 8734 "JNE,s normal\n\t" | |
| 8735 "XOR EDX,EDX\n\t" | |
| 8736 "CMP ECX,-1\n\t" | |
| 8737 "JE,s done\n" | |
| 8738 "normal: CDQ\n\t" | |
| 8739 "IDIV $div\n\t" | |
| 8740 "done:" %} | |
| 8741 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8742 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8743 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8744 %} | |
| 8745 | |
| 8746 // Divide Register Long | |
| 8747 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8748 match(Set dst (DivL src1 src2)); | |
| 8749 effect( KILL cr, KILL cx, KILL bx ); | |
| 8750 ins_cost(10000); | |
| 8751 format %{ "PUSH $src1.hi\n\t" | |
| 8752 "PUSH $src1.lo\n\t" | |
| 8753 "PUSH $src2.hi\n\t" | |
| 8754 "PUSH $src2.lo\n\t" | |
| 8755 "CALL SharedRuntime::ldiv\n\t" | |
| 8756 "ADD ESP,16" %} | |
| 8757 ins_encode( long_div(src1,src2) ); | |
| 8758 ins_pipe( pipe_slow ); | |
| 8759 %} | |
| 8760 | |
| 8761 // Integer DIVMOD with Register, both quotient and mod results | |
| 8762 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8763 match(DivModI rax div); | |
| 8764 effect(KILL cr); | |
| 8765 size(26); | |
| 8766 ins_cost(30*100+10*100); | |
| 8767 format %{ "CMP EAX,0x80000000\n\t" | |
| 8768 "JNE,s normal\n\t" | |
| 8769 "XOR EDX,EDX\n\t" | |
| 8770 "CMP ECX,-1\n\t" | |
| 8771 "JE,s done\n" | |
| 8772 "normal: CDQ\n\t" | |
| 8773 "IDIV $div\n\t" | |
| 8774 "done:" %} | |
| 8775 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8776 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8777 ins_pipe( pipe_slow ); | |
| 8778 %} | |
| 8779 | |
| 8780 // Integer MOD with Register | |
| 8781 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8782 match(Set rdx (ModI rax div)); | |
| 8783 effect(KILL rax, KILL cr); | |
| 8784 | |
| 8785 size(26); | |
| 8786 ins_cost(300); | |
| 8787 format %{ "CDQ\n\t" | |
| 8788 "IDIV $div" %} | |
| 8789 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8790 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8791 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8792 %} | |
| 8793 | |
| 8794 // Remainder Register Long | |
| 8795 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8796 match(Set dst (ModL src1 src2)); | |
| 8797 effect( KILL cr, KILL cx, KILL bx ); | |
| 8798 ins_cost(10000); | |
| 8799 format %{ "PUSH $src1.hi\n\t" | |
| 8800 "PUSH $src1.lo\n\t" | |
| 8801 "PUSH $src2.hi\n\t" | |
| 8802 "PUSH $src2.lo\n\t" | |
| 8803 "CALL SharedRuntime::lrem\n\t" | |
| 8804 "ADD ESP,16" %} | |
| 8805 ins_encode( long_mod(src1,src2) ); | |
| 8806 ins_pipe( pipe_slow ); | |
| 8807 %} | |
| 8808 | |
| 8809 // Integer Shift Instructions | |
| 8810 // Shift Left by one | |
| 8811 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8812 match(Set dst (LShiftI dst shift)); | |
| 8813 effect(KILL cr); | |
| 8814 | |
| 8815 size(2); | |
| 8816 format %{ "SHL $dst,$shift" %} | |
| 8817 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8818 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8819 ins_pipe( ialu_reg ); | |
| 8820 %} | |
| 8821 | |
| 8822 // Shift Left by 8-bit immediate | |
| 8823 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8824 match(Set dst (LShiftI dst shift)); | |
| 8825 effect(KILL cr); | |
| 8826 | |
| 8827 size(3); | |
| 8828 format %{ "SHL $dst,$shift" %} | |
| 8829 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8830 ins_encode( RegOpcImm( dst, shift) ); | |
| 8831 ins_pipe( ialu_reg ); | |
| 8832 %} | |
| 8833 | |
| 8834 // Shift Left by variable | |
| 8835 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8836 match(Set dst (LShiftI dst shift)); | |
| 8837 effect(KILL cr); | |
| 8838 | |
| 8839 size(2); | |
| 8840 format %{ "SHL $dst,$shift" %} | |
| 8841 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8842 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8843 ins_pipe( ialu_reg_reg ); | |
| 8844 %} | |
| 8845 | |
| 8846 // Arithmetic shift right by one | |
| 8847 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8848 match(Set dst (RShiftI dst shift)); | |
| 8849 effect(KILL cr); | |
| 8850 | |
| 8851 size(2); | |
| 8852 format %{ "SAR $dst,$shift" %} | |
| 8853 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8854 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8855 ins_pipe( ialu_reg ); | |
| 8856 %} | |
| 8857 | |
| 8858 // Arithmetic shift right by one | |
| 8859 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8860 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8861 effect(KILL cr); | |
| 8862 format %{ "SAR $dst,$shift" %} | |
| 8863 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8864 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8865 ins_pipe( ialu_mem_imm ); | |
| 8866 %} | |
| 8867 | |
| 8868 // Arithmetic Shift Right by 8-bit immediate | |
| 8869 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8870 match(Set dst (RShiftI dst shift)); | |
| 8871 effect(KILL cr); | |
| 8872 | |
| 8873 size(3); | |
| 8874 format %{ "SAR $dst,$shift" %} | |
| 8875 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8876 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8877 ins_pipe( ialu_mem_imm ); | |
| 8878 %} | |
| 8879 | |
| 8880 // Arithmetic Shift Right by 8-bit immediate | |
| 8881 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8882 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8883 effect(KILL cr); | |
| 8884 | |
| 8885 format %{ "SAR $dst,$shift" %} | |
| 8886 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8887 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8888 ins_pipe( ialu_mem_imm ); | |
| 8889 %} | |
| 8890 | |
| 8891 // Arithmetic Shift Right by variable | |
| 8892 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8893 match(Set dst (RShiftI dst shift)); | |
| 8894 effect(KILL cr); | |
| 8895 | |
| 8896 size(2); | |
| 8897 format %{ "SAR $dst,$shift" %} | |
| 8898 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8899 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8900 ins_pipe( ialu_reg_reg ); | |
| 8901 %} | |
| 8902 | |
| 8903 // Logical shift right by one | |
| 8904 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8905 match(Set dst (URShiftI dst shift)); | |
| 8906 effect(KILL cr); | |
| 8907 | |
| 8908 size(2); | |
| 8909 format %{ "SHR $dst,$shift" %} | |
| 8910 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8911 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8912 ins_pipe( ialu_reg ); | |
| 8913 %} | |
| 8914 | |
| 8915 // Logical Shift Right by 8-bit immediate | |
| 8916 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8917 match(Set dst (URShiftI dst shift)); | |
| 8918 effect(KILL cr); | |
| 8919 | |
| 8920 size(3); | |
| 8921 format %{ "SHR $dst,$shift" %} | |
| 8922 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8923 ins_encode( RegOpcImm( dst, shift) ); | |
| 8924 ins_pipe( ialu_reg ); | |
| 8925 %} | |
| 8926 | |
|
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8927 |
| 0 | 8928 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8929 // This idiom is used by the compiler for the i2b bytecode. | |
| 785 | 8930 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 8931 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 8932 | |
| 8933 size(3); | |
| 8934 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 8935 ins_encode %{ |
| 8936 __ movsbl($dst$$Register, $src$$Register); | |
| 8937 %} | |
| 8938 ins_pipe(ialu_reg_reg); | |
| 0 | 8939 %} |
| 8940 | |
| 8941 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8942 // This idiom is used by the compiler the i2s bytecode. | |
| 785 | 8943 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8944 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8945 | |
| 8946 size(3); | |
| 8947 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8948 ins_encode %{ |
| 8949 __ movswl($dst$$Register, $src$$Register); | |
| 8950 %} | |
| 8951 ins_pipe(ialu_reg_reg); | |
| 0 | 8952 %} |
| 8953 | |
| 8954 | |
| 8955 // Logical Shift Right by variable | |
| 8956 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8957 match(Set dst (URShiftI dst shift)); | |
| 8958 effect(KILL cr); | |
| 8959 | |
| 8960 size(2); | |
| 8961 format %{ "SHR $dst,$shift" %} | |
| 8962 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8963 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8964 ins_pipe( ialu_reg_reg ); | |
| 8965 %} | |
| 8966 | |
| 8967 | |
| 8968 //----------Logical Instructions----------------------------------------------- | |
| 8969 //----------Integer Logical Instructions--------------------------------------- | |
| 8970 // And Instructions | |
| 8971 // And Register with Register | |
| 8972 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8973 match(Set dst (AndI dst src)); | |
| 8974 effect(KILL cr); | |
| 8975 | |
| 8976 size(2); | |
| 8977 format %{ "AND $dst,$src" %} | |
| 8978 opcode(0x23); | |
| 8979 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8980 ins_pipe( ialu_reg_reg ); | |
| 8981 %} | |
| 8982 | |
| 8983 // And Register with Immediate | |
| 8984 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8985 match(Set dst (AndI dst src)); | |
| 8986 effect(KILL cr); | |
| 8987 | |
| 8988 format %{ "AND $dst,$src" %} | |
| 8989 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8990 // ins_encode( RegImm( dst, src) ); | |
| 8991 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8992 ins_pipe( ialu_reg ); | |
| 8993 %} | |
| 8994 | |
| 8995 // And Register with Memory | |
| 8996 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8997 match(Set dst (AndI dst (LoadI src))); | |
| 8998 effect(KILL cr); | |
| 8999 | |
| 9000 ins_cost(125); | |
| 9001 format %{ "AND $dst,$src" %} | |
| 9002 opcode(0x23); | |
| 9003 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9004 ins_pipe( ialu_reg_mem ); | |
| 9005 %} | |
| 9006 | |
| 9007 // And Memory with Register | |
| 9008 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9009 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9010 effect(KILL cr); | |
| 9011 | |
| 9012 ins_cost(150); | |
| 9013 format %{ "AND $dst,$src" %} | |
| 9014 opcode(0x21); /* Opcode 21 /r */ | |
| 9015 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9016 ins_pipe( ialu_mem_reg ); | |
| 9017 %} | |
| 9018 | |
| 9019 // And Memory with Immediate | |
| 9020 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9021 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9022 effect(KILL cr); | |
| 9023 | |
| 9024 ins_cost(125); | |
| 9025 format %{ "AND $dst,$src" %} | |
| 9026 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9027 // ins_encode( MemImm( dst, src) ); | |
| 9028 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9029 ins_pipe( ialu_mem_imm ); | |
| 9030 %} | |
| 9031 | |
| 9032 // Or Instructions | |
| 9033 // Or Register with Register | |
| 9034 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9035 match(Set dst (OrI dst src)); | |
| 9036 effect(KILL cr); | |
| 9037 | |
| 9038 size(2); | |
| 9039 format %{ "OR $dst,$src" %} | |
| 9040 opcode(0x0B); | |
| 9041 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9042 ins_pipe( ialu_reg_reg ); | |
| 9043 %} | |
| 9044 | |
|
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9045 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ |
|
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9046 match(Set dst (OrI dst (CastP2X src))); |
|
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9047 effect(KILL cr); |
|
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9048 |
|
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9049 size(2); |
|
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9050 format %{ "OR $dst,$src" %} |
|
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9051 opcode(0x0B); |
|
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9052 ins_encode( OpcP, RegReg( dst, src) ); |
|
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9053 ins_pipe( ialu_reg_reg ); |
|
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9054 %} |
|
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9055 |
|
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|
9056 |
| 0 | 9057 // Or Register with Immediate |
| 9058 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9059 match(Set dst (OrI dst src)); | |
| 9060 effect(KILL cr); | |
| 9061 | |
| 9062 format %{ "OR $dst,$src" %} | |
| 9063 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 9064 // ins_encode( RegImm( dst, src) ); | |
| 9065 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9066 ins_pipe( ialu_reg ); | |
| 9067 %} | |
| 9068 | |
| 9069 // Or Register with Memory | |
| 9070 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9071 match(Set dst (OrI dst (LoadI src))); | |
| 9072 effect(KILL cr); | |
| 9073 | |
| 9074 ins_cost(125); | |
| 9075 format %{ "OR $dst,$src" %} | |
| 9076 opcode(0x0B); | |
| 9077 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9078 ins_pipe( ialu_reg_mem ); | |
| 9079 %} | |
| 9080 | |
| 9081 // Or Memory with Register | |
| 9082 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9083 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9084 effect(KILL cr); | |
| 9085 | |
| 9086 ins_cost(150); | |
| 9087 format %{ "OR $dst,$src" %} | |
| 9088 opcode(0x09); /* Opcode 09 /r */ | |
| 9089 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9090 ins_pipe( ialu_mem_reg ); | |
| 9091 %} | |
| 9092 | |
| 9093 // Or Memory with Immediate | |
| 9094 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9095 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9096 effect(KILL cr); | |
| 9097 | |
| 9098 ins_cost(125); | |
| 9099 format %{ "OR $dst,$src" %} | |
| 9100 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 9101 // ins_encode( MemImm( dst, src) ); | |
| 9102 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9103 ins_pipe( ialu_mem_imm ); | |
| 9104 %} | |
| 9105 | |
| 9106 // ROL/ROR | |
| 9107 // ROL expand | |
| 9108 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9109 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9110 | |
| 9111 format %{ "ROL $dst, $shift" %} | |
| 9112 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9113 ins_encode( OpcP, RegOpc( dst )); | |
| 9114 ins_pipe( ialu_reg ); | |
| 9115 %} | |
| 9116 | |
| 9117 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9118 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9119 | |
| 9120 format %{ "ROL $dst, $shift" %} | |
| 9121 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 9122 ins_encode( RegOpcImm(dst, shift) ); | |
| 9123 ins_pipe(ialu_reg); | |
| 9124 %} | |
| 9125 | |
| 9126 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9127 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9128 | |
| 9129 format %{ "ROL $dst, $shift" %} | |
| 9130 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9131 ins_encode(OpcP, RegOpc(dst)); | |
| 9132 ins_pipe( ialu_reg_reg ); | |
| 9133 %} | |
| 9134 // end of ROL expand | |
| 9135 | |
| 9136 // ROL 32bit by one once | |
| 9137 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ | |
| 9138 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9139 | |
| 9140 expand %{ | |
| 9141 rolI_eReg_imm1(dst, lshift, cr); | |
| 9142 %} | |
| 9143 %} | |
| 9144 | |
| 9145 // ROL 32bit var by imm8 once | |
| 9146 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ | |
| 9147 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9148 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9149 | |
| 9150 expand %{ | |
| 9151 rolI_eReg_imm8(dst, lshift, cr); | |
| 9152 %} | |
| 9153 %} | |
| 9154 | |
| 9155 // ROL 32bit var by var once | |
| 9156 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9157 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9158 | |
| 9159 expand %{ | |
| 9160 rolI_eReg_CL(dst, shift, cr); | |
| 9161 %} | |
| 9162 %} | |
| 9163 | |
| 9164 // ROL 32bit var by var once | |
| 9165 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9166 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9167 | |
| 9168 expand %{ | |
| 9169 rolI_eReg_CL(dst, shift, cr); | |
| 9170 %} | |
| 9171 %} | |
| 9172 | |
| 9173 // ROR expand | |
| 9174 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9175 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9176 | |
| 9177 format %{ "ROR $dst, $shift" %} | |
| 9178 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 9179 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9180 ins_pipe( ialu_reg ); | |
| 9181 %} | |
| 9182 | |
| 9183 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9184 effect (USE_DEF dst, USE shift, KILL cr); | |
| 9185 | |
| 9186 format %{ "ROR $dst, $shift" %} | |
| 9187 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 9188 ins_encode( RegOpcImm(dst, shift) ); | |
| 9189 ins_pipe( ialu_reg ); | |
| 9190 %} | |
| 9191 | |
| 9192 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 9193 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9194 | |
| 9195 format %{ "ROR $dst, $shift" %} | |
| 9196 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 9197 ins_encode(OpcP, RegOpc(dst)); | |
| 9198 ins_pipe( ialu_reg_reg ); | |
| 9199 %} | |
| 9200 // end of ROR expand | |
| 9201 | |
| 9202 // ROR right once | |
| 9203 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ | |
| 9204 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9205 | |
| 9206 expand %{ | |
| 9207 rorI_eReg_imm1(dst, rshift, cr); | |
| 9208 %} | |
| 9209 %} | |
| 9210 | |
| 9211 // ROR 32bit by immI8 once | |
| 9212 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ | |
| 9213 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9214 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9215 | |
| 9216 expand %{ | |
| 9217 rorI_eReg_imm8(dst, rshift, cr); | |
| 9218 %} | |
| 9219 %} | |
| 9220 | |
| 9221 // ROR 32bit var by var once | |
| 9222 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9223 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9224 | |
| 9225 expand %{ | |
| 9226 rorI_eReg_CL(dst, shift, cr); | |
| 9227 %} | |
| 9228 %} | |
| 9229 | |
| 9230 // ROR 32bit var by var once | |
| 9231 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9232 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9233 | |
| 9234 expand %{ | |
| 9235 rorI_eReg_CL(dst, shift, cr); | |
| 9236 %} | |
| 9237 %} | |
| 9238 | |
| 9239 // Xor Instructions | |
| 9240 // Xor Register with Register | |
| 9241 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9242 match(Set dst (XorI dst src)); | |
| 9243 effect(KILL cr); | |
| 9244 | |
| 9245 size(2); | |
| 9246 format %{ "XOR $dst,$src" %} | |
| 9247 opcode(0x33); | |
| 9248 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9249 ins_pipe( ialu_reg_reg ); | |
| 9250 %} | |
| 9251 | |
| 403 | 9252 // Xor Register with Immediate -1 |
| 9253 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ | |
| 9254 match(Set dst (XorI dst imm)); | |
| 9255 | |
| 9256 size(2); | |
| 9257 format %{ "NOT $dst" %} | |
| 9258 ins_encode %{ | |
| 9259 __ notl($dst$$Register); | |
| 9260 %} | |
| 9261 ins_pipe( ialu_reg ); | |
| 9262 %} | |
| 9263 | |
| 0 | 9264 // Xor Register with Immediate |
| 9265 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9266 match(Set dst (XorI dst src)); | |
| 9267 effect(KILL cr); | |
| 9268 | |
| 9269 format %{ "XOR $dst,$src" %} | |
| 9270 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 9271 // ins_encode( RegImm( dst, src) ); | |
| 9272 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9273 ins_pipe( ialu_reg ); | |
| 9274 %} | |
| 9275 | |
| 9276 // Xor Register with Memory | |
| 9277 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9278 match(Set dst (XorI dst (LoadI src))); | |
| 9279 effect(KILL cr); | |
| 9280 | |
| 9281 ins_cost(125); | |
| 9282 format %{ "XOR $dst,$src" %} | |
| 9283 opcode(0x33); | |
| 9284 ins_encode( OpcP, RegMem(dst, src) ); | |
| 9285 ins_pipe( ialu_reg_mem ); | |
| 9286 %} | |
| 9287 | |
| 9288 // Xor Memory with Register | |
| 9289 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9290 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9291 effect(KILL cr); | |
| 9292 | |
| 9293 ins_cost(150); | |
| 9294 format %{ "XOR $dst,$src" %} | |
| 9295 opcode(0x31); /* Opcode 31 /r */ | |
| 9296 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9297 ins_pipe( ialu_mem_reg ); | |
| 9298 %} | |
| 9299 | |
| 9300 // Xor Memory with Immediate | |
| 9301 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9302 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9303 effect(KILL cr); | |
| 9304 | |
| 9305 ins_cost(125); | |
| 9306 format %{ "XOR $dst,$src" %} | |
| 9307 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 9308 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9309 ins_pipe( ialu_mem_imm ); | |
| 9310 %} | |
| 9311 | |
| 9312 //----------Convert Int to Boolean--------------------------------------------- | |
| 9313 | |
| 9314 instruct movI_nocopy(eRegI dst, eRegI src) %{ | |
| 9315 effect( DEF dst, USE src ); | |
| 9316 format %{ "MOV $dst,$src" %} | |
| 9317 ins_encode( enc_Copy( dst, src) ); | |
| 9318 ins_pipe( ialu_reg_reg ); | |
| 9319 %} | |
| 9320 | |
| 9321 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9322 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9323 | |
| 9324 size(4); | |
| 9325 format %{ "NEG $dst\n\t" | |
| 9326 "ADC $dst,$src" %} | |
| 9327 ins_encode( neg_reg(dst), | |
| 9328 OpcRegReg(0x13,dst,src) ); | |
| 9329 ins_pipe( ialu_reg_reg_long ); | |
| 9330 %} | |
| 9331 | |
| 9332 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9333 match(Set dst (Conv2B src)); | |
| 9334 | |
| 9335 expand %{ | |
| 9336 movI_nocopy(dst,src); | |
| 9337 ci2b(dst,src,cr); | |
| 9338 %} | |
| 9339 %} | |
| 9340 | |
| 9341 instruct movP_nocopy(eRegI dst, eRegP src) %{ | |
| 9342 effect( DEF dst, USE src ); | |
| 9343 format %{ "MOV $dst,$src" %} | |
| 9344 ins_encode( enc_Copy( dst, src) ); | |
| 9345 ins_pipe( ialu_reg_reg ); | |
| 9346 %} | |
| 9347 | |
| 9348 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9349 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9350 format %{ "NEG $dst\n\t" | |
| 9351 "ADC $dst,$src" %} | |
| 9352 ins_encode( neg_reg(dst), | |
| 9353 OpcRegReg(0x13,dst,src) ); | |
| 9354 ins_pipe( ialu_reg_reg_long ); | |
| 9355 %} | |
| 9356 | |
| 9357 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9358 match(Set dst (Conv2B src)); | |
| 9359 | |
| 9360 expand %{ | |
| 9361 movP_nocopy(dst,src); | |
| 9362 cp2b(dst,src,cr); | |
| 9363 %} | |
| 9364 %} | |
| 9365 | |
| 9366 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 9367 match(Set dst (CmpLTMask p q)); | |
| 9368 effect( KILL cr ); | |
| 9369 ins_cost(400); | |
| 9370 | |
| 9371 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 9372 format %{ "XOR $dst,$dst\n\t" | |
| 9373 "CMP $p,$q\n\t" | |
| 9374 "SETlt $dst\n\t" | |
| 9375 "NEG $dst" %} | |
| 9376 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 9377 OpcRegReg(0x3B,p,q), | |
| 9378 setLT_reg(dst), neg_reg(dst) ); | |
| 9379 ins_pipe( pipe_slow ); | |
| 9380 %} | |
| 9381 | |
| 9382 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ | |
| 9383 match(Set dst (CmpLTMask dst zero)); | |
| 9384 effect( DEF dst, KILL cr ); | |
| 9385 ins_cost(100); | |
| 9386 | |
| 9387 format %{ "SAR $dst,31" %} | |
| 9388 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9389 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 9390 ins_pipe( ialu_reg ); | |
| 9391 %} | |
| 9392 | |
| 9393 | |
| 9394 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9395 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9396 effect( KILL tmp, KILL cr ); | |
| 9397 ins_cost(400); | |
| 9398 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 9399 // any format or encoding | |
| 9400 format %{ "SUB $p,$q\n\t" | |
| 9401 "SBB ECX,ECX\n\t" | |
| 9402 "AND ECX,$y\n\t" | |
| 9403 "ADD $p,ECX" %} | |
| 9404 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 9405 ins_pipe( pipe_cmplt ); | |
| 9406 %} | |
| 9407 | |
| 9408 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9409 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9410 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9411 effect( USE_KILL tmp, KILL cr ); | |
| 9412 ins_cost(400); | |
| 9413 | |
| 9414 format %{ "SUB $p,$q\n\t" | |
| 9415 "SBB ECX,ECX\n\t" | |
| 9416 "AND ECX,$y\n\t" | |
| 9417 "ADD $p,ECX" %} | |
| 9418 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9419 %} | |
| 9420 */ | |
| 9421 | |
| 9422 //----------Long Instructions------------------------------------------------ | |
| 9423 // Add Long Register with Register | |
| 9424 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9425 match(Set dst (AddL dst src)); | |
| 9426 effect(KILL cr); | |
| 9427 ins_cost(200); | |
| 9428 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9429 "ADC $dst.hi,$src.hi" %} | |
| 9430 opcode(0x03, 0x13); | |
| 9431 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9432 ins_pipe( ialu_reg_reg_long ); | |
| 9433 %} | |
| 9434 | |
| 9435 // Add Long Register with Immediate | |
| 9436 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9437 match(Set dst (AddL dst src)); | |
| 9438 effect(KILL cr); | |
| 9439 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9440 "ADC $dst.hi,$src.hi" %} | |
| 9441 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9442 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9443 ins_pipe( ialu_reg_long ); | |
| 9444 %} | |
| 9445 | |
| 9446 // Add Long Register with Memory | |
| 9447 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9448 match(Set dst (AddL dst (LoadL mem))); | |
| 9449 effect(KILL cr); | |
| 9450 ins_cost(125); | |
| 9451 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9452 "ADC $dst.hi,$mem+4" %} | |
| 9453 opcode(0x03, 0x13); | |
| 9454 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9455 ins_pipe( ialu_reg_long_mem ); | |
| 9456 %} | |
| 9457 | |
| 9458 // Subtract Long Register with Register. | |
| 9459 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9460 match(Set dst (SubL dst src)); | |
| 9461 effect(KILL cr); | |
| 9462 ins_cost(200); | |
| 9463 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9464 "SBB $dst.hi,$src.hi" %} | |
| 9465 opcode(0x2B, 0x1B); | |
| 9466 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9467 ins_pipe( ialu_reg_reg_long ); | |
| 9468 %} | |
| 9469 | |
| 9470 // Subtract Long Register with Immediate | |
| 9471 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9472 match(Set dst (SubL dst src)); | |
| 9473 effect(KILL cr); | |
| 9474 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9475 "SBB $dst.hi,$src.hi" %} | |
| 9476 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9477 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9478 ins_pipe( ialu_reg_long ); | |
| 9479 %} | |
| 9480 | |
| 9481 // Subtract Long Register with Memory | |
| 9482 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9483 match(Set dst (SubL dst (LoadL mem))); | |
| 9484 effect(KILL cr); | |
| 9485 ins_cost(125); | |
| 9486 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9487 "SBB $dst.hi,$mem+4" %} | |
| 9488 opcode(0x2B, 0x1B); | |
| 9489 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9490 ins_pipe( ialu_reg_long_mem ); | |
| 9491 %} | |
| 9492 | |
| 9493 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9494 match(Set dst (SubL zero dst)); | |
| 9495 effect(KILL cr); | |
| 9496 ins_cost(300); | |
| 9497 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9498 ins_encode( neg_long(dst) ); | |
| 9499 ins_pipe( ialu_reg_reg_long ); | |
| 9500 %} | |
| 9501 | |
| 9502 // And Long Register with Register | |
| 9503 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9504 match(Set dst (AndL dst src)); | |
| 9505 effect(KILL cr); | |
| 9506 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9507 "AND $dst.hi,$src.hi" %} | |
| 9508 opcode(0x23,0x23); | |
| 9509 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9510 ins_pipe( ialu_reg_reg_long ); | |
| 9511 %} | |
| 9512 | |
| 9513 // And Long Register with Immediate | |
| 9514 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9515 match(Set dst (AndL dst src)); | |
| 9516 effect(KILL cr); | |
| 9517 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9518 "AND $dst.hi,$src.hi" %} | |
| 9519 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9520 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9521 ins_pipe( ialu_reg_long ); | |
| 9522 %} | |
| 9523 | |
| 9524 // And Long Register with Memory | |
| 9525 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9526 match(Set dst (AndL dst (LoadL mem))); | |
| 9527 effect(KILL cr); | |
| 9528 ins_cost(125); | |
| 9529 format %{ "AND $dst.lo,$mem\n\t" | |
| 9530 "AND $dst.hi,$mem+4" %} | |
| 9531 opcode(0x23, 0x23); | |
| 9532 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9533 ins_pipe( ialu_reg_long_mem ); | |
| 9534 %} | |
| 9535 | |
| 9536 // Or Long Register with Register | |
| 9537 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9538 match(Set dst (OrL dst src)); | |
| 9539 effect(KILL cr); | |
| 9540 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9541 "OR $dst.hi,$src.hi" %} | |
| 9542 opcode(0x0B,0x0B); | |
| 9543 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9544 ins_pipe( ialu_reg_reg_long ); | |
| 9545 %} | |
| 9546 | |
| 9547 // Or Long Register with Immediate | |
| 9548 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9549 match(Set dst (OrL dst src)); | |
| 9550 effect(KILL cr); | |
| 9551 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9552 "OR $dst.hi,$src.hi" %} | |
| 9553 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9554 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9555 ins_pipe( ialu_reg_long ); | |
| 9556 %} | |
| 9557 | |
| 9558 // Or Long Register with Memory | |
| 9559 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9560 match(Set dst (OrL dst (LoadL mem))); | |
| 9561 effect(KILL cr); | |
| 9562 ins_cost(125); | |
| 9563 format %{ "OR $dst.lo,$mem\n\t" | |
| 9564 "OR $dst.hi,$mem+4" %} | |
| 9565 opcode(0x0B,0x0B); | |
| 9566 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9567 ins_pipe( ialu_reg_long_mem ); | |
| 9568 %} | |
| 9569 | |
| 9570 // Xor Long Register with Register | |
| 9571 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9572 match(Set dst (XorL dst src)); | |
| 9573 effect(KILL cr); | |
| 9574 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9575 "XOR $dst.hi,$src.hi" %} | |
| 9576 opcode(0x33,0x33); | |
| 9577 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9578 ins_pipe( ialu_reg_reg_long ); | |
| 9579 %} | |
| 9580 | |
| 403 | 9581 // Xor Long Register with Immediate -1 |
| 9582 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9583 match(Set dst (XorL dst imm)); | |
| 9584 format %{ "NOT $dst.lo\n\t" | |
| 9585 "NOT $dst.hi" %} | |
| 9586 ins_encode %{ | |
| 9587 __ notl($dst$$Register); | |
| 9588 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9589 %} | |
| 9590 ins_pipe( ialu_reg_long ); | |
| 9591 %} | |
| 9592 | |
| 0 | 9593 // Xor Long Register with Immediate |
| 9594 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9595 match(Set dst (XorL dst src)); | |
| 9596 effect(KILL cr); | |
| 9597 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9598 "XOR $dst.hi,$src.hi" %} | |
| 9599 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9600 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9601 ins_pipe( ialu_reg_long ); | |
| 9602 %} | |
| 9603 | |
| 9604 // Xor Long Register with Memory | |
| 9605 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9606 match(Set dst (XorL dst (LoadL mem))); | |
| 9607 effect(KILL cr); | |
| 9608 ins_cost(125); | |
| 9609 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9610 "XOR $dst.hi,$mem+4" %} | |
| 9611 opcode(0x33,0x33); | |
| 9612 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9613 ins_pipe( ialu_reg_long_mem ); | |
| 9614 %} | |
| 9615 | |
| 219 | 9616 // Shift Left Long by 1 |
| 9617 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9618 predicate(UseNewLongLShift); | |
| 9619 match(Set dst (LShiftL dst cnt)); | |
| 9620 effect(KILL cr); | |
| 9621 ins_cost(100); | |
| 9622 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9623 "ADC $dst.hi,$dst.hi" %} | |
| 9624 ins_encode %{ | |
| 9625 __ addl($dst$$Register,$dst$$Register); | |
| 9626 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9627 %} | |
| 9628 ins_pipe( ialu_reg_long ); | |
| 9629 %} | |
| 9630 | |
| 9631 // Shift Left Long by 2 | |
| 9632 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9633 predicate(UseNewLongLShift); | |
| 9634 match(Set dst (LShiftL dst cnt)); | |
| 9635 effect(KILL cr); | |
| 9636 ins_cost(100); | |
| 9637 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9638 "ADC $dst.hi,$dst.hi\n\t" | |
| 9639 "ADD $dst.lo,$dst.lo\n\t" | |
| 9640 "ADC $dst.hi,$dst.hi" %} | |
| 9641 ins_encode %{ | |
| 9642 __ addl($dst$$Register,$dst$$Register); | |
| 9643 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9644 __ addl($dst$$Register,$dst$$Register); | |
| 9645 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9646 %} | |
| 9647 ins_pipe( ialu_reg_long ); | |
| 9648 %} | |
| 9649 | |
| 9650 // Shift Left Long by 3 | |
| 9651 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9652 predicate(UseNewLongLShift); | |
| 9653 match(Set dst (LShiftL dst cnt)); | |
| 9654 effect(KILL cr); | |
| 9655 ins_cost(100); | |
| 9656 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9657 "ADC $dst.hi,$dst.hi\n\t" | |
| 9658 "ADD $dst.lo,$dst.lo\n\t" | |
| 9659 "ADC $dst.hi,$dst.hi\n\t" | |
| 9660 "ADD $dst.lo,$dst.lo\n\t" | |
| 9661 "ADC $dst.hi,$dst.hi" %} | |
| 9662 ins_encode %{ | |
| 9663 __ addl($dst$$Register,$dst$$Register); | |
| 9664 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9665 __ addl($dst$$Register,$dst$$Register); | |
| 9666 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9667 __ addl($dst$$Register,$dst$$Register); | |
| 9668 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9669 %} | |
| 9670 ins_pipe( ialu_reg_long ); | |
| 9671 %} | |
| 9672 | |
| 0 | 9673 // Shift Left Long by 1-31 |
| 9674 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9675 match(Set dst (LShiftL dst cnt)); | |
| 9676 effect(KILL cr); | |
| 9677 ins_cost(200); | |
| 9678 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9679 "SHL $dst.lo,$cnt" %} | |
| 9680 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9681 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9682 ins_pipe( ialu_reg_long ); | |
| 9683 %} | |
| 9684 | |
| 9685 // Shift Left Long by 32-63 | |
| 9686 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9687 match(Set dst (LShiftL dst cnt)); | |
| 9688 effect(KILL cr); | |
| 9689 ins_cost(300); | |
| 9690 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9691 "\tSHL $dst.hi,$cnt-32\n" | |
| 9692 "\tXOR $dst.lo,$dst.lo" %} | |
| 9693 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9694 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9695 ins_pipe( ialu_reg_long ); | |
| 9696 %} | |
| 9697 | |
| 9698 // Shift Left Long by variable | |
| 9699 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9700 match(Set dst (LShiftL dst shift)); | |
| 9701 effect(KILL cr); | |
| 9702 ins_cost(500+200); | |
| 9703 size(17); | |
| 9704 format %{ "TEST $shift,32\n\t" | |
| 9705 "JEQ,s small\n\t" | |
| 9706 "MOV $dst.hi,$dst.lo\n\t" | |
| 9707 "XOR $dst.lo,$dst.lo\n" | |
| 9708 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9709 "SHL $dst.lo,$shift" %} | |
| 9710 ins_encode( shift_left_long( dst, shift ) ); | |
| 9711 ins_pipe( pipe_slow ); | |
| 9712 %} | |
| 9713 | |
| 9714 // Shift Right Long by 1-31 | |
| 9715 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9716 match(Set dst (URShiftL dst cnt)); | |
| 9717 effect(KILL cr); | |
| 9718 ins_cost(200); | |
| 9719 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9720 "SHR $dst.hi,$cnt" %} | |
| 9721 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9722 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9723 ins_pipe( ialu_reg_long ); | |
| 9724 %} | |
| 9725 | |
| 9726 // Shift Right Long by 32-63 | |
| 9727 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9728 match(Set dst (URShiftL dst cnt)); | |
| 9729 effect(KILL cr); | |
| 9730 ins_cost(300); | |
| 9731 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9732 "\tSHR $dst.lo,$cnt-32\n" | |
| 9733 "\tXOR $dst.hi,$dst.hi" %} | |
| 9734 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9735 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9736 ins_pipe( ialu_reg_long ); | |
| 9737 %} | |
| 9738 | |
| 9739 // Shift Right Long by variable | |
| 9740 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9741 match(Set dst (URShiftL dst shift)); | |
| 9742 effect(KILL cr); | |
| 9743 ins_cost(600); | |
| 9744 size(17); | |
| 9745 format %{ "TEST $shift,32\n\t" | |
| 9746 "JEQ,s small\n\t" | |
| 9747 "MOV $dst.lo,$dst.hi\n\t" | |
| 9748 "XOR $dst.hi,$dst.hi\n" | |
| 9749 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9750 "SHR $dst.hi,$shift" %} | |
| 9751 ins_encode( shift_right_long( dst, shift ) ); | |
| 9752 ins_pipe( pipe_slow ); | |
| 9753 %} | |
| 9754 | |
| 9755 // Shift Right Long by 1-31 | |
| 9756 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9757 match(Set dst (RShiftL dst cnt)); | |
| 9758 effect(KILL cr); | |
| 9759 ins_cost(200); | |
| 9760 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9761 "SAR $dst.hi,$cnt" %} | |
| 9762 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9763 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9764 ins_pipe( ialu_reg_long ); | |
| 9765 %} | |
| 9766 | |
| 9767 // Shift Right Long by 32-63 | |
| 9768 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9769 match(Set dst (RShiftL dst cnt)); | |
| 9770 effect(KILL cr); | |
| 9771 ins_cost(300); | |
| 9772 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9773 "\tSAR $dst.lo,$cnt-32\n" | |
| 9774 "\tSAR $dst.hi,31" %} | |
| 9775 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9776 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9777 ins_pipe( ialu_reg_long ); | |
| 9778 %} | |
| 9779 | |
| 9780 // Shift Right arithmetic Long by variable | |
| 9781 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9782 match(Set dst (RShiftL dst shift)); | |
| 9783 effect(KILL cr); | |
| 9784 ins_cost(600); | |
| 9785 size(18); | |
| 9786 format %{ "TEST $shift,32\n\t" | |
| 9787 "JEQ,s small\n\t" | |
| 9788 "MOV $dst.lo,$dst.hi\n\t" | |
| 9789 "SAR $dst.hi,31\n" | |
| 9790 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9791 "SAR $dst.hi,$shift" %} | |
| 9792 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9793 ins_pipe( pipe_slow ); | |
| 9794 %} | |
| 9795 | |
| 9796 | |
| 9797 //----------Double Instructions------------------------------------------------ | |
| 9798 // Double Math | |
| 9799 | |
| 9800 // Compare & branch | |
| 9801 | |
| 9802 // P6 version of float compare, sets condition codes in EFLAGS | |
| 9803 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9804 predicate(VM_Version::supports_cmov() && UseSSE <=1); | |
| 9805 match(Set cr (CmpD src1 src2)); | |
| 9806 effect(KILL rax); | |
| 9807 ins_cost(150); | |
| 9808 format %{ "FLD $src1\n\t" | |
| 9809 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9810 "JNP exit\n\t" | |
| 9811 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9812 "SAHF\n" | |
| 9813 "exit:\tNOP // avoid branch to branch" %} | |
| 9814 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 9815 ins_encode( Push_Reg_D(src1), | |
| 9816 OpcP, RegOpc(src2), | |
| 9817 cmpF_P6_fixup ); | |
| 9818 ins_pipe( pipe_slow ); | |
| 9819 %} | |
| 9820 | |
|
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|
9821 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9822 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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|
9823 match(Set cr (CmpD src1 src2)); |
|
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|
9824 ins_cost(150); |
|
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|
9825 format %{ "FLD $src1\n\t" |
|
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|
9826 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
9827 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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|
9828 ins_encode( Push_Reg_D(src1), |
|
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diff
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|
9829 OpcP, RegOpc(src2)); |
|
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diff
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|
9830 ins_pipe( pipe_slow ); |
|
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diff
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|
9831 %} |
|
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|
9832 |
| 0 | 9833 // Compare & branch |
| 9834 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9835 predicate(UseSSE<=1); | |
| 9836 match(Set cr (CmpD src1 src2)); | |
| 9837 effect(KILL rax); | |
| 9838 ins_cost(200); | |
| 9839 format %{ "FLD $src1\n\t" | |
| 9840 "FCOMp $src2\n\t" | |
| 9841 "FNSTSW AX\n\t" | |
| 9842 "TEST AX,0x400\n\t" | |
| 9843 "JZ,s flags\n\t" | |
| 9844 "MOV AH,1\t# unordered treat as LT\n" | |
| 9845 "flags:\tSAHF" %} | |
| 9846 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 9847 ins_encode( Push_Reg_D(src1), | |
| 9848 OpcP, RegOpc(src2), | |
| 9849 fpu_flags); | |
| 9850 ins_pipe( pipe_slow ); | |
| 9851 %} | |
| 9852 | |
| 9853 // Compare vs zero into -1,0,1 | |
| 9854 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 9855 predicate(UseSSE<=1); | |
| 9856 match(Set dst (CmpD3 src1 zero)); | |
| 9857 effect(KILL cr, KILL rax); | |
| 9858 ins_cost(280); | |
| 9859 format %{ "FTSTD $dst,$src1" %} | |
| 9860 opcode(0xE4, 0xD9); | |
| 9861 ins_encode( Push_Reg_D(src1), | |
| 9862 OpcS, OpcP, PopFPU, | |
| 9863 CmpF_Result(dst)); | |
| 9864 ins_pipe( pipe_slow ); | |
| 9865 %} | |
| 9866 | |
| 9867 // Compare into -1,0,1 | |
| 9868 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 9869 predicate(UseSSE<=1); | |
| 9870 match(Set dst (CmpD3 src1 src2)); | |
| 9871 effect(KILL cr, KILL rax); | |
| 9872 ins_cost(300); | |
| 9873 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9874 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 9875 ins_encode( Push_Reg_D(src1), | |
| 9876 OpcP, RegOpc(src2), | |
| 9877 CmpF_Result(dst)); | |
| 9878 ins_pipe( pipe_slow ); | |
| 9879 %} | |
| 9880 | |
| 9881 // float compare and set condition codes in EFLAGS by XMM regs | |
| 9882 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ | |
| 9883 predicate(UseSSE>=2); | |
| 9884 match(Set cr (CmpD dst src)); | |
| 9885 effect(KILL rax); | |
| 9886 ins_cost(125); | |
| 9887 format %{ "COMISD $dst,$src\n" | |
| 9888 "\tJNP exit\n" | |
| 9889 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 9890 "\tSAHF\n" | |
| 9891 "exit:\tNOP // avoid branch to branch" %} | |
| 9892 opcode(0x66, 0x0F, 0x2F); | |
| 9893 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); | |
| 9894 ins_pipe( pipe_slow ); | |
| 9895 %} | |
| 9896 | |
|
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9897 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
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|
9898 predicate(UseSSE>=2); |
|
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diff
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|
9899 match(Set cr (CmpD dst src)); |
|
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|
9900 ins_cost(100); |
|
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diff
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|
9901 format %{ "COMISD $dst,$src" %} |
|
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|
9902 opcode(0x66, 0x0F, 0x2F); |
|
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|
9903 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); |
|
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|
9904 ins_pipe( pipe_slow ); |
|
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|
9905 %} |
|
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|
9906 |
| 0 | 9907 // float compare and set condition codes in EFLAGS by XMM regs |
| 9908 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ | |
| 9909 predicate(UseSSE>=2); | |
| 9910 match(Set cr (CmpD dst (LoadD src))); | |
| 9911 effect(KILL rax); | |
| 9912 ins_cost(145); | |
| 9913 format %{ "COMISD $dst,$src\n" | |
| 9914 "\tJNP exit\n" | |
| 9915 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 9916 "\tSAHF\n" | |
| 9917 "exit:\tNOP // avoid branch to branch" %} | |
| 9918 opcode(0x66, 0x0F, 0x2F); | |
| 9919 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); | |
| 9920 ins_pipe( pipe_slow ); | |
| 9921 %} | |
| 9922 | |
|
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9923 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{ |
|
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|
9924 predicate(UseSSE>=2); |
|
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diff
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|
9925 match(Set cr (CmpD dst (LoadD src))); |
|
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|
9926 ins_cost(100); |
|
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|
9927 format %{ "COMISD $dst,$src" %} |
|
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|
9928 opcode(0x66, 0x0F, 0x2F); |
|
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|
9929 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src)); |
|
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|
9930 ins_pipe( pipe_slow ); |
|
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diff
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|
9931 %} |
|
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|
9932 |
| 0 | 9933 // Compare into -1,0,1 in XMM |
| 9934 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ | |
| 9935 predicate(UseSSE>=2); | |
| 9936 match(Set dst (CmpD3 src1 src2)); | |
| 9937 effect(KILL cr); | |
| 9938 ins_cost(255); | |
| 9939 format %{ "XOR $dst,$dst\n" | |
| 9940 "\tCOMISD $src1,$src2\n" | |
| 9941 "\tJP,s nan\n" | |
| 9942 "\tJEQ,s exit\n" | |
| 9943 "\tJA,s inc\n" | |
| 9944 "nan:\tDEC $dst\n" | |
| 9945 "\tJMP,s exit\n" | |
| 9946 "inc:\tINC $dst\n" | |
| 9947 "exit:" | |
| 9948 %} | |
| 9949 opcode(0x66, 0x0F, 0x2F); | |
| 9950 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), | |
| 9951 CmpX_Result(dst)); | |
| 9952 ins_pipe( pipe_slow ); | |
| 9953 %} | |
| 9954 | |
| 9955 // Compare into -1,0,1 in XMM and memory | |
| 9956 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ | |
| 9957 predicate(UseSSE>=2); | |
| 9958 match(Set dst (CmpD3 src1 (LoadD mem))); | |
| 9959 effect(KILL cr); | |
| 9960 ins_cost(275); | |
| 9961 format %{ "COMISD $src1,$mem\n" | |
| 9962 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 9963 "\tJP,s nan\n" | |
| 9964 "\tJEQ,s exit\n" | |
| 9965 "\tJA,s inc\n" | |
| 9966 "nan:\tDEC $dst\n" | |
| 9967 "\tJMP,s exit\n" | |
| 9968 "inc:\tINC $dst\n" | |
| 9969 "exit:" | |
| 9970 %} | |
| 9971 opcode(0x66, 0x0F, 0x2F); | |
| 9972 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), | |
| 9973 LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 9974 ins_pipe( pipe_slow ); | |
| 9975 %} | |
| 9976 | |
| 9977 | |
| 9978 instruct subD_reg(regD dst, regD src) %{ | |
| 9979 predicate (UseSSE <=1); | |
| 9980 match(Set dst (SubD dst src)); | |
| 9981 | |
| 9982 format %{ "FLD $src\n\t" | |
| 9983 "DSUBp $dst,ST" %} | |
| 9984 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9985 ins_cost(150); | |
| 9986 ins_encode( Push_Reg_D(src), | |
| 9987 OpcP, RegOpc(dst) ); | |
| 9988 ins_pipe( fpu_reg_reg ); | |
| 9989 %} | |
| 9990 | |
| 9991 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 9992 predicate (UseSSE <=1); | |
| 9993 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9994 ins_cost(250); | |
| 9995 | |
| 9996 format %{ "FLD $src2\n\t" | |
| 9997 "DSUB ST,$src1\n\t" | |
| 9998 "FSTP_D $dst\t# D-round" %} | |
| 9999 opcode(0xD8, 0x5); | |
| 10000 ins_encode( Push_Reg_D(src2), | |
| 10001 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10002 ins_pipe( fpu_mem_reg_reg ); | |
| 10003 %} | |
| 10004 | |
| 10005 | |
| 10006 instruct subD_reg_mem(regD dst, memory src) %{ | |
| 10007 predicate (UseSSE <=1); | |
| 10008 match(Set dst (SubD dst (LoadD src))); | |
| 10009 ins_cost(150); | |
| 10010 | |
| 10011 format %{ "FLD $src\n\t" | |
| 10012 "DSUBp $dst,ST" %} | |
| 10013 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10014 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10015 OpcP, RegOpc(dst) ); | |
| 10016 ins_pipe( fpu_reg_mem ); | |
| 10017 %} | |
| 10018 | |
| 10019 instruct absD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10020 predicate (UseSSE<=1); | |
| 10021 match(Set dst (AbsD src)); | |
| 10022 ins_cost(100); | |
| 10023 format %{ "FABS" %} | |
| 10024 opcode(0xE1, 0xD9); | |
| 10025 ins_encode( OpcS, OpcP ); | |
| 10026 ins_pipe( fpu_reg_reg ); | |
| 10027 %} | |
| 10028 | |
| 10029 instruct absXD_reg( regXD dst ) %{ | |
| 10030 predicate(UseSSE>=2); | |
| 10031 match(Set dst (AbsD dst)); | |
| 10032 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} | |
| 10033 ins_encode( AbsXD_encoding(dst)); | |
| 10034 ins_pipe( pipe_slow ); | |
| 10035 %} | |
| 10036 | |
| 10037 instruct negD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10038 predicate(UseSSE<=1); | |
| 10039 match(Set dst (NegD src)); | |
| 10040 ins_cost(100); | |
| 10041 format %{ "FCHS" %} | |
| 10042 opcode(0xE0, 0xD9); | |
| 10043 ins_encode( OpcS, OpcP ); | |
| 10044 ins_pipe( fpu_reg_reg ); | |
| 10045 %} | |
| 10046 | |
| 10047 instruct negXD_reg( regXD dst ) %{ | |
| 10048 predicate(UseSSE>=2); | |
| 10049 match(Set dst (NegD dst)); | |
| 10050 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} | |
| 10051 ins_encode %{ | |
| 10052 __ xorpd($dst$$XMMRegister, | |
| 10053 ExternalAddress((address)double_signflip_pool)); | |
| 10054 %} | |
| 10055 ins_pipe( pipe_slow ); | |
| 10056 %} | |
| 10057 | |
| 10058 instruct addD_reg(regD dst, regD src) %{ | |
| 10059 predicate(UseSSE<=1); | |
| 10060 match(Set dst (AddD dst src)); | |
| 10061 format %{ "FLD $src\n\t" | |
| 10062 "DADD $dst,ST" %} | |
| 10063 size(4); | |
| 10064 ins_cost(150); | |
| 10065 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 10066 ins_encode( Push_Reg_D(src), | |
| 10067 OpcP, RegOpc(dst) ); | |
| 10068 ins_pipe( fpu_reg_reg ); | |
| 10069 %} | |
| 10070 | |
| 10071 | |
| 10072 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10073 predicate(UseSSE<=1); | |
| 10074 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 10075 ins_cost(250); | |
| 10076 | |
| 10077 format %{ "FLD $src2\n\t" | |
| 10078 "DADD ST,$src1\n\t" | |
| 10079 "FSTP_D $dst\t# D-round" %} | |
| 10080 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
| 10081 ins_encode( Push_Reg_D(src2), | |
| 10082 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10083 ins_pipe( fpu_mem_reg_reg ); | |
| 10084 %} | |
| 10085 | |
| 10086 | |
| 10087 instruct addD_reg_mem(regD dst, memory src) %{ | |
| 10088 predicate(UseSSE<=1); | |
| 10089 match(Set dst (AddD dst (LoadD src))); | |
| 10090 ins_cost(150); | |
| 10091 | |
| 10092 format %{ "FLD $src\n\t" | |
| 10093 "DADDp $dst,ST" %} | |
| 10094 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10095 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10096 OpcP, RegOpc(dst) ); | |
| 10097 ins_pipe( fpu_reg_mem ); | |
| 10098 %} | |
| 10099 | |
| 10100 // add-to-memory | |
| 10101 instruct addD_mem_reg(memory dst, regD src) %{ | |
| 10102 predicate(UseSSE<=1); | |
| 10103 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 10104 ins_cost(150); | |
| 10105 | |
| 10106 format %{ "FLD_D $dst\n\t" | |
| 10107 "DADD ST,$src\n\t" | |
| 10108 "FST_D $dst" %} | |
| 10109 opcode(0xDD, 0x0); | |
| 10110 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 10111 Opcode(0xD8), RegOpc(src), | |
| 10112 set_instruction_start, | |
| 10113 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 10114 ins_pipe( fpu_reg_mem ); | |
| 10115 %} | |
| 10116 | |
| 10117 instruct addD_reg_imm1(regD dst, immD1 src) %{ | |
| 10118 predicate(UseSSE<=1); | |
| 10119 match(Set dst (AddD dst src)); | |
| 10120 ins_cost(125); | |
| 10121 format %{ "FLD1\n\t" | |
| 10122 "DADDp $dst,ST" %} | |
| 10123 opcode(0xDE, 0x00); | |
| 10124 ins_encode( LdImmD(src), | |
| 10125 OpcP, RegOpc(dst) ); | |
| 10126 ins_pipe( fpu_reg ); | |
| 10127 %} | |
| 10128 | |
| 10129 instruct addD_reg_imm(regD dst, immD src) %{ | |
| 10130 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); | |
| 10131 match(Set dst (AddD dst src)); | |
| 10132 ins_cost(200); | |
| 10133 format %{ "FLD_D [$src]\n\t" | |
| 10134 "DADDp $dst,ST" %} | |
| 10135 opcode(0xDE, 0x00); /* DE /0 */ | |
| 10136 ins_encode( LdImmD(src), | |
| 10137 OpcP, RegOpc(dst)); | |
| 10138 ins_pipe( fpu_reg_mem ); | |
| 10139 %} | |
| 10140 | |
| 10141 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ | |
| 10142 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); | |
| 10143 match(Set dst (RoundDouble (AddD src con))); | |
| 10144 ins_cost(200); | |
| 10145 format %{ "FLD_D [$con]\n\t" | |
| 10146 "DADD ST,$src\n\t" | |
| 10147 "FSTP_D $dst\t# D-round" %} | |
| 10148 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 10149 ins_encode( LdImmD(con), | |
| 10150 OpcP, RegOpc(src), Pop_Mem_D(dst)); | |
| 10151 ins_pipe( fpu_mem_reg_con ); | |
| 10152 %} | |
| 10153 | |
| 10154 // Add two double precision floating point values in xmm | |
| 10155 instruct addXD_reg(regXD dst, regXD src) %{ | |
| 10156 predicate(UseSSE>=2); | |
| 10157 match(Set dst (AddD dst src)); | |
| 10158 format %{ "ADDSD $dst,$src" %} | |
| 10159 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 10160 ins_pipe( pipe_slow ); | |
| 10161 %} | |
| 10162 | |
| 10163 instruct addXD_imm(regXD dst, immXD con) %{ | |
| 10164 predicate(UseSSE>=2); | |
| 10165 match(Set dst (AddD dst con)); | |
| 10166 format %{ "ADDSD $dst,[$con]" %} | |
| 10167 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) ); | |
| 10168 ins_pipe( pipe_slow ); | |
| 10169 %} | |
| 10170 | |
| 10171 instruct addXD_mem(regXD dst, memory mem) %{ | |
| 10172 predicate(UseSSE>=2); | |
| 10173 match(Set dst (AddD dst (LoadD mem))); | |
| 10174 format %{ "ADDSD $dst,$mem" %} | |
| 10175 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); | |
| 10176 ins_pipe( pipe_slow ); | |
| 10177 %} | |
| 10178 | |
| 10179 // Sub two double precision floating point values in xmm | |
| 10180 instruct subXD_reg(regXD dst, regXD src) %{ | |
| 10181 predicate(UseSSE>=2); | |
| 10182 match(Set dst (SubD dst src)); | |
| 10183 format %{ "SUBSD $dst,$src" %} | |
| 10184 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 10185 ins_pipe( pipe_slow ); | |
| 10186 %} | |
| 10187 | |
| 10188 instruct subXD_imm(regXD dst, immXD con) %{ | |
| 10189 predicate(UseSSE>=2); | |
| 10190 match(Set dst (SubD dst con)); | |
| 10191 format %{ "SUBSD $dst,[$con]" %} | |
| 10192 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) ); | |
| 10193 ins_pipe( pipe_slow ); | |
| 10194 %} | |
| 10195 | |
| 10196 instruct subXD_mem(regXD dst, memory mem) %{ | |
| 10197 predicate(UseSSE>=2); | |
| 10198 match(Set dst (SubD dst (LoadD mem))); | |
| 10199 format %{ "SUBSD $dst,$mem" %} | |
| 10200 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 10201 ins_pipe( pipe_slow ); | |
| 10202 %} | |
| 10203 | |
| 10204 // Mul two double precision floating point values in xmm | |
| 10205 instruct mulXD_reg(regXD dst, regXD src) %{ | |
| 10206 predicate(UseSSE>=2); | |
| 10207 match(Set dst (MulD dst src)); | |
| 10208 format %{ "MULSD $dst,$src" %} | |
| 10209 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 10210 ins_pipe( pipe_slow ); | |
| 10211 %} | |
| 10212 | |
| 10213 instruct mulXD_imm(regXD dst, immXD con) %{ | |
| 10214 predicate(UseSSE>=2); | |
| 10215 match(Set dst (MulD dst con)); | |
| 10216 format %{ "MULSD $dst,[$con]" %} | |
| 10217 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) ); | |
| 10218 ins_pipe( pipe_slow ); | |
| 10219 %} | |
| 10220 | |
| 10221 instruct mulXD_mem(regXD dst, memory mem) %{ | |
| 10222 predicate(UseSSE>=2); | |
| 10223 match(Set dst (MulD dst (LoadD mem))); | |
| 10224 format %{ "MULSD $dst,$mem" %} | |
| 10225 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 10226 ins_pipe( pipe_slow ); | |
| 10227 %} | |
| 10228 | |
| 10229 // Div two double precision floating point values in xmm | |
| 10230 instruct divXD_reg(regXD dst, regXD src) %{ | |
| 10231 predicate(UseSSE>=2); | |
| 10232 match(Set dst (DivD dst src)); | |
| 10233 format %{ "DIVSD $dst,$src" %} | |
| 10234 opcode(0xF2, 0x0F, 0x5E); | |
| 10235 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 10236 ins_pipe( pipe_slow ); | |
| 10237 %} | |
| 10238 | |
| 10239 instruct divXD_imm(regXD dst, immXD con) %{ | |
| 10240 predicate(UseSSE>=2); | |
| 10241 match(Set dst (DivD dst con)); | |
| 10242 format %{ "DIVSD $dst,[$con]" %} | |
| 10243 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con)); | |
| 10244 ins_pipe( pipe_slow ); | |
| 10245 %} | |
| 10246 | |
| 10247 instruct divXD_mem(regXD dst, memory mem) %{ | |
| 10248 predicate(UseSSE>=2); | |
| 10249 match(Set dst (DivD dst (LoadD mem))); | |
| 10250 format %{ "DIVSD $dst,$mem" %} | |
| 10251 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 10252 ins_pipe( pipe_slow ); | |
| 10253 %} | |
| 10254 | |
| 10255 | |
| 10256 instruct mulD_reg(regD dst, regD src) %{ | |
| 10257 predicate(UseSSE<=1); | |
| 10258 match(Set dst (MulD dst src)); | |
| 10259 format %{ "FLD $src\n\t" | |
| 10260 "DMULp $dst,ST" %} | |
| 10261 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10262 ins_cost(150); | |
| 10263 ins_encode( Push_Reg_D(src), | |
| 10264 OpcP, RegOpc(dst) ); | |
| 10265 ins_pipe( fpu_reg_reg ); | |
| 10266 %} | |
| 10267 | |
| 10268 // Strict FP instruction biases argument before multiply then | |
| 10269 // biases result to avoid double rounding of subnormals. | |
| 10270 // | |
| 10271 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 10272 // load arg2 | |
| 10273 // multiply scaled arg1 by arg2 | |
| 10274 // rescale product by 2^(15360) | |
| 10275 // | |
| 10276 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10277 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10278 match(Set dst (MulD dst src)); | |
| 10279 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 10280 | |
| 10281 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10282 "DMULp $dst,ST\n\t" | |
| 10283 "FLD $src\n\t" | |
| 10284 "DMULp $dst,ST\n\t" | |
| 10285 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10286 "DMULp $dst,ST\n\t" %} | |
| 10287 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10288 ins_encode( strictfp_bias1(dst), | |
| 10289 Push_Reg_D(src), | |
| 10290 OpcP, RegOpc(dst), | |
| 10291 strictfp_bias2(dst) ); | |
| 10292 ins_pipe( fpu_reg_reg ); | |
| 10293 %} | |
| 10294 | |
| 10295 instruct mulD_reg_imm(regD dst, immD src) %{ | |
| 10296 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); | |
| 10297 match(Set dst (MulD dst src)); | |
| 10298 ins_cost(200); | |
| 10299 format %{ "FLD_D [$src]\n\t" | |
| 10300 "DMULp $dst,ST" %} | |
| 10301 opcode(0xDE, 0x1); /* DE /1 */ | |
| 10302 ins_encode( LdImmD(src), | |
| 10303 OpcP, RegOpc(dst) ); | |
| 10304 ins_pipe( fpu_reg_mem ); | |
| 10305 %} | |
| 10306 | |
| 10307 | |
| 10308 instruct mulD_reg_mem(regD dst, memory src) %{ | |
| 10309 predicate( UseSSE<=1 ); | |
| 10310 match(Set dst (MulD dst (LoadD src))); | |
| 10311 ins_cost(200); | |
| 10312 format %{ "FLD_D $src\n\t" | |
| 10313 "DMULp $dst,ST" %} | |
| 10314 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 10315 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10316 OpcP, RegOpc(dst) ); | |
| 10317 ins_pipe( fpu_reg_mem ); | |
| 10318 %} | |
| 10319 | |
| 10320 // | |
| 10321 // Cisc-alternate to reg-reg multiply | |
| 10322 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ | |
| 10323 predicate( UseSSE<=1 ); | |
| 10324 match(Set dst (MulD src (LoadD mem))); | |
| 10325 ins_cost(250); | |
| 10326 format %{ "FLD_D $mem\n\t" | |
| 10327 "DMUL ST,$src\n\t" | |
| 10328 "FSTP_D $dst" %} | |
| 10329 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 10330 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
| 10331 OpcReg_F(src), | |
| 10332 Pop_Reg_D(dst) ); | |
| 10333 ins_pipe( fpu_reg_reg_mem ); | |
| 10334 %} | |
| 10335 | |
| 10336 | |
| 10337 // MACRO3 -- addD a mulD | |
| 10338 // This instruction is a '2-address' instruction in that the result goes | |
| 10339 // back to src2. This eliminates a move from the macro; possibly the | |
| 10340 // register allocator will have to add it back (and maybe not). | |
| 10341 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10342 predicate( UseSSE<=1 ); | |
| 10343 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 10344 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10345 "DMUL ST,$src1\n\t" | |
| 10346 "DADDp $src2,ST" %} | |
| 10347 ins_cost(250); | |
| 10348 opcode(0xDD); /* LoadD DD /0 */ | |
| 10349 ins_encode( Push_Reg_F(src0), | |
| 10350 FMul_ST_reg(src1), | |
| 10351 FAddP_reg_ST(src2) ); | |
| 10352 ins_pipe( fpu_reg_reg_reg ); | |
| 10353 %} | |
| 10354 | |
| 10355 | |
| 10356 // MACRO3 -- subD a mulD | |
| 10357 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10358 predicate( UseSSE<=1 ); | |
| 10359 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 10360 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10361 "DMUL ST,$src1\n\t" | |
| 10362 "DSUBRp $src2,ST" %} | |
| 10363 ins_cost(250); | |
| 10364 ins_encode( Push_Reg_F(src0), | |
| 10365 FMul_ST_reg(src1), | |
| 10366 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 10367 ins_pipe( fpu_reg_reg_reg ); | |
| 10368 %} | |
| 10369 | |
| 10370 | |
| 10371 instruct divD_reg(regD dst, regD src) %{ | |
| 10372 predicate( UseSSE<=1 ); | |
| 10373 match(Set dst (DivD dst src)); | |
| 10374 | |
| 10375 format %{ "FLD $src\n\t" | |
| 10376 "FDIVp $dst,ST" %} | |
| 10377 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10378 ins_cost(150); | |
| 10379 ins_encode( Push_Reg_D(src), | |
| 10380 OpcP, RegOpc(dst) ); | |
| 10381 ins_pipe( fpu_reg_reg ); | |
| 10382 %} | |
| 10383 | |
| 10384 // Strict FP instruction biases argument before division then | |
| 10385 // biases result, to avoid double rounding of subnormals. | |
| 10386 // | |
| 10387 // scale dividend by multiplying dividend by 2^(-15360) | |
| 10388 // load divisor | |
| 10389 // divide scaled dividend by divisor | |
| 10390 // rescale quotient by 2^(15360) | |
| 10391 // | |
| 10392 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10393 predicate (UseSSE<=1); | |
| 10394 match(Set dst (DivD dst src)); | |
| 10395 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10396 ins_cost(01); | |
| 10397 | |
| 10398 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10399 "DMULp $dst,ST\n\t" | |
| 10400 "FLD $src\n\t" | |
| 10401 "FDIVp $dst,ST\n\t" | |
| 10402 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10403 "DMULp $dst,ST\n\t" %} | |
| 10404 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10405 ins_encode( strictfp_bias1(dst), | |
| 10406 Push_Reg_D(src), | |
| 10407 OpcP, RegOpc(dst), | |
| 10408 strictfp_bias2(dst) ); | |
| 10409 ins_pipe( fpu_reg_reg ); | |
| 10410 %} | |
| 10411 | |
| 10412 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10413 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); | |
| 10414 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 10415 | |
| 10416 format %{ "FLD $src1\n\t" | |
| 10417 "FDIV ST,$src2\n\t" | |
| 10418 "FSTP_D $dst\t# D-round" %} | |
| 10419 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
| 10420 ins_encode( Push_Reg_D(src1), | |
| 10421 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); | |
| 10422 ins_pipe( fpu_mem_reg_reg ); | |
| 10423 %} | |
| 10424 | |
| 10425 | |
| 10426 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ | |
| 10427 predicate(UseSSE<=1); | |
| 10428 match(Set dst (ModD dst src)); | |
| 10429 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 10430 | |
| 10431 format %{ "DMOD $dst,$src" %} | |
| 10432 ins_cost(250); | |
| 10433 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 10434 emitModD(), | |
| 10435 Push_Result_Mod_D(src), | |
| 10436 Pop_Reg_D(dst)); | |
| 10437 ins_pipe( pipe_slow ); | |
| 10438 %} | |
| 10439 | |
| 10440 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 10441 predicate(UseSSE>=2); | |
| 10442 match(Set dst (ModD src0 src1)); | |
| 10443 effect(KILL rax, KILL cr); | |
| 10444 | |
| 10445 format %{ "SUB ESP,8\t # DMOD\n" | |
| 10446 "\tMOVSD [ESP+0],$src1\n" | |
| 10447 "\tFLD_D [ESP+0]\n" | |
| 10448 "\tMOVSD [ESP+0],$src0\n" | |
| 10449 "\tFLD_D [ESP+0]\n" | |
| 10450 "loop:\tFPREM\n" | |
| 10451 "\tFWAIT\n" | |
| 10452 "\tFNSTSW AX\n" | |
| 10453 "\tSAHF\n" | |
| 10454 "\tJP loop\n" | |
| 10455 "\tFSTP_D [ESP+0]\n" | |
| 10456 "\tMOVSD $dst,[ESP+0]\n" | |
| 10457 "\tADD ESP,8\n" | |
| 10458 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10459 %} | |
| 10460 ins_cost(250); | |
| 10461 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); | |
| 10462 ins_pipe( pipe_slow ); | |
| 10463 %} | |
| 10464 | |
| 10465 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10466 predicate (UseSSE<=1); | |
| 10467 match(Set dst (SinD src)); | |
| 10468 ins_cost(1800); | |
| 10469 format %{ "DSIN $dst" %} | |
| 10470 opcode(0xD9, 0xFE); | |
| 10471 ins_encode( OpcP, OpcS ); | |
| 10472 ins_pipe( pipe_slow ); | |
| 10473 %} | |
| 10474 | |
| 10475 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10476 predicate (UseSSE>=2); | |
| 10477 match(Set dst (SinD dst)); | |
| 10478 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10479 ins_cost(1800); | |
| 10480 format %{ "DSIN $dst" %} | |
| 10481 opcode(0xD9, 0xFE); | |
| 10482 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10483 ins_pipe( pipe_slow ); | |
| 10484 %} | |
| 10485 | |
| 10486 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10487 predicate (UseSSE<=1); | |
| 10488 match(Set dst (CosD src)); | |
| 10489 ins_cost(1800); | |
| 10490 format %{ "DCOS $dst" %} | |
| 10491 opcode(0xD9, 0xFF); | |
| 10492 ins_encode( OpcP, OpcS ); | |
| 10493 ins_pipe( pipe_slow ); | |
| 10494 %} | |
| 10495 | |
| 10496 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10497 predicate (UseSSE>=2); | |
| 10498 match(Set dst (CosD dst)); | |
| 10499 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10500 ins_cost(1800); | |
| 10501 format %{ "DCOS $dst" %} | |
| 10502 opcode(0xD9, 0xFF); | |
| 10503 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10504 ins_pipe( pipe_slow ); | |
| 10505 %} | |
| 10506 | |
| 10507 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10508 predicate (UseSSE<=1); | |
| 10509 match(Set dst(TanD src)); | |
| 10510 format %{ "DTAN $dst" %} | |
| 10511 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10512 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10513 ins_pipe( pipe_slow ); | |
| 10514 %} | |
| 10515 | |
| 10516 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10517 predicate (UseSSE>=2); | |
| 10518 match(Set dst(TanD dst)); | |
| 10519 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10520 format %{ "DTAN $dst" %} | |
| 10521 ins_encode( Push_SrcXD(dst), | |
| 10522 Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10523 Opcode(0xDD), Opcode(0xD8), // fstp st | |
| 10524 Push_ResultXD(dst) ); | |
| 10525 ins_pipe( pipe_slow ); | |
| 10526 %} | |
| 10527 | |
| 10528 instruct atanD_reg(regD dst, regD src) %{ | |
| 10529 predicate (UseSSE<=1); | |
| 10530 match(Set dst(AtanD dst src)); | |
| 10531 format %{ "DATA $dst,$src" %} | |
| 10532 opcode(0xD9, 0xF3); | |
| 10533 ins_encode( Push_Reg_D(src), | |
| 10534 OpcP, OpcS, RegOpc(dst) ); | |
| 10535 ins_pipe( pipe_slow ); | |
| 10536 %} | |
| 10537 | |
| 10538 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10539 predicate (UseSSE>=2); | |
| 10540 match(Set dst(AtanD dst src)); | |
| 10541 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10542 format %{ "DATA $dst,$src" %} | |
| 10543 opcode(0xD9, 0xF3); | |
| 10544 ins_encode( Push_SrcXD(src), | |
| 10545 OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10546 ins_pipe( pipe_slow ); | |
| 10547 %} | |
| 10548 | |
| 10549 instruct sqrtD_reg(regD dst, regD src) %{ | |
| 10550 predicate (UseSSE<=1); | |
| 10551 match(Set dst (SqrtD src)); | |
| 10552 format %{ "DSQRT $dst,$src" %} | |
| 10553 opcode(0xFA, 0xD9); | |
| 10554 ins_encode( Push_Reg_D(src), | |
| 10555 OpcS, OpcP, Pop_Reg_D(dst) ); | |
| 10556 ins_pipe( pipe_slow ); | |
| 10557 %} | |
| 10558 | |
| 10559 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10560 predicate (UseSSE<=1); | |
| 10561 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
| 10562 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10563 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10564 "FLD_D $X\n\t" | |
| 10565 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10566 | |
| 10567 "FDUP \t\t\t# Q Q\n\t" | |
| 10568 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10569 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10570 "FISTP dword [ESP]\n\t" | |
| 10571 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10572 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10573 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10574 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10575 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10576 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10577 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10578 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10579 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10580 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10581 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10582 "MOV [ESP+0],0\n\t" | |
| 10583 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10584 | |
| 10585 "ADD ESP,8" | |
| 10586 %} | |
| 10587 ins_encode( push_stack_temp_qword, | |
| 10588 Push_Reg_D(X), | |
| 10589 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10590 pow_exp_core_encoding, | |
| 10591 pop_stack_temp_qword); | |
| 10592 ins_pipe( pipe_slow ); | |
| 10593 %} | |
| 10594 | |
| 10595 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ | |
| 10596 predicate (UseSSE>=2); | |
| 10597 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
| 10598 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); | |
| 10599 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10600 "MOVSD [ESP],$src1\n\t" | |
| 10601 "FLD FPR1,$src1\n\t" | |
| 10602 "MOVSD [ESP],$src0\n\t" | |
| 10603 "FLD FPR1,$src0\n\t" | |
| 10604 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10605 | |
| 10606 "FDUP \t\t\t# Q Q\n\t" | |
| 10607 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10608 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10609 "FISTP dword [ESP]\n\t" | |
| 10610 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10611 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10612 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10613 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10614 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10615 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10616 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10617 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10618 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10619 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10620 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10621 "MOV [ESP+0],0\n\t" | |
| 10622 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10623 | |
| 10624 "FST_D [ESP]\n\t" | |
| 10625 "MOVSD $dst,[ESP]\n\t" | |
| 10626 "ADD ESP,8" | |
| 10627 %} | |
| 10628 ins_encode( push_stack_temp_qword, | |
| 10629 push_xmm_to_fpr1(src1), | |
| 10630 push_xmm_to_fpr1(src0), | |
| 10631 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10632 pow_exp_core_encoding, | |
| 10633 Push_ResultXD(dst) ); | |
| 10634 ins_pipe( pipe_slow ); | |
| 10635 %} | |
| 10636 | |
| 10637 | |
| 10638 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10639 predicate (UseSSE<=1); | |
| 10640 match(Set dpr1 (ExpD dpr1)); | |
| 10641 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10642 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" | |
| 10643 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10644 "FMULP \t\t\t# Q=X*log2(e)\n\t" | |
| 10645 | |
| 10646 "FDUP \t\t\t# Q Q\n\t" | |
| 10647 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10648 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10649 "FISTP dword [ESP]\n\t" | |
| 10650 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10651 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10652 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10653 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10654 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10655 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10656 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10657 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10658 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10659 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10660 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10661 "MOV [ESP+0],0\n\t" | |
| 10662 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10663 | |
| 10664 "ADD ESP,8" | |
| 10665 %} | |
| 10666 ins_encode( push_stack_temp_qword, | |
| 10667 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10668 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10669 pow_exp_core_encoding, | |
| 10670 pop_stack_temp_qword); | |
| 10671 ins_pipe( pipe_slow ); | |
| 10672 %} | |
| 10673 | |
| 10674 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10675 predicate (UseSSE>=2); | |
| 10676 match(Set dst (ExpD src)); | |
| 10677 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); | |
| 10678 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" | |
| 10679 "MOVSD [ESP],$src\n\t" | |
| 10680 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10681 "FMULP \t\t\t# Q=X*log2(e) X\n\t" | |
| 10682 | |
| 10683 "FDUP \t\t\t# Q Q\n\t" | |
| 10684 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10685 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10686 "FISTP dword [ESP]\n\t" | |
| 10687 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10688 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10689 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10690 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10691 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10692 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10693 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10694 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10695 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10696 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10697 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10698 "MOV [ESP+0],0\n\t" | |
| 10699 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10700 | |
| 10701 "FST_D [ESP]\n\t" | |
| 10702 "MOVSD $dst,[ESP]\n\t" | |
| 10703 "ADD ESP,8" | |
| 10704 %} | |
| 10705 ins_encode( Push_SrcXD(src), | |
| 10706 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10707 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10708 pow_exp_core_encoding, | |
| 10709 Push_ResultXD(dst) ); | |
| 10710 ins_pipe( pipe_slow ); | |
| 10711 %} | |
| 10712 | |
| 10713 | |
| 10714 | |
| 10715 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10716 predicate (UseSSE<=1); | |
| 10717 // The source Double operand on FPU stack | |
| 10718 match(Set dst (Log10D src)); | |
| 10719 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10720 // fxch ; swap ST(0) with ST(1) | |
| 10721 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10722 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10723 "FXCH \n\t" | |
| 10724 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10725 %} | |
| 10726 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10727 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10728 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10729 | |
| 10730 ins_pipe( pipe_slow ); | |
| 10731 %} | |
| 10732 | |
| 10733 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10734 predicate (UseSSE>=2); | |
| 10735 effect(KILL cr); | |
| 10736 match(Set dst (Log10D src)); | |
| 10737 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10738 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10739 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10740 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10741 %} | |
| 10742 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10743 Push_SrcXD(src), | |
| 10744 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10745 Push_ResultXD(dst)); | |
| 10746 | |
| 10747 ins_pipe( pipe_slow ); | |
| 10748 %} | |
| 10749 | |
| 10750 instruct logD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10751 predicate (UseSSE<=1); | |
| 10752 // The source Double operand on FPU stack | |
| 10753 match(Set dst (LogD src)); | |
| 10754 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10755 // fxch ; swap ST(0) with ST(1) | |
| 10756 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10757 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10758 "FXCH \n\t" | |
| 10759 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10760 %} | |
| 10761 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10762 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10763 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10764 | |
| 10765 ins_pipe( pipe_slow ); | |
| 10766 %} | |
| 10767 | |
| 10768 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10769 predicate (UseSSE>=2); | |
| 10770 effect(KILL cr); | |
| 10771 // The source and result Double operands in XMM registers | |
| 10772 match(Set dst (LogD src)); | |
| 10773 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10774 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10775 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10776 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10777 %} | |
| 10778 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10779 Push_SrcXD(src), | |
| 10780 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10781 Push_ResultXD(dst)); | |
| 10782 ins_pipe( pipe_slow ); | |
| 10783 %} | |
| 10784 | |
| 10785 //-------------Float Instructions------------------------------- | |
| 10786 // Float Math | |
| 10787 | |
| 10788 // Code for float compare: | |
| 10789 // fcompp(); | |
| 10790 // fwait(); fnstsw_ax(); | |
| 10791 // sahf(); | |
| 10792 // movl(dst, unordered_result); | |
| 10793 // jcc(Assembler::parity, exit); | |
| 10794 // movl(dst, less_result); | |
| 10795 // jcc(Assembler::below, exit); | |
| 10796 // movl(dst, equal_result); | |
| 10797 // jcc(Assembler::equal, exit); | |
| 10798 // movl(dst, greater_result); | |
| 10799 // exit: | |
| 10800 | |
| 10801 // P6 version of float compare, sets condition codes in EFLAGS | |
| 10802 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 10803 predicate(VM_Version::supports_cmov() && UseSSE == 0); | |
| 10804 match(Set cr (CmpF src1 src2)); | |
| 10805 effect(KILL rax); | |
| 10806 ins_cost(150); | |
| 10807 format %{ "FLD $src1\n\t" | |
| 10808 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10809 "JNP exit\n\t" | |
| 10810 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10811 "SAHF\n" | |
| 10812 "exit:\tNOP // avoid branch to branch" %} | |
| 10813 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 10814 ins_encode( Push_Reg_D(src1), | |
| 10815 OpcP, RegOpc(src2), | |
| 10816 cmpF_P6_fixup ); | |
| 10817 ins_pipe( pipe_slow ); | |
| 10818 %} | |
| 10819 | |
|
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10820 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
10821 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
4d9884b01ba6
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|
10822 match(Set cr (CmpF src1 src2)); |
|
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diff
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|
10823 ins_cost(100); |
|
4d9884b01ba6
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403
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|
10824 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
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|
10825 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
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diff
changeset
|
10826 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4d9884b01ba6
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|
10827 ins_encode( Push_Reg_D(src1), |
|
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403
diff
changeset
|
10828 OpcP, RegOpc(src2)); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
10829 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
10830 %} |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
10831 |
| 0 | 10832 |
| 10833 // Compare & branch | |
| 10834 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 10835 predicate(UseSSE == 0); | |
| 10836 match(Set cr (CmpF src1 src2)); | |
| 10837 effect(KILL rax); | |
| 10838 ins_cost(200); | |
| 10839 format %{ "FLD $src1\n\t" | |
| 10840 "FCOMp $src2\n\t" | |
| 10841 "FNSTSW AX\n\t" | |
| 10842 "TEST AX,0x400\n\t" | |
| 10843 "JZ,s flags\n\t" | |
| 10844 "MOV AH,1\t# unordered treat as LT\n" | |
| 10845 "flags:\tSAHF" %} | |
| 10846 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10847 ins_encode( Push_Reg_D(src1), | |
| 10848 OpcP, RegOpc(src2), | |
| 10849 fpu_flags); | |
| 10850 ins_pipe( pipe_slow ); | |
| 10851 %} | |
| 10852 | |
| 10853 // Compare vs zero into -1,0,1 | |
| 10854 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 10855 predicate(UseSSE == 0); | |
| 10856 match(Set dst (CmpF3 src1 zero)); | |
| 10857 effect(KILL cr, KILL rax); | |
| 10858 ins_cost(280); | |
| 10859 format %{ "FTSTF $dst,$src1" %} | |
| 10860 opcode(0xE4, 0xD9); | |
| 10861 ins_encode( Push_Reg_D(src1), | |
| 10862 OpcS, OpcP, PopFPU, | |
| 10863 CmpF_Result(dst)); | |
| 10864 ins_pipe( pipe_slow ); | |
| 10865 %} | |
| 10866 | |
| 10867 // Compare into -1,0,1 | |
| 10868 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 10869 predicate(UseSSE == 0); | |
| 10870 match(Set dst (CmpF3 src1 src2)); | |
| 10871 effect(KILL cr, KILL rax); | |
| 10872 ins_cost(300); | |
| 10873 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10874 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10875 ins_encode( Push_Reg_D(src1), | |
| 10876 OpcP, RegOpc(src2), | |
| 10877 CmpF_Result(dst)); | |
| 10878 ins_pipe( pipe_slow ); | |
| 10879 %} | |
| 10880 | |
| 10881 // float compare and set condition codes in EFLAGS by XMM regs | |
| 10882 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ | |
| 10883 predicate(UseSSE>=1); | |
| 10884 match(Set cr (CmpF dst src)); | |
| 10885 effect(KILL rax); | |
| 10886 ins_cost(145); | |
| 10887 format %{ "COMISS $dst,$src\n" | |
| 10888 "\tJNP exit\n" | |
| 10889 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10890 "\tSAHF\n" | |
| 10891 "exit:\tNOP // avoid branch to branch" %} | |
| 10892 opcode(0x0F, 0x2F); | |
| 10893 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); | |
| 10894 ins_pipe( pipe_slow ); | |
| 10895 %} | |
| 10896 | |
|
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|
10897 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
10898 predicate(UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10899 match(Set cr (CmpF dst src)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10900 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10901 format %{ "COMISS $dst,$src" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10902 opcode(0x0F, 0x2F); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
10903 ins_encode(OpcP, OpcS, RegReg(dst, src)); |
|
4d9884b01ba6
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10904 ins_pipe( pipe_slow ); |
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10905 %} |
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10906 |
| 0 | 10907 // float compare and set condition codes in EFLAGS by XMM regs |
| 10908 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ | |
| 10909 predicate(UseSSE>=1); | |
| 10910 match(Set cr (CmpF dst (LoadF src))); | |
| 10911 effect(KILL rax); | |
| 10912 ins_cost(165); | |
| 10913 format %{ "COMISS $dst,$src\n" | |
| 10914 "\tJNP exit\n" | |
| 10915 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10916 "\tSAHF\n" | |
| 10917 "exit:\tNOP // avoid branch to branch" %} | |
| 10918 opcode(0x0F, 0x2F); | |
| 10919 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); | |
| 10920 ins_pipe( pipe_slow ); | |
| 10921 %} | |
| 10922 | |
|
415
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10923 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{ |
|
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10924 predicate(UseSSE>=1); |
|
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10925 match(Set cr (CmpF dst (LoadF src))); |
|
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10926 ins_cost(100); |
|
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10927 format %{ "COMISS $dst,$src" %} |
|
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10928 opcode(0x0F, 0x2F); |
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10929 ins_encode(OpcP, OpcS, RegMem(dst, src)); |
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10930 ins_pipe( pipe_slow ); |
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10931 %} |
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10932 |
| 0 | 10933 // Compare into -1,0,1 in XMM |
| 10934 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ | |
| 10935 predicate(UseSSE>=1); | |
| 10936 match(Set dst (CmpF3 src1 src2)); | |
| 10937 effect(KILL cr); | |
| 10938 ins_cost(255); | |
| 10939 format %{ "XOR $dst,$dst\n" | |
| 10940 "\tCOMISS $src1,$src2\n" | |
| 10941 "\tJP,s nan\n" | |
| 10942 "\tJEQ,s exit\n" | |
| 10943 "\tJA,s inc\n" | |
| 10944 "nan:\tDEC $dst\n" | |
| 10945 "\tJMP,s exit\n" | |
| 10946 "inc:\tINC $dst\n" | |
| 10947 "exit:" | |
| 10948 %} | |
| 10949 opcode(0x0F, 0x2F); | |
| 10950 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); | |
| 10951 ins_pipe( pipe_slow ); | |
| 10952 %} | |
| 10953 | |
| 10954 // Compare into -1,0,1 in XMM and memory | |
| 10955 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ | |
| 10956 predicate(UseSSE>=1); | |
| 10957 match(Set dst (CmpF3 src1 (LoadF mem))); | |
| 10958 effect(KILL cr); | |
| 10959 ins_cost(275); | |
| 10960 format %{ "COMISS $src1,$mem\n" | |
| 10961 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 10962 "\tJP,s nan\n" | |
| 10963 "\tJEQ,s exit\n" | |
| 10964 "\tJA,s inc\n" | |
| 10965 "nan:\tDEC $dst\n" | |
| 10966 "\tJMP,s exit\n" | |
| 10967 "inc:\tINC $dst\n" | |
| 10968 "exit:" | |
| 10969 %} | |
| 10970 opcode(0x0F, 0x2F); | |
| 10971 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 10972 ins_pipe( pipe_slow ); | |
| 10973 %} | |
| 10974 | |
| 10975 // Spill to obtain 24-bit precision | |
| 10976 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 10977 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 10978 match(Set dst (SubF src1 src2)); | |
| 10979 | |
| 10980 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10981 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
| 10982 ins_encode( Push_Reg_F(src1), | |
| 10983 OpcReg_F(src2), | |
| 10984 Pop_Mem_F(dst) ); | |
| 10985 ins_pipe( fpu_mem_reg_reg ); | |
| 10986 %} | |
| 10987 // | |
| 10988 // This instruction does not round to 24-bits | |
| 10989 instruct subF_reg(regF dst, regF src) %{ | |
| 10990 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 10991 match(Set dst (SubF dst src)); | |
| 10992 | |
| 10993 format %{ "FSUB $dst,$src" %} | |
| 10994 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 10995 ins_encode( Push_Reg_F(src), | |
| 10996 OpcP, RegOpc(dst) ); | |
| 10997 ins_pipe( fpu_reg_reg ); | |
| 10998 %} | |
| 10999 | |
| 11000 // Spill to obtain 24-bit precision | |
| 11001 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11002 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11003 match(Set dst (AddF src1 src2)); | |
| 11004 | |
| 11005 format %{ "FADD $dst,$src1,$src2" %} | |
| 11006 opcode(0xD8, 0x0); /* D8 C0+i */ | |
| 11007 ins_encode( Push_Reg_F(src2), | |
| 11008 OpcReg_F(src1), | |
| 11009 Pop_Mem_F(dst) ); | |
| 11010 ins_pipe( fpu_mem_reg_reg ); | |
| 11011 %} | |
| 11012 // | |
| 11013 // This instruction does not round to 24-bits | |
| 11014 instruct addF_reg(regF dst, regF src) %{ | |
| 11015 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11016 match(Set dst (AddF dst src)); | |
| 11017 | |
| 11018 format %{ "FLD $src\n\t" | |
| 11019 "FADDp $dst,ST" %} | |
| 11020 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 11021 ins_encode( Push_Reg_F(src), | |
| 11022 OpcP, RegOpc(dst) ); | |
| 11023 ins_pipe( fpu_reg_reg ); | |
| 11024 %} | |
| 11025 | |
| 11026 // Add two single precision floating point values in xmm | |
| 11027 instruct addX_reg(regX dst, regX src) %{ | |
| 11028 predicate(UseSSE>=1); | |
| 11029 match(Set dst (AddF dst src)); | |
| 11030 format %{ "ADDSS $dst,$src" %} | |
| 11031 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 11032 ins_pipe( pipe_slow ); | |
| 11033 %} | |
| 11034 | |
| 11035 instruct addX_imm(regX dst, immXF con) %{ | |
| 11036 predicate(UseSSE>=1); | |
| 11037 match(Set dst (AddF dst con)); | |
| 11038 format %{ "ADDSS $dst,[$con]" %} | |
| 11039 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) ); | |
| 11040 ins_pipe( pipe_slow ); | |
| 11041 %} | |
| 11042 | |
| 11043 instruct addX_mem(regX dst, memory mem) %{ | |
| 11044 predicate(UseSSE>=1); | |
| 11045 match(Set dst (AddF dst (LoadF mem))); | |
| 11046 format %{ "ADDSS $dst,$mem" %} | |
| 11047 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); | |
| 11048 ins_pipe( pipe_slow ); | |
| 11049 %} | |
| 11050 | |
| 11051 // Subtract two single precision floating point values in xmm | |
| 11052 instruct subX_reg(regX dst, regX src) %{ | |
| 11053 predicate(UseSSE>=1); | |
| 11054 match(Set dst (SubF dst src)); | |
| 11055 format %{ "SUBSS $dst,$src" %} | |
| 11056 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 11057 ins_pipe( pipe_slow ); | |
| 11058 %} | |
| 11059 | |
| 11060 instruct subX_imm(regX dst, immXF con) %{ | |
| 11061 predicate(UseSSE>=1); | |
| 11062 match(Set dst (SubF dst con)); | |
| 11063 format %{ "SUBSS $dst,[$con]" %} | |
| 11064 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) ); | |
| 11065 ins_pipe( pipe_slow ); | |
| 11066 %} | |
| 11067 | |
| 11068 instruct subX_mem(regX dst, memory mem) %{ | |
| 11069 predicate(UseSSE>=1); | |
| 11070 match(Set dst (SubF dst (LoadF mem))); | |
| 11071 format %{ "SUBSS $dst,$mem" %} | |
| 11072 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 11073 ins_pipe( pipe_slow ); | |
| 11074 %} | |
| 11075 | |
| 11076 // Multiply two single precision floating point values in xmm | |
| 11077 instruct mulX_reg(regX dst, regX src) %{ | |
| 11078 predicate(UseSSE>=1); | |
| 11079 match(Set dst (MulF dst src)); | |
| 11080 format %{ "MULSS $dst,$src" %} | |
| 11081 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 11082 ins_pipe( pipe_slow ); | |
| 11083 %} | |
| 11084 | |
| 11085 instruct mulX_imm(regX dst, immXF con) %{ | |
| 11086 predicate(UseSSE>=1); | |
| 11087 match(Set dst (MulF dst con)); | |
| 11088 format %{ "MULSS $dst,[$con]" %} | |
| 11089 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) ); | |
| 11090 ins_pipe( pipe_slow ); | |
| 11091 %} | |
| 11092 | |
| 11093 instruct mulX_mem(regX dst, memory mem) %{ | |
| 11094 predicate(UseSSE>=1); | |
| 11095 match(Set dst (MulF dst (LoadF mem))); | |
| 11096 format %{ "MULSS $dst,$mem" %} | |
| 11097 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 11098 ins_pipe( pipe_slow ); | |
| 11099 %} | |
| 11100 | |
| 11101 // Divide two single precision floating point values in xmm | |
| 11102 instruct divX_reg(regX dst, regX src) %{ | |
| 11103 predicate(UseSSE>=1); | |
| 11104 match(Set dst (DivF dst src)); | |
| 11105 format %{ "DIVSS $dst,$src" %} | |
| 11106 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 11107 ins_pipe( pipe_slow ); | |
| 11108 %} | |
| 11109 | |
| 11110 instruct divX_imm(regX dst, immXF con) %{ | |
| 11111 predicate(UseSSE>=1); | |
| 11112 match(Set dst (DivF dst con)); | |
| 11113 format %{ "DIVSS $dst,[$con]" %} | |
| 11114 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) ); | |
| 11115 ins_pipe( pipe_slow ); | |
| 11116 %} | |
| 11117 | |
| 11118 instruct divX_mem(regX dst, memory mem) %{ | |
| 11119 predicate(UseSSE>=1); | |
| 11120 match(Set dst (DivF dst (LoadF mem))); | |
| 11121 format %{ "DIVSS $dst,$mem" %} | |
| 11122 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 11123 ins_pipe( pipe_slow ); | |
| 11124 %} | |
| 11125 | |
| 11126 // Get the square root of a single precision floating point values in xmm | |
| 11127 instruct sqrtX_reg(regX dst, regX src) %{ | |
| 11128 predicate(UseSSE>=1); | |
| 11129 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 11130 format %{ "SQRTSS $dst,$src" %} | |
| 11131 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11132 ins_pipe( pipe_slow ); | |
| 11133 %} | |
| 11134 | |
| 11135 instruct sqrtX_mem(regX dst, memory mem) %{ | |
| 11136 predicate(UseSSE>=1); | |
| 11137 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); | |
| 11138 format %{ "SQRTSS $dst,$mem" %} | |
| 11139 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11140 ins_pipe( pipe_slow ); | |
| 11141 %} | |
| 11142 | |
| 11143 // Get the square root of a double precision floating point values in xmm | |
| 11144 instruct sqrtXD_reg(regXD dst, regXD src) %{ | |
| 11145 predicate(UseSSE>=2); | |
| 11146 match(Set dst (SqrtD src)); | |
| 11147 format %{ "SQRTSD $dst,$src" %} | |
| 11148 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11149 ins_pipe( pipe_slow ); | |
| 11150 %} | |
| 11151 | |
| 11152 instruct sqrtXD_mem(regXD dst, memory mem) %{ | |
| 11153 predicate(UseSSE>=2); | |
| 11154 match(Set dst (SqrtD (LoadD mem))); | |
| 11155 format %{ "SQRTSD $dst,$mem" %} | |
| 11156 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11157 ins_pipe( pipe_slow ); | |
| 11158 %} | |
| 11159 | |
| 11160 instruct absF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11161 predicate(UseSSE==0); | |
| 11162 match(Set dst (AbsF src)); | |
| 11163 ins_cost(100); | |
| 11164 format %{ "FABS" %} | |
| 11165 opcode(0xE1, 0xD9); | |
| 11166 ins_encode( OpcS, OpcP ); | |
| 11167 ins_pipe( fpu_reg_reg ); | |
| 11168 %} | |
| 11169 | |
| 11170 instruct absX_reg(regX dst ) %{ | |
| 11171 predicate(UseSSE>=1); | |
| 11172 match(Set dst (AbsF dst)); | |
| 11173 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} | |
| 11174 ins_encode( AbsXF_encoding(dst)); | |
| 11175 ins_pipe( pipe_slow ); | |
| 11176 %} | |
| 11177 | |
| 11178 instruct negF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11179 predicate(UseSSE==0); | |
| 11180 match(Set dst (NegF src)); | |
| 11181 ins_cost(100); | |
| 11182 format %{ "FCHS" %} | |
| 11183 opcode(0xE0, 0xD9); | |
| 11184 ins_encode( OpcS, OpcP ); | |
| 11185 ins_pipe( fpu_reg_reg ); | |
| 11186 %} | |
| 11187 | |
| 11188 instruct negX_reg( regX dst ) %{ | |
| 11189 predicate(UseSSE>=1); | |
| 11190 match(Set dst (NegF dst)); | |
| 11191 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} | |
| 11192 ins_encode( NegXF_encoding(dst)); | |
| 11193 ins_pipe( pipe_slow ); | |
| 11194 %} | |
| 11195 | |
| 11196 // Cisc-alternate to addF_reg | |
| 11197 // Spill to obtain 24-bit precision | |
| 11198 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11199 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11200 match(Set dst (AddF src1 (LoadF src2))); | |
| 11201 | |
| 11202 format %{ "FLD $src2\n\t" | |
| 11203 "FADD ST,$src1\n\t" | |
| 11204 "FSTP_S $dst" %} | |
| 11205 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11206 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11207 OpcReg_F(src1), | |
| 11208 Pop_Mem_F(dst) ); | |
| 11209 ins_pipe( fpu_mem_reg_mem ); | |
| 11210 %} | |
| 11211 // | |
| 11212 // Cisc-alternate to addF_reg | |
| 11213 // This instruction does not round to 24-bits | |
| 11214 instruct addF_reg_mem(regF dst, memory src) %{ | |
| 11215 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11216 match(Set dst (AddF dst (LoadF src))); | |
| 11217 | |
| 11218 format %{ "FADD $dst,$src" %} | |
| 11219 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 11220 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 11221 OpcP, RegOpc(dst) ); | |
| 11222 ins_pipe( fpu_reg_mem ); | |
| 11223 %} | |
| 11224 | |
| 11225 // // Following two instructions for _222_mpegaudio | |
| 11226 // Spill to obtain 24-bit precision | |
| 11227 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ | |
| 11228 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11229 match(Set dst (AddF src1 src2)); | |
| 11230 | |
| 11231 format %{ "FADD $dst,$src1,$src2" %} | |
| 11232 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11233 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
| 11234 OpcReg_F(src2), | |
| 11235 Pop_Mem_F(dst) ); | |
| 11236 ins_pipe( fpu_mem_reg_mem ); | |
| 11237 %} | |
| 11238 | |
| 11239 // Cisc-spill variant | |
| 11240 // Spill to obtain 24-bit precision | |
| 11241 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ | |
| 11242 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11243 match(Set dst (AddF src1 (LoadF src2))); | |
| 11244 | |
| 11245 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 11246 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11247 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11248 set_instruction_start, | |
| 11249 OpcP, RMopc_Mem(secondary,src1), | |
| 11250 Pop_Mem_F(dst) ); | |
| 11251 ins_pipe( fpu_mem_mem_mem ); | |
| 11252 %} | |
| 11253 | |
| 11254 // Spill to obtain 24-bit precision | |
| 11255 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11256 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11257 match(Set dst (AddF src1 src2)); | |
| 11258 | |
| 11259 format %{ "FADD $dst,$src1,$src2" %} | |
| 11260 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 11261 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11262 set_instruction_start, | |
| 11263 OpcP, RMopc_Mem(secondary,src1), | |
| 11264 Pop_Mem_F(dst) ); | |
| 11265 ins_pipe( fpu_mem_mem_mem ); | |
| 11266 %} | |
| 11267 | |
| 11268 | |
| 11269 // Spill to obtain 24-bit precision | |
| 11270 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ | |
| 11271 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11272 match(Set dst (AddF src1 src2)); | |
| 11273 format %{ "FLD $src1\n\t" | |
| 11274 "FADD $src2\n\t" | |
| 11275 "FSTP_S $dst" %} | |
| 11276 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 11277 ins_encode( Push_Reg_F(src1), | |
| 11278 Opc_MemImm_F(src2), | |
| 11279 Pop_Mem_F(dst)); | |
| 11280 ins_pipe( fpu_mem_reg_con ); | |
| 11281 %} | |
| 11282 // | |
| 11283 // This instruction does not round to 24-bits | |
| 11284 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{ | |
| 11285 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11286 match(Set dst (AddF src1 src2)); | |
| 11287 format %{ "FLD $src1\n\t" | |
| 11288 "FADD $src2\n\t" | |
| 11289 "FSTP_S $dst" %} | |
| 11290 opcode(0xD8, 0x00); /* D8 /0 */ | |
| 11291 ins_encode( Push_Reg_F(src1), | |
| 11292 Opc_MemImm_F(src2), | |
| 11293 Pop_Reg_F(dst)); | |
| 11294 ins_pipe( fpu_reg_reg_con ); | |
| 11295 %} | |
| 11296 | |
| 11297 // Spill to obtain 24-bit precision | |
| 11298 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11299 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11300 match(Set dst (MulF src1 src2)); | |
| 11301 | |
| 11302 format %{ "FLD $src1\n\t" | |
| 11303 "FMUL $src2\n\t" | |
| 11304 "FSTP_S $dst" %} | |
| 11305 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
| 11306 ins_encode( Push_Reg_F(src1), | |
| 11307 OpcReg_F(src2), | |
| 11308 Pop_Mem_F(dst) ); | |
| 11309 ins_pipe( fpu_mem_reg_reg ); | |
| 11310 %} | |
| 11311 // | |
| 11312 // This instruction does not round to 24-bits | |
| 11313 instruct mulF_reg(regF dst, regF src1, regF src2) %{ | |
| 11314 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11315 match(Set dst (MulF src1 src2)); | |
| 11316 | |
| 11317 format %{ "FLD $src1\n\t" | |
| 11318 "FMUL $src2\n\t" | |
| 11319 "FSTP_S $dst" %} | |
| 11320 opcode(0xD8, 0x1); /* D8 C8+i */ | |
| 11321 ins_encode( Push_Reg_F(src2), | |
| 11322 OpcReg_F(src1), | |
| 11323 Pop_Reg_F(dst) ); | |
| 11324 ins_pipe( fpu_reg_reg_reg ); | |
| 11325 %} | |
| 11326 | |
| 11327 | |
| 11328 // Spill to obtain 24-bit precision | |
| 11329 // Cisc-alternate to reg-reg multiply | |
| 11330 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11331 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11332 match(Set dst (MulF src1 (LoadF src2))); | |
| 11333 | |
| 11334 format %{ "FLD_S $src2\n\t" | |
| 11335 "FMUL $src1\n\t" | |
| 11336 "FSTP_S $dst" %} | |
| 11337 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 11338 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11339 OpcReg_F(src1), | |
| 11340 Pop_Mem_F(dst) ); | |
| 11341 ins_pipe( fpu_mem_reg_mem ); | |
| 11342 %} | |
| 11343 // | |
| 11344 // This instruction does not round to 24-bits | |
| 11345 // Cisc-alternate to reg-reg multiply | |
| 11346 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ | |
| 11347 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11348 match(Set dst (MulF src1 (LoadF src2))); | |
| 11349 | |
| 11350 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11351 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 11352 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11353 OpcReg_F(src1), | |
| 11354 Pop_Reg_F(dst) ); | |
| 11355 ins_pipe( fpu_reg_reg_mem ); | |
| 11356 %} | |
| 11357 | |
| 11358 // Spill to obtain 24-bit precision | |
| 11359 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11360 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11361 match(Set dst (MulF src1 src2)); | |
| 11362 | |
| 11363 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11364 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 11365 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11366 set_instruction_start, | |
| 11367 OpcP, RMopc_Mem(secondary,src1), | |
| 11368 Pop_Mem_F(dst) ); | |
| 11369 ins_pipe( fpu_mem_mem_mem ); | |
| 11370 %} | |
| 11371 | |
| 11372 // Spill to obtain 24-bit precision | |
| 11373 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ | |
| 11374 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11375 match(Set dst (MulF src1 src2)); | |
| 11376 | |
| 11377 format %{ "FMULc $dst,$src1,$src2" %} | |
| 11378 opcode(0xD8, 0x1); /* D8 /1*/ | |
| 11379 ins_encode( Push_Reg_F(src1), | |
| 11380 Opc_MemImm_F(src2), | |
| 11381 Pop_Mem_F(dst)); | |
| 11382 ins_pipe( fpu_mem_reg_con ); | |
| 11383 %} | |
| 11384 // | |
| 11385 // This instruction does not round to 24-bits | |
| 11386 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{ | |
| 11387 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11388 match(Set dst (MulF src1 src2)); | |
| 11389 | |
| 11390 format %{ "FMULc $dst. $src1, $src2" %} | |
| 11391 opcode(0xD8, 0x1); /* D8 /1*/ | |
| 11392 ins_encode( Push_Reg_F(src1), | |
| 11393 Opc_MemImm_F(src2), | |
| 11394 Pop_Reg_F(dst)); | |
| 11395 ins_pipe( fpu_reg_reg_con ); | |
| 11396 %} | |
| 11397 | |
| 11398 | |
| 11399 // | |
| 11400 // MACRO1 -- subsume unshared load into mulF | |
| 11401 // This instruction does not round to 24-bits | |
| 11402 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ | |
| 11403 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11404 match(Set dst (MulF (LoadF mem1) src)); | |
| 11405 | |
| 11406 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 11407 "FMUL ST,$src\n\t" | |
| 11408 "FSTP $dst" %} | |
| 11409 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 11410 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
| 11411 OpcReg_F(src), | |
| 11412 Pop_Reg_F(dst) ); | |
| 11413 ins_pipe( fpu_reg_reg_mem ); | |
| 11414 %} | |
| 11415 // | |
| 11416 // MACRO2 -- addF a mulF which subsumed an unshared load | |
| 11417 // This instruction does not round to 24-bits | |
| 11418 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ | |
| 11419 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11420 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 11421 ins_cost(95); | |
| 11422 | |
| 11423 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
| 11424 "FMUL ST,$src1 subsume mulF left load\n\t" | |
| 11425 "FADD ST,$src2\n\t" | |
| 11426 "FSTP $dst" %} | |
| 11427 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11428 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 11429 FMul_ST_reg(src1), | |
| 11430 FAdd_ST_reg(src2), | |
| 11431 Pop_Reg_F(dst) ); | |
| 11432 ins_pipe( fpu_reg_mem_reg_reg ); | |
| 11433 %} | |
| 11434 | |
| 11435 // MACRO3 -- addF a mulF | |
| 11436 // This instruction does not round to 24-bits. It is a '2-address' | |
| 11437 // instruction in that the result goes back to src2. This eliminates | |
| 11438 // a move from the macro; possibly the register allocator will have | |
| 11439 // to add it back (and maybe not). | |
| 11440 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ | |
| 11441 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11442 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 11443 | |
| 11444 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 11445 "FMUL ST,$src1\n\t" | |
| 11446 "FADDP $src2,ST" %} | |
| 11447 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11448 ins_encode( Push_Reg_F(src0), | |
| 11449 FMul_ST_reg(src1), | |
| 11450 FAddP_reg_ST(src2) ); | |
| 11451 ins_pipe( fpu_reg_reg_reg ); | |
| 11452 %} | |
| 11453 | |
| 11454 // MACRO4 -- divF subF | |
| 11455 // This instruction does not round to 24-bits | |
| 11456 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ | |
| 11457 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11458 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 11459 | |
| 11460 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 11461 "FSUB ST,$src1\n\t" | |
| 11462 "FDIV ST,$src3\n\t" | |
| 11463 "FSTP $dst" %} | |
| 11464 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11465 ins_encode( Push_Reg_F(src2), | |
| 11466 subF_divF_encode(src1,src3), | |
| 11467 Pop_Reg_F(dst) ); | |
| 11468 ins_pipe( fpu_reg_reg_reg_reg ); | |
| 11469 %} | |
| 11470 | |
| 11471 // Spill to obtain 24-bit precision | |
| 11472 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11473 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11474 match(Set dst (DivF src1 src2)); | |
| 11475 | |
| 11476 format %{ "FDIV $dst,$src1,$src2" %} | |
| 11477 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
| 11478 ins_encode( Push_Reg_F(src1), | |
| 11479 OpcReg_F(src2), | |
| 11480 Pop_Mem_F(dst) ); | |
| 11481 ins_pipe( fpu_mem_reg_reg ); | |
| 11482 %} | |
| 11483 // | |
| 11484 // This instruction does not round to 24-bits | |
| 11485 instruct divF_reg(regF dst, regF src) %{ | |
| 11486 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11487 match(Set dst (DivF dst src)); | |
| 11488 | |
| 11489 format %{ "FDIV $dst,$src" %} | |
| 11490 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11491 ins_encode( Push_Reg_F(src), | |
| 11492 OpcP, RegOpc(dst) ); | |
| 11493 ins_pipe( fpu_reg_reg ); | |
| 11494 %} | |
| 11495 | |
| 11496 | |
| 11497 // Spill to obtain 24-bit precision | |
| 11498 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11499 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11500 match(Set dst (ModF src1 src2)); | |
| 11501 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11502 | |
| 11503 format %{ "FMOD $dst,$src1,$src2" %} | |
| 11504 ins_encode( Push_Reg_Mod_D(src1, src2), | |
| 11505 emitModD(), | |
| 11506 Push_Result_Mod_D(src2), | |
| 11507 Pop_Mem_F(dst)); | |
| 11508 ins_pipe( pipe_slow ); | |
| 11509 %} | |
| 11510 // | |
| 11511 // This instruction does not round to 24-bits | |
| 11512 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ | |
| 11513 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11514 match(Set dst (ModF dst src)); | |
| 11515 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11516 | |
| 11517 format %{ "FMOD $dst,$src" %} | |
| 11518 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 11519 emitModD(), | |
| 11520 Push_Result_Mod_D(src), | |
| 11521 Pop_Reg_F(dst)); | |
| 11522 ins_pipe( pipe_slow ); | |
| 11523 %} | |
| 11524 | |
| 11525 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 11526 predicate(UseSSE>=1); | |
| 11527 match(Set dst (ModF src0 src1)); | |
| 11528 effect(KILL rax, KILL cr); | |
| 11529 format %{ "SUB ESP,4\t # FMOD\n" | |
| 11530 "\tMOVSS [ESP+0],$src1\n" | |
| 11531 "\tFLD_S [ESP+0]\n" | |
| 11532 "\tMOVSS [ESP+0],$src0\n" | |
| 11533 "\tFLD_S [ESP+0]\n" | |
| 11534 "loop:\tFPREM\n" | |
| 11535 "\tFWAIT\n" | |
| 11536 "\tFNSTSW AX\n" | |
| 11537 "\tSAHF\n" | |
| 11538 "\tJP loop\n" | |
| 11539 "\tFSTP_S [ESP+0]\n" | |
| 11540 "\tMOVSS $dst,[ESP+0]\n" | |
| 11541 "\tADD ESP,4\n" | |
| 11542 "\tFSTP ST0\t # Restore FPU Stack" | |
| 11543 %} | |
| 11544 ins_cost(250); | |
| 11545 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); | |
| 11546 ins_pipe( pipe_slow ); | |
| 11547 %} | |
| 11548 | |
| 11549 | |
| 11550 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 11551 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 11552 | |
| 11553 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ | |
| 11554 predicate(UseSSE==0); | |
| 11555 match(Set dst (RoundFloat src)); | |
| 11556 ins_cost(125); | |
| 11557 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11558 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 11559 ins_pipe( fpu_mem_reg ); | |
| 11560 %} | |
| 11561 | |
| 11562 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ | |
| 11563 predicate(UseSSE<=1); | |
| 11564 match(Set dst (RoundDouble src)); | |
| 11565 ins_cost(125); | |
| 11566 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11567 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 11568 ins_pipe( fpu_mem_reg ); | |
| 11569 %} | |
| 11570 | |
| 11571 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11572 instruct convD2F_reg(stackSlotF dst, regD src) %{ | |
| 11573 predicate(UseSSE==0); | |
| 11574 match(Set dst (ConvD2F src)); | |
| 11575 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11576 expand %{ | |
| 11577 roundFloat_mem_reg(dst,src); | |
| 11578 %} | |
| 11579 %} | |
| 11580 | |
| 11581 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11582 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ | |
| 11583 predicate(UseSSE==1); | |
| 11584 match(Set dst (ConvD2F src)); | |
| 11585 effect( KILL cr ); | |
| 11586 format %{ "SUB ESP,4\n\t" | |
| 11587 "FST_S [ESP],$src\t# F-round\n\t" | |
| 11588 "MOVSS $dst,[ESP]\n\t" | |
| 11589 "ADD ESP,4" %} | |
| 11590 ins_encode( D2X_encoding(dst, src) ); | |
| 11591 ins_pipe( pipe_slow ); | |
| 11592 %} | |
| 11593 | |
| 11594 // Force rounding double precision to single precision | |
| 11595 instruct convXD2X_reg(regX dst, regXD src) %{ | |
| 11596 predicate(UseSSE>=2); | |
| 11597 match(Set dst (ConvD2F src)); | |
| 11598 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 11599 opcode(0xF2, 0x0F, 0x5A); | |
| 11600 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11601 ins_pipe( pipe_slow ); | |
| 11602 %} | |
| 11603 | |
| 11604 instruct convF2D_reg_reg(regD dst, regF src) %{ | |
| 11605 predicate(UseSSE==0); | |
| 11606 match(Set dst (ConvF2D src)); | |
| 11607 format %{ "FST_S $dst,$src\t# D-round" %} | |
| 11608 ins_encode( Pop_Reg_Reg_D(dst, src)); | |
| 11609 ins_pipe( fpu_reg_reg ); | |
| 11610 %} | |
| 11611 | |
| 11612 instruct convF2D_reg(stackSlotD dst, regF src) %{ | |
| 11613 predicate(UseSSE==1); | |
| 11614 match(Set dst (ConvF2D src)); | |
| 11615 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11616 expand %{ | |
| 11617 roundDouble_mem_reg(dst,src); | |
| 11618 %} | |
| 11619 %} | |
| 11620 | |
| 11621 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ | |
| 11622 predicate(UseSSE==1); | |
| 11623 match(Set dst (ConvF2D src)); | |
| 11624 effect( KILL cr ); | |
| 11625 format %{ "SUB ESP,4\n\t" | |
| 11626 "MOVSS [ESP] $src\n\t" | |
| 11627 "FLD_S [ESP]\n\t" | |
| 11628 "ADD ESP,4\n\t" | |
| 11629 "FSTP $dst\t# D-round" %} | |
| 11630 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); | |
| 11631 ins_pipe( pipe_slow ); | |
| 11632 %} | |
| 11633 | |
| 11634 instruct convX2XD_reg(regXD dst, regX src) %{ | |
| 11635 predicate(UseSSE>=2); | |
| 11636 match(Set dst (ConvF2D src)); | |
| 11637 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 11638 opcode(0xF3, 0x0F, 0x5A); | |
| 11639 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11640 ins_pipe( pipe_slow ); | |
| 11641 %} | |
| 11642 | |
| 11643 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11644 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ | |
| 11645 predicate(UseSSE<=1); | |
| 11646 match(Set dst (ConvD2I src)); | |
| 11647 effect( KILL tmp, KILL cr ); | |
| 11648 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 11649 "FLDCW trunc mode\n\t" | |
| 11650 "SUB ESP,4\n\t" | |
| 11651 "FISTp [ESP + #0]\n\t" | |
| 11652 "FLDCW std/24-bit mode\n\t" | |
| 11653 "POP EAX\n\t" | |
| 11654 "CMP EAX,0x80000000\n\t" | |
| 11655 "JNE,s fast\n\t" | |
| 11656 "FLD_D $src\n\t" | |
| 11657 "CALL d2i_wrapper\n" | |
| 11658 "fast:" %} | |
| 11659 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); | |
| 11660 ins_pipe( pipe_slow ); | |
| 11661 %} | |
| 11662 | |
| 11663 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11664 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ | |
| 11665 predicate(UseSSE>=2); | |
| 11666 match(Set dst (ConvD2I src)); | |
| 11667 effect( KILL tmp, KILL cr ); | |
| 11668 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 11669 "CMP $dst,0x80000000\n\t" | |
| 11670 "JNE,s fast\n\t" | |
| 11671 "SUB ESP, 8\n\t" | |
| 11672 "MOVSD [ESP], $src\n\t" | |
| 11673 "FLD_D [ESP]\n\t" | |
| 11674 "ADD ESP, 8\n\t" | |
| 11675 "CALL d2i_wrapper\n" | |
| 11676 "fast:" %} | |
| 11677 opcode(0x1); // double-precision conversion | |
| 11678 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11679 ins_pipe( pipe_slow ); | |
| 11680 %} | |
| 11681 | |
| 11682 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ | |
| 11683 predicate(UseSSE<=1); | |
| 11684 match(Set dst (ConvD2L src)); | |
| 11685 effect( KILL cr ); | |
| 11686 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 11687 "FLDCW trunc mode\n\t" | |
| 11688 "SUB ESP,8\n\t" | |
| 11689 "FISTp [ESP + #0]\n\t" | |
| 11690 "FLDCW std/24-bit mode\n\t" | |
| 11691 "POP EAX\n\t" | |
| 11692 "POP EDX\n\t" | |
| 11693 "CMP EDX,0x80000000\n\t" | |
| 11694 "JNE,s fast\n\t" | |
| 11695 "TEST EAX,EAX\n\t" | |
| 11696 "JNE,s fast\n\t" | |
| 11697 "FLD $src\n\t" | |
| 11698 "CALL d2l_wrapper\n" | |
| 11699 "fast:" %} | |
| 11700 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); | |
| 11701 ins_pipe( pipe_slow ); | |
| 11702 %} | |
| 11703 | |
| 11704 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11705 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ | |
| 11706 predicate (UseSSE>=2); | |
| 11707 match(Set dst (ConvD2L src)); | |
| 11708 effect( KILL cr ); | |
| 11709 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11710 "MOVSD [ESP],$src\n\t" | |
| 11711 "FLD_D [ESP]\n\t" | |
| 11712 "FLDCW trunc mode\n\t" | |
| 11713 "FISTp [ESP + #0]\n\t" | |
| 11714 "FLDCW std/24-bit mode\n\t" | |
| 11715 "POP EAX\n\t" | |
| 11716 "POP EDX\n\t" | |
| 11717 "CMP EDX,0x80000000\n\t" | |
| 11718 "JNE,s fast\n\t" | |
| 11719 "TEST EAX,EAX\n\t" | |
| 11720 "JNE,s fast\n\t" | |
| 11721 "SUB ESP,8\n\t" | |
| 11722 "MOVSD [ESP],$src\n\t" | |
| 11723 "FLD_D [ESP]\n\t" | |
| 11724 "CALL d2l_wrapper\n" | |
| 11725 "fast:" %} | |
| 11726 ins_encode( XD2L_encoding(src) ); | |
| 11727 ins_pipe( pipe_slow ); | |
| 11728 %} | |
| 11729 | |
| 11730 // Convert a double to an int. Java semantics require we do complex | |
| 11731 // manglations in the corner cases. So we set the rounding mode to | |
| 11732 // 'zero', store the darned double down as an int, and reset the | |
| 11733 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11734 // if we would overflow or converted a NAN; we check for this and | |
| 11735 // and go the slow path if needed. | |
| 11736 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ | |
| 11737 predicate(UseSSE==0); | |
| 11738 match(Set dst (ConvF2I src)); | |
| 11739 effect( KILL tmp, KILL cr ); | |
| 11740 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11741 "FLDCW trunc mode\n\t" | |
| 11742 "SUB ESP,4\n\t" | |
| 11743 "FISTp [ESP + #0]\n\t" | |
| 11744 "FLDCW std/24-bit mode\n\t" | |
| 11745 "POP EAX\n\t" | |
| 11746 "CMP EAX,0x80000000\n\t" | |
| 11747 "JNE,s fast\n\t" | |
| 11748 "FLD $src\n\t" | |
| 11749 "CALL d2i_wrapper\n" | |
| 11750 "fast:" %} | |
| 11751 // D2I_encoding works for F2I | |
| 11752 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); | |
| 11753 ins_pipe( pipe_slow ); | |
| 11754 %} | |
| 11755 | |
| 11756 // Convert a float in xmm to an int reg. | |
| 11757 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ | |
| 11758 predicate(UseSSE>=1); | |
| 11759 match(Set dst (ConvF2I src)); | |
| 11760 effect( KILL tmp, KILL cr ); | |
| 11761 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11762 "CMP $dst,0x80000000\n\t" | |
| 11763 "JNE,s fast\n\t" | |
| 11764 "SUB ESP, 4\n\t" | |
| 11765 "MOVSS [ESP], $src\n\t" | |
| 11766 "FLD [ESP]\n\t" | |
| 11767 "ADD ESP, 4\n\t" | |
| 11768 "CALL d2i_wrapper\n" | |
| 11769 "fast:" %} | |
| 11770 opcode(0x0); // single-precision conversion | |
| 11771 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11772 ins_pipe( pipe_slow ); | |
| 11773 %} | |
| 11774 | |
| 11775 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ | |
| 11776 predicate(UseSSE==0); | |
| 11777 match(Set dst (ConvF2L src)); | |
| 11778 effect( KILL cr ); | |
| 11779 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11780 "FLDCW trunc mode\n\t" | |
| 11781 "SUB ESP,8\n\t" | |
| 11782 "FISTp [ESP + #0]\n\t" | |
| 11783 "FLDCW std/24-bit mode\n\t" | |
| 11784 "POP EAX\n\t" | |
| 11785 "POP EDX\n\t" | |
| 11786 "CMP EDX,0x80000000\n\t" | |
| 11787 "JNE,s fast\n\t" | |
| 11788 "TEST EAX,EAX\n\t" | |
| 11789 "JNE,s fast\n\t" | |
| 11790 "FLD $src\n\t" | |
| 11791 "CALL d2l_wrapper\n" | |
| 11792 "fast:" %} | |
| 11793 // D2L_encoding works for F2L | |
| 11794 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); | |
| 11795 ins_pipe( pipe_slow ); | |
| 11796 %} | |
| 11797 | |
| 11798 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11799 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ | |
| 11800 predicate (UseSSE>=1); | |
| 11801 match(Set dst (ConvF2L src)); | |
| 11802 effect( KILL cr ); | |
| 11803 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11804 "MOVSS [ESP],$src\n\t" | |
| 11805 "FLD_S [ESP]\n\t" | |
| 11806 "FLDCW trunc mode\n\t" | |
| 11807 "FISTp [ESP + #0]\n\t" | |
| 11808 "FLDCW std/24-bit mode\n\t" | |
| 11809 "POP EAX\n\t" | |
| 11810 "POP EDX\n\t" | |
| 11811 "CMP EDX,0x80000000\n\t" | |
| 11812 "JNE,s fast\n\t" | |
| 11813 "TEST EAX,EAX\n\t" | |
| 11814 "JNE,s fast\n\t" | |
| 11815 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11816 "MOVSS [ESP],$src\n\t" | |
| 11817 "FLD_S [ESP]\n\t" | |
| 11818 "ADD ESP,4\n\t" | |
| 11819 "CALL d2l_wrapper\n" | |
| 11820 "fast:" %} | |
| 11821 ins_encode( X2L_encoding(src) ); | |
| 11822 ins_pipe( pipe_slow ); | |
| 11823 %} | |
| 11824 | |
| 11825 instruct convI2D_reg(regD dst, stackSlotI src) %{ | |
| 11826 predicate( UseSSE<=1 ); | |
| 11827 match(Set dst (ConvI2D src)); | |
| 11828 format %{ "FILD $src\n\t" | |
| 11829 "FSTP $dst" %} | |
| 11830 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11831 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); | |
| 11832 ins_pipe( fpu_reg_mem ); | |
| 11833 %} | |
| 11834 | |
| 11835 instruct convI2XD_reg(regXD dst, eRegI src) %{ | |
| 71 | 11836 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11837 match(Set dst (ConvI2D src)); |
| 11838 format %{ "CVTSI2SD $dst,$src" %} | |
| 11839 opcode(0xF2, 0x0F, 0x2A); | |
| 11840 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11841 ins_pipe( pipe_slow ); | |
| 11842 %} | |
| 11843 | |
| 11844 instruct convI2XD_mem(regXD dst, memory mem) %{ | |
| 11845 predicate( UseSSE>=2 ); | |
| 11846 match(Set dst (ConvI2D (LoadI mem))); | |
| 11847 format %{ "CVTSI2SD $dst,$mem" %} | |
| 11848 opcode(0xF2, 0x0F, 0x2A); | |
| 11849 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); | |
| 11850 ins_pipe( pipe_slow ); | |
| 11851 %} | |
| 11852 | |
| 71 | 11853 instruct convXI2XD_reg(regXD dst, eRegI src) |
| 11854 %{ | |
| 11855 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11856 match(Set dst (ConvI2D src)); | |
| 11857 | |
| 11858 format %{ "MOVD $dst,$src\n\t" | |
| 11859 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11860 ins_encode %{ | |
| 304 | 11861 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11862 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11863 %} | |
| 11864 ins_pipe(pipe_slow); // XXX | |
| 11865 %} | |
| 11866 | |
| 0 | 11867 instruct convI2D_mem(regD dst, memory mem) %{ |
| 11868 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); | |
| 11869 match(Set dst (ConvI2D (LoadI mem))); | |
| 11870 format %{ "FILD $mem\n\t" | |
| 11871 "FSTP $dst" %} | |
| 11872 opcode(0xDB); /* DB /0 */ | |
| 11873 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11874 Pop_Reg_D(dst)); | |
| 11875 ins_pipe( fpu_reg_mem ); | |
| 11876 %} | |
| 11877 | |
| 11878 // Convert a byte to a float; no rounding step needed. | |
| 11879 instruct conv24I2F_reg(regF dst, stackSlotI src) %{ | |
| 11880 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); | |
| 11881 match(Set dst (ConvI2F src)); | |
| 11882 format %{ "FILD $src\n\t" | |
| 11883 "FSTP $dst" %} | |
| 11884 | |
| 11885 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11886 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); | |
| 11887 ins_pipe( fpu_reg_mem ); | |
| 11888 %} | |
| 11889 | |
| 11890 // In 24-bit mode, force exponent rounding by storing back out | |
| 11891 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ | |
| 11892 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11893 match(Set dst (ConvI2F src)); | |
| 11894 ins_cost(200); | |
| 11895 format %{ "FILD $src\n\t" | |
| 11896 "FSTP_S $dst" %} | |
| 11897 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11898 ins_encode( Push_Mem_I(src), | |
| 11899 Pop_Mem_F(dst)); | |
| 11900 ins_pipe( fpu_mem_mem ); | |
| 11901 %} | |
| 11902 | |
| 11903 // In 24-bit mode, force exponent rounding by storing back out | |
| 11904 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ | |
| 11905 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11906 match(Set dst (ConvI2F (LoadI mem))); | |
| 11907 ins_cost(200); | |
| 11908 format %{ "FILD $mem\n\t" | |
| 11909 "FSTP_S $dst" %} | |
| 11910 opcode(0xDB); /* DB /0 */ | |
| 11911 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11912 Pop_Mem_F(dst)); | |
| 11913 ins_pipe( fpu_mem_mem ); | |
| 11914 %} | |
| 11915 | |
| 11916 // This instruction does not round to 24-bits | |
| 11917 instruct convI2F_reg(regF dst, stackSlotI src) %{ | |
| 11918 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11919 match(Set dst (ConvI2F src)); | |
| 11920 format %{ "FILD $src\n\t" | |
| 11921 "FSTP $dst" %} | |
| 11922 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11923 ins_encode( Push_Mem_I(src), | |
| 11924 Pop_Reg_F(dst)); | |
| 11925 ins_pipe( fpu_reg_mem ); | |
| 11926 %} | |
| 11927 | |
| 11928 // This instruction does not round to 24-bits | |
| 11929 instruct convI2F_mem(regF dst, memory mem) %{ | |
| 11930 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11931 match(Set dst (ConvI2F (LoadI mem))); | |
| 11932 format %{ "FILD $mem\n\t" | |
| 11933 "FSTP $dst" %} | |
| 11934 opcode(0xDB); /* DB /0 */ | |
| 11935 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 11936 Pop_Reg_F(dst)); | |
| 11937 ins_pipe( fpu_reg_mem ); | |
| 11938 %} | |
| 11939 | |
| 11940 // Convert an int to a float in xmm; no rounding step needed. | |
| 11941 instruct convI2X_reg(regX dst, eRegI src) %{ | |
| 71 | 11942 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11943 match(Set dst (ConvI2F src)); |
| 11944 format %{ "CVTSI2SS $dst, $src" %} | |
| 11945 | |
| 11946 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ | |
| 11947 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11948 ins_pipe( pipe_slow ); | |
| 11949 %} | |
| 11950 | |
| 71 | 11951 instruct convXI2X_reg(regX dst, eRegI src) |
| 11952 %{ | |
| 11953 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11954 match(Set dst (ConvI2F src)); | |
| 11955 | |
| 11956 format %{ "MOVD $dst,$src\n\t" | |
| 11957 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11958 ins_encode %{ | |
| 304 | 11959 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11960 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11961 %} | |
| 11962 ins_pipe(pipe_slow); // XXX | |
| 11963 %} | |
| 11964 | |
| 0 | 11965 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ |
| 11966 match(Set dst (ConvI2L src)); | |
| 11967 effect(KILL cr); | |
| 624 | 11968 ins_cost(375); |
| 0 | 11969 format %{ "MOV $dst.lo,$src\n\t" |
| 11970 "MOV $dst.hi,$src\n\t" | |
| 11971 "SAR $dst.hi,31" %} | |
| 11972 ins_encode(convert_int_long(dst,src)); | |
| 11973 ins_pipe( ialu_reg_reg_long ); | |
| 11974 %} | |
| 11975 | |
| 11976 // Zero-extend convert int to long | |
| 11977 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11978 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 11979 effect( KILL flags ); | |
| 624 | 11980 ins_cost(250); |
| 0 | 11981 format %{ "MOV $dst.lo,$src\n\t" |
| 11982 "XOR $dst.hi,$dst.hi" %} | |
| 11983 opcode(0x33); // XOR | |
| 11984 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11985 ins_pipe( ialu_reg_reg_long ); | |
| 11986 %} | |
| 11987 | |
| 11988 // Zero-extend long | |
| 11989 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11990 match(Set dst (AndL src mask) ); | |
| 11991 effect( KILL flags ); | |
| 624 | 11992 ins_cost(250); |
| 0 | 11993 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11994 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11995 opcode(0x33); // XOR | |
| 11996 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11997 ins_pipe( ialu_reg_reg_long ); | |
| 11998 %} | |
| 11999 | |
| 12000 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ | |
| 12001 predicate (UseSSE<=1); | |
| 12002 match(Set dst (ConvL2D src)); | |
| 12003 effect( KILL cr ); | |
| 12004 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12005 "PUSH $src.lo\n\t" | |
| 12006 "FILD ST,[ESP + #0]\n\t" | |
| 12007 "ADD ESP,8\n\t" | |
| 12008 "FSTP_D $dst\t# D-round" %} | |
| 12009 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12010 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); | |
| 12011 ins_pipe( pipe_slow ); | |
| 12012 %} | |
| 12013 | |
| 12014 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ | |
| 12015 predicate (UseSSE>=2); | |
| 12016 match(Set dst (ConvL2D src)); | |
| 12017 effect( KILL cr ); | |
| 12018 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12019 "PUSH $src.lo\n\t" | |
| 12020 "FILD_D [ESP]\n\t" | |
| 12021 "FSTP_D [ESP]\n\t" | |
| 12022 "MOVSD $dst,[ESP]\n\t" | |
| 12023 "ADD ESP,8" %} | |
| 12024 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12025 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); | |
| 12026 ins_pipe( pipe_slow ); | |
| 12027 %} | |
| 12028 | |
| 12029 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ | |
| 12030 predicate (UseSSE>=1); | |
| 12031 match(Set dst (ConvL2F src)); | |
| 12032 effect( KILL cr ); | |
| 12033 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12034 "PUSH $src.lo\n\t" | |
| 12035 "FILD_D [ESP]\n\t" | |
| 12036 "FSTP_S [ESP]\n\t" | |
| 12037 "MOVSS $dst,[ESP]\n\t" | |
| 12038 "ADD ESP,8" %} | |
| 12039 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12040 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); | |
| 12041 ins_pipe( pipe_slow ); | |
| 12042 %} | |
| 12043 | |
| 12044 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ | |
| 12045 match(Set dst (ConvL2F src)); | |
| 12046 effect( KILL cr ); | |
| 12047 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12048 "PUSH $src.lo\n\t" | |
| 12049 "FILD ST,[ESP + #0]\n\t" | |
| 12050 "ADD ESP,8\n\t" | |
| 12051 "FSTP_S $dst\t# F-round" %} | |
| 12052 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12053 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); | |
| 12054 ins_pipe( pipe_slow ); | |
| 12055 %} | |
| 12056 | |
| 12057 instruct convL2I_reg( eRegI dst, eRegL src ) %{ | |
| 12058 match(Set dst (ConvL2I src)); | |
| 12059 effect( DEF dst, USE src ); | |
| 12060 format %{ "MOV $dst,$src.lo" %} | |
| 12061 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 12062 ins_pipe( ialu_reg_reg ); | |
| 12063 %} | |
| 12064 | |
| 12065 | |
| 12066 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ | |
| 12067 match(Set dst (MoveF2I src)); | |
| 12068 effect( DEF dst, USE src ); | |
| 12069 ins_cost(100); | |
| 12070 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 12071 opcode(0x8B); | |
| 12072 ins_encode( OpcP, RegMem(dst,src)); | |
| 12073 ins_pipe( ialu_reg_mem ); | |
| 12074 %} | |
| 12075 | |
| 12076 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 12077 predicate(UseSSE==0); | |
| 12078 match(Set dst (MoveF2I src)); | |
| 12079 effect( DEF dst, USE src ); | |
| 12080 | |
| 12081 ins_cost(125); | |
| 12082 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
| 12083 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 12084 ins_pipe( fpu_mem_reg ); | |
| 12085 %} | |
| 12086 | |
| 12087 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ | |
| 12088 predicate(UseSSE>=1); | |
| 12089 match(Set dst (MoveF2I src)); | |
| 12090 effect( DEF dst, USE src ); | |
| 12091 | |
| 12092 ins_cost(95); | |
| 12093 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 12094 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); | |
| 12095 ins_pipe( pipe_slow ); | |
| 12096 %} | |
| 12097 | |
| 12098 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ | |
| 12099 predicate(UseSSE>=2); | |
| 12100 match(Set dst (MoveF2I src)); | |
| 12101 effect( DEF dst, USE src ); | |
| 12102 ins_cost(85); | |
| 12103 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 12104 ins_encode( MovX2I_reg(dst, src)); | |
| 12105 ins_pipe( pipe_slow ); | |
| 12106 %} | |
| 12107 | |
| 12108 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ | |
| 12109 match(Set dst (MoveI2F src)); | |
| 12110 effect( DEF dst, USE src ); | |
| 12111 | |
| 12112 ins_cost(100); | |
| 12113 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 12114 opcode(0x89); | |
| 12115 ins_encode( OpcPRegSS( dst, src ) ); | |
| 12116 ins_pipe( ialu_mem_reg ); | |
| 12117 %} | |
| 12118 | |
| 12119 | |
| 12120 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 12121 predicate(UseSSE==0); | |
| 12122 match(Set dst (MoveI2F src)); | |
| 12123 effect(DEF dst, USE src); | |
| 12124 | |
| 12125 ins_cost(125); | |
| 12126 format %{ "FLD_S $src\n\t" | |
| 12127 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 12128 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 12129 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12130 Pop_Reg_F(dst) ); | |
| 12131 ins_pipe( fpu_reg_mem ); | |
| 12132 %} | |
| 12133 | |
| 12134 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ | |
| 12135 predicate(UseSSE>=1); | |
| 12136 match(Set dst (MoveI2F src)); | |
| 12137 effect( DEF dst, USE src ); | |
| 12138 | |
| 12139 ins_cost(95); | |
| 12140 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 12141 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12142 ins_pipe( pipe_slow ); | |
| 12143 %} | |
| 12144 | |
| 12145 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ | |
| 12146 predicate(UseSSE>=2); | |
| 12147 match(Set dst (MoveI2F src)); | |
| 12148 effect( DEF dst, USE src ); | |
| 12149 | |
| 12150 ins_cost(85); | |
| 12151 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 12152 ins_encode( MovI2X_reg(dst, src) ); | |
| 12153 ins_pipe( pipe_slow ); | |
| 12154 %} | |
| 12155 | |
| 12156 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 12157 match(Set dst (MoveD2L src)); | |
| 12158 effect(DEF dst, USE src); | |
| 12159 | |
| 12160 ins_cost(250); | |
| 12161 format %{ "MOV $dst.lo,$src\n\t" | |
| 12162 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 12163 opcode(0x8B, 0x8B); | |
| 12164 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 12165 ins_pipe( ialu_mem_long_reg ); | |
| 12166 %} | |
| 12167 | |
| 12168 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 12169 predicate(UseSSE<=1); | |
| 12170 match(Set dst (MoveD2L src)); | |
| 12171 effect(DEF dst, USE src); | |
| 12172 | |
| 12173 ins_cost(125); | |
| 12174 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
| 12175 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 12176 ins_pipe( fpu_mem_reg ); | |
| 12177 %} | |
| 12178 | |
| 12179 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ | |
| 12180 predicate(UseSSE>=2); | |
| 12181 match(Set dst (MoveD2L src)); | |
| 12182 effect(DEF dst, USE src); | |
| 12183 ins_cost(95); | |
| 12184 | |
| 12185 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 12186 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); | |
| 12187 ins_pipe( pipe_slow ); | |
| 12188 %} | |
| 12189 | |
| 12190 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ | |
| 12191 predicate(UseSSE>=2); | |
| 12192 match(Set dst (MoveD2L src)); | |
| 12193 effect(DEF dst, USE src, TEMP tmp); | |
| 12194 ins_cost(85); | |
| 12195 format %{ "MOVD $dst.lo,$src\n\t" | |
| 12196 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 12197 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 12198 ins_encode( MovXD2L_reg(dst, src, tmp) ); | |
| 12199 ins_pipe( pipe_slow ); | |
| 12200 %} | |
| 12201 | |
| 12202 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 12203 match(Set dst (MoveL2D src)); | |
| 12204 effect(DEF dst, USE src); | |
| 12205 | |
| 12206 ins_cost(200); | |
| 12207 format %{ "MOV $dst,$src.lo\n\t" | |
| 12208 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 12209 opcode(0x89, 0x89); | |
| 12210 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 12211 ins_pipe( ialu_mem_long_reg ); | |
| 12212 %} | |
| 12213 | |
| 12214 | |
| 12215 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 12216 predicate(UseSSE<=1); | |
| 12217 match(Set dst (MoveL2D src)); | |
| 12218 effect(DEF dst, USE src); | |
| 12219 ins_cost(125); | |
| 12220 | |
| 12221 format %{ "FLD_D $src\n\t" | |
| 12222 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 12223 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 12224 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12225 Pop_Reg_D(dst) ); | |
| 12226 ins_pipe( fpu_reg_mem ); | |
| 12227 %} | |
| 12228 | |
| 12229 | |
| 12230 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ | |
| 12231 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 12232 match(Set dst (MoveL2D src)); | |
| 12233 effect(DEF dst, USE src); | |
| 12234 | |
| 12235 ins_cost(95); | |
| 12236 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12237 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12238 ins_pipe( pipe_slow ); | |
| 12239 %} | |
| 12240 | |
| 12241 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ | |
| 12242 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 12243 match(Set dst (MoveL2D src)); | |
| 12244 effect(DEF dst, USE src); | |
| 12245 | |
| 12246 ins_cost(95); | |
| 12247 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12248 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); | |
| 12249 ins_pipe( pipe_slow ); | |
| 12250 %} | |
| 12251 | |
| 12252 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ | |
| 12253 predicate(UseSSE>=2); | |
| 12254 match(Set dst (MoveL2D src)); | |
| 12255 effect(TEMP dst, USE src, TEMP tmp); | |
| 12256 ins_cost(85); | |
| 12257 format %{ "MOVD $dst,$src.lo\n\t" | |
| 12258 "MOVD $tmp,$src.hi\n\t" | |
| 12259 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 12260 ins_encode( MovL2XD_reg(dst, src, tmp) ); | |
| 12261 ins_pipe( pipe_slow ); | |
| 12262 %} | |
| 12263 | |
| 12264 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12265 instruct Repl8B_reg(regXD dst, regXD src) %{ | |
| 12266 predicate(UseSSE>=2); | |
| 12267 match(Set dst (Replicate8B src)); | |
| 12268 format %{ "MOVDQA $dst,$src\n\t" | |
| 12269 "PUNPCKLBW $dst,$dst\n\t" | |
| 12270 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12271 ins_encode( pshufd_8x8(dst, src)); | |
| 12272 ins_pipe( pipe_slow ); | |
| 12273 %} | |
| 12274 | |
| 12275 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12276 instruct Repl8B_eRegI(regXD dst, eRegI src) %{ | |
| 12277 predicate(UseSSE>=2); | |
| 12278 match(Set dst (Replicate8B src)); | |
| 12279 format %{ "MOVD $dst,$src\n\t" | |
| 12280 "PUNPCKLBW $dst,$dst\n\t" | |
| 12281 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12282 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 12283 ins_pipe( pipe_slow ); | |
| 12284 %} | |
| 12285 | |
| 12286 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 12287 instruct Repl8B_immI0(regXD dst, immI0 zero) %{ | |
| 12288 predicate(UseSSE>=2); | |
| 12289 match(Set dst (Replicate8B zero)); | |
| 12290 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 12291 ins_encode( pxor(dst, dst)); | |
| 12292 ins_pipe( fpu_reg_reg ); | |
| 12293 %} | |
| 12294 | |
| 12295 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12296 instruct Repl4S_reg(regXD dst, regXD src) %{ | |
| 12297 predicate(UseSSE>=2); | |
| 12298 match(Set dst (Replicate4S src)); | |
| 12299 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 12300 ins_encode( pshufd_4x16(dst, src)); | |
| 12301 ins_pipe( fpu_reg_reg ); | |
| 12302 %} | |
| 12303 | |
| 12304 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12305 instruct Repl4S_eRegI(regXD dst, eRegI src) %{ | |
| 12306 predicate(UseSSE>=2); | |
| 12307 match(Set dst (Replicate4S src)); | |
| 12308 format %{ "MOVD $dst,$src\n\t" | |
| 12309 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 12310 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12311 ins_pipe( fpu_reg_reg ); | |
| 12312 %} | |
| 12313 | |
| 12314 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 12315 instruct Repl4S_immI0(regXD dst, immI0 zero) %{ | |
| 12316 predicate(UseSSE>=2); | |
| 12317 match(Set dst (Replicate4S zero)); | |
| 12318 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 12319 ins_encode( pxor(dst, dst)); | |
| 12320 ins_pipe( fpu_reg_reg ); | |
| 12321 %} | |
| 12322 | |
| 12323 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12324 instruct Repl4C_reg(regXD dst, regXD src) %{ | |
| 12325 predicate(UseSSE>=2); | |
| 12326 match(Set dst (Replicate4C src)); | |
| 12327 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 12328 ins_encode( pshufd_4x16(dst, src)); | |
| 12329 ins_pipe( fpu_reg_reg ); | |
| 12330 %} | |
| 12331 | |
| 12332 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12333 instruct Repl4C_eRegI(regXD dst, eRegI src) %{ | |
| 12334 predicate(UseSSE>=2); | |
| 12335 match(Set dst (Replicate4C src)); | |
| 12336 format %{ "MOVD $dst,$src\n\t" | |
| 12337 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 12338 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12339 ins_pipe( fpu_reg_reg ); | |
| 12340 %} | |
| 12341 | |
| 12342 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 12343 instruct Repl4C_immI0(regXD dst, immI0 zero) %{ | |
| 12344 predicate(UseSSE>=2); | |
| 12345 match(Set dst (Replicate4C zero)); | |
| 12346 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 12347 ins_encode( pxor(dst, dst)); | |
| 12348 ins_pipe( fpu_reg_reg ); | |
| 12349 %} | |
| 12350 | |
| 12351 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12352 instruct Repl2I_reg(regXD dst, regXD src) %{ | |
| 12353 predicate(UseSSE>=2); | |
| 12354 match(Set dst (Replicate2I src)); | |
| 12355 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 12356 ins_encode( pshufd(dst, src, 0x00)); | |
| 12357 ins_pipe( fpu_reg_reg ); | |
| 12358 %} | |
| 12359 | |
| 12360 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12361 instruct Repl2I_eRegI(regXD dst, eRegI src) %{ | |
| 12362 predicate(UseSSE>=2); | |
| 12363 match(Set dst (Replicate2I src)); | |
| 12364 format %{ "MOVD $dst,$src\n\t" | |
| 12365 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 12366 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 12367 ins_pipe( fpu_reg_reg ); | |
| 12368 %} | |
| 12369 | |
| 12370 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 12371 instruct Repl2I_immI0(regXD dst, immI0 zero) %{ | |
| 12372 predicate(UseSSE>=2); | |
| 12373 match(Set dst (Replicate2I zero)); | |
| 12374 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 12375 ins_encode( pxor(dst, dst)); | |
| 12376 ins_pipe( fpu_reg_reg ); | |
| 12377 %} | |
| 12378 | |
| 12379 // Replicate scalar to packed single precision floating point values in xmm | |
| 12380 instruct Repl2F_reg(regXD dst, regXD src) %{ | |
| 12381 predicate(UseSSE>=2); | |
| 12382 match(Set dst (Replicate2F src)); | |
| 12383 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12384 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12385 ins_pipe( fpu_reg_reg ); | |
| 12386 %} | |
| 12387 | |
| 12388 // Replicate scalar to packed single precision floating point values in xmm | |
| 12389 instruct Repl2F_regX(regXD dst, regX src) %{ | |
| 12390 predicate(UseSSE>=2); | |
| 12391 match(Set dst (Replicate2F src)); | |
| 12392 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12393 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12394 ins_pipe( fpu_reg_reg ); | |
| 12395 %} | |
| 12396 | |
| 12397 // Replicate scalar to packed single precision floating point values in xmm | |
| 12398 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ | |
| 12399 predicate(UseSSE>=2); | |
| 12400 match(Set dst (Replicate2F zero)); | |
| 12401 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 12402 ins_encode( pxor(dst, dst)); | |
| 12403 ins_pipe( fpu_reg_reg ); | |
| 12404 %} | |
| 12405 | |
| 12406 // ======================================================================= | |
| 12407 // fast clearing of an array | |
| 12408 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 12409 match(Set dummy (ClearArray cnt base)); | |
| 12410 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 12411 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 12412 "XOR EAX,EAX\n\t" | |
| 12413 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 12414 opcode(0,0x4); | |
| 12415 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 12416 OpcRegReg(0x33,EAX,EAX), | |
| 12417 Opcode(0xF3), Opcode(0xAB) ); | |
| 12418 ins_pipe( pipe_slow ); | |
| 12419 %} | |
| 12420 | |
|
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12421 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2, |
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12422 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{ |
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12423 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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12424 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
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12425 |
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12426 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %} |
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12427 ins_encode %{ |
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12428 __ string_compare($str1$$Register, $str2$$Register, |
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12429 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
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12430 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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12431 %} |
| 681 | 12432 ins_pipe( pipe_slow ); |
| 12433 %} | |
| 12434 | |
| 12435 // fast string equals | |
|
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12436 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
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12437 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
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12438 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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12439 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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12440 |
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12441 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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12442 ins_encode %{ |
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12443 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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12444 $cnt$$Register, $result$$Register, $tmp3$$Register, |
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12445 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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12446 %} |
|
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12447 ins_pipe( pipe_slow ); |
|
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12448 %} |
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12449 |
|
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12450 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
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12451 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{ |
| 681 | 12452 predicate(UseSSE42Intrinsics); |
|
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12453 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
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12454 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr); |
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12455 |
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12456 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %} |
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12457 ins_encode %{ |
|
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12458 __ string_indexof($str1$$Register, $str2$$Register, |
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12459 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
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12460 $tmp1$$XMMRegister, $tmp2$$Register); |
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12461 %} |
| 0 | 12462 ins_pipe( pipe_slow ); |
| 12463 %} | |
| 12464 | |
|
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12465 // fast array equals |
|
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12466 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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12467 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
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12468 %{ |
|
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12469 match(Set result (AryEq ary1 ary2)); |
| 681 | 12470 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
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12471 //ins_cost(300); |
|
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12472 |
|
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12473 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
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12474 ins_encode %{ |
|
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12475 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
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12476 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
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12477 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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12478 %} |
|
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12479 ins_pipe( pipe_slow ); |
|
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12480 %} |
|
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12481 |
| 0 | 12482 //----------Control Flow Instructions------------------------------------------ |
| 12483 // Signed compare Instructions | |
| 12484 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ | |
| 12485 match(Set cr (CmpI op1 op2)); | |
| 12486 effect( DEF cr, USE op1, USE op2 ); | |
| 12487 format %{ "CMP $op1,$op2" %} | |
| 12488 opcode(0x3B); /* Opcode 3B /r */ | |
| 12489 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12490 ins_pipe( ialu_cr_reg_reg ); | |
| 12491 %} | |
| 12492 | |
| 12493 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ | |
| 12494 match(Set cr (CmpI op1 op2)); | |
| 12495 effect( DEF cr, USE op1 ); | |
| 12496 format %{ "CMP $op1,$op2" %} | |
| 12497 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12498 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 12499 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12500 ins_pipe( ialu_cr_reg_imm ); | |
| 12501 %} | |
| 12502 | |
| 12503 // Cisc-spilled version of cmpI_eReg | |
| 12504 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ | |
| 12505 match(Set cr (CmpI op1 (LoadI op2))); | |
| 12506 | |
| 12507 format %{ "CMP $op1,$op2" %} | |
| 12508 ins_cost(500); | |
| 12509 opcode(0x3B); /* Opcode 3B /r */ | |
| 12510 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12511 ins_pipe( ialu_cr_reg_mem ); | |
| 12512 %} | |
| 12513 | |
| 12514 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ | |
| 12515 match(Set cr (CmpI src zero)); | |
| 12516 effect( DEF cr, USE src ); | |
| 12517 | |
| 12518 format %{ "TEST $src,$src" %} | |
| 12519 opcode(0x85); | |
| 12520 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12521 ins_pipe( ialu_cr_reg_imm ); | |
| 12522 %} | |
| 12523 | |
| 12524 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ | |
| 12525 match(Set cr (CmpI (AndI src con) zero)); | |
| 12526 | |
| 12527 format %{ "TEST $src,$con" %} | |
| 12528 opcode(0xF7,0x00); | |
| 12529 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 12530 ins_pipe( ialu_cr_reg_imm ); | |
| 12531 %} | |
| 12532 | |
| 12533 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ | |
| 12534 match(Set cr (CmpI (AndI src mem) zero)); | |
| 12535 | |
| 12536 format %{ "TEST $src,$mem" %} | |
| 12537 opcode(0x85); | |
| 12538 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 12539 ins_pipe( ialu_cr_reg_mem ); | |
| 12540 %} | |
| 12541 | |
| 12542 // Unsigned compare Instructions; really, same as signed except they | |
| 12543 // produce an eFlagsRegU instead of eFlagsReg. | |
| 12544 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ | |
| 12545 match(Set cr (CmpU op1 op2)); | |
| 12546 | |
| 12547 format %{ "CMPu $op1,$op2" %} | |
| 12548 opcode(0x3B); /* Opcode 3B /r */ | |
| 12549 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12550 ins_pipe( ialu_cr_reg_reg ); | |
| 12551 %} | |
| 12552 | |
| 12553 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ | |
| 12554 match(Set cr (CmpU op1 op2)); | |
| 12555 | |
| 12556 format %{ "CMPu $op1,$op2" %} | |
| 12557 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12558 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12559 ins_pipe( ialu_cr_reg_imm ); | |
| 12560 %} | |
| 12561 | |
| 12562 // // Cisc-spilled version of cmpU_eReg | |
| 12563 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ | |
| 12564 match(Set cr (CmpU op1 (LoadI op2))); | |
| 12565 | |
| 12566 format %{ "CMPu $op1,$op2" %} | |
| 12567 ins_cost(500); | |
| 12568 opcode(0x3B); /* Opcode 3B /r */ | |
| 12569 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12570 ins_pipe( ialu_cr_reg_mem ); | |
| 12571 %} | |
| 12572 | |
| 12573 // // Cisc-spilled version of cmpU_eReg | |
| 12574 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ | |
| 12575 // match(Set cr (CmpU (LoadI op1) op2)); | |
| 12576 // | |
| 12577 // format %{ "CMPu $op1,$op2" %} | |
| 12578 // ins_cost(500); | |
| 12579 // opcode(0x39); /* Opcode 39 /r */ | |
| 12580 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12581 //%} | |
| 12582 | |
| 12583 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ | |
| 12584 match(Set cr (CmpU src zero)); | |
| 12585 | |
| 12586 format %{ "TESTu $src,$src" %} | |
| 12587 opcode(0x85); | |
| 12588 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12589 ins_pipe( ialu_cr_reg_imm ); | |
| 12590 %} | |
| 12591 | |
| 12592 // Unsigned pointer compare Instructions | |
| 12593 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 12594 match(Set cr (CmpP op1 op2)); | |
| 12595 | |
| 12596 format %{ "CMPu $op1,$op2" %} | |
| 12597 opcode(0x3B); /* Opcode 3B /r */ | |
| 12598 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12599 ins_pipe( ialu_cr_reg_reg ); | |
| 12600 %} | |
| 12601 | |
| 12602 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 12603 match(Set cr (CmpP op1 op2)); | |
| 12604 | |
| 12605 format %{ "CMPu $op1,$op2" %} | |
| 12606 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12607 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12608 ins_pipe( ialu_cr_reg_imm ); | |
| 12609 %} | |
| 12610 | |
| 12611 // // Cisc-spilled version of cmpP_eReg | |
| 12612 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 12613 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12614 | |
| 12615 format %{ "CMPu $op1,$op2" %} | |
| 12616 ins_cost(500); | |
| 12617 opcode(0x3B); /* Opcode 3B /r */ | |
| 12618 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12619 ins_pipe( ialu_cr_reg_mem ); | |
| 12620 %} | |
| 12621 | |
| 12622 // // Cisc-spilled version of cmpP_eReg | |
| 12623 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 12624 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 12625 // | |
| 12626 // format %{ "CMPu $op1,$op2" %} | |
| 12627 // ins_cost(500); | |
| 12628 // opcode(0x39); /* Opcode 39 /r */ | |
| 12629 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12630 //%} | |
| 12631 | |
| 12632 // Compare raw pointer (used in out-of-heap check). | |
| 12633 // Only works because non-oop pointers must be raw pointers | |
| 12634 // and raw pointers have no anti-dependencies. | |
| 12635 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
| 12636 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); | |
| 12637 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12638 | |
| 12639 format %{ "CMPu $op1,$op2" %} | |
| 12640 opcode(0x3B); /* Opcode 3B /r */ | |
| 12641 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12642 ins_pipe( ialu_cr_reg_mem ); | |
| 12643 %} | |
| 12644 | |
| 12645 // | |
| 12646 // This will generate a signed flags result. This should be ok | |
| 12647 // since any compare to a zero should be eq/neq. | |
| 12648 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 12649 match(Set cr (CmpP src zero)); | |
| 12650 | |
| 12651 format %{ "TEST $src,$src" %} | |
| 12652 opcode(0x85); | |
| 12653 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12654 ins_pipe( ialu_cr_reg_imm ); | |
| 12655 %} | |
| 12656 | |
| 12657 // Cisc-spilled version of testP_reg | |
| 12658 // This will generate a signed flags result. This should be ok | |
| 12659 // since any compare to a zero should be eq/neq. | |
| 12660 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12661 match(Set cr (CmpP (LoadP op) zero)); | |
| 12662 | |
| 12663 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12664 ins_cost(500); | |
| 12665 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12666 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12667 ins_pipe( ialu_cr_reg_imm ); | |
| 12668 %} | |
| 12669 | |
| 12670 // Yanked all unsigned pointer compare operations. | |
| 12671 // Pointer compares are done with CmpP which is already unsigned. | |
| 12672 | |
| 12673 //----------Max and Min-------------------------------------------------------- | |
| 12674 // Min Instructions | |
| 12675 //// | |
| 12676 // *** Min and Max using the conditional move are slower than the | |
| 12677 // *** branch version on a Pentium III. | |
| 12678 // // Conditional move for min | |
| 12679 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12680 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12681 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12682 // opcode(0x4C,0x0F); | |
| 12683 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12684 // ins_pipe( pipe_cmov_reg ); | |
| 12685 //%} | |
| 12686 // | |
| 12687 //// Min Register with Register (P6 version) | |
| 12688 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12689 // predicate(VM_Version::supports_cmov() ); | |
| 12690 // match(Set op2 (MinI op1 op2)); | |
| 12691 // ins_cost(200); | |
| 12692 // expand %{ | |
| 12693 // eFlagsReg cr; | |
| 12694 // compI_eReg(cr,op1,op2); | |
| 12695 // cmovI_reg_lt(op2,op1,cr); | |
| 12696 // %} | |
| 12697 //%} | |
| 12698 | |
| 12699 // Min Register with Register (generic version) | |
| 12700 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12701 match(Set dst (MinI dst src)); | |
| 12702 effect(KILL flags); | |
| 12703 ins_cost(300); | |
| 12704 | |
| 12705 format %{ "MIN $dst,$src" %} | |
| 12706 opcode(0xCC); | |
| 12707 ins_encode( min_enc(dst,src) ); | |
| 12708 ins_pipe( pipe_slow ); | |
| 12709 %} | |
| 12710 | |
| 12711 // Max Register with Register | |
| 12712 // *** Min and Max using the conditional move are slower than the | |
| 12713 // *** branch version on a Pentium III. | |
| 12714 // // Conditional move for max | |
| 12715 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12716 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12717 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12718 // opcode(0x4F,0x0F); | |
| 12719 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12720 // ins_pipe( pipe_cmov_reg ); | |
| 12721 //%} | |
| 12722 // | |
| 12723 // // Max Register with Register (P6 version) | |
| 12724 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12725 // predicate(VM_Version::supports_cmov() ); | |
| 12726 // match(Set op2 (MaxI op1 op2)); | |
| 12727 // ins_cost(200); | |
| 12728 // expand %{ | |
| 12729 // eFlagsReg cr; | |
| 12730 // compI_eReg(cr,op1,op2); | |
| 12731 // cmovI_reg_gt(op2,op1,cr); | |
| 12732 // %} | |
| 12733 //%} | |
| 12734 | |
| 12735 // Max Register with Register (generic version) | |
| 12736 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12737 match(Set dst (MaxI dst src)); | |
| 12738 effect(KILL flags); | |
| 12739 ins_cost(300); | |
| 12740 | |
| 12741 format %{ "MAX $dst,$src" %} | |
| 12742 opcode(0xCC); | |
| 12743 ins_encode( max_enc(dst,src) ); | |
| 12744 ins_pipe( pipe_slow ); | |
| 12745 %} | |
| 12746 | |
| 12747 // ============================================================================ | |
| 12748 // Branch Instructions | |
| 12749 // Jump Table | |
| 12750 instruct jumpXtnd(eRegI switch_val) %{ | |
| 12751 match(Jump switch_val); | |
| 12752 ins_cost(350); | |
| 12753 | |
| 12754 format %{ "JMP [table_base](,$switch_val,1)\n\t" %} | |
| 12755 | |
| 12756 ins_encode %{ | |
| 12757 address table_base = __ address_table_constant(_index2label); | |
| 12758 | |
| 12759 // Jump to Address(table_base + switch_reg) | |
| 12760 InternalAddress table(table_base); | |
| 12761 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 12762 __ jump(ArrayAddress(table, index)); | |
| 12763 %} | |
| 12764 ins_pc_relative(1); | |
| 12765 ins_pipe(pipe_jmp); | |
| 12766 %} | |
| 12767 | |
| 12768 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12769 instruct jmpDir(label labl) %{ | |
| 12770 match(Goto); | |
| 12771 effect(USE labl); | |
| 12772 | |
| 12773 ins_cost(300); | |
| 12774 format %{ "JMP $labl" %} | |
| 12775 size(5); | |
| 12776 opcode(0xE9); | |
| 12777 ins_encode( OpcP, Lbl( labl ) ); | |
| 12778 ins_pipe( pipe_jmp ); | |
| 12779 ins_pc_relative(1); | |
| 12780 %} | |
| 12781 | |
| 12782 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12783 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12784 match(If cop cr); | |
| 12785 effect(USE labl); | |
| 12786 | |
| 12787 ins_cost(300); | |
| 12788 format %{ "J$cop $labl" %} | |
| 12789 size(6); | |
| 12790 opcode(0x0F, 0x80); | |
| 12791 ins_encode( Jcc( cop, labl) ); | |
| 12792 ins_pipe( pipe_jcc ); | |
| 12793 ins_pc_relative(1); | |
| 12794 %} | |
| 12795 | |
| 12796 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12797 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12798 match(CountedLoopEnd cop cr); | |
| 12799 effect(USE labl); | |
| 12800 | |
| 12801 ins_cost(300); | |
| 12802 format %{ "J$cop $labl\t# Loop end" %} | |
| 12803 size(6); | |
| 12804 opcode(0x0F, 0x80); | |
| 12805 ins_encode( Jcc( cop, labl) ); | |
| 12806 ins_pipe( pipe_jcc ); | |
| 12807 ins_pc_relative(1); | |
| 12808 %} | |
| 12809 | |
| 12810 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12811 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12812 match(CountedLoopEnd cop cmp); | |
| 12813 effect(USE labl); | |
| 12814 | |
| 12815 ins_cost(300); | |
| 12816 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12817 size(6); | |
| 12818 opcode(0x0F, 0x80); | |
| 12819 ins_encode( Jcc( cop, labl) ); | |
| 12820 ins_pipe( pipe_jcc ); | |
| 12821 ins_pc_relative(1); | |
| 12822 %} | |
| 12823 | |
|
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12824 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12825 match(CountedLoopEnd cop cmp); |
|
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|
12826 effect(USE labl); |
|
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|
12827 |
|
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|
12828 ins_cost(200); |
|
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|
12829 format %{ "J$cop,u $labl\t# Loop end" %} |
|
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|
12830 size(6); |
|
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|
12831 opcode(0x0F, 0x80); |
|
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|
12832 ins_encode( Jcc( cop, labl) ); |
|
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|
12833 ins_pipe( pipe_jcc ); |
|
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|
12834 ins_pc_relative(1); |
|
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|
12835 %} |
|
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|
12836 |
| 0 | 12837 // Jump Direct Conditional - using unsigned comparison |
| 12838 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12839 match(If cop cmp); | |
| 12840 effect(USE labl); | |
| 12841 | |
| 12842 ins_cost(300); | |
| 12843 format %{ "J$cop,u $labl" %} | |
| 12844 size(6); | |
| 12845 opcode(0x0F, 0x80); | |
|
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|
12846 ins_encode(Jcc(cop, labl)); |
|
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|
12847 ins_pipe(pipe_jcc); |
|
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|
12848 ins_pc_relative(1); |
|
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|
12849 %} |
|
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|
12850 |
|
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|
12851 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12852 match(If cop cmp); |
|
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|
12853 effect(USE labl); |
|
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diff
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|
12854 |
|
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diff
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|
12855 ins_cost(200); |
|
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diff
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|
12856 format %{ "J$cop,u $labl" %} |
|
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diff
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|
12857 size(6); |
|
4d9884b01ba6
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diff
changeset
|
12858 opcode(0x0F, 0x80); |
|
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|
12859 ins_encode(Jcc(cop, labl)); |
|
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|
12860 ins_pipe(pipe_jcc); |
|
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diff
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|
12861 ins_pc_relative(1); |
|
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diff
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|
12862 %} |
|
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diff
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|
12863 |
|
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diff
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|
12864 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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diff
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|
12865 match(If cop cmp); |
|
4d9884b01ba6
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diff
changeset
|
12866 effect(USE labl); |
|
4d9884b01ba6
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diff
changeset
|
12867 |
|
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|
12868 ins_cost(200); |
|
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|
12869 format %{ $$template |
|
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|
12870 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12871 $$emit$$"JP,u $labl\n\t" |
|
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12872 $$emit$$"J$cop,u $labl" |
|
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|
12873 } else { |
|
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|
12874 $$emit$$"JP,u done\n\t" |
|
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|
12875 $$emit$$"J$cop,u $labl\n\t" |
|
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|
12876 $$emit$$"done:" |
|
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|
12877 } |
|
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|
12878 %} |
|
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changeset
|
12879 size(12); |
|
4d9884b01ba6
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|
12880 opcode(0x0F, 0x80); |
|
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|
12881 ins_encode %{ |
|
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|
12882 Label* l = $labl$$label; |
|
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|
12883 $$$emit8$primary; |
|
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|
12884 emit_cc(cbuf, $secondary, Assembler::parity); |
|
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|
12885 int parity_disp = -1; |
|
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|
12886 bool ok = false; |
|
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|
12887 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12888 // the two jumps 6 bytes apart so the jump distances are too |
|
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|
12889 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
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|
12890 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12891 parity_disp = 6; |
|
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|
12892 ok = true; |
|
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|
12893 } else { |
|
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changeset
|
12894 ShouldNotReachHere(); |
|
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|
12895 } |
|
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|
12896 emit_d32(cbuf, parity_disp); |
|
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|
12897 $$$emit8$primary; |
|
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|
12898 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
|
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|
12899 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
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|
12900 emit_d32(cbuf, disp); |
|
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|
12901 %} |
|
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|
12902 ins_pipe(pipe_jcc); |
| 0 | 12903 ins_pc_relative(1); |
| 12904 %} | |
| 12905 | |
| 12906 // ============================================================================ | |
| 12907 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12908 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12909 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12910 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12911 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12912 match(Set result (PartialSubtypeCheck sub super)); | |
| 12913 effect( KILL rcx, KILL cr ); | |
| 12914 | |
| 12915 ins_cost(1100); // slightly larger than the next version | |
|
644
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|
12916 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12917 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12918 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12919 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12920 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12921 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12922 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12923 "miss:\t" %} | |
| 12924 | |
| 12925 opcode(0x1); // Force a XOR of EDI | |
| 12926 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12927 ins_pipe( pipe_slow ); | |
| 12928 %} | |
| 12929 | |
| 12930 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12931 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12932 effect( KILL rcx, KILL result ); | |
| 12933 | |
| 12934 ins_cost(1000); | |
|
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|
12935 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12936 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12937 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12938 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12939 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12940 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12941 "miss:\t" %} | |
| 12942 | |
| 12943 opcode(0x0); // No need to XOR EDI | |
| 12944 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12945 ins_pipe( pipe_slow ); | |
| 12946 %} | |
| 12947 | |
| 12948 // ============================================================================ | |
| 12949 // Branch Instructions -- short offset versions | |
| 12950 // | |
| 12951 // These instructions are used to replace jumps of a long offset (the default | |
| 12952 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12953 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12954 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12955 // method in the MachNode which can be used to do in-place replacement of the | |
| 12956 // long variant with the shorter variant. The compiler will determine if a | |
| 12957 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12958 // specific code section of the file. | |
| 12959 | |
| 12960 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12961 instruct jmpDir_short(label labl) %{ | |
| 12962 match(Goto); | |
| 12963 effect(USE labl); | |
| 12964 | |
| 12965 ins_cost(300); | |
| 12966 format %{ "JMP,s $labl" %} | |
| 12967 size(2); | |
| 12968 opcode(0xEB); | |
| 12969 ins_encode( OpcP, LblShort( labl ) ); | |
| 12970 ins_pipe( pipe_jmp ); | |
| 12971 ins_pc_relative(1); | |
| 12972 ins_short_branch(1); | |
| 12973 %} | |
| 12974 | |
| 12975 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12976 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12977 match(If cop cr); | |
| 12978 effect(USE labl); | |
| 12979 | |
| 12980 ins_cost(300); | |
| 12981 format %{ "J$cop,s $labl" %} | |
| 12982 size(2); | |
| 12983 opcode(0x70); | |
| 12984 ins_encode( JccShort( cop, labl) ); | |
| 12985 ins_pipe( pipe_jcc ); | |
| 12986 ins_pc_relative(1); | |
| 12987 ins_short_branch(1); | |
| 12988 %} | |
| 12989 | |
| 12990 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12991 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12992 match(CountedLoopEnd cop cr); | |
| 12993 effect(USE labl); | |
| 12994 | |
| 12995 ins_cost(300); | |
|
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|
12996 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12997 size(2); |
| 12998 opcode(0x70); | |
| 12999 ins_encode( JccShort( cop, labl) ); | |
| 13000 ins_pipe( pipe_jcc ); | |
| 13001 ins_pc_relative(1); | |
| 13002 ins_short_branch(1); | |
| 13003 %} | |
| 13004 | |
| 13005 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13006 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13007 match(CountedLoopEnd cop cmp); | |
| 13008 effect(USE labl); | |
| 13009 | |
| 13010 ins_cost(300); | |
|
415
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|
13011 format %{ "J$cop,us $labl\t# Loop end" %} |
|
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|
13012 size(2); |
|
4d9884b01ba6
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changeset
|
13013 opcode(0x70); |
|
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|
13014 ins_encode( JccShort( cop, labl) ); |
|
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|
13015 ins_pipe( pipe_jcc ); |
|
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|
13016 ins_pc_relative(1); |
|
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diff
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|
13017 ins_short_branch(1); |
|
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diff
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|
13018 %} |
|
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403
diff
changeset
|
13019 |
|
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403
diff
changeset
|
13020 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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changeset
|
13021 match(CountedLoopEnd cop cmp); |
|
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|
13022 effect(USE labl); |
|
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diff
changeset
|
13023 |
|
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changeset
|
13024 ins_cost(300); |
|
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diff
changeset
|
13025 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 13026 size(2); |
| 13027 opcode(0x70); | |
| 13028 ins_encode( JccShort( cop, labl) ); | |
| 13029 ins_pipe( pipe_jcc ); | |
| 13030 ins_pc_relative(1); | |
| 13031 ins_short_branch(1); | |
| 13032 %} | |
| 13033 | |
| 13034 // Jump Direct Conditional - using unsigned comparison | |
| 13035 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13036 match(If cop cmp); | |
| 13037 effect(USE labl); | |
| 13038 | |
| 13039 ins_cost(300); | |
| 13040 format %{ "J$cop,us $labl" %} | |
| 13041 size(2); | |
| 13042 opcode(0x70); | |
| 13043 ins_encode( JccShort( cop, labl) ); | |
| 13044 ins_pipe( pipe_jcc ); | |
| 13045 ins_pc_relative(1); | |
| 13046 ins_short_branch(1); | |
| 13047 %} | |
| 13048 | |
|
415
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|
13049 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13050 match(If cop cmp); |
|
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diff
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|
13051 effect(USE labl); |
|
4d9884b01ba6
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diff
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|
13052 |
|
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diff
changeset
|
13053 ins_cost(300); |
|
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diff
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|
13054 format %{ "J$cop,us $labl" %} |
|
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parents:
403
diff
changeset
|
13055 size(2); |
|
4d9884b01ba6
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diff
changeset
|
13056 opcode(0x70); |
|
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diff
changeset
|
13057 ins_encode( JccShort( cop, labl) ); |
|
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|
13058 ins_pipe( pipe_jcc ); |
|
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|
13059 ins_pc_relative(1); |
|
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diff
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|
13060 ins_short_branch(1); |
|
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diff
changeset
|
13061 %} |
|
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changeset
|
13062 |
|
4d9884b01ba6
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changeset
|
13063 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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changeset
|
13064 match(If cop cmp); |
|
4d9884b01ba6
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diff
changeset
|
13065 effect(USE labl); |
|
4d9884b01ba6
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diff
changeset
|
13066 |
|
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changeset
|
13067 ins_cost(300); |
|
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diff
changeset
|
13068 format %{ $$template |
|
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diff
changeset
|
13069 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
13070 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
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|
13071 $$emit$$"J$cop,u,s $labl" |
|
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diff
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|
13072 } else { |
|
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changeset
|
13073 $$emit$$"JP,u,s done\n\t" |
|
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|
13074 $$emit$$"J$cop,u,s $labl\n\t" |
|
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changeset
|
13075 $$emit$$"done:" |
|
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diff
changeset
|
13076 } |
|
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never
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403
diff
changeset
|
13077 %} |
|
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never
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403
diff
changeset
|
13078 size(4); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
13079 opcode(0x70); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
13080 ins_encode %{ |
|
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|
13081 Label* l = $labl$$label; |
|
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13082 emit_cc(cbuf, $primary, Assembler::parity); |
|
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13083 int parity_disp = -1; |
|
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13084 if ($cop$$cmpcode == Assembler::notEqual) { |
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13085 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
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13086 } else if ($cop$$cmpcode == Assembler::equal) { |
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13087 parity_disp = 2; |
|
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|
13088 } else { |
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|
13089 ShouldNotReachHere(); |
|
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|
13090 } |
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|
13091 emit_d8(cbuf, parity_disp); |
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13092 emit_cc(cbuf, $primary, $cop$$cmpcode); |
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13093 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
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13094 emit_d8(cbuf, disp); |
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13095 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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13096 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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13097 %} |
|
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|
13098 ins_pipe(pipe_jcc); |
|
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13099 ins_pc_relative(1); |
|
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13100 ins_short_branch(1); |
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13101 %} |
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|
13102 |
| 0 | 13103 // ============================================================================ |
| 13104 // Long Compare | |
| 13105 // | |
| 13106 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 13107 // is tricky. The flavor of compare used depends on whether we are testing | |
| 13108 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 13109 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 13110 // the operands (yielding a GE test) and then negating; negate again for the | |
| 13111 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 13112 // NE test is negated from that. | |
| 13113 | |
| 13114 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 13115 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 13116 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 13117 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 13118 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 13119 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 13120 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 13121 // both forms beat the trinary form of long-compare and both are very useful | |
| 13122 // on Intel which has so few registers. | |
| 13123 | |
| 13124 // Manifest a CmpL result in an integer register. Very painful. | |
| 13125 // This is the test to avoid. | |
| 13126 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 13127 match(Set dst (CmpL3 src1 src2)); | |
| 13128 effect( KILL flags ); | |
| 13129 ins_cost(1000); | |
| 13130 format %{ "XOR $dst,$dst\n\t" | |
| 13131 "CMP $src1.hi,$src2.hi\n\t" | |
| 13132 "JLT,s m_one\n\t" | |
| 13133 "JGT,s p_one\n\t" | |
| 13134 "CMP $src1.lo,$src2.lo\n\t" | |
| 13135 "JB,s m_one\n\t" | |
| 13136 "JEQ,s done\n" | |
| 13137 "p_one:\tINC $dst\n\t" | |
| 13138 "JMP,s done\n" | |
| 13139 "m_one:\tDEC $dst\n" | |
| 13140 "done:" %} | |
| 13141 ins_encode %{ | |
| 13142 Label p_one, m_one, done; | |
| 304 | 13143 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 13144 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 13145 __ jccb(Assembler::less, m_one); | |
| 13146 __ jccb(Assembler::greater, p_one); | |
| 13147 __ cmpl($src1$$Register, $src2$$Register); | |
| 13148 __ jccb(Assembler::below, m_one); | |
| 13149 __ jccb(Assembler::equal, done); | |
| 13150 __ bind(p_one); | |
| 304 | 13151 __ incrementl($dst$$Register); |
| 0 | 13152 __ jmpb(done); |
| 13153 __ bind(m_one); | |
| 304 | 13154 __ decrementl($dst$$Register); |
| 0 | 13155 __ bind(done); |
| 13156 %} | |
| 13157 ins_pipe( pipe_slow ); | |
| 13158 %} | |
| 13159 | |
| 13160 //====== | |
| 13161 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13162 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13163 // NOT GOOD FOR EQ/NE tests. | |
| 13164 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 13165 match( Set flags (CmpL src zero )); | |
| 13166 ins_cost(100); | |
| 13167 format %{ "TEST $src.hi,$src.hi" %} | |
| 13168 opcode(0x85); | |
| 13169 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 13170 ins_pipe( ialu_cr_reg_reg ); | |
| 13171 %} | |
| 13172 | |
| 13173 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13174 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13175 // NOT GOOD FOR EQ/NE tests. | |
| 13176 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13177 match( Set flags (CmpL src1 src2 )); | |
| 13178 effect( TEMP tmp ); | |
| 13179 ins_cost(300); | |
| 13180 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13181 "MOV $tmp,$src1.hi\n\t" | |
| 13182 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 13183 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 13184 ins_pipe( ialu_cr_reg_reg ); | |
| 13185 %} | |
| 13186 | |
| 13187 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13188 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13189 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 13190 match(If cmp flags); | |
| 13191 effect(USE labl); | |
| 13192 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13193 expand %{ | |
| 13194 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 13195 %} | |
| 13196 %} | |
| 13197 | |
| 13198 // Compare 2 longs and CMOVE longs. | |
| 13199 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 13200 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13201 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13202 ins_cost(400); | |
| 13203 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13204 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13205 opcode(0x0F,0x40); | |
| 13206 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13207 ins_pipe( pipe_cmov_reg_long ); | |
| 13208 %} | |
| 13209 | |
| 13210 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 13211 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13212 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13213 ins_cost(500); | |
| 13214 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13215 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13216 opcode(0x0F,0x40); | |
| 13217 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13218 ins_pipe( pipe_cmov_reg_long ); | |
| 13219 %} | |
| 13220 | |
| 13221 // Compare 2 longs and CMOVE ints. | |
| 13222 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ | |
| 13223 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13224 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13225 ins_cost(200); | |
| 13226 format %{ "CMOV$cmp $dst,$src" %} | |
| 13227 opcode(0x0F,0x40); | |
| 13228 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13229 ins_pipe( pipe_cmov_reg ); | |
| 13230 %} | |
| 13231 | |
| 13232 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ | |
| 13233 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13234 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13235 ins_cost(250); | |
| 13236 format %{ "CMOV$cmp $dst,$src" %} | |
| 13237 opcode(0x0F,0x40); | |
| 13238 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13239 ins_pipe( pipe_cmov_mem ); | |
| 13240 %} | |
| 13241 | |
| 13242 // Compare 2 longs and CMOVE ints. | |
| 13243 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 13244 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13245 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13246 ins_cost(200); | |
| 13247 format %{ "CMOV$cmp $dst,$src" %} | |
| 13248 opcode(0x0F,0x40); | |
| 13249 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13250 ins_pipe( pipe_cmov_reg ); | |
| 13251 %} | |
| 13252 | |
| 13253 // Compare 2 longs and CMOVE doubles | |
| 13254 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ | |
| 13255 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13256 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13257 ins_cost(200); | |
| 13258 expand %{ | |
| 13259 fcmovD_regS(cmp,flags,dst,src); | |
| 13260 %} | |
| 13261 %} | |
| 13262 | |
| 13263 // Compare 2 longs and CMOVE doubles | |
| 13264 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ | |
| 13265 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13266 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13267 ins_cost(200); | |
| 13268 expand %{ | |
| 13269 fcmovXD_regS(cmp,flags,dst,src); | |
| 13270 %} | |
| 13271 %} | |
| 13272 | |
| 13273 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
| 13274 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13275 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13276 ins_cost(200); | |
| 13277 expand %{ | |
| 13278 fcmovF_regS(cmp,flags,dst,src); | |
| 13279 %} | |
| 13280 %} | |
| 13281 | |
| 13282 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ | |
| 13283 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13284 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13285 ins_cost(200); | |
| 13286 expand %{ | |
| 13287 fcmovX_regS(cmp,flags,dst,src); | |
| 13288 %} | |
| 13289 %} | |
| 13290 | |
| 13291 //====== | |
| 13292 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13293 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13294 match( Set flags (CmpL src zero )); | |
| 13295 effect(TEMP tmp); | |
| 13296 ins_cost(200); | |
| 13297 format %{ "MOV $tmp,$src.lo\n\t" | |
| 13298 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 13299 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 13300 ins_pipe( ialu_reg_reg_long ); | |
| 13301 %} | |
| 13302 | |
| 13303 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13304 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 13305 match( Set flags (CmpL src1 src2 )); | |
| 13306 ins_cost(200+300); | |
| 13307 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13308 "JNE,s skip\n\t" | |
| 13309 "CMP $src1.hi,$src2.hi\n\t" | |
| 13310 "skip:\t" %} | |
| 13311 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 13312 ins_pipe( ialu_cr_reg_reg ); | |
| 13313 %} | |
| 13314 | |
| 13315 // Long compare reg == zero/reg OR reg != zero/reg | |
| 13316 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13317 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 13318 match(If cmp flags); | |
| 13319 effect(USE labl); | |
| 13320 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13321 expand %{ | |
| 13322 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 13323 %} | |
| 13324 %} | |
| 13325 | |
| 13326 // Compare 2 longs and CMOVE longs. | |
| 13327 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 13328 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13329 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13330 ins_cost(400); | |
| 13331 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13332 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13333 opcode(0x0F,0x40); | |
| 13334 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13335 ins_pipe( pipe_cmov_reg_long ); | |
| 13336 %} | |
| 13337 | |
| 13338 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 13339 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13340 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13341 ins_cost(500); | |
| 13342 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13343 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13344 opcode(0x0F,0x40); | |
| 13345 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13346 ins_pipe( pipe_cmov_reg_long ); | |
| 13347 %} | |
| 13348 | |
| 13349 // Compare 2 longs and CMOVE ints. | |
| 13350 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ | |
| 13351 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13352 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13353 ins_cost(200); | |
| 13354 format %{ "CMOV$cmp $dst,$src" %} | |
| 13355 opcode(0x0F,0x40); | |
| 13356 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13357 ins_pipe( pipe_cmov_reg ); | |
| 13358 %} | |
| 13359 | |
| 13360 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ | |
| 13361 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13362 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13363 ins_cost(250); | |
| 13364 format %{ "CMOV$cmp $dst,$src" %} | |
| 13365 opcode(0x0F,0x40); | |
| 13366 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13367 ins_pipe( pipe_cmov_mem ); | |
| 13368 %} | |
| 13369 | |
| 13370 // Compare 2 longs and CMOVE ints. | |
| 13371 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 13372 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13373 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13374 ins_cost(200); | |
| 13375 format %{ "CMOV$cmp $dst,$src" %} | |
| 13376 opcode(0x0F,0x40); | |
| 13377 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13378 ins_pipe( pipe_cmov_reg ); | |
| 13379 %} | |
| 13380 | |
| 13381 // Compare 2 longs and CMOVE doubles | |
| 13382 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ | |
| 13383 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13384 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13385 ins_cost(200); | |
| 13386 expand %{ | |
| 13387 fcmovD_regS(cmp,flags,dst,src); | |
| 13388 %} | |
| 13389 %} | |
| 13390 | |
| 13391 // Compare 2 longs and CMOVE doubles | |
| 13392 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ | |
| 13393 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13394 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13395 ins_cost(200); | |
| 13396 expand %{ | |
| 13397 fcmovXD_regS(cmp,flags,dst,src); | |
| 13398 %} | |
| 13399 %} | |
| 13400 | |
| 13401 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
| 13402 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13403 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13404 ins_cost(200); | |
| 13405 expand %{ | |
| 13406 fcmovF_regS(cmp,flags,dst,src); | |
| 13407 %} | |
| 13408 %} | |
| 13409 | |
| 13410 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ | |
| 13411 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13412 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13413 ins_cost(200); | |
| 13414 expand %{ | |
| 13415 fcmovX_regS(cmp,flags,dst,src); | |
| 13416 %} | |
| 13417 %} | |
| 13418 | |
| 13419 //====== | |
| 13420 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13421 // Same as cmpL_reg_flags_LEGT except must negate src | |
| 13422 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13423 match( Set flags (CmpL src zero )); | |
| 13424 effect( TEMP tmp ); | |
| 13425 ins_cost(300); | |
| 13426 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 13427 "CMP $tmp,$src.lo\n\t" | |
| 13428 "SBB $tmp,$src.hi\n\t" %} | |
| 13429 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 13430 ins_pipe( ialu_reg_reg_long ); | |
| 13431 %} | |
| 13432 | |
| 13433 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13434 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 13435 // requires a commuted test to get the same result. | |
| 13436 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13437 match( Set flags (CmpL src1 src2 )); | |
| 13438 effect( TEMP tmp ); | |
| 13439 ins_cost(300); | |
| 13440 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 13441 "MOV $tmp,$src2.hi\n\t" | |
| 13442 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 13443 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 13444 ins_pipe( ialu_cr_reg_reg ); | |
| 13445 %} | |
| 13446 | |
| 13447 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13448 // Just a wrapper for a normal branch, plus the predicate test | |
| 13449 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 13450 match(If cmp flags); | |
| 13451 effect(USE labl); | |
| 13452 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 13453 ins_cost(300); | |
| 13454 expand %{ | |
| 13455 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 13456 %} | |
| 13457 %} | |
| 13458 | |
| 13459 // Compare 2 longs and CMOVE longs. | |
| 13460 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 13461 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13462 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13463 ins_cost(400); | |
| 13464 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13465 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13466 opcode(0x0F,0x40); | |
| 13467 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13468 ins_pipe( pipe_cmov_reg_long ); | |
| 13469 %} | |
| 13470 | |
| 13471 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 13472 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13473 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13474 ins_cost(500); | |
| 13475 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13476 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 13477 opcode(0x0F,0x40); | |
| 13478 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13479 ins_pipe( pipe_cmov_reg_long ); | |
| 13480 %} | |
| 13481 | |
| 13482 // Compare 2 longs and CMOVE ints. | |
| 13483 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ | |
| 13484 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13485 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13486 ins_cost(200); | |
| 13487 format %{ "CMOV$cmp $dst,$src" %} | |
| 13488 opcode(0x0F,0x40); | |
| 13489 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13490 ins_pipe( pipe_cmov_reg ); | |
| 13491 %} | |
| 13492 | |
| 13493 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ | |
| 13494 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13495 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13496 ins_cost(250); | |
| 13497 format %{ "CMOV$cmp $dst,$src" %} | |
| 13498 opcode(0x0F,0x40); | |
| 13499 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13500 ins_pipe( pipe_cmov_mem ); | |
| 13501 %} | |
| 13502 | |
| 13503 // Compare 2 longs and CMOVE ptrs. | |
| 13504 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 13505 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13506 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13507 ins_cost(200); | |
| 13508 format %{ "CMOV$cmp $dst,$src" %} | |
| 13509 opcode(0x0F,0x40); | |
| 13510 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13511 ins_pipe( pipe_cmov_reg ); | |
| 13512 %} | |
| 13513 | |
| 13514 // Compare 2 longs and CMOVE doubles | |
| 13515 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ | |
| 13516 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13517 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13518 ins_cost(200); | |
| 13519 expand %{ | |
| 13520 fcmovD_regS(cmp,flags,dst,src); | |
| 13521 %} | |
| 13522 %} | |
| 13523 | |
| 13524 // Compare 2 longs and CMOVE doubles | |
| 13525 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ | |
| 13526 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13527 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13528 ins_cost(200); | |
| 13529 expand %{ | |
| 13530 fcmovXD_regS(cmp,flags,dst,src); | |
| 13531 %} | |
| 13532 %} | |
| 13533 | |
| 13534 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
| 13535 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13536 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13537 ins_cost(200); | |
| 13538 expand %{ | |
| 13539 fcmovF_regS(cmp,flags,dst,src); | |
| 13540 %} | |
| 13541 %} | |
| 13542 | |
| 13543 | |
| 13544 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ | |
| 13545 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13546 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13547 ins_cost(200); | |
| 13548 expand %{ | |
| 13549 fcmovX_regS(cmp,flags,dst,src); | |
| 13550 %} | |
| 13551 %} | |
| 13552 | |
| 13553 | |
| 13554 // ============================================================================ | |
| 13555 // Procedure Call/Return Instructions | |
| 13556 // Call Java Static Instruction | |
| 13557 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13558 // compute_padding() functions will have to be adjusted. | |
| 13559 instruct CallStaticJavaDirect(method meth) %{ | |
| 13560 match(CallStaticJava); | |
|
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13561 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 13562 effect(USE meth); |
| 13563 | |
| 13564 ins_cost(300); | |
| 13565 format %{ "CALL,static " %} | |
| 13566 opcode(0xE8); /* E8 cd */ | |
| 13567 ins_encode( pre_call_FPU, | |
| 13568 Java_Static_Call( meth ), | |
| 13569 call_epilog, | |
| 13570 post_call_FPU ); | |
| 13571 ins_pipe( pipe_slow ); | |
| 13572 ins_pc_relative(1); | |
| 13573 ins_alignment(4); | |
| 13574 %} | |
| 13575 | |
|
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13576 // Call Java Static Instruction (method handle version) |
|
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13577 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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13578 // compute_padding() functions will have to be adjusted. |
| 1567 | 13579 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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13580 match(CallStaticJava); |
|
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13581 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
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13582 effect(USE meth); |
|
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13583 // EBP is saved by all callees (for interpreter stack correction). |
|
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13584 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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13585 |
|
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13586 ins_cost(300); |
|
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13587 format %{ "CALL,static/MethodHandle " %} |
|
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13588 opcode(0xE8); /* E8 cd */ |
|
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13589 ins_encode( pre_call_FPU, |
|
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13590 preserve_SP, |
|
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13591 Java_Static_Call( meth ), |
|
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13592 restore_SP, |
|
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13593 call_epilog, |
|
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13594 post_call_FPU ); |
|
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13595 ins_pipe( pipe_slow ); |
|
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13596 ins_pc_relative(1); |
|
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13597 ins_alignment(4); |
|
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13598 %} |
|
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13599 |
| 0 | 13600 // Call Java Dynamic Instruction |
| 13601 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13602 // compute_padding() functions will have to be adjusted. | |
| 13603 instruct CallDynamicJavaDirect(method meth) %{ | |
| 13604 match(CallDynamicJava); | |
| 13605 effect(USE meth); | |
| 13606 | |
| 13607 ins_cost(300); | |
| 13608 format %{ "MOV EAX,(oop)-1\n\t" | |
| 13609 "CALL,dynamic" %} | |
| 13610 opcode(0xE8); /* E8 cd */ | |
| 13611 ins_encode( pre_call_FPU, | |
| 13612 Java_Dynamic_Call( meth ), | |
| 13613 call_epilog, | |
| 13614 post_call_FPU ); | |
| 13615 ins_pipe( pipe_slow ); | |
| 13616 ins_pc_relative(1); | |
| 13617 ins_alignment(4); | |
| 13618 %} | |
| 13619 | |
| 13620 // Call Runtime Instruction | |
| 13621 instruct CallRuntimeDirect(method meth) %{ | |
| 13622 match(CallRuntime ); | |
| 13623 effect(USE meth); | |
| 13624 | |
| 13625 ins_cost(300); | |
| 13626 format %{ "CALL,runtime " %} | |
| 13627 opcode(0xE8); /* E8 cd */ | |
| 13628 // Use FFREEs to clear entries in float stack | |
| 13629 ins_encode( pre_call_FPU, | |
| 13630 FFree_Float_Stack_All, | |
| 13631 Java_To_Runtime( meth ), | |
| 13632 post_call_FPU ); | |
| 13633 ins_pipe( pipe_slow ); | |
| 13634 ins_pc_relative(1); | |
| 13635 %} | |
| 13636 | |
| 13637 // Call runtime without safepoint | |
| 13638 instruct CallLeafDirect(method meth) %{ | |
| 13639 match(CallLeaf); | |
| 13640 effect(USE meth); | |
| 13641 | |
| 13642 ins_cost(300); | |
| 13643 format %{ "CALL_LEAF,runtime " %} | |
| 13644 opcode(0xE8); /* E8 cd */ | |
| 13645 ins_encode( pre_call_FPU, | |
| 13646 FFree_Float_Stack_All, | |
| 13647 Java_To_Runtime( meth ), | |
| 13648 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13649 ins_pipe( pipe_slow ); | |
| 13650 ins_pc_relative(1); | |
| 13651 %} | |
| 13652 | |
| 13653 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13654 match(CallLeafNoFP); | |
| 13655 effect(USE meth); | |
| 13656 | |
| 13657 ins_cost(300); | |
| 13658 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13659 opcode(0xE8); /* E8 cd */ | |
| 13660 ins_encode(Java_To_Runtime(meth)); | |
| 13661 ins_pipe( pipe_slow ); | |
| 13662 ins_pc_relative(1); | |
| 13663 %} | |
| 13664 | |
| 13665 | |
| 13666 // Return Instruction | |
| 13667 // Remove the return address & jump to it. | |
| 13668 instruct Ret() %{ | |
| 13669 match(Return); | |
| 13670 format %{ "RET" %} | |
| 13671 opcode(0xC3); | |
| 13672 ins_encode(OpcP); | |
| 13673 ins_pipe( pipe_jmp ); | |
| 13674 %} | |
| 13675 | |
| 13676 // Tail Call; Jump from runtime stub to Java code. | |
| 13677 // Also known as an 'interprocedural jump'. | |
| 13678 // Target of jump will eventually return to caller. | |
| 13679 // TailJump below removes the return address. | |
| 13680 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13681 match(TailCall jump_target method_oop ); | |
| 13682 ins_cost(300); | |
| 13683 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13684 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13685 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13686 ins_pipe( pipe_jmp ); | |
| 13687 %} | |
| 13688 | |
| 13689 | |
| 13690 // Tail Jump; remove the return address; jump to target. | |
| 13691 // TailCall above leaves the return address around. | |
| 13692 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13693 match( TailJump jump_target ex_oop ); | |
| 13694 ins_cost(300); | |
| 13695 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13696 "JMP $jump_target " %} | |
| 13697 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13698 ins_encode( enc_pop_rdx, | |
| 13699 OpcP, RegOpc(jump_target) ); | |
| 13700 ins_pipe( pipe_jmp ); | |
| 13701 %} | |
| 13702 | |
| 13703 // Create exception oop: created by stack-crawling runtime code. | |
| 13704 // Created exception is now available to this handler, and is setup | |
| 13705 // just prior to jumping to this handler. No code emitted. | |
| 13706 instruct CreateException( eAXRegP ex_oop ) | |
| 13707 %{ | |
| 13708 match(Set ex_oop (CreateEx)); | |
| 13709 | |
| 13710 size(0); | |
| 13711 // use the following format syntax | |
| 13712 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13713 ins_encode(); | |
| 13714 ins_pipe( empty ); | |
| 13715 %} | |
| 13716 | |
| 13717 | |
| 13718 // Rethrow exception: | |
| 13719 // The exception oop will come in the first argument position. | |
| 13720 // Then JUMP (not call) to the rethrow stub code. | |
| 13721 instruct RethrowException() | |
| 13722 %{ | |
| 13723 match(Rethrow); | |
| 13724 | |
| 13725 // use the following format syntax | |
| 13726 format %{ "JMP rethrow_stub" %} | |
| 13727 ins_encode(enc_rethrow); | |
| 13728 ins_pipe( pipe_jmp ); | |
| 13729 %} | |
| 13730 | |
| 13731 // inlined locking and unlocking | |
| 13732 | |
| 13733 | |
| 13734 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ | |
| 13735 match( Set cr (FastLock object box) ); | |
| 13736 effect( TEMP tmp, TEMP scr ); | |
| 13737 ins_cost(300); | |
| 13738 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} | |
| 13739 ins_encode( Fast_Lock(object,box,tmp,scr) ); | |
| 13740 ins_pipe( pipe_slow ); | |
| 13741 ins_pc_relative(1); | |
| 13742 %} | |
| 13743 | |
| 13744 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 13745 match( Set cr (FastUnlock object box) ); | |
| 13746 effect( TEMP tmp ); | |
| 13747 ins_cost(300); | |
| 13748 format %{ "FASTUNLOCK $object, $box, $tmp" %} | |
| 13749 ins_encode( Fast_Unlock(object,box,tmp) ); | |
| 13750 ins_pipe( pipe_slow ); | |
| 13751 ins_pc_relative(1); | |
| 13752 %} | |
| 13753 | |
| 13754 | |
| 13755 | |
| 13756 // ============================================================================ | |
| 13757 // Safepoint Instruction | |
| 13758 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13759 match(SafePoint); | |
| 13760 effect(KILL cr); | |
| 13761 | |
| 13762 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13763 // On SPARC that might be acceptable as we can generate the address with | |
| 13764 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13765 // putting additional pressure on the index-0 in the D$. Because of | |
| 13766 // alignment (just like the situation at hand) the lower indices tend | |
| 13767 // to see more traffic. It'd be better to change the polling address | |
| 13768 // to offset 0 of the last $line in the polling page. | |
| 13769 | |
| 13770 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13771 ins_cost(125); | |
| 13772 size(6) ; | |
| 13773 ins_encode( Safepoint_Poll() ); | |
| 13774 ins_pipe( ialu_reg_mem ); | |
| 13775 %} | |
| 13776 | |
| 13777 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 13778 // These must follow all instruction definitions as they use the names | |
| 13779 // defined in the instructions definitions. | |
| 13780 // | |
| 605 | 13781 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13782 // |
| 13783 // peepconstraint %{ | |
| 13784 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13785 // [, ...] ); | |
| 13786 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13787 // | |
| 13788 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13789 // // provide an instruction_number.operand_name for each operand that appears | |
| 13790 // // in the replacement instruction's match rule | |
| 13791 // | |
| 13792 // ---------VM FLAGS--------------------------------------------------------- | |
| 13793 // | |
| 13794 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13795 // | |
| 13796 // Each peephole rule is given an identifying number starting with zero and | |
| 13797 // increasing by one in the order seen by the parser. An individual peephole | |
| 13798 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13799 // on the command-line. | |
| 13800 // | |
| 13801 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13802 // | |
| 13803 // Only match adjacent instructions in same basic block | |
| 13804 // Only equality constraints | |
| 13805 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13806 // Only one replacement instruction | |
| 13807 // | |
| 13808 // ---------EXAMPLE---------------------------------------------------------- | |
| 13809 // | |
| 13810 // // pertinent parts of existing instructions in architecture description | |
| 13811 // instruct movI(eRegI dst, eRegI src) %{ | |
| 13812 // match(Set dst (CopyI src)); | |
| 13813 // %} | |
| 13814 // | |
| 13815 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 13816 // match(Set dst (AddI dst src)); | |
| 13817 // effect(KILL cr); | |
| 13818 // %} | |
| 13819 // | |
| 13820 // // Change (inc mov) to lea | |
| 13821 // peephole %{ | |
| 13822 // // increment preceeded by register-register move | |
| 13823 // peepmatch ( incI_eReg movI ); | |
| 13824 // // require that the destination register of the increment | |
| 13825 // // match the destination register of the move | |
| 13826 // peepconstraint ( 0.dst == 1.dst ); | |
| 13827 // // construct a replacement instruction that sets | |
| 13828 // // the destination to ( move's source register + one ) | |
| 13829 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13830 // %} | |
| 13831 // | |
| 13832 // Implementation no longer uses movX instructions since | |
| 13833 // machine-independent system no longer uses CopyX nodes. | |
| 13834 // | |
| 13835 // peephole %{ | |
| 13836 // peepmatch ( incI_eReg movI ); | |
| 13837 // peepconstraint ( 0.dst == 1.dst ); | |
| 13838 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13839 // %} | |
| 13840 // | |
| 13841 // peephole %{ | |
| 13842 // peepmatch ( decI_eReg movI ); | |
| 13843 // peepconstraint ( 0.dst == 1.dst ); | |
| 13844 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13845 // %} | |
| 13846 // | |
| 13847 // peephole %{ | |
| 13848 // peepmatch ( addI_eReg_imm movI ); | |
| 13849 // peepconstraint ( 0.dst == 1.dst ); | |
| 13850 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13851 // %} | |
| 13852 // | |
| 13853 // peephole %{ | |
| 13854 // peepmatch ( addP_eReg_imm movP ); | |
| 13855 // peepconstraint ( 0.dst == 1.dst ); | |
| 13856 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13857 // %} | |
| 13858 | |
| 13859 // // Change load of spilled value to only a spill | |
| 13860 // instruct storeI(memory mem, eRegI src) %{ | |
| 13861 // match(Set mem (StoreI mem src)); | |
| 13862 // %} | |
| 13863 // | |
| 13864 // instruct loadI(eRegI dst, memory mem) %{ | |
| 13865 // match(Set dst (LoadI mem)); | |
| 13866 // %} | |
| 13867 // | |
| 13868 peephole %{ | |
| 13869 peepmatch ( loadI storeI ); | |
| 13870 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13871 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13872 %} | |
| 13873 | |
| 13874 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13875 // These must follow all instruction definitions as they use the names | |
| 13876 // defined in the instructions definitions. |