Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 3842:c7b60b601eb4
7069452: Cleanup NodeFlags
Summary: Remove flags which duplicate information in Node::NodeClasses.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Wed, 27 Jul 2011 17:28:36 -0700 |
| parents | 3d42f82cd811 |
| children | f1c12354c3f7 |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Special Registers | |
| 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); | |
| 79 | |
| 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 81 // allocator, and only shows up in the encodings. | |
| 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 84 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 85 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 87 // the stack will not have this element so FPR1 == st(0) from the | |
| 88 // oopMap viewpoint. This same weirdness with numbering causes | |
| 89 // instruction encoding to have to play games with the register | |
| 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 91 // where it does flt->flt moves to see an example | |
| 92 // | |
| 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 107 | |
| 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. | |
| 109 // Word a in each register holds a Float, words ab hold a Double. | |
| 110 // We currently do not use the SIMD capabilities, so registers cd | |
| 111 // are unused at the moment. | |
| 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 128 | |
| 129 // Specify priority of register selection within phases of register | |
| 130 // allocation. Highest priority is first. A useful heuristic is to | |
| 131 // give registers a low priority when they are required by machine | |
| 132 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 134 // For the Intel integer registers, the equivalent Long pairs are |
| 135 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 139 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 140 | |
| 141 alloc_class chunk1( XMM0a, XMM0b, | |
| 142 XMM1a, XMM1b, | |
| 143 XMM2a, XMM2b, | |
| 144 XMM3a, XMM3b, | |
| 145 XMM4a, XMM4b, | |
| 146 XMM5a, XMM5b, | |
| 147 XMM6a, XMM6b, | |
| 148 XMM7a, XMM7b, EFLAGS); | |
| 149 | |
| 150 | |
| 151 //----------Architecture Description Register Classes-------------------------- | |
| 152 // Several register classes are automatically defined based upon information in | |
| 153 // this architecture description. | |
| 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 158 // | |
| 159 // Class for all registers | |
| 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 161 // Class for general registers | |
| 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); | |
| 163 // Class for general registers which may be used for implicit null checks on win95 | |
| 164 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
| 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); | |
| 166 // Class of "X" registers | |
| 167 reg_class x_reg(EBX, ECX, EDX, EAX); | |
| 168 // Class of registers that can appear in an address with no offset. | |
| 169 // EBP and ESP require an extra instruction byte for zero offset. | |
| 170 // Used in fast-unlock | |
| 171 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 172 // Class for general registers not including ECX | |
| 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 174 // Class for general registers not including EAX | |
| 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 176 // Class for general registers not including EAX or EBX. | |
| 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 178 // Class of EAX (for multiply and divide operations) | |
| 179 reg_class eax_reg(EAX); | |
| 180 // Class of EBX (for atomic add) | |
| 181 reg_class ebx_reg(EBX); | |
| 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 183 reg_class ecx_reg(ECX); | |
| 184 // Class of EDX (for multiply and divide operations) | |
| 185 reg_class edx_reg(EDX); | |
| 186 // Class of EDI (for synchronization) | |
| 187 reg_class edi_reg(EDI); | |
| 188 // Class of ESI (for synchronization) | |
| 189 reg_class esi_reg(ESI); | |
| 190 // Singleton class for interpreter's stack pointer | |
| 191 reg_class ebp_reg(EBP); | |
| 192 // Singleton class for stack pointer | |
| 193 reg_class sp_reg(ESP); | |
| 194 // Singleton class for instruction pointer | |
| 195 // reg_class ip_reg(EIP); | |
| 196 // Singleton class for condition codes | |
| 197 reg_class int_flags(EFLAGS); | |
| 198 // Class of integer register pairs | |
| 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 200 // Class of integer register pairs that aligns with calling convention | |
| 201 reg_class eadx_reg( EAX,EDX ); | |
| 202 reg_class ebcx_reg( ECX,EBX ); | |
| 203 // Not AX or DX, used in divides | |
| 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 205 | |
| 206 // Floating point registers. Notice FPR0 is not a choice. | |
| 207 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 208 // a 2-address instructions out of Intels FP stack. | |
| 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); | |
| 210 | |
| 211 // make a register class for SSE registers | |
| 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); | |
| 213 | |
| 214 // make a double register class for SSE2 registers | |
| 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, | |
| 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); | |
| 217 | |
| 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, | |
| 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, | |
| 220 FPR7L,FPR7H ); | |
| 221 | |
| 222 reg_class flt_reg0( FPR1L ); | |
| 223 reg_class dbl_reg0( FPR1L,FPR1H ); | |
| 224 reg_class dbl_reg1( FPR2L,FPR2H ); | |
| 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, | |
| 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); | |
| 227 | |
| 228 // XMM6 and XMM7 could be used as temporary registers for long, float and | |
| 229 // double values for SSE2. | |
| 230 reg_class xdb_reg6( XMM6a,XMM6b ); | |
| 231 reg_class xdb_reg7( XMM7a,XMM7b ); | |
| 232 %} | |
| 233 | |
| 234 | |
| 235 //----------SOURCE BLOCK------------------------------------------------------- | |
| 236 // This is a block of C++ code which provides values, functions, and | |
| 237 // definitions necessary in the rest of the architecture description | |
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238 source_hpp %{ |
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239 // Must be visible to the DFA in dfa_x86_32.cpp |
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240 extern bool is_operand_hi32_zero(Node* n); |
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241 %} |
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242 |
| 0 | 243 source %{ |
| 304 | 244 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 245 #define RELOC_DISP32 Assembler::disp32_operand |
| 246 | |
| 247 #define __ _masm. | |
| 248 | |
| 249 // How to find the high register of a Long pair, given the low register | |
| 250 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 251 | |
| 252 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 253 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 254 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 255 | |
| 256 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 259 // of 128-bits operands for SSE instructions. | |
| 260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 261 // Store the value to a 128-bits operand. | |
| 262 operand[0] = lo; | |
| 263 operand[1] = hi; | |
| 264 return operand; | |
| 265 } | |
| 266 | |
| 267 // Buffer for 128-bits masks used by SSE instructions. | |
| 268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 269 | |
| 270 // Static initialization during VM startup. | |
| 271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 275 | |
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276 // Offset hacking within calls. |
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277 static int pre_call_FPU_size() { |
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278 if (Compile::current()->in_24_bit_fp_mode()) |
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279 return 6; // fldcw |
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280 return 0; |
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281 } |
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282 |
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283 static int preserve_SP_size() { |
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284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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292 if (_method_handle_invoke) |
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293 offset += preserve_SP_size(); |
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294 return offset; |
| 0 | 295 } |
| 296 | |
| 297 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 299 } |
| 300 | |
| 301 static int sizeof_FFree_Float_Stack_All = -1; | |
| 302 | |
| 303 int MachCallRuntimeNode::ret_addr_offset() { | |
| 304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 306 } |
| 307 | |
| 308 // Indicate if the safepoint node needs the polling page as an input. | |
| 309 // Since x86 does have absolute addressing, it doesn't. | |
| 310 bool SafePointNode::needs_polling_address_input() { | |
| 311 return false; | |
| 312 } | |
| 313 | |
| 314 // | |
| 315 // Compute padding required for nodes which need alignment | |
| 316 // | |
| 317 | |
| 318 // The address of the call instruction needs to be 4-byte aligned to | |
| 319 // ensure that it does not span a cache line so that it can be patched. | |
| 320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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321 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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322 current_offset += 1; // skip call opcode byte |
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323 return round_to(current_offset, alignment_required()) - current_offset; |
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324 } |
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325 |
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326 // The address of the call instruction needs to be 4-byte aligned to |
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327 // ensure that it does not span a cache line so that it can be patched. |
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328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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329 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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330 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 331 current_offset += 1; // skip call opcode byte |
| 332 return round_to(current_offset, alignment_required()) - current_offset; | |
| 333 } | |
| 334 | |
| 335 // The address of the call instruction needs to be 4-byte aligned to | |
| 336 // ensure that it does not span a cache line so that it can be patched. | |
| 337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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338 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 339 current_offset += 5; // skip MOV instruction |
| 340 current_offset += 1; // skip call opcode byte | |
| 341 return round_to(current_offset, alignment_required()) - current_offset; | |
| 342 } | |
| 343 | |
| 344 #ifndef PRODUCT | |
| 345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 346 st->print("INT3"); | |
| 347 } | |
| 348 #endif | |
| 349 | |
| 350 // EMIT_RM() | |
| 351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 353 cbuf.insts()->emit_int8(c); |
| 0 | 354 } |
| 355 | |
| 356 // EMIT_CC() | |
| 357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 358 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 359 cbuf.insts()->emit_int8(c); |
| 0 | 360 } |
| 361 | |
| 362 // EMIT_OPCODE() | |
| 363 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 364 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 365 } |
| 366 | |
| 367 // EMIT_OPCODE() w/ relocation information | |
| 368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 369 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 370 emit_opcode(cbuf, code); |
| 371 } | |
| 372 | |
| 373 // EMIT_D8() | |
| 374 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 375 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 376 } |
| 377 | |
| 378 // EMIT_D16() | |
| 379 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 380 cbuf.insts()->emit_int16(d16); |
| 0 | 381 } |
| 382 | |
| 383 // EMIT_D32() | |
| 384 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 385 cbuf.insts()->emit_int32(d32); |
| 0 | 386 } |
| 387 | |
| 388 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 390 int format) { | |
| 1748 | 391 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 392 cbuf.insts()->emit_int32(d32); | |
| 0 | 393 } |
| 394 | |
| 395 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 397 int format) { | |
| 398 #ifdef ASSERT | |
| 399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 401 } |
| 402 #endif | |
| 1748 | 403 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 404 cbuf.insts()->emit_int32(d32); | |
| 0 | 405 } |
| 406 | |
| 407 // Access stack slot for load or store | |
| 408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 410 if( -128 <= disp && disp <= 127 ) { | |
| 411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 413 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 414 } else { | |
| 415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 417 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 418 } | |
| 419 } | |
| 420 | |
| 421 // eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { | |
| 423 // There is no index & no scale, use form without SIB byte | |
| 424 if ((index == 0x4) && | |
| 425 (scale == 0) && (base != ESP_enc)) { | |
| 426 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 427 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 428 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 429 } | |
| 430 else { // If 8-bit displacement, mode 0x1 | |
| 431 if ((displace >= -128) && (displace <= 127) | |
| 432 && !(displace_is_oop) ) { | |
| 433 emit_rm(cbuf, 0x1, reg_encoding, base); | |
| 434 emit_d8(cbuf, displace); | |
| 435 } | |
| 436 else { // If 32-bit displacement | |
| 437 if (base == -1) { // Special flag for absolute address | |
| 438 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 439 // (manual lies; no SIB needed here) | |
| 440 if ( displace_is_oop ) { | |
| 441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 442 } else { | |
| 443 emit_d32 (cbuf, displace); | |
| 444 } | |
| 445 } | |
| 446 else { // Normal base + offset | |
| 447 emit_rm(cbuf, 0x2, reg_encoding, base); | |
| 448 if ( displace_is_oop ) { | |
| 449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 450 } else { | |
| 451 emit_d32 (cbuf, displace); | |
| 452 } | |
| 453 } | |
| 454 } | |
| 455 } | |
| 456 } | |
| 457 else { // Else, encode with the SIB byte | |
| 458 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 459 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 460 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 461 emit_rm(cbuf, scale, index, base); | |
| 462 } | |
| 463 else { // If 8-bit displacement, mode 0x1 | |
| 464 if ((displace >= -128) && (displace <= 127) | |
| 465 && !(displace_is_oop) ) { | |
| 466 emit_rm(cbuf, 0x1, reg_encoding, 0x4); | |
| 467 emit_rm(cbuf, scale, index, base); | |
| 468 emit_d8(cbuf, displace); | |
| 469 } | |
| 470 else { // If 32-bit displacement | |
| 471 if (base == 0x04 ) { | |
| 472 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 473 emit_rm(cbuf, scale, index, 0x04); | |
| 474 } else { | |
| 475 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 476 emit_rm(cbuf, scale, index, base); | |
| 477 } | |
| 478 if ( displace_is_oop ) { | |
| 479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 480 } else { | |
| 481 emit_d32 (cbuf, displace); | |
| 482 } | |
| 483 } | |
| 484 } | |
| 485 } | |
| 486 } | |
| 487 | |
| 488 | |
| 489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 490 if( dst_encoding == src_encoding ) { | |
| 491 // reg-reg copy, use an empty encoding | |
| 492 } else { | |
| 493 emit_opcode( cbuf, 0x8B ); | |
| 494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 495 } | |
| 496 } | |
| 497 | |
| 498 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 499 if( dst_encoding == src_encoding ) { | |
| 500 // reg-reg copy, use an empty encoding | |
| 501 } else { | |
| 502 MacroAssembler _masm(&cbuf); | |
| 503 | |
| 504 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 505 } | |
| 506 } | |
| 507 | |
| 508 | |
| 509 //============================================================================= | |
| 2008 | 510 const bool Matcher::constant_table_absolute_addressing = true; |
| 511 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; | |
| 512 | |
| 513 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 514 // Empty encoding | |
| 515 } | |
| 516 | |
| 517 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 518 return 0; | |
| 519 } | |
| 520 | |
| 521 #ifndef PRODUCT | |
| 522 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 523 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 524 } | |
| 525 #endif | |
| 526 | |
| 527 | |
| 528 //============================================================================= | |
| 0 | 529 #ifndef PRODUCT |
| 530 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 531 Compile* C = ra_->C; | |
| 532 if( C->in_24_bit_fp_mode() ) { | |
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533 st->print("FLDCW 24 bit fpu control word"); |
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534 st->print_cr(""); st->print("\t"); |
| 0 | 535 } |
| 536 | |
| 537 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 538 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 539 // Remove two words for return addr and rbp, | |
| 540 framesize -= 2*wordSize; | |
| 541 | |
| 542 // Calls to C2R adapters often do not accept exceptional returns. | |
| 543 // We require that their callers must bang for them. But be careful, because | |
| 544 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 545 // stack. But the stack safety zone should account for that. | |
| 546 // See bugs 4446381, 4468289, 4497237. | |
| 547 if (C->need_stack_bang(framesize)) { | |
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548 st->print_cr("# stack bang"); st->print("\t"); |
| 0 | 549 } |
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550 st->print_cr("PUSHL EBP"); st->print("\t"); |
| 0 | 551 |
| 552 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
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553 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); |
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554 st->print_cr(""); st->print("\t"); |
| 0 | 555 framesize -= wordSize; |
| 556 } | |
| 557 | |
| 558 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 559 if (framesize) { | |
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560 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 561 } |
| 562 } else { | |
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563 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 564 } |
| 565 } | |
| 566 #endif | |
| 567 | |
| 568 | |
| 569 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 570 Compile* C = ra_->C; | |
| 571 | |
| 572 if (UseSSE >= 2 && VerifyFPU) { | |
| 573 MacroAssembler masm(&cbuf); | |
| 574 masm.verify_FPU(0, "FPU stack must be clean on entry"); | |
| 575 } | |
| 576 | |
| 577 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 578 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 579 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 580 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 581 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 582 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 583 // If method sets FPU control word do it now | |
| 584 if( C->in_24_bit_fp_mode() ) { | |
| 585 MacroAssembler masm(&cbuf); | |
| 586 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 587 } | |
| 588 | |
| 589 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 590 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 591 // Remove two words for return addr and rbp, | |
| 592 framesize -= 2*wordSize; | |
| 593 | |
| 594 // Calls to C2R adapters often do not accept exceptional returns. | |
| 595 // We require that their callers must bang for them. But be careful, because | |
| 596 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 597 // stack. But the stack safety zone should account for that. | |
| 598 // See bugs 4446381, 4468289, 4497237. | |
| 599 if (C->need_stack_bang(framesize)) { | |
| 600 MacroAssembler masm(&cbuf); | |
| 601 masm.generate_stack_overflow_check(framesize); | |
| 602 } | |
| 603 | |
| 604 // We always push rbp, so that on return to interpreter rbp, will be | |
| 605 // restored correctly and we can correct the stack. | |
| 606 emit_opcode(cbuf, 0x50 | EBP_enc); | |
| 607 | |
| 608 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
| 609 emit_opcode(cbuf, 0x68); // push 0xbadb100d | |
| 610 emit_d32(cbuf, 0xbadb100d); | |
| 611 framesize -= wordSize; | |
| 612 } | |
| 613 | |
| 614 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 615 if (framesize) { | |
| 616 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 617 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 618 emit_d8(cbuf, framesize); | |
| 619 } | |
| 620 } else { | |
| 621 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 622 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 623 emit_d32(cbuf, framesize); | |
| 624 } | |
| 1748 | 625 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 626 |
| 627 #ifdef ASSERT | |
| 628 if (VerifyStackAtCalls) { | |
| 629 Label L; | |
| 630 MacroAssembler masm(&cbuf); | |
| 304 | 631 masm.push(rax); |
| 632 masm.mov(rax, rsp); | |
| 633 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 634 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 635 masm.pop(rax); | |
| 0 | 636 masm.jcc(Assembler::equal, L); |
| 637 masm.stop("Stack is not properly aligned!"); | |
| 638 masm.bind(L); | |
| 639 } | |
| 640 #endif | |
| 641 | |
| 642 } | |
| 643 | |
| 644 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 645 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 646 } | |
| 647 | |
| 648 int MachPrologNode::reloc() const { | |
| 649 return 0; // a large enough number | |
| 650 } | |
| 651 | |
| 652 //============================================================================= | |
| 653 #ifndef PRODUCT | |
| 654 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 655 Compile *C = ra_->C; | |
| 656 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 657 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 658 // Remove two words for return addr and rbp, | |
| 659 framesize -= 2*wordSize; | |
| 660 | |
| 661 if( C->in_24_bit_fp_mode() ) { | |
| 662 st->print("FLDCW standard control word"); | |
| 663 st->cr(); st->print("\t"); | |
| 664 } | |
| 665 if( framesize ) { | |
| 666 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 667 st->cr(); st->print("\t"); | |
| 668 } | |
| 669 st->print_cr("POPL EBP"); st->print("\t"); | |
| 670 if( do_polling() && C->is_method_compilation() ) { | |
| 671 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 672 st->cr(); st->print("\t"); | |
| 673 } | |
| 674 } | |
| 675 #endif | |
| 676 | |
| 677 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 678 Compile *C = ra_->C; | |
| 679 | |
| 680 // If method set FPU control word, restore to standard control word | |
| 681 if( C->in_24_bit_fp_mode() ) { | |
| 682 MacroAssembler masm(&cbuf); | |
| 683 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 684 } | |
| 685 | |
| 686 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 687 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 688 // Remove two words for return addr and rbp, | |
| 689 framesize -= 2*wordSize; | |
| 690 | |
| 691 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 692 | |
| 693 if( framesize >= 128 ) { | |
| 694 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 695 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 696 emit_d32(cbuf, framesize); | |
| 697 } | |
| 698 else if( framesize ) { | |
| 699 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 700 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 701 emit_d8(cbuf, framesize); | |
| 702 } | |
| 703 | |
| 704 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 705 | |
| 706 if( do_polling() && C->is_method_compilation() ) { | |
| 1748 | 707 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 708 emit_opcode(cbuf,0x85); |
| 709 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 710 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 711 } | |
| 712 } | |
| 713 | |
| 714 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 715 Compile *C = ra_->C; | |
| 716 // If method set FPU control word, restore to standard control word | |
| 717 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 718 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 719 | |
| 720 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 721 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 722 // Remove two words for return addr and rbp, | |
| 723 framesize -= 2*wordSize; | |
| 724 | |
| 725 size++; // popl rbp, | |
| 726 | |
| 727 if( framesize >= 128 ) { | |
| 728 size += 6; | |
| 729 } else { | |
| 730 size += framesize ? 3 : 0; | |
| 731 } | |
| 732 return size; | |
| 733 } | |
| 734 | |
| 735 int MachEpilogNode::reloc() const { | |
| 736 return 0; // a large enough number | |
| 737 } | |
| 738 | |
| 739 const Pipeline * MachEpilogNode::pipeline() const { | |
| 740 return MachNode::pipeline_class(); | |
| 741 } | |
| 742 | |
| 743 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 744 | |
| 745 //============================================================================= | |
| 746 | |
| 747 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 748 static enum RC rc_class( OptoReg::Name reg ) { | |
| 749 | |
| 750 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 751 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 752 | |
| 753 VMReg r = OptoReg::as_VMReg(reg); | |
| 754 if (r->is_Register()) return rc_int; | |
| 755 if (r->is_FloatRegister()) { | |
| 756 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 757 return rc_float; | |
| 758 } | |
| 759 assert(r->is_XMMRegister(), "must be"); | |
| 760 return rc_xmm; | |
| 761 } | |
| 762 | |
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763 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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764 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 765 if( cbuf ) { |
| 766 emit_opcode (*cbuf, opcode ); | |
| 767 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); | |
| 768 #ifndef PRODUCT | |
| 769 } else if( !do_size ) { | |
|
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770 if( size != 0 ) st->print("\n\t"); |
| 0 | 771 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
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772 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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773 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 774 } else { // FLD, FST, PUSH, POP |
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775 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 776 } |
| 777 #endif | |
| 778 } | |
| 779 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 780 return size+3+offset_size; | |
| 781 } | |
| 782 | |
| 783 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 784 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
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785 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 0 | 786 if( cbuf ) { |
| 787 if( reg_lo+1 == reg_hi ) { // double move? | |
| 788 if( is_load && !UseXmmLoadAndClearUpper ) | |
| 789 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load | |
| 790 else | |
| 791 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise | |
| 792 } else { | |
| 793 emit_opcode(*cbuf, 0xF3 ); | |
| 794 } | |
| 795 emit_opcode(*cbuf, 0x0F ); | |
| 796 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) | |
| 797 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load | |
| 798 else | |
| 799 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); | |
| 800 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); | |
| 801 #ifndef PRODUCT | |
| 802 } else if( !do_size ) { | |
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803 if( size != 0 ) st->print("\n\t"); |
| 0 | 804 if( reg_lo+1 == reg_hi ) { // double move? |
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805 if( is_load ) st->print("%s %s,[ESP + #%d]", |
| 0 | 806 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", |
| 807 Matcher::regName[reg_lo], offset); | |
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808 else st->print("MOVSD [ESP + #%d],%s", |
| 0 | 809 offset, Matcher::regName[reg_lo]); |
| 810 } else { | |
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811 if( is_load ) st->print("MOVSS %s,[ESP + #%d]", |
| 0 | 812 Matcher::regName[reg_lo], offset); |
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813 else st->print("MOVSS [ESP + #%d],%s", |
| 0 | 814 offset, Matcher::regName[reg_lo]); |
| 815 } | |
| 816 #endif | |
| 817 } | |
| 818 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 819 return size+5+offset_size; | |
| 820 } | |
| 821 | |
| 822 | |
| 823 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
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824 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 0 | 825 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers |
| 826 if( cbuf ) { | |
| 827 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { | |
| 828 emit_opcode(*cbuf, 0x66 ); | |
| 829 } | |
| 830 emit_opcode(*cbuf, 0x0F ); | |
| 831 emit_opcode(*cbuf, 0x28 ); | |
| 832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 833 #ifndef PRODUCT | |
| 834 } else if( !do_size ) { | |
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835 if( size != 0 ) st->print("\n\t"); |
| 0 | 836 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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837 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 838 } else { |
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839 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 840 } |
| 841 #endif | |
| 842 } | |
| 843 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); | |
| 844 } else { | |
| 845 if( cbuf ) { | |
| 846 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); | |
| 847 emit_opcode(*cbuf, 0x0F ); | |
| 848 emit_opcode(*cbuf, 0x10 ); | |
| 849 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 850 #ifndef PRODUCT | |
| 851 } else if( !do_size ) { | |
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852 if( size != 0 ) st->print("\n\t"); |
| 0 | 853 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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854 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 855 } else { |
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856 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 857 } |
| 858 #endif | |
| 859 } | |
| 860 return size+4; | |
| 861 } | |
| 862 } | |
| 863 | |
|
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864 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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865 int src_hi, int dst_hi, int size, outputStream* st ) { |
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866 // 32-bit |
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867 if (cbuf) { |
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868 emit_opcode(*cbuf, 0x66); |
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869 emit_opcode(*cbuf, 0x0F); |
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870 emit_opcode(*cbuf, 0x6E); |
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871 emit_rm(*cbuf, 0x3, Matcher::_regEncode[dst_lo] & 7, Matcher::_regEncode[src_lo] & 7); |
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872 #ifndef PRODUCT |
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873 } else if (!do_size) { |
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874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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875 #endif |
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876 } |
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877 return 4; |
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878 } |
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879 |
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880 |
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881 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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882 int src_hi, int dst_hi, int size, outputStream* st ) { |
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883 // 32-bit |
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884 if (cbuf) { |
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885 emit_opcode(*cbuf, 0x66); |
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886 emit_opcode(*cbuf, 0x0F); |
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887 emit_opcode(*cbuf, 0x7E); |
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888 emit_rm(*cbuf, 0x3, Matcher::_regEncode[src_lo] & 7, Matcher::_regEncode[dst_lo] & 7); |
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889 #ifndef PRODUCT |
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890 } else if (!do_size) { |
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891 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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892 #endif |
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893 } |
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894 return 4; |
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895 } |
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896 |
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897 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 898 if( cbuf ) { |
| 899 emit_opcode(*cbuf, 0x8B ); | |
| 900 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 901 #ifndef PRODUCT | |
| 902 } else if( !do_size ) { | |
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903 if( size != 0 ) st->print("\n\t"); |
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904 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 905 #endif |
| 906 } | |
| 907 return size+2; | |
| 908 } | |
| 909 | |
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910 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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911 int offset, int size, outputStream* st ) { |
| 0 | 912 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 913 if( cbuf ) { | |
| 914 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 915 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 916 #ifndef PRODUCT | |
| 917 } else if( !do_size ) { | |
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918 if( size != 0 ) st->print("\n\t"); |
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919 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 920 #endif |
| 921 } | |
| 922 size += 2; | |
| 923 } | |
| 924 | |
| 925 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 926 const char *op_str; | |
| 927 int op; | |
| 928 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 929 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 930 op = 0xDD; | |
| 931 } else { // 32-bit store | |
| 932 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 933 op = 0xD9; | |
| 934 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 935 } | |
| 936 | |
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937 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 938 } |
| 939 | |
| 940 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { | |
| 941 // Get registers to move | |
| 942 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 943 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 944 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 945 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 946 | |
| 947 enum RC src_second_rc = rc_class(src_second); | |
| 948 enum RC src_first_rc = rc_class(src_first); | |
| 949 enum RC dst_second_rc = rc_class(dst_second); | |
| 950 enum RC dst_first_rc = rc_class(dst_first); | |
| 951 | |
| 952 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 953 | |
| 954 // Generate spill code! | |
| 955 int size = 0; | |
| 956 | |
| 957 if( src_first == dst_first && src_second == dst_second ) | |
| 958 return size; // Self copy, no move | |
| 959 | |
| 960 // -------------------------------------- | |
| 961 // Check for mem-mem move. push/pop to move. | |
| 962 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 963 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 964 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
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965 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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966 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 967 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 968 } | |
| 969 // move low bits | |
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970 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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971 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 972 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
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973 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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974 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 975 } |
| 976 return size; | |
| 977 } | |
| 978 | |
| 979 // -------------------------------------- | |
| 980 // Check for integer reg-reg copy | |
| 981 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
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982 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 983 |
| 984 // Check for integer store | |
| 985 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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986 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 987 |
| 988 // Check for integer load | |
| 989 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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990 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 991 |
|
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992 // Check for integer reg-xmm reg copy |
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993 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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994 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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995 "no 64 bit integer-float reg moves" ); |
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996 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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997 } |
| 0 | 998 // -------------------------------------- |
| 999 // Check for float reg-reg copy | |
| 1000 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1001 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1002 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1003 if( cbuf ) { | |
| 1004 | |
| 1005 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1006 // indexing issue mentioned in a comment in the reg_def sections | |
| 1007 // for FPR registers many lines above here. | |
| 1008 | |
| 1009 if( src_first != FPR1L_num ) { | |
| 1010 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1011 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1012 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1013 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1014 } else { | |
| 1015 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1016 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1017 } | |
| 1018 #ifndef PRODUCT | |
| 1019 } else if( !do_size ) { | |
| 1020 if( size != 0 ) st->print("\n\t"); | |
| 1021 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1022 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1023 #endif | |
| 1024 } | |
| 1025 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1026 } | |
| 1027 | |
| 1028 // Check for float store | |
| 1029 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
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1030 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1031 } |
| 1032 | |
| 1033 // Check for float load | |
| 1034 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1035 int offset = ra_->reg2offset(src_first); | |
| 1036 const char *op_str; | |
| 1037 int op; | |
| 1038 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1039 op_str = "FLD_D"; | |
| 1040 op = 0xDD; | |
| 1041 } else { // 32-bit load | |
| 1042 op_str = "FLD_S"; | |
| 1043 op = 0xD9; | |
| 1044 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1045 } | |
| 1046 if( cbuf ) { | |
| 1047 emit_opcode (*cbuf, op ); | |
| 1048 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); | |
| 1049 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1050 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1051 #ifndef PRODUCT | |
| 1052 } else if( !do_size ) { | |
| 1053 if( size != 0 ) st->print("\n\t"); | |
| 1054 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1055 #endif | |
| 1056 } | |
| 1057 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1058 return size + 3+offset_size+2; | |
| 1059 } | |
| 1060 | |
| 1061 // Check for xmm reg-reg copy | |
| 1062 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1063 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1064 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1065 "no non-adjacent float-moves" ); | |
|
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1066 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1067 } |
| 1068 | |
|
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1069 // Check for xmm reg-integer reg copy |
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1070 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1071 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1072 "no 64 bit float-integer reg moves" ); |
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1073 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1074 } |
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1075 |
| 0 | 1076 // Check for xmm store |
| 1077 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
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1078 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1079 } |
| 1080 | |
| 1081 // Check for float xmm load | |
| 1082 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
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1083 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1084 } |
| 1085 | |
| 1086 // Copy from float reg to xmm reg | |
| 1087 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1088 // copy to the top of stack from floating point reg | |
| 1089 // and use LEA to preserve flags | |
| 1090 if( cbuf ) { | |
| 1091 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1092 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1093 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1094 emit_d8(*cbuf,0xF8); | |
| 1095 #ifndef PRODUCT | |
| 1096 } else if( !do_size ) { | |
| 1097 if( size != 0 ) st->print("\n\t"); | |
| 1098 st->print("LEA ESP,[ESP-8]"); | |
| 1099 #endif | |
| 1100 } | |
| 1101 size += 4; | |
| 1102 | |
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1103 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1104 |
| 1105 // Copy from the temp memory to the xmm reg. | |
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1106 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1107 |
| 1108 if( cbuf ) { | |
| 1109 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1110 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1111 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1112 emit_d8(*cbuf,0x08); | |
| 1113 #ifndef PRODUCT | |
| 1114 } else if( !do_size ) { | |
| 1115 if( size != 0 ) st->print("\n\t"); | |
| 1116 st->print("LEA ESP,[ESP+8]"); | |
| 1117 #endif | |
| 1118 } | |
| 1119 size += 4; | |
| 1120 return size; | |
| 1121 } | |
| 1122 | |
| 1123 assert( size > 0, "missed a case" ); | |
| 1124 | |
| 1125 // -------------------------------------------------------------------- | |
| 1126 // Check for second bits still needing moving. | |
| 1127 if( src_second == dst_second ) | |
| 1128 return size; // Self copy; no move | |
| 1129 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1130 | |
| 1131 // Check for second word int-int move | |
| 1132 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1133 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1134 |
| 1135 // Check for second word integer store | |
| 1136 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1137 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1138 |
| 1139 // Check for second word integer load | |
| 1140 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1141 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1142 |
| 1143 | |
| 1144 Unimplemented(); | |
| 1145 } | |
| 1146 | |
| 1147 #ifndef PRODUCT | |
| 1148 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1149 implementation( NULL, ra_, false, st ); | |
| 1150 } | |
| 1151 #endif | |
| 1152 | |
| 1153 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1154 implementation( &cbuf, ra_, false, NULL ); | |
| 1155 } | |
| 1156 | |
| 1157 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1158 return implementation( NULL, ra_, true, NULL ); | |
| 1159 } | |
| 1160 | |
| 1161 //============================================================================= | |
| 1162 #ifndef PRODUCT | |
| 1163 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 1164 st->print("NOP \t# %d bytes pad for loops and calls", _count); | |
| 1165 } | |
| 1166 #endif | |
| 1167 | |
| 1168 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1169 MacroAssembler _masm(&cbuf); | |
| 1170 __ nop(_count); | |
| 1171 } | |
| 1172 | |
| 1173 uint MachNopNode::size(PhaseRegAlloc *) const { | |
| 1174 return _count; | |
| 1175 } | |
| 1176 | |
| 1177 | |
| 1178 //============================================================================= | |
| 1179 #ifndef PRODUCT | |
| 1180 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1181 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1182 int reg = ra_->get_reg_first(this); | |
| 1183 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1184 } | |
| 1185 #endif | |
| 1186 | |
| 1187 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1188 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1189 int reg = ra_->get_encode(this); | |
| 1190 if( offset >= 128 ) { | |
| 1191 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1192 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1193 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1194 emit_d32(cbuf, offset); | |
| 1195 } | |
| 1196 else { | |
| 1197 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1198 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1199 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1200 emit_d8(cbuf, offset); | |
| 1201 } | |
| 1202 } | |
| 1203 | |
| 1204 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1206 if( offset >= 128 ) { | |
| 1207 return 7; | |
| 1208 } | |
| 1209 else { | |
| 1210 return 4; | |
| 1211 } | |
| 1212 } | |
| 1213 | |
| 1214 //============================================================================= | |
| 1215 | |
| 1216 // emit call stub, compiled java to interpreter | |
| 1217 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1218 // Stub is fixed up when the corresponding call is converted from calling | |
| 1219 // compiled code to calling interpreted code. | |
| 1220 // mov rbx,0 | |
| 1221 // jmp -1 | |
| 1222 | |
| 1748 | 1223 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1224 | |
| 1225 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1226 // That's why we must use the macroassembler to generate a stub. |
| 1227 MacroAssembler _masm(&cbuf); | |
| 1228 | |
| 1229 address base = | |
| 1230 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1231 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1232 // static stub relocation stores the instruction address of the call | |
| 1233 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
| 1234 // static stub relocation also tags the methodOop in the code-stream. | |
| 1235 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time | |
| 304 | 1236 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1237 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1238 |
| 1239 __ end_a_stub(); | |
| 1748 | 1240 // Update current stubs pointer and restore insts_end. |
| 0 | 1241 } |
| 1242 // size of call stub, compiled java to interpretor | |
| 1243 uint size_java_to_interp() { | |
| 1244 return 10; // movl; jmp | |
| 1245 } | |
| 1246 // relocation entries for call stub, compiled java to interpretor | |
| 1247 uint reloc_java_to_interp() { | |
| 1248 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1249 } | |
| 1250 | |
| 1251 //============================================================================= | |
| 1252 #ifndef PRODUCT | |
| 1253 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1254 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1255 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1256 st->print_cr("\tNOP"); | |
| 1257 st->print_cr("\tNOP"); | |
| 1258 if( !OptoBreakpoint ) | |
| 1259 st->print_cr("\tNOP"); | |
| 1260 } | |
| 1261 #endif | |
| 1262 | |
| 1263 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1264 MacroAssembler masm(&cbuf); | |
| 1265 #ifdef ASSERT | |
| 1748 | 1266 uint insts_size = cbuf.insts_size(); |
| 0 | 1267 #endif |
| 304 | 1268 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1269 masm.jump_cc(Assembler::notEqual, |
| 1270 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1271 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1272 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1273 int nops_cnt = 2; | |
| 1274 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1275 nops_cnt += 1; | |
| 1276 masm.nop(nops_cnt); | |
| 1277 | |
| 1748 | 1278 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1279 } |
| 1280 | |
| 1281 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1282 return OptoBreakpoint ? 11 : 12; | |
| 1283 } | |
| 1284 | |
| 1285 | |
| 1286 //============================================================================= | |
| 1287 uint size_exception_handler() { | |
| 1288 // NativeCall instruction size is the same as NativeJump. | |
| 1289 // exception handler starts out as jump and can be patched to | |
| 1290 // a call be deoptimization. (4932387) | |
| 1291 // Note that this value is also credited (in output.cpp) to | |
| 1292 // the size of the code section. | |
| 1293 return NativeJump::instruction_size; | |
| 1294 } | |
| 1295 | |
| 1296 // Emit exception handler code. Stuff framesize into a register | |
| 1297 // and call a VM stub routine. | |
| 1298 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1299 | |
| 1748 | 1300 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1301 // That's why we must use the macroassembler to generate a handler. |
| 1302 MacroAssembler _masm(&cbuf); | |
| 1303 address base = | |
| 1304 __ start_a_stub(size_exception_handler()); | |
| 1305 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1306 int offset = __ offset(); | |
| 1748 | 1307 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1308 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1309 __ end_a_stub(); | |
| 1310 return offset; | |
| 1311 } | |
| 1312 | |
| 1313 uint size_deopt_handler() { | |
| 1314 // NativeCall instruction size is the same as NativeJump. | |
| 1315 // exception handler starts out as jump and can be patched to | |
| 1316 // a call be deoptimization. (4932387) | |
| 1317 // Note that this value is also credited (in output.cpp) to | |
| 1318 // the size of the code section. | |
| 1319 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1320 } | |
| 1321 | |
| 1322 // Emit deopt handler code. | |
| 1323 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1324 | |
| 1748 | 1325 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1326 // That's why we must use the macroassembler to generate a handler. |
| 1327 MacroAssembler _masm(&cbuf); | |
| 1328 address base = | |
| 1329 __ start_a_stub(size_exception_handler()); | |
| 1330 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1331 int offset = __ offset(); | |
| 1332 InternalAddress here(__ pc()); | |
| 1333 __ pushptr(here.addr()); | |
| 1334 | |
| 1335 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1336 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1337 __ end_a_stub(); | |
| 1338 return offset; | |
| 1339 } | |
| 1340 | |
| 1341 | |
|
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1342 const bool Matcher::match_rule_supported(int opcode) { |
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1343 if (!has_match_rule(opcode)) |
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1344 return false; |
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1345 |
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1346 return true; // Per default match rules are supported. |
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1347 } |
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1348 |
| 0 | 1349 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1350 return regnum - 32; // The FP registers are in the second chunk | |
| 1351 } | |
| 1352 | |
| 1353 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1354 const bool Matcher::convL2FSupported(void) { | |
| 1355 return true; | |
| 1356 } | |
| 1357 | |
| 1358 // Vector width in bytes | |
| 1359 const uint Matcher::vector_width_in_bytes(void) { | |
| 1360 return UseSSE >= 2 ? 8 : 0; | |
| 1361 } | |
| 1362 | |
| 1363 // Vector ideal reg | |
| 1364 const uint Matcher::vector_ideal_reg(void) { | |
| 1365 return Op_RegD; | |
| 1366 } | |
| 1367 | |
| 1368 // Is this branch offset short enough that a short branch can be used? | |
| 1369 // | |
| 1370 // NOTE: If the platform does not provide any short branch variants, then | |
| 1371 // this method should return false for offset 0. | |
|
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1372 bool Matcher::is_short_branch_offset(int rule, int offset) { |
|
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|
1373 // the short version of jmpConUCF2 contains multiple branches, |
|
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|
1374 // making the reach slightly less |
|
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|
1375 if (rule == jmpConUCF2_rule) |
|
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|
1376 return (-126 <= offset && offset <= 125); |
| 0 | 1377 return (-128 <= offset && offset <= 127); |
| 1378 } | |
| 1379 | |
| 1380 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1382 return false; | |
| 1383 } | |
| 1384 | |
| 1385 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1386 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1387 | |
| 1388 // Threshold size for cleararray. | |
| 1389 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1390 | |
| 1391 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1392 // be subsumed into complex addressing expressions or compute them into | |
| 1393 // registers? True for Intel but false for most RISCs | |
| 1394 const bool Matcher::clone_shift_expressions = true; | |
| 1395 | |
|
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|
1396 // Do we need to mask the count passed to shift instructions or does |
|
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|
1397 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1398 const bool Matcher::need_masked_shift_count = false; |
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|
1399 |
|
1575
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|
1400 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1401 ShouldNotCallThis(); |
|
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|
1402 return true; |
|
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|
1403 } |
|
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|
1404 |
|
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|
1405 |
| 0 | 1406 // Is it better to copy float constants, or load them directly from memory? |
| 1407 // Intel can load a float constant from a direct address, requiring no | |
| 1408 // extra registers. Most RISCs will have to materialize an address into a | |
| 1409 // register first, so they would do better to copy the constant from stack. | |
| 1410 const bool Matcher::rematerialize_float_constants = true; | |
| 1411 | |
| 1412 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1413 // needed. Else we split the double into 2 integer pieces and move it | |
| 1414 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1415 // Java calling convention forces doubles to be aligned. | |
| 1416 const bool Matcher::misaligned_doubles_ok = true; | |
| 1417 | |
| 1418 | |
| 1419 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1420 // Get the memory operand from the node | |
| 1421 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1422 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1423 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1424 uint opcnt = 1; // First operand | |
| 1425 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1426 while( idx >= skipped+num_edges ) { | |
| 1427 skipped += num_edges; | |
| 1428 opcnt++; // Bump operand count | |
| 1429 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1430 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1431 } | |
| 1432 | |
| 1433 MachOper *memory = node->_opnds[opcnt]; | |
| 1434 MachOper *new_memory = NULL; | |
| 1435 switch (memory->opcode()) { | |
| 1436 case DIRECT: | |
| 1437 case INDOFFSET32X: | |
| 1438 // No transformation necessary. | |
| 1439 return; | |
| 1440 case INDIRECT: | |
| 1441 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1442 break; | |
| 1443 case INDOFFSET8: | |
| 1444 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1445 break; | |
| 1446 case INDOFFSET32: | |
| 1447 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1448 break; | |
| 1449 case INDINDEXOFFSET: | |
| 1450 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1451 break; | |
| 1452 case INDINDEXSCALE: | |
| 1453 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1454 break; | |
| 1455 case INDINDEXSCALEOFFSET: | |
| 1456 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1457 break; | |
| 1458 case LOAD_LONG_INDIRECT: | |
| 1459 case LOAD_LONG_INDOFFSET32: | |
| 1460 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1461 return; | |
| 1462 default: | |
| 1463 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1464 return; | |
| 1465 } | |
| 1466 node->_opnds[opcnt] = new_memory; | |
| 1467 } | |
| 1468 | |
| 1469 // Advertise here if the CPU requires explicit rounding operations | |
| 1470 // to implement the UseStrictFP mode. | |
| 1471 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1472 | |
|
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1473 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1474 // On x32 it is stored with convertion only when FPU is used for floats. |
|
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|
1475 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
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|
1476 |
| 0 | 1477 // Do ints take an entire long register or just half? |
| 1478 const bool Matcher::int_in_long = false; | |
| 1479 | |
| 1480 // Return whether or not this register is ever used as an argument. This | |
| 1481 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1482 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1483 // arguments in those registers not be available to the callee. | |
| 1484 bool Matcher::can_be_java_arg( int reg ) { | |
| 1485 if( reg == ECX_num || reg == EDX_num ) return true; | |
| 1486 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; | |
| 1487 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; | |
| 1488 return false; | |
| 1489 } | |
| 1490 | |
| 1491 bool Matcher::is_spillable_arg( int reg ) { | |
| 1492 return can_be_java_arg(reg); | |
| 1493 } | |
| 1494 | |
|
1914
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|
1495 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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|
1496 // Use hardware integer DIV instruction when |
|
ae065c367d93
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|
1497 // it is faster than a code which use multiply. |
|
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|
1498 // Only when constant divisor fits into 32 bit |
|
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|
1499 // (min_jint is excluded to get only correct |
|
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|
1500 // positive 32 bit values from negative). |
|
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|
1501 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1502 (divisor == (int)divisor && divisor != min_jint); |
|
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|
1503 } |
|
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|
1504 |
| 0 | 1505 // Register for DIVI projection of divmodI |
| 1506 RegMask Matcher::divI_proj_mask() { | |
| 1507 return EAX_REG_mask; | |
| 1508 } | |
| 1509 | |
| 1510 // Register for MODI projection of divmodI | |
| 1511 RegMask Matcher::modI_proj_mask() { | |
| 1512 return EDX_REG_mask; | |
| 1513 } | |
| 1514 | |
| 1515 // Register for DIVL projection of divmodL | |
| 1516 RegMask Matcher::divL_proj_mask() { | |
| 1517 ShouldNotReachHere(); | |
| 1518 return RegMask(); | |
| 1519 } | |
| 1520 | |
| 1521 // Register for MODL projection of divmodL | |
| 1522 RegMask Matcher::modL_proj_mask() { | |
| 1523 ShouldNotReachHere(); | |
| 1524 return RegMask(); | |
| 1525 } | |
| 1526 | |
|
1137
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6829187: compiler optimizations required for JSR 292
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diff
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|
1527 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
97125851f396
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|
1528 return EBP_REG_mask; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
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|
1529 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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diff
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|
1530 |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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|
1531 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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|
1532 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
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|
1533 int opc = n->Opcode(); |
|
e8443c7be117
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|
1534 if (opc == Op_LoadUI2L) { |
|
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parents:
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diff
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|
1535 return true; |
|
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diff
changeset
|
1536 } |
|
e8443c7be117
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diff
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|
1537 if (opc == Op_AndL) { |
|
e8443c7be117
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|
1538 Node* o2 = n->in(2); |
|
e8443c7be117
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|
1539 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
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|
1540 return true; |
|
e8443c7be117
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|
1541 } |
|
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|
1542 } |
|
1914
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|
1543 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
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|
1544 return true; |
|
ae065c367d93
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|
1545 } |
|
1209
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|
1546 return false; |
|
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|
1547 } |
|
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|
1548 |
| 0 | 1549 %} |
| 1550 | |
| 1551 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1552 // This block specifies the encoding classes used by the compiler to output | |
| 1553 // byte streams. Encoding classes generate functions which are called by | |
| 1554 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1555 // instruction. Operands specify their base encoding interface with the | |
| 1556 // interface keyword. There are currently supported four interfaces, | |
| 1557 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1558 // operand to generate a function which returns its register number when | |
| 1559 // queried. CONST_INTER causes an operand to generate a function which | |
| 1560 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1561 // operand to generate four functions which return the Base Register, the | |
| 1562 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1563 // queried. COND_INTER causes an operand to generate six functions which | |
| 1564 // return the encoding code (ie - encoding bits for the instruction) | |
| 1565 // associated with each basic boolean condition for a conditional instruction. | |
| 1566 // Instructions specify two basic values for encoding. They use the | |
| 1567 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1568 // the class names specified in the encoding block), and they use the | |
| 1569 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1570 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1571 // needs for encoding need to be specified. | |
| 1572 encode %{ | |
| 1573 // Build emit functions for each basic byte or larger field in the intel | |
| 1574 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1575 // code in the enc_class source block. Emit functions will live in the | |
| 1576 // main source block for now. In future, we can generalize this by | |
| 1577 // adding a syntax that specifies the sizes of fields in an order, | |
| 1578 // so that the adlc can build the emit functions automagically | |
|
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|
1579 |
|
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|
1580 // Emit primary opcode |
|
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diff
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|
1581 enc_class OpcP %{ |
|
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|
1582 emit_opcode(cbuf, $primary); |
|
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|
1583 %} |
|
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|
1584 |
|
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|
1585 // Emit secondary opcode |
|
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|
1586 enc_class OpcS %{ |
|
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diff
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|
1587 emit_opcode(cbuf, $secondary); |
|
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|
1588 %} |
|
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|
1589 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
1590 // Emit opcode directly |
|
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|
1591 enc_class Opcode(immI d8) %{ |
|
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|
1592 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1593 %} |
| 1594 | |
| 1595 enc_class SizePrefix %{ | |
| 1596 emit_opcode(cbuf,0x66); | |
| 1597 %} | |
| 1598 | |
| 1599 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1600 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1601 %} | |
| 1602 | |
| 1603 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) | |
| 1604 emit_opcode(cbuf,$opcode$$constant); | |
| 1605 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1606 %} | |
| 1607 | |
| 1608 enc_class mov_r32_imm0( eRegI dst ) %{ | |
| 1609 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 | |
| 1610 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1611 %} | |
| 1612 | |
| 1613 enc_class cdq_enc %{ | |
| 1614 // Full implementation of Java idiv and irem; checks for | |
| 1615 // special case as described in JVM spec., p.243 & p.271. | |
| 1616 // | |
| 1617 // normal case special case | |
| 1618 // | |
| 1619 // input : rax,: dividend min_int | |
| 1620 // reg: divisor -1 | |
| 1621 // | |
| 1622 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1623 // rdx: remainder (= rax, irem reg) 0 | |
| 1624 // | |
| 1625 // Code sequnce: | |
| 1626 // | |
| 1627 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1628 // 0F 85 0B 00 00 00 jne normal_case | |
| 1629 // 33 D2 xor rdx,edx | |
| 1630 // 83 F9 FF cmp rcx,0FFh | |
| 1631 // 0F 84 03 00 00 00 je done | |
| 1632 // normal_case: | |
| 1633 // 99 cdq | |
| 1634 // F7 F9 idiv rax,ecx | |
| 1635 // done: | |
| 1636 // | |
| 1637 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1639 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1640 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1641 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1643 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1644 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1645 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1646 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1647 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1648 // normal_case: | |
| 1649 emit_opcode(cbuf,0x99); // cdq | |
| 1650 // idiv (note: must be emitted by the user of this rule) | |
| 1651 // normal: | |
| 1652 %} | |
| 1653 | |
| 1654 // Dense encoding for older common ops | |
| 1655 enc_class Opc_plus(immI opcode, eRegI reg) %{ | |
| 1656 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); | |
| 1657 %} | |
| 1658 | |
| 1659 | |
| 1660 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1661 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1662 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1663 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1664 emit_opcode(cbuf, $primary | 0x02); | |
| 1665 } | |
| 1666 else { // If 32-bit immediate | |
| 1667 emit_opcode(cbuf, $primary); | |
| 1668 } | |
| 1669 %} | |
| 1670 | |
| 1671 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m | |
| 1672 // Emit primary opcode and set sign-extend bit | |
| 1673 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1675 emit_opcode(cbuf, $primary | 0x02); } | |
| 1676 else { // If 32-bit immediate | |
| 1677 emit_opcode(cbuf, $primary); | |
| 1678 } | |
| 1679 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1680 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1681 %} | |
| 1682 | |
| 1683 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1684 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1686 $$$emit8$imm$$constant; | |
| 1687 } | |
| 1688 else { // If 32-bit immediate | |
| 1689 // Output immediate | |
| 1690 $$$emit32$imm$$constant; | |
| 1691 } | |
| 1692 %} | |
| 1693 | |
| 1694 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1695 // Emit primary opcode and set sign-extend bit | |
| 1696 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1697 int con = (int)$imm$$constant; // Throw away top bits | |
| 1698 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1699 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1700 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1701 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1702 else emit_d32(cbuf,con); | |
| 1703 %} | |
| 1704 | |
| 1705 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1706 // Emit primary opcode and set sign-extend bit | |
| 1707 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1708 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1710 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1711 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1713 else emit_d32(cbuf,con); | |
| 1714 %} | |
| 1715 | |
| 3839 | 1716 enc_class Lbl (label labl) %{ // GOTO |
| 0 | 1717 Label *l = $labl$$label; |
| 3839 | 1718 emit_d32(cbuf, (l->loc_pos() - (cbuf.insts_size()+4))); |
| 1719 %} | |
| 1720 | |
| 1721 enc_class LblShort (label labl) %{ // GOTO | |
| 0 | 1722 Label *l = $labl$$label; |
| 3839 | 1723 int disp = l->loc_pos() - (cbuf.insts_size()+1); |
| 0 | 1724 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 1725 emit_d8(cbuf, disp); | |
| 1726 %} | |
| 1727 | |
| 1728 enc_class OpcSReg (eRegI dst) %{ // BSWAP | |
| 1729 emit_cc(cbuf, $secondary, $dst$$reg ); | |
| 1730 %} | |
| 1731 | |
| 1732 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1733 int destlo = $dst$$reg; | |
| 1734 int desthi = HIGH_FROM_LOW(destlo); | |
| 1735 // bswap lo | |
| 1736 emit_opcode(cbuf, 0x0F); | |
| 1737 emit_cc(cbuf, 0xC8, destlo); | |
| 1738 // bswap hi | |
| 1739 emit_opcode(cbuf, 0x0F); | |
| 1740 emit_cc(cbuf, 0xC8, desthi); | |
| 1741 // xchg lo and hi | |
| 1742 emit_opcode(cbuf, 0x87); | |
| 1743 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1744 %} | |
| 1745 | |
| 1746 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... | |
| 1747 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); | |
| 1748 %} | |
| 1749 | |
| 1750 enc_class Jcc (cmpOp cop, label labl) %{ // JCC | |
| 1751 Label *l = $labl$$label; | |
| 1752 $$$emit8$primary; | |
| 1753 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 3839 | 1754 emit_d32(cbuf, (l->loc_pos() - (cbuf.insts_size()+4))); |
| 0 | 1755 %} |
| 1756 | |
| 1757 enc_class JccShort (cmpOp cop, label labl) %{ // JCC | |
| 1758 Label *l = $labl$$label; | |
| 1759 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 3839 | 1760 int disp = l->loc_pos() - (cbuf.insts_size()+1); |
| 0 | 1761 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 1762 emit_d8(cbuf, disp); | |
| 1763 %} | |
| 1764 | |
| 1765 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1766 $$$emit8$primary; | |
| 1767 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1768 %} | |
| 1769 | |
| 1770 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV | |
| 1771 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); | |
| 1772 emit_d8(cbuf, op >> 8 ); | |
| 1773 emit_d8(cbuf, op & 255); | |
| 1774 %} | |
| 1775 | |
| 1776 // emulate a CMOV with a conditional branch around a MOV | |
| 1777 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1778 // Invert sense of branch from sense of CMOV | |
| 1779 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1780 emit_d8( cbuf, $brOffs$$constant ); | |
| 1781 %} | |
| 1782 | |
| 1783 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1784 Register Redi = as_Register(EDI_enc); // result register | |
| 1785 Register Reax = as_Register(EAX_enc); // super class | |
| 1786 Register Recx = as_Register(ECX_enc); // killed | |
| 1787 Register Resi = as_Register(ESI_enc); // sub class | |
|
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1788 Label miss; |
| 0 | 1789 |
| 1790 MacroAssembler _masm(&cbuf); | |
|
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1791 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1792 NULL, &miss, |
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1793 /*set_cond_codes:*/ true); |
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1794 if ($primary) { |
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1795 __ xorptr(Redi, Redi); |
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1796 } |
| 0 | 1797 __ bind(miss); |
| 1798 %} | |
| 1799 | |
| 1800 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1801 MacroAssembler masm(&cbuf); | |
| 1802 int start = masm.offset(); | |
| 1803 if (UseSSE >= 2) { | |
| 1804 if (VerifyFPU) { | |
| 1805 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1806 } | |
| 1807 } else { | |
| 1808 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1809 // Compiled code leaves it dirty. Do cleanup now. | |
| 1810 masm.empty_FPU_stack(); | |
| 1811 } | |
| 1812 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1813 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1814 } else { | |
| 1815 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1816 } | |
| 1817 %} | |
| 1818 | |
| 1819 enc_class Verify_FPU_For_Leaf %{ | |
| 1820 if( VerifyFPU ) { | |
| 1821 MacroAssembler masm(&cbuf); | |
| 1822 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1823 } | |
| 1824 %} | |
| 1825 | |
| 1826 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1827 // This is the instruction starting address for relocation info. | |
| 1748 | 1828 cbuf.set_insts_mark(); |
| 0 | 1829 $$$emit8$primary; |
| 1830 // CALL directly to the runtime | |
| 1748 | 1831 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1832 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1833 | |
| 1834 if (UseSSE >= 2) { | |
| 1835 MacroAssembler _masm(&cbuf); | |
| 1836 BasicType rt = tf()->return_type(); | |
| 1837 | |
| 1838 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1839 // A C runtime call where the return value is unused. In SSE2+ | |
| 1840 // mode the result needs to be removed from the FPU stack. It's | |
| 1841 // likely that this function call could be removed by the | |
| 1842 // optimizer if the C function is a pure function. | |
| 1843 __ ffree(0); | |
| 1844 } else if (rt == T_FLOAT) { | |
| 304 | 1845 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1846 __ fstp_s(Address(rsp, 0)); |
| 1847 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1848 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1849 } else if (rt == T_DOUBLE) { |
| 304 | 1850 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1851 __ fstp_d(Address(rsp, 0)); |
| 1852 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1853 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1854 } |
| 1855 } | |
| 1856 %} | |
| 1857 | |
| 1858 | |
| 1859 enc_class pre_call_FPU %{ | |
| 1860 // If method sets FPU control word restore it here | |
| 1748 | 1861 debug_only(int off0 = cbuf.insts_size()); |
| 0 | 1862 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1863 MacroAssembler masm(&cbuf); | |
| 1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1865 } | |
| 1748 | 1866 debug_only(int off1 = cbuf.insts_size()); |
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1867 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1868 %} |
| 1869 | |
| 1870 enc_class post_call_FPU %{ | |
| 1871 // If method sets FPU control word do it here also | |
| 1872 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1873 MacroAssembler masm(&cbuf); | |
| 1874 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1875 } | |
| 1876 %} | |
| 1877 | |
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1878 enc_class preserve_SP %{ |
| 1748 | 1879 debug_only(int off0 = cbuf.insts_size()); |
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1880 MacroAssembler _masm(&cbuf); |
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1881 // RBP is preserved across all calls, even compiled calls. |
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1882 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 1883 __ movptr(rbp_mh_SP_save, rsp); |
| 1748 | 1884 debug_only(int off1 = cbuf.insts_size()); |
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1885 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
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1886 %} |
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1887 |
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1888 enc_class restore_SP %{ |
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1889 MacroAssembler _masm(&cbuf); |
| 1567 | 1890 __ movptr(rsp, rbp_mh_SP_save); |
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1891 %} |
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1892 |
| 0 | 1893 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 1894 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1895 // who we intended to call. | |
| 1748 | 1896 cbuf.set_insts_mark(); |
| 0 | 1897 $$$emit8$primary; |
| 1898 if ( !_method ) { | |
| 1748 | 1899 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1900 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1901 } else if(_optimized_virtual) { | |
| 1748 | 1902 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1903 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1904 } else { | |
| 1748 | 1905 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1906 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1907 } | |
| 1908 if( _method ) { // Emit stub for static call | |
| 1909 emit_java_to_interp(cbuf); | |
| 1910 } | |
| 1911 %} | |
| 1912 | |
| 1913 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 1914 // !!!!! | |
| 1915 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info | |
| 1916 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 1917 cbuf.set_insts_mark(); |
| 0 | 1918 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 |
| 1919 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); | |
| 1748 | 1920 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 1921 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 1922 // who we intended to call. | |
| 1748 | 1923 cbuf.set_insts_mark(); |
| 0 | 1924 $$$emit8$primary; |
| 1748 | 1925 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1926 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); |
| 1927 %} | |
| 1928 | |
| 1929 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 1930 int disp = in_bytes(methodOopDesc::from_compiled_offset()); | |
| 1931 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); | |
| 1932 | |
| 1933 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] | |
| 1748 | 1934 cbuf.set_insts_mark(); |
| 0 | 1935 $$$emit8$primary; |
| 1936 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1937 emit_d8(cbuf, disp); // Displacement | |
| 1938 | |
| 1939 %} | |
| 1940 | |
| 1941 enc_class Xor_Reg (eRegI dst) %{ | |
| 1942 emit_opcode(cbuf, 0x33); | |
| 1943 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 1944 %} | |
| 1945 | |
| 1946 // Following encoding is no longer used, but may be restored if calling | |
| 1947 // convention changes significantly. | |
| 1948 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1949 // | |
| 1950 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1951 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1952 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1953 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1954 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1955 // | |
| 1956 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1957 // // // so we load it immediately before the call | |
| 1958 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1959 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1960 // | |
| 1961 // // xor rbp,ebp | |
| 1962 // emit_opcode(cbuf, 0x33); | |
| 1963 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1964 // | |
| 1965 // // CALL to interpreter. | |
| 1748 | 1966 // cbuf.set_insts_mark(); |
| 0 | 1967 // $$$emit8$primary; |
| 1748 | 1968 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1969 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1970 // %} | |
| 1971 | |
| 1972 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR | |
| 1973 $$$emit8$primary; | |
| 1974 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1975 $$$emit8$shift$$constant; | |
| 1976 %} | |
| 1977 | |
| 1978 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate | |
| 1979 // Load immediate does not have a zero or sign extended version | |
| 1980 // for 8-bit immediates | |
| 1981 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1982 $$$emit32$src$$constant; | |
| 1983 %} | |
| 1984 | |
| 1985 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate | |
| 1986 // Load immediate does not have a zero or sign extended version | |
| 1987 // for 8-bit immediates | |
| 1988 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1989 $$$emit32$src$$constant; | |
| 1990 %} | |
| 1991 | |
| 1992 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1993 // Load immediate does not have a zero or sign extended version | |
| 1994 // for 8-bit immediates | |
| 1995 int dst_enc = $dst$$reg; | |
| 1996 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1997 if (src_con == 0) { | |
| 1998 // xor dst, dst | |
| 1999 emit_opcode(cbuf, 0x33); | |
| 2000 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 2001 } else { | |
| 2002 emit_opcode(cbuf, $primary + dst_enc); | |
| 2003 emit_d32(cbuf, src_con); | |
| 2004 } | |
| 2005 %} | |
| 2006 | |
| 2007 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 2008 // Load immediate does not have a zero or sign extended version | |
| 2009 // for 8-bit immediates | |
| 2010 int dst_enc = $dst$$reg + 2; | |
| 2011 int src_con = ((julong)($src$$constant)) >> 32; | |
| 2012 if (src_con == 0) { | |
| 2013 // xor dst, dst | |
| 2014 emit_opcode(cbuf, 0x33); | |
| 2015 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 2016 } else { | |
| 2017 emit_opcode(cbuf, $primary + dst_enc); | |
| 2018 emit_d32(cbuf, src_con); | |
| 2019 } | |
| 2020 %} | |
| 2021 | |
| 2022 | |
| 2023 enc_class MovI2X_reg(regX dst, eRegI src) %{ | |
| 2024 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2025 emit_opcode(cbuf, 0x0F ); | |
| 2026 emit_opcode(cbuf, 0x6E ); | |
| 2027 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2028 %} | |
| 2029 | |
| 2030 enc_class MovX2I_reg(eRegI dst, regX src) %{ | |
| 2031 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2032 emit_opcode(cbuf, 0x0F ); | |
| 2033 emit_opcode(cbuf, 0x7E ); | |
| 2034 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2035 %} | |
| 2036 | |
| 2037 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ | |
| 2038 { // MOVD $dst,$src.lo | |
| 2039 emit_opcode(cbuf,0x66); | |
| 2040 emit_opcode(cbuf,0x0F); | |
| 2041 emit_opcode(cbuf,0x6E); | |
| 2042 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2043 } | |
| 2044 { // MOVD $tmp,$src.hi | |
| 2045 emit_opcode(cbuf,0x66); | |
| 2046 emit_opcode(cbuf,0x0F); | |
| 2047 emit_opcode(cbuf,0x6E); | |
| 2048 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2049 } | |
| 2050 { // PUNPCKLDQ $dst,$tmp | |
| 2051 emit_opcode(cbuf,0x66); | |
| 2052 emit_opcode(cbuf,0x0F); | |
| 2053 emit_opcode(cbuf,0x62); | |
| 2054 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); | |
| 2055 } | |
| 2056 %} | |
| 2057 | |
| 2058 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ | |
| 2059 { // MOVD $dst.lo,$src | |
| 2060 emit_opcode(cbuf,0x66); | |
| 2061 emit_opcode(cbuf,0x0F); | |
| 2062 emit_opcode(cbuf,0x7E); | |
| 2063 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2064 } | |
| 2065 { // PSHUFLW $tmp,$src,0x4E (01001110b) | |
| 2066 emit_opcode(cbuf,0xF2); | |
| 2067 emit_opcode(cbuf,0x0F); | |
| 2068 emit_opcode(cbuf,0x70); | |
| 2069 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2070 emit_d8(cbuf, 0x4E); | |
| 2071 } | |
| 2072 { // MOVD $dst.hi,$tmp | |
| 2073 emit_opcode(cbuf,0x66); | |
| 2074 emit_opcode(cbuf,0x0F); | |
| 2075 emit_opcode(cbuf,0x7E); | |
| 2076 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2077 } | |
| 2078 %} | |
| 2079 | |
| 2080 | |
| 2081 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2082 enc_class enc_Copy( eRegI dst, eRegI src ) %{ | |
| 2083 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2084 %} | |
| 2085 | |
| 2086 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ | |
| 2087 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2088 %} | |
| 2089 | |
| 2090 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2091 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ | |
| 2092 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2093 %} | |
| 2094 | |
| 2095 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 2096 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2097 %} | |
| 2098 | |
| 2099 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2100 $$$emit8$primary; | |
| 2101 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2102 %} | |
| 2103 | |
| 2104 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2105 $$$emit8$secondary; | |
| 2106 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2107 %} | |
| 2108 | |
| 2109 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2110 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2111 %} | |
| 2112 | |
| 2113 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2114 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2115 %} | |
| 2116 | |
| 2117 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ | |
| 2118 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2119 %} | |
| 2120 | |
| 2121 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2122 // Output immediate | |
| 2123 $$$emit32$src$$constant; | |
| 2124 %} | |
| 2125 | |
| 2126 enc_class Con32F_as_bits(immF src) %{ // storeF_imm | |
| 2127 // Output Float immediate bits | |
| 2128 jfloat jf = $src$$constant; | |
| 2129 int jf_as_bits = jint_cast( jf ); | |
| 2130 emit_d32(cbuf, jf_as_bits); | |
| 2131 %} | |
| 2132 | |
| 2133 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm | |
| 2134 // Output Float immediate bits | |
| 2135 jfloat jf = $src$$constant; | |
| 2136 int jf_as_bits = jint_cast( jf ); | |
| 2137 emit_d32(cbuf, jf_as_bits); | |
| 2138 %} | |
| 2139 | |
| 2140 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2141 // Output immediate | |
| 2142 $$$emit16$src$$constant; | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class Con_d32(immI src) %{ | |
| 2146 emit_d32(cbuf,$src$$constant); | |
| 2147 %} | |
| 2148 | |
| 2149 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2150 // Output immediate memory reference | |
| 2151 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2152 emit_d32(cbuf, 0x00); | |
| 2153 %} | |
| 2154 | |
| 2155 enc_class lock_prefix( ) %{ | |
| 2156 if( os::is_MP() ) | |
| 2157 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2158 %} | |
| 2159 | |
| 2160 // Cmp-xchg long value. | |
| 2161 // Note: we need to swap rbx, and rcx before and after the | |
| 2162 // cmpxchg8 instruction because the instruction uses | |
| 2163 // rcx as the high order word of the new value to store but | |
| 2164 // our register encoding uses rbx,. | |
| 2165 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2166 | |
| 2167 // XCHG rbx,ecx | |
| 2168 emit_opcode(cbuf,0x87); | |
| 2169 emit_opcode(cbuf,0xD9); | |
| 2170 // [Lock] | |
| 2171 if( os::is_MP() ) | |
| 2172 emit_opcode(cbuf,0xF0); | |
| 2173 // CMPXCHG8 [Eptr] | |
| 2174 emit_opcode(cbuf,0x0F); | |
| 2175 emit_opcode(cbuf,0xC7); | |
| 2176 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2177 // XCHG rbx,ecx | |
| 2178 emit_opcode(cbuf,0x87); | |
| 2179 emit_opcode(cbuf,0xD9); | |
| 2180 %} | |
| 2181 | |
| 2182 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2183 // [Lock] | |
| 2184 if( os::is_MP() ) | |
| 2185 emit_opcode(cbuf,0xF0); | |
| 2186 | |
| 2187 // CMPXCHG [Eptr] | |
| 2188 emit_opcode(cbuf,0x0F); | |
| 2189 emit_opcode(cbuf,0xB1); | |
| 2190 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2191 %} | |
| 2192 | |
| 2193 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2194 int res_encoding = $res$$reg; | |
| 2195 | |
| 2196 // MOV res,0 | |
| 2197 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2198 emit_d32( cbuf, 0 ); | |
| 2199 // JNE,s fail | |
| 2200 emit_opcode(cbuf,0x75); | |
| 2201 emit_d8(cbuf, 5 ); | |
| 2202 // MOV res,1 | |
| 2203 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2204 emit_d32( cbuf, 1 ); | |
| 2205 // fail: | |
| 2206 %} | |
| 2207 | |
| 2208 enc_class set_instruction_start( ) %{ | |
| 1748 | 2209 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2210 %} |
| 2211 | |
| 2212 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 2213 int reg_encoding = $ereg$$reg; | |
| 2214 int base = $mem$$base; | |
| 2215 int index = $mem$$index; | |
| 2216 int scale = $mem$$scale; | |
| 2217 int displace = $mem$$disp; | |
| 2218 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2219 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2220 %} | |
| 2221 | |
| 2222 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2223 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2224 int base = $mem$$base; | |
| 2225 int index = $mem$$index; | |
| 2226 int scale = $mem$$scale; | |
| 2227 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
| 2228 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); | |
| 2229 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); | |
| 2230 %} | |
| 2231 | |
| 2232 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2233 int r1, r2; | |
| 2234 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2235 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2236 emit_opcode(cbuf,0x0F); | |
| 2237 emit_opcode(cbuf,$tertiary); | |
| 2238 emit_rm(cbuf, 0x3, r1, r2); | |
| 2239 emit_d8(cbuf,$cnt$$constant); | |
| 2240 emit_d8(cbuf,$primary); | |
| 2241 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2242 emit_d8(cbuf,$cnt$$constant); | |
| 2243 %} | |
| 2244 | |
| 2245 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2246 emit_opcode( cbuf, 0x8B ); // Move | |
| 2247 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
|
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2248 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2249 emit_d8(cbuf,$primary); |
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2250 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2251 emit_d8(cbuf,$cnt$$constant-32); |
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2252 } |
| 0 | 2253 emit_d8(cbuf,$primary); |
| 2254 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2255 emit_d8(cbuf,31); | |
| 2256 %} | |
| 2257 | |
| 2258 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2259 int r1, r2; | |
| 2260 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2261 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2262 | |
| 2263 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2264 emit_rm(cbuf, 0x3, r1, r2); | |
| 2265 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2266 emit_opcode(cbuf,$primary); | |
| 2267 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2268 emit_d8(cbuf,$cnt$$constant-32); | |
| 2269 } | |
| 2270 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2271 emit_rm(cbuf, 0x3, r2, r2); | |
| 2272 %} | |
| 2273 | |
| 2274 // Clone of RegMem but accepts an extra parameter to access each | |
| 2275 // half of a double in memory; it never needs relocation info. | |
| 2276 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ | |
| 2277 emit_opcode(cbuf,$opcode$$constant); | |
| 2278 int reg_encoding = $rm_reg$$reg; | |
| 2279 int base = $mem$$base; | |
| 2280 int index = $mem$$index; | |
| 2281 int scale = $mem$$scale; | |
| 2282 int displace = $mem$$disp + $disp_for_half$$constant; | |
| 2283 bool disp_is_oop = false; | |
| 2284 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2285 %} | |
| 2286 | |
| 2287 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2288 // | |
| 2289 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2290 // and it never needs relocation information. | |
| 2291 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2292 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2293 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2294 int base = $mem$$base; | |
| 2295 int index = $mem$$index; | |
| 2296 int scale = $mem$$scale; | |
| 2297 int displace = $mem$$disp; | |
| 2298 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); | |
| 2299 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); | |
| 2300 %} | |
| 2301 | |
| 2302 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2303 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2304 int base = $mem$$base; | |
| 2305 int index = $mem$$index; | |
| 2306 int scale = $mem$$scale; | |
| 2307 int displace = $mem$$disp; | |
| 2308 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2309 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 2310 %} | |
| 2311 | |
| 2312 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea | |
| 2313 int reg_encoding = $dst$$reg; | |
| 2314 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2315 int index = 0x04; // 0x04 indicates no index | |
| 2316 int scale = 0x00; // 0x00 indicates no scale | |
| 2317 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2318 bool disp_is_oop = false; | |
| 2319 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2320 %} | |
| 2321 | |
| 2322 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN | |
| 2323 // Compare dst,src | |
| 2324 emit_opcode(cbuf,0x3B); | |
| 2325 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2326 // jmp dst < src around move | |
| 2327 emit_opcode(cbuf,0x7C); | |
| 2328 emit_d8(cbuf,2); | |
| 2329 // move dst,src | |
| 2330 emit_opcode(cbuf,0x8B); | |
| 2331 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2332 %} | |
| 2333 | |
| 2334 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX | |
| 2335 // Compare dst,src | |
| 2336 emit_opcode(cbuf,0x3B); | |
| 2337 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2338 // jmp dst > src around move | |
| 2339 emit_opcode(cbuf,0x7F); | |
| 2340 emit_d8(cbuf,2); | |
| 2341 // move dst,src | |
| 2342 emit_opcode(cbuf,0x8B); | |
| 2343 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2344 %} | |
| 2345 | |
| 2346 enc_class enc_FP_store(memory mem, regD src) %{ | |
| 2347 // If src is FPR1, we can just FST to store it. | |
| 2348 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2349 int reg_encoding = 0x2; // Just store | |
| 2350 int base = $mem$$base; | |
| 2351 int index = $mem$$index; | |
| 2352 int scale = $mem$$scale; | |
| 2353 int displace = $mem$$disp; | |
| 2354 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2355 if( $src$$reg != FPR1L_enc ) { | |
| 2356 reg_encoding = 0x3; // Store & pop | |
| 2357 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2358 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2359 } | |
| 1748 | 2360 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2361 emit_opcode(cbuf,$primary); |
| 2362 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2363 %} | |
| 2364 | |
| 2365 enc_class neg_reg(eRegI dst) %{ | |
| 2366 // NEG $dst | |
| 2367 emit_opcode(cbuf,0xF7); | |
| 2368 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2369 %} | |
| 2370 | |
| 2371 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2372 // SETLT $dst | |
| 2373 emit_opcode(cbuf,0x0F); | |
| 2374 emit_opcode(cbuf,0x9C); | |
| 2375 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2376 %} | |
| 2377 | |
| 2378 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2379 int tmpReg = $tmp$$reg; | |
| 2380 | |
| 2381 // SUB $p,$q | |
| 2382 emit_opcode(cbuf,0x2B); | |
| 2383 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2384 // SBB $tmp,$tmp | |
| 2385 emit_opcode(cbuf,0x1B); | |
| 2386 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2387 // AND $tmp,$y | |
| 2388 emit_opcode(cbuf,0x23); | |
| 2389 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2390 // ADD $p,$tmp | |
| 2391 emit_opcode(cbuf,0x03); | |
| 2392 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2393 %} | |
| 2394 | |
| 2395 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2396 int tmpReg = $tmp$$reg; | |
| 2397 | |
| 2398 // SUB $p,$q | |
| 2399 emit_opcode(cbuf,0x2B); | |
| 2400 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2401 // SBB $tmp,$tmp | |
| 2402 emit_opcode(cbuf,0x1B); | |
| 2403 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2404 // AND $tmp,$y | |
| 1748 | 2405 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2406 emit_opcode(cbuf,0x23); |
| 2407 int reg_encoding = tmpReg; | |
| 2408 int base = $mem$$base; | |
| 2409 int index = $mem$$index; | |
| 2410 int scale = $mem$$scale; | |
| 2411 int displace = $mem$$disp; | |
| 2412 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2413 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2414 // ADD $p,$tmp | |
| 2415 emit_opcode(cbuf,0x03); | |
| 2416 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2417 %} | |
| 2418 | |
| 2419 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2420 // TEST shift,32 | |
| 2421 emit_opcode(cbuf,0xF7); | |
| 2422 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2423 emit_d32(cbuf,0x20); | |
| 2424 // JEQ,s small | |
| 2425 emit_opcode(cbuf, 0x74); | |
| 2426 emit_d8(cbuf, 0x04); | |
| 2427 // MOV $dst.hi,$dst.lo | |
| 2428 emit_opcode( cbuf, 0x8B ); | |
| 2429 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2430 // CLR $dst.lo | |
| 2431 emit_opcode(cbuf, 0x33); | |
| 2432 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2433 // small: | |
| 2434 // SHLD $dst.hi,$dst.lo,$shift | |
| 2435 emit_opcode(cbuf,0x0F); | |
| 2436 emit_opcode(cbuf,0xA5); | |
| 2437 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2438 // SHL $dst.lo,$shift" | |
| 2439 emit_opcode(cbuf,0xD3); | |
| 2440 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2441 %} | |
| 2442 | |
| 2443 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2444 // TEST shift,32 | |
| 2445 emit_opcode(cbuf,0xF7); | |
| 2446 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2447 emit_d32(cbuf,0x20); | |
| 2448 // JEQ,s small | |
| 2449 emit_opcode(cbuf, 0x74); | |
| 2450 emit_d8(cbuf, 0x04); | |
| 2451 // MOV $dst.lo,$dst.hi | |
| 2452 emit_opcode( cbuf, 0x8B ); | |
| 2453 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2454 // CLR $dst.hi | |
| 2455 emit_opcode(cbuf, 0x33); | |
| 2456 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2457 // small: | |
| 2458 // SHRD $dst.lo,$dst.hi,$shift | |
| 2459 emit_opcode(cbuf,0x0F); | |
| 2460 emit_opcode(cbuf,0xAD); | |
| 2461 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2462 // SHR $dst.hi,$shift" | |
| 2463 emit_opcode(cbuf,0xD3); | |
| 2464 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2465 %} | |
| 2466 | |
| 2467 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2468 // TEST shift,32 | |
| 2469 emit_opcode(cbuf,0xF7); | |
| 2470 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2471 emit_d32(cbuf,0x20); | |
| 2472 // JEQ,s small | |
| 2473 emit_opcode(cbuf, 0x74); | |
| 2474 emit_d8(cbuf, 0x05); | |
| 2475 // MOV $dst.lo,$dst.hi | |
| 2476 emit_opcode( cbuf, 0x8B ); | |
| 2477 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2478 // SAR $dst.hi,31 | |
| 2479 emit_opcode(cbuf, 0xC1); | |
| 2480 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2481 emit_d8(cbuf, 0x1F ); | |
| 2482 // small: | |
| 2483 // SHRD $dst.lo,$dst.hi,$shift | |
| 2484 emit_opcode(cbuf,0x0F); | |
| 2485 emit_opcode(cbuf,0xAD); | |
| 2486 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2487 // SAR $dst.hi,$shift" | |
| 2488 emit_opcode(cbuf,0xD3); | |
| 2489 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2490 %} | |
| 2491 | |
| 2492 | |
| 2493 // ----------------- Encodings for floating point unit ----------------- | |
| 2494 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
| 2495 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV | |
| 2496 $$$emit8$primary; | |
| 2497 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2498 %} | |
| 2499 | |
| 2500 // Pop argument in FPR0 with FSTP ST(0) | |
| 2501 enc_class PopFPU() %{ | |
| 2502 emit_opcode( cbuf, 0xDD ); | |
| 2503 emit_d8( cbuf, 0xD8 ); | |
| 2504 %} | |
| 2505 | |
| 2506 // !!!!! equivalent to Pop_Reg_F | |
| 2507 enc_class Pop_Reg_D( regD dst ) %{ | |
| 2508 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2509 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2510 %} | |
| 2511 | |
| 2512 enc_class Push_Reg_D( regD dst ) %{ | |
| 2513 emit_opcode( cbuf, 0xD9 ); | |
| 2514 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2515 %} | |
| 2516 | |
| 2517 enc_class strictfp_bias1( regD dst ) %{ | |
| 2518 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2519 emit_opcode( cbuf, 0x2D ); | |
| 2520 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2521 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2522 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2523 %} | |
| 2524 | |
| 2525 enc_class strictfp_bias2( regD dst ) %{ | |
| 2526 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2527 emit_opcode( cbuf, 0x2D ); | |
| 2528 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2529 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2530 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2531 %} | |
| 2532 | |
| 2533 // Special case for moving an integer register to a stack slot. | |
| 2534 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2535 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); | |
| 2536 %} | |
| 2537 | |
| 2538 // Special case for moving a register to a stack slot. | |
| 2539 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2540 // Opcode already emitted | |
| 2541 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2542 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2543 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2544 %} | |
| 2545 | |
| 2546 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2547 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2548 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2549 %} | |
| 2550 | |
| 2551 // Push the float in stackSlot 'src' onto FP-stack | |
| 2552 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] | |
| 2553 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); | |
| 2554 %} | |
| 2555 | |
| 2556 // Push the double in stackSlot 'src' onto FP-stack | |
| 2557 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] | |
| 2558 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); | |
| 2559 %} | |
| 2560 | |
| 2561 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
| 2562 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] | |
| 2563 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); | |
| 2564 %} | |
| 2565 | |
| 2566 // Same as Pop_Mem_F except for opcode | |
| 2567 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
| 2568 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] | |
| 2569 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); | |
| 2570 %} | |
| 2571 | |
| 2572 enc_class Pop_Reg_F( regF dst ) %{ | |
| 2573 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2574 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2575 %} | |
| 2576 | |
| 2577 enc_class Push_Reg_F( regF dst ) %{ | |
| 2578 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2579 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2580 %} | |
| 2581 | |
| 2582 // Push FPU's float to a stack-slot, and pop FPU-stack | |
| 2583 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ | |
| 2584 int pop = 0x02; | |
| 2585 if ($src$$reg != FPR1L_enc) { | |
| 2586 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2587 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2588 pop = 0x03; | |
| 2589 } | |
| 2590 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2591 %} | |
| 2592 | |
| 2593 // Push FPU's double to a stack-slot, and pop FPU-stack | |
| 2594 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ | |
| 2595 int pop = 0x02; | |
| 2596 if ($src$$reg != FPR1L_enc) { | |
| 2597 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2598 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2599 pop = 0x03; | |
| 2600 } | |
| 2601 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2602 %} | |
| 2603 | |
| 2604 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
| 2605 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ | |
| 2606 int pop = 0xD0 - 1; // -1 since we skip FLD | |
| 2607 if ($src$$reg != FPR1L_enc) { | |
| 2608 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2609 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2610 pop = 0xD8; | |
| 2611 } | |
| 2612 emit_opcode( cbuf, 0xDD ); | |
| 2613 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2614 %} | |
| 2615 | |
| 2616 | |
| 2617 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ | |
| 2618 MacroAssembler masm(&cbuf); | |
| 2619 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg | |
| 2620 masm.fmul( $src2$$reg+0); // value at TOS | |
| 2621 masm.fadd( $src$$reg+0); // value at TOS | |
| 2622 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store | |
| 2623 %} | |
| 2624 | |
| 2625 | |
| 2626 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ | |
| 2627 // load dst in FPR0 | |
| 2628 emit_opcode( cbuf, 0xD9 ); | |
| 2629 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2630 if ($src$$reg != FPR1L_enc) { | |
| 2631 // fincstp | |
| 2632 emit_opcode (cbuf, 0xD9); | |
| 2633 emit_opcode (cbuf, 0xF7); | |
| 2634 // swap src with FPR1: | |
| 2635 // FXCH FPR1 with src | |
| 2636 emit_opcode(cbuf, 0xD9); | |
| 2637 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2638 // fdecstp | |
| 2639 emit_opcode (cbuf, 0xD9); | |
| 2640 emit_opcode (cbuf, 0xF6); | |
| 2641 } | |
| 2642 %} | |
| 2643 | |
| 2644 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ | |
| 2645 // Allocate a word | |
| 2646 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2647 emit_opcode(cbuf,0xEC); | |
| 2648 emit_d8(cbuf,0x08); | |
| 2649 | |
| 2650 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 | |
| 2651 emit_opcode (cbuf, 0x0F ); | |
| 2652 emit_opcode (cbuf, 0x11 ); | |
| 2653 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2654 | |
| 2655 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2656 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2657 | |
| 2658 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 | |
| 2659 emit_opcode (cbuf, 0x0F ); | |
| 2660 emit_opcode (cbuf, 0x11 ); | |
| 2661 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2662 | |
| 2663 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2664 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2665 | |
| 2666 %} | |
| 2667 | |
| 2668 enc_class Push_ModX_encoding( regX src0, regX src1) %{ | |
| 2669 // Allocate a word | |
| 2670 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2671 emit_opcode(cbuf,0xEC); | |
| 2672 emit_d8(cbuf,0x04); | |
| 2673 | |
| 2674 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 | |
| 2675 emit_opcode (cbuf, 0x0F ); | |
| 2676 emit_opcode (cbuf, 0x11 ); | |
| 2677 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2678 | |
| 2679 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2680 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2681 | |
| 2682 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 | |
| 2683 emit_opcode (cbuf, 0x0F ); | |
| 2684 emit_opcode (cbuf, 0x11 ); | |
| 2685 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2686 | |
| 2687 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2688 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2689 | |
| 2690 %} | |
| 2691 | |
| 2692 enc_class Push_ResultXD(regXD dst) %{ | |
| 2693 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] | |
| 2694 | |
| 2695 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] | |
| 2696 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2697 emit_opcode (cbuf, 0x0F ); | |
| 2698 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2699 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2700 | |
| 2701 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2702 emit_opcode(cbuf,0xC4); | |
| 2703 emit_d8(cbuf,0x08); | |
| 2704 %} | |
| 2705 | |
| 2706 enc_class Push_ResultX(regX dst, immI d8) %{ | |
| 2707 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] | |
| 2708 | |
| 2709 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 2710 emit_opcode (cbuf, 0x0F ); | |
| 2711 emit_opcode (cbuf, 0x10 ); | |
| 2712 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2713 | |
| 2714 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) | |
| 2715 emit_opcode(cbuf,0xC4); | |
| 2716 emit_d8(cbuf,$d8$$constant); | |
| 2717 %} | |
| 2718 | |
| 2719 enc_class Push_SrcXD(regXD src) %{ | |
| 2720 // Allocate a word | |
| 2721 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2722 emit_opcode(cbuf,0xEC); | |
| 2723 emit_d8(cbuf,0x08); | |
| 2724 | |
| 2725 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 2726 emit_opcode (cbuf, 0x0F ); | |
| 2727 emit_opcode (cbuf, 0x11 ); | |
| 2728 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2729 | |
| 2730 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2731 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2732 %} | |
| 2733 | |
| 2734 enc_class push_stack_temp_qword() %{ | |
| 2735 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2736 emit_opcode(cbuf,0xEC); | |
| 2737 emit_d8 (cbuf,0x08); | |
| 2738 %} | |
| 2739 | |
| 2740 enc_class pop_stack_temp_qword() %{ | |
| 2741 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2742 emit_opcode(cbuf,0xC4); | |
| 2743 emit_d8 (cbuf,0x08); | |
| 2744 %} | |
| 2745 | |
| 2746 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ | |
| 2747 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src | |
| 2748 emit_opcode (cbuf, 0x0F ); | |
| 2749 emit_opcode (cbuf, 0x11 ); | |
| 2750 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2751 | |
| 2752 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2753 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2754 %} | |
| 2755 | |
| 2756 // Compute X^Y using Intel's fast hardware instructions, if possible. | |
| 2757 // Otherwise return a NaN. | |
| 2758 enc_class pow_exp_core_encoding %{ | |
| 2759 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) | |
| 2760 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q | |
| 2761 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q | |
| 2762 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) | |
| 2763 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) | |
| 2764 emit_opcode(cbuf,0x1C); | |
| 2765 emit_d8(cbuf,0x24); | |
| 2766 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 | |
| 2767 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 | |
| 2768 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) | |
| 2769 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) | |
| 2770 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); | |
| 2771 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask | |
| 2772 emit_rm(cbuf, 0x3, 0x0, ECX_enc); | |
| 2773 emit_d32(cbuf,0xFFFFF800); | |
| 2774 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias | |
| 2775 emit_rm(cbuf, 0x3, 0x0, EAX_enc); | |
| 2776 emit_d32(cbuf,1023); | |
| 2777 emit_opcode(cbuf,0x8B); // mov rbx,eax | |
| 2778 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); | |
| 2779 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position | |
| 2780 emit_rm(cbuf,0x3,0x4,EAX_enc); | |
| 2781 emit_d8(cbuf,20); | |
| 2782 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow | |
| 2783 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); | |
| 2784 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX | |
| 2785 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); | |
| 2786 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word | |
| 2787 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); | |
| 2788 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) | |
| 2789 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2790 emit_d32(cbuf,0); | |
| 2791 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q | |
| 2792 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); | |
| 2793 %} | |
| 2794 | |
| 2795 // enc_class Pop_Reg_Mod_D( regD dst, regD src) | |
| 2796 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() | |
| 2797 | |
| 2798 enc_class Push_Result_Mod_D( regD src) %{ | |
| 2799 if ($src$$reg != FPR1L_enc) { | |
| 2800 // fincstp | |
| 2801 emit_opcode (cbuf, 0xD9); | |
| 2802 emit_opcode (cbuf, 0xF7); | |
| 2803 // FXCH FPR1 with src | |
| 2804 emit_opcode(cbuf, 0xD9); | |
| 2805 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2806 // fdecstp | |
| 2807 emit_opcode (cbuf, 0xD9); | |
| 2808 emit_opcode (cbuf, 0xF6); | |
| 2809 } | |
| 2810 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2811 // // FSTP FPR$dst$$reg | |
| 2812 // emit_opcode( cbuf, 0xDD ); | |
| 2813 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2814 %} | |
| 2815 | |
| 2816 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2817 // fnstsw ax | |
| 2818 emit_opcode( cbuf, 0xDF ); | |
| 2819 emit_opcode( cbuf, 0xE0 ); | |
| 2820 // sahf | |
| 2821 emit_opcode( cbuf, 0x9E ); | |
| 2822 // jnp ::skip | |
| 2823 emit_opcode( cbuf, 0x7B ); | |
| 2824 emit_opcode( cbuf, 0x05 ); | |
| 2825 %} | |
| 2826 | |
| 2827 enc_class emitModD() %{ | |
| 2828 // fprem must be iterative | |
| 2829 // :: loop | |
| 2830 // fprem | |
| 2831 emit_opcode( cbuf, 0xD9 ); | |
| 2832 emit_opcode( cbuf, 0xF8 ); | |
| 2833 // wait | |
| 2834 emit_opcode( cbuf, 0x9b ); | |
| 2835 // fnstsw ax | |
| 2836 emit_opcode( cbuf, 0xDF ); | |
| 2837 emit_opcode( cbuf, 0xE0 ); | |
| 2838 // sahf | |
| 2839 emit_opcode( cbuf, 0x9E ); | |
| 2840 // jp ::loop | |
| 2841 emit_opcode( cbuf, 0x0F ); | |
| 2842 emit_opcode( cbuf, 0x8A ); | |
| 2843 emit_opcode( cbuf, 0xF4 ); | |
| 2844 emit_opcode( cbuf, 0xFF ); | |
| 2845 emit_opcode( cbuf, 0xFF ); | |
| 2846 emit_opcode( cbuf, 0xFF ); | |
| 2847 %} | |
| 2848 | |
| 2849 enc_class fpu_flags() %{ | |
| 2850 // fnstsw_ax | |
| 2851 emit_opcode( cbuf, 0xDF); | |
| 2852 emit_opcode( cbuf, 0xE0); | |
| 2853 // test ax,0x0400 | |
| 2854 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2855 emit_opcode( cbuf, 0xA9 ); | |
| 2856 emit_d16 ( cbuf, 0x0400 ); | |
| 2857 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2858 // // test rax,0x0400 | |
| 2859 // emit_opcode( cbuf, 0xA9 ); | |
| 2860 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2861 // | |
| 2862 // jz exit (no unordered comparison) | |
| 2863 emit_opcode( cbuf, 0x74 ); | |
| 2864 emit_d8 ( cbuf, 0x02 ); | |
| 2865 // mov ah,1 - treat as LT case (set carry flag) | |
| 2866 emit_opcode( cbuf, 0xB4 ); | |
| 2867 emit_d8 ( cbuf, 0x01 ); | |
| 2868 // sahf | |
| 2869 emit_opcode( cbuf, 0x9E); | |
| 2870 %} | |
| 2871 | |
| 2872 enc_class cmpF_P6_fixup() %{ | |
| 2873 // Fixup the integer flags in case comparison involved a NaN | |
| 2874 // | |
| 2875 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2876 emit_opcode( cbuf, 0x7B ); | |
| 2877 emit_d8 ( cbuf, 0x03 ); | |
| 2878 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2879 emit_opcode( cbuf, 0xB4 ); | |
| 2880 emit_d8 ( cbuf, 0x01 ); | |
| 2881 // SAHF | |
| 2882 emit_opcode( cbuf, 0x9E); | |
| 2883 // NOP // target for branch to avoid branch to branch | |
| 2884 emit_opcode( cbuf, 0x90); | |
| 2885 %} | |
| 2886 | |
| 2887 // fnstsw_ax(); | |
| 2888 // sahf(); | |
| 2889 // movl(dst, nan_result); | |
| 2890 // jcc(Assembler::parity, exit); | |
| 2891 // movl(dst, less_result); | |
| 2892 // jcc(Assembler::below, exit); | |
| 2893 // movl(dst, equal_result); | |
| 2894 // jcc(Assembler::equal, exit); | |
| 2895 // movl(dst, greater_result); | |
| 2896 | |
| 2897 // less_result = 1; | |
| 2898 // greater_result = -1; | |
| 2899 // equal_result = 0; | |
| 2900 // nan_result = -1; | |
| 2901 | |
| 2902 enc_class CmpF_Result(eRegI dst) %{ | |
| 2903 // fnstsw_ax(); | |
| 2904 emit_opcode( cbuf, 0xDF); | |
| 2905 emit_opcode( cbuf, 0xE0); | |
| 2906 // sahf | |
| 2907 emit_opcode( cbuf, 0x9E); | |
| 2908 // movl(dst, nan_result); | |
| 2909 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2910 emit_d32( cbuf, -1 ); | |
| 2911 // jcc(Assembler::parity, exit); | |
| 2912 emit_opcode( cbuf, 0x7A ); | |
| 2913 emit_d8 ( cbuf, 0x13 ); | |
| 2914 // movl(dst, less_result); | |
| 2915 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2916 emit_d32( cbuf, -1 ); | |
| 2917 // jcc(Assembler::below, exit); | |
| 2918 emit_opcode( cbuf, 0x72 ); | |
| 2919 emit_d8 ( cbuf, 0x0C ); | |
| 2920 // movl(dst, equal_result); | |
| 2921 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2922 emit_d32( cbuf, 0 ); | |
| 2923 // jcc(Assembler::equal, exit); | |
| 2924 emit_opcode( cbuf, 0x74 ); | |
| 2925 emit_d8 ( cbuf, 0x05 ); | |
| 2926 // movl(dst, greater_result); | |
| 2927 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2928 emit_d32( cbuf, 1 ); | |
| 2929 %} | |
| 2930 | |
| 2931 | |
| 2932 // XMM version of CmpF_Result. Because the XMM compare | |
| 2933 // instructions set the EFLAGS directly. It becomes simpler than | |
| 2934 // the float version above. | |
| 2935 enc_class CmpX_Result(eRegI dst) %{ | |
| 2936 MacroAssembler _masm(&cbuf); | |
| 2937 Label nan, inc, done; | |
| 2938 | |
| 2939 __ jccb(Assembler::parity, nan); | |
| 2940 __ jccb(Assembler::equal, done); | |
| 2941 __ jccb(Assembler::above, inc); | |
| 2942 __ bind(nan); | |
| 304 | 2943 __ decrement(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2944 __ jmpb(done); |
| 2945 __ bind(inc); | |
| 304 | 2946 __ increment(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2947 __ bind(done); |
| 2948 %} | |
| 2949 | |
| 2950 // Compare the longs and set flags | |
| 2951 // BROKEN! Do Not use as-is | |
| 2952 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2953 // CMP $src1.hi,$src2.hi | |
| 2954 emit_opcode( cbuf, 0x3B ); | |
| 2955 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2956 // JNE,s done | |
| 2957 emit_opcode(cbuf,0x75); | |
| 2958 emit_d8(cbuf, 2 ); | |
| 2959 // CMP $src1.lo,$src2.lo | |
| 2960 emit_opcode( cbuf, 0x3B ); | |
| 2961 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2962 // done: | |
| 2963 %} | |
| 2964 | |
| 2965 enc_class convert_int_long( regL dst, eRegI src ) %{ | |
| 2966 // mov $dst.lo,$src | |
| 2967 int dst_encoding = $dst$$reg; | |
| 2968 int src_encoding = $src$$reg; | |
| 2969 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2970 // mov $dst.hi,$src | |
| 2971 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2972 // sar $dst.hi,31 | |
| 2973 emit_opcode( cbuf, 0xC1 ); | |
| 2974 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2975 emit_d8(cbuf, 0x1F ); | |
| 2976 %} | |
| 2977 | |
| 2978 enc_class convert_long_double( eRegL src ) %{ | |
| 2979 // push $src.hi | |
| 2980 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2981 // push $src.lo | |
| 2982 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2983 // fild 64-bits at [SP] | |
| 2984 emit_opcode(cbuf,0xdf); | |
| 2985 emit_d8(cbuf, 0x6C); | |
| 2986 emit_d8(cbuf, 0x24); | |
| 2987 emit_d8(cbuf, 0x00); | |
| 2988 // pop stack | |
| 2989 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2990 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2991 emit_d8(cbuf, 0x8); | |
| 2992 %} | |
| 2993 | |
| 2994 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2995 // IMUL EDX:EAX,$src1 | |
| 2996 emit_opcode( cbuf, 0xF7 ); | |
| 2997 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2998 // SAR EDX,$cnt-32 | |
| 2999 int shift_count = ((int)$cnt$$constant) - 32; | |
| 3000 if (shift_count > 0) { | |
| 3001 emit_opcode(cbuf, 0xC1); | |
| 3002 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 3003 emit_d8(cbuf, shift_count); | |
| 3004 } | |
| 3005 %} | |
| 3006 | |
| 3007 // this version doesn't have add sp, 8 | |
| 3008 enc_class convert_long_double2( eRegL src ) %{ | |
| 3009 // push $src.hi | |
| 3010 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 3011 // push $src.lo | |
| 3012 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 3013 // fild 64-bits at [SP] | |
| 3014 emit_opcode(cbuf,0xdf); | |
| 3015 emit_d8(cbuf, 0x6C); | |
| 3016 emit_d8(cbuf, 0x24); | |
| 3017 emit_d8(cbuf, 0x00); | |
| 3018 %} | |
| 3019 | |
| 3020 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3021 // Basic idea: long = (long)int * (long)int | |
| 3022 // IMUL EDX:EAX, src | |
| 3023 emit_opcode( cbuf, 0xF7 ); | |
| 3024 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 3025 %} | |
| 3026 | |
| 3027 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3028 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 3029 // MUL EDX:EAX, src | |
| 3030 emit_opcode( cbuf, 0xF7 ); | |
| 3031 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 3032 %} | |
| 3033 | |
| 3034 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ | |
| 3035 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 3036 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 3037 // MOV $tmp,$src.lo | |
| 3038 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 3039 // IMUL $tmp,EDX | |
| 3040 emit_opcode( cbuf, 0x0F ); | |
| 3041 emit_opcode( cbuf, 0xAF ); | |
| 3042 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3043 // MOV EDX,$src.hi | |
| 3044 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 3045 // IMUL EDX,EAX | |
| 3046 emit_opcode( cbuf, 0x0F ); | |
| 3047 emit_opcode( cbuf, 0xAF ); | |
| 3048 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 3049 // ADD $tmp,EDX | |
| 3050 emit_opcode( cbuf, 0x03 ); | |
| 3051 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3052 // MUL EDX:EAX,$src.lo | |
| 3053 emit_opcode( cbuf, 0xF7 ); | |
| 3054 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 3055 // ADD EDX,ESI | |
| 3056 emit_opcode( cbuf, 0x03 ); | |
| 3057 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 3058 %} | |
| 3059 | |
| 3060 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ | |
| 3061 // Basic idea: lo(result) = lo(src * y_lo) | |
| 3062 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 3063 // IMUL $tmp,EDX,$src | |
| 3064 emit_opcode( cbuf, 0x6B ); | |
| 3065 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3066 emit_d8( cbuf, (int)$src$$constant ); | |
| 3067 // MOV EDX,$src | |
| 3068 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 3069 emit_d32( cbuf, (int)$src$$constant ); | |
| 3070 // MUL EDX:EAX,EDX | |
| 3071 emit_opcode( cbuf, 0xF7 ); | |
| 3072 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 3073 // ADD EDX,ESI | |
| 3074 emit_opcode( cbuf, 0x03 ); | |
| 3075 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 3076 %} | |
| 3077 | |
| 3078 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 3079 // PUSH src1.hi | |
| 3080 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3081 // PUSH src1.lo | |
| 3082 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3083 // PUSH src2.hi | |
| 3084 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3085 // PUSH src2.lo | |
| 3086 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3087 // CALL directly to the runtime | |
| 1748 | 3088 cbuf.set_insts_mark(); |
| 0 | 3089 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3090 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3091 // Restore stack |
| 3092 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3093 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3094 emit_d8(cbuf, 4*4); | |
| 3095 %} | |
| 3096 | |
| 3097 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 3098 // PUSH src1.hi | |
| 3099 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3100 // PUSH src1.lo | |
| 3101 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3102 // PUSH src2.hi | |
| 3103 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3104 // PUSH src2.lo | |
| 3105 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3106 // CALL directly to the runtime | |
| 1748 | 3107 cbuf.set_insts_mark(); |
| 0 | 3108 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3109 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3110 // Restore stack |
| 3111 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3112 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3113 emit_d8(cbuf, 4*4); | |
| 3114 %} | |
| 3115 | |
| 3116 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ | |
| 3117 // MOV $tmp,$src.lo | |
| 3118 emit_opcode(cbuf, 0x8B); | |
| 3119 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 3120 // OR $tmp,$src.hi | |
| 3121 emit_opcode(cbuf, 0x0B); | |
| 3122 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 3123 %} | |
| 3124 | |
| 3125 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 3126 // CMP $src1.lo,$src2.lo | |
| 3127 emit_opcode( cbuf, 0x3B ); | |
| 3128 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3129 // JNE,s skip | |
| 3130 emit_cc(cbuf, 0x70, 0x5); | |
| 3131 emit_d8(cbuf,2); | |
| 3132 // CMP $src1.hi,$src2.hi | |
| 3133 emit_opcode( cbuf, 0x3B ); | |
| 3134 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 3135 %} | |
| 3136 | |
| 3137 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 3138 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits | |
| 3139 emit_opcode( cbuf, 0x3B ); | |
| 3140 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3141 // MOV $tmp,$src1.hi | |
| 3142 emit_opcode( cbuf, 0x8B ); | |
| 3143 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 3144 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 3145 emit_opcode( cbuf, 0x1B ); | |
| 3146 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 3147 %} | |
| 3148 | |
| 3149 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ | |
| 3150 // XOR $tmp,$tmp | |
| 3151 emit_opcode(cbuf,0x33); // XOR | |
| 3152 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 3153 // CMP $tmp,$src.lo | |
| 3154 emit_opcode( cbuf, 0x3B ); | |
| 3155 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 3156 // SBB $tmp,$src.hi | |
| 3157 emit_opcode( cbuf, 0x1B ); | |
| 3158 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 3159 %} | |
| 3160 | |
| 3161 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 3162 enc_class neg_long( eRegL dst ) %{ | |
| 3163 emit_opcode(cbuf,0xF7); // NEG hi | |
| 3164 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3165 emit_opcode(cbuf,0xF7); // NEG lo | |
| 3166 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 3167 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 3168 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3169 emit_d8 (cbuf,0 ); | |
| 3170 %} | |
| 3171 | |
| 3172 enc_class movq_ld(regXD dst, memory mem) %{ | |
| 3173 MacroAssembler _masm(&cbuf); | |
| 624 | 3174 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3175 %} |
| 3176 | |
| 3177 enc_class movq_st(memory mem, regXD src) %{ | |
| 3178 MacroAssembler _masm(&cbuf); | |
| 624 | 3179 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3180 %} |
| 3181 | |
| 3182 enc_class pshufd_8x8(regX dst, regX src) %{ | |
| 3183 MacroAssembler _masm(&cbuf); | |
| 3184 | |
| 3185 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3186 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3187 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3188 %} | |
| 3189 | |
| 3190 enc_class pshufd_4x16(regX dst, regX src) %{ | |
| 3191 MacroAssembler _masm(&cbuf); | |
| 3192 | |
| 3193 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3194 %} | |
| 3195 | |
| 3196 enc_class pshufd(regXD dst, regXD src, int mode) %{ | |
| 3197 MacroAssembler _masm(&cbuf); | |
| 3198 | |
| 3199 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3200 %} | |
| 3201 | |
| 3202 enc_class pxor(regXD dst, regXD src) %{ | |
| 3203 MacroAssembler _masm(&cbuf); | |
| 3204 | |
| 3205 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3206 %} | |
| 3207 | |
| 3208 enc_class mov_i2x(regXD dst, eRegI src) %{ | |
| 3209 MacroAssembler _masm(&cbuf); | |
| 3210 | |
| 304 | 3211 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); |
| 0 | 3212 %} |
| 3213 | |
| 3214 | |
| 3215 // Because the transitions from emitted code to the runtime | |
| 3216 // monitorenter/exit helper stubs are so slow it's critical that | |
| 3217 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 3218 // | |
| 3219 // See also: cmpFastLock and cmpFastUnlock. | |
| 3220 // | |
| 3221 // What follows is a specialized inline transliteration of the code | |
| 3222 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 3223 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 3224 // at startup-time. These methods would accept arguments as | |
| 3225 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 3226 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 3227 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 3228 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 3229 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 3230 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 3231 // Since the helper routines would be called from multiple synchronization | |
| 3232 // sites. | |
| 3233 // | |
| 3234 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 3235 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 3236 // to those specialized methods. That'd give us a mostly platform-independent | |
| 3237 // implementation that the JITs could optimize and inline at their pleasure. | |
| 3238 // Done correctly, the only time we'd need to cross to native could would be | |
| 3239 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 3240 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 3241 // (b) explicit barriers or fence operations. | |
| 3242 // | |
| 3243 // TODO: | |
| 3244 // | |
| 3245 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 3246 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 3247 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 3248 // the lock operators would typically be faster than reifying Self. | |
| 3249 // | |
| 3250 // * Ideally I'd define the primitives as: | |
| 3251 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 3252 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 3253 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 3254 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 3255 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 3256 // sub-optimal code near the synchronization site. | |
| 3257 // | |
| 3258 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 3259 // Alternately, use a better sp-proximity test. | |
| 3260 // | |
| 3261 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 3262 // Either one is sufficient to uniquely identify a thread. | |
| 3263 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 3264 // | |
| 3265 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 3266 // object is locked by the calling thread but the waitlist is empty. | |
| 3267 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 3268 // | |
| 3269 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 3270 // But beware of excessive branch density on AMD Opterons. | |
| 3271 // | |
| 3272 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 3273 // or failure of the fast-path. If the fast-path fails then we pass | |
| 3274 // control to the slow-path, typically in C. In Fast_Lock and | |
| 3275 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 3276 // will emit a conditional branch immediately after the node. | |
| 3277 // So we have branches to branches and lots of ICC.ZF games. | |
| 3278 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3279 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3280 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3281 // In the case of failure, the node will branch directly to the | |
| 3282 // FailureLabel | |
| 3283 | |
| 3284 | |
| 3285 // obj: object to lock | |
| 3286 // box: on-stack box address (displaced header location) - KILLED | |
| 3287 // rax,: tmp -- KILLED | |
| 3288 // scr: tmp -- KILLED | |
| 3289 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3290 | |
| 3291 Register objReg = as_Register($obj$$reg); | |
| 3292 Register boxReg = as_Register($box$$reg); | |
| 3293 Register tmpReg = as_Register($tmp$$reg); | |
| 3294 Register scrReg = as_Register($scr$$reg); | |
| 3295 | |
| 3296 // Ensure the register assignents are disjoint | |
| 3297 guarantee (objReg != boxReg, "") ; | |
| 3298 guarantee (objReg != tmpReg, "") ; | |
| 3299 guarantee (objReg != scrReg, "") ; | |
| 3300 guarantee (boxReg != tmpReg, "") ; | |
| 3301 guarantee (boxReg != scrReg, "") ; | |
| 3302 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3303 | |
| 3304 MacroAssembler masm(&cbuf); | |
| 3305 | |
| 3306 if (_counters != NULL) { | |
| 3307 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3308 } | |
| 3309 if (EmitSync & 1) { | |
| 3310 // set box->dhw = unused_mark (3) | |
| 304 | 3311 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3312 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3313 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3314 } else | |
| 3315 if (EmitSync & 2) { | |
| 3316 Label DONE_LABEL ; | |
| 0 | 3317 if (UseBiasedLocking) { |
| 3318 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3319 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3320 } | |
| 3321 | |
| 304 | 3322 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3323 masm.orptr (tmpReg, 0x1); | |
| 3324 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3325 if (os::is_MP()) { masm.lock(); } |
| 304 | 3326 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3327 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3328 // Recursive locking | |
| 304 | 3329 masm.subptr(tmpReg, rsp); |
| 3330 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3331 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3332 masm.bind(DONE_LABEL) ; | |
| 3333 } else { | |
| 3334 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3335 // ------------------------------------------------ |
| 3336 // * Inflated | |
| 3337 // -- unlocked | |
| 3338 // -- Locked | |
| 3339 // = by self | |
| 3340 // = by other | |
| 3341 // * biased | |
| 3342 // -- by Self | |
| 3343 // -- by other | |
| 3344 // * neutral | |
| 3345 // * stack-locked | |
| 3346 // -- by self | |
| 3347 // = sp-proximity test hits | |
| 3348 // = sp-proximity test generates false-negative | |
| 3349 // -- by other | |
| 3350 // | |
| 3351 | |
| 3352 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3353 | |
| 3354 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3355 // order to reduce the number of conditional branches in the most common cases. | |
| 3356 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3357 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3358 // If this invariant is not held we risk exclusion (safety) failure. | |
|
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3359 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3360 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3361 } | |
| 3362 | |
| 304 | 3363 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3364 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3365 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3366 | |
| 3367 // Attempt stack-locking ... | |
| 304 | 3368 masm.orptr (tmpReg, 0x1); |
| 3369 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3370 if (os::is_MP()) { masm.lock(); } |
| 304 | 3371 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3372 if (_counters != NULL) { |
| 3373 masm.cond_inc32(Assembler::equal, | |
| 3374 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3375 } | |
| 3376 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3377 | |
| 3378 // Recursive locking | |
| 304 | 3379 masm.subptr(tmpReg, rsp); |
| 3380 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3381 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3382 if (_counters != NULL) { |
| 3383 masm.cond_inc32(Assembler::equal, | |
| 3384 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3385 } | |
| 3386 masm.jmp (DONE_LABEL) ; | |
| 3387 | |
| 3388 masm.bind (IsInflated) ; | |
| 3389 | |
| 3390 // The object is inflated. | |
| 3391 // | |
| 3392 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3393 // Use markOopDesc::monitor_value instead of "2". | |
| 3394 // use markOop::unused_mark() instead of "3". | |
| 3395 // The tmpReg value is an objectMonitor reference ORed with | |
| 3396 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3397 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3398 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3399 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3400 // | |
| 3401 // I use the latter as it avoids AGI stalls. | |
| 3402 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3403 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3404 // | |
| 3405 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3406 | |
| 3407 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3408 // We'd like to write: | |
| 3409 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3410 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3411 // additional latency as we have another ST in the store buffer that must drain. | |
| 3412 | |
| 304 | 3413 if (EmitSync & 8192) { |
| 3414 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3415 masm.get_thread (scrReg) ; | |
| 3416 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
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3417 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3418 if (os::is_MP()) { masm.lock(); } |
| 3419 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3420 } else | |
| 0 | 3421 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3422 masm.movptr(scrReg, boxReg) ; |
| 3423 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3424 |
| 3425 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3426 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3427 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3428 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3429 } |
| 3430 | |
| 3431 if ((EmitSync & 64) == 0) { | |
| 3432 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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|
3433 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3434 } else { |
| 0 | 3435 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3436 // Test-And-CAS instead of CAS | |
| 304 | 3437 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3438 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3439 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3440 } |
| 3441 | |
| 3442 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3443 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3444 // to CAS the register containing Self into m->Owner. | |
| 3445 // But we don't have enough registers, so instead we can either try to CAS | |
| 3446 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3447 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3448 // (rsp or the address of the box) into m->owner is harmless. | |
| 3449 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3450 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3451 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3452 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3453 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3454 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3455 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3456 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3457 | |
| 3458 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3459 // We use the latter tactic. | |
| 0 | 3460 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3461 // If the CAS was successful ... | |
| 3462 // Self has acquired the lock | |
| 3463 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3464 // Intentional fall-through into DONE_LABEL ... | |
| 3465 } else { | |
| 304 | 3466 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3467 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3468 |
| 3469 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3470 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3471 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3472 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3473 } |
| 3474 | |
| 3475 if ((EmitSync & 64) == 0) { | |
| 3476 // Optimistic form | |
| 304 | 3477 masm.xorptr (tmpReg, tmpReg) ; |
| 3478 } else { | |
| 0 | 3479 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3480 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3481 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3482 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3483 } |
| 3484 | |
| 3485 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3486 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3487 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3488 masm.get_thread (scrReg) ; | |
| 3489 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3490 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3491 |
| 3492 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3493 // We use the latter tactic. | |
| 3494 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3495 // If the CAS was successful ... | |
| 3496 // Self has acquired the lock | |
| 3497 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3498 // Intentional fall-through into DONE_LABEL ... | |
| 3499 } | |
| 3500 | |
| 3501 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3502 // start of cache line by padding with NOPs. | |
| 3503 // See the AMD and Intel software optimization manuals for the | |
| 3504 // most efficient "long" NOP encodings. | |
| 3505 // Unfortunately none of our alignment mechanisms suffice. | |
| 3506 masm.bind(DONE_LABEL); | |
| 3507 | |
| 3508 // Avoid branch-to-branch on AMD processors | |
| 3509 // This appears to be superstition. | |
| 3510 if (EmitSync & 32) masm.nop() ; | |
| 3511 | |
| 3512 | |
| 3513 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3514 // Fast_Unlock uses the same protocol. | |
| 3515 // ZFlag == 1 -> Success | |
| 3516 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3517 } | |
| 3518 %} | |
| 3519 | |
| 3520 // obj: object to unlock | |
| 3521 // box: box address (displaced header location), killed. Must be EAX. | |
| 3522 // rbx,: killed tmp; cannot be obj nor box. | |
| 3523 // | |
| 3524 // Some commentary on balanced locking: | |
| 3525 // | |
| 3526 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3527 // Methods that don't have provably balanced locking are forced to run in the | |
| 3528 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3529 // The interpreter provides two properties: | |
| 3530 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3531 // objects acquired the current activation (frame). Recall that the | |
| 3532 // interpreter maintains an on-stack list of locks currently held by | |
| 3533 // a frame. | |
| 3534 // I2: If a method attempts to unlock an object that is not held by the | |
| 3535 // the frame the interpreter throws IMSX. | |
| 3536 // | |
| 3537 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3538 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3539 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3540 // is still locked by A(). | |
| 3541 // | |
| 3542 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3543 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3544 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3545 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3546 | |
| 3547 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3548 | |
| 3549 Register objReg = as_Register($obj$$reg); | |
| 3550 Register boxReg = as_Register($box$$reg); | |
| 3551 Register tmpReg = as_Register($tmp$$reg); | |
| 3552 | |
| 3553 guarantee (objReg != boxReg, "") ; | |
| 3554 guarantee (objReg != tmpReg, "") ; | |
| 3555 guarantee (boxReg != tmpReg, "") ; | |
| 3556 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3557 MacroAssembler masm(&cbuf); | |
| 3558 | |
| 3559 if (EmitSync & 4) { | |
| 3560 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3561 masm.cmpptr (rsp, 0) ; |
| 3562 } else | |
| 0 | 3563 if (EmitSync & 8) { |
| 3564 Label DONE_LABEL ; | |
| 3565 if (UseBiasedLocking) { | |
| 3566 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3567 } | |
| 3568 // classic stack-locking code ... | |
| 304 | 3569 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3570 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3571 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3572 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3573 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3574 masm.bind(DONE_LABEL); |
| 3575 } else { | |
| 3576 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3577 | |
| 3578 // Critically, the biased locking test must have precedence over | |
| 3579 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3580 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3581 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3582 } | |
| 304 | 3583 |
| 3584 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3585 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3586 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3587 | |
| 304 | 3588 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3589 masm.jccb (Assembler::zero, Stacked) ; |
| 3590 | |
| 3591 masm.bind (Inflated) ; | |
| 3592 // It's inflated. | |
| 3593 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3594 // as java routines or native JNI code called by this thread might | |
| 3595 // have released the lock. | |
| 3596 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3597 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3598 // | |
| 3599 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3600 // such as recursive enter and exit -- but we have to be wary of | |
| 3601 // I$ bloat, T$ effects and BP$ effects. | |
| 3602 // | |
| 3603 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3604 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3605 // we detect and recover from the race that the 1-0 exit admits. | |
| 3606 // | |
| 3607 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3608 // before it STs null into _owner, releasing the lock. Updates | |
| 3609 // to data protected by the critical section must be visible before | |
| 3610 // we drop the lock (and thus before any other thread could acquire | |
| 3611 // the lock and observe the fields protected by the lock). | |
| 3612 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3613 // each other and there's no need for an explicit barrier (fence). | |
| 3614 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3615 | |
| 3616 masm.get_thread (boxReg) ; | |
| 2479 | 3617 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 304 | 3618 // prefetchw [ebx + Offset(_owner)-2] |
| 3619 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3620 } |
| 3621 | |
| 3622 // Note that we could employ various encoding schemes to reduce | |
| 3623 // the number of loads below (currently 4) to just 2 or 3. | |
| 3624 // Refer to the comments in synchronizer.cpp. | |
| 3625 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3626 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3627 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3628 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3629 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3630 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3631 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3632 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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3633 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3634 masm.jmpb (DONE_LABEL) ; |
| 3635 } else { | |
| 3636 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3637 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3638 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3639 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3640 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3641 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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3642 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3643 masm.jmpb (DONE_LABEL) ; |
| 0 | 3644 } |
| 3645 | |
| 3646 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3647 // contended applications and contended synchronization microbenchmarks. | |
| 3648 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3649 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3650 // with an equal number of never-executed NOPs results in the same regression. | |
| 3651 // We leave it off by default. | |
| 3652 | |
| 3653 if ((EmitSync & 65536) != 0) { | |
| 3654 Label LSuccess, LGoSlowPath ; | |
| 3655 | |
| 3656 masm.bind (CheckSucc) ; | |
| 3657 | |
| 3658 // Optional pre-test ... it's safe to elide this | |
| 304 | 3659 if ((EmitSync & 16) == 0) { |
| 3660 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3661 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3662 } |
| 3663 | |
| 3664 // We have a classic Dekker-style idiom: | |
| 3665 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3666 // There are a number of ways to implement the barrier: | |
| 3667 // (1) lock:andl &m->_owner, 0 | |
| 3668 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3669 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3670 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3671 // (2) If supported, an explicit MFENCE is appealing. | |
| 3672 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3673 // particularly if the write-buffer is full as might be the case if | |
| 3674 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3675 // In more modern implementations MFENCE appears faster, however. | |
| 3676 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3677 // The $lines underlying the top-of-stack should be in M-state. | |
| 3678 // The locked add instruction is serializing, of course. | |
| 3679 // (4) Use xchg, which is serializing | |
| 3680 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3681 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3682 // The integer condition codes will tell us if succ was 0. | |
| 3683 // Since _succ and _owner should reside in the same $line and | |
| 3684 // we just stored into _owner, it's likely that the $line | |
| 3685 // remains in M-state for the lock:orl. | |
| 3686 // | |
| 3687 // We currently use (3), although it's likely that switching to (2) | |
| 3688 // is correct for the future. | |
| 304 | 3689 |
|
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|
3690 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3691 if (os::is_MP()) { |
| 3692 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3693 masm.mfence(); | |
| 3694 } else { | |
| 3695 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3696 } |
| 3697 } | |
| 3698 // Ratify _succ remains non-null | |
| 304 | 3699 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3700 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3701 | |
| 3702 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3703 if (os::is_MP()) { masm.lock(); } |
| 304 | 3704 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3705 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3706 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3707 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3708 // non-null to non=null | |
| 3709 masm.get_thread (boxReg) ; | |
| 304 | 3710 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3711 // Intentional fall-through into LGoSlowPath ... |
| 3712 | |
| 304 | 3713 masm.bind (LGoSlowPath) ; |
| 3714 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3715 masm.jmpb (DONE_LABEL) ; | |
| 3716 | |
| 3717 masm.bind (LSuccess) ; | |
| 3718 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3719 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3720 } |
| 3721 | |
| 3722 masm.bind (Stacked) ; | |
| 3723 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3724 // It must be stack-locked. | |
| 3725 // Try to reset the header to displaced header. | |
| 3726 // The "box" value on the stack is stable, so we can reload | |
| 3727 // and be assured we observe the same value as above. | |
| 304 | 3728 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3729 if (os::is_MP()) { masm.lock(); } |
| 304 | 3730 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3731 // Intention fall-thru into DONE_LABEL |
| 3732 | |
| 3733 | |
| 3734 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3735 // start of cache line by padding with NOPs. | |
| 3736 // See the AMD and Intel software optimization manuals for the | |
| 3737 // most efficient "long" NOP encodings. | |
| 3738 // Unfortunately none of our alignment mechanisms suffice. | |
| 3739 if ((EmitSync & 65536) == 0) { | |
| 3740 masm.bind (CheckSucc) ; | |
| 3741 } | |
| 3742 masm.bind(DONE_LABEL); | |
| 3743 | |
| 3744 // Avoid branch to branch on AMD processors | |
| 3745 if (EmitSync & 32768) { masm.nop() ; } | |
| 3746 } | |
| 3747 %} | |
| 3748 | |
|
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|
3749 |
| 0 | 3750 enc_class enc_pop_rdx() %{ |
| 3751 emit_opcode(cbuf,0x5A); | |
| 3752 %} | |
| 3753 | |
| 3754 enc_class enc_rethrow() %{ | |
| 1748 | 3755 cbuf.set_insts_mark(); |
| 0 | 3756 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3757 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3758 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3759 %} | |
| 3760 | |
| 3761 | |
| 3762 // Convert a double to an int. Java semantics require we do complex | |
| 3763 // manglelations in the corner cases. So we set the rounding mode to | |
| 3764 // 'zero', store the darned double down as an int, and reset the | |
| 3765 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3766 // patches up the correct value directly to the stack. | |
| 3767 enc_class D2I_encoding( regD src ) %{ | |
| 3768 // Flip to round-to-zero mode. We attempted to allow invalid-op | |
| 3769 // exceptions here, so that a NAN or other corner-case value will | |
| 3770 // thrown an exception (but normal values get converted at full speed). | |
| 3771 // However, I2C adapters and other float-stack manglers leave pending | |
| 3772 // invalid-op exceptions hanging. We would have to clear them before | |
| 3773 // enabling them and that is more expensive than just testing for the | |
| 3774 // invalid value Intel stores down in the corner cases. | |
| 3775 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3776 emit_opcode(cbuf,0x2D); | |
| 3777 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3778 // Allocate a word | |
| 3779 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3780 emit_opcode(cbuf,0xEC); | |
| 3781 emit_d8(cbuf,0x04); | |
| 3782 // Encoding assumes a double has been pushed into FPR0. | |
| 3783 // Store down the double as an int, popping the FPU stack | |
| 3784 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3785 emit_opcode(cbuf,0x1C); | |
| 3786 emit_d8(cbuf,0x24); | |
| 3787 // Restore the rounding mode; mask the exception | |
| 3788 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3789 emit_opcode(cbuf,0x2D); | |
| 3790 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3791 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3792 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3793 | |
| 3794 // Load the converted int; adjust CPU stack | |
| 3795 emit_opcode(cbuf,0x58); // POP EAX | |
| 3796 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3797 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3798 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3799 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3800 // Push src onto stack slow-path | |
| 3801 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3802 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3803 // CALL directly to the runtime | |
| 1748 | 3804 cbuf.set_insts_mark(); |
| 0 | 3805 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3806 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3807 // Carry on here... |
| 3808 %} | |
| 3809 | |
| 3810 enc_class D2L_encoding( regD src ) %{ | |
| 3811 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3812 emit_opcode(cbuf,0x2D); | |
| 3813 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3814 // Allocate a word | |
| 3815 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3816 emit_opcode(cbuf,0xEC); | |
| 3817 emit_d8(cbuf,0x08); | |
| 3818 // Encoding assumes a double has been pushed into FPR0. | |
| 3819 // Store down the double as a long, popping the FPU stack | |
| 3820 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3821 emit_opcode(cbuf,0x3C); | |
| 3822 emit_d8(cbuf,0x24); | |
| 3823 // Restore the rounding mode; mask the exception | |
| 3824 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3825 emit_opcode(cbuf,0x2D); | |
| 3826 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3827 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3828 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3829 | |
| 3830 // Load the converted int; adjust CPU stack | |
| 3831 emit_opcode(cbuf,0x58); // POP EAX | |
| 3832 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3833 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3834 emit_d8 (cbuf,0xFA); // rdx | |
| 3835 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3836 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3837 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3838 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3839 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3840 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3841 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3842 // Push src onto stack slow-path | |
| 3843 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3844 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3845 // CALL directly to the runtime | |
| 1748 | 3846 cbuf.set_insts_mark(); |
| 0 | 3847 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3848 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3849 // Carry on here... |
| 3850 %} | |
| 3851 | |
| 3852 enc_class X2L_encoding( regX src ) %{ | |
| 3853 // Allocate a word | |
| 3854 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3855 emit_opcode(cbuf,0xEC); | |
| 3856 emit_d8(cbuf,0x08); | |
| 3857 | |
| 3858 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3859 emit_opcode (cbuf, 0x0F ); | |
| 3860 emit_opcode (cbuf, 0x11 ); | |
| 3861 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3862 | |
| 3863 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3864 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3865 | |
| 3866 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3867 emit_opcode(cbuf,0x2D); | |
| 3868 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3869 | |
| 3870 // Encoding assumes a double has been pushed into FPR0. | |
| 3871 // Store down the double as a long, popping the FPU stack | |
| 3872 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3873 emit_opcode(cbuf,0x3C); | |
| 3874 emit_d8(cbuf,0x24); | |
| 3875 | |
| 3876 // Restore the rounding mode; mask the exception | |
| 3877 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3878 emit_opcode(cbuf,0x2D); | |
| 3879 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3880 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3881 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3882 | |
| 3883 // Load the converted int; adjust CPU stack | |
| 3884 emit_opcode(cbuf,0x58); // POP EAX | |
| 3885 | |
| 3886 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3887 | |
| 3888 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3889 emit_d8 (cbuf,0xFA); // rdx | |
| 3890 emit_d32 (cbuf,0x80000000);// 0x80000000 | |
| 3891 | |
| 3892 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3893 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3894 | |
| 3895 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3896 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3897 | |
| 3898 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3899 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3900 | |
| 3901 // Allocate a word | |
| 3902 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3903 emit_opcode(cbuf,0xEC); | |
| 3904 emit_d8(cbuf,0x04); | |
| 3905 | |
| 3906 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3907 emit_opcode (cbuf, 0x0F ); | |
| 3908 emit_opcode (cbuf, 0x11 ); | |
| 3909 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3910 | |
| 3911 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3912 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3913 | |
| 3914 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 3915 emit_opcode(cbuf,0xC4); | |
| 3916 emit_d8(cbuf,0x04); | |
| 3917 | |
| 3918 // CALL directly to the runtime | |
| 1748 | 3919 cbuf.set_insts_mark(); |
| 0 | 3920 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3921 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3922 // Carry on here... |
| 3923 %} | |
| 3924 | |
| 3925 enc_class XD2L_encoding( regXD src ) %{ | |
| 3926 // Allocate a word | |
| 3927 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3928 emit_opcode(cbuf,0xEC); | |
| 3929 emit_d8(cbuf,0x08); | |
| 3930 | |
| 3931 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 3932 emit_opcode (cbuf, 0x0F ); | |
| 3933 emit_opcode (cbuf, 0x11 ); | |
| 3934 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3935 | |
| 3936 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 3937 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3938 | |
| 3939 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3940 emit_opcode(cbuf,0x2D); | |
| 3941 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3942 | |
| 3943 // Encoding assumes a double has been pushed into FPR0. | |
| 3944 // Store down the double as a long, popping the FPU stack | |
| 3945 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3946 emit_opcode(cbuf,0x3C); | |
| 3947 emit_d8(cbuf,0x24); | |
| 3948 | |
| 3949 // Restore the rounding mode; mask the exception | |
| 3950 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3951 emit_opcode(cbuf,0x2D); | |
| 3952 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3953 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3954 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3955 | |
| 3956 // Load the converted int; adjust CPU stack | |
| 3957 emit_opcode(cbuf,0x58); // POP EAX | |
| 3958 | |
| 3959 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3960 | |
| 3961 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3962 emit_d8 (cbuf,0xFA); // rdx | |
| 3963 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3964 | |
| 3965 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3966 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3967 | |
| 3968 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3969 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3970 | |
| 3971 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3972 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3973 | |
| 3974 // Push src onto stack slow-path | |
| 3975 // Allocate a word | |
| 3976 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3977 emit_opcode(cbuf,0xEC); | |
| 3978 emit_d8(cbuf,0x08); | |
| 3979 | |
| 3980 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 3981 emit_opcode (cbuf, 0x0F ); | |
| 3982 emit_opcode (cbuf, 0x11 ); | |
| 3983 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3984 | |
| 3985 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 3986 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3987 | |
| 3988 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 3989 emit_opcode(cbuf,0xC4); | |
| 3990 emit_d8(cbuf,0x08); | |
| 3991 | |
| 3992 // CALL directly to the runtime | |
| 1748 | 3993 cbuf.set_insts_mark(); |
| 0 | 3994 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3995 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3996 // Carry on here... |
| 3997 %} | |
| 3998 | |
| 3999 enc_class D2X_encoding( regX dst, regD src ) %{ | |
| 4000 // Allocate a word | |
| 4001 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4002 emit_opcode(cbuf,0xEC); | |
| 4003 emit_d8(cbuf,0x04); | |
| 4004 int pop = 0x02; | |
| 4005 if ($src$$reg != FPR1L_enc) { | |
| 4006 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 4007 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 4008 pop = 0x03; | |
| 4009 } | |
| 4010 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] | |
| 4011 | |
| 4012 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 4013 emit_opcode (cbuf, 0x0F ); | |
| 4014 emit_opcode (cbuf, 0x10 ); | |
| 4015 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4016 | |
| 4017 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4018 emit_opcode(cbuf,0xC4); | |
| 4019 emit_d8(cbuf,0x04); | |
| 4020 // Carry on here... | |
| 4021 %} | |
| 4022 | |
| 4023 enc_class FX2I_encoding( regX src, eRegI dst ) %{ | |
| 4024 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 4025 | |
| 4026 // Compare the result to see if we need to go to the slow path | |
| 4027 emit_opcode(cbuf,0x81); // CMP dst,imm | |
| 4028 emit_rm (cbuf,0x3,0x7,$dst$$reg); | |
| 4029 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 4030 | |
| 4031 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4032 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4033 // Store xmm to a temp memory | |
| 4034 // location and push it onto stack. | |
| 4035 | |
| 4036 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4037 emit_opcode(cbuf,0xEC); | |
| 4038 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4039 | |
| 4040 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm | |
| 4041 emit_opcode (cbuf, 0x0F ); | |
| 4042 emit_opcode (cbuf, 0x11 ); | |
| 4043 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4044 | |
| 4045 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] | |
| 4046 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4047 | |
| 4048 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4049 emit_opcode(cbuf,0xC4); | |
| 4050 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4051 | |
| 4052 // CALL directly to the runtime | |
| 1748 | 4053 cbuf.set_insts_mark(); |
| 0 | 4054 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 4055 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 4056 |
| 4057 // Carry on here... | |
| 4058 %} | |
| 4059 | |
| 4060 enc_class X2D_encoding( regD dst, regX src ) %{ | |
| 4061 // Allocate a word | |
| 4062 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4063 emit_opcode(cbuf,0xEC); | |
| 4064 emit_d8(cbuf,0x04); | |
| 4065 | |
| 4066 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm | |
| 4067 emit_opcode (cbuf, 0x0F ); | |
| 4068 emit_opcode (cbuf, 0x11 ); | |
| 4069 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4070 | |
| 4071 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 4072 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4073 | |
| 4074 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4075 emit_opcode(cbuf,0xC4); | |
| 4076 emit_d8(cbuf,0x04); | |
| 4077 | |
| 4078 // Carry on here... | |
| 4079 %} | |
| 4080 | |
| 4081 enc_class AbsXF_encoding(regX dst) %{ | |
| 4082 address signmask_address=(address)float_signmask_pool; | |
| 4083 // andpd:\tANDPS $dst,[signconst] | |
| 4084 emit_opcode(cbuf, 0x0F); | |
| 4085 emit_opcode(cbuf, 0x54); | |
| 4086 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4087 emit_d32(cbuf, (int)signmask_address); | |
| 4088 %} | |
| 4089 | |
| 4090 enc_class AbsXD_encoding(regXD dst) %{ | |
| 4091 address signmask_address=(address)double_signmask_pool; | |
| 4092 // andpd:\tANDPD $dst,[signconst] | |
| 4093 emit_opcode(cbuf, 0x66); | |
| 4094 emit_opcode(cbuf, 0x0F); | |
| 4095 emit_opcode(cbuf, 0x54); | |
| 4096 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4097 emit_d32(cbuf, (int)signmask_address); | |
| 4098 %} | |
| 4099 | |
| 4100 enc_class NegXF_encoding(regX dst) %{ | |
| 4101 address signmask_address=(address)float_signflip_pool; | |
| 4102 // andpd:\tXORPS $dst,[signconst] | |
| 4103 emit_opcode(cbuf, 0x0F); | |
| 4104 emit_opcode(cbuf, 0x57); | |
| 4105 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4106 emit_d32(cbuf, (int)signmask_address); | |
| 4107 %} | |
| 4108 | |
| 4109 enc_class NegXD_encoding(regXD dst) %{ | |
| 4110 address signmask_address=(address)double_signflip_pool; | |
| 4111 // andpd:\tXORPD $dst,[signconst] | |
| 4112 emit_opcode(cbuf, 0x66); | |
| 4113 emit_opcode(cbuf, 0x0F); | |
| 4114 emit_opcode(cbuf, 0x57); | |
| 4115 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4116 emit_d32(cbuf, (int)signmask_address); | |
| 4117 %} | |
| 4118 | |
| 4119 enc_class FMul_ST_reg( eRegF src1 ) %{ | |
| 4120 // Operand was loaded from memory into fp ST (stack top) | |
| 4121 // FMUL ST,$src /* D8 C8+i */ | |
| 4122 emit_opcode(cbuf, 0xD8); | |
| 4123 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 4124 %} | |
| 4125 | |
| 4126 enc_class FAdd_ST_reg( eRegF src2 ) %{ | |
| 4127 // FADDP ST,src2 /* D8 C0+i */ | |
| 4128 emit_opcode(cbuf, 0xD8); | |
| 4129 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4130 //could use FADDP src2,fpST /* DE C0+i */ | |
| 4131 %} | |
| 4132 | |
| 4133 enc_class FAddP_reg_ST( eRegF src2 ) %{ | |
| 4134 // FADDP src2,ST /* DE C0+i */ | |
| 4135 emit_opcode(cbuf, 0xDE); | |
| 4136 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4137 %} | |
| 4138 | |
| 4139 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ | |
| 4140 // Operand has been loaded into fp ST (stack top) | |
| 4141 // FSUB ST,$src1 | |
| 4142 emit_opcode(cbuf, 0xD8); | |
| 4143 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 4144 | |
| 4145 // FDIV | |
| 4146 emit_opcode(cbuf, 0xD8); | |
| 4147 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 4148 %} | |
| 4149 | |
| 4150 enc_class MulFAddF (eRegF src1, eRegF src2) %{ | |
| 4151 // Operand was loaded from memory into fp ST (stack top) | |
| 4152 // FADD ST,$src /* D8 C0+i */ | |
| 4153 emit_opcode(cbuf, 0xD8); | |
| 4154 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4155 | |
| 4156 // FMUL ST,src2 /* D8 C*+i */ | |
| 4157 emit_opcode(cbuf, 0xD8); | |
| 4158 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4159 %} | |
| 4160 | |
| 4161 | |
| 4162 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ | |
| 4163 // Operand was loaded from memory into fp ST (stack top) | |
| 4164 // FADD ST,$src /* D8 C0+i */ | |
| 4165 emit_opcode(cbuf, 0xD8); | |
| 4166 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4167 | |
| 4168 // FMULP src2,ST /* DE C8+i */ | |
| 4169 emit_opcode(cbuf, 0xDE); | |
| 4170 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4171 %} | |
| 4172 | |
| 4173 // Atomically load the volatile long | |
| 4174 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 4175 emit_opcode(cbuf,0xDF); | |
| 4176 int rm_byte_opcode = 0x05; | |
| 4177 int base = $mem$$base; | |
| 4178 int index = $mem$$index; | |
| 4179 int scale = $mem$$scale; | |
| 4180 int displace = $mem$$disp; | |
| 4181 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4182 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4183 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); | |
| 4184 %} | |
| 4185 | |
| 4186 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ | |
| 4187 { // Atomic long load | |
| 4188 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4189 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4190 emit_opcode(cbuf,0x0F); | |
| 4191 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4192 int base = $mem$$base; | |
| 4193 int index = $mem$$index; | |
| 4194 int scale = $mem$$scale; | |
| 4195 int displace = $mem$$disp; | |
| 4196 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4197 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4198 } | |
| 4199 { // MOVSD $dst,$tmp ! atomic long store | |
| 4200 emit_opcode(cbuf,0xF2); | |
| 4201 emit_opcode(cbuf,0x0F); | |
| 4202 emit_opcode(cbuf,0x11); | |
| 4203 int base = $dst$$base; | |
| 4204 int index = $dst$$index; | |
| 4205 int scale = $dst$$scale; | |
| 4206 int displace = $dst$$disp; | |
| 4207 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4208 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4209 } | |
| 4210 %} | |
| 4211 | |
| 4212 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ | |
| 4213 { // Atomic long load | |
| 4214 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4215 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4216 emit_opcode(cbuf,0x0F); | |
| 4217 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4218 int base = $mem$$base; | |
| 4219 int index = $mem$$index; | |
| 4220 int scale = $mem$$scale; | |
| 4221 int displace = $mem$$disp; | |
| 4222 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4223 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4224 } | |
| 4225 { // MOVD $dst.lo,$tmp | |
| 4226 emit_opcode(cbuf,0x66); | |
| 4227 emit_opcode(cbuf,0x0F); | |
| 4228 emit_opcode(cbuf,0x7E); | |
| 4229 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); | |
| 4230 } | |
| 4231 { // PSRLQ $tmp,32 | |
| 4232 emit_opcode(cbuf,0x66); | |
| 4233 emit_opcode(cbuf,0x0F); | |
| 4234 emit_opcode(cbuf,0x73); | |
| 4235 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); | |
| 4236 emit_d8(cbuf, 0x20); | |
| 4237 } | |
| 4238 { // MOVD $dst.hi,$tmp | |
| 4239 emit_opcode(cbuf,0x66); | |
| 4240 emit_opcode(cbuf,0x0F); | |
| 4241 emit_opcode(cbuf,0x7E); | |
| 4242 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 4243 } | |
| 4244 %} | |
| 4245 | |
| 4246 // Volatile Store Long. Must be atomic, so move it into | |
| 4247 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 4248 // target address before the store (for null-ptr checks) | |
| 4249 // so the memory operand is used twice in the encoding. | |
| 4250 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 4251 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 4252 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 4253 emit_opcode(cbuf,0xDF); |
| 4254 int rm_byte_opcode = 0x07; | |
| 4255 int base = $mem$$base; | |
| 4256 int index = $mem$$index; | |
| 4257 int scale = $mem$$scale; | |
| 4258 int displace = $mem$$disp; | |
| 4259 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4260 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4261 %} | |
| 4262 | |
| 4263 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ | |
| 4264 { // Atomic long load | |
| 4265 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] | |
| 4266 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4267 emit_opcode(cbuf,0x0F); | |
| 4268 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4269 int base = $src$$base; | |
| 4270 int index = $src$$index; | |
| 4271 int scale = $src$$scale; | |
| 4272 int displace = $src$$disp; | |
| 4273 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4274 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4275 } | |
| 1748 | 4276 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop |
| 0 | 4277 { // MOVSD $mem,$tmp ! atomic long store |
| 4278 emit_opcode(cbuf,0xF2); | |
| 4279 emit_opcode(cbuf,0x0F); | |
| 4280 emit_opcode(cbuf,0x11); | |
| 4281 int base = $mem$$base; | |
| 4282 int index = $mem$$index; | |
| 4283 int scale = $mem$$scale; | |
| 4284 int displace = $mem$$disp; | |
| 4285 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4286 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4287 } | |
| 4288 %} | |
| 4289 | |
| 4290 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ | |
| 4291 { // MOVD $tmp,$src.lo | |
| 4292 emit_opcode(cbuf,0x66); | |
| 4293 emit_opcode(cbuf,0x0F); | |
| 4294 emit_opcode(cbuf,0x6E); | |
| 4295 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 4296 } | |
| 4297 { // MOVD $tmp2,$src.hi | |
| 4298 emit_opcode(cbuf,0x66); | |
| 4299 emit_opcode(cbuf,0x0F); | |
| 4300 emit_opcode(cbuf,0x6E); | |
| 4301 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 4302 } | |
| 4303 { // PUNPCKLDQ $tmp,$tmp2 | |
| 4304 emit_opcode(cbuf,0x66); | |
| 4305 emit_opcode(cbuf,0x0F); | |
| 4306 emit_opcode(cbuf,0x62); | |
| 4307 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); | |
| 4308 } | |
| 1748 | 4309 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop |
| 0 | 4310 { // MOVSD $mem,$tmp ! atomic long store |
| 4311 emit_opcode(cbuf,0xF2); | |
| 4312 emit_opcode(cbuf,0x0F); | |
| 4313 emit_opcode(cbuf,0x11); | |
| 4314 int base = $mem$$base; | |
| 4315 int index = $mem$$index; | |
| 4316 int scale = $mem$$scale; | |
| 4317 int displace = $mem$$disp; | |
| 4318 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4319 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4320 } | |
| 4321 %} | |
| 4322 | |
| 4323 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4324 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 4325 // in the process | |
| 4326 // We current use TESTL [spp],EDI | |
| 4327 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 4328 | |
| 4329 enc_class Safepoint_Poll() %{ | |
| 1748 | 4330 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 4331 emit_opcode(cbuf,0x85); |
| 4332 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 4333 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 4334 %} | |
| 4335 %} | |
| 4336 | |
| 4337 | |
| 4338 //----------FRAME-------------------------------------------------------------- | |
| 4339 // Definition of frame structure and management information. | |
| 4340 // | |
| 4341 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4342 // | (to get allocators register number | |
| 4343 // G Owned by | | v add OptoReg::stack0()) | |
| 4344 // r CALLER | | | |
| 4345 // o | +--------+ pad to even-align allocators stack-slot | |
| 4346 // w V | pad0 | numbers; owned by CALLER | |
| 4347 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4348 // h ^ | in | 5 | |
| 4349 // | | args | 4 Holes in incoming args owned by SELF | |
| 4350 // | | | | 3 | |
| 4351 // | | +--------+ | |
| 4352 // V | | old out| Empty on Intel, window on Sparc | |
| 4353 // | old |preserve| Must be even aligned. | |
| 4354 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4355 // | | in | 3 area for Intel ret address | |
| 4356 // Owned by |preserve| Empty on Sparc. | |
| 4357 // SELF +--------+ | |
| 4358 // | | pad2 | 2 pad to align old SP | |
| 4359 // | +--------+ 1 | |
| 4360 // | | locks | 0 | |
| 4361 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4362 // | | pad1 | 11 pad to align new SP | |
| 4363 // | +--------+ | |
| 4364 // | | | 10 | |
| 4365 // | | spills | 9 spills | |
| 4366 // V | | 8 (pad0 slot for callee) | |
| 4367 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4368 // ^ | out | 7 | |
| 4369 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4370 // Owned by +--------+ | |
| 4371 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4372 // | new |preserve| Must be even-aligned. | |
| 4373 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4374 // | | | | |
| 4375 // | |
| 4376 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4377 // known from SELF's arguments and the Java calling convention. | |
| 4378 // Region 6-7 is determined per call site. | |
| 4379 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4380 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4381 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4382 // incoming area, as the Java calling convention is completely under | |
| 4383 // the control of the AD file. Doubles can be sorted and packed to | |
| 4384 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4385 // varargs C calling conventions. | |
| 4386 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4387 // even aligned with pad0 as needed. | |
| 4388 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4389 // region 6-11 is even aligned; it may be padded out more so that | |
| 4390 // the region from SP to FP meets the minimum stack alignment. | |
| 4391 | |
| 4392 frame %{ | |
| 4393 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4394 stack_direction(TOWARDS_LOW); | |
| 4395 | |
| 4396 // These three registers define part of the calling convention | |
| 4397 // between compiled code and the interpreter. | |
| 4398 inline_cache_reg(EAX); // Inline Cache Register | |
| 4399 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 4400 | |
| 4401 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 4402 cisc_spilling_operand_name(indOffset32); | |
| 4403 | |
| 4404 // Number of stack slots consumed by locking an object | |
| 4405 sync_stack_slots(1); | |
| 4406 | |
| 4407 // Compiled code's Frame Pointer | |
| 4408 frame_pointer(ESP); | |
| 4409 // Interpreter stores its frame pointer in a register which is | |
| 4410 // stored to the stack by I2CAdaptors. | |
| 4411 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4412 interpreter_frame_pointer(EBP); | |
| 4413 | |
| 4414 // Stack alignment requirement | |
| 4415 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4416 stack_alignment(StackAlignmentInBytes); | |
| 4417 | |
| 4418 // Number of stack slots between incoming argument block and the start of | |
| 4419 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4420 // EPILOG must remove this many slots. Intel needs one slot for | |
| 4421 // return address and one for rbp, (must save rbp) | |
| 4422 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 4423 | |
| 4424 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4425 // for calls to C. Supports the var-args backing area for register parms. | |
| 4426 varargs_C_out_slots_killed(0); | |
| 4427 | |
| 4428 // The after-PROLOG location of the return address. Location of | |
| 4429 // return address specifies a type (REG or STACK) and a number | |
| 4430 // representing the register number (i.e. - use a register name) or | |
| 4431 // stack slot. | |
| 4432 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4433 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4434 return_addr(STACK - 1 + | |
| 4435 round_to(1+VerifyStackAtCalls+ | |
| 4436 Compile::current()->fixed_slots(), | |
| 4437 (StackAlignmentInBytes/wordSize))); | |
| 4438 | |
| 4439 // Body of function which returns an integer array locating | |
| 4440 // arguments either in registers or in stack slots. Passed an array | |
| 4441 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4442 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4443 // arguments for a CALLEE. Incoming stack arguments are | |
| 4444 // automatically biased by the preserve_stack_slots field above. | |
| 4445 calling_convention %{ | |
| 4446 // No difference between ingoing/outgoing just pass false | |
| 4447 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4448 %} | |
| 4449 | |
| 4450 | |
| 4451 // Body of function which returns an integer array locating | |
| 4452 // arguments either in registers or in stack slots. Passed an array | |
| 4453 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4454 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4455 // arguments for a CALLEE. Incoming stack arguments are | |
| 4456 // automatically biased by the preserve_stack_slots field above. | |
| 4457 c_calling_convention %{ | |
| 4458 // This is obviously always outgoing | |
| 4459 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4460 %} | |
| 4461 | |
| 4462 // Location of C & interpreter return values | |
| 4463 c_return_value %{ | |
| 4464 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4465 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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4466 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4467 |
| 4468 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 4469 // that C functions return float and double results in XMM0. | |
| 4470 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
| 4471 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4472 if( ideal_reg == Op_RegF && UseSSE>=2 ) | |
| 4473 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4474 | |
| 4475 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4476 %} | |
| 4477 | |
| 4478 // Location of return values | |
| 4479 return_value %{ | |
| 4480 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4481 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
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diff
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|
4482 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4483 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
| 4484 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4485 if( ideal_reg == Op_RegF && UseSSE>=1 ) | |
| 4486 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4487 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4488 %} | |
| 4489 | |
| 4490 %} | |
| 4491 | |
| 4492 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4493 //----------Operand Attributes------------------------------------------------- | |
| 4494 op_attrib op_cost(0); // Required cost attribute | |
| 4495 | |
| 4496 //----------Instruction Attributes--------------------------------------------- | |
| 4497 ins_attrib ins_cost(100); // Required cost attribute | |
| 4498 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4499 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 4500 // non-matching short branch variant of some | |
| 4501 // long branch? | |
| 4502 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 4503 // specifies the alignment that some part of the instruction (not | |
| 4504 // necessarily the start) requires. If > 1, a compute_padding() | |
| 4505 // function must be provided for the instruction | |
| 4506 | |
| 4507 //----------OPERANDS----------------------------------------------------------- | |
| 4508 // Operand definitions must precede instruction definitions for correct parsing | |
| 4509 // in the ADLC because operands constitute user defined types which are used in | |
| 4510 // instruction definitions. | |
| 4511 | |
| 4512 //----------Simple Operands---------------------------------------------------- | |
| 4513 // Immediate Operands | |
| 4514 // Integer Immediate | |
| 4515 operand immI() %{ | |
| 4516 match(ConI); | |
| 4517 | |
| 4518 op_cost(10); | |
| 4519 format %{ %} | |
| 4520 interface(CONST_INTER); | |
| 4521 %} | |
| 4522 | |
| 4523 // Constant for test vs zero | |
| 4524 operand immI0() %{ | |
| 4525 predicate(n->get_int() == 0); | |
| 4526 match(ConI); | |
| 4527 | |
| 4528 op_cost(0); | |
| 4529 format %{ %} | |
| 4530 interface(CONST_INTER); | |
| 4531 %} | |
| 4532 | |
| 4533 // Constant for increment | |
| 4534 operand immI1() %{ | |
| 4535 predicate(n->get_int() == 1); | |
| 4536 match(ConI); | |
| 4537 | |
| 4538 op_cost(0); | |
| 4539 format %{ %} | |
| 4540 interface(CONST_INTER); | |
| 4541 %} | |
| 4542 | |
| 4543 // Constant for decrement | |
| 4544 operand immI_M1() %{ | |
| 4545 predicate(n->get_int() == -1); | |
| 4546 match(ConI); | |
| 4547 | |
| 4548 op_cost(0); | |
| 4549 format %{ %} | |
| 4550 interface(CONST_INTER); | |
| 4551 %} | |
| 4552 | |
| 4553 // Valid scale values for addressing modes | |
| 4554 operand immI2() %{ | |
| 4555 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4556 match(ConI); | |
| 4557 | |
| 4558 format %{ %} | |
| 4559 interface(CONST_INTER); | |
| 4560 %} | |
| 4561 | |
| 4562 operand immI8() %{ | |
| 4563 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 4564 match(ConI); | |
| 4565 | |
| 4566 op_cost(5); | |
| 4567 format %{ %} | |
| 4568 interface(CONST_INTER); | |
| 4569 %} | |
| 4570 | |
| 4571 operand immI16() %{ | |
| 4572 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4573 match(ConI); | |
| 4574 | |
| 4575 op_cost(10); | |
| 4576 format %{ %} | |
| 4577 interface(CONST_INTER); | |
| 4578 %} | |
| 4579 | |
| 4580 // Constant for long shifts | |
| 4581 operand immI_32() %{ | |
| 4582 predicate( n->get_int() == 32 ); | |
| 4583 match(ConI); | |
| 4584 | |
| 4585 op_cost(0); | |
| 4586 format %{ %} | |
| 4587 interface(CONST_INTER); | |
| 4588 %} | |
| 4589 | |
| 4590 operand immI_1_31() %{ | |
| 4591 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 4592 match(ConI); | |
| 4593 | |
| 4594 op_cost(0); | |
| 4595 format %{ %} | |
| 4596 interface(CONST_INTER); | |
| 4597 %} | |
| 4598 | |
| 4599 operand immI_32_63() %{ | |
| 4600 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 4601 match(ConI); | |
| 4602 op_cost(0); | |
| 4603 | |
| 4604 format %{ %} | |
| 4605 interface(CONST_INTER); | |
| 4606 %} | |
| 4607 | |
| 219 | 4608 operand immI_1() %{ |
| 4609 predicate( n->get_int() == 1 ); | |
| 4610 match(ConI); | |
| 4611 | |
| 4612 op_cost(0); | |
| 4613 format %{ %} | |
| 4614 interface(CONST_INTER); | |
| 4615 %} | |
| 4616 | |
| 4617 operand immI_2() %{ | |
| 4618 predicate( n->get_int() == 2 ); | |
| 4619 match(ConI); | |
| 4620 | |
| 4621 op_cost(0); | |
| 4622 format %{ %} | |
| 4623 interface(CONST_INTER); | |
| 4624 %} | |
| 4625 | |
| 4626 operand immI_3() %{ | |
| 4627 predicate( n->get_int() == 3 ); | |
| 4628 match(ConI); | |
| 4629 | |
| 4630 op_cost(0); | |
| 4631 format %{ %} | |
| 4632 interface(CONST_INTER); | |
| 4633 %} | |
| 4634 | |
| 0 | 4635 // Pointer Immediate |
| 4636 operand immP() %{ | |
| 4637 match(ConP); | |
| 4638 | |
| 4639 op_cost(10); | |
| 4640 format %{ %} | |
| 4641 interface(CONST_INTER); | |
| 4642 %} | |
| 4643 | |
| 4644 // NULL Pointer Immediate | |
| 4645 operand immP0() %{ | |
| 4646 predicate( n->get_ptr() == 0 ); | |
| 4647 match(ConP); | |
| 4648 op_cost(0); | |
| 4649 | |
| 4650 format %{ %} | |
| 4651 interface(CONST_INTER); | |
| 4652 %} | |
| 4653 | |
| 4654 // Long Immediate | |
| 4655 operand immL() %{ | |
| 4656 match(ConL); | |
| 4657 | |
| 4658 op_cost(20); | |
| 4659 format %{ %} | |
| 4660 interface(CONST_INTER); | |
| 4661 %} | |
| 4662 | |
| 4663 // Long Immediate zero | |
| 4664 operand immL0() %{ | |
| 4665 predicate( n->get_long() == 0L ); | |
| 4666 match(ConL); | |
| 4667 op_cost(0); | |
| 4668 | |
| 4669 format %{ %} | |
| 4670 interface(CONST_INTER); | |
| 4671 %} | |
| 4672 | |
| 403 | 4673 // Long Immediate zero |
| 4674 operand immL_M1() %{ | |
| 4675 predicate( n->get_long() == -1L ); | |
| 4676 match(ConL); | |
| 4677 op_cost(0); | |
| 4678 | |
| 4679 format %{ %} | |
| 4680 interface(CONST_INTER); | |
| 4681 %} | |
| 4682 | |
| 0 | 4683 // Long immediate from 0 to 127. |
| 4684 // Used for a shorter form of long mul by 10. | |
| 4685 operand immL_127() %{ | |
| 4686 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4687 match(ConL); | |
| 4688 op_cost(0); | |
| 4689 | |
| 4690 format %{ %} | |
| 4691 interface(CONST_INTER); | |
| 4692 %} | |
| 4693 | |
| 4694 // Long Immediate: low 32-bit mask | |
| 4695 operand immL_32bits() %{ | |
| 4696 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4697 match(ConL); | |
| 4698 op_cost(0); | |
| 4699 | |
| 4700 format %{ %} | |
| 4701 interface(CONST_INTER); | |
| 4702 %} | |
| 4703 | |
| 4704 // Long Immediate: low 32-bit mask | |
| 4705 operand immL32() %{ | |
| 4706 predicate(n->get_long() == (int)(n->get_long())); | |
| 4707 match(ConL); | |
| 4708 op_cost(20); | |
| 4709 | |
| 4710 format %{ %} | |
| 4711 interface(CONST_INTER); | |
| 4712 %} | |
| 4713 | |
| 4714 //Double Immediate zero | |
| 4715 operand immD0() %{ | |
| 4716 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4717 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4718 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4719 match(ConD); | |
| 4720 | |
| 4721 op_cost(5); | |
| 4722 format %{ %} | |
| 4723 interface(CONST_INTER); | |
| 4724 %} | |
| 4725 | |
| 2008 | 4726 // Double Immediate one |
| 0 | 4727 operand immD1() %{ |
| 4728 predicate( UseSSE<=1 && n->getd() == 1.0 ); | |
| 4729 match(ConD); | |
| 4730 | |
| 4731 op_cost(5); | |
| 4732 format %{ %} | |
| 4733 interface(CONST_INTER); | |
| 4734 %} | |
| 4735 | |
| 4736 // Double Immediate | |
| 4737 operand immD() %{ | |
| 4738 predicate(UseSSE<=1); | |
| 4739 match(ConD); | |
| 4740 | |
| 4741 op_cost(5); | |
| 4742 format %{ %} | |
| 4743 interface(CONST_INTER); | |
| 4744 %} | |
| 4745 | |
| 4746 operand immXD() %{ | |
| 4747 predicate(UseSSE>=2); | |
| 4748 match(ConD); | |
| 4749 | |
| 4750 op_cost(5); | |
| 4751 format %{ %} | |
| 4752 interface(CONST_INTER); | |
| 4753 %} | |
| 4754 | |
| 4755 // Double Immediate zero | |
| 4756 operand immXD0() %{ | |
| 4757 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4758 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4759 // compare equal to -0.0. | |
| 4760 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4761 match(ConD); | |
| 4762 | |
| 4763 format %{ %} | |
| 4764 interface(CONST_INTER); | |
| 4765 %} | |
| 4766 | |
| 4767 // Float Immediate zero | |
| 4768 operand immF0() %{ | |
| 2008 | 4769 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4770 match(ConF); | |
| 4771 | |
| 4772 op_cost(5); | |
| 4773 format %{ %} | |
| 4774 interface(CONST_INTER); | |
| 4775 %} | |
| 4776 | |
| 4777 // Float Immediate one | |
| 4778 operand immF1() %{ | |
| 4779 predicate(UseSSE == 0 && n->getf() == 1.0F); | |
| 0 | 4780 match(ConF); |
| 4781 | |
| 4782 op_cost(5); | |
| 4783 format %{ %} | |
| 4784 interface(CONST_INTER); | |
| 4785 %} | |
| 4786 | |
| 4787 // Float Immediate | |
| 4788 operand immF() %{ | |
| 4789 predicate( UseSSE == 0 ); | |
| 4790 match(ConF); | |
| 4791 | |
| 4792 op_cost(5); | |
| 4793 format %{ %} | |
| 4794 interface(CONST_INTER); | |
| 4795 %} | |
| 4796 | |
| 4797 // Float Immediate | |
| 4798 operand immXF() %{ | |
| 4799 predicate(UseSSE >= 1); | |
| 4800 match(ConF); | |
| 4801 | |
| 4802 op_cost(5); | |
| 4803 format %{ %} | |
| 4804 interface(CONST_INTER); | |
| 4805 %} | |
| 4806 | |
| 4807 // Float Immediate zero. Zero and not -0.0 | |
| 4808 operand immXF0() %{ | |
| 4809 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); | |
| 4810 match(ConF); | |
| 4811 | |
| 4812 op_cost(5); | |
| 4813 format %{ %} | |
| 4814 interface(CONST_INTER); | |
| 4815 %} | |
| 4816 | |
| 4817 // Immediates for special shifts (sign extend) | |
| 4818 | |
| 4819 // Constants for increment | |
| 4820 operand immI_16() %{ | |
| 4821 predicate( n->get_int() == 16 ); | |
| 4822 match(ConI); | |
| 4823 | |
| 4824 format %{ %} | |
| 4825 interface(CONST_INTER); | |
| 4826 %} | |
| 4827 | |
| 4828 operand immI_24() %{ | |
| 4829 predicate( n->get_int() == 24 ); | |
| 4830 match(ConI); | |
| 4831 | |
| 4832 format %{ %} | |
| 4833 interface(CONST_INTER); | |
| 4834 %} | |
| 4835 | |
| 4836 // Constant for byte-wide masking | |
| 4837 operand immI_255() %{ | |
| 4838 predicate( n->get_int() == 255 ); | |
| 4839 match(ConI); | |
| 4840 | |
| 4841 format %{ %} | |
| 4842 interface(CONST_INTER); | |
| 4843 %} | |
| 4844 | |
| 785 | 4845 // Constant for short-wide masking |
| 4846 operand immI_65535() %{ | |
| 4847 predicate(n->get_int() == 65535); | |
| 4848 match(ConI); | |
| 4849 | |
| 4850 format %{ %} | |
| 4851 interface(CONST_INTER); | |
| 4852 %} | |
| 4853 | |
| 0 | 4854 // Register Operands |
| 4855 // Integer Register | |
| 4856 operand eRegI() %{ | |
| 4857 constraint(ALLOC_IN_RC(e_reg)); | |
| 4858 match(RegI); | |
| 4859 match(xRegI); | |
| 4860 match(eAXRegI); | |
| 4861 match(eBXRegI); | |
| 4862 match(eCXRegI); | |
| 4863 match(eDXRegI); | |
| 4864 match(eDIRegI); | |
| 4865 match(eSIRegI); | |
| 4866 | |
| 4867 format %{ %} | |
| 4868 interface(REG_INTER); | |
| 4869 %} | |
| 4870 | |
| 4871 // Subset of Integer Register | |
| 4872 operand xRegI(eRegI reg) %{ | |
| 4873 constraint(ALLOC_IN_RC(x_reg)); | |
| 4874 match(reg); | |
| 4875 match(eAXRegI); | |
| 4876 match(eBXRegI); | |
| 4877 match(eCXRegI); | |
| 4878 match(eDXRegI); | |
| 4879 | |
| 4880 format %{ %} | |
| 4881 interface(REG_INTER); | |
| 4882 %} | |
| 4883 | |
| 4884 // Special Registers | |
| 4885 operand eAXRegI(xRegI reg) %{ | |
| 4886 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4887 match(reg); | |
| 4888 match(eRegI); | |
| 4889 | |
| 4890 format %{ "EAX" %} | |
| 4891 interface(REG_INTER); | |
| 4892 %} | |
| 4893 | |
| 4894 // Special Registers | |
| 4895 operand eBXRegI(xRegI reg) %{ | |
| 4896 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4897 match(reg); | |
| 4898 match(eRegI); | |
| 4899 | |
| 4900 format %{ "EBX" %} | |
| 4901 interface(REG_INTER); | |
| 4902 %} | |
| 4903 | |
| 4904 operand eCXRegI(xRegI reg) %{ | |
| 4905 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4906 match(reg); | |
| 4907 match(eRegI); | |
| 4908 | |
| 4909 format %{ "ECX" %} | |
| 4910 interface(REG_INTER); | |
| 4911 %} | |
| 4912 | |
| 4913 operand eDXRegI(xRegI reg) %{ | |
| 4914 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4915 match(reg); | |
| 4916 match(eRegI); | |
| 4917 | |
| 4918 format %{ "EDX" %} | |
| 4919 interface(REG_INTER); | |
| 4920 %} | |
| 4921 | |
| 4922 operand eDIRegI(xRegI reg) %{ | |
| 4923 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4924 match(reg); | |
| 4925 match(eRegI); | |
| 4926 | |
| 4927 format %{ "EDI" %} | |
| 4928 interface(REG_INTER); | |
| 4929 %} | |
| 4930 | |
| 4931 operand naxRegI() %{ | |
| 4932 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4933 match(RegI); | |
| 4934 match(eCXRegI); | |
| 4935 match(eDXRegI); | |
| 4936 match(eSIRegI); | |
| 4937 match(eDIRegI); | |
| 4938 | |
| 4939 format %{ %} | |
| 4940 interface(REG_INTER); | |
| 4941 %} | |
| 4942 | |
| 4943 operand nadxRegI() %{ | |
| 4944 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4945 match(RegI); | |
| 4946 match(eBXRegI); | |
| 4947 match(eCXRegI); | |
| 4948 match(eSIRegI); | |
| 4949 match(eDIRegI); | |
| 4950 | |
| 4951 format %{ %} | |
| 4952 interface(REG_INTER); | |
| 4953 %} | |
| 4954 | |
| 4955 operand ncxRegI() %{ | |
| 4956 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4957 match(RegI); | |
| 4958 match(eAXRegI); | |
| 4959 match(eDXRegI); | |
| 4960 match(eSIRegI); | |
| 4961 match(eDIRegI); | |
| 4962 | |
| 4963 format %{ %} | |
| 4964 interface(REG_INTER); | |
| 4965 %} | |
| 4966 | |
| 4967 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4968 // // | |
| 4969 operand eSIRegI(xRegI reg) %{ | |
| 4970 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4971 match(reg); | |
| 4972 match(eRegI); | |
| 4973 | |
| 4974 format %{ "ESI" %} | |
| 4975 interface(REG_INTER); | |
| 4976 %} | |
| 4977 | |
| 4978 // Pointer Register | |
| 4979 operand anyRegP() %{ | |
| 4980 constraint(ALLOC_IN_RC(any_reg)); | |
| 4981 match(RegP); | |
| 4982 match(eAXRegP); | |
| 4983 match(eBXRegP); | |
| 4984 match(eCXRegP); | |
| 4985 match(eDIRegP); | |
| 4986 match(eRegP); | |
| 4987 | |
| 4988 format %{ %} | |
| 4989 interface(REG_INTER); | |
| 4990 %} | |
| 4991 | |
| 4992 operand eRegP() %{ | |
| 4993 constraint(ALLOC_IN_RC(e_reg)); | |
| 4994 match(RegP); | |
| 4995 match(eAXRegP); | |
| 4996 match(eBXRegP); | |
| 4997 match(eCXRegP); | |
| 4998 match(eDIRegP); | |
| 4999 | |
| 5000 format %{ %} | |
| 5001 interface(REG_INTER); | |
| 5002 %} | |
| 5003 | |
| 5004 // On windows95, EBP is not safe to use for implicit null tests. | |
| 5005 operand eRegP_no_EBP() %{ | |
| 5006 constraint(ALLOC_IN_RC(e_reg_no_rbp)); | |
| 5007 match(RegP); | |
| 5008 match(eAXRegP); | |
| 5009 match(eBXRegP); | |
| 5010 match(eCXRegP); | |
| 5011 match(eDIRegP); | |
| 5012 | |
| 5013 op_cost(100); | |
| 5014 format %{ %} | |
| 5015 interface(REG_INTER); | |
| 5016 %} | |
| 5017 | |
| 5018 operand naxRegP() %{ | |
| 5019 constraint(ALLOC_IN_RC(nax_reg)); | |
| 5020 match(RegP); | |
| 5021 match(eBXRegP); | |
| 5022 match(eDXRegP); | |
| 5023 match(eCXRegP); | |
| 5024 match(eSIRegP); | |
| 5025 match(eDIRegP); | |
| 5026 | |
| 5027 format %{ %} | |
| 5028 interface(REG_INTER); | |
| 5029 %} | |
| 5030 | |
| 5031 operand nabxRegP() %{ | |
| 5032 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 5033 match(RegP); | |
| 5034 match(eCXRegP); | |
| 5035 match(eDXRegP); | |
| 5036 match(eSIRegP); | |
| 5037 match(eDIRegP); | |
| 5038 | |
| 5039 format %{ %} | |
| 5040 interface(REG_INTER); | |
| 5041 %} | |
| 5042 | |
| 5043 operand pRegP() %{ | |
| 5044 constraint(ALLOC_IN_RC(p_reg)); | |
| 5045 match(RegP); | |
| 5046 match(eBXRegP); | |
| 5047 match(eDXRegP); | |
| 5048 match(eSIRegP); | |
| 5049 match(eDIRegP); | |
| 5050 | |
| 5051 format %{ %} | |
| 5052 interface(REG_INTER); | |
| 5053 %} | |
| 5054 | |
| 5055 // Special Registers | |
| 5056 // Return a pointer value | |
| 5057 operand eAXRegP(eRegP reg) %{ | |
| 5058 constraint(ALLOC_IN_RC(eax_reg)); | |
| 5059 match(reg); | |
| 5060 format %{ "EAX" %} | |
| 5061 interface(REG_INTER); | |
| 5062 %} | |
| 5063 | |
| 5064 // Used in AtomicAdd | |
| 5065 operand eBXRegP(eRegP reg) %{ | |
| 5066 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 5067 match(reg); | |
| 5068 format %{ "EBX" %} | |
| 5069 interface(REG_INTER); | |
| 5070 %} | |
| 5071 | |
| 5072 // Tail-call (interprocedural jump) to interpreter | |
| 5073 operand eCXRegP(eRegP reg) %{ | |
| 5074 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 5075 match(reg); | |
| 5076 format %{ "ECX" %} | |
| 5077 interface(REG_INTER); | |
| 5078 %} | |
| 5079 | |
| 5080 operand eSIRegP(eRegP reg) %{ | |
| 5081 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5082 match(reg); | |
| 5083 format %{ "ESI" %} | |
| 5084 interface(REG_INTER); | |
| 5085 %} | |
| 5086 | |
| 5087 // Used in rep stosw | |
| 5088 operand eDIRegP(eRegP reg) %{ | |
| 5089 constraint(ALLOC_IN_RC(edi_reg)); | |
| 5090 match(reg); | |
| 5091 format %{ "EDI" %} | |
| 5092 interface(REG_INTER); | |
| 5093 %} | |
| 5094 | |
| 5095 operand eBPRegP() %{ | |
| 5096 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 5097 match(RegP); | |
| 5098 format %{ "EBP" %} | |
| 5099 interface(REG_INTER); | |
| 5100 %} | |
| 5101 | |
| 5102 operand eRegL() %{ | |
| 5103 constraint(ALLOC_IN_RC(long_reg)); | |
| 5104 match(RegL); | |
| 5105 match(eADXRegL); | |
| 5106 | |
| 5107 format %{ %} | |
| 5108 interface(REG_INTER); | |
| 5109 %} | |
| 5110 | |
| 5111 operand eADXRegL( eRegL reg ) %{ | |
| 5112 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5113 match(reg); | |
| 5114 | |
| 5115 format %{ "EDX:EAX" %} | |
| 5116 interface(REG_INTER); | |
| 5117 %} | |
| 5118 | |
| 5119 operand eBCXRegL( eRegL reg ) %{ | |
| 5120 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 5121 match(reg); | |
| 5122 | |
| 5123 format %{ "EBX:ECX" %} | |
| 5124 interface(REG_INTER); | |
| 5125 %} | |
| 5126 | |
| 5127 // Special case for integer high multiply | |
| 5128 operand eADXRegL_low_only() %{ | |
| 5129 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5130 match(RegL); | |
| 5131 | |
| 5132 format %{ "EAX" %} | |
| 5133 interface(REG_INTER); | |
| 5134 %} | |
| 5135 | |
| 5136 // Flags register, used as output of compare instructions | |
| 5137 operand eFlagsReg() %{ | |
| 5138 constraint(ALLOC_IN_RC(int_flags)); | |
| 5139 match(RegFlags); | |
| 5140 | |
| 5141 format %{ "EFLAGS" %} | |
| 5142 interface(REG_INTER); | |
| 5143 %} | |
| 5144 | |
| 5145 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5146 operand eFlagsRegU() %{ | |
| 5147 constraint(ALLOC_IN_RC(int_flags)); | |
| 5148 match(RegFlags); | |
| 5149 | |
| 5150 format %{ "EFLAGS_U" %} | |
| 5151 interface(REG_INTER); | |
| 5152 %} | |
| 5153 | |
|
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5154 operand eFlagsRegUCF() %{ |
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5155 constraint(ALLOC_IN_RC(int_flags)); |
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5156 match(RegFlags); |
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5157 predicate(false); |
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|
5158 |
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|
5159 format %{ "EFLAGS_U_CF" %} |
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5160 interface(REG_INTER); |
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|
5161 %} |
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|
5162 |
| 0 | 5163 // Condition Code Register used by long compare |
| 5164 operand flagsReg_long_LTGE() %{ | |
| 5165 constraint(ALLOC_IN_RC(int_flags)); | |
| 5166 match(RegFlags); | |
| 5167 format %{ "FLAGS_LTGE" %} | |
| 5168 interface(REG_INTER); | |
| 5169 %} | |
| 5170 operand flagsReg_long_EQNE() %{ | |
| 5171 constraint(ALLOC_IN_RC(int_flags)); | |
| 5172 match(RegFlags); | |
| 5173 format %{ "FLAGS_EQNE" %} | |
| 5174 interface(REG_INTER); | |
| 5175 %} | |
| 5176 operand flagsReg_long_LEGT() %{ | |
| 5177 constraint(ALLOC_IN_RC(int_flags)); | |
| 5178 match(RegFlags); | |
| 5179 format %{ "FLAGS_LEGT" %} | |
| 5180 interface(REG_INTER); | |
| 5181 %} | |
| 5182 | |
| 5183 // Float register operands | |
| 5184 operand regD() %{ | |
| 5185 predicate( UseSSE < 2 ); | |
| 5186 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 5187 match(RegD); | |
| 5188 match(regDPR1); | |
| 5189 match(regDPR2); | |
| 5190 format %{ %} | |
| 5191 interface(REG_INTER); | |
| 5192 %} | |
| 5193 | |
| 5194 operand regDPR1(regD reg) %{ | |
| 5195 predicate( UseSSE < 2 ); | |
| 5196 constraint(ALLOC_IN_RC(dbl_reg0)); | |
| 5197 match(reg); | |
| 5198 format %{ "FPR1" %} | |
| 5199 interface(REG_INTER); | |
| 5200 %} | |
| 5201 | |
| 5202 operand regDPR2(regD reg) %{ | |
| 5203 predicate( UseSSE < 2 ); | |
| 5204 constraint(ALLOC_IN_RC(dbl_reg1)); | |
| 5205 match(reg); | |
| 5206 format %{ "FPR2" %} | |
| 5207 interface(REG_INTER); | |
| 5208 %} | |
| 5209 | |
| 5210 operand regnotDPR1(regD reg) %{ | |
| 5211 predicate( UseSSE < 2 ); | |
| 5212 constraint(ALLOC_IN_RC(dbl_notreg0)); | |
| 5213 match(reg); | |
| 5214 format %{ %} | |
| 5215 interface(REG_INTER); | |
| 5216 %} | |
| 5217 | |
| 5218 // XMM Double register operands | |
| 5219 operand regXD() %{ | |
| 5220 predicate( UseSSE>=2 ); | |
| 5221 constraint(ALLOC_IN_RC(xdb_reg)); | |
| 5222 match(RegD); | |
| 5223 match(regXD6); | |
| 5224 match(regXD7); | |
| 5225 format %{ %} | |
| 5226 interface(REG_INTER); | |
| 5227 %} | |
| 5228 | |
| 5229 // XMM6 double register operands | |
| 5230 operand regXD6(regXD reg) %{ | |
| 5231 predicate( UseSSE>=2 ); | |
| 5232 constraint(ALLOC_IN_RC(xdb_reg6)); | |
| 5233 match(reg); | |
| 5234 format %{ "XMM6" %} | |
| 5235 interface(REG_INTER); | |
| 5236 %} | |
| 5237 | |
| 5238 // XMM7 double register operands | |
| 5239 operand regXD7(regXD reg) %{ | |
| 5240 predicate( UseSSE>=2 ); | |
| 5241 constraint(ALLOC_IN_RC(xdb_reg7)); | |
| 5242 match(reg); | |
| 5243 format %{ "XMM7" %} | |
| 5244 interface(REG_INTER); | |
| 5245 %} | |
| 5246 | |
| 5247 // Float register operands | |
| 5248 operand regF() %{ | |
| 5249 predicate( UseSSE < 2 ); | |
| 5250 constraint(ALLOC_IN_RC(flt_reg)); | |
| 5251 match(RegF); | |
| 5252 match(regFPR1); | |
| 5253 format %{ %} | |
| 5254 interface(REG_INTER); | |
| 5255 %} | |
| 5256 | |
| 5257 // Float register operands | |
| 5258 operand regFPR1(regF reg) %{ | |
| 5259 predicate( UseSSE < 2 ); | |
| 5260 constraint(ALLOC_IN_RC(flt_reg0)); | |
| 5261 match(reg); | |
| 5262 format %{ "FPR1" %} | |
| 5263 interface(REG_INTER); | |
| 5264 %} | |
| 5265 | |
| 5266 // XMM register operands | |
| 5267 operand regX() %{ | |
| 5268 predicate( UseSSE>=1 ); | |
| 5269 constraint(ALLOC_IN_RC(xmm_reg)); | |
| 5270 match(RegF); | |
| 5271 format %{ %} | |
| 5272 interface(REG_INTER); | |
| 5273 %} | |
| 5274 | |
| 5275 | |
| 5276 //----------Memory Operands---------------------------------------------------- | |
| 5277 // Direct Memory Operand | |
| 5278 operand direct(immP addr) %{ | |
| 5279 match(addr); | |
| 5280 | |
| 5281 format %{ "[$addr]" %} | |
| 5282 interface(MEMORY_INTER) %{ | |
| 5283 base(0xFFFFFFFF); | |
| 5284 index(0x4); | |
| 5285 scale(0x0); | |
| 5286 disp($addr); | |
| 5287 %} | |
| 5288 %} | |
| 5289 | |
| 5290 // Indirect Memory Operand | |
| 5291 operand indirect(eRegP reg) %{ | |
| 5292 constraint(ALLOC_IN_RC(e_reg)); | |
| 5293 match(reg); | |
| 5294 | |
| 5295 format %{ "[$reg]" %} | |
| 5296 interface(MEMORY_INTER) %{ | |
| 5297 base($reg); | |
| 5298 index(0x4); | |
| 5299 scale(0x0); | |
| 5300 disp(0x0); | |
| 5301 %} | |
| 5302 %} | |
| 5303 | |
| 5304 // Indirect Memory Plus Short Offset Operand | |
| 5305 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 5306 match(AddP reg off); | |
| 5307 | |
| 5308 format %{ "[$reg + $off]" %} | |
| 5309 interface(MEMORY_INTER) %{ | |
| 5310 base($reg); | |
| 5311 index(0x4); | |
| 5312 scale(0x0); | |
| 5313 disp($off); | |
| 5314 %} | |
| 5315 %} | |
| 5316 | |
| 5317 // Indirect Memory Plus Long Offset Operand | |
| 5318 operand indOffset32(eRegP reg, immI off) %{ | |
| 5319 match(AddP reg off); | |
| 5320 | |
| 5321 format %{ "[$reg + $off]" %} | |
| 5322 interface(MEMORY_INTER) %{ | |
| 5323 base($reg); | |
| 5324 index(0x4); | |
| 5325 scale(0x0); | |
| 5326 disp($off); | |
| 5327 %} | |
| 5328 %} | |
| 5329 | |
| 5330 // Indirect Memory Plus Long Offset Operand | |
| 5331 operand indOffset32X(eRegI reg, immP off) %{ | |
| 5332 match(AddP off reg); | |
| 5333 | |
| 5334 format %{ "[$reg + $off]" %} | |
| 5335 interface(MEMORY_INTER) %{ | |
| 5336 base($reg); | |
| 5337 index(0x4); | |
| 5338 scale(0x0); | |
| 5339 disp($off); | |
| 5340 %} | |
| 5341 %} | |
| 5342 | |
| 5343 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5344 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ | |
| 5345 match(AddP (AddP reg ireg) off); | |
| 5346 | |
| 5347 op_cost(10); | |
| 5348 format %{"[$reg + $off + $ireg]" %} | |
| 5349 interface(MEMORY_INTER) %{ | |
| 5350 base($reg); | |
| 5351 index($ireg); | |
| 5352 scale(0x0); | |
| 5353 disp($off); | |
| 5354 %} | |
| 5355 %} | |
| 5356 | |
| 5357 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5358 operand indIndex(eRegP reg, eRegI ireg) %{ | |
| 5359 match(AddP reg ireg); | |
| 5360 | |
| 5361 op_cost(10); | |
| 5362 format %{"[$reg + $ireg]" %} | |
| 5363 interface(MEMORY_INTER) %{ | |
| 5364 base($reg); | |
| 5365 index($ireg); | |
| 5366 scale(0x0); | |
| 5367 disp(0x0); | |
| 5368 %} | |
| 5369 %} | |
| 5370 | |
| 5371 // // ------------------------------------------------------------------------- | |
| 5372 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 5373 // // ------------------------------------------------------------------------- | |
| 5374 // // Scaled Memory Operands | |
| 5375 // // Indirect Memory Times Scale Plus Offset Operand | |
| 5376 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ | |
| 5377 // match(AddP off (LShiftI ireg scale)); | |
| 5378 // | |
| 5379 // op_cost(10); | |
| 5380 // format %{"[$off + $ireg << $scale]" %} | |
| 5381 // interface(MEMORY_INTER) %{ | |
| 5382 // base(0x4); | |
| 5383 // index($ireg); | |
| 5384 // scale($scale); | |
| 5385 // disp($off); | |
| 5386 // %} | |
| 5387 // %} | |
| 5388 | |
| 5389 // Indirect Memory Times Scale Plus Index Register | |
| 5390 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ | |
| 5391 match(AddP reg (LShiftI ireg scale)); | |
| 5392 | |
| 5393 op_cost(10); | |
| 5394 format %{"[$reg + $ireg << $scale]" %} | |
| 5395 interface(MEMORY_INTER) %{ | |
| 5396 base($reg); | |
| 5397 index($ireg); | |
| 5398 scale($scale); | |
| 5399 disp(0x0); | |
| 5400 %} | |
| 5401 %} | |
| 5402 | |
| 5403 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5404 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ | |
| 5405 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5406 | |
| 5407 op_cost(10); | |
| 5408 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5409 interface(MEMORY_INTER) %{ | |
| 5410 base($reg); | |
| 5411 index($ireg); | |
| 5412 scale($scale); | |
| 5413 disp($off); | |
| 5414 %} | |
| 5415 %} | |
| 5416 | |
| 5417 //----------Load Long Memory Operands------------------------------------------ | |
| 5418 // The load-long idiom will use it's address expression again after loading | |
| 5419 // the first word of the long. If the load-long destination overlaps with | |
| 5420 // registers used in the addressing expression, the 2nd half will be loaded | |
| 5421 // from a clobbered address. Fix this by requiring that load-long use | |
| 5422 // address registers that do not overlap with the load-long target. | |
| 5423 | |
| 5424 // load-long support | |
| 5425 operand load_long_RegP() %{ | |
| 5426 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5427 match(RegP); | |
| 5428 match(eSIRegP); | |
| 5429 op_cost(100); | |
| 5430 format %{ %} | |
| 5431 interface(REG_INTER); | |
| 5432 %} | |
| 5433 | |
| 5434 // Indirect Memory Operand Long | |
| 5435 operand load_long_indirect(load_long_RegP reg) %{ | |
| 5436 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5437 match(reg); | |
| 5438 | |
| 5439 format %{ "[$reg]" %} | |
| 5440 interface(MEMORY_INTER) %{ | |
| 5441 base($reg); | |
| 5442 index(0x4); | |
| 5443 scale(0x0); | |
| 5444 disp(0x0); | |
| 5445 %} | |
| 5446 %} | |
| 5447 | |
| 5448 // Indirect Memory Plus Long Offset Operand | |
| 5449 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 5450 match(AddP reg off); | |
| 5451 | |
| 5452 format %{ "[$reg + $off]" %} | |
| 5453 interface(MEMORY_INTER) %{ | |
| 5454 base($reg); | |
| 5455 index(0x4); | |
| 5456 scale(0x0); | |
| 5457 disp($off); | |
| 5458 %} | |
| 5459 %} | |
| 5460 | |
| 5461 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 5462 | |
| 5463 | |
| 5464 //----------Special Memory Operands-------------------------------------------- | |
| 5465 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5466 // values on the stack where a match requires a value to | |
| 5467 // flow through memory. | |
| 5468 operand stackSlotP(sRegP reg) %{ | |
| 5469 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5470 // No match rule because this operand is only generated in matching | |
| 5471 format %{ "[$reg]" %} | |
| 5472 interface(MEMORY_INTER) %{ | |
| 5473 base(0x4); // ESP | |
| 5474 index(0x4); // No Index | |
| 5475 scale(0x0); // No Scale | |
| 5476 disp($reg); // Stack Offset | |
| 5477 %} | |
| 5478 %} | |
| 5479 | |
| 5480 operand stackSlotI(sRegI reg) %{ | |
| 5481 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5482 // No match rule because this operand is only generated in matching | |
| 5483 format %{ "[$reg]" %} | |
| 5484 interface(MEMORY_INTER) %{ | |
| 5485 base(0x4); // ESP | |
| 5486 index(0x4); // No Index | |
| 5487 scale(0x0); // No Scale | |
| 5488 disp($reg); // Stack Offset | |
| 5489 %} | |
| 5490 %} | |
| 5491 | |
| 5492 operand stackSlotF(sRegF reg) %{ | |
| 5493 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5494 // No match rule because this operand is only generated in matching | |
| 5495 format %{ "[$reg]" %} | |
| 5496 interface(MEMORY_INTER) %{ | |
| 5497 base(0x4); // ESP | |
| 5498 index(0x4); // No Index | |
| 5499 scale(0x0); // No Scale | |
| 5500 disp($reg); // Stack Offset | |
| 5501 %} | |
| 5502 %} | |
| 5503 | |
| 5504 operand stackSlotD(sRegD reg) %{ | |
| 5505 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5506 // No match rule because this operand is only generated in matching | |
| 5507 format %{ "[$reg]" %} | |
| 5508 interface(MEMORY_INTER) %{ | |
| 5509 base(0x4); // ESP | |
| 5510 index(0x4); // No Index | |
| 5511 scale(0x0); // No Scale | |
| 5512 disp($reg); // Stack Offset | |
| 5513 %} | |
| 5514 %} | |
| 5515 | |
| 5516 operand stackSlotL(sRegL reg) %{ | |
| 5517 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5518 // No match rule because this operand is only generated in matching | |
| 5519 format %{ "[$reg]" %} | |
| 5520 interface(MEMORY_INTER) %{ | |
| 5521 base(0x4); // ESP | |
| 5522 index(0x4); // No Index | |
| 5523 scale(0x0); // No Scale | |
| 5524 disp($reg); // Stack Offset | |
| 5525 %} | |
| 5526 %} | |
| 5527 | |
| 5528 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 5529 // Indirect Memory Operand | |
| 5530 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 5531 %{ | |
| 5532 constraint(ALLOC_IN_RC(e_reg)); | |
| 5533 match(reg); | |
| 5534 | |
| 5535 op_cost(100); | |
| 5536 format %{ "[$reg]" %} | |
| 5537 interface(MEMORY_INTER) %{ | |
| 5538 base($reg); | |
| 5539 index(0x4); | |
| 5540 scale(0x0); | |
| 5541 disp(0x0); | |
| 5542 %} | |
| 5543 %} | |
| 5544 | |
| 5545 // Indirect Memory Plus Short Offset Operand | |
| 5546 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 5547 %{ | |
| 5548 match(AddP reg off); | |
| 5549 | |
| 5550 op_cost(100); | |
| 5551 format %{ "[$reg + $off]" %} | |
| 5552 interface(MEMORY_INTER) %{ | |
| 5553 base($reg); | |
| 5554 index(0x4); | |
| 5555 scale(0x0); | |
| 5556 disp($off); | |
| 5557 %} | |
| 5558 %} | |
| 5559 | |
| 5560 // Indirect Memory Plus Long Offset Operand | |
| 5561 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 5562 %{ | |
| 5563 match(AddP reg off); | |
| 5564 | |
| 5565 op_cost(100); | |
| 5566 format %{ "[$reg + $off]" %} | |
| 5567 interface(MEMORY_INTER) %{ | |
| 5568 base($reg); | |
| 5569 index(0x4); | |
| 5570 scale(0x0); | |
| 5571 disp($off); | |
| 5572 %} | |
| 5573 %} | |
| 5574 | |
| 5575 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5576 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) | |
| 5577 %{ | |
| 5578 match(AddP (AddP reg ireg) off); | |
| 5579 | |
| 5580 op_cost(100); | |
| 5581 format %{"[$reg + $off + $ireg]" %} | |
| 5582 interface(MEMORY_INTER) %{ | |
| 5583 base($reg); | |
| 5584 index($ireg); | |
| 5585 scale(0x0); | |
| 5586 disp($off); | |
| 5587 %} | |
| 5588 %} | |
| 5589 | |
| 5590 // Indirect Memory Times Scale Plus Index Register | |
| 5591 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) | |
| 5592 %{ | |
| 5593 match(AddP reg (LShiftI ireg scale)); | |
| 5594 | |
| 5595 op_cost(100); | |
| 5596 format %{"[$reg + $ireg << $scale]" %} | |
| 5597 interface(MEMORY_INTER) %{ | |
| 5598 base($reg); | |
| 5599 index($ireg); | |
| 5600 scale($scale); | |
| 5601 disp(0x0); | |
| 5602 %} | |
| 5603 %} | |
| 5604 | |
| 5605 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5606 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) | |
| 5607 %{ | |
| 5608 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5609 | |
| 5610 op_cost(100); | |
| 5611 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5612 interface(MEMORY_INTER) %{ | |
| 5613 base($reg); | |
| 5614 index($ireg); | |
| 5615 scale($scale); | |
| 5616 disp($off); | |
| 5617 %} | |
| 5618 %} | |
| 5619 | |
| 5620 //----------Conditional Branch Operands---------------------------------------- | |
| 5621 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5622 // the following set of codes: | |
| 5623 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5624 // | |
| 5625 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5626 // by the comparison instruction that sets a condition code flags register. | |
| 5627 // That result is represented by a flags operand whose subtype is appropriate | |
| 5628 // to the unsignedness (etc.) of the comparison. | |
| 5629 // | |
| 5630 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5631 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5632 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5633 | |
| 5634 // Comparision Code | |
| 5635 operand cmpOp() %{ | |
| 5636 match(Bool); | |
| 5637 | |
| 5638 format %{ "" %} | |
| 5639 interface(COND_INTER) %{ | |
|
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5640 equal(0x4, "e"); |
|
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5641 not_equal(0x5, "ne"); |
|
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5642 less(0xC, "l"); |
|
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diff
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|
5643 greater_equal(0xD, "ge"); |
|
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403
diff
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|
5644 less_equal(0xE, "le"); |
|
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diff
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|
5645 greater(0xF, "g"); |
| 0 | 5646 %} |
| 5647 %} | |
| 5648 | |
| 5649 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5650 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5651 // C0 and C3 are turned into Carry & Zero flags. | |
| 5652 operand cmpOpU() %{ | |
| 5653 match(Bool); | |
| 5654 | |
| 5655 format %{ "" %} | |
| 5656 interface(COND_INTER) %{ | |
|
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|
5657 equal(0x4, "e"); |
|
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diff
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|
5658 not_equal(0x5, "ne"); |
|
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403
diff
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|
5659 less(0x2, "b"); |
|
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|
5660 greater_equal(0x3, "nb"); |
|
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|
5661 less_equal(0x6, "be"); |
|
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|
5662 greater(0x7, "nbe"); |
|
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diff
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|
5663 %} |
|
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diff
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|
5664 %} |
|
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diff
changeset
|
5665 |
|
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diff
changeset
|
5666 // Floating comparisons that don't require any fixup for the unordered case |
|
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diff
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|
5667 operand cmpOpUCF() %{ |
|
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parents:
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|
5668 match(Bool); |
|
4d9884b01ba6
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diff
changeset
|
5669 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
5670 n->as_Bool()->_test._test == BoolTest::ge || |
|
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diff
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|
5671 n->as_Bool()->_test._test == BoolTest::le || |
|
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diff
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|
5672 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
5673 format %{ "" %} |
|
4d9884b01ba6
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diff
changeset
|
5674 interface(COND_INTER) %{ |
|
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diff
changeset
|
5675 equal(0x4, "e"); |
|
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diff
changeset
|
5676 not_equal(0x5, "ne"); |
|
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diff
changeset
|
5677 less(0x2, "b"); |
|
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diff
changeset
|
5678 greater_equal(0x3, "nb"); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
5679 less_equal(0x6, "be"); |
|
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diff
changeset
|
5680 greater(0x7, "nbe"); |
|
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|
5681 %} |
|
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|
5682 %} |
|
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|
5683 |
|
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changeset
|
5684 |
|
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diff
changeset
|
5685 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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diff
changeset
|
5686 operand cmpOpUCF2() %{ |
|
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|
5687 match(Bool); |
|
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changeset
|
5688 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
5689 n->as_Bool()->_test._test == BoolTest::eq); |
|
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changeset
|
5690 format %{ "" %} |
|
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diff
changeset
|
5691 interface(COND_INTER) %{ |
|
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diff
changeset
|
5692 equal(0x4, "e"); |
|
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diff
changeset
|
5693 not_equal(0x5, "ne"); |
|
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changeset
|
5694 less(0x2, "b"); |
|
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diff
changeset
|
5695 greater_equal(0x3, "nb"); |
|
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changeset
|
5696 less_equal(0x6, "be"); |
|
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|
5697 greater(0x7, "nbe"); |
| 0 | 5698 %} |
| 5699 %} | |
| 5700 | |
| 5701 // Comparison Code for FP conditional move | |
| 5702 operand cmpOp_fcmov() %{ | |
| 5703 match(Bool); | |
| 5704 | |
| 5705 format %{ "" %} | |
| 5706 interface(COND_INTER) %{ | |
| 5707 equal (0x0C8); | |
| 5708 not_equal (0x1C8); | |
| 5709 less (0x0C0); | |
| 5710 greater_equal(0x1C0); | |
| 5711 less_equal (0x0D0); | |
| 5712 greater (0x1D0); | |
| 5713 %} | |
| 5714 %} | |
| 5715 | |
| 5716 // Comparision Code used in long compares | |
| 5717 operand cmpOp_commute() %{ | |
| 5718 match(Bool); | |
| 5719 | |
| 5720 format %{ "" %} | |
| 5721 interface(COND_INTER) %{ | |
|
415
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|
5722 equal(0x4, "e"); |
|
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changeset
|
5723 not_equal(0x5, "ne"); |
|
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diff
changeset
|
5724 less(0xF, "g"); |
|
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diff
changeset
|
5725 greater_equal(0xE, "le"); |
|
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diff
changeset
|
5726 less_equal(0xD, "ge"); |
|
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|
5727 greater(0xC, "l"); |
| 0 | 5728 %} |
| 5729 %} | |
| 5730 | |
| 5731 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5732 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5733 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5734 // instructions for every form of operand when the instruction accepts |
| 5735 // multiple operand types with the same basic encoding and format. The classic | |
| 5736 // case of this is memory operands. | |
| 5737 | |
| 5738 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5739 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5740 | |
| 5741 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5742 // This means some kind of offset is always required and you cannot use | |
| 5743 // an oop as the offset (done when working on static globals). | |
| 5744 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5745 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5746 | |
| 5747 | |
| 5748 //----------PIPELINE----------------------------------------------------------- | |
| 5749 // Rules which define the behavior of the target architectures pipeline. | |
| 5750 pipeline %{ | |
| 5751 | |
| 5752 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5753 attributes %{ | |
| 5754 variable_size_instructions; // Fixed size instructions | |
| 5755 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5756 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5757 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5758 instruction_fetch_units = 1; // of 16 bytes | |
| 5759 | |
| 5760 // List of nop instructions | |
| 5761 nops( MachNop ); | |
| 5762 %} | |
| 5763 | |
| 5764 //----------RESOURCES---------------------------------------------------------- | |
| 5765 // Resources are the functional units available to the machine | |
| 5766 | |
| 5767 // Generic P2/P3 pipeline | |
| 5768 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5769 // 3 instructions decoded per cycle. | |
| 5770 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5771 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5772 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5773 MS0, MS1, MEM = MS0 | MS1, | |
| 5774 BR, FPU, | |
| 5775 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5776 | |
| 5777 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5778 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5779 | |
| 5780 // Generic P2/P3 pipeline | |
| 5781 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5782 | |
| 5783 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5784 // Pipeline Classes describe the stages in which input and output are | |
| 5785 // referenced by the hardware pipeline. | |
| 5786 | |
| 5787 // Naming convention: ialu or fpu | |
| 5788 // Then: _reg | |
| 5789 // Then: _reg if there is a 2nd register | |
| 5790 // Then: _long if it's a pair of instructions implementing a long | |
| 5791 // Then: _fat if it requires the big decoder | |
| 5792 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5793 | |
| 5794 // Integer ALU reg operation | |
| 5795 pipe_class ialu_reg(eRegI dst) %{ | |
| 5796 single_instruction; | |
| 5797 dst : S4(write); | |
| 5798 dst : S3(read); | |
| 5799 DECODE : S0; // any decoder | |
| 5800 ALU : S3; // any alu | |
| 5801 %} | |
| 5802 | |
| 5803 // Long ALU reg operation | |
| 5804 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5805 instruction_count(2); | |
| 5806 dst : S4(write); | |
| 5807 dst : S3(read); | |
| 5808 DECODE : S0(2); // any 2 decoders | |
| 5809 ALU : S3(2); // both alus | |
| 5810 %} | |
| 5811 | |
| 5812 // Integer ALU reg operation using big decoder | |
| 5813 pipe_class ialu_reg_fat(eRegI dst) %{ | |
| 5814 single_instruction; | |
| 5815 dst : S4(write); | |
| 5816 dst : S3(read); | |
| 5817 D0 : S0; // big decoder only | |
| 5818 ALU : S3; // any alu | |
| 5819 %} | |
| 5820 | |
| 5821 // Long ALU reg operation using big decoder | |
| 5822 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5823 instruction_count(2); | |
| 5824 dst : S4(write); | |
| 5825 dst : S3(read); | |
| 5826 D0 : S0(2); // big decoder only; twice | |
| 5827 ALU : S3(2); // any 2 alus | |
| 5828 %} | |
| 5829 | |
| 5830 // Integer ALU reg-reg operation | |
| 5831 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ | |
| 5832 single_instruction; | |
| 5833 dst : S4(write); | |
| 5834 src : S3(read); | |
| 5835 DECODE : S0; // any decoder | |
| 5836 ALU : S3; // any alu | |
| 5837 %} | |
| 5838 | |
| 5839 // Long ALU reg-reg operation | |
| 5840 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5841 instruction_count(2); | |
| 5842 dst : S4(write); | |
| 5843 src : S3(read); | |
| 5844 DECODE : S0(2); // any 2 decoders | |
| 5845 ALU : S3(2); // both alus | |
| 5846 %} | |
| 5847 | |
| 5848 // Integer ALU reg-reg operation | |
| 5849 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ | |
| 5850 single_instruction; | |
| 5851 dst : S4(write); | |
| 5852 src : S3(read); | |
| 5853 D0 : S0; // big decoder only | |
| 5854 ALU : S3; // any alu | |
| 5855 %} | |
| 5856 | |
| 5857 // Long ALU reg-reg operation | |
| 5858 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5859 instruction_count(2); | |
| 5860 dst : S4(write); | |
| 5861 src : S3(read); | |
| 5862 D0 : S0(2); // big decoder only; twice | |
| 5863 ALU : S3(2); // both alus | |
| 5864 %} | |
| 5865 | |
| 5866 // Integer ALU reg-mem operation | |
| 5867 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ | |
| 5868 single_instruction; | |
| 5869 dst : S5(write); | |
| 5870 mem : S3(read); | |
| 5871 D0 : S0; // big decoder only | |
| 5872 ALU : S4; // any alu | |
| 5873 MEM : S3; // any mem | |
| 5874 %} | |
| 5875 | |
| 5876 // Long ALU reg-mem operation | |
| 5877 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5878 instruction_count(2); | |
| 5879 dst : S5(write); | |
| 5880 mem : S3(read); | |
| 5881 D0 : S0(2); // big decoder only; twice | |
| 5882 ALU : S4(2); // any 2 alus | |
| 5883 MEM : S3(2); // both mems | |
| 5884 %} | |
| 5885 | |
| 5886 // Integer mem operation (prefetch) | |
| 5887 pipe_class ialu_mem(memory mem) | |
| 5888 %{ | |
| 5889 single_instruction; | |
| 5890 mem : S3(read); | |
| 5891 D0 : S0; // big decoder only | |
| 5892 MEM : S3; // any mem | |
| 5893 %} | |
| 5894 | |
| 5895 // Integer Store to Memory | |
| 5896 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ | |
| 5897 single_instruction; | |
| 5898 mem : S3(read); | |
| 5899 src : S5(read); | |
| 5900 D0 : S0; // big decoder only | |
| 5901 ALU : S4; // any alu | |
| 5902 MEM : S3; | |
| 5903 %} | |
| 5904 | |
| 5905 // Long Store to Memory | |
| 5906 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5907 instruction_count(2); | |
| 5908 mem : S3(read); | |
| 5909 src : S5(read); | |
| 5910 D0 : S0(2); // big decoder only; twice | |
| 5911 ALU : S4(2); // any 2 alus | |
| 5912 MEM : S3(2); // Both mems | |
| 5913 %} | |
| 5914 | |
| 5915 // Integer Store to Memory | |
| 5916 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5917 single_instruction; | |
| 5918 mem : S3(read); | |
| 5919 D0 : S0; // big decoder only | |
| 5920 ALU : S4; // any alu | |
| 5921 MEM : S3; | |
| 5922 %} | |
| 5923 | |
| 5924 // Integer ALU0 reg-reg operation | |
| 5925 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ | |
| 5926 single_instruction; | |
| 5927 dst : S4(write); | |
| 5928 src : S3(read); | |
| 5929 D0 : S0; // Big decoder only | |
| 5930 ALU0 : S3; // only alu0 | |
| 5931 %} | |
| 5932 | |
| 5933 // Integer ALU0 reg-mem operation | |
| 5934 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ | |
| 5935 single_instruction; | |
| 5936 dst : S5(write); | |
| 5937 mem : S3(read); | |
| 5938 D0 : S0; // big decoder only | |
| 5939 ALU0 : S4; // ALU0 only | |
| 5940 MEM : S3; // any mem | |
| 5941 %} | |
| 5942 | |
| 5943 // Integer ALU reg-reg operation | |
| 5944 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ | |
| 5945 single_instruction; | |
| 5946 cr : S4(write); | |
| 5947 src1 : S3(read); | |
| 5948 src2 : S3(read); | |
| 5949 DECODE : S0; // any decoder | |
| 5950 ALU : S3; // any alu | |
| 5951 %} | |
| 5952 | |
| 5953 // Integer ALU reg-imm operation | |
| 5954 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ | |
| 5955 single_instruction; | |
| 5956 cr : S4(write); | |
| 5957 src1 : S3(read); | |
| 5958 DECODE : S0; // any decoder | |
| 5959 ALU : S3; // any alu | |
| 5960 %} | |
| 5961 | |
| 5962 // Integer ALU reg-mem operation | |
| 5963 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ | |
| 5964 single_instruction; | |
| 5965 cr : S4(write); | |
| 5966 src1 : S3(read); | |
| 5967 src2 : S3(read); | |
| 5968 D0 : S0; // big decoder only | |
| 5969 ALU : S4; // any alu | |
| 5970 MEM : S3; | |
| 5971 %} | |
| 5972 | |
| 5973 // Conditional move reg-reg | |
| 5974 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ | |
| 5975 instruction_count(4); | |
| 5976 y : S4(read); | |
| 5977 q : S3(read); | |
| 5978 p : S3(read); | |
| 5979 DECODE : S0(4); // any decoder | |
| 5980 %} | |
| 5981 | |
| 5982 // Conditional move reg-reg | |
| 5983 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 5984 single_instruction; | |
| 5985 dst : S4(write); | |
| 5986 src : S3(read); | |
| 5987 cr : S3(read); | |
| 5988 DECODE : S0; // any decoder | |
| 5989 %} | |
| 5990 | |
| 5991 // Conditional move reg-mem | |
| 5992 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ | |
| 5993 single_instruction; | |
| 5994 dst : S4(write); | |
| 5995 src : S3(read); | |
| 5996 cr : S3(read); | |
| 5997 DECODE : S0; // any decoder | |
| 5998 MEM : S3; | |
| 5999 %} | |
| 6000 | |
| 6001 // Conditional move reg-reg long | |
| 6002 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 6003 single_instruction; | |
| 6004 dst : S4(write); | |
| 6005 src : S3(read); | |
| 6006 cr : S3(read); | |
| 6007 DECODE : S0(2); // any 2 decoders | |
| 6008 %} | |
| 6009 | |
| 6010 // Conditional move double reg-reg | |
| 6011 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ | |
| 6012 single_instruction; | |
| 6013 dst : S4(write); | |
| 6014 src : S3(read); | |
| 6015 cr : S3(read); | |
| 6016 DECODE : S0; // any decoder | |
| 6017 %} | |
| 6018 | |
| 6019 // Float reg-reg operation | |
| 6020 pipe_class fpu_reg(regD dst) %{ | |
| 6021 instruction_count(2); | |
| 6022 dst : S3(read); | |
| 6023 DECODE : S0(2); // any 2 decoders | |
| 6024 FPU : S3; | |
| 6025 %} | |
| 6026 | |
| 6027 // Float reg-reg operation | |
| 6028 pipe_class fpu_reg_reg(regD dst, regD src) %{ | |
| 6029 instruction_count(2); | |
| 6030 dst : S4(write); | |
| 6031 src : S3(read); | |
| 6032 DECODE : S0(2); // any 2 decoders | |
| 6033 FPU : S3; | |
| 6034 %} | |
| 6035 | |
| 6036 // Float reg-reg operation | |
| 6037 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 6038 instruction_count(3); | |
| 6039 dst : S4(write); | |
| 6040 src1 : S3(read); | |
| 6041 src2 : S3(read); | |
| 6042 DECODE : S0(3); // any 3 decoders | |
| 6043 FPU : S3(2); | |
| 6044 %} | |
| 6045 | |
| 6046 // Float reg-reg operation | |
| 6047 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ | |
| 6048 instruction_count(4); | |
| 6049 dst : S4(write); | |
| 6050 src1 : S3(read); | |
| 6051 src2 : S3(read); | |
| 6052 src3 : S3(read); | |
| 6053 DECODE : S0(4); // any 3 decoders | |
| 6054 FPU : S3(2); | |
| 6055 %} | |
| 6056 | |
| 6057 // Float reg-reg operation | |
| 6058 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ | |
| 6059 instruction_count(4); | |
| 6060 dst : S4(write); | |
| 6061 src1 : S3(read); | |
| 6062 src2 : S3(read); | |
| 6063 src3 : S3(read); | |
| 6064 DECODE : S1(3); // any 3 decoders | |
| 6065 D0 : S0; // Big decoder only | |
| 6066 FPU : S3(2); | |
| 6067 MEM : S3; | |
| 6068 %} | |
| 6069 | |
| 6070 // Float reg-mem operation | |
| 6071 pipe_class fpu_reg_mem(regD dst, memory mem) %{ | |
| 6072 instruction_count(2); | |
| 6073 dst : S5(write); | |
| 6074 mem : S3(read); | |
| 6075 D0 : S0; // big decoder only | |
| 6076 DECODE : S1; // any decoder for FPU POP | |
| 6077 FPU : S4; | |
| 6078 MEM : S3; // any mem | |
| 6079 %} | |
| 6080 | |
| 6081 // Float reg-mem operation | |
| 6082 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ | |
| 6083 instruction_count(3); | |
| 6084 dst : S5(write); | |
| 6085 src1 : S3(read); | |
| 6086 mem : S3(read); | |
| 6087 D0 : S0; // big decoder only | |
| 6088 DECODE : S1(2); // any decoder for FPU POP | |
| 6089 FPU : S4; | |
| 6090 MEM : S3; // any mem | |
| 6091 %} | |
| 6092 | |
| 6093 // Float mem-reg operation | |
| 6094 pipe_class fpu_mem_reg(memory mem, regD src) %{ | |
| 6095 instruction_count(2); | |
| 6096 src : S5(read); | |
| 6097 mem : S3(read); | |
| 6098 DECODE : S0; // any decoder for FPU PUSH | |
| 6099 D0 : S1; // big decoder only | |
| 6100 FPU : S4; | |
| 6101 MEM : S3; // any mem | |
| 6102 %} | |
| 6103 | |
| 6104 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ | |
| 6105 instruction_count(3); | |
| 6106 src1 : S3(read); | |
| 6107 src2 : S3(read); | |
| 6108 mem : S3(read); | |
| 6109 DECODE : S0(2); // any decoder for FPU PUSH | |
| 6110 D0 : S1; // big decoder only | |
| 6111 FPU : S4; | |
| 6112 MEM : S3; // any mem | |
| 6113 %} | |
| 6114 | |
| 6115 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ | |
| 6116 instruction_count(3); | |
| 6117 src1 : S3(read); | |
| 6118 src2 : S3(read); | |
| 6119 mem : S4(read); | |
| 6120 DECODE : S0; // any decoder for FPU PUSH | |
| 6121 D0 : S0(2); // big decoder only | |
| 6122 FPU : S4; | |
| 6123 MEM : S3(2); // any mem | |
| 6124 %} | |
| 6125 | |
| 6126 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 6127 instruction_count(2); | |
| 6128 src1 : S3(read); | |
| 6129 dst : S4(read); | |
| 6130 D0 : S0(2); // big decoder only | |
| 6131 MEM : S3(2); // any mem | |
| 6132 %} | |
| 6133 | |
| 6134 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 6135 instruction_count(3); | |
| 6136 src1 : S3(read); | |
| 6137 src2 : S3(read); | |
| 6138 dst : S4(read); | |
| 6139 D0 : S0(3); // big decoder only | |
| 6140 FPU : S4; | |
| 6141 MEM : S3(3); // any mem | |
| 6142 %} | |
| 6143 | |
| 6144 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ | |
| 6145 instruction_count(3); | |
| 6146 src1 : S4(read); | |
| 6147 mem : S4(read); | |
| 6148 DECODE : S0; // any decoder for FPU PUSH | |
| 6149 D0 : S0(2); // big decoder only | |
| 6150 FPU : S4; | |
| 6151 MEM : S3(2); // any mem | |
| 6152 %} | |
| 6153 | |
| 6154 // Float load constant | |
| 6155 pipe_class fpu_reg_con(regD dst) %{ | |
| 6156 instruction_count(2); | |
| 6157 dst : S5(write); | |
| 6158 D0 : S0; // big decoder only for the load | |
| 6159 DECODE : S1; // any decoder for FPU POP | |
| 6160 FPU : S4; | |
| 6161 MEM : S3; // any mem | |
| 6162 %} | |
| 6163 | |
| 6164 // Float load constant | |
| 6165 pipe_class fpu_reg_reg_con(regD dst, regD src) %{ | |
| 6166 instruction_count(3); | |
| 6167 dst : S5(write); | |
| 6168 src : S3(read); | |
| 6169 D0 : S0; // big decoder only for the load | |
| 6170 DECODE : S1(2); // any decoder for FPU POP | |
| 6171 FPU : S4; | |
| 6172 MEM : S3; // any mem | |
| 6173 %} | |
| 6174 | |
| 6175 // UnConditional branch | |
| 6176 pipe_class pipe_jmp( label labl ) %{ | |
| 6177 single_instruction; | |
| 6178 BR : S3; | |
| 6179 %} | |
| 6180 | |
| 6181 // Conditional branch | |
| 6182 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 6183 single_instruction; | |
| 6184 cr : S1(read); | |
| 6185 BR : S3; | |
| 6186 %} | |
| 6187 | |
| 6188 // Allocation idiom | |
| 6189 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 6190 instruction_count(1); force_serialization; | |
| 6191 fixed_latency(6); | |
| 6192 heap_ptr : S3(read); | |
| 6193 DECODE : S0(3); | |
| 6194 D0 : S2; | |
| 6195 MEM : S3; | |
| 6196 ALU : S3(2); | |
| 6197 dst : S5(write); | |
| 6198 BR : S5; | |
| 6199 %} | |
| 6200 | |
| 6201 // Generic big/slow expanded idiom | |
| 6202 pipe_class pipe_slow( ) %{ | |
| 6203 instruction_count(10); multiple_bundles; force_serialization; | |
| 6204 fixed_latency(100); | |
| 6205 D0 : S0(2); | |
| 6206 MEM : S3(2); | |
| 6207 %} | |
| 6208 | |
| 6209 // The real do-nothing guy | |
| 6210 pipe_class empty( ) %{ | |
| 6211 instruction_count(0); | |
| 6212 %} | |
| 6213 | |
| 6214 // Define the class for the Nop node | |
| 6215 define %{ | |
| 6216 MachNop = empty; | |
| 6217 %} | |
| 6218 | |
| 6219 %} | |
| 6220 | |
| 6221 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6222 // | |
| 6223 // match -- States which machine-independent subtree may be replaced | |
| 6224 // by this instruction. | |
| 6225 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6226 // selection to identify a minimum cost tree of machine | |
| 6227 // instructions that matches a tree of machine-independent | |
| 6228 // instructions. | |
| 6229 // format -- A string providing the disassembly for this instruction. | |
| 6230 // The value of an instruction's operand may be inserted | |
| 6231 // by referring to it with a '$' prefix. | |
| 6232 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6233 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6234 // respectively. The primary opcode is commonly used to | |
| 6235 // indicate the type of machine instruction, while secondary | |
| 6236 // and tertiary are often used for prefix options or addressing | |
| 6237 // modes. | |
| 6238 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6239 // name must have been defined in an 'enc_class' specification | |
| 6240 // in the encode section of the architecture description. | |
| 6241 | |
| 6242 //----------BSWAP-Instruction-------------------------------------------------- | |
| 6243 instruct bytes_reverse_int(eRegI dst) %{ | |
| 6244 match(Set dst (ReverseBytesI dst)); | |
| 6245 | |
| 6246 format %{ "BSWAP $dst" %} | |
| 6247 opcode(0x0F, 0xC8); | |
| 6248 ins_encode( OpcP, OpcSReg(dst) ); | |
| 6249 ins_pipe( ialu_reg ); | |
| 6250 %} | |
| 6251 | |
| 6252 instruct bytes_reverse_long(eRegL dst) %{ | |
| 6253 match(Set dst (ReverseBytesL dst)); | |
| 6254 | |
| 6255 format %{ "BSWAP $dst.lo\n\t" | |
| 6256 "BSWAP $dst.hi\n\t" | |
| 6257 "XCHG $dst.lo $dst.hi" %} | |
| 6258 | |
| 6259 ins_cost(125); | |
| 6260 ins_encode( bswap_long_bytes(dst) ); | |
| 6261 ins_pipe( ialu_reg_reg); | |
| 6262 %} | |
| 6263 | |
|
1396
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|
6264 instruct bytes_reverse_unsigned_short(eRegI dst) %{ |
|
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|
6265 match(Set dst (ReverseBytesUS dst)); |
|
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changeset
|
6266 |
|
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|
6267 format %{ "BSWAP $dst\n\t" |
|
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|
6268 "SHR $dst,16\n\t" %} |
|
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|
6269 ins_encode %{ |
|
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|
6270 __ bswapl($dst$$Register); |
|
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changeset
|
6271 __ shrl($dst$$Register, 16); |
|
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|
6272 %} |
|
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|
6273 ins_pipe( ialu_reg ); |
|
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|
6274 %} |
|
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|
6275 |
|
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|
6276 instruct bytes_reverse_short(eRegI dst) %{ |
|
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|
6277 match(Set dst (ReverseBytesS dst)); |
|
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changeset
|
6278 |
|
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changeset
|
6279 format %{ "BSWAP $dst\n\t" |
|
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|
6280 "SAR $dst,16\n\t" %} |
|
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|
6281 ins_encode %{ |
|
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|
6282 __ bswapl($dst$$Register); |
|
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|
6283 __ sarl($dst$$Register, 16); |
|
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|
6284 %} |
|
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changeset
|
6285 ins_pipe( ialu_reg ); |
|
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|
6286 %} |
|
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|
6287 |
| 0 | 6288 |
|
775
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|
6289 //---------- Zeros Count Instructions ------------------------------------------ |
|
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|
6290 |
|
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|
6291 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
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|
6292 predicate(UseCountLeadingZerosInstruction); |
|
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|
6293 match(Set dst (CountLeadingZerosI src)); |
|
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|
6294 effect(KILL cr); |
|
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|
6295 |
|
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|
6296 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
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|
6297 ins_encode %{ |
|
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|
6298 __ lzcntl($dst$$Register, $src$$Register); |
|
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|
6299 %} |
|
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|
6300 ins_pipe(ialu_reg); |
|
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|
6301 %} |
|
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|
6302 |
|
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|
6303 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
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|
6304 predicate(!UseCountLeadingZerosInstruction); |
|
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|
6305 match(Set dst (CountLeadingZerosI src)); |
|
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|
6306 effect(KILL cr); |
|
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|
6307 |
|
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|
6308 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
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|
6309 "JNZ skip\n\t" |
|
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|
6310 "MOV $dst, -1\n" |
|
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changeset
|
6311 "skip:\n\t" |
|
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|
6312 "NEG $dst\n\t" |
|
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|
6313 "ADD $dst, 31" %} |
|
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|
6314 ins_encode %{ |
|
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|
6315 Register Rdst = $dst$$Register; |
|
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|
6316 Register Rsrc = $src$$Register; |
|
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|
6317 Label skip; |
|
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|
6318 __ bsrl(Rdst, Rsrc); |
|
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|
6319 __ jccb(Assembler::notZero, skip); |
|
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|
6320 __ movl(Rdst, -1); |
|
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|
6321 __ bind(skip); |
|
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|
6322 __ negl(Rdst); |
|
93c14e5562c4
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|
6323 __ addl(Rdst, BitsPerInt - 1); |
|
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|
6324 %} |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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changeset
|
6325 ins_pipe(ialu_reg); |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
6326 %} |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
6327 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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changeset
|
6328 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
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changeset
|
6329 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
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changeset
|
6330 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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changeset
|
6331 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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changeset
|
6332 |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
6333 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6334 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6335 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6336 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6337 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6338 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6339 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6340 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6341 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6342 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6343 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6344 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6345 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6346 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6347 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6348 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6349 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6350 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6351 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6352 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6353 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6354 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6355 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6356 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6357 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6358 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6359 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6360 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6361 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6362 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6363 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6364 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6365 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6366 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6367 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6368 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6369 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6370 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6371 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6372 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6373 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6374 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6375 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6376 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6377 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6378 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6379 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6380 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6381 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6382 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6383 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6384 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6385 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6386 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6387 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6388 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6389 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6390 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6391 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6392 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6393 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6394 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6395 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6396 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6397 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6398 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6399 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6400 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6401 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6402 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6403 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6404 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6405 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6406 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6407 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6408 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6409 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6410 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6411 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6412 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6413 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6414 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6415 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6416 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6417 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6418 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6419 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6420 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6421 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6422 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6423 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6424 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6425 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6426 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6427 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6428 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6429 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6430 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6431 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6432 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6433 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6434 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6435 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
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|
6436 //---------- Population Count Instructions ------------------------------------- |
|
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6437 |
|
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6438 instruct popCountI(eRegI dst, eRegI src) %{ |
|
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|
6439 predicate(UsePopCountInstruction); |
|
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6440 match(Set dst (PopCountI src)); |
|
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|
6441 |
|
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|
6442 format %{ "POPCNT $dst, $src" %} |
|
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6443 ins_encode %{ |
|
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|
6444 __ popcntl($dst$$Register, $src$$Register); |
|
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|
6445 %} |
|
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|
6446 ins_pipe(ialu_reg); |
|
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|
6447 %} |
|
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|
6448 |
|
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|
6449 instruct popCountI_mem(eRegI dst, memory mem) %{ |
|
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|
6450 predicate(UsePopCountInstruction); |
|
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|
6451 match(Set dst (PopCountI (LoadI mem))); |
|
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|
6452 |
|
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|
6453 format %{ "POPCNT $dst, $mem" %} |
|
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|
6454 ins_encode %{ |
|
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|
6455 __ popcntl($dst$$Register, $mem$$Address); |
|
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|
6456 %} |
|
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|
6457 ins_pipe(ialu_reg); |
|
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|
6458 %} |
|
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|
6459 |
|
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|
6460 // Note: Long.bitCount(long) returns an int. |
|
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6461 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
6462 predicate(UsePopCountInstruction); |
|
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|
6463 match(Set dst (PopCountL src)); |
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|
6464 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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|
6465 |
|
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|
6466 format %{ "POPCNT $dst, $src.lo\n\t" |
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|
6467 "POPCNT $tmp, $src.hi\n\t" |
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|
6468 "ADD $dst, $tmp" %} |
|
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|
6469 ins_encode %{ |
|
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|
6470 __ popcntl($dst$$Register, $src$$Register); |
|
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|
6471 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
6472 __ addl($dst$$Register, $tmp$$Register); |
|
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|
6473 %} |
|
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|
6474 ins_pipe(ialu_reg); |
|
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|
6475 %} |
|
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|
6476 |
|
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|
6477 // Note: Long.bitCount(long) returns an int. |
|
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6478 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ |
|
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|
6479 predicate(UsePopCountInstruction); |
|
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|
6480 match(Set dst (PopCountL (LoadL mem))); |
|
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|
6481 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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|
6482 |
|
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|
6483 format %{ "POPCNT $dst, $mem\n\t" |
|
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|
6484 "POPCNT $tmp, $mem+4\n\t" |
|
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|
6485 "ADD $dst, $tmp" %} |
|
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|
6486 ins_encode %{ |
|
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|
6487 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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|
6488 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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|
6489 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); |
|
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|
6490 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); |
|
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|
6491 __ addl($dst$$Register, $tmp$$Register); |
|
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|
6492 %} |
|
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|
6493 ins_pipe(ialu_reg); |
|
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|
6494 %} |
|
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|
6495 |
|
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|
6496 |
| 0 | 6497 //----------Load/Store/Move Instructions--------------------------------------- |
| 6498 //----------Load Instructions-------------------------------------------------- | |
| 6499 // Load Byte (8bit signed) | |
| 6500 instruct loadB(xRegI dst, memory mem) %{ | |
| 6501 match(Set dst (LoadB mem)); | |
| 6502 | |
| 6503 ins_cost(125); | |
| 624 | 6504 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 6505 | |
| 6506 ins_encode %{ | |
| 6507 __ movsbl($dst$$Register, $mem$$Address); | |
| 6508 %} | |
| 6509 | |
| 6510 ins_pipe(ialu_reg_mem); | |
| 6511 %} | |
| 6512 | |
| 6513 // Load Byte (8bit signed) into Long Register | |
| 824 | 6514 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6515 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 6516 effect(KILL cr); |
| 624 | 6517 |
| 6518 ins_cost(375); | |
| 6519 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 6520 "MOV $dst.hi,$dst.lo\n\t" | |
| 6521 "SAR $dst.hi,7" %} | |
| 6522 | |
| 6523 ins_encode %{ | |
| 6524 __ movsbl($dst$$Register, $mem$$Address); | |
| 6525 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6526 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 6527 %} | |
| 6528 | |
| 6529 ins_pipe(ialu_reg_mem); | |
| 6530 %} | |
| 6531 | |
| 6532 // Load Unsigned Byte (8bit UNsigned) | |
| 6533 instruct loadUB(xRegI dst, memory mem) %{ | |
| 6534 match(Set dst (LoadUB mem)); | |
| 0 | 6535 |
| 6536 ins_cost(125); | |
| 624 | 6537 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 6538 | |
| 6539 ins_encode %{ | |
| 6540 __ movzbl($dst$$Register, $mem$$Address); | |
| 6541 %} | |
| 6542 | |
| 6543 ins_pipe(ialu_reg_mem); | |
| 6544 %} | |
| 6545 | |
| 6546 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 6547 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6548 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 6549 effect(KILL cr); |
| 624 | 6550 |
| 6551 ins_cost(250); | |
| 6552 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 6553 "XOR $dst.hi,$dst.hi" %} | |
| 6554 | |
| 6555 ins_encode %{ | |
| 824 | 6556 Register Rdst = $dst$$Register; |
| 6557 __ movzbl(Rdst, $mem$$Address); | |
| 6558 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6559 %} | |
| 6560 | |
| 6561 ins_pipe(ialu_reg_mem); | |
| 6562 %} | |
| 6563 | |
| 6564 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 6565 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 6566 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 6567 effect(KILL cr); | |
| 6568 | |
| 6569 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 6570 "XOR $dst.hi,$dst.hi\n\t" | |
| 6571 "AND $dst.lo,$mask" %} | |
| 6572 ins_encode %{ | |
| 6573 Register Rdst = $dst$$Register; | |
| 6574 __ movzbl(Rdst, $mem$$Address); | |
| 6575 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6576 __ andl(Rdst, $mask$$constant); | |
| 6577 %} | |
| 624 | 6578 ins_pipe(ialu_reg_mem); |
| 6579 %} | |
| 6580 | |
| 6581 // Load Short (16bit signed) | |
| 6582 instruct loadS(eRegI dst, memory mem) %{ | |
| 6583 match(Set dst (LoadS mem)); | |
| 6584 | |
| 6585 ins_cost(125); | |
| 6586 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 6587 | |
| 6588 ins_encode %{ | |
| 6589 __ movswl($dst$$Register, $mem$$Address); | |
| 6590 %} | |
| 6591 | |
| 6592 ins_pipe(ialu_reg_mem); | |
| 6593 %} | |
| 6594 | |
| 785 | 6595 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 6596 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6597 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 6598 | |
| 6599 ins_cost(125); | |
| 6600 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 6601 ins_encode %{ | |
| 6602 __ movsbl($dst$$Register, $mem$$Address); | |
| 6603 %} | |
| 6604 ins_pipe(ialu_reg_mem); | |
| 6605 %} | |
| 6606 | |
| 624 | 6607 // Load Short (16bit signed) into Long Register |
| 824 | 6608 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6609 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 6610 effect(KILL cr); |
| 624 | 6611 |
| 6612 ins_cost(375); | |
| 6613 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 6614 "MOV $dst.hi,$dst.lo\n\t" | |
| 6615 "SAR $dst.hi,15" %} | |
| 6616 | |
| 6617 ins_encode %{ | |
| 6618 __ movswl($dst$$Register, $mem$$Address); | |
| 6619 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6620 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 6621 %} | |
| 6622 | |
| 6623 ins_pipe(ialu_reg_mem); | |
| 0 | 6624 %} |
| 6625 | |
|
558
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|
6626 // Load Unsigned Short/Char (16bit unsigned) |
|
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|
6627 instruct loadUS(eRegI dst, memory mem) %{ |
|
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|
6628 match(Set dst (LoadUS mem)); |
| 0 | 6629 |
| 6630 ins_cost(125); | |
| 624 | 6631 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 6632 | |
| 6633 ins_encode %{ | |
| 6634 __ movzwl($dst$$Register, $mem$$Address); | |
| 6635 %} | |
| 6636 | |
| 6637 ins_pipe(ialu_reg_mem); | |
| 6638 %} | |
| 6639 | |
| 785 | 6640 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 6641 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6642 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 6643 | |
| 6644 ins_cost(125); | |
| 6645 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 6646 ins_encode %{ | |
| 6647 __ movsbl($dst$$Register, $mem$$Address); | |
| 6648 %} | |
| 6649 ins_pipe(ialu_reg_mem); | |
| 6650 %} | |
| 6651 | |
| 624 | 6652 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 6653 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6654 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 6655 effect(KILL cr); |
| 624 | 6656 |
| 6657 ins_cost(250); | |
| 6658 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 6659 "XOR $dst.hi,$dst.hi" %} | |
| 6660 | |
| 6661 ins_encode %{ | |
| 6662 __ movzwl($dst$$Register, $mem$$Address); | |
| 6663 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6664 %} | |
| 6665 | |
| 6666 ins_pipe(ialu_reg_mem); | |
| 0 | 6667 %} |
| 6668 | |
| 824 | 6669 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 6670 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6671 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6672 effect(KILL cr); | |
| 6673 | |
| 6674 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 6675 "XOR $dst.hi,$dst.hi" %} | |
| 6676 ins_encode %{ | |
| 6677 Register Rdst = $dst$$Register; | |
| 6678 __ movzbl(Rdst, $mem$$Address); | |
| 6679 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6680 %} | |
| 6681 ins_pipe(ialu_reg_mem); | |
| 6682 %} | |
| 6683 | |
| 6684 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 6685 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 6686 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6687 effect(KILL cr); | |
| 6688 | |
| 6689 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6690 "XOR $dst.hi,$dst.hi\n\t" | |
| 6691 "AND $dst.lo,$mask" %} | |
| 6692 ins_encode %{ | |
| 6693 Register Rdst = $dst$$Register; | |
| 6694 __ movzwl(Rdst, $mem$$Address); | |
| 6695 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6696 __ andl(Rdst, $mask$$constant); | |
| 6697 %} | |
| 6698 ins_pipe(ialu_reg_mem); | |
| 6699 %} | |
| 6700 | |
| 0 | 6701 // Load Integer |
| 6702 instruct loadI(eRegI dst, memory mem) %{ | |
| 6703 match(Set dst (LoadI mem)); | |
| 6704 | |
| 6705 ins_cost(125); | |
| 624 | 6706 format %{ "MOV $dst,$mem\t# int" %} |
| 6707 | |
| 6708 ins_encode %{ | |
| 6709 __ movl($dst$$Register, $mem$$Address); | |
| 6710 %} | |
| 6711 | |
| 6712 ins_pipe(ialu_reg_mem); | |
| 6713 %} | |
| 6714 | |
| 785 | 6715 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6716 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6717 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6718 | |
| 6719 ins_cost(125); | |
| 6720 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6721 ins_encode %{ | |
| 6722 __ movsbl($dst$$Register, $mem$$Address); | |
| 6723 %} | |
| 6724 ins_pipe(ialu_reg_mem); | |
| 6725 %} | |
| 6726 | |
| 6727 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6728 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ | |
| 6729 match(Set dst (AndI (LoadI mem) mask)); | |
| 6730 | |
| 6731 ins_cost(125); | |
| 6732 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6733 ins_encode %{ | |
| 6734 __ movzbl($dst$$Register, $mem$$Address); | |
| 6735 %} | |
| 6736 ins_pipe(ialu_reg_mem); | |
| 6737 %} | |
| 6738 | |
| 6739 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6740 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6741 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6742 | |
| 6743 ins_cost(125); | |
| 6744 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6745 ins_encode %{ | |
| 6746 __ movswl($dst$$Register, $mem$$Address); | |
| 6747 %} | |
| 6748 ins_pipe(ialu_reg_mem); | |
| 6749 %} | |
| 6750 | |
| 6751 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6752 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ | |
| 6753 match(Set dst (AndI (LoadI mem) mask)); | |
| 6754 | |
| 6755 ins_cost(125); | |
| 6756 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6757 ins_encode %{ | |
| 6758 __ movzwl($dst$$Register, $mem$$Address); | |
| 6759 %} | |
| 6760 ins_pipe(ialu_reg_mem); | |
| 6761 %} | |
| 6762 | |
| 624 | 6763 // Load Integer into Long Register |
| 824 | 6764 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6765 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6766 effect(KILL cr); |
| 624 | 6767 |
| 6768 ins_cost(375); | |
| 6769 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6770 "MOV $dst.hi,$dst.lo\n\t" | |
| 6771 "SAR $dst.hi,31" %} | |
| 6772 | |
| 6773 ins_encode %{ | |
| 6774 __ movl($dst$$Register, $mem$$Address); | |
| 6775 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6776 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6777 %} | |
| 6778 | |
| 6779 ins_pipe(ialu_reg_mem); | |
| 6780 %} | |
| 6781 | |
| 824 | 6782 // Load Integer with mask 0xFF into Long Register |
| 6783 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6784 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6785 effect(KILL cr); | |
| 6786 | |
| 6787 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6788 "XOR $dst.hi,$dst.hi" %} | |
| 6789 ins_encode %{ | |
| 6790 Register Rdst = $dst$$Register; | |
| 6791 __ movzbl(Rdst, $mem$$Address); | |
| 6792 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6793 %} | |
| 6794 ins_pipe(ialu_reg_mem); | |
| 6795 %} | |
| 6796 | |
| 6797 // Load Integer with mask 0xFFFF into Long Register | |
| 6798 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6799 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6800 effect(KILL cr); | |
| 6801 | |
| 6802 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6803 "XOR $dst.hi,$dst.hi" %} | |
| 6804 ins_encode %{ | |
| 6805 Register Rdst = $dst$$Register; | |
| 6806 __ movzwl(Rdst, $mem$$Address); | |
| 6807 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6808 %} | |
| 6809 ins_pipe(ialu_reg_mem); | |
| 6810 %} | |
| 6811 | |
| 6812 // Load Integer with 32-bit mask into Long Register | |
| 6813 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6814 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6815 effect(KILL cr); | |
| 6816 | |
| 6817 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6818 "XOR $dst.hi,$dst.hi\n\t" | |
| 6819 "AND $dst.lo,$mask" %} | |
| 6820 ins_encode %{ | |
| 6821 Register Rdst = $dst$$Register; | |
| 6822 __ movl(Rdst, $mem$$Address); | |
| 6823 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6824 __ andl(Rdst, $mask$$constant); | |
| 6825 %} | |
| 6826 ins_pipe(ialu_reg_mem); | |
| 6827 %} | |
| 6828 | |
| 624 | 6829 // Load Unsigned Integer into Long Register |
| 824 | 6830 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6831 match(Set dst (LoadUI2L mem)); |
| 824 | 6832 effect(KILL cr); |
| 624 | 6833 |
| 6834 ins_cost(250); | |
| 6835 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6836 "XOR $dst.hi,$dst.hi" %} | |
| 6837 | |
| 6838 ins_encode %{ | |
| 6839 __ movl($dst$$Register, $mem$$Address); | |
| 6840 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6841 %} | |
| 6842 | |
| 6843 ins_pipe(ialu_reg_mem); | |
| 0 | 6844 %} |
| 6845 | |
| 6846 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6847 // register to ESI | |
| 6848 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6849 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6850 match(Set dst (LoadL mem)); | |
| 6851 | |
| 6852 ins_cost(250); | |
| 624 | 6853 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6854 "MOV $dst.hi,$mem+4" %} |
| 624 | 6855 |
| 6856 ins_encode %{ | |
| 6857 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); | |
| 6858 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); | |
| 6859 __ movl($dst$$Register, Amemlo); | |
| 6860 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6861 %} | |
| 6862 | |
| 6863 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6864 %} |
| 6865 | |
| 6866 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6867 // then store it down to the stack and reload on the int | |
| 6868 // side. | |
| 6869 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6870 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6871 match(Set dst (LoadL mem)); | |
| 6872 | |
| 6873 ins_cost(200); | |
| 6874 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6875 "FISTp $dst" %} | |
| 6876 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6877 ins_pipe( fpu_reg_mem ); | |
| 6878 %} | |
| 6879 | |
| 6880 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ | |
| 6881 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6882 match(Set dst (LoadL mem)); | |
| 6883 effect(TEMP tmp); | |
| 6884 ins_cost(180); | |
| 6885 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6886 "MOVSD $dst,$tmp" %} | |
| 6887 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 6888 ins_pipe( pipe_slow ); | |
| 6889 %} | |
| 6890 | |
| 6891 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ | |
| 6892 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6893 match(Set dst (LoadL mem)); | |
| 6894 effect(TEMP tmp); | |
| 6895 ins_cost(160); | |
| 6896 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6897 "MOVD $dst.lo,$tmp\n\t" | |
| 6898 "PSRLQ $tmp,32\n\t" | |
| 6899 "MOVD $dst.hi,$tmp" %} | |
| 6900 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 6901 ins_pipe( pipe_slow ); | |
| 6902 %} | |
| 6903 | |
| 6904 // Load Range | |
| 6905 instruct loadRange(eRegI dst, memory mem) %{ | |
| 6906 match(Set dst (LoadRange mem)); | |
| 6907 | |
| 6908 ins_cost(125); | |
| 6909 format %{ "MOV $dst,$mem" %} | |
| 6910 opcode(0x8B); | |
| 6911 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6912 ins_pipe( ialu_reg_mem ); | |
| 6913 %} | |
| 6914 | |
| 6915 | |
| 6916 // Load Pointer | |
| 6917 instruct loadP(eRegP dst, memory mem) %{ | |
| 6918 match(Set dst (LoadP mem)); | |
| 6919 | |
| 6920 ins_cost(125); | |
| 6921 format %{ "MOV $dst,$mem" %} | |
| 6922 opcode(0x8B); | |
| 6923 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6924 ins_pipe( ialu_reg_mem ); | |
| 6925 %} | |
| 6926 | |
| 6927 // Load Klass Pointer | |
| 6928 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6929 match(Set dst (LoadKlass mem)); | |
| 6930 | |
| 6931 ins_cost(125); | |
| 6932 format %{ "MOV $dst,$mem" %} | |
| 6933 opcode(0x8B); | |
| 6934 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6935 ins_pipe( ialu_reg_mem ); | |
| 6936 %} | |
| 6937 | |
| 6938 // Load Double | |
| 6939 instruct loadD(regD dst, memory mem) %{ | |
| 6940 predicate(UseSSE<=1); | |
| 6941 match(Set dst (LoadD mem)); | |
| 6942 | |
| 6943 ins_cost(150); | |
| 6944 format %{ "FLD_D ST,$mem\n\t" | |
| 6945 "FSTP $dst" %} | |
| 6946 opcode(0xDD); /* DD /0 */ | |
| 6947 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6948 Pop_Reg_D(dst) ); | |
| 6949 ins_pipe( fpu_reg_mem ); | |
| 6950 %} | |
| 6951 | |
| 6952 // Load Double to XMM | |
| 6953 instruct loadXD(regXD dst, memory mem) %{ | |
| 6954 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 6955 match(Set dst (LoadD mem)); | |
| 6956 ins_cost(145); | |
| 6957 format %{ "MOVSD $dst,$mem" %} | |
| 6958 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6959 ins_pipe( pipe_slow ); | |
| 6960 %} | |
| 6961 | |
| 6962 instruct loadXD_partial(regXD dst, memory mem) %{ | |
| 6963 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 6964 match(Set dst (LoadD mem)); | |
| 6965 ins_cost(145); | |
| 6966 format %{ "MOVLPD $dst,$mem" %} | |
| 6967 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); | |
| 6968 ins_pipe( pipe_slow ); | |
| 6969 %} | |
| 6970 | |
| 6971 // Load to XMM register (single-precision floating point) | |
| 6972 // MOVSS instruction | |
| 6973 instruct loadX(regX dst, memory mem) %{ | |
| 6974 predicate(UseSSE>=1); | |
| 6975 match(Set dst (LoadF mem)); | |
| 6976 ins_cost(145); | |
| 6977 format %{ "MOVSS $dst,$mem" %} | |
| 6978 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6979 ins_pipe( pipe_slow ); | |
| 6980 %} | |
| 6981 | |
| 6982 // Load Float | |
| 6983 instruct loadF(regF dst, memory mem) %{ | |
| 6984 predicate(UseSSE==0); | |
| 6985 match(Set dst (LoadF mem)); | |
| 6986 | |
| 6987 ins_cost(150); | |
| 6988 format %{ "FLD_S ST,$mem\n\t" | |
| 6989 "FSTP $dst" %} | |
| 6990 opcode(0xD9); /* D9 /0 */ | |
| 6991 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6992 Pop_Reg_F(dst) ); | |
| 6993 ins_pipe( fpu_reg_mem ); | |
| 6994 %} | |
| 6995 | |
| 6996 // Load Aligned Packed Byte to XMM register | |
| 6997 instruct loadA8B(regXD dst, memory mem) %{ | |
| 6998 predicate(UseSSE>=1); | |
| 6999 match(Set dst (Load8B mem)); | |
| 7000 ins_cost(125); | |
| 7001 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 7002 ins_encode( movq_ld(dst, mem)); | |
| 7003 ins_pipe( pipe_slow ); | |
| 7004 %} | |
| 7005 | |
| 7006 // Load Aligned Packed Short to XMM register | |
| 7007 instruct loadA4S(regXD dst, memory mem) %{ | |
| 7008 predicate(UseSSE>=1); | |
| 7009 match(Set dst (Load4S mem)); | |
| 7010 ins_cost(125); | |
| 7011 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 7012 ins_encode( movq_ld(dst, mem)); | |
| 7013 ins_pipe( pipe_slow ); | |
| 7014 %} | |
| 7015 | |
| 7016 // Load Aligned Packed Char to XMM register | |
| 7017 instruct loadA4C(regXD dst, memory mem) %{ | |
| 7018 predicate(UseSSE>=1); | |
| 7019 match(Set dst (Load4C mem)); | |
| 7020 ins_cost(125); | |
| 7021 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 7022 ins_encode( movq_ld(dst, mem)); | |
| 7023 ins_pipe( pipe_slow ); | |
| 7024 %} | |
| 7025 | |
| 7026 // Load Aligned Packed Integer to XMM register | |
| 7027 instruct load2IU(regXD dst, memory mem) %{ | |
| 7028 predicate(UseSSE>=1); | |
| 7029 match(Set dst (Load2I mem)); | |
| 7030 ins_cost(125); | |
| 7031 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 7032 ins_encode( movq_ld(dst, mem)); | |
| 7033 ins_pipe( pipe_slow ); | |
| 7034 %} | |
| 7035 | |
| 7036 // Load Aligned Packed Single to XMM | |
| 7037 instruct loadA2F(regXD dst, memory mem) %{ | |
| 7038 predicate(UseSSE>=1); | |
| 7039 match(Set dst (Load2F mem)); | |
| 7040 ins_cost(145); | |
| 7041 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 7042 ins_encode( movq_ld(dst, mem)); | |
| 7043 ins_pipe( pipe_slow ); | |
| 7044 %} | |
| 7045 | |
| 7046 // Load Effective Address | |
| 7047 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 7048 match(Set dst mem); | |
| 7049 | |
| 7050 ins_cost(110); | |
| 7051 format %{ "LEA $dst,$mem" %} | |
| 7052 opcode(0x8D); | |
| 7053 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7054 ins_pipe( ialu_reg_reg_fat ); | |
| 7055 %} | |
| 7056 | |
| 7057 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 7058 match(Set dst mem); | |
| 7059 | |
| 7060 ins_cost(110); | |
| 7061 format %{ "LEA $dst,$mem" %} | |
| 7062 opcode(0x8D); | |
| 7063 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7064 ins_pipe( ialu_reg_reg_fat ); | |
| 7065 %} | |
| 7066 | |
| 7067 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 7068 match(Set dst mem); | |
| 7069 | |
| 7070 ins_cost(110); | |
| 7071 format %{ "LEA $dst,$mem" %} | |
| 7072 opcode(0x8D); | |
| 7073 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7074 ins_pipe( ialu_reg_reg_fat ); | |
| 7075 %} | |
| 7076 | |
| 7077 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 7078 match(Set dst mem); | |
| 7079 | |
| 7080 ins_cost(110); | |
| 7081 format %{ "LEA $dst,$mem" %} | |
| 7082 opcode(0x8D); | |
| 7083 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7084 ins_pipe( ialu_reg_reg_fat ); | |
| 7085 %} | |
| 7086 | |
| 7087 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 7088 match(Set dst mem); | |
| 7089 | |
| 7090 ins_cost(110); | |
| 7091 format %{ "LEA $dst,$mem" %} | |
| 7092 opcode(0x8D); | |
| 7093 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7094 ins_pipe( ialu_reg_reg_fat ); | |
| 7095 %} | |
| 7096 | |
| 7097 // Load Constant | |
| 7098 instruct loadConI(eRegI dst, immI src) %{ | |
| 7099 match(Set dst src); | |
| 7100 | |
| 7101 format %{ "MOV $dst,$src" %} | |
| 7102 ins_encode( LdImmI(dst, src) ); | |
| 7103 ins_pipe( ialu_reg_fat ); | |
| 7104 %} | |
| 7105 | |
| 7106 // Load Constant zero | |
| 7107 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ | |
| 7108 match(Set dst src); | |
| 7109 effect(KILL cr); | |
| 7110 | |
| 7111 ins_cost(50); | |
| 7112 format %{ "XOR $dst,$dst" %} | |
| 7113 opcode(0x33); /* + rd */ | |
| 7114 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 7115 ins_pipe( ialu_reg ); | |
| 7116 %} | |
| 7117 | |
| 7118 instruct loadConP(eRegP dst, immP src) %{ | |
| 7119 match(Set dst src); | |
| 7120 | |
| 7121 format %{ "MOV $dst,$src" %} | |
| 7122 opcode(0xB8); /* + rd */ | |
| 7123 ins_encode( LdImmP(dst, src) ); | |
| 7124 ins_pipe( ialu_reg_fat ); | |
| 7125 %} | |
| 7126 | |
| 7127 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 7128 match(Set dst src); | |
| 7129 effect(KILL cr); | |
| 7130 ins_cost(200); | |
| 7131 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 7132 "MOV $dst.hi,$src.hi" %} | |
| 7133 opcode(0xB8); | |
| 7134 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 7135 ins_pipe( ialu_reg_long_fat ); | |
| 7136 %} | |
| 7137 | |
| 7138 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 7139 match(Set dst src); | |
| 7140 effect(KILL cr); | |
| 7141 ins_cost(150); | |
| 7142 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 7143 "XOR $dst.hi,$dst.hi" %} | |
| 7144 opcode(0x33,0x33); | |
| 7145 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 7146 ins_pipe( ialu_reg_long ); | |
| 7147 %} | |
| 7148 | |
| 7149 // The instruction usage is guarded by predicate in operand immF(). | |
| 2008 | 7150 instruct loadConF(regF dst, immF con) %{ |
| 7151 match(Set dst con); | |
| 7152 ins_cost(125); | |
| 7153 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 7154 "FSTP $dst" %} | |
| 7155 ins_encode %{ | |
| 7156 __ fld_s($constantaddress($con)); | |
| 7157 __ fstp_d($dst$$reg); | |
| 7158 %} | |
| 7159 ins_pipe(fpu_reg_con); | |
| 7160 %} | |
| 7161 | |
| 7162 // The instruction usage is guarded by predicate in operand immF0(). | |
| 7163 instruct loadConF0(regF dst, immF0 con) %{ | |
| 7164 match(Set dst con); | |
| 0 | 7165 ins_cost(125); |
| 2008 | 7166 format %{ "FLDZ ST\n\t" |
| 0 | 7167 "FSTP $dst" %} |
| 2008 | 7168 ins_encode %{ |
| 7169 __ fldz(); | |
| 7170 __ fstp_d($dst$$reg); | |
| 7171 %} | |
| 7172 ins_pipe(fpu_reg_con); | |
| 7173 %} | |
| 7174 | |
| 7175 // The instruction usage is guarded by predicate in operand immF1(). | |
| 7176 instruct loadConF1(regF dst, immF1 con) %{ | |
| 7177 match(Set dst con); | |
| 7178 ins_cost(125); | |
| 7179 format %{ "FLD1 ST\n\t" | |
| 7180 "FSTP $dst" %} | |
| 7181 ins_encode %{ | |
| 7182 __ fld1(); | |
| 7183 __ fstp_d($dst$$reg); | |
| 7184 %} | |
| 7185 ins_pipe(fpu_reg_con); | |
| 0 | 7186 %} |
| 7187 | |
| 7188 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7189 instruct loadConX(regX dst, immXF con) %{ | |
| 7190 match(Set dst con); | |
| 7191 ins_cost(125); | |
| 2008 | 7192 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 7193 ins_encode %{ | |
| 7194 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 7195 %} | |
| 7196 ins_pipe(pipe_slow); | |
| 0 | 7197 %} |
| 7198 | |
| 7199 // The instruction usage is guarded by predicate in operand immXF0(). | |
| 7200 instruct loadConX0(regX dst, immXF0 src) %{ | |
| 7201 match(Set dst src); | |
| 7202 ins_cost(100); | |
| 7203 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 7204 ins_encode %{ |
| 7205 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 7206 %} | |
| 7207 ins_pipe(pipe_slow); | |
| 0 | 7208 %} |
| 7209 | |
| 7210 // The instruction usage is guarded by predicate in operand immD(). | |
| 2008 | 7211 instruct loadConD(regD dst, immD con) %{ |
| 7212 match(Set dst con); | |
| 7213 ins_cost(125); | |
| 7214 | |
| 7215 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 7216 "FSTP $dst" %} | |
| 7217 ins_encode %{ | |
| 7218 __ fld_d($constantaddress($con)); | |
| 7219 __ fstp_d($dst$$reg); | |
| 7220 %} | |
| 7221 ins_pipe(fpu_reg_con); | |
| 7222 %} | |
| 7223 | |
| 7224 // The instruction usage is guarded by predicate in operand immD0(). | |
| 7225 instruct loadConD0(regD dst, immD0 con) %{ | |
| 7226 match(Set dst con); | |
| 0 | 7227 ins_cost(125); |
| 7228 | |
| 2008 | 7229 format %{ "FLDZ ST\n\t" |
| 0 | 7230 "FSTP $dst" %} |
| 2008 | 7231 ins_encode %{ |
| 7232 __ fldz(); | |
| 7233 __ fstp_d($dst$$reg); | |
| 7234 %} | |
| 7235 ins_pipe(fpu_reg_con); | |
| 7236 %} | |
| 7237 | |
| 7238 // The instruction usage is guarded by predicate in operand immD1(). | |
| 7239 instruct loadConD1(regD dst, immD1 con) %{ | |
| 7240 match(Set dst con); | |
| 7241 ins_cost(125); | |
| 7242 | |
| 7243 format %{ "FLD1 ST\n\t" | |
| 7244 "FSTP $dst" %} | |
| 7245 ins_encode %{ | |
| 7246 __ fld1(); | |
| 7247 __ fstp_d($dst$$reg); | |
| 7248 %} | |
| 7249 ins_pipe(fpu_reg_con); | |
| 0 | 7250 %} |
| 7251 | |
| 7252 // The instruction usage is guarded by predicate in operand immXD(). | |
| 7253 instruct loadConXD(regXD dst, immXD con) %{ | |
| 7254 match(Set dst con); | |
| 7255 ins_cost(125); | |
| 2008 | 7256 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 7257 ins_encode %{ | |
| 7258 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 7259 %} | |
| 7260 ins_pipe(pipe_slow); | |
| 0 | 7261 %} |
| 7262 | |
| 7263 // The instruction usage is guarded by predicate in operand immXD0(). | |
| 7264 instruct loadConXD0(regXD dst, immXD0 src) %{ | |
| 7265 match(Set dst src); | |
| 7266 ins_cost(100); | |
| 7267 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 7268 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 7269 ins_pipe( pipe_slow ); | |
| 7270 %} | |
| 7271 | |
| 7272 // Load Stack Slot | |
| 7273 instruct loadSSI(eRegI dst, stackSlotI src) %{ | |
| 7274 match(Set dst src); | |
| 7275 ins_cost(125); | |
| 7276 | |
| 7277 format %{ "MOV $dst,$src" %} | |
| 7278 opcode(0x8B); | |
| 7279 ins_encode( OpcP, RegMem(dst,src)); | |
| 7280 ins_pipe( ialu_reg_mem ); | |
| 7281 %} | |
| 7282 | |
| 7283 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 7284 match(Set dst src); | |
| 7285 | |
| 7286 ins_cost(200); | |
| 7287 format %{ "MOV $dst,$src.lo\n\t" | |
| 7288 "MOV $dst+4,$src.hi" %} | |
| 7289 opcode(0x8B, 0x8B); | |
| 7290 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 7291 ins_pipe( ialu_mem_long_reg ); | |
| 7292 %} | |
| 7293 | |
| 7294 // Load Stack Slot | |
| 7295 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 7296 match(Set dst src); | |
| 7297 ins_cost(125); | |
| 7298 | |
| 7299 format %{ "MOV $dst,$src" %} | |
| 7300 opcode(0x8B); | |
| 7301 ins_encode( OpcP, RegMem(dst,src)); | |
| 7302 ins_pipe( ialu_reg_mem ); | |
| 7303 %} | |
| 7304 | |
| 7305 // Load Stack Slot | |
| 7306 instruct loadSSF(regF dst, stackSlotF src) %{ | |
| 7307 match(Set dst src); | |
| 7308 ins_cost(125); | |
| 7309 | |
| 7310 format %{ "FLD_S $src\n\t" | |
| 7311 "FSTP $dst" %} | |
| 7312 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 7313 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7314 Pop_Reg_F(dst) ); | |
| 7315 ins_pipe( fpu_reg_mem ); | |
| 7316 %} | |
| 7317 | |
| 7318 // Load Stack Slot | |
| 7319 instruct loadSSD(regD dst, stackSlotD src) %{ | |
| 7320 match(Set dst src); | |
| 7321 ins_cost(125); | |
| 7322 | |
| 7323 format %{ "FLD_D $src\n\t" | |
| 7324 "FSTP $dst" %} | |
| 7325 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 7326 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7327 Pop_Reg_D(dst) ); | |
| 7328 ins_pipe( fpu_reg_mem ); | |
| 7329 %} | |
| 7330 | |
| 7331 // Prefetch instructions. | |
| 7332 // Must be safe to execute with invalid address (cannot fault). | |
| 7333 | |
| 7334 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 7335 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 7336 match(PrefetchRead mem); |
| 7337 ins_cost(0); | |
| 7338 size(0); | |
| 7339 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 7340 ins_encode(); | |
| 7341 ins_pipe(empty); | |
| 7342 %} | |
| 7343 | |
| 7344 instruct prefetchr( memory mem ) %{ | |
| 2479 | 7345 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 7346 match(PrefetchRead mem); |
| 7347 ins_cost(100); | |
| 7348 | |
| 7349 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 7350 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ | |
| 7351 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7352 ins_pipe(ialu_mem); | |
| 7353 %} | |
| 7354 | |
| 7355 instruct prefetchrNTA( memory mem ) %{ | |
| 7356 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 7357 match(PrefetchRead mem); | |
| 7358 ins_cost(100); | |
| 7359 | |
| 7360 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 7361 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7362 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7363 ins_pipe(ialu_mem); | |
| 7364 %} | |
| 7365 | |
| 7366 instruct prefetchrT0( memory mem ) %{ | |
| 7367 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 7368 match(PrefetchRead mem); | |
| 7369 ins_cost(100); | |
| 7370 | |
| 7371 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 7372 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7373 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7374 ins_pipe(ialu_mem); | |
| 7375 %} | |
| 7376 | |
| 7377 instruct prefetchrT2( memory mem ) %{ | |
| 7378 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 7379 match(PrefetchRead mem); | |
| 7380 ins_cost(100); | |
| 7381 | |
| 7382 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 7383 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7384 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7385 ins_pipe(ialu_mem); | |
| 7386 %} | |
| 7387 | |
| 7388 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 7389 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 7390 match(PrefetchWrite mem); |
| 7391 ins_cost(0); | |
| 7392 size(0); | |
| 7393 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 7394 ins_encode(); | |
| 7395 ins_pipe(empty); | |
| 7396 %} | |
| 7397 | |
| 7398 instruct prefetchw( memory mem ) %{ | |
| 2479 | 7399 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || AllocatePrefetchInstr==3); |
| 0 | 7400 match( PrefetchWrite mem ); |
| 7401 ins_cost(100); | |
| 7402 | |
| 7403 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 7404 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 7405 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7406 ins_pipe(ialu_mem); | |
| 7407 %} | |
| 7408 | |
| 7409 instruct prefetchwNTA( memory mem ) %{ | |
| 7410 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 7411 match(PrefetchWrite mem); | |
| 7412 ins_cost(100); | |
| 7413 | |
| 7414 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 7415 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7416 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7417 ins_pipe(ialu_mem); | |
| 7418 %} | |
| 7419 | |
| 7420 instruct prefetchwT0( memory mem ) %{ | |
| 7421 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 7422 match(PrefetchWrite mem); | |
| 7423 ins_cost(100); | |
| 7424 | |
| 7425 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} | |
| 7426 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7427 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7428 ins_pipe(ialu_mem); | |
| 7429 %} | |
| 7430 | |
| 7431 instruct prefetchwT2( memory mem ) %{ | |
| 7432 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 7433 match(PrefetchWrite mem); | |
| 7434 ins_cost(100); | |
| 7435 | |
| 7436 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} | |
| 7437 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7438 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7439 ins_pipe(ialu_mem); | |
| 7440 %} | |
| 7441 | |
| 7442 //----------Store Instructions------------------------------------------------- | |
| 7443 | |
| 7444 // Store Byte | |
| 7445 instruct storeB(memory mem, xRegI src) %{ | |
| 7446 match(Set mem (StoreB mem src)); | |
| 7447 | |
| 7448 ins_cost(125); | |
| 7449 format %{ "MOV8 $mem,$src" %} | |
| 7450 opcode(0x88); | |
| 7451 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7452 ins_pipe( ialu_mem_reg ); | |
| 7453 %} | |
| 7454 | |
| 7455 // Store Char/Short | |
| 7456 instruct storeC(memory mem, eRegI src) %{ | |
| 7457 match(Set mem (StoreC mem src)); | |
| 7458 | |
| 7459 ins_cost(125); | |
| 7460 format %{ "MOV16 $mem,$src" %} | |
| 7461 opcode(0x89, 0x66); | |
| 7462 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 7463 ins_pipe( ialu_mem_reg ); | |
| 7464 %} | |
| 7465 | |
| 7466 // Store Integer | |
| 7467 instruct storeI(memory mem, eRegI src) %{ | |
| 7468 match(Set mem (StoreI mem src)); | |
| 7469 | |
| 7470 ins_cost(125); | |
| 7471 format %{ "MOV $mem,$src" %} | |
| 7472 opcode(0x89); | |
| 7473 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7474 ins_pipe( ialu_mem_reg ); | |
| 7475 %} | |
| 7476 | |
| 7477 // Store Long | |
| 7478 instruct storeL(long_memory mem, eRegL src) %{ | |
| 7479 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 7480 match(Set mem (StoreL mem src)); | |
| 7481 | |
| 7482 ins_cost(200); | |
| 7483 format %{ "MOV $mem,$src.lo\n\t" | |
| 7484 "MOV $mem+4,$src.hi" %} | |
| 7485 opcode(0x89, 0x89); | |
| 7486 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 7487 ins_pipe( ialu_mem_long_reg ); | |
| 7488 %} | |
| 7489 | |
| 824 | 7490 // Store Long to Integer |
| 7491 instruct storeL2I(memory mem, eRegL src) %{ | |
| 7492 match(Set mem (StoreI mem (ConvL2I src))); | |
| 7493 | |
| 7494 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 7495 ins_encode %{ | |
| 7496 __ movl($mem$$Address, $src$$Register); | |
| 7497 %} | |
| 7498 ins_pipe(ialu_mem_reg); | |
| 7499 %} | |
| 7500 | |
| 0 | 7501 // Volatile Store Long. Must be atomic, so move it into |
| 7502 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 7503 // target address before the store (for null-ptr checks) | |
| 7504 // so the memory operand is used twice in the encoding. | |
| 7505 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 7506 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7507 match(Set mem (StoreL mem src)); | |
| 7508 effect( KILL cr ); | |
| 7509 ins_cost(400); | |
| 7510 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7511 "FILD $src\n\t" | |
| 7512 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 7513 opcode(0x3B); | |
| 7514 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 7515 ins_pipe( fpu_reg_mem ); | |
| 7516 %} | |
| 7517 | |
| 7518 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ | |
| 7519 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7520 match(Set mem (StoreL mem src)); | |
| 7521 effect( TEMP tmp, KILL cr ); | |
| 7522 ins_cost(380); | |
| 7523 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7524 "MOVSD $tmp,$src\n\t" | |
| 7525 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7526 opcode(0x3B); | |
| 7527 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); | |
| 7528 ins_pipe( pipe_slow ); | |
| 7529 %} | |
| 7530 | |
| 7531 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ | |
| 7532 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7533 match(Set mem (StoreL mem src)); | |
| 7534 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 7535 ins_cost(360); | |
| 7536 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7537 "MOVD $tmp,$src.lo\n\t" | |
| 7538 "MOVD $tmp2,$src.hi\n\t" | |
| 7539 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 7540 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7541 opcode(0x3B); | |
| 7542 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); | |
| 7543 ins_pipe( pipe_slow ); | |
| 7544 %} | |
| 7545 | |
| 7546 // Store Pointer; for storing unknown oops and raw pointers | |
| 7547 instruct storeP(memory mem, anyRegP src) %{ | |
| 7548 match(Set mem (StoreP mem src)); | |
| 7549 | |
| 7550 ins_cost(125); | |
| 7551 format %{ "MOV $mem,$src" %} | |
| 7552 opcode(0x89); | |
| 7553 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7554 ins_pipe( ialu_mem_reg ); | |
| 7555 %} | |
| 7556 | |
| 7557 // Store Integer Immediate | |
| 7558 instruct storeImmI(memory mem, immI src) %{ | |
| 7559 match(Set mem (StoreI mem src)); | |
| 7560 | |
| 7561 ins_cost(150); | |
| 7562 format %{ "MOV $mem,$src" %} | |
| 7563 opcode(0xC7); /* C7 /0 */ | |
| 7564 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7565 ins_pipe( ialu_mem_imm ); | |
| 7566 %} | |
| 7567 | |
| 7568 // Store Short/Char Immediate | |
| 7569 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 7570 predicate(UseStoreImmI16); | |
| 7571 match(Set mem (StoreC mem src)); | |
| 7572 | |
| 7573 ins_cost(150); | |
| 7574 format %{ "MOV16 $mem,$src" %} | |
| 7575 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7576 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 7577 ins_pipe( ialu_mem_imm ); | |
| 7578 %} | |
| 7579 | |
| 7580 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 7581 // need card-mark barriers. | |
| 7582 instruct storeImmP(memory mem, immP src) %{ | |
| 7583 match(Set mem (StoreP mem src)); | |
| 7584 | |
| 7585 ins_cost(150); | |
| 7586 format %{ "MOV $mem,$src" %} | |
| 7587 opcode(0xC7); /* C7 /0 */ | |
| 7588 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7589 ins_pipe( ialu_mem_imm ); | |
| 7590 %} | |
| 7591 | |
| 7592 // Store Byte Immediate | |
| 7593 instruct storeImmB(memory mem, immI8 src) %{ | |
| 7594 match(Set mem (StoreB mem src)); | |
| 7595 | |
| 7596 ins_cost(150); | |
| 7597 format %{ "MOV8 $mem,$src" %} | |
| 7598 opcode(0xC6); /* C6 /0 */ | |
| 7599 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7600 ins_pipe( ialu_mem_imm ); | |
| 7601 %} | |
| 7602 | |
| 7603 // Store Aligned Packed Byte XMM register to memory | |
| 7604 instruct storeA8B(memory mem, regXD src) %{ | |
| 7605 predicate(UseSSE>=1); | |
| 7606 match(Set mem (Store8B mem src)); | |
| 7607 ins_cost(145); | |
| 7608 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7609 ins_encode( movq_st(mem, src)); | |
| 7610 ins_pipe( pipe_slow ); | |
| 7611 %} | |
| 7612 | |
| 7613 // Store Aligned Packed Char/Short XMM register to memory | |
| 7614 instruct storeA4C(memory mem, regXD src) %{ | |
| 7615 predicate(UseSSE>=1); | |
| 7616 match(Set mem (Store4C mem src)); | |
| 7617 ins_cost(145); | |
| 7618 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7619 ins_encode( movq_st(mem, src)); | |
| 7620 ins_pipe( pipe_slow ); | |
| 7621 %} | |
| 7622 | |
| 7623 // Store Aligned Packed Integer XMM register to memory | |
| 7624 instruct storeA2I(memory mem, regXD src) %{ | |
| 7625 predicate(UseSSE>=1); | |
| 7626 match(Set mem (Store2I mem src)); | |
| 7627 ins_cost(145); | |
| 7628 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7629 ins_encode( movq_st(mem, src)); | |
| 7630 ins_pipe( pipe_slow ); | |
| 7631 %} | |
| 7632 | |
| 7633 // Store CMS card-mark Immediate | |
| 7634 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 7635 match(Set mem (StoreCM mem src)); | |
| 7636 | |
| 7637 ins_cost(150); | |
| 7638 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 7639 opcode(0xC6); /* C6 /0 */ | |
| 7640 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7641 ins_pipe( ialu_mem_imm ); | |
| 7642 %} | |
| 7643 | |
| 7644 // Store Double | |
| 7645 instruct storeD( memory mem, regDPR1 src) %{ | |
| 7646 predicate(UseSSE<=1); | |
| 7647 match(Set mem (StoreD mem src)); | |
| 7648 | |
| 7649 ins_cost(100); | |
| 7650 format %{ "FST_D $mem,$src" %} | |
| 7651 opcode(0xDD); /* DD /2 */ | |
| 7652 ins_encode( enc_FP_store(mem,src) ); | |
| 7653 ins_pipe( fpu_mem_reg ); | |
| 7654 %} | |
| 7655 | |
| 7656 // Store double does rounding on x86 | |
| 7657 instruct storeD_rounded( memory mem, regDPR1 src) %{ | |
| 7658 predicate(UseSSE<=1); | |
| 7659 match(Set mem (StoreD mem (RoundDouble src))); | |
| 7660 | |
| 7661 ins_cost(100); | |
| 7662 format %{ "FST_D $mem,$src\t# round" %} | |
| 7663 opcode(0xDD); /* DD /2 */ | |
| 7664 ins_encode( enc_FP_store(mem,src) ); | |
| 7665 ins_pipe( fpu_mem_reg ); | |
| 7666 %} | |
| 7667 | |
| 7668 // Store XMM register to memory (double-precision floating points) | |
| 7669 // MOVSD instruction | |
| 7670 instruct storeXD(memory mem, regXD src) %{ | |
| 7671 predicate(UseSSE>=2); | |
| 7672 match(Set mem (StoreD mem src)); | |
| 7673 ins_cost(95); | |
| 7674 format %{ "MOVSD $mem,$src" %} | |
| 7675 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7676 ins_pipe( pipe_slow ); | |
| 7677 %} | |
| 7678 | |
| 7679 // Store XMM register to memory (single-precision floating point) | |
| 7680 // MOVSS instruction | |
| 7681 instruct storeX(memory mem, regX src) %{ | |
| 7682 predicate(UseSSE>=1); | |
| 7683 match(Set mem (StoreF mem src)); | |
| 7684 ins_cost(95); | |
| 7685 format %{ "MOVSS $mem,$src" %} | |
| 7686 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7687 ins_pipe( pipe_slow ); | |
| 7688 %} | |
| 7689 | |
| 7690 // Store Aligned Packed Single Float XMM register to memory | |
| 7691 instruct storeA2F(memory mem, regXD src) %{ | |
| 7692 predicate(UseSSE>=1); | |
| 7693 match(Set mem (Store2F mem src)); | |
| 7694 ins_cost(145); | |
| 7695 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7696 ins_encode( movq_st(mem, src)); | |
| 7697 ins_pipe( pipe_slow ); | |
| 7698 %} | |
| 7699 | |
| 7700 // Store Float | |
| 7701 instruct storeF( memory mem, regFPR1 src) %{ | |
| 7702 predicate(UseSSE==0); | |
| 7703 match(Set mem (StoreF mem src)); | |
| 7704 | |
| 7705 ins_cost(100); | |
| 7706 format %{ "FST_S $mem,$src" %} | |
| 7707 opcode(0xD9); /* D9 /2 */ | |
| 7708 ins_encode( enc_FP_store(mem,src) ); | |
| 7709 ins_pipe( fpu_mem_reg ); | |
| 7710 %} | |
| 7711 | |
| 7712 // Store Float does rounding on x86 | |
| 7713 instruct storeF_rounded( memory mem, regFPR1 src) %{ | |
| 7714 predicate(UseSSE==0); | |
| 7715 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7716 | |
| 7717 ins_cost(100); | |
| 7718 format %{ "FST_S $mem,$src\t# round" %} | |
| 7719 opcode(0xD9); /* D9 /2 */ | |
| 7720 ins_encode( enc_FP_store(mem,src) ); | |
| 7721 ins_pipe( fpu_mem_reg ); | |
| 7722 %} | |
| 7723 | |
| 7724 // Store Float does rounding on x86 | |
| 7725 instruct storeF_Drounded( memory mem, regDPR1 src) %{ | |
| 7726 predicate(UseSSE<=1); | |
| 7727 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7728 | |
| 7729 ins_cost(100); | |
| 7730 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7731 opcode(0xD9); /* D9 /2 */ | |
| 7732 ins_encode( enc_FP_store(mem,src) ); | |
| 7733 ins_pipe( fpu_mem_reg ); | |
| 7734 %} | |
| 7735 | |
| 7736 // Store immediate Float value (it is faster than store from FPU register) | |
| 7737 // The instruction usage is guarded by predicate in operand immF(). | |
| 7738 instruct storeF_imm( memory mem, immF src) %{ | |
| 7739 match(Set mem (StoreF mem src)); | |
| 7740 | |
| 7741 ins_cost(50); | |
| 7742 format %{ "MOV $mem,$src\t# store float" %} | |
| 7743 opcode(0xC7); /* C7 /0 */ | |
| 7744 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7745 ins_pipe( ialu_mem_imm ); | |
| 7746 %} | |
| 7747 | |
| 7748 // Store immediate Float value (it is faster than store from XMM register) | |
| 7749 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7750 instruct storeX_imm( memory mem, immXF src) %{ | |
| 7751 match(Set mem (StoreF mem src)); | |
| 7752 | |
| 7753 ins_cost(50); | |
| 7754 format %{ "MOV $mem,$src\t# store float" %} | |
| 7755 opcode(0xC7); /* C7 /0 */ | |
| 7756 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); | |
| 7757 ins_pipe( ialu_mem_imm ); | |
| 7758 %} | |
| 7759 | |
| 7760 // Store Integer to stack slot | |
| 7761 instruct storeSSI(stackSlotI dst, eRegI src) %{ | |
| 7762 match(Set dst src); | |
| 7763 | |
| 7764 ins_cost(100); | |
| 7765 format %{ "MOV $dst,$src" %} | |
| 7766 opcode(0x89); | |
| 7767 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7768 ins_pipe( ialu_mem_reg ); | |
| 7769 %} | |
| 7770 | |
| 7771 // Store Integer to stack slot | |
| 7772 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7773 match(Set dst src); | |
| 7774 | |
| 7775 ins_cost(100); | |
| 7776 format %{ "MOV $dst,$src" %} | |
| 7777 opcode(0x89); | |
| 7778 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7779 ins_pipe( ialu_mem_reg ); | |
| 7780 %} | |
| 7781 | |
| 7782 // Store Long to stack slot | |
| 7783 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7784 match(Set dst src); | |
| 7785 | |
| 7786 ins_cost(200); | |
| 7787 format %{ "MOV $dst,$src.lo\n\t" | |
| 7788 "MOV $dst+4,$src.hi" %} | |
| 7789 opcode(0x89, 0x89); | |
| 7790 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7791 ins_pipe( ialu_mem_long_reg ); | |
| 7792 %} | |
| 7793 | |
| 7794 //----------MemBar Instructions----------------------------------------------- | |
| 7795 // Memory barrier flavors | |
| 7796 | |
| 7797 instruct membar_acquire() %{ | |
| 7798 match(MemBarAcquire); | |
| 7799 ins_cost(400); | |
| 7800 | |
| 7801 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7802 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7803 ins_encode(); |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7804 ins_pipe(empty); |
| 0 | 7805 %} |
| 7806 | |
| 7807 instruct membar_acquire_lock() %{ | |
| 7808 match(MemBarAcquire); | |
| 7809 predicate(Matcher::prior_fast_lock(n)); | |
| 7810 ins_cost(0); | |
| 7811 | |
| 7812 size(0); | |
| 7813 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7814 ins_encode( ); | |
| 7815 ins_pipe(empty); | |
| 7816 %} | |
| 7817 | |
| 7818 instruct membar_release() %{ | |
| 7819 match(MemBarRelease); | |
| 7820 ins_cost(400); | |
| 7821 | |
| 7822 size(0); | |
|
671
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diff
changeset
|
7823 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7824 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
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647
diff
changeset
|
7825 ins_pipe(empty); |
| 0 | 7826 %} |
| 7827 | |
| 7828 instruct membar_release_lock() %{ | |
| 7829 match(MemBarRelease); | |
| 7830 predicate(Matcher::post_fast_unlock(n)); | |
| 7831 ins_cost(0); | |
| 7832 | |
| 7833 size(0); | |
| 7834 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7835 ins_encode( ); | |
| 7836 ins_pipe(empty); | |
| 7837 %} | |
| 7838 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7839 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7840 match(MemBarVolatile); |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7841 effect(KILL cr); |
| 0 | 7842 ins_cost(400); |
| 7843 | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7844 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
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647
diff
changeset
|
7845 $$template |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
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diff
changeset
|
7846 if (os::is_MP()) { |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7847 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7848 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7849 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7850 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7851 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7852 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7853 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7854 %} |
| 0 | 7855 ins_pipe(pipe_slow); |
| 7856 %} | |
| 7857 | |
| 7858 instruct unnecessary_membar_volatile() %{ | |
| 7859 match(MemBarVolatile); | |
| 7860 predicate(Matcher::post_store_load_barrier(n)); | |
| 7861 ins_cost(0); | |
| 7862 | |
| 7863 size(0); | |
| 7864 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7865 ins_encode( ); | |
| 7866 ins_pipe(empty); | |
| 7867 %} | |
| 7868 | |
| 7869 //----------Move Instructions-------------------------------------------------- | |
| 7870 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7871 match(Set dst (CastX2P src)); | |
| 7872 format %{ "# X2P $dst, $src" %} | |
| 7873 ins_encode( /*empty encoding*/ ); | |
| 7874 ins_cost(0); | |
| 7875 ins_pipe(empty); | |
| 7876 %} | |
| 7877 | |
| 7878 instruct castP2X(eRegI dst, eRegP src ) %{ | |
| 7879 match(Set dst (CastP2X src)); | |
| 7880 ins_cost(50); | |
| 7881 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7882 ins_encode( enc_Copy( dst, src) ); | |
| 7883 ins_pipe( ialu_reg_reg ); | |
| 7884 %} | |
| 7885 | |
| 7886 //----------Conditional Move--------------------------------------------------- | |
| 7887 // Conditional move | |
| 7888 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7889 predicate(VM_Version::supports_cmov() ); | |
| 7890 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7891 ins_cost(200); | |
| 7892 format %{ "CMOV$cop $dst,$src" %} | |
| 7893 opcode(0x0F,0x40); | |
| 7894 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7895 ins_pipe( pipe_cmov_reg ); | |
| 7896 %} | |
| 7897 | |
|
415
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diff
changeset
|
7898 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ |
| 0 | 7899 predicate(VM_Version::supports_cmov() ); |
| 7900 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7901 ins_cost(200); | |
| 7902 format %{ "CMOV$cop $dst,$src" %} | |
| 7903 opcode(0x0F,0x40); | |
| 7904 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7905 ins_pipe( pipe_cmov_reg ); | |
| 7906 %} | |
| 7907 | |
|
415
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diff
changeset
|
7908 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ |
|
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diff
changeset
|
7909 predicate(VM_Version::supports_cmov() ); |
|
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diff
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|
7910 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7911 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
7912 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7913 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7914 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7915 %} |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
7916 |
| 0 | 7917 // Conditional move |
| 7918 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ | |
| 7919 predicate(VM_Version::supports_cmov() ); | |
| 7920 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7921 ins_cost(250); | |
| 7922 format %{ "CMOV$cop $dst,$src" %} | |
| 7923 opcode(0x0F,0x40); | |
| 7924 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7925 ins_pipe( pipe_cmov_mem ); | |
| 7926 %} | |
| 7927 | |
| 7928 // Conditional move | |
|
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diff
changeset
|
7929 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ |
| 0 | 7930 predicate(VM_Version::supports_cmov() ); |
| 7931 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7932 ins_cost(250); | |
| 7933 format %{ "CMOV$cop $dst,$src" %} | |
| 7934 opcode(0x0F,0x40); | |
| 7935 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7936 ins_pipe( pipe_cmov_mem ); | |
| 7937 %} | |
| 7938 | |
|
415
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diff
changeset
|
7939 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7940 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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diff
changeset
|
7941 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
7942 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7943 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7944 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7945 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7946 %} |
|
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parents:
403
diff
changeset
|
7947 |
| 0 | 7948 // Conditional move |
| 7949 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7950 predicate(VM_Version::supports_cmov() ); | |
| 7951 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7952 ins_cost(200); | |
| 7953 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7954 opcode(0x0F,0x40); | |
| 7955 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7956 ins_pipe( pipe_cmov_reg ); | |
| 7957 %} | |
| 7958 | |
| 7959 // Conditional move (non-P6 version) | |
| 7960 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7961 // regardless of whether we are on a P6, so we | |
| 7962 // emulate a cmov here | |
| 7963 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7964 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7965 ins_cost(300); | |
| 7966 format %{ "Jn$cop skip\n\t" | |
| 7967 "MOV $dst,$src\t# pointer\n" | |
| 7968 "skip:" %} | |
| 7969 opcode(0x8b); | |
| 7970 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7971 ins_pipe( pipe_cmov_reg ); | |
| 7972 %} | |
| 7973 | |
| 7974 // Conditional move | |
|
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diff
changeset
|
7975 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7976 predicate(VM_Version::supports_cmov() ); |
| 7977 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7978 ins_cost(200); | |
| 7979 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7980 opcode(0x0F,0x40); | |
| 7981 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7982 ins_pipe( pipe_cmov_reg ); | |
| 7983 %} | |
| 7984 | |
|
415
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diff
changeset
|
7985 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
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diff
changeset
|
7986 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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diff
changeset
|
7987 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
7988 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7989 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7990 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7991 %} |
|
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diff
changeset
|
7992 %} |
|
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diff
changeset
|
7993 |
| 0 | 7994 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7995 // correctly meets the two pointer arguments; one is an incoming | |
| 7996 // register but the other is a memory operand. ALSO appears to | |
| 7997 // be buggy with implicit null checks. | |
| 7998 // | |
| 7999 //// Conditional move | |
| 8000 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 8001 // predicate(VM_Version::supports_cmov() ); | |
| 8002 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 8003 // ins_cost(250); | |
| 8004 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 8005 // opcode(0x0F,0x40); | |
| 8006 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 8007 // ins_pipe( pipe_cmov_mem ); | |
| 8008 //%} | |
| 8009 // | |
| 8010 //// Conditional move | |
| 8011 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 8012 // predicate(VM_Version::supports_cmov() ); | |
| 8013 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 8014 // ins_cost(250); | |
| 8015 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 8016 // opcode(0x0F,0x40); | |
| 8017 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 8018 // ins_pipe( pipe_cmov_mem ); | |
| 8019 //%} | |
| 8020 | |
| 8021 // Conditional move | |
| 8022 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ | |
| 8023 predicate(UseSSE<=1); | |
| 8024 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8025 ins_cost(200); | |
| 8026 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 8027 opcode(0xDA); | |
| 8028 ins_encode( enc_cmov_d(cop,src) ); | |
| 8029 ins_pipe( pipe_cmovD_reg ); | |
| 8030 %} | |
| 8031 | |
| 8032 // Conditional move | |
| 8033 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ | |
| 8034 predicate(UseSSE==0); | |
| 8035 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8036 ins_cost(200); | |
| 8037 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 8038 opcode(0xDA); | |
| 8039 ins_encode( enc_cmov_d(cop,src) ); | |
| 8040 ins_pipe( pipe_cmovD_reg ); | |
| 8041 %} | |
| 8042 | |
| 8043 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 8044 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ | |
| 8045 predicate(UseSSE<=1); | |
| 8046 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8047 ins_cost(200); | |
| 8048 format %{ "Jn$cop skip\n\t" | |
| 8049 "MOV $dst,$src\t# double\n" | |
| 8050 "skip:" %} | |
| 8051 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8052 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); | |
| 8053 ins_pipe( pipe_cmovD_reg ); | |
| 8054 %} | |
| 8055 | |
| 8056 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 8057 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ | |
| 8058 predicate(UseSSE==0); | |
| 8059 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8060 ins_cost(200); | |
| 8061 format %{ "Jn$cop skip\n\t" | |
| 8062 "MOV $dst,$src\t# float\n" | |
| 8063 "skip:" %} | |
| 8064 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8065 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); | |
| 8066 ins_pipe( pipe_cmovD_reg ); | |
| 8067 %} | |
| 8068 | |
| 8069 // No CMOVE with SSE/SSE2 | |
| 8070 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ | |
| 8071 predicate (UseSSE>=1); | |
| 8072 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8073 ins_cost(200); | |
| 8074 format %{ "Jn$cop skip\n\t" | |
| 8075 "MOVSS $dst,$src\t# float\n" | |
| 8076 "skip:" %} | |
| 8077 ins_encode %{ | |
| 8078 Label skip; | |
| 8079 // Invert sense of branch from sense of CMOV | |
| 8080 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8081 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8082 __ bind(skip); | |
| 8083 %} | |
| 8084 ins_pipe( pipe_slow ); | |
| 8085 %} | |
| 8086 | |
| 8087 // No CMOVE with SSE/SSE2 | |
| 8088 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ | |
| 8089 predicate (UseSSE>=2); | |
| 8090 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8091 ins_cost(200); | |
| 8092 format %{ "Jn$cop skip\n\t" | |
| 8093 "MOVSD $dst,$src\t# float\n" | |
| 8094 "skip:" %} | |
| 8095 ins_encode %{ | |
| 8096 Label skip; | |
| 8097 // Invert sense of branch from sense of CMOV | |
| 8098 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8099 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8100 __ bind(skip); | |
| 8101 %} | |
| 8102 ins_pipe( pipe_slow ); | |
| 8103 %} | |
| 8104 | |
| 8105 // unsigned version | |
| 8106 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ | |
| 8107 predicate (UseSSE>=1); | |
| 8108 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8109 ins_cost(200); | |
| 8110 format %{ "Jn$cop skip\n\t" | |
| 8111 "MOVSS $dst,$src\t# float\n" | |
| 8112 "skip:" %} | |
| 8113 ins_encode %{ | |
| 8114 Label skip; | |
| 8115 // Invert sense of branch from sense of CMOV | |
| 8116 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8117 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8118 __ bind(skip); | |
| 8119 %} | |
| 8120 ins_pipe( pipe_slow ); | |
| 8121 %} | |
| 8122 | |
|
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8123 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{ |
|
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|
8124 predicate (UseSSE>=1); |
|
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|
8125 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
8126 ins_cost(200); |
|
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|
8127 expand %{ |
|
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|
8128 fcmovX_regU(cop, cr, dst, src); |
|
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|
8129 %} |
|
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|
8130 %} |
|
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|
8131 |
| 0 | 8132 // unsigned version |
| 8133 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ | |
| 8134 predicate (UseSSE>=2); | |
| 8135 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8136 ins_cost(200); | |
| 8137 format %{ "Jn$cop skip\n\t" | |
| 8138 "MOVSD $dst,$src\t# float\n" | |
| 8139 "skip:" %} | |
| 8140 ins_encode %{ | |
| 8141 Label skip; | |
| 8142 // Invert sense of branch from sense of CMOV | |
| 8143 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8144 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8145 __ bind(skip); | |
| 8146 %} | |
| 8147 ins_pipe( pipe_slow ); | |
| 8148 %} | |
| 8149 | |
|
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|
8150 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
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|
8151 predicate (UseSSE>=2); |
|
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|
8152 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
8153 ins_cost(200); |
|
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|
8154 expand %{ |
|
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|
8155 fcmovXD_regU(cop, cr, dst, src); |
|
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|
8156 %} |
|
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|
8157 %} |
|
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|
8158 |
| 0 | 8159 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 8160 predicate(VM_Version::supports_cmov() ); | |
| 8161 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8162 ins_cost(200); | |
| 8163 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8164 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8165 opcode(0x0F,0x40); | |
| 8166 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8167 ins_pipe( pipe_cmov_reg_long ); | |
| 8168 %} | |
| 8169 | |
| 8170 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 8171 predicate(VM_Version::supports_cmov() ); | |
| 8172 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8173 ins_cost(200); | |
| 8174 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8175 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8176 opcode(0x0F,0x40); | |
| 8177 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8178 ins_pipe( pipe_cmov_reg_long ); | |
| 8179 %} | |
| 8180 | |
|
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8181 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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|
8182 predicate(VM_Version::supports_cmov() ); |
|
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8183 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
8184 ins_cost(200); |
|
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|
8185 expand %{ |
|
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|
8186 cmovL_regU(cop, cr, dst, src); |
|
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|
8187 %} |
|
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|
8188 %} |
|
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|
8189 |
| 0 | 8190 //----------Arithmetic Instructions-------------------------------------------- |
| 8191 //----------Addition Instructions---------------------------------------------- | |
| 8192 // Integer Addition Instructions | |
| 8193 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8194 match(Set dst (AddI dst src)); | |
| 8195 effect(KILL cr); | |
| 8196 | |
| 8197 size(2); | |
| 8198 format %{ "ADD $dst,$src" %} | |
| 8199 opcode(0x03); | |
| 8200 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8201 ins_pipe( ialu_reg_reg ); | |
| 8202 %} | |
| 8203 | |
| 8204 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8205 match(Set dst (AddI dst src)); | |
| 8206 effect(KILL cr); | |
| 8207 | |
| 8208 format %{ "ADD $dst,$src" %} | |
| 8209 opcode(0x81, 0x00); /* /0 id */ | |
| 8210 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8211 ins_pipe( ialu_reg ); | |
| 8212 %} | |
| 8213 | |
| 8214 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 8215 predicate(UseIncDec); | |
| 8216 match(Set dst (AddI dst src)); | |
| 8217 effect(KILL cr); | |
| 8218 | |
| 8219 size(1); | |
| 8220 format %{ "INC $dst" %} | |
| 8221 opcode(0x40); /* */ | |
| 8222 ins_encode( Opc_plus( primary, dst ) ); | |
| 8223 ins_pipe( ialu_reg ); | |
| 8224 %} | |
| 8225 | |
| 8226 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ | |
| 8227 match(Set dst (AddI src0 src1)); | |
| 8228 ins_cost(110); | |
| 8229 | |
| 8230 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 8231 opcode(0x8D); /* 0x8D /r */ | |
| 8232 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8233 ins_pipe( ialu_reg_reg ); | |
| 8234 %} | |
| 8235 | |
| 8236 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 8237 match(Set dst (AddP src0 src1)); | |
| 8238 ins_cost(110); | |
| 8239 | |
| 8240 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 8241 opcode(0x8D); /* 0x8D /r */ | |
| 8242 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8243 ins_pipe( ialu_reg_reg ); | |
| 8244 %} | |
| 8245 | |
| 8246 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8247 predicate(UseIncDec); | |
| 8248 match(Set dst (AddI dst src)); | |
| 8249 effect(KILL cr); | |
| 8250 | |
| 8251 size(1); | |
| 8252 format %{ "DEC $dst" %} | |
| 8253 opcode(0x48); /* */ | |
| 8254 ins_encode( Opc_plus( primary, dst ) ); | |
| 8255 ins_pipe( ialu_reg ); | |
| 8256 %} | |
| 8257 | |
| 8258 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ | |
| 8259 match(Set dst (AddP dst src)); | |
| 8260 effect(KILL cr); | |
| 8261 | |
| 8262 size(2); | |
| 8263 format %{ "ADD $dst,$src" %} | |
| 8264 opcode(0x03); | |
| 8265 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8266 ins_pipe( ialu_reg_reg ); | |
| 8267 %} | |
| 8268 | |
| 8269 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 8270 match(Set dst (AddP dst src)); | |
| 8271 effect(KILL cr); | |
| 8272 | |
| 8273 format %{ "ADD $dst,$src" %} | |
| 8274 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 8275 // ins_encode( RegImm( dst, src) ); | |
| 8276 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8277 ins_pipe( ialu_reg ); | |
| 8278 %} | |
| 8279 | |
| 8280 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8281 match(Set dst (AddI dst (LoadI src))); | |
| 8282 effect(KILL cr); | |
| 8283 | |
| 8284 ins_cost(125); | |
| 8285 format %{ "ADD $dst,$src" %} | |
| 8286 opcode(0x03); | |
| 8287 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8288 ins_pipe( ialu_reg_mem ); | |
| 8289 %} | |
| 8290 | |
| 8291 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8292 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8293 effect(KILL cr); | |
| 8294 | |
| 8295 ins_cost(150); | |
| 8296 format %{ "ADD $dst,$src" %} | |
| 8297 opcode(0x01); /* Opcode 01 /r */ | |
| 8298 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8299 ins_pipe( ialu_mem_reg ); | |
| 8300 %} | |
| 8301 | |
| 8302 // Add Memory with Immediate | |
| 8303 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8304 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8305 effect(KILL cr); | |
| 8306 | |
| 8307 ins_cost(125); | |
| 8308 format %{ "ADD $dst,$src" %} | |
| 8309 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8310 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 8311 ins_pipe( ialu_mem_imm ); | |
| 8312 %} | |
| 8313 | |
| 8314 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 8315 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8316 effect(KILL cr); | |
| 8317 | |
| 8318 ins_cost(125); | |
| 8319 format %{ "INC $dst" %} | |
| 8320 opcode(0xFF); /* Opcode FF /0 */ | |
| 8321 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 8322 ins_pipe( ialu_mem_imm ); | |
| 8323 %} | |
| 8324 | |
| 8325 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8326 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8327 effect(KILL cr); | |
| 8328 | |
| 8329 ins_cost(125); | |
| 8330 format %{ "DEC $dst" %} | |
| 8331 opcode(0xFF); /* Opcode FF /1 */ | |
| 8332 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 8333 ins_pipe( ialu_mem_imm ); | |
| 8334 %} | |
| 8335 | |
| 8336 | |
| 8337 instruct checkCastPP( eRegP dst ) %{ | |
| 8338 match(Set dst (CheckCastPP dst)); | |
| 8339 | |
| 8340 size(0); | |
| 8341 format %{ "#checkcastPP of $dst" %} | |
| 8342 ins_encode( /*empty encoding*/ ); | |
| 8343 ins_pipe( empty ); | |
| 8344 %} | |
| 8345 | |
| 8346 instruct castPP( eRegP dst ) %{ | |
| 8347 match(Set dst (CastPP dst)); | |
| 8348 format %{ "#castPP of $dst" %} | |
| 8349 ins_encode( /*empty encoding*/ ); | |
| 8350 ins_pipe( empty ); | |
| 8351 %} | |
| 8352 | |
| 8353 instruct castII( eRegI dst ) %{ | |
| 8354 match(Set dst (CastII dst)); | |
| 8355 format %{ "#castII of $dst" %} | |
| 8356 ins_encode( /*empty encoding*/ ); | |
| 8357 ins_cost(0); | |
| 8358 ins_pipe( empty ); | |
| 8359 %} | |
| 8360 | |
| 8361 | |
| 8362 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 8363 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 8364 match(Set dst (LoadPLocked mem)); | |
| 8365 | |
| 8366 ins_cost(125); | |
| 8367 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 8368 opcode(0x8B); | |
| 8369 ins_encode( OpcP, RegMem(dst,mem)); | |
| 8370 ins_pipe( ialu_reg_mem ); | |
| 8371 %} | |
| 8372 | |
| 8373 // LoadLong-locked - same as a volatile long load when used with compare-swap | |
| 8374 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ | |
| 8375 predicate(UseSSE<=1); | |
| 8376 match(Set dst (LoadLLocked mem)); | |
| 8377 | |
| 8378 ins_cost(200); | |
| 8379 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 8380 "FISTp $dst" %} | |
| 8381 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 8382 ins_pipe( fpu_reg_mem ); | |
| 8383 %} | |
| 8384 | |
| 8385 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ | |
| 8386 predicate(UseSSE>=2); | |
| 8387 match(Set dst (LoadLLocked mem)); | |
| 8388 effect(TEMP tmp); | |
| 8389 ins_cost(180); | |
| 8390 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8391 "MOVSD $dst,$tmp" %} | |
| 8392 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 8393 ins_pipe( pipe_slow ); | |
| 8394 %} | |
| 8395 | |
| 8396 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ | |
| 8397 predicate(UseSSE>=2); | |
| 8398 match(Set dst (LoadLLocked mem)); | |
| 8399 effect(TEMP tmp); | |
| 8400 ins_cost(160); | |
| 8401 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8402 "MOVD $dst.lo,$tmp\n\t" | |
| 8403 "PSRLQ $tmp,32\n\t" | |
| 8404 "MOVD $dst.hi,$tmp" %} | |
| 8405 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 8406 ins_pipe( pipe_slow ); | |
| 8407 %} | |
| 8408 | |
| 8409 // Conditional-store of the updated heap-top. | |
| 8410 // Used during allocation of the shared heap. | |
| 8411 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8412 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 8413 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 8414 // EAX is killed if there is contention, but then it's also unused. | |
| 8415 // In the common case of no contention, EAX holds the new oop address. | |
| 8416 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 8417 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 8418 ins_pipe( pipe_cmpxchg ); | |
| 8419 %} | |
| 8420 | |
|
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8421 // Conditional-store of an int value. |
|
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|
8422 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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8423 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ |
|
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|
8424 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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|
8425 effect(KILL oldval); |
|
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|
8426 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
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|
8427 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 8428 ins_pipe( pipe_cmpxchg ); |
| 8429 %} | |
| 8430 | |
|
420
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|
8431 // Conditional-store of a long value. |
|
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|
8432 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
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|
8433 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
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|
8434 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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|
8435 effect(KILL oldval); |
|
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|
8436 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
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|
8437 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
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|
8438 "XCHG EBX,ECX" |
|
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|
8439 %} |
|
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|
8440 ins_encode %{ |
|
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|
8441 // Note: we need to swap rbx, and rcx before and after the |
|
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|
8442 // cmpxchg8 instruction because the instruction uses |
|
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|
8443 // rcx as the high order word of the new value to store but |
|
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|
8444 // our register encoding uses rbx. |
|
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|
8445 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
8446 if( os::is_MP() ) |
|
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|
8447 __ lock(); |
| 624 | 8448 __ cmpxchg8($mem$$Address); |
|
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|
8449 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
8450 %} |
| 0 | 8451 ins_pipe( pipe_cmpxchg ); |
| 8452 %} | |
| 8453 | |
| 8454 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 8455 | |
| 8456 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ | |
| 8457 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8458 effect(KILL cr, KILL oldval); | |
| 8459 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8460 "MOV $res,0\n\t" | |
| 8461 "JNE,s fail\n\t" | |
| 8462 "MOV $res,1\n" | |
| 8463 "fail:" %} | |
| 8464 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 8465 enc_flags_ne_to_boolean(res) ); | |
| 8466 ins_pipe( pipe_cmpxchg ); | |
| 8467 %} | |
| 8468 | |
| 8469 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ | |
| 8470 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8471 effect(KILL cr, KILL oldval); | |
| 8472 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8473 "MOV $res,0\n\t" | |
| 8474 "JNE,s fail\n\t" | |
| 8475 "MOV $res,1\n" | |
| 8476 "fail:" %} | |
| 8477 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8478 ins_pipe( pipe_cmpxchg ); | |
| 8479 %} | |
| 8480 | |
| 8481 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ | |
| 8482 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8483 effect(KILL cr, KILL oldval); | |
| 8484 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8485 "MOV $res,0\n\t" | |
| 8486 "JNE,s fail\n\t" | |
| 8487 "MOV $res,1\n" | |
| 8488 "fail:" %} | |
| 8489 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8490 ins_pipe( pipe_cmpxchg ); | |
| 8491 %} | |
| 8492 | |
| 8493 //----------Subtraction Instructions------------------------------------------- | |
| 8494 // Integer Subtraction Instructions | |
| 8495 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8496 match(Set dst (SubI dst src)); | |
| 8497 effect(KILL cr); | |
| 8498 | |
| 8499 size(2); | |
| 8500 format %{ "SUB $dst,$src" %} | |
| 8501 opcode(0x2B); | |
| 8502 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8503 ins_pipe( ialu_reg_reg ); | |
| 8504 %} | |
| 8505 | |
| 8506 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8507 match(Set dst (SubI dst src)); | |
| 8508 effect(KILL cr); | |
| 8509 | |
| 8510 format %{ "SUB $dst,$src" %} | |
| 8511 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 8512 // ins_encode( RegImm( dst, src) ); | |
| 8513 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8514 ins_pipe( ialu_reg ); | |
| 8515 %} | |
| 8516 | |
| 8517 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8518 match(Set dst (SubI dst (LoadI src))); | |
| 8519 effect(KILL cr); | |
| 8520 | |
| 8521 ins_cost(125); | |
| 8522 format %{ "SUB $dst,$src" %} | |
| 8523 opcode(0x2B); | |
| 8524 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8525 ins_pipe( ialu_reg_mem ); | |
| 8526 %} | |
| 8527 | |
| 8528 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8529 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8530 effect(KILL cr); | |
| 8531 | |
| 8532 ins_cost(150); | |
| 8533 format %{ "SUB $dst,$src" %} | |
| 8534 opcode(0x29); /* Opcode 29 /r */ | |
| 8535 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8536 ins_pipe( ialu_mem_reg ); | |
| 8537 %} | |
| 8538 | |
| 8539 // Subtract from a pointer | |
| 8540 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ | |
| 8541 match(Set dst (AddP dst (SubI zero src))); | |
| 8542 effect(KILL cr); | |
| 8543 | |
| 8544 size(2); | |
| 8545 format %{ "SUB $dst,$src" %} | |
| 8546 opcode(0x2B); | |
| 8547 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8548 ins_pipe( ialu_reg_reg ); | |
| 8549 %} | |
| 8550 | |
| 8551 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 8552 match(Set dst (SubI zero dst)); | |
| 8553 effect(KILL cr); | |
| 8554 | |
| 8555 size(2); | |
| 8556 format %{ "NEG $dst" %} | |
| 8557 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 8558 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8559 ins_pipe( ialu_reg ); | |
| 8560 %} | |
| 8561 | |
| 8562 | |
| 8563 //----------Multiplication/Division Instructions------------------------------- | |
| 8564 // Integer Multiplication Instructions | |
| 8565 // Multiply Register | |
| 8566 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8567 match(Set dst (MulI dst src)); | |
| 8568 effect(KILL cr); | |
| 8569 | |
| 8570 size(3); | |
| 8571 ins_cost(300); | |
| 8572 format %{ "IMUL $dst,$src" %} | |
| 8573 opcode(0xAF, 0x0F); | |
| 8574 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 8575 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8576 %} | |
| 8577 | |
| 8578 // Multiply 32-bit Immediate | |
| 8579 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ | |
| 8580 match(Set dst (MulI src imm)); | |
| 8581 effect(KILL cr); | |
| 8582 | |
| 8583 ins_cost(300); | |
| 8584 format %{ "IMUL $dst,$src,$imm" %} | |
| 8585 opcode(0x69); /* 69 /r id */ | |
| 8586 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 8587 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8588 %} | |
| 8589 | |
| 8590 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 8591 match(Set dst src); | |
| 8592 effect(KILL cr); | |
| 8593 | |
| 8594 // Note that this is artificially increased to make it more expensive than loadConL | |
| 8595 ins_cost(250); | |
| 8596 format %{ "MOV EAX,$src\t// low word only" %} | |
| 8597 opcode(0xB8); | |
| 8598 ins_encode( LdImmL_Lo(dst, src) ); | |
| 8599 ins_pipe( ialu_reg_fat ); | |
| 8600 %} | |
| 8601 | |
| 8602 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8603 // (special case for shift by 32) | |
| 8604 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8605 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8606 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8607 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8608 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8609 effect(USE src1, KILL cr); | |
| 8610 | |
| 8611 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8612 ins_cost(0*100 + 1*400 - 150); | |
| 8613 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8614 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8615 ins_pipe( pipe_slow ); | |
| 8616 %} | |
| 8617 | |
| 8618 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8619 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8620 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8621 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8622 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8623 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8624 effect(USE src1, KILL cr); | |
| 8625 | |
| 8626 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8627 ins_cost(1*100 + 1*400 - 150); | |
| 8628 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8629 "SAR EDX,$cnt-32" %} | |
| 8630 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8631 ins_pipe( pipe_slow ); | |
| 8632 %} | |
| 8633 | |
| 8634 // Multiply Memory 32-bit Immediate | |
| 8635 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ | |
| 8636 match(Set dst (MulI (LoadI src) imm)); | |
| 8637 effect(KILL cr); | |
| 8638 | |
| 8639 ins_cost(300); | |
| 8640 format %{ "IMUL $dst,$src,$imm" %} | |
| 8641 opcode(0x69); /* 69 /r id */ | |
| 8642 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8643 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8644 %} | |
| 8645 | |
| 8646 // Multiply Memory | |
| 8647 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8648 match(Set dst (MulI dst (LoadI src))); | |
| 8649 effect(KILL cr); | |
| 8650 | |
| 8651 ins_cost(350); | |
| 8652 format %{ "IMUL $dst,$src" %} | |
| 8653 opcode(0xAF, 0x0F); | |
| 8654 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8655 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8656 %} | |
| 8657 | |
| 8658 // Multiply Register Int to Long | |
| 8659 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8660 // Basic Idea: long = (long)int * (long)int | |
| 8661 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8662 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8663 | |
| 8664 ins_cost(300); | |
| 8665 format %{ "IMUL $dst,$src1" %} | |
| 8666 | |
| 8667 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8668 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8669 %} | |
| 8670 | |
| 8671 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8672 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8673 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8674 effect(KILL flags); | |
| 8675 | |
| 8676 ins_cost(300); | |
| 8677 format %{ "MUL $dst,$src1" %} | |
| 8678 | |
| 8679 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8680 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8681 %} | |
| 8682 | |
| 8683 // Multiply Register Long | |
| 8684 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ | |
| 8685 match(Set dst (MulL dst src)); | |
| 8686 effect(KILL cr, TEMP tmp); | |
| 8687 ins_cost(4*100+3*400); | |
| 8688 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8689 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8690 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8691 "IMUL $tmp,EDX\n\t" | |
| 8692 "MOV EDX,$src.hi\n\t" | |
| 8693 "IMUL EDX,EAX\n\t" | |
| 8694 "ADD $tmp,EDX\n\t" | |
| 8695 "MUL EDX:EAX,$src.lo\n\t" | |
| 8696 "ADD EDX,$tmp" %} | |
| 8697 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8698 ins_pipe( pipe_slow ); | |
| 8699 %} | |
| 8700 | |
|
1209
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|
8701 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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|
8702 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8703 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
8704 match(Set dst (MulL dst src)); |
|
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|
8705 effect(KILL cr, TEMP tmp); |
|
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|
8706 ins_cost(2*100+2*400); |
|
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|
8707 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8708 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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|
8709 format %{ "MOV $tmp,$src.hi\n\t" |
|
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|
8710 "IMUL $tmp,EAX\n\t" |
|
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|
8711 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
8712 "ADD EDX,$tmp" %} |
|
e8443c7be117
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|
8713 ins_encode %{ |
|
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|
8714 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
8715 __ imull($tmp$$Register, rax); |
|
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|
8716 __ mull($src$$Register); |
|
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|
8717 __ addl(rdx, $tmp$$Register); |
|
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|
8718 %} |
|
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changeset
|
8719 ins_pipe( pipe_slow ); |
|
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|
8720 %} |
|
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|
8721 |
|
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|
8722 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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|
8723 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8724 predicate(is_operand_hi32_zero(n->in(2))); |
|
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|
8725 match(Set dst (MulL dst src)); |
|
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|
8726 effect(KILL cr, TEMP tmp); |
|
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|
8727 ins_cost(2*100+2*400); |
|
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|
8728 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8729 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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changeset
|
8730 format %{ "MOV $tmp,$src.lo\n\t" |
|
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6921969: optimize 64 long multiply for case with high bits zero
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diff
changeset
|
8731 "IMUL $tmp,EDX\n\t" |
|
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6921969: optimize 64 long multiply for case with high bits zero
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changeset
|
8732 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8733 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8734 ins_encode %{ |
|
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6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8735 __ movl($tmp$$Register, $src$$Register); |
|
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6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8736 __ imull($tmp$$Register, rdx); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8737 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8738 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8739 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8740 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8741 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8742 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8743 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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6921969: optimize 64 long multiply for case with high bits zero
never
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changeset
|
8744 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
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diff
changeset
|
8745 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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diff
changeset
|
8746 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8747 effect(KILL cr); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8748 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8749 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8750 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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6921969: optimize 64 long multiply for case with high bits zero
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1137
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|
8751 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8752 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8753 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8754 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8755 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8756 %} |
|
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6921969: optimize 64 long multiply for case with high bits zero
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1137
diff
changeset
|
8757 |
| 0 | 8758 // Multiply Register Long by small constant |
| 8759 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ | |
| 8760 match(Set dst (MulL dst src)); | |
| 8761 effect(KILL cr, TEMP tmp); | |
| 8762 ins_cost(2*100+2*400); | |
| 8763 size(12); | |
| 8764 // Basic idea: lo(result) = lo(src * EAX) | |
| 8765 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8766 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8767 "MOV EDX,$src\n\t" | |
| 8768 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8769 "ADD EDX,$tmp" %} | |
| 8770 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8771 ins_pipe( pipe_slow ); | |
| 8772 %} | |
| 8773 | |
| 8774 // Integer DIV with Register | |
| 8775 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8776 match(Set rax (DivI rax div)); | |
| 8777 effect(KILL rdx, KILL cr); | |
| 8778 size(26); | |
| 8779 ins_cost(30*100+10*100); | |
| 8780 format %{ "CMP EAX,0x80000000\n\t" | |
| 8781 "JNE,s normal\n\t" | |
| 8782 "XOR EDX,EDX\n\t" | |
| 8783 "CMP ECX,-1\n\t" | |
| 8784 "JE,s done\n" | |
| 8785 "normal: CDQ\n\t" | |
| 8786 "IDIV $div\n\t" | |
| 8787 "done:" %} | |
| 8788 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8789 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8790 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8791 %} | |
| 8792 | |
| 8793 // Divide Register Long | |
| 8794 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8795 match(Set dst (DivL src1 src2)); | |
| 8796 effect( KILL cr, KILL cx, KILL bx ); | |
| 8797 ins_cost(10000); | |
| 8798 format %{ "PUSH $src1.hi\n\t" | |
| 8799 "PUSH $src1.lo\n\t" | |
| 8800 "PUSH $src2.hi\n\t" | |
| 8801 "PUSH $src2.lo\n\t" | |
| 8802 "CALL SharedRuntime::ldiv\n\t" | |
| 8803 "ADD ESP,16" %} | |
| 8804 ins_encode( long_div(src1,src2) ); | |
| 8805 ins_pipe( pipe_slow ); | |
| 8806 %} | |
| 8807 | |
| 8808 // Integer DIVMOD with Register, both quotient and mod results | |
| 8809 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8810 match(DivModI rax div); | |
| 8811 effect(KILL cr); | |
| 8812 size(26); | |
| 8813 ins_cost(30*100+10*100); | |
| 8814 format %{ "CMP EAX,0x80000000\n\t" | |
| 8815 "JNE,s normal\n\t" | |
| 8816 "XOR EDX,EDX\n\t" | |
| 8817 "CMP ECX,-1\n\t" | |
| 8818 "JE,s done\n" | |
| 8819 "normal: CDQ\n\t" | |
| 8820 "IDIV $div\n\t" | |
| 8821 "done:" %} | |
| 8822 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8823 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8824 ins_pipe( pipe_slow ); | |
| 8825 %} | |
| 8826 | |
| 8827 // Integer MOD with Register | |
| 8828 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8829 match(Set rdx (ModI rax div)); | |
| 8830 effect(KILL rax, KILL cr); | |
| 8831 | |
| 8832 size(26); | |
| 8833 ins_cost(300); | |
| 8834 format %{ "CDQ\n\t" | |
| 8835 "IDIV $div" %} | |
| 8836 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8837 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8838 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8839 %} | |
| 8840 | |
| 8841 // Remainder Register Long | |
| 8842 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8843 match(Set dst (ModL src1 src2)); | |
| 8844 effect( KILL cr, KILL cx, KILL bx ); | |
| 8845 ins_cost(10000); | |
| 8846 format %{ "PUSH $src1.hi\n\t" | |
| 8847 "PUSH $src1.lo\n\t" | |
| 8848 "PUSH $src2.hi\n\t" | |
| 8849 "PUSH $src2.lo\n\t" | |
| 8850 "CALL SharedRuntime::lrem\n\t" | |
| 8851 "ADD ESP,16" %} | |
| 8852 ins_encode( long_mod(src1,src2) ); | |
| 8853 ins_pipe( pipe_slow ); | |
| 8854 %} | |
| 8855 | |
|
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kvn
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1748
diff
changeset
|
8856 // Divide Register Long (no special case since divisor != -1) |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
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|
8857 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8858 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8859 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8860 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8861 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8862 "XOR $tmp2,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8863 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8864 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8865 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8866 "MOV EAX,EDX\n\t" |
| 1920 | 8867 "MOV EDX,0\n\t" |
| 8868 "JLE,s pos\n\t" | |
| 8869 "LNEG EAX : $tmp2\n\t" | |
| 8870 "DIV $tmp # unsigned division\n\t" | |
| 8871 "XCHG EAX,$tmp2\n\t" | |
| 8872 "DIV $tmp\n\t" | |
| 8873 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8874 "JMP,s done\n" |
| 1920 | 8875 "pos:\n\t" |
| 8876 "DIV $tmp\n\t" | |
| 8877 "XCHG EAX,$tmp2\n" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8878 "fast:\n\t" |
| 1920 | 8879 "DIV $tmp\n" |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8880 "done:\n\t" |
| 1920 | 8881 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8882 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8883 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8884 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8885 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8886 int pcon = (con > 0) ? con : -con; |
| 1920 | 8887 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8888 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8889 __ movl($tmp$$Register, pcon); |
| 1920 | 8890 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8891 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8892 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8893 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8894 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8895 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8896 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8897 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8898 | |
| 8899 // Negative dividend. | |
| 8900 // convert value to positive to use unsigned division | |
| 8901 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8902 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8903 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8904 __ divl($tmp$$Register); |
| 8905 // revert result back to negative | |
| 8906 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8907 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8908 |
| 1920 | 8909 __ bind(Lpos); |
| 8910 __ divl($tmp$$Register); // Use unsigned division | |
| 8911 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8912 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8913 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8914 __ bind(Lfast); |
| 1920 | 8915 // fast path: src is positive |
| 8916 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8917 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8918 __ bind(Ldone); |
| 1920 | 8919 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8920 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8921 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8922 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8923 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8924 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8925 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8926 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8927 // Remainder Register Long (remainder fit into 32 bits) |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8928 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8929 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8930 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8931 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8932 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8933 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8934 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8935 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8936 "MOV EAX,EDX\n\t" |
| 1920 | 8937 "MOV EDX,0\n\t" |
| 8938 "JLE,s pos\n\t" | |
| 8939 "LNEG EAX : $tmp2\n\t" | |
| 8940 "DIV $tmp # unsigned division\n\t" | |
| 8941 "MOV EAX,$tmp2\n\t" | |
| 8942 "DIV $tmp\n\t" | |
| 8943 "NEG EDX\n\t" | |
| 8944 "JMP,s done\n" | |
| 8945 "pos:\n\t" | |
| 8946 "DIV $tmp\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8947 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8948 "fast:\n\t" |
| 1920 | 8949 "DIV $tmp\n" |
| 8950 "done:\n\t" | |
|
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8951 "MOV EAX,EDX\n\t" |
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8952 "SAR EDX,31\n\t" %} |
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|
8953 ins_encode %{ |
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|
8954 int con = (int)$imm$$constant; |
|
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8955 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
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8956 int pcon = (con > 0) ? con : -con; |
| 1920 | 8957 Label Lfast, Lpos, Ldone; |
|
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8958 |
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8959 __ movl($tmp$$Register, pcon); |
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8960 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
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8961 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
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8962 |
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|
8963 __ movl($tmp2$$Register, $dst$$Register); // save |
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|
8964 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8965 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8966 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8967 | |
| 8968 // Negative dividend. | |
| 8969 // convert value to positive to use unsigned division | |
| 8970 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8971 __ divl($tmp$$Register); | |
| 8972 __ movl($dst$$Register, $tmp2$$Register); | |
| 8973 __ divl($tmp$$Register); | |
| 8974 // revert remainder back to negative | |
| 8975 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8976 __ jmpb(Ldone); | |
| 8977 | |
| 8978 __ bind(Lpos); | |
| 8979 __ divl($tmp$$Register); | |
|
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|
8980 __ movl($dst$$Register, $tmp2$$Register); |
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8981 |
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|
8982 __ bind(Lfast); |
| 1920 | 8983 // fast path: src is positive |
| 8984 __ divl($tmp$$Register); | |
| 8985 | |
| 8986 __ bind(Ldone); | |
|
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|
8987 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
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8988 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
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|
8989 |
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|
8990 %} |
|
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|
8991 ins_pipe( pipe_slow ); |
|
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|
8992 %} |
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|
8993 |
| 0 | 8994 // Integer Shift Instructions |
| 8995 // Shift Left by one | |
| 8996 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8997 match(Set dst (LShiftI dst shift)); | |
| 8998 effect(KILL cr); | |
| 8999 | |
| 9000 size(2); | |
| 9001 format %{ "SHL $dst,$shift" %} | |
| 9002 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9003 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9004 ins_pipe( ialu_reg ); | |
| 9005 %} | |
| 9006 | |
| 9007 // Shift Left by 8-bit immediate | |
| 9008 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9009 match(Set dst (LShiftI dst shift)); | |
| 9010 effect(KILL cr); | |
| 9011 | |
| 9012 size(3); | |
| 9013 format %{ "SHL $dst,$shift" %} | |
| 9014 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9015 ins_encode( RegOpcImm( dst, shift) ); | |
| 9016 ins_pipe( ialu_reg ); | |
| 9017 %} | |
| 9018 | |
| 9019 // Shift Left by variable | |
| 9020 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9021 match(Set dst (LShiftI dst shift)); | |
| 9022 effect(KILL cr); | |
| 9023 | |
| 9024 size(2); | |
| 9025 format %{ "SHL $dst,$shift" %} | |
| 9026 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9027 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9028 ins_pipe( ialu_reg_reg ); | |
| 9029 %} | |
| 9030 | |
| 9031 // Arithmetic shift right by one | |
| 9032 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9033 match(Set dst (RShiftI dst shift)); | |
| 9034 effect(KILL cr); | |
| 9035 | |
| 9036 size(2); | |
| 9037 format %{ "SAR $dst,$shift" %} | |
| 9038 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9039 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9040 ins_pipe( ialu_reg ); | |
| 9041 %} | |
| 9042 | |
| 9043 // Arithmetic shift right by one | |
| 9044 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 9045 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9046 effect(KILL cr); | |
| 9047 format %{ "SAR $dst,$shift" %} | |
| 9048 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9049 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 9050 ins_pipe( ialu_mem_imm ); | |
| 9051 %} | |
| 9052 | |
| 9053 // Arithmetic Shift Right by 8-bit immediate | |
| 9054 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9055 match(Set dst (RShiftI dst shift)); | |
| 9056 effect(KILL cr); | |
| 9057 | |
| 9058 size(3); | |
| 9059 format %{ "SAR $dst,$shift" %} | |
| 9060 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9061 ins_encode( RegOpcImm( dst, shift ) ); | |
| 9062 ins_pipe( ialu_mem_imm ); | |
| 9063 %} | |
| 9064 | |
| 9065 // Arithmetic Shift Right by 8-bit immediate | |
| 9066 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 9067 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9068 effect(KILL cr); | |
| 9069 | |
| 9070 format %{ "SAR $dst,$shift" %} | |
| 9071 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9072 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 9073 ins_pipe( ialu_mem_imm ); | |
| 9074 %} | |
| 9075 | |
| 9076 // Arithmetic Shift Right by variable | |
| 9077 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9078 match(Set dst (RShiftI dst shift)); | |
| 9079 effect(KILL cr); | |
| 9080 | |
| 9081 size(2); | |
| 9082 format %{ "SAR $dst,$shift" %} | |
| 9083 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9084 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9085 ins_pipe( ialu_reg_reg ); | |
| 9086 %} | |
| 9087 | |
| 9088 // Logical shift right by one | |
| 9089 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9090 match(Set dst (URShiftI dst shift)); | |
| 9091 effect(KILL cr); | |
| 9092 | |
| 9093 size(2); | |
| 9094 format %{ "SHR $dst,$shift" %} | |
| 9095 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9096 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9097 ins_pipe( ialu_reg ); | |
| 9098 %} | |
| 9099 | |
| 9100 // Logical Shift Right by 8-bit immediate | |
| 9101 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9102 match(Set dst (URShiftI dst shift)); | |
| 9103 effect(KILL cr); | |
| 9104 | |
| 9105 size(3); | |
| 9106 format %{ "SHR $dst,$shift" %} | |
| 9107 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9108 ins_encode( RegOpcImm( dst, shift) ); | |
| 9109 ins_pipe( ialu_reg ); | |
| 9110 %} | |
| 9111 | |
|
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9112 |
| 0 | 9113 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 9114 // This idiom is used by the compiler for the i2b bytecode. | |
| 785 | 9115 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 9116 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 9117 | |
| 9118 size(3); | |
| 9119 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 9120 ins_encode %{ |
| 9121 __ movsbl($dst$$Register, $src$$Register); | |
| 9122 %} | |
| 9123 ins_pipe(ialu_reg_reg); | |
| 0 | 9124 %} |
| 9125 | |
| 9126 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 9127 // This idiom is used by the compiler the i2s bytecode. | |
| 785 | 9128 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 9129 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 9130 | |
| 9131 size(3); | |
| 9132 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 9133 ins_encode %{ |
| 9134 __ movswl($dst$$Register, $src$$Register); | |
| 9135 %} | |
| 9136 ins_pipe(ialu_reg_reg); | |
| 0 | 9137 %} |
| 9138 | |
| 9139 | |
| 9140 // Logical Shift Right by variable | |
| 9141 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9142 match(Set dst (URShiftI dst shift)); | |
| 9143 effect(KILL cr); | |
| 9144 | |
| 9145 size(2); | |
| 9146 format %{ "SHR $dst,$shift" %} | |
| 9147 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9148 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9149 ins_pipe( ialu_reg_reg ); | |
| 9150 %} | |
| 9151 | |
| 9152 | |
| 9153 //----------Logical Instructions----------------------------------------------- | |
| 9154 //----------Integer Logical Instructions--------------------------------------- | |
| 9155 // And Instructions | |
| 9156 // And Register with Register | |
| 9157 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9158 match(Set dst (AndI dst src)); | |
| 9159 effect(KILL cr); | |
| 9160 | |
| 9161 size(2); | |
| 9162 format %{ "AND $dst,$src" %} | |
| 9163 opcode(0x23); | |
| 9164 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9165 ins_pipe( ialu_reg_reg ); | |
| 9166 %} | |
| 9167 | |
| 9168 // And Register with Immediate | |
| 9169 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9170 match(Set dst (AndI dst src)); | |
| 9171 effect(KILL cr); | |
| 9172 | |
| 9173 format %{ "AND $dst,$src" %} | |
| 9174 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 9175 // ins_encode( RegImm( dst, src) ); | |
| 9176 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9177 ins_pipe( ialu_reg ); | |
| 9178 %} | |
| 9179 | |
| 9180 // And Register with Memory | |
| 9181 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9182 match(Set dst (AndI dst (LoadI src))); | |
| 9183 effect(KILL cr); | |
| 9184 | |
| 9185 ins_cost(125); | |
| 9186 format %{ "AND $dst,$src" %} | |
| 9187 opcode(0x23); | |
| 9188 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9189 ins_pipe( ialu_reg_mem ); | |
| 9190 %} | |
| 9191 | |
| 9192 // And Memory with Register | |
| 9193 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9194 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9195 effect(KILL cr); | |
| 9196 | |
| 9197 ins_cost(150); | |
| 9198 format %{ "AND $dst,$src" %} | |
| 9199 opcode(0x21); /* Opcode 21 /r */ | |
| 9200 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9201 ins_pipe( ialu_mem_reg ); | |
| 9202 %} | |
| 9203 | |
| 9204 // And Memory with Immediate | |
| 9205 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9206 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9207 effect(KILL cr); | |
| 9208 | |
| 9209 ins_cost(125); | |
| 9210 format %{ "AND $dst,$src" %} | |
| 9211 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9212 // ins_encode( MemImm( dst, src) ); | |
| 9213 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9214 ins_pipe( ialu_mem_imm ); | |
| 9215 %} | |
| 9216 | |
| 9217 // Or Instructions | |
| 9218 // Or Register with Register | |
| 9219 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9220 match(Set dst (OrI dst src)); | |
| 9221 effect(KILL cr); | |
| 9222 | |
| 9223 size(2); | |
| 9224 format %{ "OR $dst,$src" %} | |
| 9225 opcode(0x0B); | |
| 9226 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9227 ins_pipe( ialu_reg_reg ); | |
| 9228 %} | |
| 9229 | |
|
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9230 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ |
|
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9231 match(Set dst (OrI dst (CastP2X src))); |
|
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|
9232 effect(KILL cr); |
|
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|
9233 |
|
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|
9234 size(2); |
|
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9235 format %{ "OR $dst,$src" %} |
|
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|
9236 opcode(0x0B); |
|
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9237 ins_encode( OpcP, RegReg( dst, src) ); |
|
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9238 ins_pipe( ialu_reg_reg ); |
|
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|
9239 %} |
|
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9240 |
|
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9241 |
| 0 | 9242 // Or Register with Immediate |
| 9243 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9244 match(Set dst (OrI dst src)); | |
| 9245 effect(KILL cr); | |
| 9246 | |
| 9247 format %{ "OR $dst,$src" %} | |
| 9248 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 9249 // ins_encode( RegImm( dst, src) ); | |
| 9250 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9251 ins_pipe( ialu_reg ); | |
| 9252 %} | |
| 9253 | |
| 9254 // Or Register with Memory | |
| 9255 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9256 match(Set dst (OrI dst (LoadI src))); | |
| 9257 effect(KILL cr); | |
| 9258 | |
| 9259 ins_cost(125); | |
| 9260 format %{ "OR $dst,$src" %} | |
| 9261 opcode(0x0B); | |
| 9262 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9263 ins_pipe( ialu_reg_mem ); | |
| 9264 %} | |
| 9265 | |
| 9266 // Or Memory with Register | |
| 9267 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9268 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9269 effect(KILL cr); | |
| 9270 | |
| 9271 ins_cost(150); | |
| 9272 format %{ "OR $dst,$src" %} | |
| 9273 opcode(0x09); /* Opcode 09 /r */ | |
| 9274 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9275 ins_pipe( ialu_mem_reg ); | |
| 9276 %} | |
| 9277 | |
| 9278 // Or Memory with Immediate | |
| 9279 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9280 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9281 effect(KILL cr); | |
| 9282 | |
| 9283 ins_cost(125); | |
| 9284 format %{ "OR $dst,$src" %} | |
| 9285 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 9286 // ins_encode( MemImm( dst, src) ); | |
| 9287 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9288 ins_pipe( ialu_mem_imm ); | |
| 9289 %} | |
| 9290 | |
| 9291 // ROL/ROR | |
| 9292 // ROL expand | |
| 9293 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9294 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9295 | |
| 9296 format %{ "ROL $dst, $shift" %} | |
| 9297 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9298 ins_encode( OpcP, RegOpc( dst )); | |
| 9299 ins_pipe( ialu_reg ); | |
| 9300 %} | |
| 9301 | |
| 9302 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9303 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9304 | |
| 9305 format %{ "ROL $dst, $shift" %} | |
| 9306 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 9307 ins_encode( RegOpcImm(dst, shift) ); | |
| 9308 ins_pipe(ialu_reg); | |
| 9309 %} | |
| 9310 | |
| 9311 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9312 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9313 | |
| 9314 format %{ "ROL $dst, $shift" %} | |
| 9315 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9316 ins_encode(OpcP, RegOpc(dst)); | |
| 9317 ins_pipe( ialu_reg_reg ); | |
| 9318 %} | |
| 9319 // end of ROL expand | |
| 9320 | |
| 9321 // ROL 32bit by one once | |
| 9322 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ | |
| 9323 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9324 | |
| 9325 expand %{ | |
| 9326 rolI_eReg_imm1(dst, lshift, cr); | |
| 9327 %} | |
| 9328 %} | |
| 9329 | |
| 9330 // ROL 32bit var by imm8 once | |
| 9331 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ | |
| 9332 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9333 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9334 | |
| 9335 expand %{ | |
| 9336 rolI_eReg_imm8(dst, lshift, cr); | |
| 9337 %} | |
| 9338 %} | |
| 9339 | |
| 9340 // ROL 32bit var by var once | |
| 9341 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9342 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9343 | |
| 9344 expand %{ | |
| 9345 rolI_eReg_CL(dst, shift, cr); | |
| 9346 %} | |
| 9347 %} | |
| 9348 | |
| 9349 // ROL 32bit var by var once | |
| 9350 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9351 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9352 | |
| 9353 expand %{ | |
| 9354 rolI_eReg_CL(dst, shift, cr); | |
| 9355 %} | |
| 9356 %} | |
| 9357 | |
| 9358 // ROR expand | |
| 9359 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9360 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9361 | |
| 9362 format %{ "ROR $dst, $shift" %} | |
| 9363 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 9364 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9365 ins_pipe( ialu_reg ); | |
| 9366 %} | |
| 9367 | |
| 9368 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9369 effect (USE_DEF dst, USE shift, KILL cr); | |
| 9370 | |
| 9371 format %{ "ROR $dst, $shift" %} | |
| 9372 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 9373 ins_encode( RegOpcImm(dst, shift) ); | |
| 9374 ins_pipe( ialu_reg ); | |
| 9375 %} | |
| 9376 | |
| 9377 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 9378 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9379 | |
| 9380 format %{ "ROR $dst, $shift" %} | |
| 9381 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 9382 ins_encode(OpcP, RegOpc(dst)); | |
| 9383 ins_pipe( ialu_reg_reg ); | |
| 9384 %} | |
| 9385 // end of ROR expand | |
| 9386 | |
| 9387 // ROR right once | |
| 9388 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ | |
| 9389 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9390 | |
| 9391 expand %{ | |
| 9392 rorI_eReg_imm1(dst, rshift, cr); | |
| 9393 %} | |
| 9394 %} | |
| 9395 | |
| 9396 // ROR 32bit by immI8 once | |
| 9397 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ | |
| 9398 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9399 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9400 | |
| 9401 expand %{ | |
| 9402 rorI_eReg_imm8(dst, rshift, cr); | |
| 9403 %} | |
| 9404 %} | |
| 9405 | |
| 9406 // ROR 32bit var by var once | |
| 9407 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9408 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9409 | |
| 9410 expand %{ | |
| 9411 rorI_eReg_CL(dst, shift, cr); | |
| 9412 %} | |
| 9413 %} | |
| 9414 | |
| 9415 // ROR 32bit var by var once | |
| 9416 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9417 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9418 | |
| 9419 expand %{ | |
| 9420 rorI_eReg_CL(dst, shift, cr); | |
| 9421 %} | |
| 9422 %} | |
| 9423 | |
| 9424 // Xor Instructions | |
| 9425 // Xor Register with Register | |
| 9426 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9427 match(Set dst (XorI dst src)); | |
| 9428 effect(KILL cr); | |
| 9429 | |
| 9430 size(2); | |
| 9431 format %{ "XOR $dst,$src" %} | |
| 9432 opcode(0x33); | |
| 9433 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9434 ins_pipe( ialu_reg_reg ); | |
| 9435 %} | |
| 9436 | |
| 403 | 9437 // Xor Register with Immediate -1 |
| 9438 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ | |
| 9439 match(Set dst (XorI dst imm)); | |
| 9440 | |
| 9441 size(2); | |
| 9442 format %{ "NOT $dst" %} | |
| 9443 ins_encode %{ | |
| 9444 __ notl($dst$$Register); | |
| 9445 %} | |
| 9446 ins_pipe( ialu_reg ); | |
| 9447 %} | |
| 9448 | |
| 0 | 9449 // Xor Register with Immediate |
| 9450 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9451 match(Set dst (XorI dst src)); | |
| 9452 effect(KILL cr); | |
| 9453 | |
| 9454 format %{ "XOR $dst,$src" %} | |
| 9455 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 9456 // ins_encode( RegImm( dst, src) ); | |
| 9457 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9458 ins_pipe( ialu_reg ); | |
| 9459 %} | |
| 9460 | |
| 9461 // Xor Register with Memory | |
| 9462 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9463 match(Set dst (XorI dst (LoadI src))); | |
| 9464 effect(KILL cr); | |
| 9465 | |
| 9466 ins_cost(125); | |
| 9467 format %{ "XOR $dst,$src" %} | |
| 9468 opcode(0x33); | |
| 9469 ins_encode( OpcP, RegMem(dst, src) ); | |
| 9470 ins_pipe( ialu_reg_mem ); | |
| 9471 %} | |
| 9472 | |
| 9473 // Xor Memory with Register | |
| 9474 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9475 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9476 effect(KILL cr); | |
| 9477 | |
| 9478 ins_cost(150); | |
| 9479 format %{ "XOR $dst,$src" %} | |
| 9480 opcode(0x31); /* Opcode 31 /r */ | |
| 9481 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9482 ins_pipe( ialu_mem_reg ); | |
| 9483 %} | |
| 9484 | |
| 9485 // Xor Memory with Immediate | |
| 9486 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9487 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9488 effect(KILL cr); | |
| 9489 | |
| 9490 ins_cost(125); | |
| 9491 format %{ "XOR $dst,$src" %} | |
| 9492 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 9493 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9494 ins_pipe( ialu_mem_imm ); | |
| 9495 %} | |
| 9496 | |
| 9497 //----------Convert Int to Boolean--------------------------------------------- | |
| 9498 | |
| 9499 instruct movI_nocopy(eRegI dst, eRegI src) %{ | |
| 9500 effect( DEF dst, USE src ); | |
| 9501 format %{ "MOV $dst,$src" %} | |
| 9502 ins_encode( enc_Copy( dst, src) ); | |
| 9503 ins_pipe( ialu_reg_reg ); | |
| 9504 %} | |
| 9505 | |
| 9506 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9507 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9508 | |
| 9509 size(4); | |
| 9510 format %{ "NEG $dst\n\t" | |
| 9511 "ADC $dst,$src" %} | |
| 9512 ins_encode( neg_reg(dst), | |
| 9513 OpcRegReg(0x13,dst,src) ); | |
| 9514 ins_pipe( ialu_reg_reg_long ); | |
| 9515 %} | |
| 9516 | |
| 9517 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9518 match(Set dst (Conv2B src)); | |
| 9519 | |
| 9520 expand %{ | |
| 9521 movI_nocopy(dst,src); | |
| 9522 ci2b(dst,src,cr); | |
| 9523 %} | |
| 9524 %} | |
| 9525 | |
| 9526 instruct movP_nocopy(eRegI dst, eRegP src) %{ | |
| 9527 effect( DEF dst, USE src ); | |
| 9528 format %{ "MOV $dst,$src" %} | |
| 9529 ins_encode( enc_Copy( dst, src) ); | |
| 9530 ins_pipe( ialu_reg_reg ); | |
| 9531 %} | |
| 9532 | |
| 9533 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9534 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9535 format %{ "NEG $dst\n\t" | |
| 9536 "ADC $dst,$src" %} | |
| 9537 ins_encode( neg_reg(dst), | |
| 9538 OpcRegReg(0x13,dst,src) ); | |
| 9539 ins_pipe( ialu_reg_reg_long ); | |
| 9540 %} | |
| 9541 | |
| 9542 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9543 match(Set dst (Conv2B src)); | |
| 9544 | |
| 9545 expand %{ | |
| 9546 movP_nocopy(dst,src); | |
| 9547 cp2b(dst,src,cr); | |
| 9548 %} | |
| 9549 %} | |
| 9550 | |
| 9551 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 9552 match(Set dst (CmpLTMask p q)); | |
| 9553 effect( KILL cr ); | |
| 9554 ins_cost(400); | |
| 9555 | |
| 9556 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 9557 format %{ "XOR $dst,$dst\n\t" | |
| 9558 "CMP $p,$q\n\t" | |
| 9559 "SETlt $dst\n\t" | |
| 9560 "NEG $dst" %} | |
| 9561 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 9562 OpcRegReg(0x3B,p,q), | |
| 9563 setLT_reg(dst), neg_reg(dst) ); | |
| 9564 ins_pipe( pipe_slow ); | |
| 9565 %} | |
| 9566 | |
| 9567 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ | |
| 9568 match(Set dst (CmpLTMask dst zero)); | |
| 9569 effect( DEF dst, KILL cr ); | |
| 9570 ins_cost(100); | |
| 9571 | |
| 9572 format %{ "SAR $dst,31" %} | |
| 9573 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9574 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 9575 ins_pipe( ialu_reg ); | |
| 9576 %} | |
| 9577 | |
| 9578 | |
| 9579 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9580 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9581 effect( KILL tmp, KILL cr ); | |
| 9582 ins_cost(400); | |
| 9583 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 9584 // any format or encoding | |
| 9585 format %{ "SUB $p,$q\n\t" | |
| 9586 "SBB ECX,ECX\n\t" | |
| 9587 "AND ECX,$y\n\t" | |
| 9588 "ADD $p,ECX" %} | |
| 9589 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 9590 ins_pipe( pipe_cmplt ); | |
| 9591 %} | |
| 9592 | |
| 9593 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9594 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9595 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9596 effect( USE_KILL tmp, KILL cr ); | |
| 9597 ins_cost(400); | |
| 9598 | |
| 9599 format %{ "SUB $p,$q\n\t" | |
| 9600 "SBB ECX,ECX\n\t" | |
| 9601 "AND ECX,$y\n\t" | |
| 9602 "ADD $p,ECX" %} | |
| 9603 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9604 %} | |
| 9605 */ | |
| 9606 | |
| 9607 //----------Long Instructions------------------------------------------------ | |
| 9608 // Add Long Register with Register | |
| 9609 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9610 match(Set dst (AddL dst src)); | |
| 9611 effect(KILL cr); | |
| 9612 ins_cost(200); | |
| 9613 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9614 "ADC $dst.hi,$src.hi" %} | |
| 9615 opcode(0x03, 0x13); | |
| 9616 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9617 ins_pipe( ialu_reg_reg_long ); | |
| 9618 %} | |
| 9619 | |
| 9620 // Add Long Register with Immediate | |
| 9621 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9622 match(Set dst (AddL dst src)); | |
| 9623 effect(KILL cr); | |
| 9624 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9625 "ADC $dst.hi,$src.hi" %} | |
| 9626 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9627 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9628 ins_pipe( ialu_reg_long ); | |
| 9629 %} | |
| 9630 | |
| 9631 // Add Long Register with Memory | |
| 9632 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9633 match(Set dst (AddL dst (LoadL mem))); | |
| 9634 effect(KILL cr); | |
| 9635 ins_cost(125); | |
| 9636 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9637 "ADC $dst.hi,$mem+4" %} | |
| 9638 opcode(0x03, 0x13); | |
| 9639 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9640 ins_pipe( ialu_reg_long_mem ); | |
| 9641 %} | |
| 9642 | |
| 9643 // Subtract Long Register with Register. | |
| 9644 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9645 match(Set dst (SubL dst src)); | |
| 9646 effect(KILL cr); | |
| 9647 ins_cost(200); | |
| 9648 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9649 "SBB $dst.hi,$src.hi" %} | |
| 9650 opcode(0x2B, 0x1B); | |
| 9651 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9652 ins_pipe( ialu_reg_reg_long ); | |
| 9653 %} | |
| 9654 | |
| 9655 // Subtract Long Register with Immediate | |
| 9656 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9657 match(Set dst (SubL dst src)); | |
| 9658 effect(KILL cr); | |
| 9659 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9660 "SBB $dst.hi,$src.hi" %} | |
| 9661 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9662 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9663 ins_pipe( ialu_reg_long ); | |
| 9664 %} | |
| 9665 | |
| 9666 // Subtract Long Register with Memory | |
| 9667 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9668 match(Set dst (SubL dst (LoadL mem))); | |
| 9669 effect(KILL cr); | |
| 9670 ins_cost(125); | |
| 9671 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9672 "SBB $dst.hi,$mem+4" %} | |
| 9673 opcode(0x2B, 0x1B); | |
| 9674 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9675 ins_pipe( ialu_reg_long_mem ); | |
| 9676 %} | |
| 9677 | |
| 9678 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9679 match(Set dst (SubL zero dst)); | |
| 9680 effect(KILL cr); | |
| 9681 ins_cost(300); | |
| 9682 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9683 ins_encode( neg_long(dst) ); | |
| 9684 ins_pipe( ialu_reg_reg_long ); | |
| 9685 %} | |
| 9686 | |
| 9687 // And Long Register with Register | |
| 9688 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9689 match(Set dst (AndL dst src)); | |
| 9690 effect(KILL cr); | |
| 9691 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9692 "AND $dst.hi,$src.hi" %} | |
| 9693 opcode(0x23,0x23); | |
| 9694 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9695 ins_pipe( ialu_reg_reg_long ); | |
| 9696 %} | |
| 9697 | |
| 9698 // And Long Register with Immediate | |
| 9699 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9700 match(Set dst (AndL dst src)); | |
| 9701 effect(KILL cr); | |
| 9702 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9703 "AND $dst.hi,$src.hi" %} | |
| 9704 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9705 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9706 ins_pipe( ialu_reg_long ); | |
| 9707 %} | |
| 9708 | |
| 9709 // And Long Register with Memory | |
| 9710 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9711 match(Set dst (AndL dst (LoadL mem))); | |
| 9712 effect(KILL cr); | |
| 9713 ins_cost(125); | |
| 9714 format %{ "AND $dst.lo,$mem\n\t" | |
| 9715 "AND $dst.hi,$mem+4" %} | |
| 9716 opcode(0x23, 0x23); | |
| 9717 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9718 ins_pipe( ialu_reg_long_mem ); | |
| 9719 %} | |
| 9720 | |
| 9721 // Or Long Register with Register | |
| 9722 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9723 match(Set dst (OrL dst src)); | |
| 9724 effect(KILL cr); | |
| 9725 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9726 "OR $dst.hi,$src.hi" %} | |
| 9727 opcode(0x0B,0x0B); | |
| 9728 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9729 ins_pipe( ialu_reg_reg_long ); | |
| 9730 %} | |
| 9731 | |
| 9732 // Or Long Register with Immediate | |
| 9733 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9734 match(Set dst (OrL dst src)); | |
| 9735 effect(KILL cr); | |
| 9736 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9737 "OR $dst.hi,$src.hi" %} | |
| 9738 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9739 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9740 ins_pipe( ialu_reg_long ); | |
| 9741 %} | |
| 9742 | |
| 9743 // Or Long Register with Memory | |
| 9744 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9745 match(Set dst (OrL dst (LoadL mem))); | |
| 9746 effect(KILL cr); | |
| 9747 ins_cost(125); | |
| 9748 format %{ "OR $dst.lo,$mem\n\t" | |
| 9749 "OR $dst.hi,$mem+4" %} | |
| 9750 opcode(0x0B,0x0B); | |
| 9751 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9752 ins_pipe( ialu_reg_long_mem ); | |
| 9753 %} | |
| 9754 | |
| 9755 // Xor Long Register with Register | |
| 9756 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9757 match(Set dst (XorL dst src)); | |
| 9758 effect(KILL cr); | |
| 9759 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9760 "XOR $dst.hi,$src.hi" %} | |
| 9761 opcode(0x33,0x33); | |
| 9762 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9763 ins_pipe( ialu_reg_reg_long ); | |
| 9764 %} | |
| 9765 | |
| 403 | 9766 // Xor Long Register with Immediate -1 |
| 9767 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9768 match(Set dst (XorL dst imm)); | |
| 9769 format %{ "NOT $dst.lo\n\t" | |
| 9770 "NOT $dst.hi" %} | |
| 9771 ins_encode %{ | |
| 9772 __ notl($dst$$Register); | |
| 9773 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9774 %} | |
| 9775 ins_pipe( ialu_reg_long ); | |
| 9776 %} | |
| 9777 | |
| 0 | 9778 // Xor Long Register with Immediate |
| 9779 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9780 match(Set dst (XorL dst src)); | |
| 9781 effect(KILL cr); | |
| 9782 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9783 "XOR $dst.hi,$src.hi" %} | |
| 9784 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9785 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9786 ins_pipe( ialu_reg_long ); | |
| 9787 %} | |
| 9788 | |
| 9789 // Xor Long Register with Memory | |
| 9790 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9791 match(Set dst (XorL dst (LoadL mem))); | |
| 9792 effect(KILL cr); | |
| 9793 ins_cost(125); | |
| 9794 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9795 "XOR $dst.hi,$mem+4" %} | |
| 9796 opcode(0x33,0x33); | |
| 9797 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9798 ins_pipe( ialu_reg_long_mem ); | |
| 9799 %} | |
| 9800 | |
| 219 | 9801 // Shift Left Long by 1 |
| 9802 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9803 predicate(UseNewLongLShift); | |
| 9804 match(Set dst (LShiftL dst cnt)); | |
| 9805 effect(KILL cr); | |
| 9806 ins_cost(100); | |
| 9807 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9808 "ADC $dst.hi,$dst.hi" %} | |
| 9809 ins_encode %{ | |
| 9810 __ addl($dst$$Register,$dst$$Register); | |
| 9811 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9812 %} | |
| 9813 ins_pipe( ialu_reg_long ); | |
| 9814 %} | |
| 9815 | |
| 9816 // Shift Left Long by 2 | |
| 9817 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9818 predicate(UseNewLongLShift); | |
| 9819 match(Set dst (LShiftL dst cnt)); | |
| 9820 effect(KILL cr); | |
| 9821 ins_cost(100); | |
| 9822 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9823 "ADC $dst.hi,$dst.hi\n\t" | |
| 9824 "ADD $dst.lo,$dst.lo\n\t" | |
| 9825 "ADC $dst.hi,$dst.hi" %} | |
| 9826 ins_encode %{ | |
| 9827 __ addl($dst$$Register,$dst$$Register); | |
| 9828 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9829 __ addl($dst$$Register,$dst$$Register); | |
| 9830 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9831 %} | |
| 9832 ins_pipe( ialu_reg_long ); | |
| 9833 %} | |
| 9834 | |
| 9835 // Shift Left Long by 3 | |
| 9836 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9837 predicate(UseNewLongLShift); | |
| 9838 match(Set dst (LShiftL dst cnt)); | |
| 9839 effect(KILL cr); | |
| 9840 ins_cost(100); | |
| 9841 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9842 "ADC $dst.hi,$dst.hi\n\t" | |
| 9843 "ADD $dst.lo,$dst.lo\n\t" | |
| 9844 "ADC $dst.hi,$dst.hi\n\t" | |
| 9845 "ADD $dst.lo,$dst.lo\n\t" | |
| 9846 "ADC $dst.hi,$dst.hi" %} | |
| 9847 ins_encode %{ | |
| 9848 __ addl($dst$$Register,$dst$$Register); | |
| 9849 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9850 __ addl($dst$$Register,$dst$$Register); | |
| 9851 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9852 __ addl($dst$$Register,$dst$$Register); | |
| 9853 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9854 %} | |
| 9855 ins_pipe( ialu_reg_long ); | |
| 9856 %} | |
| 9857 | |
| 0 | 9858 // Shift Left Long by 1-31 |
| 9859 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9860 match(Set dst (LShiftL dst cnt)); | |
| 9861 effect(KILL cr); | |
| 9862 ins_cost(200); | |
| 9863 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9864 "SHL $dst.lo,$cnt" %} | |
| 9865 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9866 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9867 ins_pipe( ialu_reg_long ); | |
| 9868 %} | |
| 9869 | |
| 9870 // Shift Left Long by 32-63 | |
| 9871 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9872 match(Set dst (LShiftL dst cnt)); | |
| 9873 effect(KILL cr); | |
| 9874 ins_cost(300); | |
| 9875 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9876 "\tSHL $dst.hi,$cnt-32\n" | |
| 9877 "\tXOR $dst.lo,$dst.lo" %} | |
| 9878 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9879 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9880 ins_pipe( ialu_reg_long ); | |
| 9881 %} | |
| 9882 | |
| 9883 // Shift Left Long by variable | |
| 9884 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9885 match(Set dst (LShiftL dst shift)); | |
| 9886 effect(KILL cr); | |
| 9887 ins_cost(500+200); | |
| 9888 size(17); | |
| 9889 format %{ "TEST $shift,32\n\t" | |
| 9890 "JEQ,s small\n\t" | |
| 9891 "MOV $dst.hi,$dst.lo\n\t" | |
| 9892 "XOR $dst.lo,$dst.lo\n" | |
| 9893 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9894 "SHL $dst.lo,$shift" %} | |
| 9895 ins_encode( shift_left_long( dst, shift ) ); | |
| 9896 ins_pipe( pipe_slow ); | |
| 9897 %} | |
| 9898 | |
| 9899 // Shift Right Long by 1-31 | |
| 9900 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9901 match(Set dst (URShiftL dst cnt)); | |
| 9902 effect(KILL cr); | |
| 9903 ins_cost(200); | |
| 9904 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9905 "SHR $dst.hi,$cnt" %} | |
| 9906 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9907 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9908 ins_pipe( ialu_reg_long ); | |
| 9909 %} | |
| 9910 | |
| 9911 // Shift Right Long by 32-63 | |
| 9912 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9913 match(Set dst (URShiftL dst cnt)); | |
| 9914 effect(KILL cr); | |
| 9915 ins_cost(300); | |
| 9916 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9917 "\tSHR $dst.lo,$cnt-32\n" | |
| 9918 "\tXOR $dst.hi,$dst.hi" %} | |
| 9919 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9920 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9921 ins_pipe( ialu_reg_long ); | |
| 9922 %} | |
| 9923 | |
| 9924 // Shift Right Long by variable | |
| 9925 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9926 match(Set dst (URShiftL dst shift)); | |
| 9927 effect(KILL cr); | |
| 9928 ins_cost(600); | |
| 9929 size(17); | |
| 9930 format %{ "TEST $shift,32\n\t" | |
| 9931 "JEQ,s small\n\t" | |
| 9932 "MOV $dst.lo,$dst.hi\n\t" | |
| 9933 "XOR $dst.hi,$dst.hi\n" | |
| 9934 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9935 "SHR $dst.hi,$shift" %} | |
| 9936 ins_encode( shift_right_long( dst, shift ) ); | |
| 9937 ins_pipe( pipe_slow ); | |
| 9938 %} | |
| 9939 | |
| 9940 // Shift Right Long by 1-31 | |
| 9941 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9942 match(Set dst (RShiftL dst cnt)); | |
| 9943 effect(KILL cr); | |
| 9944 ins_cost(200); | |
| 9945 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9946 "SAR $dst.hi,$cnt" %} | |
| 9947 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9948 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9949 ins_pipe( ialu_reg_long ); | |
| 9950 %} | |
| 9951 | |
| 9952 // Shift Right Long by 32-63 | |
| 9953 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9954 match(Set dst (RShiftL dst cnt)); | |
| 9955 effect(KILL cr); | |
| 9956 ins_cost(300); | |
| 9957 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9958 "\tSAR $dst.lo,$cnt-32\n" | |
| 9959 "\tSAR $dst.hi,31" %} | |
| 9960 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9961 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9962 ins_pipe( ialu_reg_long ); | |
| 9963 %} | |
| 9964 | |
| 9965 // Shift Right arithmetic Long by variable | |
| 9966 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9967 match(Set dst (RShiftL dst shift)); | |
| 9968 effect(KILL cr); | |
| 9969 ins_cost(600); | |
| 9970 size(18); | |
| 9971 format %{ "TEST $shift,32\n\t" | |
| 9972 "JEQ,s small\n\t" | |
| 9973 "MOV $dst.lo,$dst.hi\n\t" | |
| 9974 "SAR $dst.hi,31\n" | |
| 9975 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9976 "SAR $dst.hi,$shift" %} | |
| 9977 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9978 ins_pipe( pipe_slow ); | |
| 9979 %} | |
| 9980 | |
| 9981 | |
| 9982 //----------Double Instructions------------------------------------------------ | |
| 9983 // Double Math | |
| 9984 | |
| 9985 // Compare & branch | |
| 9986 | |
| 9987 // P6 version of float compare, sets condition codes in EFLAGS | |
| 9988 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9989 predicate(VM_Version::supports_cmov() && UseSSE <=1); | |
| 9990 match(Set cr (CmpD src1 src2)); | |
| 9991 effect(KILL rax); | |
| 9992 ins_cost(150); | |
| 9993 format %{ "FLD $src1\n\t" | |
| 9994 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9995 "JNP exit\n\t" | |
| 9996 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9997 "SAHF\n" | |
| 9998 "exit:\tNOP // avoid branch to branch" %} | |
| 9999 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 10000 ins_encode( Push_Reg_D(src1), | |
| 10001 OpcP, RegOpc(src2), | |
| 10002 cmpF_P6_fixup ); | |
| 10003 ins_pipe( pipe_slow ); | |
| 10004 %} | |
| 10005 | |
|
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10006 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
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10007 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
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10008 match(Set cr (CmpD src1 src2)); |
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10009 ins_cost(150); |
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10010 format %{ "FLD $src1\n\t" |
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10011 "FUCOMIP ST,$src2 // P6 instruction" %} |
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10012 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
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10013 ins_encode( Push_Reg_D(src1), |
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10014 OpcP, RegOpc(src2)); |
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10015 ins_pipe( pipe_slow ); |
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10016 %} |
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10017 |
| 0 | 10018 // Compare & branch |
| 10019 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 10020 predicate(UseSSE<=1); | |
| 10021 match(Set cr (CmpD src1 src2)); | |
| 10022 effect(KILL rax); | |
| 10023 ins_cost(200); | |
| 10024 format %{ "FLD $src1\n\t" | |
| 10025 "FCOMp $src2\n\t" | |
| 10026 "FNSTSW AX\n\t" | |
| 10027 "TEST AX,0x400\n\t" | |
| 10028 "JZ,s flags\n\t" | |
| 10029 "MOV AH,1\t# unordered treat as LT\n" | |
| 10030 "flags:\tSAHF" %} | |
| 10031 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10032 ins_encode( Push_Reg_D(src1), | |
| 10033 OpcP, RegOpc(src2), | |
| 10034 fpu_flags); | |
| 10035 ins_pipe( pipe_slow ); | |
| 10036 %} | |
| 10037 | |
| 10038 // Compare vs zero into -1,0,1 | |
| 10039 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 10040 predicate(UseSSE<=1); | |
| 10041 match(Set dst (CmpD3 src1 zero)); | |
| 10042 effect(KILL cr, KILL rax); | |
| 10043 ins_cost(280); | |
| 10044 format %{ "FTSTD $dst,$src1" %} | |
| 10045 opcode(0xE4, 0xD9); | |
| 10046 ins_encode( Push_Reg_D(src1), | |
| 10047 OpcS, OpcP, PopFPU, | |
| 10048 CmpF_Result(dst)); | |
| 10049 ins_pipe( pipe_slow ); | |
| 10050 %} | |
| 10051 | |
| 10052 // Compare into -1,0,1 | |
| 10053 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 10054 predicate(UseSSE<=1); | |
| 10055 match(Set dst (CmpD3 src1 src2)); | |
| 10056 effect(KILL cr, KILL rax); | |
| 10057 ins_cost(300); | |
| 10058 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 10059 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10060 ins_encode( Push_Reg_D(src1), | |
| 10061 OpcP, RegOpc(src2), | |
| 10062 CmpF_Result(dst)); | |
| 10063 ins_pipe( pipe_slow ); | |
| 10064 %} | |
| 10065 | |
| 10066 // float compare and set condition codes in EFLAGS by XMM regs | |
| 10067 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ | |
| 10068 predicate(UseSSE>=2); | |
| 10069 match(Set cr (CmpD dst src)); | |
| 10070 effect(KILL rax); | |
| 10071 ins_cost(125); | |
| 10072 format %{ "COMISD $dst,$src\n" | |
| 10073 "\tJNP exit\n" | |
| 10074 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10075 "\tSAHF\n" | |
| 10076 "exit:\tNOP // avoid branch to branch" %} | |
| 10077 opcode(0x66, 0x0F, 0x2F); | |
| 10078 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); | |
| 10079 ins_pipe( pipe_slow ); | |
| 10080 %} | |
| 10081 | |
|
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10082 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{ |
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10083 predicate(UseSSE>=2); |
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10084 match(Set cr (CmpD dst src)); |
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10085 ins_cost(100); |
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10086 format %{ "COMISD $dst,$src" %} |
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10087 opcode(0x66, 0x0F, 0x2F); |
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10088 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); |
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10089 ins_pipe( pipe_slow ); |
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10090 %} |
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10091 |
| 0 | 10092 // float compare and set condition codes in EFLAGS by XMM regs |
| 10093 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ | |
| 10094 predicate(UseSSE>=2); | |
| 10095 match(Set cr (CmpD dst (LoadD src))); | |
| 10096 effect(KILL rax); | |
| 10097 ins_cost(145); | |
| 10098 format %{ "COMISD $dst,$src\n" | |
| 10099 "\tJNP exit\n" | |
| 10100 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10101 "\tSAHF\n" | |
| 10102 "exit:\tNOP // avoid branch to branch" %} | |
| 10103 opcode(0x66, 0x0F, 0x2F); | |
| 10104 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); | |
| 10105 ins_pipe( pipe_slow ); | |
| 10106 %} | |
| 10107 | |
|
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10108 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{ |
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10109 predicate(UseSSE>=2); |
|
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10110 match(Set cr (CmpD dst (LoadD src))); |
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10111 ins_cost(100); |
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10112 format %{ "COMISD $dst,$src" %} |
|
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10113 opcode(0x66, 0x0F, 0x2F); |
|
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10114 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src)); |
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10115 ins_pipe( pipe_slow ); |
|
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10116 %} |
|
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10117 |
| 0 | 10118 // Compare into -1,0,1 in XMM |
| 10119 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ | |
| 10120 predicate(UseSSE>=2); | |
| 10121 match(Set dst (CmpD3 src1 src2)); | |
| 10122 effect(KILL cr); | |
| 10123 ins_cost(255); | |
| 10124 format %{ "XOR $dst,$dst\n" | |
| 10125 "\tCOMISD $src1,$src2\n" | |
| 10126 "\tJP,s nan\n" | |
| 10127 "\tJEQ,s exit\n" | |
| 10128 "\tJA,s inc\n" | |
| 10129 "nan:\tDEC $dst\n" | |
| 10130 "\tJMP,s exit\n" | |
| 10131 "inc:\tINC $dst\n" | |
| 10132 "exit:" | |
| 10133 %} | |
| 10134 opcode(0x66, 0x0F, 0x2F); | |
| 10135 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), | |
| 10136 CmpX_Result(dst)); | |
| 10137 ins_pipe( pipe_slow ); | |
| 10138 %} | |
| 10139 | |
| 10140 // Compare into -1,0,1 in XMM and memory | |
| 10141 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ | |
| 10142 predicate(UseSSE>=2); | |
| 10143 match(Set dst (CmpD3 src1 (LoadD mem))); | |
| 10144 effect(KILL cr); | |
| 10145 ins_cost(275); | |
| 10146 format %{ "COMISD $src1,$mem\n" | |
| 10147 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 10148 "\tJP,s nan\n" | |
| 10149 "\tJEQ,s exit\n" | |
| 10150 "\tJA,s inc\n" | |
| 10151 "nan:\tDEC $dst\n" | |
| 10152 "\tJMP,s exit\n" | |
| 10153 "inc:\tINC $dst\n" | |
| 10154 "exit:" | |
| 10155 %} | |
| 10156 opcode(0x66, 0x0F, 0x2F); | |
| 10157 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), | |
| 10158 LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 10159 ins_pipe( pipe_slow ); | |
| 10160 %} | |
| 10161 | |
| 10162 | |
| 10163 instruct subD_reg(regD dst, regD src) %{ | |
| 10164 predicate (UseSSE <=1); | |
| 10165 match(Set dst (SubD dst src)); | |
| 10166 | |
| 10167 format %{ "FLD $src\n\t" | |
| 10168 "DSUBp $dst,ST" %} | |
| 10169 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 10170 ins_cost(150); | |
| 10171 ins_encode( Push_Reg_D(src), | |
| 10172 OpcP, RegOpc(dst) ); | |
| 10173 ins_pipe( fpu_reg_reg ); | |
| 10174 %} | |
| 10175 | |
| 10176 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10177 predicate (UseSSE <=1); | |
| 10178 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 10179 ins_cost(250); | |
| 10180 | |
| 10181 format %{ "FLD $src2\n\t" | |
| 10182 "DSUB ST,$src1\n\t" | |
| 10183 "FSTP_D $dst\t# D-round" %} | |
| 10184 opcode(0xD8, 0x5); | |
| 10185 ins_encode( Push_Reg_D(src2), | |
| 10186 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10187 ins_pipe( fpu_mem_reg_reg ); | |
| 10188 %} | |
| 10189 | |
| 10190 | |
| 10191 instruct subD_reg_mem(regD dst, memory src) %{ | |
| 10192 predicate (UseSSE <=1); | |
| 10193 match(Set dst (SubD dst (LoadD src))); | |
| 10194 ins_cost(150); | |
| 10195 | |
| 10196 format %{ "FLD $src\n\t" | |
| 10197 "DSUBp $dst,ST" %} | |
| 10198 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10199 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10200 OpcP, RegOpc(dst) ); | |
| 10201 ins_pipe( fpu_reg_mem ); | |
| 10202 %} | |
| 10203 | |
| 10204 instruct absD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10205 predicate (UseSSE<=1); | |
| 10206 match(Set dst (AbsD src)); | |
| 10207 ins_cost(100); | |
| 10208 format %{ "FABS" %} | |
| 10209 opcode(0xE1, 0xD9); | |
| 10210 ins_encode( OpcS, OpcP ); | |
| 10211 ins_pipe( fpu_reg_reg ); | |
| 10212 %} | |
| 10213 | |
| 10214 instruct absXD_reg( regXD dst ) %{ | |
| 10215 predicate(UseSSE>=2); | |
| 10216 match(Set dst (AbsD dst)); | |
| 10217 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} | |
| 10218 ins_encode( AbsXD_encoding(dst)); | |
| 10219 ins_pipe( pipe_slow ); | |
| 10220 %} | |
| 10221 | |
| 10222 instruct negD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10223 predicate(UseSSE<=1); | |
| 10224 match(Set dst (NegD src)); | |
| 10225 ins_cost(100); | |
| 10226 format %{ "FCHS" %} | |
| 10227 opcode(0xE0, 0xD9); | |
| 10228 ins_encode( OpcS, OpcP ); | |
| 10229 ins_pipe( fpu_reg_reg ); | |
| 10230 %} | |
| 10231 | |
| 10232 instruct negXD_reg( regXD dst ) %{ | |
| 10233 predicate(UseSSE>=2); | |
| 10234 match(Set dst (NegD dst)); | |
| 10235 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} | |
| 10236 ins_encode %{ | |
| 10237 __ xorpd($dst$$XMMRegister, | |
| 10238 ExternalAddress((address)double_signflip_pool)); | |
| 10239 %} | |
| 10240 ins_pipe( pipe_slow ); | |
| 10241 %} | |
| 10242 | |
| 10243 instruct addD_reg(regD dst, regD src) %{ | |
| 10244 predicate(UseSSE<=1); | |
| 10245 match(Set dst (AddD dst src)); | |
| 10246 format %{ "FLD $src\n\t" | |
| 10247 "DADD $dst,ST" %} | |
| 10248 size(4); | |
| 10249 ins_cost(150); | |
| 10250 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 10251 ins_encode( Push_Reg_D(src), | |
| 10252 OpcP, RegOpc(dst) ); | |
| 10253 ins_pipe( fpu_reg_reg ); | |
| 10254 %} | |
| 10255 | |
| 10256 | |
| 10257 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10258 predicate(UseSSE<=1); | |
| 10259 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 10260 ins_cost(250); | |
| 10261 | |
| 10262 format %{ "FLD $src2\n\t" | |
| 10263 "DADD ST,$src1\n\t" | |
| 10264 "FSTP_D $dst\t# D-round" %} | |
| 10265 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
| 10266 ins_encode( Push_Reg_D(src2), | |
| 10267 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10268 ins_pipe( fpu_mem_reg_reg ); | |
| 10269 %} | |
| 10270 | |
| 10271 | |
| 10272 instruct addD_reg_mem(regD dst, memory src) %{ | |
| 10273 predicate(UseSSE<=1); | |
| 10274 match(Set dst (AddD dst (LoadD src))); | |
| 10275 ins_cost(150); | |
| 10276 | |
| 10277 format %{ "FLD $src\n\t" | |
| 10278 "DADDp $dst,ST" %} | |
| 10279 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10280 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10281 OpcP, RegOpc(dst) ); | |
| 10282 ins_pipe( fpu_reg_mem ); | |
| 10283 %} | |
| 10284 | |
| 10285 // add-to-memory | |
| 10286 instruct addD_mem_reg(memory dst, regD src) %{ | |
| 10287 predicate(UseSSE<=1); | |
| 10288 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 10289 ins_cost(150); | |
| 10290 | |
| 10291 format %{ "FLD_D $dst\n\t" | |
| 10292 "DADD ST,$src\n\t" | |
| 10293 "FST_D $dst" %} | |
| 10294 opcode(0xDD, 0x0); | |
| 10295 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 10296 Opcode(0xD8), RegOpc(src), | |
| 10297 set_instruction_start, | |
| 10298 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 10299 ins_pipe( fpu_reg_mem ); | |
| 10300 %} | |
| 10301 | |
| 2008 | 10302 instruct addD_reg_imm1(regD dst, immD1 con) %{ |
| 0 | 10303 predicate(UseSSE<=1); |
| 2008 | 10304 match(Set dst (AddD dst con)); |
| 0 | 10305 ins_cost(125); |
| 10306 format %{ "FLD1\n\t" | |
| 10307 "DADDp $dst,ST" %} | |
| 2008 | 10308 ins_encode %{ |
| 10309 __ fld1(); | |
| 10310 __ faddp($dst$$reg); | |
| 10311 %} | |
| 10312 ins_pipe(fpu_reg); | |
| 10313 %} | |
| 10314 | |
| 10315 instruct addD_reg_imm(regD dst, immD con) %{ | |
| 0 | 10316 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 10317 match(Set dst (AddD dst con)); |
| 0 | 10318 ins_cost(200); |
| 2008 | 10319 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10320 "DADDp $dst,ST" %} |
| 2008 | 10321 ins_encode %{ |
| 10322 __ fld_d($constantaddress($con)); | |
| 10323 __ faddp($dst$$reg); | |
| 10324 %} | |
| 10325 ins_pipe(fpu_reg_mem); | |
| 0 | 10326 %} |
| 10327 | |
| 10328 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ | |
| 10329 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); | |
| 10330 match(Set dst (RoundDouble (AddD src con))); | |
| 10331 ins_cost(200); | |
| 2008 | 10332 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10333 "DADD ST,$src\n\t" |
| 10334 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 10335 ins_encode %{ |
| 10336 __ fld_d($constantaddress($con)); | |
| 10337 __ fadd($src$$reg); | |
| 10338 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 10339 %} | |
| 10340 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10341 %} |
| 10342 | |
| 10343 // Add two double precision floating point values in xmm | |
| 10344 instruct addXD_reg(regXD dst, regXD src) %{ | |
| 10345 predicate(UseSSE>=2); | |
| 10346 match(Set dst (AddD dst src)); | |
| 10347 format %{ "ADDSD $dst,$src" %} | |
| 10348 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 10349 ins_pipe( pipe_slow ); | |
| 10350 %} | |
| 10351 | |
| 10352 instruct addXD_imm(regXD dst, immXD con) %{ | |
| 10353 predicate(UseSSE>=2); | |
| 10354 match(Set dst (AddD dst con)); | |
| 2008 | 10355 format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10356 ins_encode %{ | |
| 10357 __ addsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10358 %} | |
| 10359 ins_pipe(pipe_slow); | |
| 0 | 10360 %} |
| 10361 | |
| 10362 instruct addXD_mem(regXD dst, memory mem) %{ | |
| 10363 predicate(UseSSE>=2); | |
| 10364 match(Set dst (AddD dst (LoadD mem))); | |
| 10365 format %{ "ADDSD $dst,$mem" %} | |
| 10366 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); | |
| 10367 ins_pipe( pipe_slow ); | |
| 10368 %} | |
| 10369 | |
| 10370 // Sub two double precision floating point values in xmm | |
| 10371 instruct subXD_reg(regXD dst, regXD src) %{ | |
| 10372 predicate(UseSSE>=2); | |
| 10373 match(Set dst (SubD dst src)); | |
| 10374 format %{ "SUBSD $dst,$src" %} | |
| 10375 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 10376 ins_pipe( pipe_slow ); | |
| 10377 %} | |
| 10378 | |
| 10379 instruct subXD_imm(regXD dst, immXD con) %{ | |
| 10380 predicate(UseSSE>=2); | |
| 10381 match(Set dst (SubD dst con)); | |
| 2008 | 10382 format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10383 ins_encode %{ | |
| 10384 __ subsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10385 %} | |
| 10386 ins_pipe(pipe_slow); | |
| 0 | 10387 %} |
| 10388 | |
| 10389 instruct subXD_mem(regXD dst, memory mem) %{ | |
| 10390 predicate(UseSSE>=2); | |
| 10391 match(Set dst (SubD dst (LoadD mem))); | |
| 10392 format %{ "SUBSD $dst,$mem" %} | |
| 10393 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 10394 ins_pipe( pipe_slow ); | |
| 10395 %} | |
| 10396 | |
| 10397 // Mul two double precision floating point values in xmm | |
| 10398 instruct mulXD_reg(regXD dst, regXD src) %{ | |
| 10399 predicate(UseSSE>=2); | |
| 10400 match(Set dst (MulD dst src)); | |
| 10401 format %{ "MULSD $dst,$src" %} | |
| 10402 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 10403 ins_pipe( pipe_slow ); | |
| 10404 %} | |
| 10405 | |
| 10406 instruct mulXD_imm(regXD dst, immXD con) %{ | |
| 10407 predicate(UseSSE>=2); | |
| 10408 match(Set dst (MulD dst con)); | |
| 2008 | 10409 format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10410 ins_encode %{ | |
| 10411 __ mulsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10412 %} | |
| 10413 ins_pipe(pipe_slow); | |
| 0 | 10414 %} |
| 10415 | |
| 10416 instruct mulXD_mem(regXD dst, memory mem) %{ | |
| 10417 predicate(UseSSE>=2); | |
| 10418 match(Set dst (MulD dst (LoadD mem))); | |
| 10419 format %{ "MULSD $dst,$mem" %} | |
| 10420 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 10421 ins_pipe( pipe_slow ); | |
| 10422 %} | |
| 10423 | |
| 10424 // Div two double precision floating point values in xmm | |
| 10425 instruct divXD_reg(regXD dst, regXD src) %{ | |
| 10426 predicate(UseSSE>=2); | |
| 10427 match(Set dst (DivD dst src)); | |
| 10428 format %{ "DIVSD $dst,$src" %} | |
| 10429 opcode(0xF2, 0x0F, 0x5E); | |
| 10430 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 10431 ins_pipe( pipe_slow ); | |
| 10432 %} | |
| 10433 | |
| 10434 instruct divXD_imm(regXD dst, immXD con) %{ | |
| 10435 predicate(UseSSE>=2); | |
| 10436 match(Set dst (DivD dst con)); | |
| 2008 | 10437 format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10438 ins_encode %{ | |
| 10439 __ divsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10440 %} | |
| 10441 ins_pipe(pipe_slow); | |
| 0 | 10442 %} |
| 10443 | |
| 10444 instruct divXD_mem(regXD dst, memory mem) %{ | |
| 10445 predicate(UseSSE>=2); | |
| 10446 match(Set dst (DivD dst (LoadD mem))); | |
| 10447 format %{ "DIVSD $dst,$mem" %} | |
| 10448 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 10449 ins_pipe( pipe_slow ); | |
| 10450 %} | |
| 10451 | |
| 10452 | |
| 10453 instruct mulD_reg(regD dst, regD src) %{ | |
| 10454 predicate(UseSSE<=1); | |
| 10455 match(Set dst (MulD dst src)); | |
| 10456 format %{ "FLD $src\n\t" | |
| 10457 "DMULp $dst,ST" %} | |
| 10458 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10459 ins_cost(150); | |
| 10460 ins_encode( Push_Reg_D(src), | |
| 10461 OpcP, RegOpc(dst) ); | |
| 10462 ins_pipe( fpu_reg_reg ); | |
| 10463 %} | |
| 10464 | |
| 10465 // Strict FP instruction biases argument before multiply then | |
| 10466 // biases result to avoid double rounding of subnormals. | |
| 10467 // | |
| 10468 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 10469 // load arg2 | |
| 10470 // multiply scaled arg1 by arg2 | |
| 10471 // rescale product by 2^(15360) | |
| 10472 // | |
| 10473 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10474 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10475 match(Set dst (MulD dst src)); | |
| 10476 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 10477 | |
| 10478 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10479 "DMULp $dst,ST\n\t" | |
| 10480 "FLD $src\n\t" | |
| 10481 "DMULp $dst,ST\n\t" | |
| 10482 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10483 "DMULp $dst,ST\n\t" %} | |
| 10484 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10485 ins_encode( strictfp_bias1(dst), | |
| 10486 Push_Reg_D(src), | |
| 10487 OpcP, RegOpc(dst), | |
| 10488 strictfp_bias2(dst) ); | |
| 10489 ins_pipe( fpu_reg_reg ); | |
| 10490 %} | |
| 10491 | |
| 2008 | 10492 instruct mulD_reg_imm(regD dst, immD con) %{ |
| 0 | 10493 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 10494 match(Set dst (MulD dst con)); |
| 0 | 10495 ins_cost(200); |
| 2008 | 10496 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10497 "DMULp $dst,ST" %} |
| 2008 | 10498 ins_encode %{ |
| 10499 __ fld_d($constantaddress($con)); | |
| 10500 __ fmulp($dst$$reg); | |
| 10501 %} | |
| 10502 ins_pipe(fpu_reg_mem); | |
| 0 | 10503 %} |
| 10504 | |
| 10505 | |
| 10506 instruct mulD_reg_mem(regD dst, memory src) %{ | |
| 10507 predicate( UseSSE<=1 ); | |
| 10508 match(Set dst (MulD dst (LoadD src))); | |
| 10509 ins_cost(200); | |
| 10510 format %{ "FLD_D $src\n\t" | |
| 10511 "DMULp $dst,ST" %} | |
| 10512 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 10513 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10514 OpcP, RegOpc(dst) ); | |
| 10515 ins_pipe( fpu_reg_mem ); | |
| 10516 %} | |
| 10517 | |
| 10518 // | |
| 10519 // Cisc-alternate to reg-reg multiply | |
| 10520 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ | |
| 10521 predicate( UseSSE<=1 ); | |
| 10522 match(Set dst (MulD src (LoadD mem))); | |
| 10523 ins_cost(250); | |
| 10524 format %{ "FLD_D $mem\n\t" | |
| 10525 "DMUL ST,$src\n\t" | |
| 10526 "FSTP_D $dst" %} | |
| 10527 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 10528 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
| 10529 OpcReg_F(src), | |
| 10530 Pop_Reg_D(dst) ); | |
| 10531 ins_pipe( fpu_reg_reg_mem ); | |
| 10532 %} | |
| 10533 | |
| 10534 | |
| 10535 // MACRO3 -- addD a mulD | |
| 10536 // This instruction is a '2-address' instruction in that the result goes | |
| 10537 // back to src2. This eliminates a move from the macro; possibly the | |
| 10538 // register allocator will have to add it back (and maybe not). | |
| 10539 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10540 predicate( UseSSE<=1 ); | |
| 10541 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 10542 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10543 "DMUL ST,$src1\n\t" | |
| 10544 "DADDp $src2,ST" %} | |
| 10545 ins_cost(250); | |
| 10546 opcode(0xDD); /* LoadD DD /0 */ | |
| 10547 ins_encode( Push_Reg_F(src0), | |
| 10548 FMul_ST_reg(src1), | |
| 10549 FAddP_reg_ST(src2) ); | |
| 10550 ins_pipe( fpu_reg_reg_reg ); | |
| 10551 %} | |
| 10552 | |
| 10553 | |
| 10554 // MACRO3 -- subD a mulD | |
| 10555 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10556 predicate( UseSSE<=1 ); | |
| 10557 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 10558 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10559 "DMUL ST,$src1\n\t" | |
| 10560 "DSUBRp $src2,ST" %} | |
| 10561 ins_cost(250); | |
| 10562 ins_encode( Push_Reg_F(src0), | |
| 10563 FMul_ST_reg(src1), | |
| 10564 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 10565 ins_pipe( fpu_reg_reg_reg ); | |
| 10566 %} | |
| 10567 | |
| 10568 | |
| 10569 instruct divD_reg(regD dst, regD src) %{ | |
| 10570 predicate( UseSSE<=1 ); | |
| 10571 match(Set dst (DivD dst src)); | |
| 10572 | |
| 10573 format %{ "FLD $src\n\t" | |
| 10574 "FDIVp $dst,ST" %} | |
| 10575 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10576 ins_cost(150); | |
| 10577 ins_encode( Push_Reg_D(src), | |
| 10578 OpcP, RegOpc(dst) ); | |
| 10579 ins_pipe( fpu_reg_reg ); | |
| 10580 %} | |
| 10581 | |
| 10582 // Strict FP instruction biases argument before division then | |
| 10583 // biases result, to avoid double rounding of subnormals. | |
| 10584 // | |
| 10585 // scale dividend by multiplying dividend by 2^(-15360) | |
| 10586 // load divisor | |
| 10587 // divide scaled dividend by divisor | |
| 10588 // rescale quotient by 2^(15360) | |
| 10589 // | |
| 10590 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10591 predicate (UseSSE<=1); | |
| 10592 match(Set dst (DivD dst src)); | |
| 10593 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10594 ins_cost(01); | |
| 10595 | |
| 10596 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10597 "DMULp $dst,ST\n\t" | |
| 10598 "FLD $src\n\t" | |
| 10599 "FDIVp $dst,ST\n\t" | |
| 10600 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10601 "DMULp $dst,ST\n\t" %} | |
| 10602 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10603 ins_encode( strictfp_bias1(dst), | |
| 10604 Push_Reg_D(src), | |
| 10605 OpcP, RegOpc(dst), | |
| 10606 strictfp_bias2(dst) ); | |
| 10607 ins_pipe( fpu_reg_reg ); | |
| 10608 %} | |
| 10609 | |
| 10610 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10611 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); | |
| 10612 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 10613 | |
| 10614 format %{ "FLD $src1\n\t" | |
| 10615 "FDIV ST,$src2\n\t" | |
| 10616 "FSTP_D $dst\t# D-round" %} | |
| 10617 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
| 10618 ins_encode( Push_Reg_D(src1), | |
| 10619 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); | |
| 10620 ins_pipe( fpu_mem_reg_reg ); | |
| 10621 %} | |
| 10622 | |
| 10623 | |
| 10624 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ | |
| 10625 predicate(UseSSE<=1); | |
| 10626 match(Set dst (ModD dst src)); | |
| 10627 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 10628 | |
| 10629 format %{ "DMOD $dst,$src" %} | |
| 10630 ins_cost(250); | |
| 10631 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 10632 emitModD(), | |
| 10633 Push_Result_Mod_D(src), | |
| 10634 Pop_Reg_D(dst)); | |
| 10635 ins_pipe( pipe_slow ); | |
| 10636 %} | |
| 10637 | |
| 10638 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 10639 predicate(UseSSE>=2); | |
| 10640 match(Set dst (ModD src0 src1)); | |
| 10641 effect(KILL rax, KILL cr); | |
| 10642 | |
| 10643 format %{ "SUB ESP,8\t # DMOD\n" | |
| 10644 "\tMOVSD [ESP+0],$src1\n" | |
| 10645 "\tFLD_D [ESP+0]\n" | |
| 10646 "\tMOVSD [ESP+0],$src0\n" | |
| 10647 "\tFLD_D [ESP+0]\n" | |
| 10648 "loop:\tFPREM\n" | |
| 10649 "\tFWAIT\n" | |
| 10650 "\tFNSTSW AX\n" | |
| 10651 "\tSAHF\n" | |
| 10652 "\tJP loop\n" | |
| 10653 "\tFSTP_D [ESP+0]\n" | |
| 10654 "\tMOVSD $dst,[ESP+0]\n" | |
| 10655 "\tADD ESP,8\n" | |
| 10656 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10657 %} | |
| 10658 ins_cost(250); | |
| 10659 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); | |
| 10660 ins_pipe( pipe_slow ); | |
| 10661 %} | |
| 10662 | |
| 10663 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10664 predicate (UseSSE<=1); | |
| 10665 match(Set dst (SinD src)); | |
| 10666 ins_cost(1800); | |
| 10667 format %{ "DSIN $dst" %} | |
| 10668 opcode(0xD9, 0xFE); | |
| 10669 ins_encode( OpcP, OpcS ); | |
| 10670 ins_pipe( pipe_slow ); | |
| 10671 %} | |
| 10672 | |
| 10673 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10674 predicate (UseSSE>=2); | |
| 10675 match(Set dst (SinD dst)); | |
| 10676 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10677 ins_cost(1800); | |
| 10678 format %{ "DSIN $dst" %} | |
| 10679 opcode(0xD9, 0xFE); | |
| 10680 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10681 ins_pipe( pipe_slow ); | |
| 10682 %} | |
| 10683 | |
| 10684 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10685 predicate (UseSSE<=1); | |
| 10686 match(Set dst (CosD src)); | |
| 10687 ins_cost(1800); | |
| 10688 format %{ "DCOS $dst" %} | |
| 10689 opcode(0xD9, 0xFF); | |
| 10690 ins_encode( OpcP, OpcS ); | |
| 10691 ins_pipe( pipe_slow ); | |
| 10692 %} | |
| 10693 | |
| 10694 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10695 predicate (UseSSE>=2); | |
| 10696 match(Set dst (CosD dst)); | |
| 10697 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10698 ins_cost(1800); | |
| 10699 format %{ "DCOS $dst" %} | |
| 10700 opcode(0xD9, 0xFF); | |
| 10701 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10702 ins_pipe( pipe_slow ); | |
| 10703 %} | |
| 10704 | |
| 10705 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10706 predicate (UseSSE<=1); | |
| 10707 match(Set dst(TanD src)); | |
| 10708 format %{ "DTAN $dst" %} | |
| 10709 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10710 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10711 ins_pipe( pipe_slow ); | |
| 10712 %} | |
| 10713 | |
| 10714 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10715 predicate (UseSSE>=2); | |
| 10716 match(Set dst(TanD dst)); | |
| 10717 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10718 format %{ "DTAN $dst" %} | |
| 10719 ins_encode( Push_SrcXD(dst), | |
| 10720 Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10721 Opcode(0xDD), Opcode(0xD8), // fstp st | |
| 10722 Push_ResultXD(dst) ); | |
| 10723 ins_pipe( pipe_slow ); | |
| 10724 %} | |
| 10725 | |
| 10726 instruct atanD_reg(regD dst, regD src) %{ | |
| 10727 predicate (UseSSE<=1); | |
| 10728 match(Set dst(AtanD dst src)); | |
| 10729 format %{ "DATA $dst,$src" %} | |
| 10730 opcode(0xD9, 0xF3); | |
| 10731 ins_encode( Push_Reg_D(src), | |
| 10732 OpcP, OpcS, RegOpc(dst) ); | |
| 10733 ins_pipe( pipe_slow ); | |
| 10734 %} | |
| 10735 | |
| 10736 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10737 predicate (UseSSE>=2); | |
| 10738 match(Set dst(AtanD dst src)); | |
| 10739 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10740 format %{ "DATA $dst,$src" %} | |
| 10741 opcode(0xD9, 0xF3); | |
| 10742 ins_encode( Push_SrcXD(src), | |
| 10743 OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10744 ins_pipe( pipe_slow ); | |
| 10745 %} | |
| 10746 | |
| 10747 instruct sqrtD_reg(regD dst, regD src) %{ | |
| 10748 predicate (UseSSE<=1); | |
| 10749 match(Set dst (SqrtD src)); | |
| 10750 format %{ "DSQRT $dst,$src" %} | |
| 10751 opcode(0xFA, 0xD9); | |
| 10752 ins_encode( Push_Reg_D(src), | |
| 10753 OpcS, OpcP, Pop_Reg_D(dst) ); | |
| 10754 ins_pipe( pipe_slow ); | |
| 10755 %} | |
| 10756 | |
| 10757 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10758 predicate (UseSSE<=1); | |
| 10759 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
| 10760 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10761 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10762 "FLD_D $X\n\t" | |
| 10763 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10764 | |
| 10765 "FDUP \t\t\t# Q Q\n\t" | |
| 10766 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10767 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10768 "FISTP dword [ESP]\n\t" | |
| 10769 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10770 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10771 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10772 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10773 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10774 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10775 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10776 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10777 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10778 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10779 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10780 "MOV [ESP+0],0\n\t" | |
| 10781 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10782 | |
| 10783 "ADD ESP,8" | |
| 10784 %} | |
| 10785 ins_encode( push_stack_temp_qword, | |
| 10786 Push_Reg_D(X), | |
| 10787 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10788 pow_exp_core_encoding, | |
| 10789 pop_stack_temp_qword); | |
| 10790 ins_pipe( pipe_slow ); | |
| 10791 %} | |
| 10792 | |
| 10793 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ | |
| 10794 predicate (UseSSE>=2); | |
| 10795 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
| 10796 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); | |
| 10797 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10798 "MOVSD [ESP],$src1\n\t" | |
| 10799 "FLD FPR1,$src1\n\t" | |
| 10800 "MOVSD [ESP],$src0\n\t" | |
| 10801 "FLD FPR1,$src0\n\t" | |
| 10802 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10803 | |
| 10804 "FDUP \t\t\t# Q Q\n\t" | |
| 10805 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10806 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10807 "FISTP dword [ESP]\n\t" | |
| 10808 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10809 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10810 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10811 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10812 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10813 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10814 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10815 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10816 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10817 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10818 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10819 "MOV [ESP+0],0\n\t" | |
| 10820 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10821 | |
| 10822 "FST_D [ESP]\n\t" | |
| 10823 "MOVSD $dst,[ESP]\n\t" | |
| 10824 "ADD ESP,8" | |
| 10825 %} | |
| 10826 ins_encode( push_stack_temp_qword, | |
| 10827 push_xmm_to_fpr1(src1), | |
| 10828 push_xmm_to_fpr1(src0), | |
| 10829 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10830 pow_exp_core_encoding, | |
| 10831 Push_ResultXD(dst) ); | |
| 10832 ins_pipe( pipe_slow ); | |
| 10833 %} | |
| 10834 | |
| 10835 | |
| 10836 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10837 predicate (UseSSE<=1); | |
| 10838 match(Set dpr1 (ExpD dpr1)); | |
| 10839 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10840 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" | |
| 10841 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10842 "FMULP \t\t\t# Q=X*log2(e)\n\t" | |
| 10843 | |
| 10844 "FDUP \t\t\t# Q Q\n\t" | |
| 10845 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10846 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10847 "FISTP dword [ESP]\n\t" | |
| 10848 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10849 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10850 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10851 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10852 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10853 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10854 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10855 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10856 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10857 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10858 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10859 "MOV [ESP+0],0\n\t" | |
| 10860 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10861 | |
| 10862 "ADD ESP,8" | |
| 10863 %} | |
| 10864 ins_encode( push_stack_temp_qword, | |
| 10865 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10866 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10867 pow_exp_core_encoding, | |
| 10868 pop_stack_temp_qword); | |
| 10869 ins_pipe( pipe_slow ); | |
| 10870 %} | |
| 10871 | |
| 10872 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10873 predicate (UseSSE>=2); | |
| 10874 match(Set dst (ExpD src)); | |
| 10875 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); | |
| 10876 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" | |
| 10877 "MOVSD [ESP],$src\n\t" | |
| 10878 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10879 "FMULP \t\t\t# Q=X*log2(e) X\n\t" | |
| 10880 | |
| 10881 "FDUP \t\t\t# Q Q\n\t" | |
| 10882 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10883 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10884 "FISTP dword [ESP]\n\t" | |
| 10885 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10886 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10887 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10888 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10889 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10890 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10891 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10892 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10893 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10894 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10895 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10896 "MOV [ESP+0],0\n\t" | |
| 10897 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10898 | |
| 10899 "FST_D [ESP]\n\t" | |
| 10900 "MOVSD $dst,[ESP]\n\t" | |
| 10901 "ADD ESP,8" | |
| 10902 %} | |
| 10903 ins_encode( Push_SrcXD(src), | |
| 10904 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10905 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10906 pow_exp_core_encoding, | |
| 10907 Push_ResultXD(dst) ); | |
| 10908 ins_pipe( pipe_slow ); | |
| 10909 %} | |
| 10910 | |
| 10911 | |
| 10912 | |
| 10913 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10914 predicate (UseSSE<=1); | |
| 10915 // The source Double operand on FPU stack | |
| 10916 match(Set dst (Log10D src)); | |
| 10917 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10918 // fxch ; swap ST(0) with ST(1) | |
| 10919 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10920 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10921 "FXCH \n\t" | |
| 10922 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10923 %} | |
| 10924 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10925 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10926 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10927 | |
| 10928 ins_pipe( pipe_slow ); | |
| 10929 %} | |
| 10930 | |
| 10931 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10932 predicate (UseSSE>=2); | |
| 10933 effect(KILL cr); | |
| 10934 match(Set dst (Log10D src)); | |
| 10935 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10936 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10937 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10938 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10939 %} | |
| 10940 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10941 Push_SrcXD(src), | |
| 10942 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10943 Push_ResultXD(dst)); | |
| 10944 | |
| 10945 ins_pipe( pipe_slow ); | |
| 10946 %} | |
| 10947 | |
| 10948 instruct logD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10949 predicate (UseSSE<=1); | |
| 10950 // The source Double operand on FPU stack | |
| 10951 match(Set dst (LogD src)); | |
| 10952 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10953 // fxch ; swap ST(0) with ST(1) | |
| 10954 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10955 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10956 "FXCH \n\t" | |
| 10957 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10958 %} | |
| 10959 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10960 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10961 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10962 | |
| 10963 ins_pipe( pipe_slow ); | |
| 10964 %} | |
| 10965 | |
| 10966 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10967 predicate (UseSSE>=2); | |
| 10968 effect(KILL cr); | |
| 10969 // The source and result Double operands in XMM registers | |
| 10970 match(Set dst (LogD src)); | |
| 10971 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10972 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10973 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10974 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10975 %} | |
| 10976 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10977 Push_SrcXD(src), | |
| 10978 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10979 Push_ResultXD(dst)); | |
| 10980 ins_pipe( pipe_slow ); | |
| 10981 %} | |
| 10982 | |
| 10983 //-------------Float Instructions------------------------------- | |
| 10984 // Float Math | |
| 10985 | |
| 10986 // Code for float compare: | |
| 10987 // fcompp(); | |
| 10988 // fwait(); fnstsw_ax(); | |
| 10989 // sahf(); | |
| 10990 // movl(dst, unordered_result); | |
| 10991 // jcc(Assembler::parity, exit); | |
| 10992 // movl(dst, less_result); | |
| 10993 // jcc(Assembler::below, exit); | |
| 10994 // movl(dst, equal_result); | |
| 10995 // jcc(Assembler::equal, exit); | |
| 10996 // movl(dst, greater_result); | |
| 10997 // exit: | |
| 10998 | |
| 10999 // P6 version of float compare, sets condition codes in EFLAGS | |
| 11000 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 11001 predicate(VM_Version::supports_cmov() && UseSSE == 0); | |
| 11002 match(Set cr (CmpF src1 src2)); | |
| 11003 effect(KILL rax); | |
| 11004 ins_cost(150); | |
| 11005 format %{ "FLD $src1\n\t" | |
| 11006 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 11007 "JNP exit\n\t" | |
| 11008 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 11009 "SAHF\n" | |
| 11010 "exit:\tNOP // avoid branch to branch" %} | |
| 11011 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 11012 ins_encode( Push_Reg_D(src1), | |
| 11013 OpcP, RegOpc(src2), | |
| 11014 cmpF_P6_fixup ); | |
| 11015 ins_pipe( pipe_slow ); | |
| 11016 %} | |
| 11017 | |
|
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11018 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
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11019 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
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11020 match(Set cr (CmpF src1 src2)); |
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11021 ins_cost(100); |
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11022 format %{ "FLD $src1\n\t" |
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11023 "FUCOMIP ST,$src2 // P6 instruction" %} |
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11024 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
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11025 ins_encode( Push_Reg_D(src1), |
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11026 OpcP, RegOpc(src2)); |
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11027 ins_pipe( pipe_slow ); |
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11028 %} |
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11029 |
| 0 | 11030 |
| 11031 // Compare & branch | |
| 11032 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 11033 predicate(UseSSE == 0); | |
| 11034 match(Set cr (CmpF src1 src2)); | |
| 11035 effect(KILL rax); | |
| 11036 ins_cost(200); | |
| 11037 format %{ "FLD $src1\n\t" | |
| 11038 "FCOMp $src2\n\t" | |
| 11039 "FNSTSW AX\n\t" | |
| 11040 "TEST AX,0x400\n\t" | |
| 11041 "JZ,s flags\n\t" | |
| 11042 "MOV AH,1\t# unordered treat as LT\n" | |
| 11043 "flags:\tSAHF" %} | |
| 11044 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 11045 ins_encode( Push_Reg_D(src1), | |
| 11046 OpcP, RegOpc(src2), | |
| 11047 fpu_flags); | |
| 11048 ins_pipe( pipe_slow ); | |
| 11049 %} | |
| 11050 | |
| 11051 // Compare vs zero into -1,0,1 | |
| 11052 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 11053 predicate(UseSSE == 0); | |
| 11054 match(Set dst (CmpF3 src1 zero)); | |
| 11055 effect(KILL cr, KILL rax); | |
| 11056 ins_cost(280); | |
| 11057 format %{ "FTSTF $dst,$src1" %} | |
| 11058 opcode(0xE4, 0xD9); | |
| 11059 ins_encode( Push_Reg_D(src1), | |
| 11060 OpcS, OpcP, PopFPU, | |
| 11061 CmpF_Result(dst)); | |
| 11062 ins_pipe( pipe_slow ); | |
| 11063 %} | |
| 11064 | |
| 11065 // Compare into -1,0,1 | |
| 11066 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11067 predicate(UseSSE == 0); | |
| 11068 match(Set dst (CmpF3 src1 src2)); | |
| 11069 effect(KILL cr, KILL rax); | |
| 11070 ins_cost(300); | |
| 11071 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 11072 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 11073 ins_encode( Push_Reg_D(src1), | |
| 11074 OpcP, RegOpc(src2), | |
| 11075 CmpF_Result(dst)); | |
| 11076 ins_pipe( pipe_slow ); | |
| 11077 %} | |
| 11078 | |
| 11079 // float compare and set condition codes in EFLAGS by XMM regs | |
| 11080 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ | |
| 11081 predicate(UseSSE>=1); | |
| 11082 match(Set cr (CmpF dst src)); | |
| 11083 effect(KILL rax); | |
| 11084 ins_cost(145); | |
| 11085 format %{ "COMISS $dst,$src\n" | |
| 11086 "\tJNP exit\n" | |
| 11087 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 11088 "\tSAHF\n" | |
| 11089 "exit:\tNOP // avoid branch to branch" %} | |
| 11090 opcode(0x0F, 0x2F); | |
| 11091 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); | |
| 11092 ins_pipe( pipe_slow ); | |
| 11093 %} | |
| 11094 | |
|
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11095 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{ |
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11096 predicate(UseSSE>=1); |
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11097 match(Set cr (CmpF dst src)); |
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11098 ins_cost(100); |
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11099 format %{ "COMISS $dst,$src" %} |
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11100 opcode(0x0F, 0x2F); |
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11101 ins_encode(OpcP, OpcS, RegReg(dst, src)); |
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11102 ins_pipe( pipe_slow ); |
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11103 %} |
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11104 |
| 0 | 11105 // float compare and set condition codes in EFLAGS by XMM regs |
| 11106 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ | |
| 11107 predicate(UseSSE>=1); | |
| 11108 match(Set cr (CmpF dst (LoadF src))); | |
| 11109 effect(KILL rax); | |
| 11110 ins_cost(165); | |
| 11111 format %{ "COMISS $dst,$src\n" | |
| 11112 "\tJNP exit\n" | |
| 11113 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 11114 "\tSAHF\n" | |
| 11115 "exit:\tNOP // avoid branch to branch" %} | |
| 11116 opcode(0x0F, 0x2F); | |
| 11117 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); | |
| 11118 ins_pipe( pipe_slow ); | |
| 11119 %} | |
| 11120 | |
|
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11121 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{ |
|
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11122 predicate(UseSSE>=1); |
|
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11123 match(Set cr (CmpF dst (LoadF src))); |
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11124 ins_cost(100); |
|
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11125 format %{ "COMISS $dst,$src" %} |
|
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11126 opcode(0x0F, 0x2F); |
|
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11127 ins_encode(OpcP, OpcS, RegMem(dst, src)); |
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11128 ins_pipe( pipe_slow ); |
|
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|
11129 %} |
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|
11130 |
| 0 | 11131 // Compare into -1,0,1 in XMM |
| 11132 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ | |
| 11133 predicate(UseSSE>=1); | |
| 11134 match(Set dst (CmpF3 src1 src2)); | |
| 11135 effect(KILL cr); | |
| 11136 ins_cost(255); | |
| 11137 format %{ "XOR $dst,$dst\n" | |
| 11138 "\tCOMISS $src1,$src2\n" | |
| 11139 "\tJP,s nan\n" | |
| 11140 "\tJEQ,s exit\n" | |
| 11141 "\tJA,s inc\n" | |
| 11142 "nan:\tDEC $dst\n" | |
| 11143 "\tJMP,s exit\n" | |
| 11144 "inc:\tINC $dst\n" | |
| 11145 "exit:" | |
| 11146 %} | |
| 11147 opcode(0x0F, 0x2F); | |
| 11148 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); | |
| 11149 ins_pipe( pipe_slow ); | |
| 11150 %} | |
| 11151 | |
| 11152 // Compare into -1,0,1 in XMM and memory | |
| 11153 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ | |
| 11154 predicate(UseSSE>=1); | |
| 11155 match(Set dst (CmpF3 src1 (LoadF mem))); | |
| 11156 effect(KILL cr); | |
| 11157 ins_cost(275); | |
| 11158 format %{ "COMISS $src1,$mem\n" | |
| 11159 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 11160 "\tJP,s nan\n" | |
| 11161 "\tJEQ,s exit\n" | |
| 11162 "\tJA,s inc\n" | |
| 11163 "nan:\tDEC $dst\n" | |
| 11164 "\tJMP,s exit\n" | |
| 11165 "inc:\tINC $dst\n" | |
| 11166 "exit:" | |
| 11167 %} | |
| 11168 opcode(0x0F, 0x2F); | |
| 11169 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 11170 ins_pipe( pipe_slow ); | |
| 11171 %} | |
| 11172 | |
| 11173 // Spill to obtain 24-bit precision | |
| 11174 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11175 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11176 match(Set dst (SubF src1 src2)); | |
| 11177 | |
| 11178 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 11179 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
| 11180 ins_encode( Push_Reg_F(src1), | |
| 11181 OpcReg_F(src2), | |
| 11182 Pop_Mem_F(dst) ); | |
| 11183 ins_pipe( fpu_mem_reg_reg ); | |
| 11184 %} | |
| 11185 // | |
| 11186 // This instruction does not round to 24-bits | |
| 11187 instruct subF_reg(regF dst, regF src) %{ | |
| 11188 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11189 match(Set dst (SubF dst src)); | |
| 11190 | |
| 11191 format %{ "FSUB $dst,$src" %} | |
| 11192 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 11193 ins_encode( Push_Reg_F(src), | |
| 11194 OpcP, RegOpc(dst) ); | |
| 11195 ins_pipe( fpu_reg_reg ); | |
| 11196 %} | |
| 11197 | |
| 11198 // Spill to obtain 24-bit precision | |
| 11199 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11200 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11201 match(Set dst (AddF src1 src2)); | |
| 11202 | |
| 11203 format %{ "FADD $dst,$src1,$src2" %} | |
| 11204 opcode(0xD8, 0x0); /* D8 C0+i */ | |
| 11205 ins_encode( Push_Reg_F(src2), | |
| 11206 OpcReg_F(src1), | |
| 11207 Pop_Mem_F(dst) ); | |
| 11208 ins_pipe( fpu_mem_reg_reg ); | |
| 11209 %} | |
| 11210 // | |
| 11211 // This instruction does not round to 24-bits | |
| 11212 instruct addF_reg(regF dst, regF src) %{ | |
| 11213 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11214 match(Set dst (AddF dst src)); | |
| 11215 | |
| 11216 format %{ "FLD $src\n\t" | |
| 11217 "FADDp $dst,ST" %} | |
| 11218 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 11219 ins_encode( Push_Reg_F(src), | |
| 11220 OpcP, RegOpc(dst) ); | |
| 11221 ins_pipe( fpu_reg_reg ); | |
| 11222 %} | |
| 11223 | |
| 11224 // Add two single precision floating point values in xmm | |
| 11225 instruct addX_reg(regX dst, regX src) %{ | |
| 11226 predicate(UseSSE>=1); | |
| 11227 match(Set dst (AddF dst src)); | |
| 11228 format %{ "ADDSS $dst,$src" %} | |
| 11229 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 11230 ins_pipe( pipe_slow ); | |
| 11231 %} | |
| 11232 | |
| 11233 instruct addX_imm(regX dst, immXF con) %{ | |
| 11234 predicate(UseSSE>=1); | |
| 11235 match(Set dst (AddF dst con)); | |
| 2008 | 11236 format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11237 ins_encode %{ | |
| 11238 __ addss($dst$$XMMRegister, $constantaddress($con)); | |
| 11239 %} | |
| 11240 ins_pipe(pipe_slow); | |
| 0 | 11241 %} |
| 11242 | |
| 11243 instruct addX_mem(regX dst, memory mem) %{ | |
| 11244 predicate(UseSSE>=1); | |
| 11245 match(Set dst (AddF dst (LoadF mem))); | |
| 11246 format %{ "ADDSS $dst,$mem" %} | |
| 11247 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); | |
| 11248 ins_pipe( pipe_slow ); | |
| 11249 %} | |
| 11250 | |
| 11251 // Subtract two single precision floating point values in xmm | |
| 11252 instruct subX_reg(regX dst, regX src) %{ | |
| 11253 predicate(UseSSE>=1); | |
| 11254 match(Set dst (SubF dst src)); | |
| 11255 format %{ "SUBSS $dst,$src" %} | |
| 11256 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 11257 ins_pipe( pipe_slow ); | |
| 11258 %} | |
| 11259 | |
| 11260 instruct subX_imm(regX dst, immXF con) %{ | |
| 11261 predicate(UseSSE>=1); | |
| 11262 match(Set dst (SubF dst con)); | |
| 2008 | 11263 format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11264 ins_encode %{ | |
| 11265 __ subss($dst$$XMMRegister, $constantaddress($con)); | |
| 11266 %} | |
| 11267 ins_pipe(pipe_slow); | |
| 0 | 11268 %} |
| 11269 | |
| 11270 instruct subX_mem(regX dst, memory mem) %{ | |
| 11271 predicate(UseSSE>=1); | |
| 11272 match(Set dst (SubF dst (LoadF mem))); | |
| 11273 format %{ "SUBSS $dst,$mem" %} | |
| 11274 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 11275 ins_pipe( pipe_slow ); | |
| 11276 %} | |
| 11277 | |
| 11278 // Multiply two single precision floating point values in xmm | |
| 11279 instruct mulX_reg(regX dst, regX src) %{ | |
| 11280 predicate(UseSSE>=1); | |
| 11281 match(Set dst (MulF dst src)); | |
| 11282 format %{ "MULSS $dst,$src" %} | |
| 11283 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 11284 ins_pipe( pipe_slow ); | |
| 11285 %} | |
| 11286 | |
| 11287 instruct mulX_imm(regX dst, immXF con) %{ | |
| 11288 predicate(UseSSE>=1); | |
| 11289 match(Set dst (MulF dst con)); | |
| 2008 | 11290 format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11291 ins_encode %{ | |
| 11292 __ mulss($dst$$XMMRegister, $constantaddress($con)); | |
| 11293 %} | |
| 11294 ins_pipe(pipe_slow); | |
| 0 | 11295 %} |
| 11296 | |
| 11297 instruct mulX_mem(regX dst, memory mem) %{ | |
| 11298 predicate(UseSSE>=1); | |
| 11299 match(Set dst (MulF dst (LoadF mem))); | |
| 11300 format %{ "MULSS $dst,$mem" %} | |
| 11301 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 11302 ins_pipe( pipe_slow ); | |
| 11303 %} | |
| 11304 | |
| 11305 // Divide two single precision floating point values in xmm | |
| 11306 instruct divX_reg(regX dst, regX src) %{ | |
| 11307 predicate(UseSSE>=1); | |
| 11308 match(Set dst (DivF dst src)); | |
| 11309 format %{ "DIVSS $dst,$src" %} | |
| 11310 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 11311 ins_pipe( pipe_slow ); | |
| 11312 %} | |
| 11313 | |
| 11314 instruct divX_imm(regX dst, immXF con) %{ | |
| 11315 predicate(UseSSE>=1); | |
| 11316 match(Set dst (DivF dst con)); | |
| 2008 | 11317 format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11318 ins_encode %{ | |
| 11319 __ divss($dst$$XMMRegister, $constantaddress($con)); | |
| 11320 %} | |
| 11321 ins_pipe(pipe_slow); | |
| 0 | 11322 %} |
| 11323 | |
| 11324 instruct divX_mem(regX dst, memory mem) %{ | |
| 11325 predicate(UseSSE>=1); | |
| 11326 match(Set dst (DivF dst (LoadF mem))); | |
| 11327 format %{ "DIVSS $dst,$mem" %} | |
| 11328 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 11329 ins_pipe( pipe_slow ); | |
| 11330 %} | |
| 11331 | |
| 11332 // Get the square root of a single precision floating point values in xmm | |
| 11333 instruct sqrtX_reg(regX dst, regX src) %{ | |
| 11334 predicate(UseSSE>=1); | |
| 11335 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 11336 format %{ "SQRTSS $dst,$src" %} | |
| 11337 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11338 ins_pipe( pipe_slow ); | |
| 11339 %} | |
| 11340 | |
| 11341 instruct sqrtX_mem(regX dst, memory mem) %{ | |
| 11342 predicate(UseSSE>=1); | |
| 11343 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); | |
| 11344 format %{ "SQRTSS $dst,$mem" %} | |
| 11345 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11346 ins_pipe( pipe_slow ); | |
| 11347 %} | |
| 11348 | |
| 11349 // Get the square root of a double precision floating point values in xmm | |
| 11350 instruct sqrtXD_reg(regXD dst, regXD src) %{ | |
| 11351 predicate(UseSSE>=2); | |
| 11352 match(Set dst (SqrtD src)); | |
| 11353 format %{ "SQRTSD $dst,$src" %} | |
| 11354 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11355 ins_pipe( pipe_slow ); | |
| 11356 %} | |
| 11357 | |
| 11358 instruct sqrtXD_mem(regXD dst, memory mem) %{ | |
| 11359 predicate(UseSSE>=2); | |
| 11360 match(Set dst (SqrtD (LoadD mem))); | |
| 11361 format %{ "SQRTSD $dst,$mem" %} | |
| 11362 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11363 ins_pipe( pipe_slow ); | |
| 11364 %} | |
| 11365 | |
| 11366 instruct absF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11367 predicate(UseSSE==0); | |
| 11368 match(Set dst (AbsF src)); | |
| 11369 ins_cost(100); | |
| 11370 format %{ "FABS" %} | |
| 11371 opcode(0xE1, 0xD9); | |
| 11372 ins_encode( OpcS, OpcP ); | |
| 11373 ins_pipe( fpu_reg_reg ); | |
| 11374 %} | |
| 11375 | |
| 11376 instruct absX_reg(regX dst ) %{ | |
| 11377 predicate(UseSSE>=1); | |
| 11378 match(Set dst (AbsF dst)); | |
| 11379 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} | |
| 11380 ins_encode( AbsXF_encoding(dst)); | |
| 11381 ins_pipe( pipe_slow ); | |
| 11382 %} | |
| 11383 | |
| 11384 instruct negF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11385 predicate(UseSSE==0); | |
| 11386 match(Set dst (NegF src)); | |
| 11387 ins_cost(100); | |
| 11388 format %{ "FCHS" %} | |
| 11389 opcode(0xE0, 0xD9); | |
| 11390 ins_encode( OpcS, OpcP ); | |
| 11391 ins_pipe( fpu_reg_reg ); | |
| 11392 %} | |
| 11393 | |
| 11394 instruct negX_reg( regX dst ) %{ | |
| 11395 predicate(UseSSE>=1); | |
| 11396 match(Set dst (NegF dst)); | |
| 11397 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} | |
| 11398 ins_encode( NegXF_encoding(dst)); | |
| 11399 ins_pipe( pipe_slow ); | |
| 11400 %} | |
| 11401 | |
| 11402 // Cisc-alternate to addF_reg | |
| 11403 // Spill to obtain 24-bit precision | |
| 11404 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11405 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11406 match(Set dst (AddF src1 (LoadF src2))); | |
| 11407 | |
| 11408 format %{ "FLD $src2\n\t" | |
| 11409 "FADD ST,$src1\n\t" | |
| 11410 "FSTP_S $dst" %} | |
| 11411 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11412 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11413 OpcReg_F(src1), | |
| 11414 Pop_Mem_F(dst) ); | |
| 11415 ins_pipe( fpu_mem_reg_mem ); | |
| 11416 %} | |
| 11417 // | |
| 11418 // Cisc-alternate to addF_reg | |
| 11419 // This instruction does not round to 24-bits | |
| 11420 instruct addF_reg_mem(regF dst, memory src) %{ | |
| 11421 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11422 match(Set dst (AddF dst (LoadF src))); | |
| 11423 | |
| 11424 format %{ "FADD $dst,$src" %} | |
| 11425 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 11426 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 11427 OpcP, RegOpc(dst) ); | |
| 11428 ins_pipe( fpu_reg_mem ); | |
| 11429 %} | |
| 11430 | |
| 11431 // // Following two instructions for _222_mpegaudio | |
| 11432 // Spill to obtain 24-bit precision | |
| 11433 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ | |
| 11434 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11435 match(Set dst (AddF src1 src2)); | |
| 11436 | |
| 11437 format %{ "FADD $dst,$src1,$src2" %} | |
| 11438 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11439 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
| 11440 OpcReg_F(src2), | |
| 11441 Pop_Mem_F(dst) ); | |
| 11442 ins_pipe( fpu_mem_reg_mem ); | |
| 11443 %} | |
| 11444 | |
| 11445 // Cisc-spill variant | |
| 11446 // Spill to obtain 24-bit precision | |
| 11447 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ | |
| 11448 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11449 match(Set dst (AddF src1 (LoadF src2))); | |
| 11450 | |
| 11451 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 11452 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11453 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11454 set_instruction_start, | |
| 11455 OpcP, RMopc_Mem(secondary,src1), | |
| 11456 Pop_Mem_F(dst) ); | |
| 11457 ins_pipe( fpu_mem_mem_mem ); | |
| 11458 %} | |
| 11459 | |
| 11460 // Spill to obtain 24-bit precision | |
| 11461 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11462 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11463 match(Set dst (AddF src1 src2)); | |
| 11464 | |
| 11465 format %{ "FADD $dst,$src1,$src2" %} | |
| 11466 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 11467 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11468 set_instruction_start, | |
| 11469 OpcP, RMopc_Mem(secondary,src1), | |
| 11470 Pop_Mem_F(dst) ); | |
| 11471 ins_pipe( fpu_mem_mem_mem ); | |
| 11472 %} | |
| 11473 | |
| 11474 | |
| 11475 // Spill to obtain 24-bit precision | |
| 2008 | 11476 instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{ |
| 0 | 11477 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 11478 match(Set dst (AddF src con)); |
| 11479 format %{ "FLD $src\n\t" | |
| 11480 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 11481 "FSTP_S $dst" %} |
| 2008 | 11482 ins_encode %{ |
| 11483 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11484 __ fadd_s($constantaddress($con)); | |
| 11485 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 11486 %} | |
| 11487 ins_pipe(fpu_mem_reg_con); | |
| 0 | 11488 %} |
| 11489 // | |
| 11490 // This instruction does not round to 24-bits | |
| 2008 | 11491 instruct addF_reg_imm(regF dst, regF src, immF con) %{ |
| 0 | 11492 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 11493 match(Set dst (AddF src con)); |
| 11494 format %{ "FLD $src\n\t" | |
| 11495 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11496 "FSTP $dst" %} | |
| 11497 ins_encode %{ | |
| 11498 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11499 __ fadd_s($constantaddress($con)); | |
| 11500 __ fstp_d($dst$$reg); | |
| 11501 %} | |
| 11502 ins_pipe(fpu_reg_reg_con); | |
| 0 | 11503 %} |
| 11504 | |
| 11505 // Spill to obtain 24-bit precision | |
| 11506 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11507 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11508 match(Set dst (MulF src1 src2)); | |
| 11509 | |
| 11510 format %{ "FLD $src1\n\t" | |
| 11511 "FMUL $src2\n\t" | |
| 11512 "FSTP_S $dst" %} | |
| 11513 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
| 11514 ins_encode( Push_Reg_F(src1), | |
| 11515 OpcReg_F(src2), | |
| 11516 Pop_Mem_F(dst) ); | |
| 11517 ins_pipe( fpu_mem_reg_reg ); | |
| 11518 %} | |
| 11519 // | |
| 11520 // This instruction does not round to 24-bits | |
| 11521 instruct mulF_reg(regF dst, regF src1, regF src2) %{ | |
| 11522 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11523 match(Set dst (MulF src1 src2)); | |
| 11524 | |
| 11525 format %{ "FLD $src1\n\t" | |
| 11526 "FMUL $src2\n\t" | |
| 11527 "FSTP_S $dst" %} | |
| 11528 opcode(0xD8, 0x1); /* D8 C8+i */ | |
| 11529 ins_encode( Push_Reg_F(src2), | |
| 11530 OpcReg_F(src1), | |
| 11531 Pop_Reg_F(dst) ); | |
| 11532 ins_pipe( fpu_reg_reg_reg ); | |
| 11533 %} | |
| 11534 | |
| 11535 | |
| 11536 // Spill to obtain 24-bit precision | |
| 11537 // Cisc-alternate to reg-reg multiply | |
| 11538 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11539 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11540 match(Set dst (MulF src1 (LoadF src2))); | |
| 11541 | |
| 11542 format %{ "FLD_S $src2\n\t" | |
| 11543 "FMUL $src1\n\t" | |
| 11544 "FSTP_S $dst" %} | |
| 11545 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 11546 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11547 OpcReg_F(src1), | |
| 11548 Pop_Mem_F(dst) ); | |
| 11549 ins_pipe( fpu_mem_reg_mem ); | |
| 11550 %} | |
| 11551 // | |
| 11552 // This instruction does not round to 24-bits | |
| 11553 // Cisc-alternate to reg-reg multiply | |
| 11554 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ | |
| 11555 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11556 match(Set dst (MulF src1 (LoadF src2))); | |
| 11557 | |
| 11558 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11559 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 11560 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11561 OpcReg_F(src1), | |
| 11562 Pop_Reg_F(dst) ); | |
| 11563 ins_pipe( fpu_reg_reg_mem ); | |
| 11564 %} | |
| 11565 | |
| 11566 // Spill to obtain 24-bit precision | |
| 11567 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11568 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11569 match(Set dst (MulF src1 src2)); | |
| 11570 | |
| 11571 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11572 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 11573 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11574 set_instruction_start, | |
| 11575 OpcP, RMopc_Mem(secondary,src1), | |
| 11576 Pop_Mem_F(dst) ); | |
| 11577 ins_pipe( fpu_mem_mem_mem ); | |
| 11578 %} | |
| 11579 | |
| 11580 // Spill to obtain 24-bit precision | |
| 2008 | 11581 instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{ |
| 0 | 11582 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 11583 match(Set dst (MulF src con)); |
| 11584 | |
| 11585 format %{ "FLD $src\n\t" | |
| 11586 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11587 "FSTP_S $dst" %} | |
| 11588 ins_encode %{ | |
| 11589 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11590 __ fmul_s($constantaddress($con)); | |
| 11591 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 11592 %} | |
| 11593 ins_pipe(fpu_mem_reg_con); | |
| 0 | 11594 %} |
| 11595 // | |
| 11596 // This instruction does not round to 24-bits | |
| 2008 | 11597 instruct mulF_reg_imm(regF dst, regF src, immF con) %{ |
| 0 | 11598 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 11599 match(Set dst (MulF src con)); |
| 11600 | |
| 11601 format %{ "FLD $src\n\t" | |
| 11602 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11603 "FSTP $dst" %} | |
| 11604 ins_encode %{ | |
| 11605 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11606 __ fmul_s($constantaddress($con)); | |
| 11607 __ fstp_d($dst$$reg); | |
| 11608 %} | |
| 11609 ins_pipe(fpu_reg_reg_con); | |
| 0 | 11610 %} |
| 11611 | |
| 11612 | |
| 11613 // | |
| 11614 // MACRO1 -- subsume unshared load into mulF | |
| 11615 // This instruction does not round to 24-bits | |
| 11616 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ | |
| 11617 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11618 match(Set dst (MulF (LoadF mem1) src)); | |
| 11619 | |
| 11620 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 11621 "FMUL ST,$src\n\t" | |
| 11622 "FSTP $dst" %} | |
| 11623 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 11624 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
| 11625 OpcReg_F(src), | |
| 11626 Pop_Reg_F(dst) ); | |
| 11627 ins_pipe( fpu_reg_reg_mem ); | |
| 11628 %} | |
| 11629 // | |
| 11630 // MACRO2 -- addF a mulF which subsumed an unshared load | |
| 11631 // This instruction does not round to 24-bits | |
| 11632 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ | |
| 11633 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11634 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 11635 ins_cost(95); | |
| 11636 | |
| 11637 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
| 11638 "FMUL ST,$src1 subsume mulF left load\n\t" | |
| 11639 "FADD ST,$src2\n\t" | |
| 11640 "FSTP $dst" %} | |
| 11641 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11642 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 11643 FMul_ST_reg(src1), | |
| 11644 FAdd_ST_reg(src2), | |
| 11645 Pop_Reg_F(dst) ); | |
| 11646 ins_pipe( fpu_reg_mem_reg_reg ); | |
| 11647 %} | |
| 11648 | |
| 11649 // MACRO3 -- addF a mulF | |
| 11650 // This instruction does not round to 24-bits. It is a '2-address' | |
| 11651 // instruction in that the result goes back to src2. This eliminates | |
| 11652 // a move from the macro; possibly the register allocator will have | |
| 11653 // to add it back (and maybe not). | |
| 11654 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ | |
| 11655 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11656 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 11657 | |
| 11658 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 11659 "FMUL ST,$src1\n\t" | |
| 11660 "FADDP $src2,ST" %} | |
| 11661 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11662 ins_encode( Push_Reg_F(src0), | |
| 11663 FMul_ST_reg(src1), | |
| 11664 FAddP_reg_ST(src2) ); | |
| 11665 ins_pipe( fpu_reg_reg_reg ); | |
| 11666 %} | |
| 11667 | |
| 11668 // MACRO4 -- divF subF | |
| 11669 // This instruction does not round to 24-bits | |
| 11670 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ | |
| 11671 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11672 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 11673 | |
| 11674 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 11675 "FSUB ST,$src1\n\t" | |
| 11676 "FDIV ST,$src3\n\t" | |
| 11677 "FSTP $dst" %} | |
| 11678 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11679 ins_encode( Push_Reg_F(src2), | |
| 11680 subF_divF_encode(src1,src3), | |
| 11681 Pop_Reg_F(dst) ); | |
| 11682 ins_pipe( fpu_reg_reg_reg_reg ); | |
| 11683 %} | |
| 11684 | |
| 11685 // Spill to obtain 24-bit precision | |
| 11686 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11687 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11688 match(Set dst (DivF src1 src2)); | |
| 11689 | |
| 11690 format %{ "FDIV $dst,$src1,$src2" %} | |
| 11691 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
| 11692 ins_encode( Push_Reg_F(src1), | |
| 11693 OpcReg_F(src2), | |
| 11694 Pop_Mem_F(dst) ); | |
| 11695 ins_pipe( fpu_mem_reg_reg ); | |
| 11696 %} | |
| 11697 // | |
| 11698 // This instruction does not round to 24-bits | |
| 11699 instruct divF_reg(regF dst, regF src) %{ | |
| 11700 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11701 match(Set dst (DivF dst src)); | |
| 11702 | |
| 11703 format %{ "FDIV $dst,$src" %} | |
| 11704 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11705 ins_encode( Push_Reg_F(src), | |
| 11706 OpcP, RegOpc(dst) ); | |
| 11707 ins_pipe( fpu_reg_reg ); | |
| 11708 %} | |
| 11709 | |
| 11710 | |
| 11711 // Spill to obtain 24-bit precision | |
| 11712 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11713 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11714 match(Set dst (ModF src1 src2)); | |
| 11715 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11716 | |
| 11717 format %{ "FMOD $dst,$src1,$src2" %} | |
| 11718 ins_encode( Push_Reg_Mod_D(src1, src2), | |
| 11719 emitModD(), | |
| 11720 Push_Result_Mod_D(src2), | |
| 11721 Pop_Mem_F(dst)); | |
| 11722 ins_pipe( pipe_slow ); | |
| 11723 %} | |
| 11724 // | |
| 11725 // This instruction does not round to 24-bits | |
| 11726 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ | |
| 11727 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11728 match(Set dst (ModF dst src)); | |
| 11729 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11730 | |
| 11731 format %{ "FMOD $dst,$src" %} | |
| 11732 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 11733 emitModD(), | |
| 11734 Push_Result_Mod_D(src), | |
| 11735 Pop_Reg_F(dst)); | |
| 11736 ins_pipe( pipe_slow ); | |
| 11737 %} | |
| 11738 | |
| 11739 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 11740 predicate(UseSSE>=1); | |
| 11741 match(Set dst (ModF src0 src1)); | |
| 11742 effect(KILL rax, KILL cr); | |
| 11743 format %{ "SUB ESP,4\t # FMOD\n" | |
| 11744 "\tMOVSS [ESP+0],$src1\n" | |
| 11745 "\tFLD_S [ESP+0]\n" | |
| 11746 "\tMOVSS [ESP+0],$src0\n" | |
| 11747 "\tFLD_S [ESP+0]\n" | |
| 11748 "loop:\tFPREM\n" | |
| 11749 "\tFWAIT\n" | |
| 11750 "\tFNSTSW AX\n" | |
| 11751 "\tSAHF\n" | |
| 11752 "\tJP loop\n" | |
| 11753 "\tFSTP_S [ESP+0]\n" | |
| 11754 "\tMOVSS $dst,[ESP+0]\n" | |
| 11755 "\tADD ESP,4\n" | |
| 11756 "\tFSTP ST0\t # Restore FPU Stack" | |
| 11757 %} | |
| 11758 ins_cost(250); | |
| 11759 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); | |
| 11760 ins_pipe( pipe_slow ); | |
| 11761 %} | |
| 11762 | |
| 11763 | |
| 11764 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 11765 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 11766 | |
| 11767 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ | |
| 11768 predicate(UseSSE==0); | |
| 11769 match(Set dst (RoundFloat src)); | |
| 11770 ins_cost(125); | |
| 11771 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11772 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 11773 ins_pipe( fpu_mem_reg ); | |
| 11774 %} | |
| 11775 | |
| 11776 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ | |
| 11777 predicate(UseSSE<=1); | |
| 11778 match(Set dst (RoundDouble src)); | |
| 11779 ins_cost(125); | |
| 11780 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11781 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 11782 ins_pipe( fpu_mem_reg ); | |
| 11783 %} | |
| 11784 | |
| 11785 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11786 instruct convD2F_reg(stackSlotF dst, regD src) %{ | |
| 11787 predicate(UseSSE==0); | |
| 11788 match(Set dst (ConvD2F src)); | |
| 11789 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11790 expand %{ | |
| 11791 roundFloat_mem_reg(dst,src); | |
| 11792 %} | |
| 11793 %} | |
| 11794 | |
| 11795 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11796 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ | |
| 11797 predicate(UseSSE==1); | |
| 11798 match(Set dst (ConvD2F src)); | |
| 11799 effect( KILL cr ); | |
| 11800 format %{ "SUB ESP,4\n\t" | |
| 11801 "FST_S [ESP],$src\t# F-round\n\t" | |
| 11802 "MOVSS $dst,[ESP]\n\t" | |
| 11803 "ADD ESP,4" %} | |
| 11804 ins_encode( D2X_encoding(dst, src) ); | |
| 11805 ins_pipe( pipe_slow ); | |
| 11806 %} | |
| 11807 | |
| 11808 // Force rounding double precision to single precision | |
| 11809 instruct convXD2X_reg(regX dst, regXD src) %{ | |
| 11810 predicate(UseSSE>=2); | |
| 11811 match(Set dst (ConvD2F src)); | |
| 11812 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 11813 opcode(0xF2, 0x0F, 0x5A); | |
| 11814 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11815 ins_pipe( pipe_slow ); | |
| 11816 %} | |
| 11817 | |
| 11818 instruct convF2D_reg_reg(regD dst, regF src) %{ | |
| 11819 predicate(UseSSE==0); | |
| 11820 match(Set dst (ConvF2D src)); | |
| 11821 format %{ "FST_S $dst,$src\t# D-round" %} | |
| 11822 ins_encode( Pop_Reg_Reg_D(dst, src)); | |
| 11823 ins_pipe( fpu_reg_reg ); | |
| 11824 %} | |
| 11825 | |
| 11826 instruct convF2D_reg(stackSlotD dst, regF src) %{ | |
| 11827 predicate(UseSSE==1); | |
| 11828 match(Set dst (ConvF2D src)); | |
| 11829 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11830 expand %{ | |
| 11831 roundDouble_mem_reg(dst,src); | |
| 11832 %} | |
| 11833 %} | |
| 11834 | |
| 11835 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ | |
| 11836 predicate(UseSSE==1); | |
| 11837 match(Set dst (ConvF2D src)); | |
| 11838 effect( KILL cr ); | |
| 11839 format %{ "SUB ESP,4\n\t" | |
| 11840 "MOVSS [ESP] $src\n\t" | |
| 11841 "FLD_S [ESP]\n\t" | |
| 11842 "ADD ESP,4\n\t" | |
| 11843 "FSTP $dst\t# D-round" %} | |
| 11844 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); | |
| 11845 ins_pipe( pipe_slow ); | |
| 11846 %} | |
| 11847 | |
| 11848 instruct convX2XD_reg(regXD dst, regX src) %{ | |
| 11849 predicate(UseSSE>=2); | |
| 11850 match(Set dst (ConvF2D src)); | |
| 11851 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 11852 opcode(0xF3, 0x0F, 0x5A); | |
| 11853 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11854 ins_pipe( pipe_slow ); | |
| 11855 %} | |
| 11856 | |
| 11857 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11858 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ | |
| 11859 predicate(UseSSE<=1); | |
| 11860 match(Set dst (ConvD2I src)); | |
| 11861 effect( KILL tmp, KILL cr ); | |
| 11862 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 11863 "FLDCW trunc mode\n\t" | |
| 11864 "SUB ESP,4\n\t" | |
| 11865 "FISTp [ESP + #0]\n\t" | |
| 11866 "FLDCW std/24-bit mode\n\t" | |
| 11867 "POP EAX\n\t" | |
| 11868 "CMP EAX,0x80000000\n\t" | |
| 11869 "JNE,s fast\n\t" | |
| 11870 "FLD_D $src\n\t" | |
| 11871 "CALL d2i_wrapper\n" | |
| 11872 "fast:" %} | |
| 11873 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); | |
| 11874 ins_pipe( pipe_slow ); | |
| 11875 %} | |
| 11876 | |
| 11877 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11878 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ | |
| 11879 predicate(UseSSE>=2); | |
| 11880 match(Set dst (ConvD2I src)); | |
| 11881 effect( KILL tmp, KILL cr ); | |
| 11882 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 11883 "CMP $dst,0x80000000\n\t" | |
| 11884 "JNE,s fast\n\t" | |
| 11885 "SUB ESP, 8\n\t" | |
| 11886 "MOVSD [ESP], $src\n\t" | |
| 11887 "FLD_D [ESP]\n\t" | |
| 11888 "ADD ESP, 8\n\t" | |
| 11889 "CALL d2i_wrapper\n" | |
| 11890 "fast:" %} | |
| 11891 opcode(0x1); // double-precision conversion | |
| 11892 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11893 ins_pipe( pipe_slow ); | |
| 11894 %} | |
| 11895 | |
| 11896 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ | |
| 11897 predicate(UseSSE<=1); | |
| 11898 match(Set dst (ConvD2L src)); | |
| 11899 effect( KILL cr ); | |
| 11900 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 11901 "FLDCW trunc mode\n\t" | |
| 11902 "SUB ESP,8\n\t" | |
| 11903 "FISTp [ESP + #0]\n\t" | |
| 11904 "FLDCW std/24-bit mode\n\t" | |
| 11905 "POP EAX\n\t" | |
| 11906 "POP EDX\n\t" | |
| 11907 "CMP EDX,0x80000000\n\t" | |
| 11908 "JNE,s fast\n\t" | |
| 11909 "TEST EAX,EAX\n\t" | |
| 11910 "JNE,s fast\n\t" | |
| 11911 "FLD $src\n\t" | |
| 11912 "CALL d2l_wrapper\n" | |
| 11913 "fast:" %} | |
| 11914 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); | |
| 11915 ins_pipe( pipe_slow ); | |
| 11916 %} | |
| 11917 | |
| 11918 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11919 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ | |
| 11920 predicate (UseSSE>=2); | |
| 11921 match(Set dst (ConvD2L src)); | |
| 11922 effect( KILL cr ); | |
| 11923 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11924 "MOVSD [ESP],$src\n\t" | |
| 11925 "FLD_D [ESP]\n\t" | |
| 11926 "FLDCW trunc mode\n\t" | |
| 11927 "FISTp [ESP + #0]\n\t" | |
| 11928 "FLDCW std/24-bit mode\n\t" | |
| 11929 "POP EAX\n\t" | |
| 11930 "POP EDX\n\t" | |
| 11931 "CMP EDX,0x80000000\n\t" | |
| 11932 "JNE,s fast\n\t" | |
| 11933 "TEST EAX,EAX\n\t" | |
| 11934 "JNE,s fast\n\t" | |
| 11935 "SUB ESP,8\n\t" | |
| 11936 "MOVSD [ESP],$src\n\t" | |
| 11937 "FLD_D [ESP]\n\t" | |
| 11938 "CALL d2l_wrapper\n" | |
| 11939 "fast:" %} | |
| 11940 ins_encode( XD2L_encoding(src) ); | |
| 11941 ins_pipe( pipe_slow ); | |
| 11942 %} | |
| 11943 | |
| 11944 // Convert a double to an int. Java semantics require we do complex | |
| 11945 // manglations in the corner cases. So we set the rounding mode to | |
| 11946 // 'zero', store the darned double down as an int, and reset the | |
| 11947 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11948 // if we would overflow or converted a NAN; we check for this and | |
| 11949 // and go the slow path if needed. | |
| 11950 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ | |
| 11951 predicate(UseSSE==0); | |
| 11952 match(Set dst (ConvF2I src)); | |
| 11953 effect( KILL tmp, KILL cr ); | |
| 11954 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11955 "FLDCW trunc mode\n\t" | |
| 11956 "SUB ESP,4\n\t" | |
| 11957 "FISTp [ESP + #0]\n\t" | |
| 11958 "FLDCW std/24-bit mode\n\t" | |
| 11959 "POP EAX\n\t" | |
| 11960 "CMP EAX,0x80000000\n\t" | |
| 11961 "JNE,s fast\n\t" | |
| 11962 "FLD $src\n\t" | |
| 11963 "CALL d2i_wrapper\n" | |
| 11964 "fast:" %} | |
| 11965 // D2I_encoding works for F2I | |
| 11966 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); | |
| 11967 ins_pipe( pipe_slow ); | |
| 11968 %} | |
| 11969 | |
| 11970 // Convert a float in xmm to an int reg. | |
| 11971 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ | |
| 11972 predicate(UseSSE>=1); | |
| 11973 match(Set dst (ConvF2I src)); | |
| 11974 effect( KILL tmp, KILL cr ); | |
| 11975 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11976 "CMP $dst,0x80000000\n\t" | |
| 11977 "JNE,s fast\n\t" | |
| 11978 "SUB ESP, 4\n\t" | |
| 11979 "MOVSS [ESP], $src\n\t" | |
| 11980 "FLD [ESP]\n\t" | |
| 11981 "ADD ESP, 4\n\t" | |
| 11982 "CALL d2i_wrapper\n" | |
| 11983 "fast:" %} | |
| 11984 opcode(0x0); // single-precision conversion | |
| 11985 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11986 ins_pipe( pipe_slow ); | |
| 11987 %} | |
| 11988 | |
| 11989 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ | |
| 11990 predicate(UseSSE==0); | |
| 11991 match(Set dst (ConvF2L src)); | |
| 11992 effect( KILL cr ); | |
| 11993 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11994 "FLDCW trunc mode\n\t" | |
| 11995 "SUB ESP,8\n\t" | |
| 11996 "FISTp [ESP + #0]\n\t" | |
| 11997 "FLDCW std/24-bit mode\n\t" | |
| 11998 "POP EAX\n\t" | |
| 11999 "POP EDX\n\t" | |
| 12000 "CMP EDX,0x80000000\n\t" | |
| 12001 "JNE,s fast\n\t" | |
| 12002 "TEST EAX,EAX\n\t" | |
| 12003 "JNE,s fast\n\t" | |
| 12004 "FLD $src\n\t" | |
| 12005 "CALL d2l_wrapper\n" | |
| 12006 "fast:" %} | |
| 12007 // D2L_encoding works for F2L | |
| 12008 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); | |
| 12009 ins_pipe( pipe_slow ); | |
| 12010 %} | |
| 12011 | |
| 12012 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 12013 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ | |
| 12014 predicate (UseSSE>=1); | |
| 12015 match(Set dst (ConvF2L src)); | |
| 12016 effect( KILL cr ); | |
| 12017 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 12018 "MOVSS [ESP],$src\n\t" | |
| 12019 "FLD_S [ESP]\n\t" | |
| 12020 "FLDCW trunc mode\n\t" | |
| 12021 "FISTp [ESP + #0]\n\t" | |
| 12022 "FLDCW std/24-bit mode\n\t" | |
| 12023 "POP EAX\n\t" | |
| 12024 "POP EDX\n\t" | |
| 12025 "CMP EDX,0x80000000\n\t" | |
| 12026 "JNE,s fast\n\t" | |
| 12027 "TEST EAX,EAX\n\t" | |
| 12028 "JNE,s fast\n\t" | |
| 12029 "SUB ESP,4\t# Convert float to long\n\t" | |
| 12030 "MOVSS [ESP],$src\n\t" | |
| 12031 "FLD_S [ESP]\n\t" | |
| 12032 "ADD ESP,4\n\t" | |
| 12033 "CALL d2l_wrapper\n" | |
| 12034 "fast:" %} | |
| 12035 ins_encode( X2L_encoding(src) ); | |
| 12036 ins_pipe( pipe_slow ); | |
| 12037 %} | |
| 12038 | |
| 12039 instruct convI2D_reg(regD dst, stackSlotI src) %{ | |
| 12040 predicate( UseSSE<=1 ); | |
| 12041 match(Set dst (ConvI2D src)); | |
| 12042 format %{ "FILD $src\n\t" | |
| 12043 "FSTP $dst" %} | |
| 12044 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12045 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); | |
| 12046 ins_pipe( fpu_reg_mem ); | |
| 12047 %} | |
| 12048 | |
| 12049 instruct convI2XD_reg(regXD dst, eRegI src) %{ | |
| 71 | 12050 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 12051 match(Set dst (ConvI2D src)); |
| 12052 format %{ "CVTSI2SD $dst,$src" %} | |
| 12053 opcode(0xF2, 0x0F, 0x2A); | |
| 12054 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 12055 ins_pipe( pipe_slow ); | |
| 12056 %} | |
| 12057 | |
| 12058 instruct convI2XD_mem(regXD dst, memory mem) %{ | |
| 12059 predicate( UseSSE>=2 ); | |
| 12060 match(Set dst (ConvI2D (LoadI mem))); | |
| 12061 format %{ "CVTSI2SD $dst,$mem" %} | |
| 12062 opcode(0xF2, 0x0F, 0x2A); | |
| 12063 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); | |
| 12064 ins_pipe( pipe_slow ); | |
| 12065 %} | |
| 12066 | |
| 71 | 12067 instruct convXI2XD_reg(regXD dst, eRegI src) |
| 12068 %{ | |
| 12069 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 12070 match(Set dst (ConvI2D src)); | |
| 12071 | |
| 12072 format %{ "MOVD $dst,$src\n\t" | |
| 12073 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 12074 ins_encode %{ | |
| 304 | 12075 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 12076 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 12077 %} | |
| 12078 ins_pipe(pipe_slow); // XXX | |
| 12079 %} | |
| 12080 | |
| 0 | 12081 instruct convI2D_mem(regD dst, memory mem) %{ |
| 12082 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); | |
| 12083 match(Set dst (ConvI2D (LoadI mem))); | |
| 12084 format %{ "FILD $mem\n\t" | |
| 12085 "FSTP $dst" %} | |
| 12086 opcode(0xDB); /* DB /0 */ | |
| 12087 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12088 Pop_Reg_D(dst)); | |
| 12089 ins_pipe( fpu_reg_mem ); | |
| 12090 %} | |
| 12091 | |
| 12092 // Convert a byte to a float; no rounding step needed. | |
| 12093 instruct conv24I2F_reg(regF dst, stackSlotI src) %{ | |
| 12094 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); | |
| 12095 match(Set dst (ConvI2F src)); | |
| 12096 format %{ "FILD $src\n\t" | |
| 12097 "FSTP $dst" %} | |
| 12098 | |
| 12099 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12100 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); | |
| 12101 ins_pipe( fpu_reg_mem ); | |
| 12102 %} | |
| 12103 | |
| 12104 // In 24-bit mode, force exponent rounding by storing back out | |
| 12105 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ | |
| 12106 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 12107 match(Set dst (ConvI2F src)); | |
| 12108 ins_cost(200); | |
| 12109 format %{ "FILD $src\n\t" | |
| 12110 "FSTP_S $dst" %} | |
| 12111 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12112 ins_encode( Push_Mem_I(src), | |
| 12113 Pop_Mem_F(dst)); | |
| 12114 ins_pipe( fpu_mem_mem ); | |
| 12115 %} | |
| 12116 | |
| 12117 // In 24-bit mode, force exponent rounding by storing back out | |
| 12118 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ | |
| 12119 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 12120 match(Set dst (ConvI2F (LoadI mem))); | |
| 12121 ins_cost(200); | |
| 12122 format %{ "FILD $mem\n\t" | |
| 12123 "FSTP_S $dst" %} | |
| 12124 opcode(0xDB); /* DB /0 */ | |
| 12125 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12126 Pop_Mem_F(dst)); | |
| 12127 ins_pipe( fpu_mem_mem ); | |
| 12128 %} | |
| 12129 | |
| 12130 // This instruction does not round to 24-bits | |
| 12131 instruct convI2F_reg(regF dst, stackSlotI src) %{ | |
| 12132 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 12133 match(Set dst (ConvI2F src)); | |
| 12134 format %{ "FILD $src\n\t" | |
| 12135 "FSTP $dst" %} | |
| 12136 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12137 ins_encode( Push_Mem_I(src), | |
| 12138 Pop_Reg_F(dst)); | |
| 12139 ins_pipe( fpu_reg_mem ); | |
| 12140 %} | |
| 12141 | |
| 12142 // This instruction does not round to 24-bits | |
| 12143 instruct convI2F_mem(regF dst, memory mem) %{ | |
| 12144 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 12145 match(Set dst (ConvI2F (LoadI mem))); | |
| 12146 format %{ "FILD $mem\n\t" | |
| 12147 "FSTP $dst" %} | |
| 12148 opcode(0xDB); /* DB /0 */ | |
| 12149 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12150 Pop_Reg_F(dst)); | |
| 12151 ins_pipe( fpu_reg_mem ); | |
| 12152 %} | |
| 12153 | |
| 12154 // Convert an int to a float in xmm; no rounding step needed. | |
| 12155 instruct convI2X_reg(regX dst, eRegI src) %{ | |
| 71 | 12156 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 12157 match(Set dst (ConvI2F src)); |
| 12158 format %{ "CVTSI2SS $dst, $src" %} | |
| 12159 | |
| 12160 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ | |
| 12161 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 12162 ins_pipe( pipe_slow ); | |
| 12163 %} | |
| 12164 | |
| 71 | 12165 instruct convXI2X_reg(regX dst, eRegI src) |
| 12166 %{ | |
| 12167 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 12168 match(Set dst (ConvI2F src)); | |
| 12169 | |
| 12170 format %{ "MOVD $dst,$src\n\t" | |
| 12171 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 12172 ins_encode %{ | |
| 304 | 12173 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 12174 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 12175 %} | |
| 12176 ins_pipe(pipe_slow); // XXX | |
| 12177 %} | |
| 12178 | |
| 0 | 12179 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ |
| 12180 match(Set dst (ConvI2L src)); | |
| 12181 effect(KILL cr); | |
| 624 | 12182 ins_cost(375); |
| 0 | 12183 format %{ "MOV $dst.lo,$src\n\t" |
| 12184 "MOV $dst.hi,$src\n\t" | |
| 12185 "SAR $dst.hi,31" %} | |
| 12186 ins_encode(convert_int_long(dst,src)); | |
| 12187 ins_pipe( ialu_reg_reg_long ); | |
| 12188 %} | |
| 12189 | |
| 12190 // Zero-extend convert int to long | |
| 12191 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 12192 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 12193 effect( KILL flags ); | |
| 624 | 12194 ins_cost(250); |
| 0 | 12195 format %{ "MOV $dst.lo,$src\n\t" |
| 12196 "XOR $dst.hi,$dst.hi" %} | |
| 12197 opcode(0x33); // XOR | |
| 12198 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 12199 ins_pipe( ialu_reg_reg_long ); | |
| 12200 %} | |
| 12201 | |
| 12202 // Zero-extend long | |
| 12203 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 12204 match(Set dst (AndL src mask) ); | |
| 12205 effect( KILL flags ); | |
| 624 | 12206 ins_cost(250); |
| 0 | 12207 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 12208 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 12209 opcode(0x33); // XOR | |
| 12210 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 12211 ins_pipe( ialu_reg_reg_long ); | |
| 12212 %} | |
| 12213 | |
| 12214 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ | |
| 12215 predicate (UseSSE<=1); | |
| 12216 match(Set dst (ConvL2D src)); | |
| 12217 effect( KILL cr ); | |
| 12218 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12219 "PUSH $src.lo\n\t" | |
| 12220 "FILD ST,[ESP + #0]\n\t" | |
| 12221 "ADD ESP,8\n\t" | |
| 12222 "FSTP_D $dst\t# D-round" %} | |
| 12223 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12224 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); | |
| 12225 ins_pipe( pipe_slow ); | |
| 12226 %} | |
| 12227 | |
| 12228 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ | |
| 12229 predicate (UseSSE>=2); | |
| 12230 match(Set dst (ConvL2D src)); | |
| 12231 effect( KILL cr ); | |
| 12232 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12233 "PUSH $src.lo\n\t" | |
| 12234 "FILD_D [ESP]\n\t" | |
| 12235 "FSTP_D [ESP]\n\t" | |
| 12236 "MOVSD $dst,[ESP]\n\t" | |
| 12237 "ADD ESP,8" %} | |
| 12238 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12239 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); | |
| 12240 ins_pipe( pipe_slow ); | |
| 12241 %} | |
| 12242 | |
| 12243 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ | |
| 12244 predicate (UseSSE>=1); | |
| 12245 match(Set dst (ConvL2F src)); | |
| 12246 effect( KILL cr ); | |
| 12247 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12248 "PUSH $src.lo\n\t" | |
| 12249 "FILD_D [ESP]\n\t" | |
| 12250 "FSTP_S [ESP]\n\t" | |
| 12251 "MOVSS $dst,[ESP]\n\t" | |
| 12252 "ADD ESP,8" %} | |
| 12253 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12254 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); | |
| 12255 ins_pipe( pipe_slow ); | |
| 12256 %} | |
| 12257 | |
| 12258 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ | |
| 12259 match(Set dst (ConvL2F src)); | |
| 12260 effect( KILL cr ); | |
| 12261 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12262 "PUSH $src.lo\n\t" | |
| 12263 "FILD ST,[ESP + #0]\n\t" | |
| 12264 "ADD ESP,8\n\t" | |
| 12265 "FSTP_S $dst\t# F-round" %} | |
| 12266 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12267 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); | |
| 12268 ins_pipe( pipe_slow ); | |
| 12269 %} | |
| 12270 | |
| 12271 instruct convL2I_reg( eRegI dst, eRegL src ) %{ | |
| 12272 match(Set dst (ConvL2I src)); | |
| 12273 effect( DEF dst, USE src ); | |
| 12274 format %{ "MOV $dst,$src.lo" %} | |
| 12275 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 12276 ins_pipe( ialu_reg_reg ); | |
| 12277 %} | |
| 12278 | |
| 12279 | |
| 12280 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ | |
| 12281 match(Set dst (MoveF2I src)); | |
| 12282 effect( DEF dst, USE src ); | |
| 12283 ins_cost(100); | |
| 12284 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 12285 opcode(0x8B); | |
| 12286 ins_encode( OpcP, RegMem(dst,src)); | |
| 12287 ins_pipe( ialu_reg_mem ); | |
| 12288 %} | |
| 12289 | |
| 12290 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 12291 predicate(UseSSE==0); | |
| 12292 match(Set dst (MoveF2I src)); | |
| 12293 effect( DEF dst, USE src ); | |
| 12294 | |
| 12295 ins_cost(125); | |
| 12296 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
| 12297 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 12298 ins_pipe( fpu_mem_reg ); | |
| 12299 %} | |
| 12300 | |
| 12301 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ | |
| 12302 predicate(UseSSE>=1); | |
| 12303 match(Set dst (MoveF2I src)); | |
| 12304 effect( DEF dst, USE src ); | |
| 12305 | |
| 12306 ins_cost(95); | |
| 12307 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 12308 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); | |
| 12309 ins_pipe( pipe_slow ); | |
| 12310 %} | |
| 12311 | |
| 12312 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ | |
| 12313 predicate(UseSSE>=2); | |
| 12314 match(Set dst (MoveF2I src)); | |
| 12315 effect( DEF dst, USE src ); | |
| 12316 ins_cost(85); | |
| 12317 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 12318 ins_encode( MovX2I_reg(dst, src)); | |
| 12319 ins_pipe( pipe_slow ); | |
| 12320 %} | |
| 12321 | |
| 12322 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ | |
| 12323 match(Set dst (MoveI2F src)); | |
| 12324 effect( DEF dst, USE src ); | |
| 12325 | |
| 12326 ins_cost(100); | |
| 12327 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 12328 opcode(0x89); | |
| 12329 ins_encode( OpcPRegSS( dst, src ) ); | |
| 12330 ins_pipe( ialu_mem_reg ); | |
| 12331 %} | |
| 12332 | |
| 12333 | |
| 12334 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 12335 predicate(UseSSE==0); | |
| 12336 match(Set dst (MoveI2F src)); | |
| 12337 effect(DEF dst, USE src); | |
| 12338 | |
| 12339 ins_cost(125); | |
| 12340 format %{ "FLD_S $src\n\t" | |
| 12341 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 12342 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 12343 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12344 Pop_Reg_F(dst) ); | |
| 12345 ins_pipe( fpu_reg_mem ); | |
| 12346 %} | |
| 12347 | |
| 12348 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ | |
| 12349 predicate(UseSSE>=1); | |
| 12350 match(Set dst (MoveI2F src)); | |
| 12351 effect( DEF dst, USE src ); | |
| 12352 | |
| 12353 ins_cost(95); | |
| 12354 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 12355 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12356 ins_pipe( pipe_slow ); | |
| 12357 %} | |
| 12358 | |
| 12359 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ | |
| 12360 predicate(UseSSE>=2); | |
| 12361 match(Set dst (MoveI2F src)); | |
| 12362 effect( DEF dst, USE src ); | |
| 12363 | |
| 12364 ins_cost(85); | |
| 12365 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 12366 ins_encode( MovI2X_reg(dst, src) ); | |
| 12367 ins_pipe( pipe_slow ); | |
| 12368 %} | |
| 12369 | |
| 12370 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 12371 match(Set dst (MoveD2L src)); | |
| 12372 effect(DEF dst, USE src); | |
| 12373 | |
| 12374 ins_cost(250); | |
| 12375 format %{ "MOV $dst.lo,$src\n\t" | |
| 12376 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 12377 opcode(0x8B, 0x8B); | |
| 12378 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 12379 ins_pipe( ialu_mem_long_reg ); | |
| 12380 %} | |
| 12381 | |
| 12382 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 12383 predicate(UseSSE<=1); | |
| 12384 match(Set dst (MoveD2L src)); | |
| 12385 effect(DEF dst, USE src); | |
| 12386 | |
| 12387 ins_cost(125); | |
| 12388 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
| 12389 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 12390 ins_pipe( fpu_mem_reg ); | |
| 12391 %} | |
| 12392 | |
| 12393 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ | |
| 12394 predicate(UseSSE>=2); | |
| 12395 match(Set dst (MoveD2L src)); | |
| 12396 effect(DEF dst, USE src); | |
| 12397 ins_cost(95); | |
| 12398 | |
| 12399 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 12400 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); | |
| 12401 ins_pipe( pipe_slow ); | |
| 12402 %} | |
| 12403 | |
| 12404 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ | |
| 12405 predicate(UseSSE>=2); | |
| 12406 match(Set dst (MoveD2L src)); | |
| 12407 effect(DEF dst, USE src, TEMP tmp); | |
| 12408 ins_cost(85); | |
| 12409 format %{ "MOVD $dst.lo,$src\n\t" | |
| 12410 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 12411 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 12412 ins_encode( MovXD2L_reg(dst, src, tmp) ); | |
| 12413 ins_pipe( pipe_slow ); | |
| 12414 %} | |
| 12415 | |
| 12416 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 12417 match(Set dst (MoveL2D src)); | |
| 12418 effect(DEF dst, USE src); | |
| 12419 | |
| 12420 ins_cost(200); | |
| 12421 format %{ "MOV $dst,$src.lo\n\t" | |
| 12422 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 12423 opcode(0x89, 0x89); | |
| 12424 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 12425 ins_pipe( ialu_mem_long_reg ); | |
| 12426 %} | |
| 12427 | |
| 12428 | |
| 12429 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 12430 predicate(UseSSE<=1); | |
| 12431 match(Set dst (MoveL2D src)); | |
| 12432 effect(DEF dst, USE src); | |
| 12433 ins_cost(125); | |
| 12434 | |
| 12435 format %{ "FLD_D $src\n\t" | |
| 12436 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 12437 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 12438 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12439 Pop_Reg_D(dst) ); | |
| 12440 ins_pipe( fpu_reg_mem ); | |
| 12441 %} | |
| 12442 | |
| 12443 | |
| 12444 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ | |
| 12445 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 12446 match(Set dst (MoveL2D src)); | |
| 12447 effect(DEF dst, USE src); | |
| 12448 | |
| 12449 ins_cost(95); | |
| 12450 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12451 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12452 ins_pipe( pipe_slow ); | |
| 12453 %} | |
| 12454 | |
| 12455 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ | |
| 12456 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 12457 match(Set dst (MoveL2D src)); | |
| 12458 effect(DEF dst, USE src); | |
| 12459 | |
| 12460 ins_cost(95); | |
| 12461 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12462 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); | |
| 12463 ins_pipe( pipe_slow ); | |
| 12464 %} | |
| 12465 | |
| 12466 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ | |
| 12467 predicate(UseSSE>=2); | |
| 12468 match(Set dst (MoveL2D src)); | |
| 12469 effect(TEMP dst, USE src, TEMP tmp); | |
| 12470 ins_cost(85); | |
| 12471 format %{ "MOVD $dst,$src.lo\n\t" | |
| 12472 "MOVD $tmp,$src.hi\n\t" | |
| 12473 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 12474 ins_encode( MovL2XD_reg(dst, src, tmp) ); | |
| 12475 ins_pipe( pipe_slow ); | |
| 12476 %} | |
| 12477 | |
| 12478 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12479 instruct Repl8B_reg(regXD dst, regXD src) %{ | |
| 12480 predicate(UseSSE>=2); | |
| 12481 match(Set dst (Replicate8B src)); | |
| 12482 format %{ "MOVDQA $dst,$src\n\t" | |
| 12483 "PUNPCKLBW $dst,$dst\n\t" | |
| 12484 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12485 ins_encode( pshufd_8x8(dst, src)); | |
| 12486 ins_pipe( pipe_slow ); | |
| 12487 %} | |
| 12488 | |
| 12489 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12490 instruct Repl8B_eRegI(regXD dst, eRegI src) %{ | |
| 12491 predicate(UseSSE>=2); | |
| 12492 match(Set dst (Replicate8B src)); | |
| 12493 format %{ "MOVD $dst,$src\n\t" | |
| 12494 "PUNPCKLBW $dst,$dst\n\t" | |
| 12495 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12496 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 12497 ins_pipe( pipe_slow ); | |
| 12498 %} | |
| 12499 | |
| 12500 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 12501 instruct Repl8B_immI0(regXD dst, immI0 zero) %{ | |
| 12502 predicate(UseSSE>=2); | |
| 12503 match(Set dst (Replicate8B zero)); | |
| 12504 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 12505 ins_encode( pxor(dst, dst)); | |
| 12506 ins_pipe( fpu_reg_reg ); | |
| 12507 %} | |
| 12508 | |
| 12509 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12510 instruct Repl4S_reg(regXD dst, regXD src) %{ | |
| 12511 predicate(UseSSE>=2); | |
| 12512 match(Set dst (Replicate4S src)); | |
| 12513 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 12514 ins_encode( pshufd_4x16(dst, src)); | |
| 12515 ins_pipe( fpu_reg_reg ); | |
| 12516 %} | |
| 12517 | |
| 12518 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12519 instruct Repl4S_eRegI(regXD dst, eRegI src) %{ | |
| 12520 predicate(UseSSE>=2); | |
| 12521 match(Set dst (Replicate4S src)); | |
| 12522 format %{ "MOVD $dst,$src\n\t" | |
| 12523 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 12524 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12525 ins_pipe( fpu_reg_reg ); | |
| 12526 %} | |
| 12527 | |
| 12528 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 12529 instruct Repl4S_immI0(regXD dst, immI0 zero) %{ | |
| 12530 predicate(UseSSE>=2); | |
| 12531 match(Set dst (Replicate4S zero)); | |
| 12532 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 12533 ins_encode( pxor(dst, dst)); | |
| 12534 ins_pipe( fpu_reg_reg ); | |
| 12535 %} | |
| 12536 | |
| 12537 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12538 instruct Repl4C_reg(regXD dst, regXD src) %{ | |
| 12539 predicate(UseSSE>=2); | |
| 12540 match(Set dst (Replicate4C src)); | |
| 12541 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 12542 ins_encode( pshufd_4x16(dst, src)); | |
| 12543 ins_pipe( fpu_reg_reg ); | |
| 12544 %} | |
| 12545 | |
| 12546 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12547 instruct Repl4C_eRegI(regXD dst, eRegI src) %{ | |
| 12548 predicate(UseSSE>=2); | |
| 12549 match(Set dst (Replicate4C src)); | |
| 12550 format %{ "MOVD $dst,$src\n\t" | |
| 12551 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 12552 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12553 ins_pipe( fpu_reg_reg ); | |
| 12554 %} | |
| 12555 | |
| 12556 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 12557 instruct Repl4C_immI0(regXD dst, immI0 zero) %{ | |
| 12558 predicate(UseSSE>=2); | |
| 12559 match(Set dst (Replicate4C zero)); | |
| 12560 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 12561 ins_encode( pxor(dst, dst)); | |
| 12562 ins_pipe( fpu_reg_reg ); | |
| 12563 %} | |
| 12564 | |
| 12565 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12566 instruct Repl2I_reg(regXD dst, regXD src) %{ | |
| 12567 predicate(UseSSE>=2); | |
| 12568 match(Set dst (Replicate2I src)); | |
| 12569 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 12570 ins_encode( pshufd(dst, src, 0x00)); | |
| 12571 ins_pipe( fpu_reg_reg ); | |
| 12572 %} | |
| 12573 | |
| 12574 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12575 instruct Repl2I_eRegI(regXD dst, eRegI src) %{ | |
| 12576 predicate(UseSSE>=2); | |
| 12577 match(Set dst (Replicate2I src)); | |
| 12578 format %{ "MOVD $dst,$src\n\t" | |
| 12579 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 12580 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 12581 ins_pipe( fpu_reg_reg ); | |
| 12582 %} | |
| 12583 | |
| 12584 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 12585 instruct Repl2I_immI0(regXD dst, immI0 zero) %{ | |
| 12586 predicate(UseSSE>=2); | |
| 12587 match(Set dst (Replicate2I zero)); | |
| 12588 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 12589 ins_encode( pxor(dst, dst)); | |
| 12590 ins_pipe( fpu_reg_reg ); | |
| 12591 %} | |
| 12592 | |
| 12593 // Replicate scalar to packed single precision floating point values in xmm | |
| 12594 instruct Repl2F_reg(regXD dst, regXD src) %{ | |
| 12595 predicate(UseSSE>=2); | |
| 12596 match(Set dst (Replicate2F src)); | |
| 12597 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12598 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12599 ins_pipe( fpu_reg_reg ); | |
| 12600 %} | |
| 12601 | |
| 12602 // Replicate scalar to packed single precision floating point values in xmm | |
| 12603 instruct Repl2F_regX(regXD dst, regX src) %{ | |
| 12604 predicate(UseSSE>=2); | |
| 12605 match(Set dst (Replicate2F src)); | |
| 12606 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12607 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12608 ins_pipe( fpu_reg_reg ); | |
| 12609 %} | |
| 12610 | |
| 12611 // Replicate scalar to packed single precision floating point values in xmm | |
| 12612 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ | |
| 12613 predicate(UseSSE>=2); | |
| 12614 match(Set dst (Replicate2F zero)); | |
| 12615 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 12616 ins_encode( pxor(dst, dst)); | |
| 12617 ins_pipe( fpu_reg_reg ); | |
| 12618 %} | |
| 12619 | |
| 12620 // ======================================================================= | |
| 12621 // fast clearing of an array | |
| 12622 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 12623 match(Set dummy (ClearArray cnt base)); | |
| 12624 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 12625 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 12626 "XOR EAX,EAX\n\t" | |
| 12627 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 12628 opcode(0,0x4); | |
| 12629 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 12630 OpcRegReg(0x33,EAX,EAX), | |
| 12631 Opcode(0xF3), Opcode(0xAB) ); | |
| 12632 ins_pipe( pipe_slow ); | |
| 12633 %} | |
| 12634 | |
| 2262 | 12635 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
| 12636 eAXRegI result, regXD tmp1, eFlagsReg cr) %{ | |
|
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12637 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 12638 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 12639 | |
| 12640 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
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12641 ins_encode %{ |
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12642 __ string_compare($str1$$Register, $str2$$Register, |
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12643 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 12644 $tmp1$$XMMRegister); |
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12645 %} |
| 681 | 12646 ins_pipe( pipe_slow ); |
| 12647 %} | |
| 12648 | |
| 12649 // fast string equals | |
|
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12650 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
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12651 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
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12652 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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12653 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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12654 |
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12655 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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12656 ins_encode %{ |
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12657 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
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12658 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
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12659 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
12660 %} |
|
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|
12661 ins_pipe( pipe_slow ); |
|
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|
12662 %} |
|
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12663 |
|
2320
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12664 // fast search of substring with known size. |
|
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|
12665 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
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12666 eBXRegI result, regXD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
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12667 predicate(UseSSE42Intrinsics); |
|
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12668 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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12669 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
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|
12670 |
|
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|
12671 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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|
12672 ins_encode %{ |
|
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|
12673 int icnt2 = (int)$int_cnt2$$constant; |
|
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12674 if (icnt2 >= 8) { |
|
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|
12675 // IndexOf for constant substrings with size >= 8 elements |
|
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12676 // which don't need to be loaded through stack. |
|
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12677 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
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12678 $cnt1$$Register, $cnt2$$Register, |
|
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|
12679 icnt2, $result$$Register, |
|
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12680 $vec$$XMMRegister, $tmp$$Register); |
|
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|
12681 } else { |
|
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|
12682 // Small strings are loaded through stack if they cross page boundary. |
|
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|
12683 __ string_indexof($str1$$Register, $str2$$Register, |
|
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|
12684 $cnt1$$Register, $cnt2$$Register, |
|
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|
12685 icnt2, $result$$Register, |
|
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|
12686 $vec$$XMMRegister, $tmp$$Register); |
|
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|
12687 } |
|
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|
12688 %} |
|
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|
12689 ins_pipe( pipe_slow ); |
|
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|
12690 %} |
|
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|
12691 |
|
986
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|
12692 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
2320
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|
12693 eBXRegI result, regXD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 12694 predicate(UseSSE42Intrinsics); |
|
986
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|
12695 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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|
12696 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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|
12697 |
|
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|
12698 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
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|
12699 ins_encode %{ |
|
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|
12700 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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|
12701 $cnt1$$Register, $cnt2$$Register, |
|
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|
12702 (-1), $result$$Register, |
|
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|
12703 $vec$$XMMRegister, $tmp$$Register); |
|
986
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|
12704 %} |
| 0 | 12705 ins_pipe( pipe_slow ); |
| 12706 %} | |
| 12707 | |
|
169
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6695049: (coll) Create an x86 intrinsic for Arrays.equals
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|
12708 // fast array equals |
|
986
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|
12709 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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|
12710 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
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|
12711 %{ |
|
169
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|
12712 match(Set result (AryEq ary1 ary2)); |
| 681 | 12713 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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|
12714 //ins_cost(300); |
|
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|
12715 |
|
986
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|
12716 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
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|
12717 ins_encode %{ |
|
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|
12718 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
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|
12719 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
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|
12720 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
12721 %} |
|
169
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|
12722 ins_pipe( pipe_slow ); |
|
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|
12723 %} |
|
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|
12724 |
| 0 | 12725 //----------Control Flow Instructions------------------------------------------ |
| 12726 // Signed compare Instructions | |
| 12727 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ | |
| 12728 match(Set cr (CmpI op1 op2)); | |
| 12729 effect( DEF cr, USE op1, USE op2 ); | |
| 12730 format %{ "CMP $op1,$op2" %} | |
| 12731 opcode(0x3B); /* Opcode 3B /r */ | |
| 12732 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12733 ins_pipe( ialu_cr_reg_reg ); | |
| 12734 %} | |
| 12735 | |
| 12736 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ | |
| 12737 match(Set cr (CmpI op1 op2)); | |
| 12738 effect( DEF cr, USE op1 ); | |
| 12739 format %{ "CMP $op1,$op2" %} | |
| 12740 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12741 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 12742 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12743 ins_pipe( ialu_cr_reg_imm ); | |
| 12744 %} | |
| 12745 | |
| 12746 // Cisc-spilled version of cmpI_eReg | |
| 12747 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ | |
| 12748 match(Set cr (CmpI op1 (LoadI op2))); | |
| 12749 | |
| 12750 format %{ "CMP $op1,$op2" %} | |
| 12751 ins_cost(500); | |
| 12752 opcode(0x3B); /* Opcode 3B /r */ | |
| 12753 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12754 ins_pipe( ialu_cr_reg_mem ); | |
| 12755 %} | |
| 12756 | |
| 12757 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ | |
| 12758 match(Set cr (CmpI src zero)); | |
| 12759 effect( DEF cr, USE src ); | |
| 12760 | |
| 12761 format %{ "TEST $src,$src" %} | |
| 12762 opcode(0x85); | |
| 12763 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12764 ins_pipe( ialu_cr_reg_imm ); | |
| 12765 %} | |
| 12766 | |
| 12767 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ | |
| 12768 match(Set cr (CmpI (AndI src con) zero)); | |
| 12769 | |
| 12770 format %{ "TEST $src,$con" %} | |
| 12771 opcode(0xF7,0x00); | |
| 12772 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 12773 ins_pipe( ialu_cr_reg_imm ); | |
| 12774 %} | |
| 12775 | |
| 12776 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ | |
| 12777 match(Set cr (CmpI (AndI src mem) zero)); | |
| 12778 | |
| 12779 format %{ "TEST $src,$mem" %} | |
| 12780 opcode(0x85); | |
| 12781 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 12782 ins_pipe( ialu_cr_reg_mem ); | |
| 12783 %} | |
| 12784 | |
| 12785 // Unsigned compare Instructions; really, same as signed except they | |
| 12786 // produce an eFlagsRegU instead of eFlagsReg. | |
| 12787 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ | |
| 12788 match(Set cr (CmpU op1 op2)); | |
| 12789 | |
| 12790 format %{ "CMPu $op1,$op2" %} | |
| 12791 opcode(0x3B); /* Opcode 3B /r */ | |
| 12792 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12793 ins_pipe( ialu_cr_reg_reg ); | |
| 12794 %} | |
| 12795 | |
| 12796 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ | |
| 12797 match(Set cr (CmpU op1 op2)); | |
| 12798 | |
| 12799 format %{ "CMPu $op1,$op2" %} | |
| 12800 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12801 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12802 ins_pipe( ialu_cr_reg_imm ); | |
| 12803 %} | |
| 12804 | |
| 12805 // // Cisc-spilled version of cmpU_eReg | |
| 12806 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ | |
| 12807 match(Set cr (CmpU op1 (LoadI op2))); | |
| 12808 | |
| 12809 format %{ "CMPu $op1,$op2" %} | |
| 12810 ins_cost(500); | |
| 12811 opcode(0x3B); /* Opcode 3B /r */ | |
| 12812 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12813 ins_pipe( ialu_cr_reg_mem ); | |
| 12814 %} | |
| 12815 | |
| 12816 // // Cisc-spilled version of cmpU_eReg | |
| 12817 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ | |
| 12818 // match(Set cr (CmpU (LoadI op1) op2)); | |
| 12819 // | |
| 12820 // format %{ "CMPu $op1,$op2" %} | |
| 12821 // ins_cost(500); | |
| 12822 // opcode(0x39); /* Opcode 39 /r */ | |
| 12823 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12824 //%} | |
| 12825 | |
| 12826 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ | |
| 12827 match(Set cr (CmpU src zero)); | |
| 12828 | |
| 12829 format %{ "TESTu $src,$src" %} | |
| 12830 opcode(0x85); | |
| 12831 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12832 ins_pipe( ialu_cr_reg_imm ); | |
| 12833 %} | |
| 12834 | |
| 12835 // Unsigned pointer compare Instructions | |
| 12836 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 12837 match(Set cr (CmpP op1 op2)); | |
| 12838 | |
| 12839 format %{ "CMPu $op1,$op2" %} | |
| 12840 opcode(0x3B); /* Opcode 3B /r */ | |
| 12841 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12842 ins_pipe( ialu_cr_reg_reg ); | |
| 12843 %} | |
| 12844 | |
| 12845 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 12846 match(Set cr (CmpP op1 op2)); | |
| 12847 | |
| 12848 format %{ "CMPu $op1,$op2" %} | |
| 12849 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12850 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12851 ins_pipe( ialu_cr_reg_imm ); | |
| 12852 %} | |
| 12853 | |
| 12854 // // Cisc-spilled version of cmpP_eReg | |
| 12855 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 12856 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12857 | |
| 12858 format %{ "CMPu $op1,$op2" %} | |
| 12859 ins_cost(500); | |
| 12860 opcode(0x3B); /* Opcode 3B /r */ | |
| 12861 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12862 ins_pipe( ialu_cr_reg_mem ); | |
| 12863 %} | |
| 12864 | |
| 12865 // // Cisc-spilled version of cmpP_eReg | |
| 12866 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 12867 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 12868 // | |
| 12869 // format %{ "CMPu $op1,$op2" %} | |
| 12870 // ins_cost(500); | |
| 12871 // opcode(0x39); /* Opcode 39 /r */ | |
| 12872 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12873 //%} | |
| 12874 | |
| 12875 // Compare raw pointer (used in out-of-heap check). | |
| 12876 // Only works because non-oop pointers must be raw pointers | |
| 12877 // and raw pointers have no anti-dependencies. | |
| 12878 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
| 12879 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); | |
| 12880 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12881 | |
| 12882 format %{ "CMPu $op1,$op2" %} | |
| 12883 opcode(0x3B); /* Opcode 3B /r */ | |
| 12884 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12885 ins_pipe( ialu_cr_reg_mem ); | |
| 12886 %} | |
| 12887 | |
| 12888 // | |
| 12889 // This will generate a signed flags result. This should be ok | |
| 12890 // since any compare to a zero should be eq/neq. | |
| 12891 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 12892 match(Set cr (CmpP src zero)); | |
| 12893 | |
| 12894 format %{ "TEST $src,$src" %} | |
| 12895 opcode(0x85); | |
| 12896 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12897 ins_pipe( ialu_cr_reg_imm ); | |
| 12898 %} | |
| 12899 | |
| 12900 // Cisc-spilled version of testP_reg | |
| 12901 // This will generate a signed flags result. This should be ok | |
| 12902 // since any compare to a zero should be eq/neq. | |
| 12903 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12904 match(Set cr (CmpP (LoadP op) zero)); | |
| 12905 | |
| 12906 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12907 ins_cost(500); | |
| 12908 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12909 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12910 ins_pipe( ialu_cr_reg_imm ); | |
| 12911 %} | |
| 12912 | |
| 12913 // Yanked all unsigned pointer compare operations. | |
| 12914 // Pointer compares are done with CmpP which is already unsigned. | |
| 12915 | |
| 12916 //----------Max and Min-------------------------------------------------------- | |
| 12917 // Min Instructions | |
| 12918 //// | |
| 12919 // *** Min and Max using the conditional move are slower than the | |
| 12920 // *** branch version on a Pentium III. | |
| 12921 // // Conditional move for min | |
| 12922 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12923 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12924 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12925 // opcode(0x4C,0x0F); | |
| 12926 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12927 // ins_pipe( pipe_cmov_reg ); | |
| 12928 //%} | |
| 12929 // | |
| 12930 //// Min Register with Register (P6 version) | |
| 12931 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12932 // predicate(VM_Version::supports_cmov() ); | |
| 12933 // match(Set op2 (MinI op1 op2)); | |
| 12934 // ins_cost(200); | |
| 12935 // expand %{ | |
| 12936 // eFlagsReg cr; | |
| 12937 // compI_eReg(cr,op1,op2); | |
| 12938 // cmovI_reg_lt(op2,op1,cr); | |
| 12939 // %} | |
| 12940 //%} | |
| 12941 | |
| 12942 // Min Register with Register (generic version) | |
| 12943 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12944 match(Set dst (MinI dst src)); | |
| 12945 effect(KILL flags); | |
| 12946 ins_cost(300); | |
| 12947 | |
| 12948 format %{ "MIN $dst,$src" %} | |
| 12949 opcode(0xCC); | |
| 12950 ins_encode( min_enc(dst,src) ); | |
| 12951 ins_pipe( pipe_slow ); | |
| 12952 %} | |
| 12953 | |
| 12954 // Max Register with Register | |
| 12955 // *** Min and Max using the conditional move are slower than the | |
| 12956 // *** branch version on a Pentium III. | |
| 12957 // // Conditional move for max | |
| 12958 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12959 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12960 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12961 // opcode(0x4F,0x0F); | |
| 12962 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12963 // ins_pipe( pipe_cmov_reg ); | |
| 12964 //%} | |
| 12965 // | |
| 12966 // // Max Register with Register (P6 version) | |
| 12967 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12968 // predicate(VM_Version::supports_cmov() ); | |
| 12969 // match(Set op2 (MaxI op1 op2)); | |
| 12970 // ins_cost(200); | |
| 12971 // expand %{ | |
| 12972 // eFlagsReg cr; | |
| 12973 // compI_eReg(cr,op1,op2); | |
| 12974 // cmovI_reg_gt(op2,op1,cr); | |
| 12975 // %} | |
| 12976 //%} | |
| 12977 | |
| 12978 // Max Register with Register (generic version) | |
| 12979 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12980 match(Set dst (MaxI dst src)); | |
| 12981 effect(KILL flags); | |
| 12982 ins_cost(300); | |
| 12983 | |
| 12984 format %{ "MAX $dst,$src" %} | |
| 12985 opcode(0xCC); | |
| 12986 ins_encode( max_enc(dst,src) ); | |
| 12987 ins_pipe( pipe_slow ); | |
| 12988 %} | |
| 12989 | |
| 12990 // ============================================================================ | |
| 3345 | 12991 // Counted Loop limit node which represents exact final iterator value. |
| 12992 // Note: the resulting value should fit into integer range since | |
| 12993 // counted loops have limit check on overflow. | |
| 12994 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 12995 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 12996 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 12997 ins_cost(300); | |
| 12998 | |
| 12999 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 13000 ins_encode %{ | |
| 13001 int strd = (int)$stride$$constant; | |
| 13002 assert(strd != 1 && strd != -1, "sanity"); | |
| 13003 int m1 = (strd > 0) ? 1 : -1; | |
| 13004 // Convert limit to long (EAX:EDX) | |
| 13005 __ cdql(); | |
| 13006 // Convert init to long (init:tmp) | |
| 13007 __ movl($tmp$$Register, $init$$Register); | |
| 13008 __ sarl($tmp$$Register, 31); | |
| 13009 // $limit - $init | |
| 13010 __ subl($limit$$Register, $init$$Register); | |
| 13011 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 13012 // + ($stride - 1) | |
| 13013 if (strd > 0) { | |
| 13014 __ addl($limit$$Register, (strd - 1)); | |
| 13015 __ adcl($limit_hi$$Register, 0); | |
| 13016 __ movl($tmp$$Register, strd); | |
| 13017 } else { | |
| 13018 __ addl($limit$$Register, (strd + 1)); | |
| 13019 __ adcl($limit_hi$$Register, -1); | |
| 13020 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 13021 __ movl($tmp$$Register, -strd); | |
| 13022 } | |
| 13023 // signed devision: (EAX:EDX) / pos_stride | |
| 13024 __ idivl($tmp$$Register); | |
| 13025 if (strd < 0) { | |
| 13026 // restore sign | |
| 13027 __ negl($tmp$$Register); | |
| 13028 } | |
| 13029 // (EAX) * stride | |
| 13030 __ mull($tmp$$Register); | |
| 13031 // + init (ignore upper bits) | |
| 13032 __ addl($limit$$Register, $init$$Register); | |
| 13033 %} | |
| 13034 ins_pipe( pipe_slow ); | |
| 13035 %} | |
| 13036 | |
| 13037 // ============================================================================ | |
| 0 | 13038 // Branch Instructions |
| 13039 // Jump Table | |
| 13040 instruct jumpXtnd(eRegI switch_val) %{ | |
| 13041 match(Jump switch_val); | |
| 13042 ins_cost(350); | |
| 2008 | 13043 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 13044 ins_encode %{ | |
| 0 | 13045 // Jump to Address(table_base + switch_reg) |
| 13046 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 13047 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 13048 %} |
| 13049 ins_pipe(pipe_jmp); | |
| 13050 %} | |
| 13051 | |
| 13052 // Jump Direct - Label defines a relative address from JMP+1 | |
| 13053 instruct jmpDir(label labl) %{ | |
| 13054 match(Goto); | |
| 13055 effect(USE labl); | |
| 13056 | |
| 13057 ins_cost(300); | |
| 13058 format %{ "JMP $labl" %} | |
| 13059 size(5); | |
| 13060 opcode(0xE9); | |
| 13061 ins_encode( OpcP, Lbl( labl ) ); | |
| 13062 ins_pipe( pipe_jmp ); | |
| 13063 %} | |
| 13064 | |
| 13065 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13066 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13067 match(If cop cr); | |
| 13068 effect(USE labl); | |
| 13069 | |
| 13070 ins_cost(300); | |
| 13071 format %{ "J$cop $labl" %} | |
| 13072 size(6); | |
| 13073 opcode(0x0F, 0x80); | |
| 13074 ins_encode( Jcc( cop, labl) ); | |
| 13075 ins_pipe( pipe_jcc ); | |
| 13076 %} | |
| 13077 | |
| 13078 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13079 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13080 match(CountedLoopEnd cop cr); | |
| 13081 effect(USE labl); | |
| 13082 | |
| 13083 ins_cost(300); | |
| 13084 format %{ "J$cop $labl\t# Loop end" %} | |
| 13085 size(6); | |
| 13086 opcode(0x0F, 0x80); | |
| 13087 ins_encode( Jcc( cop, labl) ); | |
| 13088 ins_pipe( pipe_jcc ); | |
| 13089 %} | |
| 13090 | |
| 13091 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13092 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13093 match(CountedLoopEnd cop cmp); | |
| 13094 effect(USE labl); | |
| 13095 | |
| 13096 ins_cost(300); | |
| 13097 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 13098 size(6); | |
| 13099 opcode(0x0F, 0x80); | |
| 13100 ins_encode( Jcc( cop, labl) ); | |
| 13101 ins_pipe( pipe_jcc ); | |
| 13102 %} | |
| 13103 | |
|
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13104 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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13105 match(CountedLoopEnd cop cmp); |
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13106 effect(USE labl); |
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13107 |
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13108 ins_cost(200); |
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13109 format %{ "J$cop,u $labl\t# Loop end" %} |
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13110 size(6); |
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13111 opcode(0x0F, 0x80); |
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13112 ins_encode( Jcc( cop, labl) ); |
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13113 ins_pipe( pipe_jcc ); |
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13114 %} |
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13115 |
| 0 | 13116 // Jump Direct Conditional - using unsigned comparison |
| 13117 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13118 match(If cop cmp); | |
| 13119 effect(USE labl); | |
| 13120 | |
| 13121 ins_cost(300); | |
| 13122 format %{ "J$cop,u $labl" %} | |
| 13123 size(6); | |
| 13124 opcode(0x0F, 0x80); | |
|
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13125 ins_encode(Jcc(cop, labl)); |
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13126 ins_pipe(pipe_jcc); |
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13127 %} |
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13128 |
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13129 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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13130 match(If cop cmp); |
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13131 effect(USE labl); |
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13132 |
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13133 ins_cost(200); |
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13134 format %{ "J$cop,u $labl" %} |
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13135 size(6); |
|
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13136 opcode(0x0F, 0x80); |
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13137 ins_encode(Jcc(cop, labl)); |
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13138 ins_pipe(pipe_jcc); |
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13139 %} |
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13140 |
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13141 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
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13142 match(If cop cmp); |
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13143 effect(USE labl); |
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13144 |
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13145 ins_cost(200); |
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|
13146 format %{ $$template |
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13147 if ($cop$$cmpcode == Assembler::notEqual) { |
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13148 $$emit$$"JP,u $labl\n\t" |
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13149 $$emit$$"J$cop,u $labl" |
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13150 } else { |
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13151 $$emit$$"JP,u done\n\t" |
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13152 $$emit$$"J$cop,u $labl\n\t" |
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13153 $$emit$$"done:" |
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13154 } |
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13155 %} |
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13156 size(12); |
|
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13157 opcode(0x0F, 0x80); |
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13158 ins_encode %{ |
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13159 Label* l = $labl$$label; |
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13160 $$$emit8$primary; |
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13161 emit_cc(cbuf, $secondary, Assembler::parity); |
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13162 int parity_disp = -1; |
|
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13163 bool ok = false; |
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13164 if ($cop$$cmpcode == Assembler::notEqual) { |
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13165 // the two jumps 6 bytes apart so the jump distances are too |
| 3839 | 13166 parity_disp = l->loc_pos() - (cbuf.insts_size() + 4); |
|
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13167 } else if ($cop$$cmpcode == Assembler::equal) { |
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13168 parity_disp = 6; |
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13169 ok = true; |
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13170 } else { |
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13171 ShouldNotReachHere(); |
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13172 } |
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13173 emit_d32(cbuf, parity_disp); |
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13174 $$$emit8$primary; |
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13175 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
| 3839 | 13176 int disp = l->loc_pos() - (cbuf.insts_size() + 4); |
|
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13177 emit_d32(cbuf, disp); |
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13178 %} |
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|
13179 ins_pipe(pipe_jcc); |
| 0 | 13180 %} |
| 13181 | |
| 13182 // ============================================================================ | |
| 13183 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 13184 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 13185 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 13186 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 13187 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 13188 match(Set result (PartialSubtypeCheck sub super)); | |
| 13189 effect( KILL rcx, KILL cr ); | |
| 13190 | |
| 13191 ins_cost(1100); // slightly larger than the next version | |
|
644
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|
13192 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 13193 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 13194 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 13195 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 13196 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 13197 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 13198 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 13199 "miss:\t" %} | |
| 13200 | |
| 13201 opcode(0x1); // Force a XOR of EDI | |
| 13202 ins_encode( enc_PartialSubtypeCheck() ); | |
| 13203 ins_pipe( pipe_slow ); | |
| 13204 %} | |
| 13205 | |
| 13206 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 13207 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 13208 effect( KILL rcx, KILL result ); | |
| 13209 | |
| 13210 ins_cost(1000); | |
|
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|
13211 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 13212 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 13213 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 13214 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 13215 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 13216 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 13217 "miss:\t" %} | |
| 13218 | |
| 13219 opcode(0x0); // No need to XOR EDI | |
| 13220 ins_encode( enc_PartialSubtypeCheck() ); | |
| 13221 ins_pipe( pipe_slow ); | |
| 13222 %} | |
| 13223 | |
| 13224 // ============================================================================ | |
| 13225 // Branch Instructions -- short offset versions | |
| 13226 // | |
| 13227 // These instructions are used to replace jumps of a long offset (the default | |
| 13228 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 13229 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 13230 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 13231 // method in the MachNode which can be used to do in-place replacement of the | |
| 13232 // long variant with the shorter variant. The compiler will determine if a | |
| 13233 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 13234 // specific code section of the file. | |
| 13235 | |
| 13236 // Jump Direct - Label defines a relative address from JMP+1 | |
| 13237 instruct jmpDir_short(label labl) %{ | |
| 13238 match(Goto); | |
| 13239 effect(USE labl); | |
| 13240 | |
| 13241 ins_cost(300); | |
| 13242 format %{ "JMP,s $labl" %} | |
| 13243 size(2); | |
| 13244 opcode(0xEB); | |
| 13245 ins_encode( OpcP, LblShort( labl ) ); | |
| 13246 ins_pipe( pipe_jmp ); | |
| 13247 ins_short_branch(1); | |
| 13248 %} | |
| 13249 | |
| 13250 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13251 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13252 match(If cop cr); | |
| 13253 effect(USE labl); | |
| 13254 | |
| 13255 ins_cost(300); | |
| 13256 format %{ "J$cop,s $labl" %} | |
| 13257 size(2); | |
| 13258 opcode(0x70); | |
| 13259 ins_encode( JccShort( cop, labl) ); | |
| 13260 ins_pipe( pipe_jcc ); | |
| 13261 ins_short_branch(1); | |
| 13262 %} | |
| 13263 | |
| 13264 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13265 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13266 match(CountedLoopEnd cop cr); | |
| 13267 effect(USE labl); | |
| 13268 | |
| 13269 ins_cost(300); | |
|
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|
13270 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 13271 size(2); |
| 13272 opcode(0x70); | |
| 13273 ins_encode( JccShort( cop, labl) ); | |
| 13274 ins_pipe( pipe_jcc ); | |
| 13275 ins_short_branch(1); | |
| 13276 %} | |
| 13277 | |
| 13278 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13279 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13280 match(CountedLoopEnd cop cmp); | |
| 13281 effect(USE labl); | |
| 13282 | |
| 13283 ins_cost(300); | |
|
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13284 format %{ "J$cop,us $labl\t# Loop end" %} |
|
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13285 size(2); |
|
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|
13286 opcode(0x70); |
|
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|
13287 ins_encode( JccShort( cop, labl) ); |
|
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|
13288 ins_pipe( pipe_jcc ); |
|
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13289 ins_short_branch(1); |
|
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|
13290 %} |
|
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|
13291 |
|
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|
13292 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13293 match(CountedLoopEnd cop cmp); |
|
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13294 effect(USE labl); |
|
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|
13295 |
|
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|
13296 ins_cost(300); |
|
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|
13297 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 13298 size(2); |
| 13299 opcode(0x70); | |
| 13300 ins_encode( JccShort( cop, labl) ); | |
| 13301 ins_pipe( pipe_jcc ); | |
| 13302 ins_short_branch(1); | |
| 13303 %} | |
| 13304 | |
| 13305 // Jump Direct Conditional - using unsigned comparison | |
| 13306 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13307 match(If cop cmp); | |
| 13308 effect(USE labl); | |
| 13309 | |
| 13310 ins_cost(300); | |
| 13311 format %{ "J$cop,us $labl" %} | |
| 13312 size(2); | |
| 13313 opcode(0x70); | |
| 13314 ins_encode( JccShort( cop, labl) ); | |
| 13315 ins_pipe( pipe_jcc ); | |
| 13316 ins_short_branch(1); | |
| 13317 %} | |
| 13318 | |
|
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13319 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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13320 match(If cop cmp); |
|
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|
13321 effect(USE labl); |
|
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13322 |
|
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|
13323 ins_cost(300); |
|
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|
13324 format %{ "J$cop,us $labl" %} |
|
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|
13325 size(2); |
|
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|
13326 opcode(0x70); |
|
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|
13327 ins_encode( JccShort( cop, labl) ); |
|
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|
13328 ins_pipe( pipe_jcc ); |
|
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|
13329 ins_short_branch(1); |
|
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|
13330 %} |
|
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|
13331 |
|
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|
13332 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13333 match(If cop cmp); |
|
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|
13334 effect(USE labl); |
|
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|
13335 |
|
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|
13336 ins_cost(300); |
|
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|
13337 format %{ $$template |
|
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|
13338 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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13339 $$emit$$"JP,u,s $labl\n\t" |
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13340 $$emit$$"J$cop,u,s $labl" |
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13341 } else { |
|
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|
13342 $$emit$$"JP,u,s done\n\t" |
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13343 $$emit$$"J$cop,u,s $labl\n\t" |
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13344 $$emit$$"done:" |
|
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|
13345 } |
|
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|
13346 %} |
|
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|
13347 size(4); |
|
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|
13348 opcode(0x70); |
|
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|
13349 ins_encode %{ |
|
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|
13350 Label* l = $labl$$label; |
|
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13351 emit_cc(cbuf, $primary, Assembler::parity); |
|
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|
13352 int parity_disp = -1; |
|
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|
13353 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3839 | 13354 parity_disp = l->loc_pos() - (cbuf.insts_size() + 1); |
|
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13355 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
13356 parity_disp = 2; |
|
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|
13357 } else { |
|
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|
13358 ShouldNotReachHere(); |
|
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|
13359 } |
|
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|
13360 emit_d8(cbuf, parity_disp); |
|
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|
13361 emit_cc(cbuf, $primary, $cop$$cmpcode); |
| 3839 | 13362 int disp = l->loc_pos() - (cbuf.insts_size() + 1); |
|
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|
13363 emit_d8(cbuf, disp); |
|
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|
13364 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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|
13365 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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|
13366 %} |
|
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|
13367 ins_pipe(pipe_jcc); |
|
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|
13368 ins_short_branch(1); |
|
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|
13369 %} |
|
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|
13370 |
| 0 | 13371 // ============================================================================ |
| 13372 // Long Compare | |
| 13373 // | |
| 13374 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 13375 // is tricky. The flavor of compare used depends on whether we are testing | |
| 13376 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 13377 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 13378 // the operands (yielding a GE test) and then negating; negate again for the | |
| 13379 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 13380 // NE test is negated from that. | |
| 13381 | |
| 13382 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 13383 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 13384 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 13385 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 13386 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 13387 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 13388 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 13389 // both forms beat the trinary form of long-compare and both are very useful | |
| 13390 // on Intel which has so few registers. | |
| 13391 | |
| 13392 // Manifest a CmpL result in an integer register. Very painful. | |
| 13393 // This is the test to avoid. | |
| 13394 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 13395 match(Set dst (CmpL3 src1 src2)); | |
| 13396 effect( KILL flags ); | |
| 13397 ins_cost(1000); | |
| 13398 format %{ "XOR $dst,$dst\n\t" | |
| 13399 "CMP $src1.hi,$src2.hi\n\t" | |
| 13400 "JLT,s m_one\n\t" | |
| 13401 "JGT,s p_one\n\t" | |
| 13402 "CMP $src1.lo,$src2.lo\n\t" | |
| 13403 "JB,s m_one\n\t" | |
| 13404 "JEQ,s done\n" | |
| 13405 "p_one:\tINC $dst\n\t" | |
| 13406 "JMP,s done\n" | |
| 13407 "m_one:\tDEC $dst\n" | |
| 13408 "done:" %} | |
| 13409 ins_encode %{ | |
| 13410 Label p_one, m_one, done; | |
| 304 | 13411 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 13412 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 13413 __ jccb(Assembler::less, m_one); | |
| 13414 __ jccb(Assembler::greater, p_one); | |
| 13415 __ cmpl($src1$$Register, $src2$$Register); | |
| 13416 __ jccb(Assembler::below, m_one); | |
| 13417 __ jccb(Assembler::equal, done); | |
| 13418 __ bind(p_one); | |
| 304 | 13419 __ incrementl($dst$$Register); |
| 0 | 13420 __ jmpb(done); |
| 13421 __ bind(m_one); | |
| 304 | 13422 __ decrementl($dst$$Register); |
| 0 | 13423 __ bind(done); |
| 13424 %} | |
| 13425 ins_pipe( pipe_slow ); | |
| 13426 %} | |
| 13427 | |
| 13428 //====== | |
| 13429 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13430 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13431 // NOT GOOD FOR EQ/NE tests. | |
| 13432 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 13433 match( Set flags (CmpL src zero )); | |
| 13434 ins_cost(100); | |
| 13435 format %{ "TEST $src.hi,$src.hi" %} | |
| 13436 opcode(0x85); | |
| 13437 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 13438 ins_pipe( ialu_cr_reg_reg ); | |
| 13439 %} | |
| 13440 | |
| 13441 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13442 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13443 // NOT GOOD FOR EQ/NE tests. | |
| 13444 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13445 match( Set flags (CmpL src1 src2 )); | |
| 13446 effect( TEMP tmp ); | |
| 13447 ins_cost(300); | |
| 13448 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13449 "MOV $tmp,$src1.hi\n\t" | |
| 13450 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 13451 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 13452 ins_pipe( ialu_cr_reg_reg ); | |
| 13453 %} | |
| 13454 | |
| 13455 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13456 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13457 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 13458 match(If cmp flags); | |
| 13459 effect(USE labl); | |
| 13460 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13461 expand %{ | |
| 13462 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 13463 %} | |
| 13464 %} | |
| 13465 | |
| 13466 // Compare 2 longs and CMOVE longs. | |
| 13467 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 13468 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13469 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13470 ins_cost(400); | |
| 13471 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13472 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13473 opcode(0x0F,0x40); | |
| 13474 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13475 ins_pipe( pipe_cmov_reg_long ); | |
| 13476 %} | |
| 13477 | |
| 13478 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 13479 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13480 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13481 ins_cost(500); | |
| 13482 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13483 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13484 opcode(0x0F,0x40); | |
| 13485 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13486 ins_pipe( pipe_cmov_reg_long ); | |
| 13487 %} | |
| 13488 | |
| 13489 // Compare 2 longs and CMOVE ints. | |
| 13490 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ | |
| 13491 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13492 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13493 ins_cost(200); | |
| 13494 format %{ "CMOV$cmp $dst,$src" %} | |
| 13495 opcode(0x0F,0x40); | |
| 13496 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13497 ins_pipe( pipe_cmov_reg ); | |
| 13498 %} | |
| 13499 | |
| 13500 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ | |
| 13501 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13502 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13503 ins_cost(250); | |
| 13504 format %{ "CMOV$cmp $dst,$src" %} | |
| 13505 opcode(0x0F,0x40); | |
| 13506 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13507 ins_pipe( pipe_cmov_mem ); | |
| 13508 %} | |
| 13509 | |
| 13510 // Compare 2 longs and CMOVE ints. | |
| 13511 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 13512 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13513 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13514 ins_cost(200); | |
| 13515 format %{ "CMOV$cmp $dst,$src" %} | |
| 13516 opcode(0x0F,0x40); | |
| 13517 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13518 ins_pipe( pipe_cmov_reg ); | |
| 13519 %} | |
| 13520 | |
| 13521 // Compare 2 longs and CMOVE doubles | |
| 13522 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ | |
| 13523 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13524 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13525 ins_cost(200); | |
| 13526 expand %{ | |
| 13527 fcmovD_regS(cmp,flags,dst,src); | |
| 13528 %} | |
| 13529 %} | |
| 13530 | |
| 13531 // Compare 2 longs and CMOVE doubles | |
| 13532 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ | |
| 13533 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13534 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13535 ins_cost(200); | |
| 13536 expand %{ | |
| 13537 fcmovXD_regS(cmp,flags,dst,src); | |
| 13538 %} | |
| 13539 %} | |
| 13540 | |
| 13541 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
| 13542 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13543 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13544 ins_cost(200); | |
| 13545 expand %{ | |
| 13546 fcmovF_regS(cmp,flags,dst,src); | |
| 13547 %} | |
| 13548 %} | |
| 13549 | |
| 13550 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ | |
| 13551 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13552 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13553 ins_cost(200); | |
| 13554 expand %{ | |
| 13555 fcmovX_regS(cmp,flags,dst,src); | |
| 13556 %} | |
| 13557 %} | |
| 13558 | |
| 13559 //====== | |
| 13560 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13561 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13562 match( Set flags (CmpL src zero )); | |
| 13563 effect(TEMP tmp); | |
| 13564 ins_cost(200); | |
| 13565 format %{ "MOV $tmp,$src.lo\n\t" | |
| 13566 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 13567 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 13568 ins_pipe( ialu_reg_reg_long ); | |
| 13569 %} | |
| 13570 | |
| 13571 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13572 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 13573 match( Set flags (CmpL src1 src2 )); | |
| 13574 ins_cost(200+300); | |
| 13575 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13576 "JNE,s skip\n\t" | |
| 13577 "CMP $src1.hi,$src2.hi\n\t" | |
| 13578 "skip:\t" %} | |
| 13579 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 13580 ins_pipe( ialu_cr_reg_reg ); | |
| 13581 %} | |
| 13582 | |
| 13583 // Long compare reg == zero/reg OR reg != zero/reg | |
| 13584 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13585 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 13586 match(If cmp flags); | |
| 13587 effect(USE labl); | |
| 13588 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13589 expand %{ | |
| 13590 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 13591 %} | |
| 13592 %} | |
| 13593 | |
| 13594 // Compare 2 longs and CMOVE longs. | |
| 13595 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 13596 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13597 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13598 ins_cost(400); | |
| 13599 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13600 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13601 opcode(0x0F,0x40); | |
| 13602 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13603 ins_pipe( pipe_cmov_reg_long ); | |
| 13604 %} | |
| 13605 | |
| 13606 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 13607 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13608 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13609 ins_cost(500); | |
| 13610 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13611 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13612 opcode(0x0F,0x40); | |
| 13613 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13614 ins_pipe( pipe_cmov_reg_long ); | |
| 13615 %} | |
| 13616 | |
| 13617 // Compare 2 longs and CMOVE ints. | |
| 13618 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ | |
| 13619 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13620 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13621 ins_cost(200); | |
| 13622 format %{ "CMOV$cmp $dst,$src" %} | |
| 13623 opcode(0x0F,0x40); | |
| 13624 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13625 ins_pipe( pipe_cmov_reg ); | |
| 13626 %} | |
| 13627 | |
| 13628 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ | |
| 13629 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13630 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13631 ins_cost(250); | |
| 13632 format %{ "CMOV$cmp $dst,$src" %} | |
| 13633 opcode(0x0F,0x40); | |
| 13634 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13635 ins_pipe( pipe_cmov_mem ); | |
| 13636 %} | |
| 13637 | |
| 13638 // Compare 2 longs and CMOVE ints. | |
| 13639 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 13640 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13641 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13642 ins_cost(200); | |
| 13643 format %{ "CMOV$cmp $dst,$src" %} | |
| 13644 opcode(0x0F,0x40); | |
| 13645 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13646 ins_pipe( pipe_cmov_reg ); | |
| 13647 %} | |
| 13648 | |
| 13649 // Compare 2 longs and CMOVE doubles | |
| 13650 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ | |
| 13651 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13652 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13653 ins_cost(200); | |
| 13654 expand %{ | |
| 13655 fcmovD_regS(cmp,flags,dst,src); | |
| 13656 %} | |
| 13657 %} | |
| 13658 | |
| 13659 // Compare 2 longs and CMOVE doubles | |
| 13660 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ | |
| 13661 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13662 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13663 ins_cost(200); | |
| 13664 expand %{ | |
| 13665 fcmovXD_regS(cmp,flags,dst,src); | |
| 13666 %} | |
| 13667 %} | |
| 13668 | |
| 13669 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
| 13670 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13671 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13672 ins_cost(200); | |
| 13673 expand %{ | |
| 13674 fcmovF_regS(cmp,flags,dst,src); | |
| 13675 %} | |
| 13676 %} | |
| 13677 | |
| 13678 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ | |
| 13679 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13680 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13681 ins_cost(200); | |
| 13682 expand %{ | |
| 13683 fcmovX_regS(cmp,flags,dst,src); | |
| 13684 %} | |
| 13685 %} | |
| 13686 | |
| 13687 //====== | |
| 13688 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13689 // Same as cmpL_reg_flags_LEGT except must negate src | |
| 13690 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13691 match( Set flags (CmpL src zero )); | |
| 13692 effect( TEMP tmp ); | |
| 13693 ins_cost(300); | |
| 13694 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 13695 "CMP $tmp,$src.lo\n\t" | |
| 13696 "SBB $tmp,$src.hi\n\t" %} | |
| 13697 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 13698 ins_pipe( ialu_reg_reg_long ); | |
| 13699 %} | |
| 13700 | |
| 13701 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13702 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 13703 // requires a commuted test to get the same result. | |
| 13704 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13705 match( Set flags (CmpL src1 src2 )); | |
| 13706 effect( TEMP tmp ); | |
| 13707 ins_cost(300); | |
| 13708 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 13709 "MOV $tmp,$src2.hi\n\t" | |
| 13710 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 13711 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 13712 ins_pipe( ialu_cr_reg_reg ); | |
| 13713 %} | |
| 13714 | |
| 13715 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13716 // Just a wrapper for a normal branch, plus the predicate test | |
| 13717 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 13718 match(If cmp flags); | |
| 13719 effect(USE labl); | |
| 13720 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 13721 ins_cost(300); | |
| 13722 expand %{ | |
| 13723 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 13724 %} | |
| 13725 %} | |
| 13726 | |
| 13727 // Compare 2 longs and CMOVE longs. | |
| 13728 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 13729 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13730 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13731 ins_cost(400); | |
| 13732 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13733 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13734 opcode(0x0F,0x40); | |
| 13735 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13736 ins_pipe( pipe_cmov_reg_long ); | |
| 13737 %} | |
| 13738 | |
| 13739 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 13740 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13741 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13742 ins_cost(500); | |
| 13743 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13744 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 13745 opcode(0x0F,0x40); | |
| 13746 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13747 ins_pipe( pipe_cmov_reg_long ); | |
| 13748 %} | |
| 13749 | |
| 13750 // Compare 2 longs and CMOVE ints. | |
| 13751 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ | |
| 13752 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13753 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13754 ins_cost(200); | |
| 13755 format %{ "CMOV$cmp $dst,$src" %} | |
| 13756 opcode(0x0F,0x40); | |
| 13757 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13758 ins_pipe( pipe_cmov_reg ); | |
| 13759 %} | |
| 13760 | |
| 13761 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ | |
| 13762 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13763 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13764 ins_cost(250); | |
| 13765 format %{ "CMOV$cmp $dst,$src" %} | |
| 13766 opcode(0x0F,0x40); | |
| 13767 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13768 ins_pipe( pipe_cmov_mem ); | |
| 13769 %} | |
| 13770 | |
| 13771 // Compare 2 longs and CMOVE ptrs. | |
| 13772 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 13773 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13774 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13775 ins_cost(200); | |
| 13776 format %{ "CMOV$cmp $dst,$src" %} | |
| 13777 opcode(0x0F,0x40); | |
| 13778 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13779 ins_pipe( pipe_cmov_reg ); | |
| 13780 %} | |
| 13781 | |
| 13782 // Compare 2 longs and CMOVE doubles | |
| 13783 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ | |
| 13784 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13785 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13786 ins_cost(200); | |
| 13787 expand %{ | |
| 13788 fcmovD_regS(cmp,flags,dst,src); | |
| 13789 %} | |
| 13790 %} | |
| 13791 | |
| 13792 // Compare 2 longs and CMOVE doubles | |
| 13793 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ | |
| 13794 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13795 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13796 ins_cost(200); | |
| 13797 expand %{ | |
| 13798 fcmovXD_regS(cmp,flags,dst,src); | |
| 13799 %} | |
| 13800 %} | |
| 13801 | |
| 13802 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
| 13803 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13804 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13805 ins_cost(200); | |
| 13806 expand %{ | |
| 13807 fcmovF_regS(cmp,flags,dst,src); | |
| 13808 %} | |
| 13809 %} | |
| 13810 | |
| 13811 | |
| 13812 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ | |
| 13813 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13814 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13815 ins_cost(200); | |
| 13816 expand %{ | |
| 13817 fcmovX_regS(cmp,flags,dst,src); | |
| 13818 %} | |
| 13819 %} | |
| 13820 | |
| 13821 | |
| 13822 // ============================================================================ | |
| 13823 // Procedure Call/Return Instructions | |
| 13824 // Call Java Static Instruction | |
| 13825 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13826 // compute_padding() functions will have to be adjusted. | |
| 13827 instruct CallStaticJavaDirect(method meth) %{ | |
| 13828 match(CallStaticJava); | |
|
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13829 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 13830 effect(USE meth); |
| 13831 | |
| 13832 ins_cost(300); | |
| 13833 format %{ "CALL,static " %} | |
| 13834 opcode(0xE8); /* E8 cd */ | |
| 13835 ins_encode( pre_call_FPU, | |
| 13836 Java_Static_Call( meth ), | |
| 13837 call_epilog, | |
| 13838 post_call_FPU ); | |
| 13839 ins_pipe( pipe_slow ); | |
| 13840 ins_alignment(4); | |
| 13841 %} | |
| 13842 | |
|
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13843 // Call Java Static Instruction (method handle version) |
|
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13844 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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13845 // compute_padding() functions will have to be adjusted. |
| 1567 | 13846 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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13847 match(CallStaticJava); |
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13848 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
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13849 effect(USE meth); |
|
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13850 // EBP is saved by all callees (for interpreter stack correction). |
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13851 // We use it here for a similar purpose, in {preserve,restore}_SP. |
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13852 |
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13853 ins_cost(300); |
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13854 format %{ "CALL,static/MethodHandle " %} |
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13855 opcode(0xE8); /* E8 cd */ |
|
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13856 ins_encode( pre_call_FPU, |
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13857 preserve_SP, |
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13858 Java_Static_Call( meth ), |
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13859 restore_SP, |
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13860 call_epilog, |
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13861 post_call_FPU ); |
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13862 ins_pipe( pipe_slow ); |
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13863 ins_alignment(4); |
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13864 %} |
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13865 |
| 0 | 13866 // Call Java Dynamic Instruction |
| 13867 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13868 // compute_padding() functions will have to be adjusted. | |
| 13869 instruct CallDynamicJavaDirect(method meth) %{ | |
| 13870 match(CallDynamicJava); | |
| 13871 effect(USE meth); | |
| 13872 | |
| 13873 ins_cost(300); | |
| 13874 format %{ "MOV EAX,(oop)-1\n\t" | |
| 13875 "CALL,dynamic" %} | |
| 13876 opcode(0xE8); /* E8 cd */ | |
| 13877 ins_encode( pre_call_FPU, | |
| 13878 Java_Dynamic_Call( meth ), | |
| 13879 call_epilog, | |
| 13880 post_call_FPU ); | |
| 13881 ins_pipe( pipe_slow ); | |
| 13882 ins_alignment(4); | |
| 13883 %} | |
| 13884 | |
| 13885 // Call Runtime Instruction | |
| 13886 instruct CallRuntimeDirect(method meth) %{ | |
| 13887 match(CallRuntime ); | |
| 13888 effect(USE meth); | |
| 13889 | |
| 13890 ins_cost(300); | |
| 13891 format %{ "CALL,runtime " %} | |
| 13892 opcode(0xE8); /* E8 cd */ | |
| 13893 // Use FFREEs to clear entries in float stack | |
| 13894 ins_encode( pre_call_FPU, | |
| 13895 FFree_Float_Stack_All, | |
| 13896 Java_To_Runtime( meth ), | |
| 13897 post_call_FPU ); | |
| 13898 ins_pipe( pipe_slow ); | |
| 13899 %} | |
| 13900 | |
| 13901 // Call runtime without safepoint | |
| 13902 instruct CallLeafDirect(method meth) %{ | |
| 13903 match(CallLeaf); | |
| 13904 effect(USE meth); | |
| 13905 | |
| 13906 ins_cost(300); | |
| 13907 format %{ "CALL_LEAF,runtime " %} | |
| 13908 opcode(0xE8); /* E8 cd */ | |
| 13909 ins_encode( pre_call_FPU, | |
| 13910 FFree_Float_Stack_All, | |
| 13911 Java_To_Runtime( meth ), | |
| 13912 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13913 ins_pipe( pipe_slow ); | |
| 13914 %} | |
| 13915 | |
| 13916 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13917 match(CallLeafNoFP); | |
| 13918 effect(USE meth); | |
| 13919 | |
| 13920 ins_cost(300); | |
| 13921 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13922 opcode(0xE8); /* E8 cd */ | |
| 13923 ins_encode(Java_To_Runtime(meth)); | |
| 13924 ins_pipe( pipe_slow ); | |
| 13925 %} | |
| 13926 | |
| 13927 | |
| 13928 // Return Instruction | |
| 13929 // Remove the return address & jump to it. | |
| 13930 instruct Ret() %{ | |
| 13931 match(Return); | |
| 13932 format %{ "RET" %} | |
| 13933 opcode(0xC3); | |
| 13934 ins_encode(OpcP); | |
| 13935 ins_pipe( pipe_jmp ); | |
| 13936 %} | |
| 13937 | |
| 13938 // Tail Call; Jump from runtime stub to Java code. | |
| 13939 // Also known as an 'interprocedural jump'. | |
| 13940 // Target of jump will eventually return to caller. | |
| 13941 // TailJump below removes the return address. | |
| 13942 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13943 match(TailCall jump_target method_oop ); | |
| 13944 ins_cost(300); | |
| 13945 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13946 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13947 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13948 ins_pipe( pipe_jmp ); | |
| 13949 %} | |
| 13950 | |
| 13951 | |
| 13952 // Tail Jump; remove the return address; jump to target. | |
| 13953 // TailCall above leaves the return address around. | |
| 13954 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13955 match( TailJump jump_target ex_oop ); | |
| 13956 ins_cost(300); | |
| 13957 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13958 "JMP $jump_target " %} | |
| 13959 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13960 ins_encode( enc_pop_rdx, | |
| 13961 OpcP, RegOpc(jump_target) ); | |
| 13962 ins_pipe( pipe_jmp ); | |
| 13963 %} | |
| 13964 | |
| 13965 // Create exception oop: created by stack-crawling runtime code. | |
| 13966 // Created exception is now available to this handler, and is setup | |
| 13967 // just prior to jumping to this handler. No code emitted. | |
| 13968 instruct CreateException( eAXRegP ex_oop ) | |
| 13969 %{ | |
| 13970 match(Set ex_oop (CreateEx)); | |
| 13971 | |
| 13972 size(0); | |
| 13973 // use the following format syntax | |
| 13974 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13975 ins_encode(); | |
| 13976 ins_pipe( empty ); | |
| 13977 %} | |
| 13978 | |
| 13979 | |
| 13980 // Rethrow exception: | |
| 13981 // The exception oop will come in the first argument position. | |
| 13982 // Then JUMP (not call) to the rethrow stub code. | |
| 13983 instruct RethrowException() | |
| 13984 %{ | |
| 13985 match(Rethrow); | |
| 13986 | |
| 13987 // use the following format syntax | |
| 13988 format %{ "JMP rethrow_stub" %} | |
| 13989 ins_encode(enc_rethrow); | |
| 13990 ins_pipe( pipe_jmp ); | |
| 13991 %} | |
| 13992 | |
| 13993 // inlined locking and unlocking | |
| 13994 | |
| 13995 | |
| 13996 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ | |
| 13997 match( Set cr (FastLock object box) ); | |
| 13998 effect( TEMP tmp, TEMP scr ); | |
| 13999 ins_cost(300); | |
| 14000 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} | |
| 14001 ins_encode( Fast_Lock(object,box,tmp,scr) ); | |
| 14002 ins_pipe( pipe_slow ); | |
| 14003 %} | |
| 14004 | |
| 14005 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 14006 match( Set cr (FastUnlock object box) ); | |
| 14007 effect( TEMP tmp ); | |
| 14008 ins_cost(300); | |
| 14009 format %{ "FASTUNLOCK $object, $box, $tmp" %} | |
| 14010 ins_encode( Fast_Unlock(object,box,tmp) ); | |
| 14011 ins_pipe( pipe_slow ); | |
| 14012 %} | |
| 14013 | |
| 14014 | |
| 14015 | |
| 14016 // ============================================================================ | |
| 14017 // Safepoint Instruction | |
| 14018 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 14019 match(SafePoint); | |
| 14020 effect(KILL cr); | |
| 14021 | |
| 14022 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 14023 // On SPARC that might be acceptable as we can generate the address with | |
| 14024 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 14025 // putting additional pressure on the index-0 in the D$. Because of | |
| 14026 // alignment (just like the situation at hand) the lower indices tend | |
| 14027 // to see more traffic. It'd be better to change the polling address | |
| 14028 // to offset 0 of the last $line in the polling page. | |
| 14029 | |
| 14030 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 14031 ins_cost(125); | |
| 14032 size(6) ; | |
| 14033 ins_encode( Safepoint_Poll() ); | |
| 14034 ins_pipe( ialu_reg_mem ); | |
| 14035 %} | |
| 14036 | |
| 14037 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 14038 // These must follow all instruction definitions as they use the names | |
| 14039 // defined in the instructions definitions. | |
| 14040 // | |
| 605 | 14041 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 14042 // |
| 14043 // peepconstraint %{ | |
| 14044 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 14045 // [, ...] ); | |
| 14046 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 14047 // | |
| 14048 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 14049 // // provide an instruction_number.operand_name for each operand that appears | |
| 14050 // // in the replacement instruction's match rule | |
| 14051 // | |
| 14052 // ---------VM FLAGS--------------------------------------------------------- | |
| 14053 // | |
| 14054 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 14055 // | |
| 14056 // Each peephole rule is given an identifying number starting with zero and | |
| 14057 // increasing by one in the order seen by the parser. An individual peephole | |
| 14058 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 14059 // on the command-line. | |
| 14060 // | |
| 14061 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 14062 // | |
| 14063 // Only match adjacent instructions in same basic block | |
| 14064 // Only equality constraints | |
| 14065 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 14066 // Only one replacement instruction | |
| 14067 // | |
| 14068 // ---------EXAMPLE---------------------------------------------------------- | |
| 14069 // | |
| 14070 // // pertinent parts of existing instructions in architecture description | |
| 14071 // instruct movI(eRegI dst, eRegI src) %{ | |
| 14072 // match(Set dst (CopyI src)); | |
| 14073 // %} | |
| 14074 // | |
| 14075 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 14076 // match(Set dst (AddI dst src)); | |
| 14077 // effect(KILL cr); | |
| 14078 // %} | |
| 14079 // | |
| 14080 // // Change (inc mov) to lea | |
| 14081 // peephole %{ | |
| 14082 // // increment preceeded by register-register move | |
| 14083 // peepmatch ( incI_eReg movI ); | |
| 14084 // // require that the destination register of the increment | |
| 14085 // // match the destination register of the move | |
| 14086 // peepconstraint ( 0.dst == 1.dst ); | |
| 14087 // // construct a replacement instruction that sets | |
| 14088 // // the destination to ( move's source register + one ) | |
| 14089 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14090 // %} | |
| 14091 // | |
| 14092 // Implementation no longer uses movX instructions since | |
| 14093 // machine-independent system no longer uses CopyX nodes. | |
| 14094 // | |
| 14095 // peephole %{ | |
| 14096 // peepmatch ( incI_eReg movI ); | |
| 14097 // peepconstraint ( 0.dst == 1.dst ); | |
| 14098 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14099 // %} | |
| 14100 // | |
| 14101 // peephole %{ | |
| 14102 // peepmatch ( decI_eReg movI ); | |
| 14103 // peepconstraint ( 0.dst == 1.dst ); | |
| 14104 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14105 // %} | |
| 14106 // | |
| 14107 // peephole %{ | |
| 14108 // peepmatch ( addI_eReg_imm movI ); | |
| 14109 // peepconstraint ( 0.dst == 1.dst ); | |
| 14110 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14111 // %} | |
| 14112 // | |
| 14113 // peephole %{ | |
| 14114 // peepmatch ( addP_eReg_imm movP ); | |
| 14115 // peepconstraint ( 0.dst == 1.dst ); | |
| 14116 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14117 // %} | |
| 14118 | |
| 14119 // // Change load of spilled value to only a spill | |
| 14120 // instruct storeI(memory mem, eRegI src) %{ | |
| 14121 // match(Set mem (StoreI mem src)); | |
| 14122 // %} | |
| 14123 // | |
| 14124 // instruct loadI(eRegI dst, memory mem) %{ | |
| 14125 // match(Set dst (LoadI mem)); | |
| 14126 // %} | |
| 14127 // | |
| 14128 peephole %{ | |
| 14129 peepmatch ( loadI storeI ); | |
| 14130 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 14131 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 14132 %} | |
| 14133 | |
| 14134 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 14135 // These must follow all instruction definitions as they use the names | |
| 14136 // defined in the instructions definitions. |