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comparison src/cpu/x86/vm/vm_version_x86.cpp @ 1730:f55c4f82ab9d

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6978249: spill between cpu and fpu registers when those moves are fast Reviewed-by: kvn
author never
date Thu, 19 Aug 2010 14:51:47 -0700
parents 76efbe666d6c
children 3e8fbc61cee8
comparison
equal deleted inserted replaced
1729:13b87063b4d8 1730:f55c4f82ab9d
480 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 480 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
481 UsePopCountInstruction = true; 481 UsePopCountInstruction = true;
482 } 482 }
483 } 483 }
484 484
485 #ifdef COMPILER2
486 if (UseFPUForSpilling) {
487 if (UseSSE < 2) {
488 // Only supported with SSE2+
489 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
490 }
491 }
492 #endif
493
485 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); 494 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
486 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); 495 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
487 496
488 // set valid Prefetch instruction 497 // set valid Prefetch instruction
489 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; 498 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
518 #endif 527 #endif
519 } 528 }
520 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus 529 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
521 AllocatePrefetchDistance = 192; 530 AllocatePrefetchDistance = 192;
522 AllocatePrefetchLines = 4; 531 AllocatePrefetchLines = 4;
532 #ifdef COMPILER2
533 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
534 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
535 }
536 #endif
523 } 537 }
524 } 538 }
525 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); 539 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
526 540
527 #ifdef _LP64 541 #ifdef _LP64