Mercurial > hg > truffle
comparison src/cpu/x86/vm/icache_x86.hpp @ 1972:f95d63e2154a
6989984: Use standard include model for Hospot
Summary: Replaced MakeDeps and the includeDB files with more standardized solutions.
Reviewed-by: coleenp, kvn, kamg
author | stefank |
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date | Tue, 23 Nov 2010 13:22:55 -0800 |
parents | c18cbe5936b8 |
children | 6ae7a1561b53 |
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1971:e33f46fc48ed | 1972:f95d63e2154a |
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1 /* | 1 /* |
2 * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved. | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | 4 * |
5 * This code is free software; you can redistribute it and/or modify it | 5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as | 6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. | 7 * published by the Free Software Foundation. |
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
20 * or visit www.oracle.com if you need additional information or have any | 20 * or visit www.oracle.com if you need additional information or have any |
21 * questions. | 21 * questions. |
22 * | 22 * |
23 */ | 23 */ |
24 | |
25 #ifndef CPU_X86_VM_ICACHE_X86_HPP | |
26 #define CPU_X86_VM_ICACHE_X86_HPP | |
24 | 27 |
25 // Interface for updating the instruction cache. Whenever the VM modifies | 28 // Interface for updating the instruction cache. Whenever the VM modifies |
26 // code, part of the processor instruction cache potentially has to be flushed. | 29 // code, part of the processor instruction cache potentially has to be flushed. |
27 | 30 |
28 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent | 31 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent |
51 line_size = BytesPerWord, // conservative | 54 line_size = BytesPerWord, // conservative |
52 log2_line_size = LogBytesPerWord // log2(line_size) | 55 log2_line_size = LogBytesPerWord // log2(line_size) |
53 }; | 56 }; |
54 #endif // AMD64 | 57 #endif // AMD64 |
55 }; | 58 }; |
59 | |
60 #endif // CPU_X86_VM_ICACHE_X86_HPP |