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annotate src/cpu/x86/vm/icache_x86.hpp @ 1972:f95d63e2154a
6989984: Use standard include model for Hospot
Summary: Replaced MakeDeps and the includeDB files with more standardized solutions.
Reviewed-by: coleenp, kvn, kamg
| author | stefank |
|---|---|
| date | Tue, 23 Nov 2010 13:22:55 -0800 |
| parents | c18cbe5936b8 |
| children | 6ae7a1561b53 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1972 | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_ICACHE_X86_HPP |
| 26 #define CPU_X86_VM_ICACHE_X86_HPP | |
| 27 | |
| 0 | 28 // Interface for updating the instruction cache. Whenever the VM modifies |
| 29 // code, part of the processor instruction cache potentially has to be flushed. | |
| 30 | |
| 31 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent | |
| 32 // after the next jump, and the VM never modifies instructions directly ahead | |
| 33 // of the instruction fetch path. | |
| 34 | |
| 35 // [phh] It's not clear that the above comment is correct, because on an MP | |
| 36 // system where the dcaches are not snooped, only the thread doing the invalidate | |
| 37 // will see the update. Even in the snooped case, a memory fence would be | |
| 38 // necessary if stores weren't ordered. Fortunately, they are on all known | |
| 39 // x86 implementations. | |
| 40 | |
| 41 class ICache : public AbstractICache { | |
| 42 public: | |
| 43 #ifdef AMD64 | |
| 44 enum { | |
| 45 stub_size = 64, // Size of the icache flush stub in bytes | |
| 46 line_size = 32, // Icache line size in bytes | |
| 47 log2_line_size = 5 // log2(line_size) | |
| 48 }; | |
| 49 | |
| 50 // Use default implementation | |
| 51 #else | |
| 52 enum { | |
| 53 stub_size = 16, // Size of the icache flush stub in bytes | |
| 54 line_size = BytesPerWord, // conservative | |
| 55 log2_line_size = LogBytesPerWord // log2(line_size) | |
| 56 }; | |
| 57 #endif // AMD64 | |
| 58 }; | |
| 1972 | 59 |
| 60 #endif // CPU_X86_VM_ICACHE_X86_HPP |