Mercurial > hg > truffle
changeset 4254:1cf920630944
Canonicalize parameter lists and names
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--- a/graal/com.oracle.max.cri/src/com/oracle/max/cri/ci/CiValueUtil.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.cri/src/com/oracle/max/cri/ci/CiValueUtil.java Tue Jan 10 08:50:07 2012 -0800 @@ -98,4 +98,27 @@ assert value.kind == CiKind.Double; return asRegister(value); } + + + public static boolean sameRegister(CiValue...values) { + for (int i = 0; i < values.length; i++) { + for (int j = i + 1; j < values.length; j++) { + if (isRegister(values[i]) && isRegister(values[j]) && asRegister(values[i]) != asRegister(values[j])) { + return false; + } + } + } + return true; + } + + public static boolean differentRegisters(CiValue...values) { + for (int i = 0; i < values.length; i++) { + for (int j = i + 1; j < values.length; j++) { + if (isRegister(values[i]) && isRegister(values[j]) && asRegister(values[i]) == asRegister(values[j])) { + return false; + } + } + } + return true; + } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/lir/LIRCall.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/lir/LIRCall.java Tue Jan 10 08:50:07 2012 -0800 @@ -78,14 +78,6 @@ this.target = target; } - public RiMethod method() { - return (RiMethod) target; - } - - public CiRuntimeCall runtimeCall() { - return (CiRuntimeCall) target; - } - public CiValue targetAddress() { if (targetAddressIndex >= 0) { return input(targetAddressIndex);
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ArithmeticOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ArithmeticOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -38,22 +38,20 @@ FADD, FSUB, FMUL, FDIV, DADD, DSUB, DMUL, DDIV; - public LIRInstruction create(Variable result, CiValue left, CiValue right) { - assert (name().startsWith("I") && result.kind == CiKind.Int && left.kind.stackKind() == CiKind.Int && right.kind.stackKind() == CiKind.Int) - || (name().startsWith("L") && result.kind == CiKind.Long && left.kind == CiKind.Long && right.kind == CiKind.Long) - || (name().startsWith("F") && result.kind == CiKind.Float && left.kind == CiKind.Float && right.kind == CiKind.Float) - || (name().startsWith("D") && result.kind == CiKind.Double && left.kind == CiKind.Double && right.kind == CiKind.Double); + public LIRInstruction create(CiValue result, CiValue x, CiValue y) { + assert (name().startsWith("I") && result.kind == CiKind.Int && x.kind.stackKind() == CiKind.Int && y.kind.stackKind() == CiKind.Int) + || (name().startsWith("L") && result.kind == CiKind.Long && x.kind == CiKind.Long && y.kind == CiKind.Long) + || (name().startsWith("F") && result.kind == CiKind.Float && x.kind == CiKind.Float && y.kind == CiKind.Float) + || (name().startsWith("D") && result.kind == CiKind.Double && x.kind == CiKind.Double && y.kind == CiKind.Double); - CiValue[] inputs = new CiValue[] {left}; - CiValue[] alives = new CiValue[] {right}; + CiValue[] inputs = new CiValue[] {x}; + CiValue[] alives = new CiValue[] {y}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, alives, LIRInstruction.NO_OPERANDS) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - assert !(alive(0) instanceof CiRegisterValue) || asRegister(output(0)) != asRegister(alive(0)) : "result and right must be different registers"; - AMD64MoveOpcode.move(tasm, masm, output(0), input(0)); - emit(tasm, masm, output(0), alive(0)); + emit(tasm, masm, output(0), input(0), alive(0)); } @Override @@ -70,10 +68,13 @@ }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue leftAndResult, CiValue right) { - CiRegister dst = asRegister(leftAndResult); - if (isRegister(right)) { - CiRegister rreg = asRegister(right); + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x, CiValue y) { + assert sameRegister(x, y) || differentRegisters(result, y); + AMD64MoveOpcode.move(tasm, masm, result, x); + + CiRegister dst = asRegister(result); + if (isRegister(y)) { + CiRegister rreg = asRegister(y); switch (this) { case IADD: masm.addl(dst, rreg); break; case ISUB: masm.subl(dst, rreg); break; @@ -95,30 +96,30 @@ case DDIV: masm.divsd(dst, rreg); break; default: throw Util.shouldNotReachHere(); } - } else if (isConstant(right)) { + } else if (isConstant(y)) { switch (this) { - case IADD: masm.incrementl(dst, tasm.asIntConst(right)); break; - case ISUB: masm.decrementl(dst, tasm.asIntConst(right)); break; - case IAND: masm.andl(dst, tasm.asIntConst(right)); break; - case IOR: masm.orl(dst, tasm.asIntConst(right)); break; - case IXOR: masm.xorl(dst, tasm.asIntConst(right)); break; - case LADD: masm.addq(dst, tasm.asIntConst(right)); break; - case LSUB: masm.subq(dst, tasm.asIntConst(right)); break; - case LAND: masm.andq(dst, tasm.asIntConst(right)); break; - case LOR: masm.orq(dst, tasm.asIntConst(right)); break; - case LXOR: masm.xorq(dst, tasm.asIntConst(right)); break; - case FADD: masm.addss(dst, tasm.asFloatConstRef(right)); break; - case FSUB: masm.subss(dst, tasm.asFloatConstRef(right)); break; - case FMUL: masm.mulss(dst, tasm.asFloatConstRef(right)); break; - case FDIV: masm.divss(dst, tasm.asFloatConstRef(right)); break; - case DADD: masm.addsd(dst, tasm.asDoubleConstRef(right)); break; - case DSUB: masm.subsd(dst, tasm.asDoubleConstRef(right)); break; - case DMUL: masm.mulsd(dst, tasm.asDoubleConstRef(right)); break; - case DDIV: masm.divsd(dst, tasm.asDoubleConstRef(right)); break; + case IADD: masm.incrementl(dst, tasm.asIntConst(y)); break; + case ISUB: masm.decrementl(dst, tasm.asIntConst(y)); break; + case IAND: masm.andl(dst, tasm.asIntConst(y)); break; + case IOR: masm.orl(dst, tasm.asIntConst(y)); break; + case IXOR: masm.xorl(dst, tasm.asIntConst(y)); break; + case LADD: masm.addq(dst, tasm.asIntConst(y)); break; + case LSUB: masm.subq(dst, tasm.asIntConst(y)); break; + case LAND: masm.andq(dst, tasm.asIntConst(y)); break; + case LOR: masm.orq(dst, tasm.asIntConst(y)); break; + case LXOR: masm.xorq(dst, tasm.asIntConst(y)); break; + case FADD: masm.addss(dst, tasm.asFloatConstRef(y)); break; + case FSUB: masm.subss(dst, tasm.asFloatConstRef(y)); break; + case FMUL: masm.mulss(dst, tasm.asFloatConstRef(y)); break; + case FDIV: masm.divss(dst, tasm.asFloatConstRef(y)); break; + case DADD: masm.addsd(dst, tasm.asDoubleConstRef(y)); break; + case DSUB: masm.subsd(dst, tasm.asDoubleConstRef(y)); break; + case DMUL: masm.mulsd(dst, tasm.asDoubleConstRef(y)); break; + case DDIV: masm.divsd(dst, tasm.asDoubleConstRef(y)); break; default: throw Util.shouldNotReachHere(); } } else { - CiAddress raddr = tasm.asAddress(right); + CiAddress raddr = tasm.asAddress(y); switch (this) { case IADD: masm.addl(dst, raddr); break; case ISUB: masm.subl(dst, raddr); break;
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64CompareOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64CompareOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -35,14 +35,14 @@ public enum AMD64CompareOpcode implements LIROpcode { ICMP, LCMP, ACMP, FCMP, DCMP; - public LIRInstruction create(Variable left, CiValue right) { - assert (name().startsWith("I") && left.kind == CiKind.Int && right.kind.stackKind() == CiKind.Int) - || (name().startsWith("I") && left.kind == CiKind.Jsr && right.kind == CiKind.Jsr) - || (name().startsWith("L") && left.kind == CiKind.Long && right.kind == CiKind.Long) - || (name().startsWith("A") && left.kind == CiKind.Object && right.kind == CiKind.Object) - || (name().startsWith("F") && left.kind == CiKind.Float && right.kind == CiKind.Float) - || (name().startsWith("D") && left.kind == CiKind.Double && right.kind == CiKind.Double) : "left.kind=" + left.kind + ", right.kind=" + right.kind; - CiValue[] inputs = new CiValue[] {left, right}; + public LIRInstruction create(CiValue x, CiValue y) { + assert (name().startsWith("I") && x.kind == CiKind.Int && y.kind.stackKind() == CiKind.Int) + || (name().startsWith("I") && x.kind == CiKind.Jsr && y.kind == CiKind.Jsr) + || (name().startsWith("L") && x.kind == CiKind.Long && y.kind == CiKind.Long) + || (name().startsWith("A") && x.kind == CiKind.Object && y.kind == CiKind.Object) + || (name().startsWith("F") && x.kind == CiKind.Float && y.kind == CiKind.Float) + || (name().startsWith("D") && x.kind == CiKind.Double && y.kind == CiKind.Double); + CiValue[] inputs = new CiValue[] {x, y}; return new AMD64LIRInstruction(this, LIRInstruction.NO_OPERANDS, null, inputs, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS) { @Override @@ -60,10 +60,10 @@ }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue left, CiValue right) { - CiRegister lreg = asRegister(left); - if (isRegister(right)) { - CiRegister rreg = asRegister(right); + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue x, CiValue y) { + CiRegister lreg = asRegister(x); + if (isRegister(y)) { + CiRegister rreg = asRegister(y); switch (this) { case ICMP: masm.cmpl(lreg, rreg); break; case LCMP: masm.cmpq(lreg, rreg); break; @@ -72,22 +72,22 @@ case DCMP: masm.ucomisd(lreg, rreg); break; default: throw Util.shouldNotReachHere(); } - } else if (isConstant(right)) { + } else if (isConstant(y)) { switch (this) { - case ICMP: masm.cmpl(lreg, tasm.asIntConst(right)); break; - case LCMP: masm.cmpq(lreg, tasm.asIntConst(right)); break; + case ICMP: masm.cmpl(lreg, tasm.asIntConst(y)); break; + case LCMP: masm.cmpq(lreg, tasm.asIntConst(y)); break; case ACMP: - if (((CiConstant) right).isNull()) { + if (((CiConstant) y).isNull()) { masm.cmpq(lreg, 0); break; } else { throw Util.shouldNotReachHere("Only null object constants are allowed in comparisons"); } - case FCMP: masm.ucomiss(lreg, tasm.asFloatConstRef(right)); break; - case DCMP: masm.ucomisd(lreg, tasm.asDoubleConstRef(right)); break; + case FCMP: masm.ucomiss(lreg, tasm.asFloatConstRef(y)); break; + case DCMP: masm.ucomisd(lreg, tasm.asDoubleConstRef(y)); break; default: throw Util.shouldNotReachHere(); } } else { - CiAddress raddr = tasm.asAddress(right); + CiAddress raddr = tasm.asAddress(y); switch (this) { case ICMP: masm.cmpl(lreg, raddr); break; case LCMP: masm.cmpq(lreg, raddr); break;
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64CompareToIntOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64CompareToIntOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -40,7 +40,7 @@ public enum AMD64CompareToIntOpcode implements LIROpcode { CMP2INT, CMP2INT_UG, CMP2INT_UL; - public LIRInstruction create(Variable result) { + public LIRInstruction create(CiValue result) { CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS) {
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertFIOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertFIOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -36,8 +36,8 @@ public enum AMD64ConvertFIOpcode implements LIROpcode { F2I, D2I; - public LIRInstruction create(Variable result, final CompilerStub stub, Variable input) { - CiValue[] inputs = new CiValue[] {input}; + public LIRInstruction create(CiValue result, final CompilerStub stub, CiValue x) { + CiValue[] inputs = new CiValue[] {x}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS) { @@ -48,17 +48,17 @@ }; } - private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CompilerStub stub, CiValue input) { + private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CompilerStub stub, CiValue x) { switch (this) { - case F2I: masm.cvttss2sil(asIntReg(result), asFloatReg(input)); break; - case D2I: masm.cvttsd2sil(asIntReg(result), asDoubleReg(input)); break; + case F2I: masm.cvttss2sil(asIntReg(result), asFloatReg(x)); break; + case D2I: masm.cvttsd2sil(asIntReg(result), asDoubleReg(x)); break; default: throw Util.shouldNotReachHere(); } Label endLabel = new Label(); masm.cmp32(asIntReg(result), Integer.MIN_VALUE); masm.jcc(ConditionFlag.notEqual, endLabel); - AMD64CallOpcode.callStub(tasm, masm, stub, null, result, input); + AMD64CallOpcode.callStub(tasm, masm, stub, null, result, x); masm.bind(endLabel); } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertFLOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertFLOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -36,8 +36,8 @@ public enum AMD64ConvertFLOpcode implements LIROpcode { F2L, D2L; - public LIRInstruction create(Variable result, final CompilerStub stub, Variable input, Variable scratch) { - CiValue[] inputs = new CiValue[] {input}; + public LIRInstruction create(CiValue result, final CompilerStub stub, CiValue x, CiValue scratch) { + CiValue[] inputs = new CiValue[] {x}; CiValue[] temps = new CiValue[] {scratch}; CiValue[] outputs = new CiValue[] {result}; @@ -49,12 +49,14 @@ }; } - private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CompilerStub stub, CiValue input, CiValue scratch) { + private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CompilerStub stub, CiValue x, CiValue scratch) { + assert differentRegisters(result, scratch); + CiRegister dst = asLongReg(result); CiRegister tmp = asLongReg(scratch); switch (this) { - case F2L: masm.cvttss2siq(dst, asFloatReg(input)); break; - case D2L: masm.cvttsd2siq(dst, asDoubleReg(input)); break; + case F2L: masm.cvttss2siq(dst, asFloatReg(x)); break; + case D2L: masm.cvttsd2siq(dst, asDoubleReg(x)); break; default: throw Util.shouldNotReachHere(); } @@ -62,7 +64,7 @@ masm.movq(tmp, java.lang.Long.MIN_VALUE); masm.cmpq(dst, tmp); masm.jcc(ConditionFlag.notEqual, endLabel); - AMD64CallOpcode.callStub(tasm, masm, stub, null, result, input); + AMD64CallOpcode.callStub(tasm, masm, stub, null, result, x); masm.bind(endLabel); } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ConvertOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -39,8 +39,8 @@ L2F, L2D, MOV_I2F, MOV_L2D, MOV_F2I, MOV_D2L; - public LIRInstruction create(Variable result, Variable input) { - CiValue[] inputs = new CiValue[] {input}; + public LIRInstruction create(CiValue result, CiValue x) { + CiValue[] inputs = new CiValue[] {x}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS) { @@ -59,35 +59,35 @@ }; } - private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue input) { + private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x) { switch (this) { case L2I: - AMD64MoveOpcode.move(tasm, masm, result, input); + AMD64MoveOpcode.move(tasm, masm, result, x); masm.andl(asIntReg(result), 0xFFFFFFFF); break; case I2B: - AMD64MoveOpcode.move(tasm, masm, result, input); + AMD64MoveOpcode.move(tasm, masm, result, x); masm.signExtendByte(asIntReg(result)); break; case I2C: - AMD64MoveOpcode.move(tasm, masm, result, input); + AMD64MoveOpcode.move(tasm, masm, result, x); masm.andl(asIntReg(result), 0xFFFF); break; case I2S: - AMD64MoveOpcode.move(tasm, masm, result, input); + AMD64MoveOpcode.move(tasm, masm, result, x); masm.signExtendShort(asIntReg(result)); break; - case I2L: masm.movslq(asLongReg(result), asIntReg(input)); break; - case F2D: masm.cvtss2sd(asDoubleReg(result), asFloatReg(input)); break; - case D2F: masm.cvtsd2ss(asFloatReg(result), asDoubleReg(input)); break; - case I2F: masm.cvtsi2ssl(asFloatReg(result), asIntReg(input)); break; - case I2D: masm.cvtsi2sdl(asDoubleReg(result), asIntReg(input)); break; - case L2F: masm.cvtsi2ssq(asFloatReg(result), asLongReg(input)); break; - case L2D: masm.cvtsi2sdq(asDoubleReg(result), asLongReg(input)); break; - case MOV_I2F: masm.movdl(asFloatReg(result), asIntReg(input)); break; - case MOV_L2D: masm.movdq(asDoubleReg(result), asLongReg(input)); break; - case MOV_F2I: masm.movdl(asIntReg(result), asFloatReg(input)); break; - case MOV_D2L: masm.movdq(asLongReg(result), asDoubleReg(input)); break; + case I2L: masm.movslq(asLongReg(result), asIntReg(x)); break; + case F2D: masm.cvtss2sd(asDoubleReg(result), asFloatReg(x)); break; + case D2F: masm.cvtsd2ss(asFloatReg(result), asDoubleReg(x)); break; + case I2F: masm.cvtsi2ssl(asFloatReg(result), asIntReg(x)); break; + case I2D: masm.cvtsi2sdl(asDoubleReg(result), asIntReg(x)); break; + case L2F: masm.cvtsi2ssq(asFloatReg(result), asLongReg(x)); break; + case L2D: masm.cvtsi2sdq(asDoubleReg(result), asLongReg(x)); break; + case MOV_I2F: masm.movdl(asFloatReg(result), asIntReg(x)); break; + case MOV_L2D: masm.movdq(asDoubleReg(result), asLongReg(x)); break; + case MOV_F2I: masm.movdl(asIntReg(result), asFloatReg(x)); break; + case MOV_D2L: masm.movdq(asLongReg(result), asDoubleReg(x)); break; default: throw Util.shouldNotReachHere(); } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64DivOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64DivOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -33,28 +33,28 @@ import com.oracle.max.graal.compiler.util.*; public enum AMD64DivOpcode implements LIROpcode { - IDIV, IREM, UIDIV, UIREM, - LDIV, LREM, ULDIV, ULREM; + IDIV, IREM, IUDIV, IUREM, + LDIV, LREM, LUDIV, LUREM; - public LIRInstruction create(CiRegisterValue result, LIRDebugInfo info, CiRegisterValue left, Variable right) { - CiValue[] inputs = new CiValue[] {left}; - CiValue[] alives = new CiValue[] {right}; - CiValue[] temps = new CiValue[] {result.reg == AMD64.rax ? AMD64.rdx.asValue(result.kind) : AMD64.rax.asValue(result.kind)}; + public LIRInstruction create(CiValue result, LIRDebugInfo info, CiValue x, CiValue y) { + CiValue[] inputs = new CiValue[] {x}; + CiValue[] alives = new CiValue[] {y}; + CiValue[] temps = new CiValue[] {asRegister(result) == AMD64.rax ? AMD64.rdx.asValue(result.kind) : AMD64.rax.asValue(result.kind)}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, info, inputs, alives, temps) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - emit(tasm, masm, asRegister(output(0)), info, asRegister(input(0)), asRegister(alive(0))); + emit(tasm, masm, output(0), info, input(0), alive(0)); } }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiRegister result, LIRDebugInfo info, CiRegister left, CiRegister right) { + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, LIRDebugInfo info, CiValue x, CiValue y) { // left input in rax, right input in any register but rax and rdx, result quotient in rax, result remainder in rdx - assert left == AMD64.rax; - assert right != AMD64.rax && right != AMD64.rdx; - assert (name().endsWith("DIV") && result == AMD64.rax) || (name().endsWith("REM") && result == AMD64.rdx); + assert asRegister(x) == AMD64.rax; + assert differentRegisters(y, AMD64.rax.asValue(), AMD64.rdx.asValue()); + assert (name().endsWith("DIV") && asRegister(result) == AMD64.rax) || (name().endsWith("REM") && asRegister(result) == AMD64.rdx); int exceptionOffset; switch (this) { @@ -62,7 +62,7 @@ case IREM: masm.cdql(); exceptionOffset = masm.codeBuffer.position(); - masm.idivl(right); + masm.idivl(asRegister(y)); break; case LDIV: @@ -74,31 +74,31 @@ masm.movq(AMD64.rdx, java.lang.Long.MIN_VALUE); masm.cmpq(AMD64.rax, AMD64.rdx); masm.jcc(ConditionFlag.notEqual, normalCase); - masm.cmpl(right, -1); + masm.cmpl(asRegister(y), -1); masm.jcc(ConditionFlag.equal, continuation); masm.bind(normalCase); } masm.cdqq(); exceptionOffset = masm.codeBuffer.position(); - masm.idivq(right); + masm.idivq(asRegister(y)); masm.bind(continuation); break; - case UIDIV: - case UIREM: + case IUDIV: + case IUREM: // Must zero the high 64-bit word (in RDX) of the dividend masm.xorq(AMD64.rdx, AMD64.rdx); exceptionOffset = masm.codeBuffer.position(); - masm.divl(right); + masm.divl(asRegister(y)); break; - case ULDIV: - case ULREM: + case LUDIV: + case LUREM: // Must zero the high 64-bit word (in RDX) of the dividend masm.xorq(AMD64.rdx, AMD64.rdx); exceptionOffset = masm.codeBuffer.position(); - masm.divq(right); + masm.divq(asRegister(y)); break; default:
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64LIRGenerator.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64LIRGenerator.java Tue Jan 10 08:50:07 2012 -0800 @@ -305,11 +305,11 @@ switch(a.kind) { case Int: append(MOVE.create(RAX_I, load(a))); - append(UIDIV.create(RAX_I, state(), RAX_I, load(b))); + append(IUDIV.create(RAX_I, state(), RAX_I, load(b))); return emitMove(RAX_I); case Long: append(MOVE.create(RAX_L, load(a))); - append(ULDIV.create(RAX_L, state(), RAX_L, load(b))); + append(LUDIV.create(RAX_L, state(), RAX_L, load(b))); return emitMove(RAX_L); default: throw Util.shouldNotReachHere(); @@ -321,11 +321,11 @@ switch(a.kind) { case Int: append(MOVE.create(RAX_I, load(a))); - append(UIREM.create(RDX_I, state(), RAX_I, load(b))); + append(IUREM.create(RDX_I, state(), RAX_I, load(b))); return emitMove(RDX_I); case Long: append(MOVE.create(RAX_L, load(a))); - append(ULREM.create(RDX_L, state(), RAX_L, load(b))); + append(LUREM.create(RDX_L, state(), RAX_L, load(b))); return emitMove(RDX_L); default: throw Util.shouldNotReachHere(); @@ -393,8 +393,8 @@ public Variable emitUShr(CiValue a, CiValue b) { Variable result = newVariable(a.kind); switch (a.kind) { - case Int: append(UISHR.create(result, a, loadShiftCount(b))); break; - case Long: append(ULSHR.create(result, a, loadShiftCount(b))); break; + case Int: append(IUSHR.create(result, a, loadShiftCount(b))); break; + case Long: append(LUSHR.create(result, a, loadShiftCount(b))); break; default: Util.shouldNotReachHere(); } return result;
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64LogicFloatOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64LogicFloatOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -36,20 +36,18 @@ FAND, FOR, FXOR, DAND, DOR, DXOR; - public LIRInstruction create(Variable result, CiValue left, CiValue right) { - assert (name().startsWith("F") && result.kind == CiKind.Float && left.kind == CiKind.Float && right.kind == CiKind.Float) - || (name().startsWith("D") && result.kind == CiKind.Double && left.kind == CiKind.Double && right.kind == CiKind.Double); + public LIRInstruction create(CiValue result, CiValue x, CiValue y) { + assert (name().startsWith("F") && result.kind == CiKind.Float && x.kind == CiKind.Float && y.kind == CiKind.Float) + || (name().startsWith("D") && result.kind == CiKind.Double && x.kind == CiKind.Double && y.kind == CiKind.Double); - CiValue[] inputs = new CiValue[] {left}; - CiValue[] alives = new CiValue[] {right}; + CiValue[] inputs = new CiValue[] {x}; + CiValue[] alives = new CiValue[] {y}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, alives, LIRInstruction.NO_OPERANDS) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - assert !(alive(0) instanceof CiRegisterValue) || asRegister(output(0)) != asRegister(alive(0)) : "result and right must be different registers"; - AMD64MoveOpcode.move(tasm, masm, output(0), input(0)); - emit(tasm, masm, output(0), alive(0)); + emit(tasm, masm, output(0), input(0), alive(0)); } @Override @@ -66,10 +64,13 @@ }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue leftAndResult, CiValue right) { - CiRegister dst = asRegister(leftAndResult); - if (isRegister(right)) { - CiRegister rreg = asRegister(right); + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x, CiValue y) { + assert sameRegister(x, y) || differentRegisters(result, y); + AMD64MoveOpcode.move(tasm, masm, result, x); + + CiRegister dst = asRegister(result); + if (isRegister(y)) { + CiRegister rreg = asRegister(y); switch (this) { case FAND: masm.andps(dst, rreg); break; case FOR: masm.orps(dst, rreg); break; @@ -79,18 +80,16 @@ case DXOR: masm.xorpd(dst, rreg); break; default: throw Util.shouldNotReachHere(); } - } else if (isConstant(right)) { + } else { switch (this) { - case FAND: masm.andps(dst, tasm.asFloatConstRef(right, 16)); break; - case FOR: masm.orps(dst, tasm.asFloatConstRef(right, 16)); break; - case FXOR: masm.xorps(dst, tasm.asFloatConstRef(right, 16)); break; - case DAND: masm.andpd(dst, tasm.asDoubleConstRef(right, 16)); break; - case DOR: masm.orpd(dst, tasm.asDoubleConstRef(right, 16)); break; - case DXOR: masm.xorpd(dst, tasm.asDoubleConstRef(right, 16)); break; + case FAND: masm.andps(dst, tasm.asFloatConstRef(y, 16)); break; + case FOR: masm.orps(dst, tasm.asFloatConstRef(y, 16)); break; + case FXOR: masm.xorps(dst, tasm.asFloatConstRef(y, 16)); break; + case DAND: masm.andpd(dst, tasm.asDoubleConstRef(y, 16)); break; + case DOR: masm.orpd(dst, tasm.asDoubleConstRef(y, 16)); break; + case DXOR: masm.xorpd(dst, tasm.asDoubleConstRef(y, 16)); break; default: throw Util.shouldNotReachHere(); } - } else { - throw Util.shouldNotReachHere(); } } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64MulOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64MulOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -35,17 +35,15 @@ public enum AMD64MulOpcode implements LIROpcode { IMUL, LMUL; - public LIRInstruction create(Variable result, CiValue left, CiValue right) { - CiValue[] inputs = new CiValue[] {left}; - CiValue[] alives = new CiValue[] {right}; + public LIRInstruction create(CiValue result, CiValue x, CiValue y) { + CiValue[] inputs = new CiValue[] {x}; + CiValue[] alives = new CiValue[] {y}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, alives, LIRInstruction.NO_OPERANDS) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - assert !(alive(0) instanceof CiRegisterValue) || asRegister(output(0)) != asRegister(alive(0)) : "result and right must be different registers"; - AMD64MoveOpcode.move(tasm, masm, output(0), input(0)); - emit(tasm, masm, output(0), alive(0)); + emit(tasm, masm, output(0), input(0), alive(0)); } @Override @@ -62,22 +60,23 @@ }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue leftAndResult, CiValue right) { - CiRegister dst = asRegister(leftAndResult); - if (isRegister(right)) { + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x, CiValue y) { + assert sameRegister(x, y) || differentRegisters(result, y); + AMD64MoveOpcode.move(tasm, masm, result, x); + + CiRegister dst = asRegister(result); + if (isRegister(y)) { switch (this) { - case IMUL: masm.imull(dst, asRegister(right)); break; - case LMUL: masm.imulq(dst, asRegister(right)); break; - default: throw Util.shouldNotReachHere(); - } - } else if (isConstant(right)) { - switch (this) { - case IMUL: masm.imull(dst, dst, tasm.asIntConst(right)); break; - case LMUL: masm.imulq(dst, dst, tasm.asIntConst(right)); break; + case IMUL: masm.imull(dst, asRegister(y)); break; + case LMUL: masm.imulq(dst, asRegister(y)); break; default: throw Util.shouldNotReachHere(); } } else { - throw Util.shouldNotReachHere(); + switch (this) { + case IMUL: masm.imull(dst, dst, tasm.asIntConst(y)); break; + case LMUL: masm.imulq(dst, dst, tasm.asIntConst(y)); break; + default: throw Util.shouldNotReachHere(); + } } } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64Op1Opcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64Op1Opcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -35,15 +35,14 @@ public enum AMD64Op1Opcode implements LIROpcode { INEG, LNEG; - public LIRInstruction create(Variable result, CiValue input) { - CiValue[] inputs = new CiValue[] {input}; + public LIRInstruction create(CiValue result, CiValue x) { + CiValue[] inputs = new CiValue[] {x}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - AMD64MoveOpcode.move(tasm, masm, output(0), input(0)); - emit(masm, output(0)); + emit(tasm, masm, output(0), input(0)); } @Override @@ -58,10 +57,11 @@ }; } - private void emit(AMD64MacroAssembler masm, CiValue inputAndResult) { + private void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x) { + AMD64MoveOpcode.move(tasm, masm, result, x); switch (this) { - case INEG: masm.negl(asIntReg(inputAndResult)); break; - case LNEG: masm.negq(asLongReg(inputAndResult)); break; + case INEG: masm.negl(asIntReg(result)); break; + case LNEG: masm.negq(asLongReg(result)); break; default: throw Util.shouldNotReachHere(); } }
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ShiftOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ShiftOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -33,20 +33,18 @@ import com.oracle.max.graal.compiler.util.*; public enum AMD64ShiftOpcode implements LIROpcode { - ISHL, ISHR, UISHR, - LSHL, LSHR, ULSHR; + ISHL, ISHR, IUSHR, + LSHL, LSHR, LUSHR; - public LIRInstruction create(Variable result, CiValue left, CiValue right) { - CiValue[] inputs = new CiValue[] {left}; - CiValue[] alives = new CiValue[] {right}; + public LIRInstruction create(CiValue result, CiValue x, CiValue y) { + CiValue[] inputs = new CiValue[] {x}; + CiValue[] alives = new CiValue[] {y}; CiValue[] outputs = new CiValue[] {result}; return new AMD64LIRInstruction(this, outputs, null, inputs, alives, LIRInstruction.NO_OPERANDS) { @Override public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { - assert !(alive(0) instanceof CiRegisterValue) || asRegister(output(0)) != asRegister(alive(0)) : "result and right must be different registers"; - AMD64MoveOpcode.move(tasm, masm, output(0), input(0)); - emit(tasm, masm, output(0), alive(0)); + emit(tasm, masm, output(0), input(0), alive(0)); } @Override @@ -63,27 +61,30 @@ }; } - protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue leftAndResult, CiValue right) { - CiRegister dst = asRegister(leftAndResult); - if (isRegister(right)) { - assert asRegister(right) == AMD64.rcx; + protected void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x, CiValue y) { + assert sameRegister(x, y) || differentRegisters(result, y); + AMD64MoveOpcode.move(tasm, masm, result, x); + + CiRegister dst = asRegister(result); + if (isRegister(y)) { + assert asRegister(y) == AMD64.rcx; switch (this) { case ISHL: masm.shll(dst); break; case ISHR: masm.sarl(dst); break; - case UISHR: masm.shrl(dst); break; + case IUSHR: masm.shrl(dst); break; case LSHL: masm.shlq(dst); break; case LSHR: masm.sarq(dst); break; - case ULSHR: masm.shrq(dst); break; + case LUSHR: masm.shrq(dst); break; default: throw Util.shouldNotReachHere(); } - } else if (isConstant(right)) { + } else if (isConstant(y)) { switch (this) { - case ISHL: masm.shll(dst, tasm.asIntConst(right) & 31); break; - case ISHR: masm.sarl(dst, tasm.asIntConst(right) & 31); break; - case UISHR: masm.shrl(dst, tasm.asIntConst(right) & 31); break; - case LSHL: masm.shlq(dst, tasm.asIntConst(right) & 63); break; - case LSHR: masm.sarq(dst, tasm.asIntConst(right) & 63); break; - case ULSHR: masm.shrq(dst, tasm.asIntConst(right) & 63); break; + case ISHL: masm.shll(dst, tasm.asIntConst(y) & 31); break; + case ISHR: masm.sarl(dst, tasm.asIntConst(y) & 31); break; + case IUSHR: masm.shrl(dst, tasm.asIntConst(y) & 31); break; + case LSHL: masm.shlq(dst, tasm.asIntConst(y) & 63); break; + case LSHR: masm.sarq(dst, tasm.asIntConst(y) & 63); break; + case LUSHR: masm.shrq(dst, tasm.asIntConst(y) & 63); break; default: throw Util.shouldNotReachHere(); } } else {
--- a/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64XirOpcode.java Mon Jan 09 22:01:39 2012 +0100 +++ b/graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64XirOpcode.java Tue Jan 10 08:50:07 2012 -0800 @@ -154,7 +154,7 @@ break; case Shr: - emitXirViaLir(tasm, masm, AMD64ShiftOpcode.UISHR, AMD64ShiftOpcode.ULSHR, null, null, operands[inst.x().index], operands[inst.y().index], operands[inst.result.index]); + emitXirViaLir(tasm, masm, AMD64ShiftOpcode.IUSHR, AMD64ShiftOpcode.LUSHR, null, null, operands[inst.x().index], operands[inst.y().index], operands[inst.result.index]); break; case And: @@ -531,13 +531,13 @@ } if (code instanceof AMD64ArithmeticOpcode) { - ((AMD64ArithmeticOpcode) code).emit(tasm, masm, left, right); + ((AMD64ArithmeticOpcode) code).emit(tasm, masm, result, left, right); } else if (code instanceof AMD64MulOpcode) { - ((AMD64MulOpcode) code).emit(tasm, masm, left, right); + ((AMD64MulOpcode) code).emit(tasm, masm, result, left, right); } else if (code instanceof AMD64DivOpcode) { - ((AMD64DivOpcode) code).emit(tasm, masm, asRegister(result), null, asRegister(left), asRegister(right)); + ((AMD64DivOpcode) code).emit(tasm, masm, result, null, left, right); } else if (code instanceof AMD64ShiftOpcode) { - ((AMD64ShiftOpcode) code).emit(tasm, masm, left, right); + ((AMD64ShiftOpcode) code).emit(tasm, masm, result, left, right); } }