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changeset 13265:2d76d0c85345

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Make selection of x86 floating point move instruction extensible.
author Roland Schatz <roland.schatz@oracle.com>
date Mon, 09 Dec 2013 13:44:10 +0100
parents b23cbfb4366a
children 78ed696884b3
files graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64MacroAssembler.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java
diffstat 2 files changed, 15 insertions(+), 10 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64MacroAssembler.java	Sun Dec 08 21:55:09 2013 -0800
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64MacroAssembler.java	Mon Dec 09 13:44:10 2013 +0100
@@ -171,7 +171,7 @@
         movsxw(reg, reg);
     }
 
-    public final void movflt(Register dst, Register src) {
+    public void movflt(Register dst, Register src) {
         assert dst.getRegisterCategory() == AMD64.XMM && src.getRegisterCategory() == AMD64.XMM;
         if (UseXmmRegToRegMoveAll) {
             movaps(dst, src);
@@ -180,17 +180,17 @@
         }
     }
 
-    public final void movflt(Register dst, AMD64Address src) {
+    public void movflt(Register dst, AMD64Address src) {
         assert dst.getRegisterCategory() == AMD64.XMM;
         movss(dst, src);
     }
 
-    public final void movflt(AMD64Address dst, Register src) {
+    public void movflt(AMD64Address dst, Register src) {
         assert src.getRegisterCategory() == AMD64.XMM;
         movss(dst, src);
     }
 
-    public final void movdbl(Register dst, Register src) {
+    public void movdbl(Register dst, Register src) {
         assert dst.getRegisterCategory() == AMD64.XMM && src.getRegisterCategory() == AMD64.XMM;
         if (UseXmmRegToRegMoveAll) {
             movapd(dst, src);
@@ -199,7 +199,7 @@
         }
     }
 
-    public final void movdbl(Register dst, AMD64Address src) {
+    public void movdbl(Register dst, AMD64Address src) {
         assert dst.getRegisterCategory() == AMD64.XMM;
         if (UseXmmLoadAndClearUpper) {
             movsd(dst, src);
@@ -208,6 +208,11 @@
         }
     }
 
+    public void movdbl(AMD64Address dst, Register src) {
+        assert src.getRegisterCategory() == AMD64.XMM;
+        movsd(dst, src);
+    }
+
     /**
      * Non-atomic write of a 64-bit constant to memory. Do not use if the address might be a
      * volatile field!
@@ -257,7 +262,7 @@
         assert value.getRegisterCategory() == AMD64.XMM;
         AMD64Address tmp = new AMD64Address(AMD64.rsp);
         subq(AMD64.rsp, target.arch.getSizeInBytes(Kind.Double));
-        movsd(tmp, value);
+        movdbl(tmp, value);
         fldd(tmp);
         return tmp;
     }
@@ -265,7 +270,7 @@
     private void trigEpilogue(Register dest, AMD64Address tmp) {
         assert dest.getRegisterCategory() == AMD64.XMM;
         fstpd(tmp);
-        movsd(dest, tmp);
+        movdbl(dest, tmp);
         addq(AMD64.rsp, target.arch.getSizeInBytes(Kind.Double));
     }
 
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Sun Dec 08 21:55:09 2013 -0800
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Mon Dec 09 13:44:10 2013 +0100
@@ -322,9 +322,9 @@
                 masm.flds(tmp);
             } else {
                 assert opcode == DREM;
-                masm.movsd(tmp, asRegister(y));
+                masm.movdbl(tmp, asRegister(y));
                 masm.fldd(tmp);
-                masm.movsd(tmp, asRegister(x));
+                masm.movdbl(tmp, asRegister(x));
                 masm.fldd(tmp);
             }
 
@@ -343,7 +343,7 @@
                 masm.movflt(asRegister(result), tmp);
             } else {
                 masm.fstpd(tmp);
-                masm.movsd(asRegister(result), tmp);
+                masm.movdbl(asRegister(result), tmp);
             }
             masm.addq(AMD64.rsp, 8);
         }