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changeset 18842:437894ecd7c5

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Fix type error in code generation.
author Roland Schatz <roland.schatz@oracle.com>
date Mon, 12 Jan 2015 18:02:01 +0100
parents f2f2897880c8
children 5e80dd2f1783 f2261069ba99
files graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java
diffstat 1 files changed, 4 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Mon Jan 12 15:56:59 2015 +0100
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Mon Jan 12 18:02:01 2015 +0100
@@ -334,10 +334,10 @@
             if (isRegister(x)) {
                 switch (opcode) {
                     case IMUL:
-                        masm.imull(asIntReg(result), asIntReg(x), y.asInt());
+                        masm.imull(asIntReg(result), asIntReg(x), crb.asIntConst(y));
                         break;
                     case LMUL:
-                        masm.imulq(asLongReg(result), asLongReg(x), y.asInt());
+                        masm.imulq(asLongReg(result), asLongReg(x), crb.asIntConst(y));
                         break;
                     default:
                         throw GraalInternalError.shouldNotReachHere();
@@ -346,10 +346,10 @@
                 assert isStackSlot(x);
                 switch (opcode) {
                     case IMUL:
-                        masm.imull(asIntReg(result), (AMD64Address) crb.asIntAddr(x), y.asInt());
+                        masm.imull(asIntReg(result), (AMD64Address) crb.asIntAddr(x), crb.asIntConst(y));
                         break;
                     case LMUL:
-                        masm.imulq(asLongReg(result), (AMD64Address) crb.asLongAddr(x), y.asInt());
+                        masm.imulq(asLongReg(result), (AMD64Address) crb.asLongAddr(x), crb.asIntConst(y));
                         break;
                     default:
                         throw GraalInternalError.shouldNotReachHere();