--- a/src/cpu/sparc/vm/sparc.ad	Fri Apr 17 14:28:00 2015 +0200
+++ b/src/cpu/sparc/vm/sparc.ad	Fri Apr 17 15:40:26 2015 +0200
@@ -6355,17 +6355,18 @@
   ins_pipe(iload_mem);
 %}
 
-// Use BIS instruction to prefetch for allocation.
+// Use PREFETCHA instruction to prefetch for allocation.
 // Could fault, need space at the end of TLAB.
 instruct prefetchAlloc_bis( iRegP dst ) %{
   predicate(AllocatePrefetchInstr == 1);
   match( PrefetchAllocation dst );
   ins_cost(MEMORY_REF_COST);
   size(4);
-
-  format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
-  ins_encode %{
-    __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
+  // Using prefetcha insteadof stxa. Because stxa does write to the tlab 32 bytes with zero, which leads to an overzero of 
+  // TLAB which triggers assertion error in ThreadLocalAllocBuffer::clear_before_allocation
+  format %{ "PREFETCHA   [$dst] #ASI_BLK_INIT_QUAD_LDD_P, severalWritesAndPossiblyReads\t! // Prefetch allocation using PREFETCHA" %}
+  ins_encode %{
+    __ prefetcha($dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY,  Assembler::severalWritesAndPossiblyReads);
   %}
   ins_pipe(istore_mem_reg);
 %}

--- a/src/share/vm/adlc/Doc/Syntax.doc	Fri Apr 17 14:28:00 2015 +0200
+++ b/src/share/vm/adlc/Doc/Syntax.doc	Fri Apr 17 15:40:26 2015 +0200
@@ -33,7 +33,7 @@
 the architecture of a processor, and is the input to the ADL Compiler.  The
 ADL Compiler compiles an ADL file into code which is incorporated into the
 Optimizing Just In Time Compiler (OJIT) to generate efficient and correct code
-for the target architecture.  The ADL describes three bassic different types
+for the target architecture.  The ADL describes three basic different types
 of architectural features.  It describes the instruction set (and associated
 operands) of the target architecture.  It describes the register set of the
 target architecture along with relevant information for the register allocator.