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changeset 19908:d1b9c58e17ce

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AMD64Assembler: introduce addq(AMD64Address, Register).
author Josef Eisl <josef.eisl@jku.at>
date Mon, 16 Mar 2015 16:35:20 +0100
parents 22b14fba2e99
children 1fed7073f288
files graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java
diffstat 1 files changed, 4 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Tue Mar 17 17:19:39 2015 +0100
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Mon Mar 16 16:35:20 2015 +0100
@@ -1943,6 +1943,10 @@
         ADD.rmOp.emit(this, QWORD, dst, src);
     }
 
+    public final void addq(AMD64Address dst, Register src) {
+        ADD.mrOp.emit(this, QWORD, dst, src);
+    }
+
     public final void andq(Register dst, int imm32) {
         AND.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
     }