SPARCAssembler (Graal OpenJDK Project Documentation)

java.lang.Object
- com.oracle.graal.asm.Assembler
- - com.oracle.graal.asm.sparc.SPARCAssembler

Direct Known Subclasses:

SPARCMacroAssembler
```
public abstract class SPARCAssembler
extends Assembler
```
This class implements an assembler that can encode most SPARC instructions.

Nested Class Summary

Nested Classes
Modifier and Type	Class and Description
`static class`	`SPARCAssembler.Annul`
`static class`	`SPARCAssembler.Asi` Represents the Address Space Identifier defined in the SPARC architecture.
`static class`	`SPARCAssembler.BitKey`
`static class`	`SPARCAssembler.BitKeyIndex` Represents a prefix tree of `SPARCAssembler.BitSpec` objects to find the most accurate SPARCOp.
`static class`	`SPARCAssembler.BitSpec` Specifies various bit fields used in SPARC instructions.
`static class`	`SPARCAssembler.Bpcc`
`static class`	`SPARCAssembler.Bpr`
`static class`	`SPARCAssembler.Br`
`static class`	`SPARCAssembler.BranchPredict`
`static class`	`SPARCAssembler.CBCond`
`static class`	`SPARCAssembler.CC` Condition Codes to use for instruction.
`static class`	`SPARCAssembler.CompositeBitSpec`
`static class`	`SPARCAssembler.ConditionFlag`
`static class`	`SPARCAssembler.ContinousBitSpec`
`static class`	`SPARCAssembler.ControlTransferOp` Base class for control transfer operations; provides access to the disp field.
`static class`	`SPARCAssembler.Fcn`
`static class`	`SPARCAssembler.MembarMask`
`static class`	`SPARCAssembler.Op2Op`
`static class`	`SPARCAssembler.Op2s`
`static class`	`SPARCAssembler.Op3Op`
`static class`	`SPARCAssembler.Op3s`
`static class`	`SPARCAssembler.Opfs`
`static class`	`SPARCAssembler.Ops`
`static class`	`SPARCAssembler.RCondition`
`static class`	`SPARCAssembler.Sethi`
`static class`	`SPARCAssembler.SPARCOp` Represents a class of SPARC instruction and gives methods to modify its fields.

Nested classes/interfaces inherited from class com.oracle.graal.asm.Assembler
Assembler.InstructionCounter, Assembler.LabelHint

Field Summary

Fields
Modifier and Type	Field and Description
`static SPARCAssembler.Bpcc`	`BPCC`
`static SPARCAssembler.Bpr`	`BPR`
`static SPARCAssembler.Br`	`BR`
`static SPARCAssembler.SPARCOp`	`BRANCH`
`static SPARCAssembler.SPARCOp`	`CALL`
`static SPARCAssembler.CBCond`	`CBCOND`
`static int`	`CCR_ICC_SHIFT`
`static int`	`CCR_V_SHIFT`
`static int`	`CCR_XCC_SHIFT`
`protected static int`	`D10HI_MASK`
`protected static int`	`D10HI_SHIFT`
`protected static int`	`D10LO_MASK`
`protected static int`	`D10LO_SHIFT`
`protected static int`	`D16HI_MASK`
`protected static int`	`D16HI_SHIFT`
`protected static int`	`D16LO_MASK`
`protected static int`	`D16LO_SHIFT`
`private ArrayList<Integer>`	`delaySlotOptimizationPoints`
`protected static int`	`DISP19_MASK`
`protected static int`	`DISP19_SHIFT`
`protected static int`	`DISP22_MASK`
`protected static int`	`DISP22_SHIFT`
`static SPARCAssembler.Bpcc`	`FBPCC`
`private static SPARCAssembler.BitKeyIndex`	`INDEX`
`static SPARCAssembler.SPARCOp`	`LDST`
`protected static int`	`OP2_MASK`
`protected static int`	`OP2_SHIFT`
`private static SPARCAssembler.Op2s[]`	`OP2S`
`static SPARCAssembler.Op3Op`	`OP3`
`private static SPARCAssembler.Op3s[][]`	`OP3S`
`private static SPARCAssembler.Ops[]`	`OPS`
`static int`	`PC_RETURN_OFFSET`
`static SPARCAssembler.Sethi`	`SETHI`

Fields inherited from class com.oracle.graal.asm.Assembler
target

Constructor Summary

Constructors
Constructor and Description

SPARCAssembler(TargetDescription target, RegisterConfig registerConfig)
Constructs an assembler for the SPARC architecture.

Constructors
Constructor and Description
`SPARCAssembler(TargetDescription target, RegisterConfig registerConfig)` Constructs an assembler for the SPARC architecture.

Method Summary

All Methods Static Methods Instance Methods Concrete Methods
Modifier and Type	Method and Description
`void`	`add(Register rs1, int simm13, Register rd)`
`void`	`add(Register rs1, Register rs2, Register rd)`
`void`	`addc(Register rs1, int simm13, Register rd)`
`void`	`addc(Register rs1, Register rs2, Register rd)`
`void`	`addcc(Register rs1, int simm13, Register rd)`
`void`	`addcc(Register rs1, Register rs2, Register rd)`
`void`	`and(Register rs1, int simm13, Register rd)`
`void`	`and(Register rs1, Register rs2, Register rd)`
`void`	`andcc(Register rs1, int simm13, Register rd)`
`void`	`andcc(Register rs1, Register rs2, Register rd)`
`void`	`andn(Register rs1, int simm13, Register rd)`
`void`	`andn(Register rs1, Register rs2, Register rd)`
`void`	`andncc(Register rs1, int simm13, Register rd)`
`void`	`andncc(Register rs1, Register rs2, Register rd)`
`private void`	`bcc(SPARCAssembler.Op2s op2, SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l)` Branch on (Integer\|Floatingpoint) Condition Codes.
`void`	`bicc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l)` Branch on Integer Condition Codes.
`void`	`bpcc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l, SPARCAssembler.CC cc, SPARCAssembler.BranchPredict predictTaken)` Branch on Integer Condition Codes with Prediction.
`private void`	`bpcc(SPARCAssembler.Op2s op2, SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l, SPARCAssembler.CC cc, SPARCAssembler.BranchPredict predictTaken)` Used for fbpcc (Float) and bpcc (Integer).
`void`	`bpr(SPARCAssembler.RCondition cond, SPARCAssembler.Annul annul, Label l, SPARCAssembler.BranchPredict predictTaken, Register rs1)` Branch on Integer Register with Prediction.
`int`	`call(int disp30)` Instruction format for calls.
`void`	`casa(Register rs1, Register rs2, Register rd, SPARCAssembler.Asi asi)`
`void`	`casxa(Register rs1, Register rs2, Register rd, SPARCAssembler.Asi asi)`
`private void`	`cbcond(int cc2, int i, SPARCAssembler.ConditionFlag cf, Register rs1, int rs2, Label l)`
`void`	`cbcondw(SPARCAssembler.ConditionFlag cf, Register rs1, int rs2, Label lab)`
`void`	`cbcondw(SPARCAssembler.ConditionFlag cf, Register rs1, Register rs2, Label lab)`
`void`	`cbcondx(SPARCAssembler.ConditionFlag cf, Register rs1, int rs2, Label lab)`
`void`	`cbcondx(SPARCAssembler.ConditionFlag cf, Register rs1, Register rs2, Label lab)`
`void`	`fabsd(Register rs2, Register rd)`
`void`	`fabss(Register rs2, Register rd)`
`void`	`faddd(Register rs1, Register rs2, Register rd)`
`void`	`faddq(Register rs1, Register rs2, Register rd)`
`void`	`fadds(Register rs1, Register rs2, Register rd)`
`void`	`fandd(Register rs1, Register rs2, Register rd)`
`void`	`fbcc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l)` Branch on Floating-Point Condition Codes.
`void`	`fbpcc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.Annul annul, Label l, SPARCAssembler.CC cc, SPARCAssembler.BranchPredict predictTaken)` Branch on Integer Condition Codes with Prediction.
`void`	`fcmp(SPARCAssembler.CC cc, SPARCAssembler.Opfs opf, Register rs1, Register rs2)` Instruction format for fcmp.
`void`	`fdivd(Register rs1, Register rs2, Register rd)`
`void`	`fdivs(Register rs1, Register rs2, Register rd)`
`void`	`fdtoi(Register rs2, Register rd)`
`void`	`fdtos(Register rs2, Register rd)`
`void`	`fdtox(Register rs2, Register rd)`
`void`	`fitod(Register rs2, Register rd)`
`void`	`fitos(Register rs2, Register rd)`
`void`	`flushw()`
`private void`	`fmovcc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.CC cc, Register rs2, Register rd, int opfLow)`
`void`	`fmovd(Register rs2, Register rd)`
`void`	`fmovdcc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.CC cc, Register rs2, Register rd)`
`void`	`fmovs(Register rs2, Register rd)`
`void`	`fmovscc(SPARCAssembler.ConditionFlag cond, SPARCAssembler.CC cc, Register rs2, Register rd)`
`protected void`	`fmt(int op, int rd, int op3, int rs1, int b)` Instruction format for most arithmetic stuff.
`protected void`	`fmt00(int a, int op2, int b)` Instruction format for Fmt00 instructions.
`protected void`	`fmt10(int rd, int op3, int rs1, int b)` Instruction format for most arithmetic stuff.
`void`	`fmuld(Register rs1, Register rs2, Register rd)`
`void`	`fmuls(Register rs1, Register rs2, Register rd)`
`void`	`fnegd(Register rs2, Register rd)`
`void`	`fnegs(Register rs2, Register rd)`
`void`	`fpadd32(Register rs1, Register rs2, Register rd)`
`void`	`fsmuld(Register rs1, Register rs2, Register rd)`
`void`	`fsqrtd(Register rs2, Register rd)`
`void`	`fsqrts(Register rs2, Register rd)`
`void`	`fsrc2d(Register rs2, Register rd)`
`void`	`fsrc2s(Register rs2, Register rd)`
`void`	`fstod(Register rs2, Register rd)`
`void`	`fstoi(Register rs2, Register rd)`
`void`	`fstox(Register rs2, Register rd)`
`void`	`fsubd(Register rs1, Register rs2, Register rd)`
`void`	`fsubs(Register rs1, Register rs2, Register rd)`
`void`	`fxtod(Register rs2, Register rd)`
`void`	`fxtos(Register rs2, Register rd)`
`void`	`fzerod(Register rd)`
`void`	`fzeros(Register rd)`
`static int`	`getBits(int inst, int hiBit, int lowBit)`
`Assembler.InstructionCounter`	`getInstructionCounter()`
`private static SPARCAssembler.Ops`	`getOp(int inst)`
`private static SPARCAssembler.Op2s`	`getOp2(int inst)`
`static SPARCAssembler.SPARCOp`	`getSPARCOp(int inst)`
`private static int`	`getXBit(SPARCAssembler.Op3s op3)` Helper method to determine if the instruction needs the X bit set.
`boolean`	`hasFeature(SPARC.CPUFeature feature)`
`static int`	`hi22(int x)`
`void`	`illtrap(int const22)`
`void`	`insertNopAfterCBCond()`
`protected static boolean`	`isCBCond(int inst)`
`static boolean`	`isImm(int x, int nbits)`
`private static boolean`	`isOp2(SPARCAssembler.Ops ops, SPARCAssembler.Op2s op2s, int inst)`
`static boolean`	`isSimm(long imm, int nbits)` Test if imm is within signed immediate range for nbits.
`static boolean`	`isSimm10(long imm)`
`static boolean`	`isSimm11(JavaConstant constant)`
`static boolean`	`isSimm11(long imm)`
`static boolean`	`isSimm13(int imm)`
`static boolean`	`isSimm13(JavaConstant constant)`
`static boolean`	`isSimm13(long imm)`
`static boolean`	`isSimm5(JavaConstant constant)`
`static boolean`	`isWordDisp30(long imm)`
`int`	`jmpl(Register rs1, int simm13, Register rd)`
`void`	`jmpl(Register rs1, Register rs2, Register rd)`
`void`	`ld(SPARCAddress src, Register dst, int bytes, boolean signed)`
`protected void`	`ld(SPARCAssembler.Op3s op3, SPARCAddress addr, Register rd)`
`protected void`	`ld(SPARCAssembler.Op3s op3, SPARCAddress addr, Register rd, SPARCAssembler.Asi asi)`
`void`	`lddf(SPARCAddress src, Register dst)`
`void`	`ldf(SPARCAddress src, Register dst)`
`void`	`ldsb(SPARCAddress src, Register dst)`
`void`	`ldsh(SPARCAddress src, Register dst)`
`void`	`ldsw(SPARCAddress src, Register dst)`
`void`	`ldub(SPARCAddress src, Register dst)`
`void`	`lduh(SPARCAddress src, Register dst)`
`void`	`lduw(SPARCAddress src, Register dst)`
`void`	`lduwa(Register rs1, Register rs2, Register rd, SPARCAssembler.Asi asi)`
`void`	`ldx(SPARCAddress src, Register dst)`
`void`	`ldxa(Register rs1, Register rs2, Register rd, SPARCAssembler.Asi asi)`
`static int`	`lo10(int x)`
`static long`	`maxSimm(long nbits)` Maximum value for signed immediate ranges.
`void`	`membar(int barriers)`
`static long`	`minSimm(long nbits)` Minimum value for signed immediate ranges.
`private void`	`movcc(SPARCAssembler.ConditionFlag conditionFlag, SPARCAssembler.CC cc, int i, int imm, Register rd)`
`void`	`movcc(SPARCAssembler.ConditionFlag conditionFlag, SPARCAssembler.CC cc, int simm11, Register rd)`
`void`	`movcc(SPARCAssembler.ConditionFlag conditionFlag, SPARCAssembler.CC cc, Register rs2, Register rd)`
`void`	`movdtox(Register rs2, Register rd)`
`void`	`movstosw(Register rs2, Register rd)`
`void`	`movstouw(Register rs2, Register rd)`
`void`	`movwtos(Register rs2, Register rd)`
`void`	`movxtod(Register rs2, Register rd)`
`void`	`mulx(Register rs1, int simm13, Register rd)`
`void`	`mulx(Register rs1, Register rs2, Register rd)`
`void`	`nop()` NOP.
`protected void`	`op3(SPARCAssembler.Op3s op3, Register rs1, int simm13, Register rd)`
`protected void`	`op3(SPARCAssembler.Op3s op3, Register rs1, Register rs2, Register rd)`
`private void`	`op3(SPARCAssembler.Op3s op3, SPARCAssembler.Opfs opf, Register rs1, Register rs2, Register rd)`
`private void`	`optimizeDelaySlot(int i)` Optimizes branch instruction b which has a nop in the delay slot.
`void`	`or(Register rs1, int simm13, Register rd)`
`void`	`or(Register rs1, Register rs2, Register rd)`
`void`	`patchAddImmediate(int position, int simm13)`
`protected int`	`patchUnbound(Label label)`
`void`	`peephole()` Does peephole optimization on code generated by this assembler.
`void`	`popc(int simm13, Register rd)`
`void`	`popc(Register rs2, Register rd)`
`void`	`prefetch(SPARCAddress addr, SPARCAssembler.Fcn fcn)`
`void`	`rdpc(Register rd)`
`void`	`restore(Register rs1, Register rs2, Register rd)`
`void`	`save(Register rs1, int simm13, Register rd)`
`void`	`save(Register rs1, Register rs2, Register rd)`
`void`	`sdivx(Register rs1, int simm13, Register rd)`
`void`	`sdivx(Register rs1, Register rs2, Register rd)`
`void`	`sethi(int imm22, Register dst)`
`static int`	`simm(int x, int nbits)`
`void`	`sll(Register rs1, int shcnt32, Register rd)`
`void`	`sll(Register rs1, Register rs2, Register rd)`
`void`	`sllx(Register rs1, int shcnt64, Register rd)`
`void`	`sllx(Register rs1, Register rs2, Register rd)`
`void`	`sra(Register rs1, int simm13, Register rd)`
`void`	`sra(Register rs1, Register rs2, Register rd)`
`void`	`srax(Register rs1, int shcnt64, Register rd)`
`void`	`srax(Register rs1, Register rs2, Register rd)`
`void`	`srl(Register rs1, int simm13, Register rd)`
`void`	`srl(Register rs1, Register rs2, Register rd)`
`void`	`srlx(Register rs1, int shcnt64, Register rd)`
`void`	`srlx(Register rs1, Register rs2, Register rd)`
`protected void`	`st(SPARCAssembler.Op3s op3, Register rs1, SPARCAddress dest)`
`void`	`stb(Register rd, SPARCAddress addr)`
`void`	`stdf(Register rd, SPARCAddress addr)`
`void`	`stf(Register rd, SPARCAddress addr)`
`void`	`sth(Register rd, SPARCAddress addr)`
`void`	`stw(Register rd, SPARCAddress addr)`
`void`	`stx(Register rd, SPARCAddress addr)`
`void`	`sub(Register rs1, int simm13, Register rd)`
`void`	`sub(Register rs1, Register rs2, Register rd)`
`void`	`subcc(Register rs1, int simm13, Register rd)`
`void`	`subcc(Register rs1, Register rs2, Register rd)`
`void`	`ta(int trap)`
`void`	`tcc(SPARCAssembler.CC cc, SPARCAssembler.ConditionFlag flag, int trap)`
`void`	`udivx(Register rs1, int simm13, Register rd)`
`void`	`udivx(Register rs1, Register rs2, Register rd)`
`void`	`umulxhi(Register rs1, Register rs2, Register rd)`
`void`	`wrccr(Register rs1, int simm13)`
`void`	`wrccr(Register rs1, Register rs2)`
`void`	`xnor(Register rs1, int simm13, Register rd)`
`void`	`xnor(Register rs1, Register rs2, Register rd)`
`void`	`xor(Register rs1, int simm13, Register rd)`
`void`	`xor(Register rs1, Register rs2, Register rd)`
`void`	`xorcc(Register rs1, int simm13, Register rd)`
`void`	`xorcc(Register rs1, Register rs2, Register rd)`

Methods inherited from class com.oracle.graal.asm.Assembler
align, bind, close, createLabelName, emitByte, emitByte, emitInt, emitInt, emitLong, emitLong, emitShort, emitShort, emitString, emitString, emitString0, ensureUniquePC, getByte, getInt, getPlaceholder, getShort, jmp, makeAddress, nameOf, patchJumpTarget, position, requestLabelHint, reset

Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

CCR_ICC_SHIFT
```
public static final int CCR_ICC_SHIFT
```
See Also:

Constant Field Values

CCR_XCC_SHIFT
```
public static final int CCR_XCC_SHIFT
```
See Also:

Constant Field Values

CCR_V_SHIFT
```
public static final int CCR_V_SHIFT
```
See Also:

Constant Field Values

OP2_SHIFT
```
protected static final int OP2_SHIFT
```
See Also:

Constant Field Values

OP2_MASK
```
protected static final int OP2_MASK
```
See Also:

Constant Field Values

DISP22_SHIFT
```
protected static final int DISP22_SHIFT
```
See Also:

Constant Field Values

DISP22_MASK
```
protected static final int DISP22_MASK
```
See Also:

Constant Field Values

DISP19_SHIFT
```
protected static final int DISP19_SHIFT
```
See Also:

Constant Field Values

DISP19_MASK
```
protected static final int DISP19_MASK
```
See Also:

Constant Field Values

D16HI_SHIFT
```
protected static final int D16HI_SHIFT
```
See Also:

Constant Field Values

D16HI_MASK
```
protected static final int D16HI_MASK
```
See Also:

Constant Field Values

D16LO_SHIFT
```
protected static final int D16LO_SHIFT
```
See Also:

Constant Field Values

D16LO_MASK
```
protected static final int D16LO_MASK
```
See Also:

Constant Field Values

D10LO_MASK
```
protected static final int D10LO_MASK
```
See Also:

Constant Field Values

D10HI_MASK
```
protected static final int D10HI_MASK
```
See Also:

Constant Field Values

D10LO_SHIFT
```
protected static final int D10LO_SHIFT
```
See Also:

Constant Field Values

D10HI_SHIFT
```
protected static final int D10HI_SHIFT
```
See Also:

Constant Field Values

OPS

private static final SPARCAssembler.Ops[] OPS

OP2S

private static final SPARCAssembler.Op2s[] OP2S

OP3S

private static final SPARCAssembler.Op3s[][] OP3S

delaySlotOptimizationPoints

private ArrayList<Integer> delaySlotOptimizationPoints

BPCC

public static final SPARCAssembler.Bpcc BPCC

FBPCC

public static final SPARCAssembler.Bpcc FBPCC

CBCOND

public static final SPARCAssembler.CBCond CBCOND

BPR

public static final SPARCAssembler.Bpr BPR

BR

public static final SPARCAssembler.Br BR

SETHI

public static final SPARCAssembler.Sethi SETHI

OP3

public static final SPARCAssembler.Op3Op OP3

LDST

public static final SPARCAssembler.SPARCOp LDST

BRANCH

public static final SPARCAssembler.SPARCOp BRANCH

CALL

public static final SPARCAssembler.SPARCOp CALL

INDEX

private static final SPARCAssembler.BitKeyIndex INDEX

PC_RETURN_OFFSET
```
public static final int PC_RETURN_OFFSET
```
See Also:

Constant Field Values

Constructor Detail
- SPARCAssembler
```
public SPARCAssembler(TargetDescription target,
                      RegisterConfig registerConfig)
```
  Constructs an assembler for the SPARC architecture.
  
  Parameters:
  
  registerConfig - the register configuration used to bind Register.Frame and Register.CallerFrame to physical registers. This value can be null if this assembler instance will not be used to assemble instructions using these logical registers.

Method Detail

getSPARCOp

public static SPARCAssembler.SPARCOp getSPARCOp(int inst)

hasFeature

public boolean hasFeature(SPARC.CPUFeature feature)

simm

public static final int simm(int x,
                             int nbits)

isImm

public static final boolean isImm(int x,
                                  int nbits)

minSimm
```
public static long minSimm(long nbits)
```
Minimum value for signed immediate ranges.

maxSimm
```
public static long maxSimm(long nbits)
```
Maximum value for signed immediate ranges.

isSimm

public static boolean isSimm(long imm,
                             int nbits)

Test if imm is within signed immediate range for nbits.

isSimm10

public static boolean isSimm10(long imm)

isSimm11

public static boolean isSimm11(long imm)

isSimm11

public static boolean isSimm11(JavaConstant constant)

isSimm5

public static boolean isSimm5(JavaConstant constant)

isSimm13

public static boolean isSimm13(int imm)

isSimm13

public static boolean isSimm13(JavaConstant constant)

isSimm13

public static boolean isSimm13(long imm)

isWordDisp30

public static boolean isWordDisp30(long imm)

hi22
```
public static final int hi22(int x)
```

lo10
```
public static final int lo10(int x)
```

fmt00

protected void fmt00(int a,
                     int op2,
                     int b)

Instruction format for Fmt00 instructions. This abstraction is needed as it makes the patching easier later on.

 | 00  |    a   | op2 |               b                         |
 |31 30|29    25|24 22|21                                      0|

op3

private void op3(SPARCAssembler.Op3s op3,
                 SPARCAssembler.Opfs opf,
                 Register rs1,
                 Register rs2,
                 Register rd)

op3

protected void op3(SPARCAssembler.Op3s op3,
                   Register rs1,
                   Register rs2,
                   Register rd)

op3

protected void op3(SPARCAssembler.Op3s op3,
                   Register rs1,
                   int simm13,
                   Register rd)

bicc

public void bicc(SPARCAssembler.ConditionFlag cond,
                 SPARCAssembler.Annul annul,
                 Label l)

Branch on Integer Condition Codes.

 | 00  |annul| cond| 010 |               disp22                 |
 |31 30|29   |28 25|24 22|21                                   0|

fbcc

public void fbcc(SPARCAssembler.ConditionFlag cond,
                 SPARCAssembler.Annul annul,
                 Label l)

Branch on Floating-Point Condition Codes.

 | 00  |annul| cond| 110 |               disp22                 |
 |31 30|29   |28 25|24 22|21                                   0|

bcc

private void bcc(SPARCAssembler.Op2s op2,
                 SPARCAssembler.ConditionFlag cond,
                 SPARCAssembler.Annul annul,
                 Label l)

Branch on (Integer|Floatingpoint) Condition Codes.

 | 00  |annul| cond| op2 |               disp22                 |
 |31 30|29   |28 25|24 22|21                                   0|

insertNopAfterCBCond
```
public void insertNopAfterCBCond()
```

isCBCond

protected static boolean isCBCond(int inst)

isOp2

private static boolean isOp2(SPARCAssembler.Ops ops,
                             SPARCAssembler.Op2s op2s,
                             int inst)

getOp

private static SPARCAssembler.Ops getOp(int inst)

getOp2

private static SPARCAssembler.Op2s getOp2(int inst)

getBits

public static int getBits(int inst,
                          int hiBit,
                          int lowBit)

bpcc

public void bpcc(SPARCAssembler.ConditionFlag cond,
                 SPARCAssembler.Annul annul,
                 Label l,
                 SPARCAssembler.CC cc,
                 SPARCAssembler.BranchPredict predictTaken)

Branch on Integer Condition Codes with Prediction.

 | 00  |an|cond | 001 |cc1 2|p |           disp19               |
 |31 30|29|28 25|24 22|21 20|19|                               0|

fbpcc

public void fbpcc(SPARCAssembler.ConditionFlag cond,
                  SPARCAssembler.Annul annul,
                  Label l,
                  SPARCAssembler.CC cc,
                  SPARCAssembler.BranchPredict predictTaken)

Branch on Integer Condition Codes with Prediction.

 | 00  |an|cond | 101 |cc1 2|p |           disp19               |
 |31 30|29|28 25|24 22|21 20|19|                               0|

bpcc

private void bpcc(SPARCAssembler.Op2s op2,
                  SPARCAssembler.ConditionFlag cond,
                  SPARCAssembler.Annul annul,
                  Label l,
                  SPARCAssembler.CC cc,
                  SPARCAssembler.BranchPredict predictTaken)

Used for fbpcc (Float) and bpcc (Integer).

 | 00  |an|cond | op2 |cc1 2|p |           disp19               |
 |31 30|29|28 25|24 22|21 20|19|                               0|

bpr

public void bpr(SPARCAssembler.RCondition cond,
                SPARCAssembler.Annul annul,
                Label l,
                SPARCAssembler.BranchPredict predictTaken,
                Register rs1)

Branch on Integer Register with Prediction.

 | 00  |an| 0|rcond | 011 |d16hi|p | rs1 |    d16lo             |
 |31 30|29|28|27 25 |24 22|21 20|19|18 14|                     0|

patchUnbound

protected int patchUnbound(Label label)

cbcondw

public void cbcondw(SPARCAssembler.ConditionFlag cf,
                    Register rs1,
                    Register rs2,
                    Label lab)

cbcondw

public void cbcondw(SPARCAssembler.ConditionFlag cf,
                    Register rs1,
                    int rs2,
                    Label lab)

cbcondx

public void cbcondx(SPARCAssembler.ConditionFlag cf,
                    Register rs1,
                    Register rs2,
                    Label lab)

cbcondx

public void cbcondx(SPARCAssembler.ConditionFlag cf,
                    Register rs1,
                    int rs2,
                    Label lab)

cbcond

private void cbcond(int cc2,
                    int i,
                    SPARCAssembler.ConditionFlag cf,
                    Register rs1,
                    int rs2,
                    Label l)

nop

public void nop()

NOP.

 | 00  |00000| 100 |                0                    |
 |31 30|29 25|24 22|21                                  0|

sethi

public void sethi(int imm22,
                  Register dst)

call

public int call(int disp30)

Instruction format for calls.

 | 01  |                      disp30                             |
 |31 30|29                                                      0|

Returns:: Position of the call instruction

add

public void add(Register rs1,
                Register rs2,
                Register rd)

add

public void add(Register rs1,
                int simm13,
                Register rd)

addc

public void addc(Register rs1,
                 Register rs2,
                 Register rd)

addc

public void addc(Register rs1,
                 int simm13,
                 Register rd)

addcc

public void addcc(Register rs1,
                  Register rs2,
                  Register rd)

addcc

public void addcc(Register rs1,
                  int simm13,
                  Register rd)

and

public void and(Register rs1,
                Register rs2,
                Register rd)

and

public void and(Register rs1,
                int simm13,
                Register rd)

andcc

public void andcc(Register rs1,
                  Register rs2,
                  Register rd)

andcc

public void andcc(Register rs1,
                  int simm13,
                  Register rd)

andn

public void andn(Register rs1,
                 Register rs2,
                 Register rd)

andn

public void andn(Register rs1,
                 int simm13,
                 Register rd)

andncc

public void andncc(Register rs1,
                   Register rs2,
                   Register rd)

andncc

public void andncc(Register rs1,
                   int simm13,
                   Register rd)

movwtos

public void movwtos(Register rs2,
                    Register rd)

umulxhi

public void umulxhi(Register rs1,
                    Register rs2,
                    Register rd)

fdtos

public void fdtos(Register rs2,
                  Register rd)

movstouw

public void movstouw(Register rs2,
                     Register rd)

movstosw

public void movstosw(Register rs2,
                     Register rd)

movdtox

public void movdtox(Register rs2,
                    Register rd)

movxtod

public void movxtod(Register rs2,
                    Register rd)

fadds

public void fadds(Register rs1,
                  Register rs2,
                  Register rd)

faddd

public void faddd(Register rs1,
                  Register rs2,
                  Register rd)

faddq

public void faddq(Register rs1,
                  Register rs2,
                  Register rd)

fdivs

public void fdivs(Register rs1,
                  Register rs2,
                  Register rd)

fdivd

public void fdivd(Register rs1,
                  Register rs2,
                  Register rd)

fmovs

public void fmovs(Register rs2,
                  Register rd)

fmovd

public void fmovd(Register rs2,
                  Register rd)

fsrc2s

public void fsrc2s(Register rs2,
                   Register rd)

fsrc2d

public void fsrc2d(Register rs2,
                   Register rd)

fmuls

public void fmuls(Register rs1,
                  Register rs2,
                  Register rd)

fsmuld

public void fsmuld(Register rs1,
                   Register rs2,
                   Register rd)

fmuld

public void fmuld(Register rs1,
                  Register rs2,
                  Register rd)

fnegs

public void fnegs(Register rs2,
                  Register rd)

fnegd

public void fnegd(Register rs2,
                  Register rd)

getXBit
```
private static int getXBit(SPARCAssembler.Op3s op3)
```
Helper method to determine if the instruction needs the X bit set.

fstoi

public void fstoi(Register rs2,
                  Register rd)

fstox

public void fstox(Register rs2,
                  Register rd)

fdtox

public void fdtox(Register rs2,
                  Register rd)

fstod

public void fstod(Register rs2,
                  Register rd)

fdtoi

public void fdtoi(Register rs2,
                  Register rd)

fitos

public void fitos(Register rs2,
                  Register rd)

fitod

public void fitod(Register rs2,
                  Register rd)

fxtos

public void fxtos(Register rs2,
                  Register rd)

fxtod

public void fxtod(Register rs2,
                  Register rd)

fzeros
```
public void fzeros(Register rd)
```

fzerod
```
public void fzerod(Register rd)
```

flushw
```
public void flushw()
```

fsqrtd

public void fsqrtd(Register rs2,
                   Register rd)

fsqrts

public void fsqrts(Register rs2,
                   Register rd)

fabss

public void fabss(Register rs2,
                  Register rd)

fabsd

public void fabsd(Register rs2,
                  Register rd)

fsubs

public void fsubs(Register rs1,
                  Register rs2,
                  Register rd)

fsubd

public void fsubd(Register rs1,
                  Register rs2,
                  Register rd)

fcmp

public void fcmp(SPARCAssembler.CC cc,
                 SPARCAssembler.Opfs opf,
                 Register rs1,
                 Register rs2)

Instruction format for fcmp.

 | 10  | --- |cc1|cc0|desc |   rs1   |   opf  | rs2 |
 |31 30|29 27|26 |25 |24 19|18     14|13     5|4   0|

fmt10

protected void fmt10(int rd,
                     int op3,
                     int rs1,
                     int b)

Instruction format for most arithmetic stuff.

 |  10 | rd  | op3 | rs1 |   b   |
 |31 30|29 25|24 19|18 14|13    0|

fmt

protected void fmt(int op,
                   int rd,
                   int op3,
                   int rs1,
                   int b)

Instruction format for most arithmetic stuff.

 |  op | rd  | op3 | rs1 |   b   |
 |31 30|29 25|24 19|18 14|13    0|

illtrap
```
public void illtrap(int const22)
```

jmpl

public void jmpl(Register rs1,
                 Register rs2,
                 Register rd)

jmpl

public int jmpl(Register rs1,
                int simm13,
                Register rd)

Returns:: Position of the jmpl instruction

fmovdcc

public void fmovdcc(SPARCAssembler.ConditionFlag cond,
                    SPARCAssembler.CC cc,
                    Register rs2,
                    Register rd)

fmovscc

public void fmovscc(SPARCAssembler.ConditionFlag cond,
                    SPARCAssembler.CC cc,
                    Register rs2,
                    Register rd)

fmovcc

private void fmovcc(SPARCAssembler.ConditionFlag cond,
                    SPARCAssembler.CC cc,
                    Register rs2,
                    Register rd,
                    int opfLow)

movcc

public void movcc(SPARCAssembler.ConditionFlag conditionFlag,
                  SPARCAssembler.CC cc,
                  Register rs2,
                  Register rd)

movcc

public void movcc(SPARCAssembler.ConditionFlag conditionFlag,
                  SPARCAssembler.CC cc,
                  int simm11,
                  Register rd)

movcc

private void movcc(SPARCAssembler.ConditionFlag conditionFlag,
                   SPARCAssembler.CC cc,
                   int i,
                   int imm,
                   Register rd)

mulx

public void mulx(Register rs1,
                 Register rs2,
                 Register rd)

mulx

public void mulx(Register rs1,
                 int simm13,
                 Register rd)

or

public void or(Register rs1,
               Register rs2,
               Register rd)

or

public void or(Register rs1,
               int simm13,
               Register rd)

popc

public void popc(Register rs2,
                 Register rd)

popc

public void popc(int simm13,
                 Register rd)

prefetch

public void prefetch(SPARCAddress addr,
                     SPARCAssembler.Fcn fcn)

rdpc
```
public void rdpc(Register rd)
```

restore

public void restore(Register rs1,
                    Register rs2,
                    Register rd)

save

public void save(Register rs1,
                 Register rs2,
                 Register rd)

save

public void save(Register rs1,
                 int simm13,
                 Register rd)

sdivx

public void sdivx(Register rs1,
                  Register rs2,
                  Register rd)

sdivx

public void sdivx(Register rs1,
                  int simm13,
                  Register rd)

udivx

public void udivx(Register rs1,
                  Register rs2,
                  Register rd)

udivx

public void udivx(Register rs1,
                  int simm13,
                  Register rd)

sll

public void sll(Register rs1,
                Register rs2,
                Register rd)

sll

public void sll(Register rs1,
                int shcnt32,
                Register rd)

sllx

public void sllx(Register rs1,
                 Register rs2,
                 Register rd)

sllx

public void sllx(Register rs1,
                 int shcnt64,
                 Register rd)

sra

public void sra(Register rs1,
                Register rs2,
                Register rd)

sra

public void sra(Register rs1,
                int simm13,
                Register rd)

srax

public void srax(Register rs1,
                 Register rs2,
                 Register rd)

srax

public void srax(Register rs1,
                 int shcnt64,
                 Register rd)

srl

public void srl(Register rs1,
                Register rs2,
                Register rd)

srl

public void srl(Register rs1,
                int simm13,
                Register rd)

srlx

public void srlx(Register rs1,
                 Register rs2,
                 Register rd)

srlx

public void srlx(Register rs1,
                 int shcnt64,
                 Register rd)

fandd

public void fandd(Register rs1,
                  Register rs2,
                  Register rd)

sub

public void sub(Register rs1,
                Register rs2,
                Register rd)

sub

public void sub(Register rs1,
                int simm13,
                Register rd)

subcc

public void subcc(Register rs1,
                  Register rs2,
                  Register rd)

subcc

public void subcc(Register rs1,
                  int simm13,
                  Register rd)

ta
```
public void ta(int trap)
```

tcc

public void tcc(SPARCAssembler.CC cc,
                SPARCAssembler.ConditionFlag flag,
                int trap)

wrccr

public void wrccr(Register rs1,
                  Register rs2)

wrccr

public void wrccr(Register rs1,
                  int simm13)

xor

public void xor(Register rs1,
                Register rs2,
                Register rd)

xor

public void xor(Register rs1,
                int simm13,
                Register rd)

xorcc

public void xorcc(Register rs1,
                  Register rs2,
                  Register rd)

xorcc

public void xorcc(Register rs1,
                  int simm13,
                  Register rd)

xnor

public void xnor(Register rs1,
                 Register rs2,
                 Register rd)

xnor

public void xnor(Register rs1,
                 int simm13,
                 Register rd)

ld

protected void ld(SPARCAssembler.Op3s op3,
                  SPARCAddress addr,
                  Register rd,
                  SPARCAssembler.Asi asi)

ld

protected void ld(SPARCAssembler.Op3s op3,
                  SPARCAddress addr,
                  Register rd)

lddf

public void lddf(SPARCAddress src,
                 Register dst)

ldf

public void ldf(SPARCAddress src,
                Register dst)

lduh

public void lduh(SPARCAddress src,
                 Register dst)

ldsh

public void ldsh(SPARCAddress src,
                 Register dst)

ld

public void ld(SPARCAddress src,
               Register dst,
               int bytes,
               boolean signed)

ldub

public void ldub(SPARCAddress src,
                 Register dst)

ldsb

public void ldsb(SPARCAddress src,
                 Register dst)

lduw

public void lduw(SPARCAddress src,
                 Register dst)

ldsw

public void ldsw(SPARCAddress src,
                 Register dst)

ldx

public void ldx(SPARCAddress src,
                Register dst)

ldxa

public void ldxa(Register rs1,
                 Register rs2,
                 Register rd,
                 SPARCAssembler.Asi asi)

lduwa

public void lduwa(Register rs1,
                  Register rs2,
                  Register rd,
                  SPARCAssembler.Asi asi)

st

protected void st(SPARCAssembler.Op3s op3,
                  Register rs1,
                  SPARCAddress dest)

stdf

public void stdf(Register rd,
                 SPARCAddress addr)

stf

public void stf(Register rd,
                SPARCAddress addr)

stb

public void stb(Register rd,
                SPARCAddress addr)

sth

public void sth(Register rd,
                SPARCAddress addr)

stw

public void stw(Register rd,
                SPARCAddress addr)

stx

public void stx(Register rd,
                SPARCAddress addr)

membar
```
public void membar(int barriers)
```

casa

public void casa(Register rs1,
                 Register rs2,
                 Register rd,
                 SPARCAssembler.Asi asi)

casxa

public void casxa(Register rs1,
                  Register rs2,
                  Register rd,
                  SPARCAssembler.Asi asi)

getInstructionCounter
```
public Assembler.InstructionCounter getInstructionCounter()
```
Overrides:

getInstructionCounter in class Assembler

patchAddImmediate

public void patchAddImmediate(int position,
                              int simm13)

fpadd32

public void fpadd32(Register rs1,
                    Register rs2,
                    Register rd)

peephole
```
public void peephole()
```
Does peephole optimization on code generated by this assembler. This method should be called at the end of code generation.
It searches for conditional branch instructions which has nop in the delay slot then looks at the instruction at branch target; if it is an arithmetic instruction, which does not throw an exception (e.g. division), it pulls this instruction into the delay slot and increments the displacement by 1.

optimizeDelaySlot
```
private void optimizeDelaySlot(int i)
```
Optimizes branch instruction b which has a nop in the delay slot. It tries to stuff the instruction at bs branch target into the delay slot of b, set the annul flag and increments bs disp field by 1;
If bs branch target instruction is an unconditional branch t, then it tries to put ts delayed instruction into the delay slot of b and add the ts disp field to bs disp field.

Class SPARCAssembler

Nested Class Summary

Nested classes/interfaces inherited from class com.oracle.graal.asm.Assembler

Field Summary

Fields inherited from class com.oracle.graal.asm.Assembler

Constructor Summary

Method Summary

Methods inherited from class com.oracle.graal.asm.Assembler

Methods inherited from class java.lang.Object

Field Detail

CCR_ICC_SHIFT

CCR_XCC_SHIFT

CCR_V_SHIFT

OP2_SHIFT

OP2_MASK

DISP22_SHIFT

DISP22_MASK

DISP19_SHIFT

DISP19_MASK

D16HI_SHIFT

D16HI_MASK

D16LO_SHIFT

D16LO_MASK

D10LO_MASK

D10HI_MASK

D10LO_SHIFT

D10HI_SHIFT

OPS

OP2S

OP3S

delaySlotOptimizationPoints

BPCC

FBPCC

CBCOND

BPR

BR

SETHI

OP3

LDST

BRANCH

CALL

INDEX

PC_RETURN_OFFSET

Constructor Detail

SPARCAssembler

Method Detail

getSPARCOp

hasFeature

simm

isImm

minSimm

maxSimm

isSimm

isSimm10

isSimm11

isSimm11

isSimm5

isSimm13

isSimm13

isSimm13

isWordDisp30

hi22

lo10

fmt00

op3

op3

op3

bicc

fbcc

bcc

insertNopAfterCBCond

isCBCond

isOp2

getOp

getOp2

getBits

bpcc

fbpcc

bpcc

bpr