Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 15137:4a162f0b59d7
Simplify NodePredicates (use overrides instead of if cascades)
author | Gilles Duboscq <duboscq@ssw.jku.at> |
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date | Fri, 11 Apr 2014 18:16:32 +0200 |
parents | 4ca6dc0799b6 |
children | 52b4284cb496 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_Compilation.hpp" | |
27 #include "c1/c1_LIRAssembler.hpp" | |
28 #include "c1/c1_MacroAssembler.hpp" | |
29 #include "c1/c1_Runtime1.hpp" | |
30 #include "c1/c1_ValueStack.hpp" | |
31 #include "ci/ciArrayKlass.hpp" | |
32 #include "ci/ciInstance.hpp" | |
33 #include "gc_interface/collectedHeap.hpp" | |
34 #include "memory/barrierSet.hpp" | |
35 #include "memory/cardTableModRefBS.hpp" | |
36 #include "nativeInst_sparc.hpp" | |
37 #include "oops/objArrayKlass.hpp" | |
38 #include "runtime/sharedRuntime.hpp" | |
0 | 39 |
40 #define __ _masm-> | |
41 | |
42 | |
43 //------------------------------------------------------------ | |
44 | |
45 | |
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
47 if (opr->is_constant()) { | |
48 LIR_Const* constant = opr->as_constant_ptr(); | |
49 switch (constant->type()) { | |
50 case T_INT: { | |
51 jint value = constant->as_jint(); | |
52 return Assembler::is_simm13(value); | |
53 } | |
54 | |
55 default: | |
56 return false; | |
57 } | |
58 } | |
59 return false; | |
60 } | |
61 | |
62 | |
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { | |
64 switch (op->code()) { | |
65 case lir_null_check: | |
66 return true; | |
67 | |
68 | |
69 case lir_add: | |
70 case lir_ushr: | |
71 case lir_shr: | |
72 case lir_shl: | |
73 // integer shifts and adds are always one instruction | |
74 return op->result_opr()->is_single_cpu(); | |
75 | |
76 | |
77 case lir_move: { | |
78 LIR_Op1* op1 = op->as_Op1(); | |
79 LIR_Opr src = op1->in_opr(); | |
80 LIR_Opr dst = op1->result_opr(); | |
81 | |
82 if (src == dst) { | |
83 NEEDS_CLEANUP; | |
84 // this works around a problem where moves with the same src and dst | |
85 // end up in the delay slot and then the assembler swallows the mov | |
86 // since it has no effect and then it complains because the delay slot | |
87 // is empty. returning false stops the optimizer from putting this in | |
88 // the delay slot | |
89 return false; | |
90 } | |
91 | |
92 // don't put moves involving oops into the delay slot since the VerifyOops code | |
93 // will make it much larger than a single instruction. | |
94 if (VerifyOops) { | |
95 return false; | |
96 } | |
97 | |
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || | |
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { | |
100 return false; | |
101 } | |
102 | |
2002 | 103 if (UseCompressedOops) { |
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; | |
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; | |
106 } | |
107 | |
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108 if (UseCompressedClassPointers) { |
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109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS && |
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110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false; |
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111 } |
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112 |
0 | 113 if (dst->is_register()) { |
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { | |
115 return !PatchALot; | |
116 } else if (src->is_single_stack()) { | |
117 return true; | |
118 } | |
119 } | |
120 | |
121 if (src->is_register()) { | |
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { | |
123 return !PatchALot; | |
124 } else if (dst->is_single_stack()) { | |
125 return true; | |
126 } | |
127 } | |
128 | |
129 if (dst->is_register() && | |
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || | |
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { | |
132 return true; | |
133 } | |
134 | |
135 return false; | |
136 } | |
137 | |
138 default: | |
139 return false; | |
140 } | |
141 ShouldNotReachHere(); | |
142 } | |
143 | |
144 | |
145 LIR_Opr LIR_Assembler::receiverOpr() { | |
146 return FrameMap::O0_oop_opr; | |
147 } | |
148 | |
149 | |
150 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
151 return FrameMap::I0_opr; | |
152 } | |
153 | |
154 | |
155 int LIR_Assembler::initial_frame_size_in_bytes() { | |
156 return in_bytes(frame_map()->framesize_in_bytes()); | |
157 } | |
158 | |
159 | |
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); | |
161 // we fetch the class of the receiver (O0) and compare it with the cached class. | |
162 // If they do not match we jump to slow case. | |
163 int LIR_Assembler::check_icache() { | |
164 int offset = __ offset(); | |
165 __ inline_cache_check(O0, G5_inline_cache_reg); | |
166 return offset; | |
167 } | |
168 | |
169 | |
170 void LIR_Assembler::osr_entry() { | |
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): | |
172 // | |
173 // 1. Create a new compiled activation. | |
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty | |
175 // at the osr_bci; it is not initialized. | |
176 // 3. Jump to the continuation address in compiled code to resume execution. | |
177 | |
178 // OSR entry point | |
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
181 ValueStack* entry_state = osr_entry->end()->state(); | |
182 int number_of_locks = entry_state->locks_size(); | |
183 | |
184 // Create a frame for the compiled activation. | |
185 __ build_frame(initial_frame_size_in_bytes()); | |
186 | |
187 // OSR buffer is | |
188 // | |
189 // locals[nlocals-1..0] | |
190 // monitors[number_of_locks-1..0] | |
191 // | |
192 // locals is a direct copy of the interpreter frame so in the osr buffer | |
193 // so first slot in the local array is the last local from the interpreter | |
194 // and last slot is local[0] (receiver) from the interpreter | |
195 // | |
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
198 // in the interpreter frame (the method lock if a sync method) | |
199 | |
200 // Initialize monitors in the compiled activation. | |
201 // I0: pointer to osr buffer | |
202 // | |
203 // All other registers are dead at this point and the locals will be | |
204 // copied into place by code emitted in the IR. | |
205 | |
206 Register OSR_buf = osrBufferPointer()->as_register(); | |
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); | |
208 int monitor_offset = BytesPerWord * method()->max_locals() + | |
1060 | 209 (2 * BytesPerWord) * (number_of_locks - 1); |
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
211 // the OSR buffer using 2 word entries: first the lock and then | |
212 // the oop. | |
0 | 213 for (int i = 0; i < number_of_locks; i++) { |
1060 | 214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
0 | 215 #ifdef ASSERT |
216 // verify the interpreter's monitor has a non-null object | |
217 { | |
218 Label L; | |
1060 | 219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
3839 | 220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L); |
0 | 221 __ stop("locked object is NULL"); |
222 __ bind(L); | |
223 } | |
224 #endif // ASSERT | |
225 // Copy the lock field into the compiled activation. | |
1060 | 226 __ ld_ptr(OSR_buf, slot_offset + 0, O7); |
0 | 227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
1060 | 228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
0 | 229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
230 } | |
231 } | |
232 } | |
233 | |
234 | |
235 // Optimized Library calls | |
236 // This is the fast version of java.lang.String.compare; it has not | |
237 // OSR-entry and therefore, we generate a slow version for OSR's | |
238 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { | |
239 Register str0 = left->as_register(); | |
240 Register str1 = right->as_register(); | |
241 | |
242 Label Ldone; | |
243 | |
244 Register result = dst->as_register(); | |
245 { | |
6057 | 246 // Get a pointer to the first character of string0 in tmp0 |
247 // and get string0.length() in str0 | |
248 // Get a pointer to the first character of string1 in tmp1 | |
249 // and get string1.length() in str1 | |
250 // Also, get string0.length()-string1.length() in | |
251 // o7 and get the condition code set | |
0 | 252 // Note: some instructions have been hoisted for better instruction scheduling |
253 | |
254 Register tmp0 = L0; | |
255 Register tmp1 = L1; | |
256 Register tmp2 = L2; | |
257 | |
258 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array | |
6057 | 259 if (java_lang_String::has_offset_field()) { |
260 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
261 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
262 __ load_heap_oop(str0, value_offset, tmp0); | |
263 __ ld(str0, offset_offset, tmp2); | |
264 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); | |
265 __ ld(str0, count_offset, str0); | |
266 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); | |
267 } else { | |
268 __ load_heap_oop(str0, value_offset, tmp1); | |
269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); | |
270 __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0); | |
271 } | |
0 | 272 |
273 // str1 may be null | |
274 add_debug_info_for_null_check_here(info); | |
275 | |
6057 | 276 if (java_lang_String::has_offset_field()) { |
277 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
278 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
279 __ load_heap_oop(str1, value_offset, tmp1); | |
280 __ add(tmp0, tmp2, tmp0); | |
281 | |
282 __ ld(str1, offset_offset, tmp2); | |
283 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); | |
284 __ ld(str1, count_offset, str1); | |
285 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); | |
286 __ add(tmp1, tmp2, tmp1); | |
287 } else { | |
288 __ load_heap_oop(str1, value_offset, tmp2); | |
289 __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); | |
290 __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1); | |
291 } | |
0 | 292 __ subcc(str0, str1, O7); |
293 } | |
294 | |
295 { | |
296 // Compute the minimum of the string lengths, scale it and store it in limit | |
297 Register count0 = I0; | |
298 Register count1 = I1; | |
299 Register limit = L3; | |
300 | |
301 Label Lskip; | |
302 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter | |
303 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
304 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter | |
305 __ bind(Lskip); | |
306 | |
307 // If either string is empty (or both of them) the result is the difference in lengths | |
308 __ cmp(limit, 0); | |
309 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
310 __ delayed()->mov(O7, result); // result is difference in lengths | |
311 } | |
312 | |
313 { | |
314 // Neither string is empty | |
315 Label Lloop; | |
316 | |
317 Register base0 = L0; | |
318 Register base1 = L1; | |
319 Register chr0 = I0; | |
320 Register chr1 = I1; | |
321 Register limit = L3; | |
322 | |
323 // Shift base0 and base1 to the end of the arrays, negate limit | |
324 __ add(base0, limit, base0); | |
325 __ add(base1, limit, base1); | |
6057 | 326 __ neg(limit); // limit = -min{string0.length(), string1.length()} |
0 | 327 |
328 __ lduh(base0, limit, chr0); | |
329 __ bind(Lloop); | |
330 __ lduh(base1, limit, chr1); | |
331 __ subcc(chr0, chr1, chr0); | |
332 __ br(Assembler::notZero, false, Assembler::pn, Ldone); | |
333 assert(chr0 == result, "result must be pre-placed"); | |
334 __ delayed()->inccc(limit, sizeof(jchar)); | |
335 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
336 __ delayed()->lduh(base0, limit, chr0); | |
337 } | |
338 | |
339 // If strings are equal up to min length, return the length difference. | |
340 __ mov(O7, result); | |
341 | |
342 // Otherwise, return the difference between the first mismatched chars. | |
343 __ bind(Ldone); | |
344 } | |
345 | |
346 | |
347 // -------------------------------------------------------------------------------------------- | |
348 | |
349 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { | |
350 if (!GenerateSynchronizationCode) return; | |
351 | |
352 Register obj_reg = obj_opr->as_register(); | |
353 Register lock_reg = lock_opr->as_register(); | |
354 | |
355 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
356 Register reg = mon_addr.base(); | |
357 int offset = mon_addr.disp(); | |
358 // compute pointer to BasicLock | |
359 if (mon_addr.is_simm13()) { | |
360 __ add(reg, offset, lock_reg); | |
361 } | |
362 else { | |
363 __ set(offset, lock_reg); | |
364 __ add(reg, lock_reg, lock_reg); | |
365 } | |
366 // unlock object | |
367 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); | |
368 // _slow_case_stubs->append(slow_case); | |
369 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
370 _slow_case_stubs->append(slow_case); | |
371 if (UseFastLocking) { | |
372 // try inlined fast unlocking first, revert to slow locking if it fails | |
373 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
374 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
375 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
376 } else { | |
377 // always do slow unlocking | |
378 // note: the slow unlocking code could be inlined here, however if we use | |
379 // slow unlocking, speed doesn't matter anyway and this solution is | |
380 // simpler and requires less duplicated code - additionally, the | |
381 // slow unlocking code is the same in either case which simplifies | |
382 // debugging | |
383 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); | |
384 __ delayed()->nop(); | |
385 } | |
386 // done | |
387 __ bind(*slow_case->continuation()); | |
388 } | |
389 | |
390 | |
1204 | 391 int LIR_Assembler::emit_exception_handler() { |
0 | 392 // if the last instruction is a call (typically to do a throw which |
393 // is coming at the end after block reordering) the return address | |
394 // must still point into the code area in order to avoid assertion | |
395 // failures when searching for the corresponding bci => add a nop | |
396 // (was bug 5/14/1999 - gri) | |
397 __ nop(); | |
398 | |
399 // generate code for exception handler | |
400 ciMethod* method = compilation()->method(); | |
401 | |
402 address handler_base = __ start_a_stub(exception_handler_size); | |
403 | |
404 if (handler_base == NULL) { | |
405 // not enough space left for the handler | |
406 bailout("exception handler overflow"); | |
1204 | 407 return -1; |
0 | 408 } |
1204 | 409 |
0 | 410 int offset = code_offset(); |
411 | |
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412 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); |
0 | 413 __ delayed()->nop(); |
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414 __ should_not_reach_here(); |
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415 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); |
0 | 416 __ end_a_stub(); |
1204 | 417 |
418 return offset; | |
0 | 419 } |
420 | |
1204 | 421 |
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422 // Emit the code to remove the frame from the stack in the exception |
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423 // unwind path. |
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424 int LIR_Assembler::emit_unwind_handler() { |
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425 #ifndef PRODUCT |
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426 if (CommentedAssembly) { |
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427 _masm->block_comment("Unwind handler"); |
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428 } |
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429 #endif |
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430 |
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431 int offset = code_offset(); |
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432 |
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433 // Fetch the exception from TLS and clear out exception related thread state |
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434 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); |
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435 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); |
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436 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
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437 |
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438 __ bind(_unwind_handler_entry); |
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439 __ verify_not_null_oop(O0); |
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440 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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441 __ mov(O0, I0); // Preserve the exception |
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442 } |
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443 |
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444 // Preform needed unlocking |
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445 MonitorExitStub* stub = NULL; |
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446 if (method()->is_synchronized()) { |
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447 monitor_address(0, FrameMap::I1_opr); |
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448 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); |
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449 __ unlock_object(I3, I2, I1, *stub->entry()); |
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450 __ bind(*stub->continuation()); |
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451 } |
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452 |
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453 if (compilation()->env()->dtrace_method_probes()) { |
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454 __ mov(G2_thread, O0); |
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455 __ save_thread(I1); // need to preserve thread in G2 across |
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456 // runtime call |
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457 metadata2reg(method()->constant_encoding(), O1); |
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458 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); |
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459 __ delayed()->nop(); |
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460 __ restore_thread(I1); |
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461 } |
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462 |
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463 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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464 __ mov(I0, O0); // Restore the exception |
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465 } |
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466 |
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467 // dispatch to the unwind logic |
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468 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
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469 __ delayed()->nop(); |
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470 |
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471 // Emit the slow path assembly |
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472 if (stub != NULL) { |
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473 stub->emit_code(this); |
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474 } |
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475 |
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476 return offset; |
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477 } |
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478 |
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479 |
1204 | 480 int LIR_Assembler::emit_deopt_handler() { |
0 | 481 // if the last instruction is a call (typically to do a throw which |
482 // is coming at the end after block reordering) the return address | |
483 // must still point into the code area in order to avoid assertion | |
484 // failures when searching for the corresponding bci => add a nop | |
485 // (was bug 5/14/1999 - gri) | |
486 __ nop(); | |
487 | |
488 // generate code for deopt handler | |
489 ciMethod* method = compilation()->method(); | |
490 address handler_base = __ start_a_stub(deopt_handler_size); | |
491 if (handler_base == NULL) { | |
492 // not enough space left for the handler | |
493 bailout("deopt handler overflow"); | |
1204 | 494 return -1; |
0 | 495 } |
1204 | 496 |
0 | 497 int offset = code_offset(); |
727 | 498 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
499 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp | |
0 | 500 __ delayed()->nop(); |
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501 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); |
0 | 502 __ end_a_stub(); |
1204 | 503 |
504 return offset; | |
0 | 505 } |
506 | |
507 | |
508 void LIR_Assembler::jobject2reg(jobject o, Register reg) { | |
509 if (o == NULL) { | |
510 __ set(NULL_WORD, reg); | |
511 } else { | |
512 int oop_index = __ oop_recorder()->find_index(o); | |
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513 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop"); |
0 | 514 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
515 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created | |
516 } | |
517 } | |
518 | |
519 | |
520 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { | |
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521 // Allocate a new index in table to hold the object once it's been patched |
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522 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); |
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523 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); |
0 | 524 |
727 | 525 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); |
526 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); | |
0 | 527 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
528 // NULL will be dynamically patched later and the patched value may be large. We must | |
529 // therefore generate the sethi/add as a placeholders | |
727 | 530 __ patchable_set(addrlit, reg); |
0 | 531 |
532 patching_epilog(patch, lir_patch_normal, reg, info); | |
533 } | |
534 | |
535 | |
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536 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { |
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537 __ set_metadata_constant(o, reg); |
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538 } |
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539 |
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540 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { |
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541 // Allocate a new index in table to hold the klass once it's been patched |
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542 int index = __ oop_recorder()->allocate_metadata_index(NULL); |
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543 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); |
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544 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index)); |
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545 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); |
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546 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
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547 // NULL will be dynamically patched later and the patched value may be large. We must |
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548 // therefore generate the sethi/add as a placeholders |
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549 __ patchable_set(addrlit, reg); |
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550 |
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551 patching_epilog(patch, lir_patch_normal, reg, info); |
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552 } |
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553 |
0 | 554 void LIR_Assembler::emit_op3(LIR_Op3* op) { |
555 Register Rdividend = op->in_opr1()->as_register(); | |
556 Register Rdivisor = noreg; | |
557 Register Rscratch = op->in_opr3()->as_register(); | |
558 Register Rresult = op->result_opr()->as_register(); | |
559 int divisor = -1; | |
560 | |
561 if (op->in_opr2()->is_register()) { | |
562 Rdivisor = op->in_opr2()->as_register(); | |
563 } else { | |
564 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); | |
565 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
566 } | |
567 | |
568 assert(Rdividend != Rscratch, ""); | |
569 assert(Rdivisor != Rscratch, ""); | |
570 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); | |
571 | |
572 if (Rdivisor == noreg && is_power_of_2(divisor)) { | |
573 // convert division by a power of two into some shifts and logical operations | |
574 if (op->code() == lir_idiv) { | |
575 if (divisor == 2) { | |
576 __ srl(Rdividend, 31, Rscratch); | |
577 } else { | |
578 __ sra(Rdividend, 31, Rscratch); | |
579 __ and3(Rscratch, divisor - 1, Rscratch); | |
580 } | |
581 __ add(Rdividend, Rscratch, Rscratch); | |
582 __ sra(Rscratch, log2_intptr(divisor), Rresult); | |
583 return; | |
584 } else { | |
585 if (divisor == 2) { | |
586 __ srl(Rdividend, 31, Rscratch); | |
587 } else { | |
588 __ sra(Rdividend, 31, Rscratch); | |
589 __ and3(Rscratch, divisor - 1,Rscratch); | |
590 } | |
591 __ add(Rdividend, Rscratch, Rscratch); | |
592 __ andn(Rscratch, divisor - 1,Rscratch); | |
593 __ sub(Rdividend, Rscratch, Rresult); | |
594 return; | |
595 } | |
596 } | |
597 | |
598 __ sra(Rdividend, 31, Rscratch); | |
599 __ wry(Rscratch); | |
600 | |
601 add_debug_info_for_div0_here(op->info()); | |
602 | |
603 if (Rdivisor != noreg) { | |
604 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
605 } else { | |
606 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
607 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
608 } | |
609 | |
610 Label skip; | |
611 __ br(Assembler::overflowSet, true, Assembler::pn, skip); | |
612 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
613 __ bind(skip); | |
614 | |
615 if (op->code() == lir_irem) { | |
616 if (Rdivisor != noreg) { | |
617 __ smul(Rscratch, Rdivisor, Rscratch); | |
618 } else { | |
619 __ smul(Rscratch, divisor, Rscratch); | |
620 } | |
621 __ sub(Rdividend, Rscratch, Rresult); | |
622 } | |
623 } | |
624 | |
625 | |
626 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
627 #ifdef ASSERT | |
628 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
629 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
630 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
631 #endif | |
632 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); | |
633 | |
634 if (op->cond() == lir_cond_always) { | |
635 __ br(Assembler::always, false, Assembler::pt, *(op->label())); | |
636 } else if (op->code() == lir_cond_float_branch) { | |
637 assert(op->ublock() != NULL, "must have unordered successor"); | |
638 bool is_unordered = (op->ublock() == op->block()); | |
639 Assembler::Condition acond; | |
640 switch (op->cond()) { | |
641 case lir_cond_equal: acond = Assembler::f_equal; break; | |
642 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; | |
643 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; | |
644 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; | |
645 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; | |
646 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; | |
647 default : ShouldNotReachHere(); | |
648 } | |
649 __ fb( acond, false, Assembler::pn, *(op->label())); | |
650 } else { | |
651 assert (op->code() == lir_branch, "just checking"); | |
652 | |
653 Assembler::Condition acond; | |
654 switch (op->cond()) { | |
655 case lir_cond_equal: acond = Assembler::equal; break; | |
656 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
657 case lir_cond_less: acond = Assembler::less; break; | |
658 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
659 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
660 case lir_cond_greater: acond = Assembler::greater; break; | |
661 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
662 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
663 default: ShouldNotReachHere(); | |
664 }; | |
665 | |
666 // sparc has different condition codes for testing 32-bit | |
667 // vs. 64-bit values. We could always test xcc is we could | |
668 // guarantee that 32-bit loads always sign extended but that isn't | |
669 // true and since sign extension isn't free, it would impose a | |
670 // slight cost. | |
671 #ifdef _LP64 | |
672 if (op->type() == T_INT) { | |
673 __ br(acond, false, Assembler::pn, *(op->label())); | |
674 } else | |
675 #endif | |
676 __ brx(acond, false, Assembler::pn, *(op->label())); | |
677 } | |
678 // The peephole pass fills the delay slot | |
679 } | |
680 | |
681 | |
682 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
683 Bytecodes::Code code = op->bytecode(); | |
684 LIR_Opr dst = op->result_opr(); | |
685 | |
686 switch(code) { | |
687 case Bytecodes::_i2l: { | |
688 Register rlo = dst->as_register_lo(); | |
689 Register rhi = dst->as_register_hi(); | |
690 Register rval = op->in_opr()->as_register(); | |
691 #ifdef _LP64 | |
692 __ sra(rval, 0, rlo); | |
693 #else | |
694 __ mov(rval, rlo); | |
695 __ sra(rval, BitsPerInt-1, rhi); | |
696 #endif | |
697 break; | |
698 } | |
699 case Bytecodes::_i2d: | |
700 case Bytecodes::_i2f: { | |
701 bool is_double = (code == Bytecodes::_i2d); | |
702 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
703 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
704 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
705 if (rsrc != rdst) { | |
706 __ fmov(FloatRegisterImpl::S, rsrc, rdst); | |
707 } | |
708 __ fitof(w, rdst, rdst); | |
709 break; | |
710 } | |
711 case Bytecodes::_f2i:{ | |
712 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
713 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); | |
714 Label L; | |
715 // result must be 0 if value is NaN; test by comparing value to itself | |
716 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); | |
717 __ fb(Assembler::f_unordered, true, Assembler::pn, L); | |
718 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN | |
719 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); | |
720 // move integer result from float register to int register | |
721 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); | |
722 __ bind (L); | |
723 break; | |
724 } | |
725 case Bytecodes::_l2i: { | |
726 Register rlo = op->in_opr()->as_register_lo(); | |
727 Register rhi = op->in_opr()->as_register_hi(); | |
728 Register rdst = dst->as_register(); | |
729 #ifdef _LP64 | |
730 __ sra(rlo, 0, rdst); | |
731 #else | |
732 __ mov(rlo, rdst); | |
733 #endif | |
734 break; | |
735 } | |
736 case Bytecodes::_d2f: | |
737 case Bytecodes::_f2d: { | |
738 bool is_double = (code == Bytecodes::_f2d); | |
739 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); | |
740 LIR_Opr val = op->in_opr(); | |
741 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); | |
742 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
743 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; | |
744 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
745 __ ftof(vw, dw, rval, rdst); | |
746 break; | |
747 } | |
748 case Bytecodes::_i2s: | |
749 case Bytecodes::_i2b: { | |
750 Register rval = op->in_opr()->as_register(); | |
751 Register rdst = dst->as_register(); | |
752 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); | |
753 __ sll (rval, shift, rdst); | |
754 __ sra (rdst, shift, rdst); | |
755 break; | |
756 } | |
757 case Bytecodes::_i2c: { | |
758 Register rval = op->in_opr()->as_register(); | |
759 Register rdst = dst->as_register(); | |
760 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; | |
761 __ sll (rval, shift, rdst); | |
762 __ srl (rdst, shift, rdst); | |
763 break; | |
764 } | |
765 | |
766 default: ShouldNotReachHere(); | |
767 } | |
768 } | |
769 | |
770 | |
771 void LIR_Assembler::align_call(LIR_Code) { | |
772 // do nothing since all instructions are word aligned on sparc | |
773 } | |
774 | |
775 | |
1295 | 776 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
777 __ call(op->addr(), rtype); | |
1564 | 778 // The peephole pass fills the delay slot, add_call_info is done in |
779 // LIR_Assembler::emit_delay. | |
0 | 780 } |
781 | |
782 | |
1295 | 783 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
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784 __ ic_call(op->addr(), false); |
1564 | 785 // The peephole pass fills the delay slot, add_call_info is done in |
786 // LIR_Assembler::emit_delay. | |
0 | 787 } |
788 | |
789 | |
1295 | 790 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
791 add_debug_info_for_null_check_here(op->info()); | |
2002 | 792 __ load_klass(O0, G3_scratch); |
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793 if (Assembler::is_simm13(op->vtable_offset())) { |
1295 | 794 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); |
0 | 795 } else { |
796 // This will generate 2 instructions | |
1295 | 797 __ set(op->vtable_offset(), G5_method); |
0 | 798 // ld_ptr, set_hi, set |
799 __ ld_ptr(G3_scratch, G5_method, G5_method); | |
800 } | |
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801 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch); |
0 | 802 __ callr(G3_scratch, G0); |
803 // the peephole pass fills the delay slot | |
804 } | |
805 | |
2002 | 806 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { |
0 | 807 int store_offset; |
808 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
809 assert(!unaligned, "can't handle this"); | |
810 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 811 __ set(offset, O7); |
2002 | 812 store_offset = store(from_reg, base, O7, type, wide); |
0 | 813 } else { |
2002 | 814 if (type == T_ARRAY || type == T_OBJECT) { |
815 __ verify_oop(from_reg->as_register()); | |
816 } | |
0 | 817 store_offset = code_offset(); |
818 switch (type) { | |
819 case T_BOOLEAN: // fall through | |
820 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; | |
821 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; | |
822 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; | |
823 case T_INT : __ stw(from_reg->as_register(), base, offset); break; | |
824 case T_LONG : | |
825 #ifdef _LP64 | |
826 if (unaligned || PatchALot) { | |
827 __ srax(from_reg->as_register_lo(), 32, O7); | |
828 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
829 __ stw(O7, base, offset + hi_word_offset_in_bytes); | |
830 } else { | |
831 __ stx(from_reg->as_register_lo(), base, offset); | |
832 } | |
833 #else | |
834 assert(Assembler::is_simm13(offset + 4), "must be"); | |
835 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
836 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); | |
837 #endif | |
838 break; | |
2002 | 839 case T_ADDRESS: |
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840 case T_METADATA: |
2002 | 841 __ st_ptr(from_reg->as_register(), base, offset); |
842 break; | |
0 | 843 case T_ARRAY : // fall through |
2002 | 844 case T_OBJECT: |
845 { | |
846 if (UseCompressedOops && !wide) { | |
847 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
848 store_offset = code_offset(); | |
849 __ stw(G3_scratch, base, offset); | |
850 } else { | |
851 __ st_ptr(from_reg->as_register(), base, offset); | |
852 } | |
853 break; | |
854 } | |
855 | |
0 | 856 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; |
857 case T_DOUBLE: | |
858 { | |
859 FloatRegister reg = from_reg->as_double_reg(); | |
860 // split unaligned stores | |
861 if (unaligned || PatchALot) { | |
862 assert(Assembler::is_simm13(offset + 4), "must be"); | |
863 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); | |
864 __ stf(FloatRegisterImpl::S, reg, base, offset); | |
865 } else { | |
866 __ stf(FloatRegisterImpl::D, reg, base, offset); | |
867 } | |
868 break; | |
869 } | |
870 default : ShouldNotReachHere(); | |
871 } | |
872 } | |
873 return store_offset; | |
874 } | |
875 | |
876 | |
2002 | 877 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { |
878 if (type == T_ARRAY || type == T_OBJECT) { | |
879 __ verify_oop(from_reg->as_register()); | |
880 } | |
0 | 881 int store_offset = code_offset(); |
882 switch (type) { | |
883 case T_BOOLEAN: // fall through | |
884 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; | |
885 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; | |
886 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; | |
887 case T_INT : __ stw(from_reg->as_register(), base, disp); break; | |
888 case T_LONG : | |
889 #ifdef _LP64 | |
890 __ stx(from_reg->as_register_lo(), base, disp); | |
891 #else | |
892 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); | |
893 __ std(from_reg->as_register_hi(), base, disp); | |
894 #endif | |
895 break; | |
2002 | 896 case T_ADDRESS: |
897 __ st_ptr(from_reg->as_register(), base, disp); | |
898 break; | |
0 | 899 case T_ARRAY : // fall through |
2002 | 900 case T_OBJECT: |
901 { | |
902 if (UseCompressedOops && !wide) { | |
903 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
904 store_offset = code_offset(); | |
905 __ stw(G3_scratch, base, disp); | |
906 } else { | |
907 __ st_ptr(from_reg->as_register(), base, disp); | |
908 } | |
909 break; | |
910 } | |
0 | 911 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; |
912 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; | |
913 default : ShouldNotReachHere(); | |
914 } | |
915 return store_offset; | |
916 } | |
917 | |
918 | |
2002 | 919 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { |
0 | 920 int load_offset; |
921 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
922 assert(base != O7, "destroying register"); | |
923 assert(!unaligned, "can't handle this"); | |
924 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 925 __ set(offset, O7); |
2002 | 926 load_offset = load(base, O7, to_reg, type, wide); |
0 | 927 } else { |
928 load_offset = code_offset(); | |
929 switch(type) { | |
930 case T_BOOLEAN: // fall through | |
931 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; | |
932 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; | |
933 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; | |
934 case T_INT : __ ld(base, offset, to_reg->as_register()); break; | |
935 case T_LONG : | |
936 if (!unaligned) { | |
937 #ifdef _LP64 | |
938 __ ldx(base, offset, to_reg->as_register_lo()); | |
939 #else | |
940 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
941 "must be sequential"); | |
942 __ ldd(base, offset, to_reg->as_register_hi()); | |
943 #endif | |
944 } else { | |
945 #ifdef _LP64 | |
946 assert(base != to_reg->as_register_lo(), "can't handle this"); | |
1060 | 947 assert(O7 != to_reg->as_register_lo(), "can't handle this"); |
0 | 948 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); |
1060 | 949 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last |
0 | 950 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); |
1060 | 951 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); |
0 | 952 #else |
953 if (base == to_reg->as_register_lo()) { | |
954 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
955 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
956 } else { | |
957 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
958 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
959 } | |
960 #endif | |
961 } | |
962 break; | |
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963 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break; |
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964 case T_ADDRESS: |
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965 #ifdef _LP64 |
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966 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) { |
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967 __ lduw(base, offset, to_reg->as_register()); |
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968 __ decode_klass_not_null(to_reg->as_register()); |
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969 } else |
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970 #endif |
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971 { |
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972 __ ld_ptr(base, offset, to_reg->as_register()); |
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973 } |
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974 break; |
0 | 975 case T_ARRAY : // fall through |
2002 | 976 case T_OBJECT: |
977 { | |
978 if (UseCompressedOops && !wide) { | |
979 __ lduw(base, offset, to_reg->as_register()); | |
980 __ decode_heap_oop(to_reg->as_register()); | |
981 } else { | |
982 __ ld_ptr(base, offset, to_reg->as_register()); | |
983 } | |
984 break; | |
985 } | |
0 | 986 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; |
987 case T_DOUBLE: | |
988 { | |
989 FloatRegister reg = to_reg->as_double_reg(); | |
990 // split unaligned loads | |
991 if (unaligned || PatchALot) { | |
1060 | 992 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); |
993 __ ldf(FloatRegisterImpl::S, base, offset, reg); | |
0 | 994 } else { |
995 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); | |
996 } | |
997 break; | |
998 } | |
999 default : ShouldNotReachHere(); | |
1000 } | |
2002 | 1001 if (type == T_ARRAY || type == T_OBJECT) { |
1002 __ verify_oop(to_reg->as_register()); | |
1003 } | |
0 | 1004 } |
1005 return load_offset; | |
1006 } | |
1007 | |
1008 | |
2002 | 1009 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { |
0 | 1010 int load_offset = code_offset(); |
1011 switch(type) { | |
1012 case T_BOOLEAN: // fall through | |
2002 | 1013 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; |
1014 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; | |
1015 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; | |
1016 case T_INT : __ ld(base, disp, to_reg->as_register()); break; | |
1017 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; | |
0 | 1018 case T_ARRAY : // fall through |
2002 | 1019 case T_OBJECT: |
1020 { | |
1021 if (UseCompressedOops && !wide) { | |
1022 __ lduw(base, disp, to_reg->as_register()); | |
1023 __ decode_heap_oop(to_reg->as_register()); | |
1024 } else { | |
1025 __ ld_ptr(base, disp, to_reg->as_register()); | |
1026 } | |
1027 break; | |
1028 } | |
0 | 1029 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; |
1030 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; | |
1031 case T_LONG : | |
1032 #ifdef _LP64 | |
1033 __ ldx(base, disp, to_reg->as_register_lo()); | |
1034 #else | |
1035 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
1036 "must be sequential"); | |
1037 __ ldd(base, disp, to_reg->as_register_hi()); | |
1038 #endif | |
1039 break; | |
1040 default : ShouldNotReachHere(); | |
1041 } | |
2002 | 1042 if (type == T_ARRAY || type == T_OBJECT) { |
1043 __ verify_oop(to_reg->as_register()); | |
1044 } | |
0 | 1045 return load_offset; |
1046 } | |
1047 | |
1048 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
1049 LIR_Const* c = src->as_constant_ptr(); | |
1050 switch (c->type()) { | |
1051 case T_INT: | |
2002 | 1052 case T_FLOAT: { |
1053 Register src_reg = O7; | |
1054 int value = c->as_jint_bits(); | |
1055 if (value == 0) { | |
1056 src_reg = G0; | |
1057 } else { | |
1058 __ set(value, O7); | |
1059 } | |
1060 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1061 __ stw(src_reg, addr.base(), addr.disp()); | |
1062 break; | |
1063 } | |
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1064 case T_ADDRESS: { |
0 | 1065 Register src_reg = O7; |
1066 int value = c->as_jint_bits(); | |
1067 if (value == 0) { | |
1068 src_reg = G0; | |
1069 } else { | |
1070 __ set(value, O7); | |
1071 } | |
1072 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
2002 | 1073 __ st_ptr(src_reg, addr.base(), addr.disp()); |
0 | 1074 break; |
1075 } | |
1076 case T_OBJECT: { | |
1077 Register src_reg = O7; | |
1078 jobject2reg(c->as_jobject(), src_reg); | |
1079 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1080 __ st_ptr(src_reg, addr.base(), addr.disp()); | |
1081 break; | |
1082 } | |
1083 case T_LONG: | |
1084 case T_DOUBLE: { | |
1085 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1086 | |
1087 Register tmp = O7; | |
1088 int value_lo = c->as_jint_lo_bits(); | |
1089 if (value_lo == 0) { | |
1090 tmp = G0; | |
1091 } else { | |
1092 __ set(value_lo, O7); | |
1093 } | |
1094 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); | |
1095 int value_hi = c->as_jint_hi_bits(); | |
1096 if (value_hi == 0) { | |
1097 tmp = G0; | |
1098 } else { | |
1099 __ set(value_hi, O7); | |
1100 } | |
1101 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); | |
1102 break; | |
1103 } | |
1104 default: | |
1105 Unimplemented(); | |
1106 } | |
1107 } | |
1108 | |
1109 | |
2002 | 1110 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
0 | 1111 LIR_Const* c = src->as_constant_ptr(); |
1112 LIR_Address* addr = dest->as_address_ptr(); | |
1113 Register base = addr->base()->as_pointer_register(); | |
2002 | 1114 int offset = -1; |
1115 | |
0 | 1116 switch (c->type()) { |
1117 case T_INT: | |
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1118 case T_FLOAT: |
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1119 case T_ADDRESS: { |
0 | 1120 LIR_Opr tmp = FrameMap::O7_opr; |
1121 int value = c->as_jint_bits(); | |
1122 if (value == 0) { | |
1123 tmp = FrameMap::G0_opr; | |
1124 } else if (Assembler::is_simm13(value)) { | |
1125 __ set(value, O7); | |
1126 } | |
1127 if (addr->index()->is_valid()) { | |
1128 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1129 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1130 } else { |
1131 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1132 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1133 } |
1134 break; | |
1135 } | |
1136 case T_LONG: | |
1137 case T_DOUBLE: { | |
1138 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); | |
1139 assert(Assembler::is_simm13(addr->disp()) && | |
1140 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); | |
1141 | |
2002 | 1142 LIR_Opr tmp = FrameMap::O7_opr; |
0 | 1143 int value_lo = c->as_jint_lo_bits(); |
1144 if (value_lo == 0) { | |
2002 | 1145 tmp = FrameMap::G0_opr; |
0 | 1146 } else { |
1147 __ set(value_lo, O7); | |
1148 } | |
2002 | 1149 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); |
0 | 1150 int value_hi = c->as_jint_hi_bits(); |
1151 if (value_hi == 0) { | |
2002 | 1152 tmp = FrameMap::G0_opr; |
0 | 1153 } else { |
1154 __ set(value_hi, O7); | |
1155 } | |
4052 | 1156 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); |
0 | 1157 break; |
1158 } | |
1159 case T_OBJECT: { | |
1160 jobject obj = c->as_jobject(); | |
1161 LIR_Opr tmp; | |
1162 if (obj == NULL) { | |
1163 tmp = FrameMap::G0_opr; | |
1164 } else { | |
1165 tmp = FrameMap::O7_opr; | |
1166 jobject2reg(c->as_jobject(), O7); | |
1167 } | |
1168 // handle either reg+reg or reg+disp address | |
1169 if (addr->index()->is_valid()) { | |
1170 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1171 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1172 } else { |
1173 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1174 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1175 } |
1176 | |
1177 break; | |
1178 } | |
1179 default: | |
1180 Unimplemented(); | |
1181 } | |
2002 | 1182 if (info != NULL) { |
1183 assert(offset != -1, "offset should've been set"); | |
1184 add_debug_info_for_null_check(offset, info); | |
1185 } | |
0 | 1186 } |
1187 | |
1188 | |
1189 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
1190 LIR_Const* c = src->as_constant_ptr(); | |
1191 LIR_Opr to_reg = dest; | |
1192 | |
1193 switch (c->type()) { | |
1194 case T_INT: | |
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1195 case T_ADDRESS: |
0 | 1196 { |
1197 jint con = c->as_jint(); | |
1198 if (to_reg->is_single_cpu()) { | |
1199 assert(patch_code == lir_patch_none, "no patching handled here"); | |
1200 __ set(con, to_reg->as_register()); | |
1201 } else { | |
1202 ShouldNotReachHere(); | |
1203 assert(to_reg->is_single_fpu(), "wrong register kind"); | |
1204 | |
1205 __ set(con, O7); | |
727 | 1206 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); |
0 | 1207 __ st(O7, temp_slot); |
1208 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); | |
1209 } | |
1210 } | |
1211 break; | |
1212 | |
1213 case T_LONG: | |
1214 { | |
1215 jlong con = c->as_jlong(); | |
1216 | |
1217 if (to_reg->is_double_cpu()) { | |
1218 #ifdef _LP64 | |
1219 __ set(con, to_reg->as_register_lo()); | |
1220 #else | |
1221 __ set(low(con), to_reg->as_register_lo()); | |
1222 __ set(high(con), to_reg->as_register_hi()); | |
1223 #endif | |
1224 #ifdef _LP64 | |
1225 } else if (to_reg->is_single_cpu()) { | |
1226 __ set(con, to_reg->as_register()); | |
1227 #endif | |
1228 } else { | |
1229 ShouldNotReachHere(); | |
1230 assert(to_reg->is_double_fpu(), "wrong register kind"); | |
727 | 1231 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
1232 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); | |
0 | 1233 __ set(low(con), O7); |
1234 __ st(O7, temp_slot_lo); | |
1235 __ set(high(con), O7); | |
1236 __ st(O7, temp_slot_hi); | |
1237 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); | |
1238 } | |
1239 } | |
1240 break; | |
1241 | |
1242 case T_OBJECT: | |
1243 { | |
1244 if (patch_code == lir_patch_none) { | |
1245 jobject2reg(c->as_jobject(), to_reg->as_register()); | |
1246 } else { | |
1247 jobject2reg_with_patching(to_reg->as_register(), info); | |
1248 } | |
1249 } | |
1250 break; | |
1251 | |
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1252 case T_METADATA: |
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1253 { |
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1254 if (patch_code == lir_patch_none) { |
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1255 metadata2reg(c->as_metadata(), to_reg->as_register()); |
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1256 } else { |
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1257 klass2reg_with_patching(to_reg->as_register(), info); |
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1258 } |
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1259 } |
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1260 break; |
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1261 |
0 | 1262 case T_FLOAT: |
1263 { | |
1264 address const_addr = __ float_constant(c->as_jfloat()); | |
1265 if (const_addr == NULL) { | |
1266 bailout("const section overflow"); | |
1267 break; | |
1268 } | |
1269 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
727 | 1270 AddressLiteral const_addrlit(const_addr, rspec); |
0 | 1271 if (to_reg->is_single_fpu()) { |
727 | 1272 __ patchable_sethi(const_addrlit, O7); |
0 | 1273 __ relocate(rspec); |
727 | 1274 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); |
0 | 1275 |
1276 } else { | |
1277 assert(to_reg->is_single_cpu(), "Must be a cpu register."); | |
1278 | |
727 | 1279 __ set(const_addrlit, O7); |
2002 | 1280 __ ld(O7, 0, to_reg->as_register()); |
0 | 1281 } |
1282 } | |
1283 break; | |
1284 | |
1285 case T_DOUBLE: | |
1286 { | |
1287 address const_addr = __ double_constant(c->as_jdouble()); | |
1288 if (const_addr == NULL) { | |
1289 bailout("const section overflow"); | |
1290 break; | |
1291 } | |
1292 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
1293 | |
1294 if (to_reg->is_double_fpu()) { | |
727 | 1295 AddressLiteral const_addrlit(const_addr, rspec); |
1296 __ patchable_sethi(const_addrlit, O7); | |
0 | 1297 __ relocate(rspec); |
727 | 1298 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); |
0 | 1299 } else { |
1300 assert(to_reg->is_double_cpu(), "Must be a long register."); | |
1301 #ifdef _LP64 | |
1302 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); | |
1303 #else | |
1304 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); | |
1305 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); | |
1306 #endif | |
1307 } | |
1308 | |
1309 } | |
1310 break; | |
1311 | |
1312 default: | |
1313 ShouldNotReachHere(); | |
1314 } | |
1315 } | |
1316 | |
1317 Address LIR_Assembler::as_Address(LIR_Address* addr) { | |
14909 | 1318 Register reg = addr->base()->as_register(); |
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1319 LIR_Opr index = addr->index(); |
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1320 if (index->is_illegal()) { |
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1321 return Address(reg, addr->disp()); |
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1322 } else { |
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1323 assert (addr->disp() == 0, "unsupported address mode"); |
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1324 return Address(reg, index->as_pointer_register()); |
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1325 } |
0 | 1326 } |
1327 | |
1328 | |
1329 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1330 switch (type) { | |
1331 case T_INT: | |
1332 case T_FLOAT: { | |
1333 Register tmp = O7; | |
1334 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1335 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1336 __ lduw(from.base(), from.disp(), tmp); | |
1337 __ stw(tmp, to.base(), to.disp()); | |
1338 break; | |
1339 } | |
1340 case T_OBJECT: { | |
1341 Register tmp = O7; | |
1342 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1343 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1344 __ ld_ptr(from.base(), from.disp(), tmp); | |
1345 __ st_ptr(tmp, to.base(), to.disp()); | |
1346 break; | |
1347 } | |
1348 case T_LONG: | |
1349 case T_DOUBLE: { | |
1350 Register tmp = O7; | |
1351 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1352 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1353 __ lduw(from.base(), from.disp(), tmp); | |
1354 __ stw(tmp, to.base(), to.disp()); | |
1355 __ lduw(from.base(), from.disp() + 4, tmp); | |
1356 __ stw(tmp, to.base(), to.disp() + 4); | |
1357 break; | |
1358 } | |
1359 | |
1360 default: | |
1361 ShouldNotReachHere(); | |
1362 } | |
1363 } | |
1364 | |
1365 | |
1366 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
1367 Address base = as_Address(addr); | |
727 | 1368 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); |
0 | 1369 } |
1370 | |
1371 | |
1372 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
1373 Address base = as_Address(addr); | |
727 | 1374 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); |
0 | 1375 } |
1376 | |
1377 | |
1378 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, | |
2002 | 1379 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { |
0 | 1380 |
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1381 assert(type != T_METADATA, "load of metadata ptr not supported"); |
0 | 1382 LIR_Address* addr = src_opr->as_address_ptr(); |
1383 LIR_Opr to_reg = dest; | |
1384 | |
1385 Register src = addr->base()->as_pointer_register(); | |
1386 Register disp_reg = noreg; | |
1387 int disp_value = addr->disp(); | |
1388 bool needs_patching = (patch_code != lir_patch_none); | |
1389 | |
1390 if (addr->base()->type() == T_OBJECT) { | |
1391 __ verify_oop(src); | |
1392 } | |
1393 | |
1394 PatchingStub* patch = NULL; | |
1395 if (needs_patching) { | |
1396 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1397 assert(!to_reg->is_double_cpu() || | |
1398 patch_code == lir_patch_none || | |
1399 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1400 } | |
1401 | |
1402 if (addr->index()->is_illegal()) { | |
1403 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1404 if (needs_patching) { | |
727 | 1405 __ patchable_set(0, O7); |
0 | 1406 } else { |
1407 __ set(disp_value, O7); | |
1408 } | |
1409 disp_reg = O7; | |
1410 } | |
1411 } else if (unaligned || PatchALot) { | |
1412 __ add(src, addr->index()->as_register(), O7); | |
1413 src = O7; | |
1414 } else { | |
1415 disp_reg = addr->index()->as_pointer_register(); | |
1416 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1417 } | |
1418 | |
1419 // remember the offset of the load. The patching_epilog must be done | |
1420 // before the call to add_debug_info, otherwise the PcDescs don't get | |
1421 // entered in increasing order. | |
1422 int offset = code_offset(); | |
1423 | |
1424 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1425 if (disp_reg == noreg) { | |
2002 | 1426 offset = load(src, disp_value, to_reg, type, wide, unaligned); |
0 | 1427 } else { |
1428 assert(!unaligned, "can't handle this"); | |
2002 | 1429 offset = load(src, disp_reg, to_reg, type, wide); |
0 | 1430 } |
1431 | |
1432 if (patch != NULL) { | |
1433 patching_epilog(patch, patch_code, src, info); | |
1434 } | |
1435 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1436 } | |
1437 | |
1438 | |
1439 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1440 LIR_Address* addr = src->as_address_ptr(); | |
1441 Address from_addr = as_Address(addr); | |
1442 | |
1443 if (VM_Version::has_v9()) { | |
1444 __ prefetch(from_addr, Assembler::severalReads); | |
1445 } | |
1446 } | |
1447 | |
1448 | |
1449 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1450 LIR_Address* addr = src->as_address_ptr(); | |
1451 Address from_addr = as_Address(addr); | |
1452 | |
1453 if (VM_Version::has_v9()) { | |
1454 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); | |
1455 } | |
1456 } | |
1457 | |
1458 | |
1459 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1460 Address addr; | |
1461 if (src->is_single_word()) { | |
1462 addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1463 } else if (src->is_double_word()) { | |
1464 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1465 } | |
1466 | |
1467 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1468 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); |
0 | 1469 } |
1470 | |
1471 | |
1472 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
1473 Address addr; | |
1474 if (dest->is_single_word()) { | |
1475 addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1476 } else if (dest->is_double_word()) { | |
1477 addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
1478 } | |
1479 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1480 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); |
0 | 1481 } |
1482 | |
1483 | |
1484 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { | |
1485 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { | |
1486 if (from_reg->is_double_fpu()) { | |
1487 // double to double moves | |
1488 assert(to_reg->is_double_fpu(), "should match"); | |
1489 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); | |
1490 } else { | |
1491 // float to float moves | |
1492 assert(to_reg->is_single_fpu(), "should match"); | |
1493 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); | |
1494 } | |
1495 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { | |
1496 if (from_reg->is_double_cpu()) { | |
1497 #ifdef _LP64 | |
1498 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); | |
1499 #else | |
1500 assert(to_reg->is_double_cpu() && | |
1501 from_reg->as_register_hi() != to_reg->as_register_lo() && | |
1502 from_reg->as_register_lo() != to_reg->as_register_hi(), | |
1503 "should both be long and not overlap"); | |
1504 // long to long moves | |
1505 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); | |
1506 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); | |
1507 #endif | |
1508 #ifdef _LP64 | |
1509 } else if (to_reg->is_double_cpu()) { | |
1510 // int to int moves | |
1511 __ mov(from_reg->as_register(), to_reg->as_register_lo()); | |
1512 #endif | |
1513 } else { | |
1514 // int to int moves | |
1515 __ mov(from_reg->as_register(), to_reg->as_register()); | |
1516 } | |
1517 } else { | |
1518 ShouldNotReachHere(); | |
1519 } | |
1520 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { | |
1521 __ verify_oop(to_reg->as_register()); | |
1522 } | |
1523 } | |
1524 | |
1525 | |
1526 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, | |
1527 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, | |
2002 | 1528 bool wide, bool unaligned) { |
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1529 assert(type != T_METADATA, "store of metadata ptr not supported"); |
0 | 1530 LIR_Address* addr = dest->as_address_ptr(); |
1531 | |
1532 Register src = addr->base()->as_pointer_register(); | |
1533 Register disp_reg = noreg; | |
1534 int disp_value = addr->disp(); | |
1535 bool needs_patching = (patch_code != lir_patch_none); | |
1536 | |
1537 if (addr->base()->is_oop_register()) { | |
1538 __ verify_oop(src); | |
1539 } | |
1540 | |
1541 PatchingStub* patch = NULL; | |
1542 if (needs_patching) { | |
1543 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1544 assert(!from_reg->is_double_cpu() || | |
1545 patch_code == lir_patch_none || | |
1546 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1547 } | |
1548 | |
1549 if (addr->index()->is_illegal()) { | |
1550 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1551 if (needs_patching) { | |
727 | 1552 __ patchable_set(0, O7); |
0 | 1553 } else { |
1554 __ set(disp_value, O7); | |
1555 } | |
1556 disp_reg = O7; | |
1557 } | |
1558 } else if (unaligned || PatchALot) { | |
1559 __ add(src, addr->index()->as_register(), O7); | |
1560 src = O7; | |
1561 } else { | |
1562 disp_reg = addr->index()->as_pointer_register(); | |
1563 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1564 } | |
1565 | |
1566 // remember the offset of the store. The patching_epilog must be done | |
1567 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get | |
1568 // entered in increasing order. | |
1569 int offset; | |
1570 | |
1571 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1572 if (disp_reg == noreg) { | |
2002 | 1573 offset = store(from_reg, src, disp_value, type, wide, unaligned); |
0 | 1574 } else { |
1575 assert(!unaligned, "can't handle this"); | |
2002 | 1576 offset = store(from_reg, src, disp_reg, type, wide); |
0 | 1577 } |
1578 | |
1579 if (patch != NULL) { | |
1580 patching_epilog(patch, patch_code, src, info); | |
1581 } | |
1582 | |
1583 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1584 } | |
1585 | |
1586 | |
1587 void LIR_Assembler::return_op(LIR_Opr result) { | |
1588 // the poll may need a register so just pick one that isn't the return register | |
1783 | 1589 #if defined(TIERED) && !defined(_LP64) |
0 | 1590 if (result->type_field() == LIR_OprDesc::long_type) { |
1591 // Must move the result to G1 | |
1592 // Must leave proper result in O0,O1 and G1 (TIERED only) | |
1593 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
1594 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
1595 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
1783 | 1596 #ifdef ASSERT |
1597 // mangle it so any problems will show up | |
1598 __ set(0xdeadbeef, I0); | |
1599 __ set(0xdeadbeef, I1); | |
1600 #endif | |
0 | 1601 } |
1602 #endif // TIERED | |
1603 __ set((intptr_t)os::get_polling_page(), L0); | |
1604 __ relocate(relocInfo::poll_return_type); | |
1605 __ ld_ptr(L0, 0, G0); | |
1606 __ ret(); | |
1607 __ delayed()->restore(); | |
1608 } | |
1609 | |
1610 | |
1611 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
1612 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); | |
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1613 __ relocate(relocInfo::poll_type); |
0 | 1614 if (info != NULL) { |
1615 add_debug_info_for_branch(info); | |
1616 } | |
1617 | |
1618 int offset = __ offset(); | |
1619 __ ld_ptr(tmp->as_register(), 0, G0); | |
1620 | |
1621 return offset; | |
1622 } | |
1623 | |
1624 | |
1625 void LIR_Assembler::emit_static_call_stub() { | |
1626 address call_pc = __ pc(); | |
1627 address stub = __ start_a_stub(call_stub_size); | |
1628 if (stub == NULL) { | |
1629 bailout("static call stub overflow"); | |
1630 return; | |
1631 } | |
1632 | |
1633 int start = __ offset(); | |
1634 __ relocate(static_stub_Relocation::spec(call_pc)); | |
1635 | |
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1636 __ set_metadata(NULL, G5); |
0 | 1637 // must be set to -1 at code generation time |
727 | 1638 AddressLiteral addrlit(-1); |
1639 __ jump_to(addrlit, G3); | |
0 | 1640 __ delayed()->nop(); |
1641 | |
1642 assert(__ offset() - start <= call_stub_size, "stub too big"); | |
1643 __ end_a_stub(); | |
1644 } | |
1645 | |
1646 | |
1647 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
1648 if (opr1->is_single_fpu()) { | |
1649 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); | |
1650 } else if (opr1->is_double_fpu()) { | |
1651 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); | |
1652 } else if (opr1->is_single_cpu()) { | |
1653 if (opr2->is_constant()) { | |
1654 switch (opr2->as_constant_ptr()->type()) { | |
1655 case T_INT: | |
1656 { jint con = opr2->as_constant_ptr()->as_jint(); | |
1657 if (Assembler::is_simm13(con)) { | |
1658 __ cmp(opr1->as_register(), con); | |
1659 } else { | |
1660 __ set(con, O7); | |
1661 __ cmp(opr1->as_register(), O7); | |
1662 } | |
1663 } | |
1664 break; | |
1665 | |
1666 case T_OBJECT: | |
1667 // there are only equal/notequal comparisions on objects | |
1668 { jobject con = opr2->as_constant_ptr()->as_jobject(); | |
1669 if (con == NULL) { | |
1670 __ cmp(opr1->as_register(), 0); | |
1671 } else { | |
1672 jobject2reg(con, O7); | |
1673 __ cmp(opr1->as_register(), O7); | |
1674 } | |
1675 } | |
1676 break; | |
1677 | |
1678 default: | |
1679 ShouldNotReachHere(); | |
1680 break; | |
1681 } | |
1682 } else { | |
1683 if (opr2->is_address()) { | |
1684 LIR_Address * addr = opr2->as_address_ptr(); | |
1685 BasicType type = addr->type(); | |
1686 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1687 else __ ld(as_Address(addr), O7); | |
1688 __ cmp(opr1->as_register(), O7); | |
1689 } else { | |
1690 __ cmp(opr1->as_register(), opr2->as_register()); | |
1691 } | |
1692 } | |
1693 } else if (opr1->is_double_cpu()) { | |
1694 Register xlo = opr1->as_register_lo(); | |
1695 Register xhi = opr1->as_register_hi(); | |
1696 if (opr2->is_constant() && opr2->as_jlong() == 0) { | |
1697 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); | |
1698 #ifdef _LP64 | |
1699 __ orcc(xhi, G0, G0); | |
1700 #else | |
1701 __ orcc(xhi, xlo, G0); | |
1702 #endif | |
1703 } else if (opr2->is_register()) { | |
1704 Register ylo = opr2->as_register_lo(); | |
1705 Register yhi = opr2->as_register_hi(); | |
1706 #ifdef _LP64 | |
1707 __ cmp(xlo, ylo); | |
1708 #else | |
1709 __ subcc(xlo, ylo, xlo); | |
1710 __ subccc(xhi, yhi, xhi); | |
1711 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
1712 __ orcc(xhi, xlo, G0); | |
1713 } | |
1714 #endif | |
1715 } else { | |
1716 ShouldNotReachHere(); | |
1717 } | |
1718 } else if (opr1->is_address()) { | |
1719 LIR_Address * addr = opr1->as_address_ptr(); | |
1720 BasicType type = addr->type(); | |
1721 assert (opr2->is_constant(), "Checking"); | |
1722 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1723 else __ ld(as_Address(addr), O7); | |
1724 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); | |
1725 } else { | |
1726 ShouldNotReachHere(); | |
1727 } | |
1728 } | |
1729 | |
1730 | |
1731 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ | |
1732 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
1733 bool is_unordered_less = (code == lir_ucmp_fd2i); | |
1734 if (left->is_single_fpu()) { | |
1735 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); | |
1736 } else if (left->is_double_fpu()) { | |
1737 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); | |
1738 } else { | |
1739 ShouldNotReachHere(); | |
1740 } | |
1741 } else if (code == lir_cmp_l2i) { | |
1369 | 1742 #ifdef _LP64 |
1743 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); | |
1744 #else | |
0 | 1745 __ lcmp(left->as_register_hi(), left->as_register_lo(), |
1746 right->as_register_hi(), right->as_register_lo(), | |
1747 dst->as_register()); | |
1369 | 1748 #endif |
0 | 1749 } else { |
1750 ShouldNotReachHere(); | |
1751 } | |
1752 } | |
1753 | |
1754 | |
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1755 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
0 | 1756 Assembler::Condition acond; |
1757 switch (condition) { | |
1758 case lir_cond_equal: acond = Assembler::equal; break; | |
1759 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1760 case lir_cond_less: acond = Assembler::less; break; | |
1761 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1762 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
1763 case lir_cond_greater: acond = Assembler::greater; break; | |
1764 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
1765 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
1766 default: ShouldNotReachHere(); | |
1767 }; | |
1768 | |
1769 if (opr1->is_constant() && opr1->type() == T_INT) { | |
1770 Register dest = result->as_register(); | |
1771 // load up first part of constant before branch | |
1772 // and do the rest in the delay slot. | |
1773 if (!Assembler::is_simm13(opr1->as_jint())) { | |
1774 __ sethi(opr1->as_jint(), dest); | |
1775 } | |
1776 } else if (opr1->is_constant()) { | |
1777 const2reg(opr1, result, lir_patch_none, NULL); | |
1778 } else if (opr1->is_register()) { | |
1779 reg2reg(opr1, result); | |
1780 } else if (opr1->is_stack()) { | |
1781 stack2reg(opr1, result, result->type()); | |
1782 } else { | |
1783 ShouldNotReachHere(); | |
1784 } | |
1785 Label skip; | |
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1786 #ifdef _LP64 |
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1787 if (type == T_INT) { |
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1788 __ br(acond, false, Assembler::pt, skip); |
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1789 } else |
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1790 #endif |
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1791 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit |
0 | 1792 if (opr1->is_constant() && opr1->type() == T_INT) { |
1793 Register dest = result->as_register(); | |
1794 if (Assembler::is_simm13(opr1->as_jint())) { | |
1795 __ delayed()->or3(G0, opr1->as_jint(), dest); | |
1796 } else { | |
1797 // the sethi has been done above, so just put in the low 10 bits | |
1798 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); | |
1799 } | |
1800 } else { | |
1801 // can't do anything useful in the delay slot | |
1802 __ delayed()->nop(); | |
1803 } | |
1804 if (opr2->is_constant()) { | |
1805 const2reg(opr2, result, lir_patch_none, NULL); | |
1806 } else if (opr2->is_register()) { | |
1807 reg2reg(opr2, result); | |
1808 } else if (opr2->is_stack()) { | |
1809 stack2reg(opr2, result, result->type()); | |
1810 } else { | |
1811 ShouldNotReachHere(); | |
1812 } | |
1813 __ bind(skip); | |
1814 } | |
1815 | |
1816 | |
1817 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
1818 assert(info == NULL, "unused on this code path"); | |
1819 assert(left->is_register(), "wrong items state"); | |
1820 assert(dest->is_register(), "wrong items state"); | |
1821 | |
1822 if (right->is_register()) { | |
1823 if (dest->is_float_kind()) { | |
1824 | |
1825 FloatRegister lreg, rreg, res; | |
1826 FloatRegisterImpl::Width w; | |
1827 if (right->is_single_fpu()) { | |
1828 w = FloatRegisterImpl::S; | |
1829 lreg = left->as_float_reg(); | |
1830 rreg = right->as_float_reg(); | |
1831 res = dest->as_float_reg(); | |
1832 } else { | |
1833 w = FloatRegisterImpl::D; | |
1834 lreg = left->as_double_reg(); | |
1835 rreg = right->as_double_reg(); | |
1836 res = dest->as_double_reg(); | |
1837 } | |
1838 | |
1839 switch (code) { | |
1840 case lir_add: __ fadd(w, lreg, rreg, res); break; | |
1841 case lir_sub: __ fsub(w, lreg, rreg, res); break; | |
1842 case lir_mul: // fall through | |
1843 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; | |
1844 case lir_div: // fall through | |
1845 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; | |
1846 default: ShouldNotReachHere(); | |
1847 } | |
1848 | |
1849 } else if (dest->is_double_cpu()) { | |
1850 #ifdef _LP64 | |
1851 Register dst_lo = dest->as_register_lo(); | |
1852 Register op1_lo = left->as_pointer_register(); | |
1853 Register op2_lo = right->as_pointer_register(); | |
1854 | |
1855 switch (code) { | |
1856 case lir_add: | |
1857 __ add(op1_lo, op2_lo, dst_lo); | |
1858 break; | |
1859 | |
1860 case lir_sub: | |
1861 __ sub(op1_lo, op2_lo, dst_lo); | |
1862 break; | |
1863 | |
1864 default: ShouldNotReachHere(); | |
1865 } | |
1866 #else | |
1867 Register op1_lo = left->as_register_lo(); | |
1868 Register op1_hi = left->as_register_hi(); | |
1869 Register op2_lo = right->as_register_lo(); | |
1870 Register op2_hi = right->as_register_hi(); | |
1871 Register dst_lo = dest->as_register_lo(); | |
1872 Register dst_hi = dest->as_register_hi(); | |
1873 | |
1874 switch (code) { | |
1875 case lir_add: | |
1876 __ addcc(op1_lo, op2_lo, dst_lo); | |
1877 __ addc (op1_hi, op2_hi, dst_hi); | |
1878 break; | |
1879 | |
1880 case lir_sub: | |
1881 __ subcc(op1_lo, op2_lo, dst_lo); | |
1882 __ subc (op1_hi, op2_hi, dst_hi); | |
1883 break; | |
1884 | |
1885 default: ShouldNotReachHere(); | |
1886 } | |
1887 #endif | |
1888 } else { | |
1889 assert (right->is_single_cpu(), "Just Checking"); | |
1890 | |
1891 Register lreg = left->as_register(); | |
1892 Register res = dest->as_register(); | |
1893 Register rreg = right->as_register(); | |
1894 switch (code) { | |
1895 case lir_add: __ add (lreg, rreg, res); break; | |
1896 case lir_sub: __ sub (lreg, rreg, res); break; | |
10997 | 1897 case lir_mul: __ mulx (lreg, rreg, res); break; |
0 | 1898 default: ShouldNotReachHere(); |
1899 } | |
1900 } | |
1901 } else { | |
1902 assert (right->is_constant(), "must be constant"); | |
1903 | |
1904 if (dest->is_single_cpu()) { | |
1905 Register lreg = left->as_register(); | |
1906 Register res = dest->as_register(); | |
1907 int simm13 = right->as_constant_ptr()->as_jint(); | |
1908 | |
1909 switch (code) { | |
1910 case lir_add: __ add (lreg, simm13, res); break; | |
1911 case lir_sub: __ sub (lreg, simm13, res); break; | |
10997 | 1912 case lir_mul: __ mulx (lreg, simm13, res); break; |
0 | 1913 default: ShouldNotReachHere(); |
1914 } | |
1915 } else { | |
1916 Register lreg = left->as_pointer_register(); | |
1917 Register res = dest->as_register_lo(); | |
1918 long con = right->as_constant_ptr()->as_jlong(); | |
1919 assert(Assembler::is_simm13(con), "must be simm13"); | |
1920 | |
1921 switch (code) { | |
1922 case lir_add: __ add (lreg, (int)con, res); break; | |
1923 case lir_sub: __ sub (lreg, (int)con, res); break; | |
10997 | 1924 case lir_mul: __ mulx (lreg, (int)con, res); break; |
0 | 1925 default: ShouldNotReachHere(); |
1926 } | |
1927 } | |
1928 } | |
1929 } | |
1930 | |
1931 | |
1932 void LIR_Assembler::fpop() { | |
1933 // do nothing | |
1934 } | |
1935 | |
1936 | |
1937 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { | |
1938 switch (code) { | |
1939 case lir_sin: | |
1940 case lir_tan: | |
1941 case lir_cos: { | |
1942 assert(thread->is_valid(), "preserve the thread object for performance reasons"); | |
1943 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); | |
1944 break; | |
1945 } | |
1946 case lir_sqrt: { | |
1947 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); | |
1948 FloatRegister src_reg = value->as_double_reg(); | |
1949 FloatRegister dst_reg = dest->as_double_reg(); | |
1950 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); | |
1951 break; | |
1952 } | |
1953 case lir_abs: { | |
1954 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); | |
1955 FloatRegister src_reg = value->as_double_reg(); | |
1956 FloatRegister dst_reg = dest->as_double_reg(); | |
1957 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); | |
1958 break; | |
1959 } | |
1960 default: { | |
1961 ShouldNotReachHere(); | |
1962 break; | |
1963 } | |
1964 } | |
1965 } | |
1966 | |
1967 | |
1968 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { | |
1969 if (right->is_constant()) { | |
1970 if (dest->is_single_cpu()) { | |
1971 int simm13 = right->as_constant_ptr()->as_jint(); | |
1972 switch (code) { | |
1973 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; | |
1974 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; | |
1975 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; | |
1976 default: ShouldNotReachHere(); | |
1977 } | |
1978 } else { | |
1979 long c = right->as_constant_ptr()->as_jlong(); | |
1980 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); | |
1981 int simm13 = (int)c; | |
1982 switch (code) { | |
1983 case lir_logic_and: | |
1984 #ifndef _LP64 | |
1985 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
1986 #endif | |
1987 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
1988 break; | |
1989 | |
1990 case lir_logic_or: | |
1991 #ifndef _LP64 | |
1992 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
1993 #endif | |
1994 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
1995 break; | |
1996 | |
1997 case lir_logic_xor: | |
1998 #ifndef _LP64 | |
1999 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
2000 #endif | |
2001 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
2002 break; | |
2003 | |
2004 default: ShouldNotReachHere(); | |
2005 } | |
2006 } | |
2007 } else { | |
2008 assert(right->is_register(), "right should be in register"); | |
2009 | |
2010 if (dest->is_single_cpu()) { | |
2011 switch (code) { | |
2012 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2013 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2014 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2015 default: ShouldNotReachHere(); | |
2016 } | |
2017 } else { | |
2018 #ifdef _LP64 | |
2019 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : | |
2020 left->as_register_lo(); | |
2021 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : | |
2022 right->as_register_lo(); | |
2023 | |
2024 switch (code) { | |
2025 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; | |
2026 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; | |
2027 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; | |
2028 default: ShouldNotReachHere(); | |
2029 } | |
2030 #else | |
2031 switch (code) { | |
2032 case lir_logic_and: | |
2033 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2034 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2035 break; | |
2036 | |
2037 case lir_logic_or: | |
2038 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2039 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2040 break; | |
2041 | |
2042 case lir_logic_xor: | |
2043 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2044 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2045 break; | |
2046 | |
2047 default: ShouldNotReachHere(); | |
2048 } | |
2049 #endif | |
2050 } | |
2051 } | |
2052 } | |
2053 | |
2054 | |
2055 int LIR_Assembler::shift_amount(BasicType t) { | |
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2056 int elem_size = type2aelembytes(t); |
0 | 2057 switch (elem_size) { |
2058 case 1 : return 0; | |
2059 case 2 : return 1; | |
2060 case 4 : return 2; | |
2061 case 8 : return 3; | |
2062 } | |
2063 ShouldNotReachHere(); | |
2064 return -1; | |
2065 } | |
2066 | |
2067 | |
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2068 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
0 | 2069 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2070 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); |
0 | 2071 |
2072 info->add_register_oop(exceptionOop); | |
2073 | |
1378
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2074 // reuse the debug info from the safepoint poll for the throw op itself |
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2075 address pc_for_athrow = __ pc(); |
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2076 int pc_for_athrow_offset = __ offset(); |
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2077 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); |
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2078 __ set(pc_for_athrow, Oissuing_pc, rspec); |
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2079 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2080 |
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2081 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
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2082 __ delayed()->nop(); |
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2083 } |
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2084 |
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2085 |
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2086 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2087 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2088 |
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2089 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); |
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2090 __ delayed()->nop(); |
0 | 2091 } |
2092 | |
2093 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
2094 Register src = op->src()->as_register(); | |
2095 Register dst = op->dst()->as_register(); | |
2096 Register src_pos = op->src_pos()->as_register(); | |
2097 Register dst_pos = op->dst_pos()->as_register(); | |
2098 Register length = op->length()->as_register(); | |
2099 Register tmp = op->tmp()->as_register(); | |
2100 Register tmp2 = O7; | |
2101 | |
2102 int flags = op->flags(); | |
2103 ciArrayKlass* default_type = op->expected_type(); | |
2104 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
2105 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
2106 | |
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2107 #ifdef _LP64 |
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2108 // higher 32bits must be null |
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2109 __ sra(dst_pos, 0, dst_pos); |
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2110 __ sra(src_pos, 0, src_pos); |
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2111 __ sra(length, 0, length); |
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2112 #endif |
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2113 |
0 | 2114 // set up the arraycopy stub information |
2115 ArrayCopyStub* stub = op->stub(); | |
2116 | |
2117 // always do stub if no type information is available. it's ok if | |
2118 // the known type isn't loaded since the code sanity checks | |
2119 // in debug mode and the type isn't required when we know the exact type | |
2120 // also check that the type is an array type. | |
2446 | 2121 if (op->expected_type() == NULL) { |
0 | 2122 __ mov(src, O0); |
2123 __ mov(src_pos, O1); | |
2124 __ mov(dst, O2); | |
2125 __ mov(dst_pos, O3); | |
2126 __ mov(length, O4); | |
2446 | 2127 address copyfunc_addr = StubRoutines::generic_arraycopy(); |
2128 | |
2129 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
2130 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); | |
2131 } else { | |
2132 #ifndef PRODUCT | |
2133 if (PrintC1Statistics) { | |
2134 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; | |
2135 __ inc_counter(counter, G1, G3); | |
2136 } | |
2137 #endif | |
2138 __ call_VM_leaf(tmp, copyfunc_addr); | |
2139 } | |
2140 | |
2141 if (copyfunc_addr != NULL) { | |
2142 __ xor3(O0, -1, tmp); | |
2143 __ sub(length, tmp, length); | |
2144 __ add(src_pos, tmp, src_pos); | |
3839 | 2145 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); |
2446 | 2146 __ delayed()->add(dst_pos, tmp, dst_pos); |
2147 } else { | |
3839 | 2148 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); |
2446 | 2149 __ delayed()->nop(); |
2150 } | |
0 | 2151 __ bind(*stub->continuation()); |
2152 return; | |
2153 } | |
2154 | |
2155 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); | |
2156 | |
2157 // make sure src and dst are non-null and load array length | |
2158 if (flags & LIR_OpArrayCopy::src_null_check) { | |
2159 __ tst(src); | |
2002 | 2160 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2161 __ delayed()->nop(); |
2162 } | |
2163 | |
2164 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
2165 __ tst(dst); | |
2002 | 2166 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2167 __ delayed()->nop(); |
2168 } | |
2169 | |
2170 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
2171 // test src_pos register | |
3839 | 2172 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry()); |
0 | 2173 __ delayed()->nop(); |
2174 } | |
2175 | |
2176 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
2177 // test dst_pos register | |
3839 | 2178 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry()); |
0 | 2179 __ delayed()->nop(); |
2180 } | |
2181 | |
2182 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
2183 // make sure length isn't negative | |
3839 | 2184 __ cmp_zero_and_br(Assembler::less, length, *stub->entry()); |
0 | 2185 __ delayed()->nop(); |
2186 } | |
2187 | |
2188 if (flags & LIR_OpArrayCopy::src_range_check) { | |
2189 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2190 __ add(length, src_pos, tmp); | |
2191 __ cmp(tmp2, tmp); | |
2192 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2193 __ delayed()->nop(); | |
2194 } | |
2195 | |
2196 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
2197 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2198 __ add(length, dst_pos, tmp); | |
2199 __ cmp(tmp2, tmp); | |
2200 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2201 __ delayed()->nop(); | |
2202 } | |
2203 | |
2446 | 2204 int shift = shift_amount(basic_type); |
2205 | |
0 | 2206 if (flags & LIR_OpArrayCopy::type_check) { |
2446 | 2207 // We don't know the array types are compatible |
2208 if (basic_type != T_OBJECT) { | |
2209 // Simple test for basic type arrays | |
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2210 if (UseCompressedClassPointers) { |
2446 | 2211 // We don't need decode because we just need to compare |
2212 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2213 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2214 __ cmp(tmp, tmp2); | |
2215 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2216 } else { | |
2217 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2218 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2219 __ cmp(tmp, tmp2); | |
2220 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2221 } | |
2222 __ delayed()->nop(); | |
2002 | 2223 } else { |
2446 | 2224 // For object arrays, if src is a sub class of dst then we can |
2225 // safely do the copy. | |
2226 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
2227 | |
2228 Label cont, slow; | |
2229 assert_different_registers(tmp, tmp2, G3, G1); | |
2230 | |
2231 __ load_klass(src, G3); | |
2232 __ load_klass(dst, G1); | |
2233 | |
2234 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); | |
2235 | |
2236 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2237 __ delayed()->nop(); | |
2238 | |
2239 __ cmp(G3, 0); | |
2240 if (copyfunc_addr != NULL) { // use stub if available | |
2241 // src is not a sub class of dst so we have to do a | |
2242 // per-element check. | |
2243 __ br(Assembler::notEqual, false, Assembler::pt, cont); | |
2244 __ delayed()->nop(); | |
2245 | |
2246 __ bind(slow); | |
2247 | |
2248 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
2249 if ((flags & mask) != mask) { | |
2250 // Check that at least both of them object arrays. | |
2251 assert(flags & mask, "one of the two should be known to be an object array"); | |
2252 | |
2253 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
2254 __ load_klass(src, tmp); | |
2255 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
2256 __ load_klass(dst, tmp); | |
2257 } | |
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2258 int lh_offset = in_bytes(Klass::layout_helper_offset()); |
2446 | 2259 |
2260 __ lduw(tmp, lh_offset, tmp2); | |
2261 | |
2262 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
2263 __ set(objArray_lh, tmp); | |
2264 __ cmp(tmp, tmp2); | |
2265 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2266 __ delayed()->nop(); | |
2267 } | |
2268 | |
2269 Register src_ptr = O0; | |
2270 Register dst_ptr = O1; | |
2271 Register len = O2; | |
2272 Register chk_off = O3; | |
2273 Register super_k = O4; | |
2274 | |
2275 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2276 if (shift == 0) { | |
2277 __ add(src_ptr, src_pos, src_ptr); | |
2278 } else { | |
2279 __ sll(src_pos, shift, tmp); | |
2280 __ add(src_ptr, tmp, src_ptr); | |
2281 } | |
2282 | |
2283 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2284 if (shift == 0) { | |
2285 __ add(dst_ptr, dst_pos, dst_ptr); | |
2286 } else { | |
2287 __ sll(dst_pos, shift, tmp); | |
2288 __ add(dst_ptr, tmp, dst_ptr); | |
2289 } | |
2290 __ mov(length, len); | |
2291 __ load_klass(dst, tmp); | |
2292 | |
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2293 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); |
2446 | 2294 __ ld_ptr(tmp, ek_offset, super_k); |
2295 | |
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2296 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
2446 | 2297 __ lduw(super_k, sco_offset, chk_off); |
2298 | |
2299 __ call_VM_leaf(tmp, copyfunc_addr); | |
2300 | |
2301 #ifndef PRODUCT | |
2302 if (PrintC1Statistics) { | |
2303 Label failed; | |
3839 | 2304 __ br_notnull_short(O0, Assembler::pn, failed); |
2446 | 2305 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); |
2306 __ bind(failed); | |
2307 } | |
2308 #endif | |
2309 | |
2310 __ br_null(O0, false, Assembler::pt, *stub->continuation()); | |
2311 __ delayed()->xor3(O0, -1, tmp); | |
2312 | |
2313 #ifndef PRODUCT | |
2314 if (PrintC1Statistics) { | |
2315 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); | |
2316 } | |
2317 #endif | |
2318 | |
2319 __ sub(length, tmp, length); | |
2320 __ add(src_pos, tmp, src_pos); | |
2321 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); | |
2322 __ delayed()->add(dst_pos, tmp, dst_pos); | |
2323 | |
2324 __ bind(cont); | |
2325 } else { | |
2326 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
2327 __ delayed()->nop(); | |
2328 __ bind(cont); | |
2329 } | |
2002 | 2330 } |
0 | 2331 } |
2332 | |
2333 #ifdef ASSERT | |
2334 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
2335 // Sanity check the known type with the incoming class. For the | |
2336 // primitive case the types must match exactly with src.klass and | |
2337 // dst.klass each exactly matching the default type. For the | |
2338 // object array case, if no type check is needed then either the | |
2339 // dst type is exactly the expected type and the src type is a | |
2340 // subtype which we can't check or src is the same array as dst | |
2341 // but not necessarily exactly of type default_type. | |
2342 Label known_ok, halt; | |
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2343 metadata2reg(op->expected_type()->constant_encoding(), tmp); |
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2344 if (UseCompressedClassPointers) { |
2002 | 2345 // tmp holds the default type. It currently comes uncompressed after the |
2346 // load of a constant, so encode it. | |
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2347 __ encode_klass_not_null(tmp); |
2002 | 2348 // load the raw value of the dst klass, since we will be comparing |
2349 // uncompressed values directly. | |
2350 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2351 if (basic_type != T_OBJECT) { | |
2352 __ cmp(tmp, tmp2); | |
2353 __ br(Assembler::notEqual, false, Assembler::pn, halt); | |
2354 // load the raw value of the src klass. | |
2355 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
3839 | 2356 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); |
2002 | 2357 } else { |
2358 __ cmp(tmp, tmp2); | |
2359 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
2360 __ delayed()->cmp(src, dst); | |
2361 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2362 __ delayed()->nop(); | |
2363 } | |
0 | 2364 } else { |
2002 | 2365 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
2366 if (basic_type != T_OBJECT) { | |
2367 __ cmp(tmp, tmp2); | |
2368 __ brx(Assembler::notEqual, false, Assembler::pn, halt); | |
2369 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
3839 | 2370 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); |
2002 | 2371 } else { |
2372 __ cmp(tmp, tmp2); | |
2373 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2374 __ delayed()->cmp(src, dst); | |
2375 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2376 __ delayed()->nop(); | |
2377 } | |
0 | 2378 } |
2379 __ bind(halt); | |
2380 __ stop("incorrect type information in arraycopy"); | |
2381 __ bind(known_ok); | |
2382 } | |
2383 #endif | |
2384 | |
2446 | 2385 #ifndef PRODUCT |
2386 if (PrintC1Statistics) { | |
2387 address counter = Runtime1::arraycopy_count_address(basic_type); | |
2388 __ inc_counter(counter, G1, G3); | |
2389 } | |
2390 #endif | |
0 | 2391 |
2392 Register src_ptr = O0; | |
2393 Register dst_ptr = O1; | |
2394 Register len = O2; | |
2395 | |
2396 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2397 if (shift == 0) { | |
2398 __ add(src_ptr, src_pos, src_ptr); | |
2399 } else { | |
2400 __ sll(src_pos, shift, tmp); | |
2401 __ add(src_ptr, tmp, src_ptr); | |
2402 } | |
2403 | |
2404 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2405 if (shift == 0) { | |
2406 __ add(dst_ptr, dst_pos, dst_ptr); | |
2407 } else { | |
2408 __ sll(dst_pos, shift, tmp); | |
2409 __ add(dst_ptr, tmp, dst_ptr); | |
2410 } | |
2411 | |
2446 | 2412 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; |
2413 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
2414 const char *name; | |
2415 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
2416 | |
2417 // arraycopy stubs takes a length in number of elements, so don't scale it. | |
2418 __ mov(length, len); | |
2419 __ call_VM_leaf(tmp, entry); | |
0 | 2420 |
2421 __ bind(*stub->continuation()); | |
2422 } | |
2423 | |
2424 | |
2425 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
2426 if (dest->is_single_cpu()) { | |
2427 #ifdef _LP64 | |
2428 if (left->type() == T_OBJECT) { | |
2429 switch (code) { | |
2430 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; | |
2431 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; | |
2432 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2433 default: ShouldNotReachHere(); | |
2434 } | |
2435 } else | |
2436 #endif | |
2437 switch (code) { | |
2438 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; | |
2439 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; | |
2440 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2441 default: ShouldNotReachHere(); | |
2442 } | |
2443 } else { | |
2444 #ifdef _LP64 | |
2445 switch (code) { | |
2446 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2447 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2448 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2449 default: ShouldNotReachHere(); | |
2450 } | |
2451 #else | |
2452 switch (code) { | |
2453 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2454 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2455 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2456 default: ShouldNotReachHere(); | |
2457 } | |
2458 #endif | |
2459 } | |
2460 } | |
2461 | |
2462 | |
2463 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
2464 #ifdef _LP64 | |
2465 if (left->type() == T_OBJECT) { | |
2466 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) | |
2467 Register l = left->as_register(); | |
2468 Register d = dest->as_register_lo(); | |
2469 switch (code) { | |
2470 case lir_shl: __ sllx (l, count, d); break; | |
2471 case lir_shr: __ srax (l, count, d); break; | |
2472 case lir_ushr: __ srlx (l, count, d); break; | |
2473 default: ShouldNotReachHere(); | |
2474 } | |
2475 return; | |
2476 } | |
2477 #endif | |
2478 | |
2479 if (dest->is_single_cpu()) { | |
2480 count = count & 0x1F; // Java spec | |
2481 switch (code) { | |
2482 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; | |
2483 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; | |
2484 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; | |
2485 default: ShouldNotReachHere(); | |
2486 } | |
2487 } else if (dest->is_double_cpu()) { | |
2488 count = count & 63; // Java spec | |
2489 switch (code) { | |
2490 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2491 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2492 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2493 default: ShouldNotReachHere(); | |
2494 } | |
2495 } else { | |
2496 ShouldNotReachHere(); | |
2497 } | |
2498 } | |
2499 | |
2500 | |
2501 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
2502 assert(op->tmp1()->as_register() == G1 && | |
2503 op->tmp2()->as_register() == G3 && | |
2504 op->tmp3()->as_register() == G4 && | |
2505 op->obj()->as_register() == O0 && | |
2506 op->klass()->as_register() == G5, "must be"); | |
2507 if (op->init_check()) { | |
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2508 __ ldub(op->klass()->as_register(), |
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2509 in_bytes(InstanceKlass::init_state_offset()), |
0 | 2510 op->tmp1()->as_register()); |
2511 add_debug_info_for_null_check_here(op->stub()->info()); | |
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2512 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized); |
0 | 2513 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); |
2514 __ delayed()->nop(); | |
2515 } | |
2516 __ allocate_object(op->obj()->as_register(), | |
2517 op->tmp1()->as_register(), | |
2518 op->tmp2()->as_register(), | |
2519 op->tmp3()->as_register(), | |
2520 op->header_size(), | |
2521 op->object_size(), | |
2522 op->klass()->as_register(), | |
2523 *op->stub()->entry()); | |
2524 __ bind(*op->stub()->continuation()); | |
2525 __ verify_oop(op->obj()->as_register()); | |
2526 } | |
2527 | |
2528 | |
2529 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
2530 assert(op->tmp1()->as_register() == G1 && | |
2531 op->tmp2()->as_register() == G3 && | |
2532 op->tmp3()->as_register() == G4 && | |
2533 op->tmp4()->as_register() == O1 && | |
2534 op->klass()->as_register() == G5, "must be"); | |
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2535 |
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2536 LP64_ONLY( __ signx(op->len()->as_register()); ) |
0 | 2537 if (UseSlowPath || |
2538 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
2539 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
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2540 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
0 | 2541 __ delayed()->nop(); |
2542 } else { | |
2543 __ allocate_array(op->obj()->as_register(), | |
2544 op->len()->as_register(), | |
2545 op->tmp1()->as_register(), | |
2546 op->tmp2()->as_register(), | |
2547 op->tmp3()->as_register(), | |
2548 arrayOopDesc::header_size(op->type()), | |
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2549 type2aelembytes(op->type()), |
0 | 2550 op->klass()->as_register(), |
2551 *op->stub()->entry()); | |
2552 } | |
2553 __ bind(*op->stub()->continuation()); | |
2554 } | |
2555 | |
2556 | |
1783 | 2557 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, |
2558 ciMethodData *md, ciProfileData *data, | |
2559 Register recv, Register tmp1, Label* update_done) { | |
2560 uint i; | |
2561 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2562 Label next_test; | |
2563 // See if the receiver is receiver[n]. | |
2564 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2565 mdo_offset_bias); | |
2566 __ ld_ptr(receiver_addr, tmp1); | |
12955 | 2567 __ verify_klass_ptr(tmp1); |
3839 | 2568 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test); |
1783 | 2569 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - |
2570 mdo_offset_bias); | |
2571 __ ld_ptr(data_addr, tmp1); | |
2572 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
2573 __ st_ptr(tmp1, data_addr); | |
3839 | 2574 __ ba(*update_done); |
1783 | 2575 __ delayed()->nop(); |
2576 __ bind(next_test); | |
2577 } | |
2578 | |
2579 // Didn't find receiver; find next empty slot and fill it in | |
2580 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2581 Label next_test; | |
2582 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2583 mdo_offset_bias); | |
2002 | 2584 __ ld_ptr(recv_addr, tmp1); |
3839 | 2585 __ br_notnull_short(tmp1, Assembler::pt, next_test); |
1783 | 2586 __ st_ptr(recv, recv_addr); |
2587 __ set(DataLayout::counter_increment, tmp1); | |
2588 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
2589 mdo_offset_bias); | |
3839 | 2590 __ ba(*update_done); |
1783 | 2591 __ delayed()->nop(); |
2592 __ bind(next_test); | |
2593 } | |
2594 } | |
2595 | |
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2596 |
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2597 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, |
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2598 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { |
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2599 md = method->method_data_or_null(); |
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2600 assert(md != NULL, "Sanity"); |
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2601 data = md->bci_to_data(bci); |
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2602 assert(data != NULL, "need data for checkcast"); |
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2603 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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2604 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { |
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2605 // The offset is large so bias the mdo by the base of the slot so |
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2606 // that the ld can use simm13s to reference the slots of the data |
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2607 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); |
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2608 } |
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2609 } |
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2610 |
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2611 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
1783 | 2612 // we always need a stub for the failure case. |
2613 CodeStub* stub = op->stub(); | |
2614 Register obj = op->object()->as_register(); | |
2615 Register k_RInfo = op->tmp1()->as_register(); | |
2616 Register klass_RInfo = op->tmp2()->as_register(); | |
2617 Register dst = op->result_opr()->as_register(); | |
2618 Register Rtmp1 = op->tmp3()->as_register(); | |
2619 ciKlass* k = op->klass(); | |
2620 | |
2621 | |
2622 if (obj == k_RInfo) { | |
2623 k_RInfo = klass_RInfo; | |
2624 klass_RInfo = obj; | |
2625 } | |
2626 | |
2627 ciMethodData* md; | |
2628 ciProfileData* data; | |
2629 int mdo_offset_bias = 0; | |
2630 if (op->should_profile()) { | |
2631 ciMethod* method = op->profiled_method(); | |
2632 assert(method != NULL, "Should have method"); | |
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2633 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2634 |
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2635 Label not_null; |
3839 | 2636 __ br_notnull_short(obj, Assembler::pn, not_null); |
1783 | 2637 Register mdo = k_RInfo; |
2638 Register data_val = Rtmp1; | |
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2639 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2640 if (mdo_offset_bias > 0) { |
2641 __ set(mdo_offset_bias, data_val); | |
2642 __ add(mdo, data_val, mdo); | |
2643 } | |
2644 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); | |
2645 __ ldub(flags_addr, data_val); | |
2646 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); | |
2647 __ stb(data_val, flags_addr); | |
3839 | 2648 __ ba(*obj_is_null); |
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2649 __ delayed()->nop(); |
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2650 __ bind(not_null); |
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2651 } else { |
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2652 __ br_null(obj, false, Assembler::pn, *obj_is_null); |
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2653 __ delayed()->nop(); |
1783 | 2654 } |
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2655 |
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2656 Label profile_cast_failure, profile_cast_success; |
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2657 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
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2658 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
1783 | 2659 |
2660 // patching may screw with our temporaries on sparc, | |
2661 // so let's do it before loading the class | |
2662 if (k->is_loaded()) { | |
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2663 metadata2reg(k->constant_encoding(), k_RInfo); |
1783 | 2664 } else { |
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2665 klass2reg_with_patching(k_RInfo, op->info_for_patch()); |
1783 | 2666 } |
2667 assert(obj != k_RInfo, "must be different"); | |
2668 | |
2669 // get object class | |
2670 // not a safepoint as obj null check happens earlier | |
2002 | 2671 __ load_klass(obj, klass_RInfo); |
1783 | 2672 if (op->fast_check()) { |
2673 assert_different_registers(klass_RInfo, k_RInfo); | |
2674 __ cmp(k_RInfo, klass_RInfo); | |
2675 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); | |
2676 __ delayed()->nop(); | |
2677 } else { | |
2678 bool need_slow_path = true; | |
2679 if (k->is_loaded()) { | |
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2680 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) |
1783 | 2681 need_slow_path = false; |
2682 // perform the fast part of the checking logic | |
2683 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, | |
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2684 (need_slow_path ? success_target : NULL), |
1783 | 2685 failure_target, NULL, |
2686 RegisterOrConstant(k->super_check_offset())); | |
2687 } else { | |
2688 // perform the fast part of the checking logic | |
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2689 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, |
1783 | 2690 failure_target, NULL); |
2691 } | |
2692 if (need_slow_path) { | |
2693 // call out-of-line instance of __ check_klass_subtype_slow_path(...): | |
2694 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); | |
2695 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2696 __ delayed()->nop(); | |
2697 __ cmp(G3, 0); | |
2698 __ br(Assembler::equal, false, Assembler::pn, *failure_target); | |
2699 __ delayed()->nop(); | |
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2700 // Fall through to success case |
1783 | 2701 } |
2702 } | |
2703 | |
2704 if (op->should_profile()) { | |
2705 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; | |
2706 assert_different_registers(obj, mdo, recv, tmp1); | |
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2707 __ bind(profile_cast_success); |
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2708 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2709 if (mdo_offset_bias > 0) { |
2710 __ set(mdo_offset_bias, tmp1); | |
2711 __ add(mdo, tmp1, mdo); | |
2712 } | |
2002 | 2713 __ load_klass(obj, recv); |
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2714 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); |
1783 | 2715 // Jump over the failure case |
3839 | 2716 __ ba(*success); |
1783 | 2717 __ delayed()->nop(); |
2718 // Cast failure case | |
2719 __ bind(profile_cast_failure); | |
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2720 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2721 if (mdo_offset_bias > 0) { |
2722 __ set(mdo_offset_bias, tmp1); | |
2723 __ add(mdo, tmp1, mdo); | |
2724 } | |
2725 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); | |
2726 __ ld_ptr(data_addr, tmp1); | |
2727 __ sub(tmp1, DataLayout::counter_increment, tmp1); | |
2728 __ st_ptr(tmp1, data_addr); | |
3839 | 2729 __ ba(*failure); |
1783 | 2730 __ delayed()->nop(); |
2731 } | |
3839 | 2732 __ ba(*success); |
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2733 __ delayed()->nop(); |
1783 | 2734 } |
2735 | |
0 | 2736 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
2737 LIR_Code code = op->code(); | |
2738 if (code == lir_store_check) { | |
2739 Register value = op->object()->as_register(); | |
2740 Register array = op->array()->as_register(); | |
2741 Register k_RInfo = op->tmp1()->as_register(); | |
2742 Register klass_RInfo = op->tmp2()->as_register(); | |
2743 Register Rtmp1 = op->tmp3()->as_register(); | |
2744 | |
2745 __ verify_oop(value); | |
2746 CodeStub* stub = op->stub(); | |
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2747 // check if it needs to be profiled |
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2748 ciMethodData* md; |
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2749 ciProfileData* data; |
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2750 int mdo_offset_bias = 0; |
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2751 if (op->should_profile()) { |
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2752 ciMethod* method = op->profiled_method(); |
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2753 assert(method != NULL, "Should have method"); |
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2754 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2755 } |
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2756 Label profile_cast_success, profile_cast_failure, done; |
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2757 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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2758 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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2759 |
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2760 if (op->should_profile()) { |
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2761 Label not_null; |
3839 | 2762 __ br_notnull_short(value, Assembler::pn, not_null); |
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2763 Register mdo = k_RInfo; |
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2764 Register data_val = Rtmp1; |
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2765 metadata2reg(md->constant_encoding(), mdo); |
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2766 if (mdo_offset_bias > 0) { |
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2767 __ set(mdo_offset_bias, data_val); |
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2768 __ add(mdo, data_val, mdo); |
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2769 } |
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2770 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); |
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2771 __ ldub(flags_addr, data_val); |
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2772 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); |
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2773 __ stb(data_val, flags_addr); |
3839 | 2774 __ ba_short(done); |
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2775 __ bind(not_null); |
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2776 } else { |
3839 | 2777 __ br_null_short(value, Assembler::pn, done); |
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2778 } |
2002 | 2779 add_debug_info_for_null_check_here(op->info_for_exception()); |
2780 __ load_klass(array, k_RInfo); | |
2781 __ load_klass(value, klass_RInfo); | |
0 | 2782 |
2783 // get instance klass | |
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2784 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo); |
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2785 // perform the fast part of the checking logic |
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2786 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); |
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2787 |
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2788 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2789 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
0 | 2790 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
2791 __ delayed()->nop(); | |
2792 __ cmp(G3, 0); | |
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2793 __ br(Assembler::equal, false, Assembler::pn, *failure_target); |
0 | 2794 __ delayed()->nop(); |
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2795 // fall through to the success case |
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2796 |
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2797 if (op->should_profile()) { |
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2798 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; |
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2799 assert_different_registers(value, mdo, recv, tmp1); |
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2800 __ bind(profile_cast_success); |
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2801 metadata2reg(md->constant_encoding(), mdo); |
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2802 if (mdo_offset_bias > 0) { |
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2803 __ set(mdo_offset_bias, tmp1); |
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2804 __ add(mdo, tmp1, mdo); |
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2805 } |
2002 | 2806 __ load_klass(value, recv); |
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2807 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); |
3839 | 2808 __ ba_short(done); |
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2809 // Cast failure case |
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2810 __ bind(profile_cast_failure); |
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2811 metadata2reg(md->constant_encoding(), mdo); |
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2812 if (mdo_offset_bias > 0) { |
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2813 __ set(mdo_offset_bias, tmp1); |
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2814 __ add(mdo, tmp1, mdo); |
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2815 } |
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2816 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
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2817 __ ld_ptr(data_addr, tmp1); |
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2818 __ sub(tmp1, DataLayout::counter_increment, tmp1); |
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2819 __ st_ptr(tmp1, data_addr); |
3839 | 2820 __ ba(*stub->entry()); |
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2821 __ delayed()->nop(); |
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2822 } |
0 | 2823 __ bind(done); |
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2824 } else if (code == lir_checkcast) { |
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2825 Register obj = op->object()->as_register(); |
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2826 Register dst = op->result_opr()->as_register(); |
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2827 Label success; |
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2828 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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2829 __ bind(success); |
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2830 __ mov(obj, dst); |
0 | 2831 } else if (code == lir_instanceof) { |
2832 Register obj = op->object()->as_register(); | |
2833 Register dst = op->result_opr()->as_register(); | |
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2834 Label success, failure, done; |
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2835 emit_typecheck_helper(op, &success, &failure, &failure); |
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2836 __ bind(failure); |
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2837 __ set(0, dst); |
3839 | 2838 __ ba_short(done); |
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2839 __ bind(success); |
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2840 __ set(1, dst); |
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2841 __ bind(done); |
0 | 2842 } else { |
2843 ShouldNotReachHere(); | |
2844 } | |
2845 | |
2846 } | |
2847 | |
2848 | |
2849 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
2850 if (op->code() == lir_cas_long) { | |
2851 assert(VM_Version::supports_cx8(), "wrong machine"); | |
2852 Register addr = op->addr()->as_pointer_register(); | |
2853 Register cmp_value_lo = op->cmp_value()->as_register_lo(); | |
2854 Register cmp_value_hi = op->cmp_value()->as_register_hi(); | |
2855 Register new_value_lo = op->new_value()->as_register_lo(); | |
2856 Register new_value_hi = op->new_value()->as_register_hi(); | |
2857 Register t1 = op->tmp1()->as_register(); | |
2858 Register t2 = op->tmp2()->as_register(); | |
2859 #ifdef _LP64 | |
2860 __ mov(cmp_value_lo, t1); | |
2861 __ mov(new_value_lo, t2); | |
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2862 // perform the compare and swap operation |
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|
2863 __ casx(addr, t1, t2); |
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2864 // generate condition code - if the swap succeeded, t2 ("new value" reg) was |
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2865 // overwritten with the original value in "addr" and will be equal to t1. |
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2866 __ cmp(t1, t2); |
0 | 2867 #else |
2868 // move high and low halves of long values into single registers | |
2869 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg | |
2870 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half | |
2871 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value | |
2872 __ sllx(new_value_hi, 32, t2); | |
2873 __ srl(new_value_lo, 0, new_value_lo); | |
2874 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap | |
2875 // perform the compare and swap operation | |
2876 __ casx(addr, t1, t2); | |
2877 // generate condition code - if the swap succeeded, t2 ("new value" reg) was | |
2878 // overwritten with the original value in "addr" and will be equal to t1. | |
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|
2879 // Produce icc flag for 32bit. |
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2880 __ sub(t1, t2, t2); |
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2881 __ srlx(t2, 32, t1); |
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2882 __ orcc(t2, t1, G0); |
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2883 #endif |
0 | 2884 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { |
2885 Register addr = op->addr()->as_pointer_register(); | |
2886 Register cmp_value = op->cmp_value()->as_register(); | |
2887 Register new_value = op->new_value()->as_register(); | |
2888 Register t1 = op->tmp1()->as_register(); | |
2889 Register t2 = op->tmp2()->as_register(); | |
2890 __ mov(cmp_value, t1); | |
2891 __ mov(new_value, t2); | |
2892 if (op->code() == lir_cas_obj) { | |
2002 | 2893 if (UseCompressedOops) { |
2894 __ encode_heap_oop(t1); | |
2895 __ encode_heap_oop(t2); | |
0 | 2896 __ cas(addr, t1, t2); |
2002 | 2897 } else { |
2010 | 2898 __ cas_ptr(addr, t1, t2); |
0 | 2899 } |
2002 | 2900 } else { |
2901 __ cas(addr, t1, t2); | |
2902 } | |
0 | 2903 __ cmp(t1, t2); |
2904 } else { | |
2905 Unimplemented(); | |
2906 } | |
2907 } | |
2908 | |
2909 void LIR_Assembler::set_24bit_FPU() { | |
2910 Unimplemented(); | |
2911 } | |
2912 | |
2913 | |
2914 void LIR_Assembler::reset_FPU() { | |
2915 Unimplemented(); | |
2916 } | |
2917 | |
2918 | |
2919 void LIR_Assembler::breakpoint() { | |
2920 __ breakpoint_trap(); | |
2921 } | |
2922 | |
2923 | |
2924 void LIR_Assembler::push(LIR_Opr opr) { | |
2925 Unimplemented(); | |
2926 } | |
2927 | |
2928 | |
2929 void LIR_Assembler::pop(LIR_Opr opr) { | |
2930 Unimplemented(); | |
2931 } | |
2932 | |
2933 | |
2934 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { | |
2935 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
2936 Register dst = dst_opr->as_register(); | |
2937 Register reg = mon_addr.base(); | |
2938 int offset = mon_addr.disp(); | |
2939 // compute pointer to BasicLock | |
2940 if (mon_addr.is_simm13()) { | |
2941 __ add(reg, offset, dst); | |
2942 } else { | |
2943 __ set(offset, dst); | |
2944 __ add(dst, reg, dst); | |
2945 } | |
2946 } | |
2947 | |
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2948 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { |
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2949 fatal("CRC32 intrinsic is not implemented on this platform"); |
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2950 } |
0 | 2951 |
2952 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
2953 Register obj = op->obj_opr()->as_register(); | |
2954 Register hdr = op->hdr_opr()->as_register(); | |
2955 Register lock = op->lock_opr()->as_register(); | |
2956 | |
2957 // obj may not be an oop | |
2958 if (op->code() == lir_lock) { | |
2959 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); | |
2960 if (UseFastLocking) { | |
2961 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2962 // add debug info for NullPointerException only if one is possible | |
2963 if (op->info() != NULL) { | |
2964 add_debug_info_for_null_check_here(op->info()); | |
2965 } | |
2966 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); | |
2967 } else { | |
2968 // always do slow locking | |
2969 // note: the slow locking code could be inlined here, however if we use | |
2970 // slow locking, speed doesn't matter anyway and this solution is | |
2971 // simpler and requires less duplicated code - additionally, the | |
2972 // slow locking code is the same in either case which simplifies | |
2973 // debugging | |
2974 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
2975 __ delayed()->nop(); | |
2976 } | |
2977 } else { | |
2978 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); | |
2979 if (UseFastLocking) { | |
2980 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2981 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
2982 } else { | |
2983 // always do slow unlocking | |
2984 // note: the slow unlocking code could be inlined here, however if we use | |
2985 // slow unlocking, speed doesn't matter anyway and this solution is | |
2986 // simpler and requires less duplicated code - additionally, the | |
2987 // slow unlocking code is the same in either case which simplifies | |
2988 // debugging | |
2989 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
2990 __ delayed()->nop(); | |
2991 } | |
2992 } | |
2993 __ bind(*op->stub()->continuation()); | |
2994 } | |
2995 | |
2996 | |
2997 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
2998 ciMethod* method = op->profiled_method(); | |
2999 int bci = op->profiled_bci(); | |
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3000 ciMethod* callee = op->profiled_callee(); |
0 | 3001 |
3002 // Update counter for all call types | |
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3003 ciMethodData* md = method->method_data_or_null(); |
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3004 assert(md != NULL, "Sanity"); |
0 | 3005 ciProfileData* data = md->bci_to_data(bci); |
3006 assert(data->is_CounterData(), "need CounterData for calls"); | |
3007 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
1783 | 3008 Register mdo = op->mdo()->as_register(); |
3009 #ifdef _LP64 | |
3010 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); | |
3011 Register tmp1 = op->tmp1()->as_register_lo(); | |
3012 #else | |
0 | 3013 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); |
3014 Register tmp1 = op->tmp1()->as_register(); | |
1783 | 3015 #endif |
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3016 metadata2reg(md->constant_encoding(), mdo); |
0 | 3017 int mdo_offset_bias = 0; |
3018 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + | |
3019 data->size_in_bytes())) { | |
3020 // The offset is large so bias the mdo by the base of the slot so | |
3021 // that the ld can use simm13s to reference the slots of the data | |
3022 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); | |
3023 __ set(mdo_offset_bias, O7); | |
3024 __ add(mdo, O7, mdo); | |
3025 } | |
3026 | |
727 | 3027 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
0 | 3028 Bytecodes::Code bc = method->java_code_at_bci(bci); |
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|
3029 const bool callee_is_static = callee->is_loaded() && callee->is_static(); |
0 | 3030 // Perform additional virtual call profiling for invokevirtual and |
3031 // invokeinterface bytecodes | |
3032 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
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|
3033 !callee_is_static && // required for optimized MH invokes |
1783 | 3034 C1ProfileVirtualCalls) { |
0 | 3035 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3036 Register recv = op->recv()->as_register(); | |
3037 assert_different_registers(mdo, tmp1, recv); | |
3038 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3039 ciKlass* known_klass = op->known_holder(); | |
1783 | 3040 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
0 | 3041 // We know the type that will be seen at this call site; we can |
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|
3042 // statically update the MethodData* rather than needing to do |
0 | 3043 // dynamic tests on the receiver type |
3044 | |
3045 // NOTE: we should probably put a lock around this search to | |
3046 // avoid collisions by concurrent compilations | |
3047 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3048 uint i; | |
3049 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3050 ciKlass* receiver = vc_data->receiver(i); | |
3051 if (known_klass->equals(receiver)) { | |
727 | 3052 Address data_addr(mdo, md->byte_offset_of_slot(data, |
3053 VirtualCallData::receiver_count_offset(i)) - | |
0 | 3054 mdo_offset_bias); |
1783 | 3055 __ ld_ptr(data_addr, tmp1); |
0 | 3056 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3057 __ st_ptr(tmp1, data_addr); |
0 | 3058 return; |
3059 } | |
3060 } | |
3061 | |
3062 // Receiver type not found in profile data; select an empty slot | |
3063 | |
3064 // Note that this is less efficient than it should be because it | |
3065 // always does a write to the receiver part of the | |
3066 // VirtualCallData rather than just the first time | |
3067 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3068 ciKlass* receiver = vc_data->receiver(i); | |
3069 if (receiver == NULL) { | |
727 | 3070 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
0 | 3071 mdo_offset_bias); |
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3072 metadata2reg(known_klass->constant_encoding(), tmp1); |
0 | 3073 __ st_ptr(tmp1, recv_addr); |
727 | 3074 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
0 | 3075 mdo_offset_bias); |
1783 | 3076 __ ld_ptr(data_addr, tmp1); |
0 | 3077 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3078 __ st_ptr(tmp1, data_addr); |
0 | 3079 return; |
3080 } | |
3081 } | |
3082 } else { | |
2002 | 3083 __ load_klass(recv, recv); |
0 | 3084 Label update_done; |
1783 | 3085 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); |
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3086 // Receiver did not match any saved receiver and there is no empty row for it. |
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3087 // Increment total counter to indicate polymorphic case. |
1783 | 3088 __ ld_ptr(counter_addr, tmp1); |
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3089 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3090 __ st_ptr(tmp1, counter_addr); |
0 | 3091 |
3092 __ bind(update_done); | |
3093 } | |
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3094 } else { |
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|
3095 // Static call |
1783 | 3096 __ ld_ptr(counter_addr, tmp1); |
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3097 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3098 __ st_ptr(tmp1, counter_addr); |
0 | 3099 } |
3100 } | |
3101 | |
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3102 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { |
14909 | 3103 fatal("Type profiling not implemented on this platform"); |
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3104 } |
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3105 |
0 | 3106 void LIR_Assembler::align_backward_branch_target() { |
1365 | 3107 __ align(OptoLoopAlignment); |
0 | 3108 } |
3109 | |
3110 | |
3111 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { | |
3112 // make sure we are expecting a delay | |
3113 // this has the side effect of clearing the delay state | |
3114 // so we can use _masm instead of _masm->delayed() to do the | |
3115 // code generation. | |
3116 __ delayed(); | |
3117 | |
3118 // make sure we only emit one instruction | |
3119 int offset = code_offset(); | |
3120 op->delay_op()->emit_code(this); | |
3121 #ifdef ASSERT | |
3122 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { | |
3123 op->delay_op()->print(); | |
3124 } | |
3125 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, | |
3126 "only one instruction can go in a delay slot"); | |
3127 #endif | |
3128 | |
3129 // we may also be emitting the call info for the instruction | |
3130 // which we are the delay slot of. | |
1564 | 3131 CodeEmitInfo* call_info = op->call_info(); |
0 | 3132 if (call_info) { |
3133 add_call_info(code_offset(), call_info); | |
3134 } | |
3135 | |
3136 if (VerifyStackAtCalls) { | |
3137 _masm->sub(FP, SP, O7); | |
3138 _masm->cmp(O7, initial_frame_size_in_bytes()); | |
3139 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); | |
3140 } | |
3141 } | |
3142 | |
3143 | |
3144 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3145 assert(left->is_register(), "can only handle registers"); | |
3146 | |
3147 if (left->is_single_cpu()) { | |
3148 __ neg(left->as_register(), dest->as_register()); | |
3149 } else if (left->is_single_fpu()) { | |
3150 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); | |
3151 } else if (left->is_double_fpu()) { | |
3152 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); | |
3153 } else { | |
3154 assert (left->is_double_cpu(), "Must be a long"); | |
3155 Register Rlow = left->as_register_lo(); | |
3156 Register Rhi = left->as_register_hi(); | |
3157 #ifdef _LP64 | |
3158 __ sub(G0, Rlow, dest->as_register_lo()); | |
3159 #else | |
3160 __ subcc(G0, Rlow, dest->as_register_lo()); | |
3161 __ subc (G0, Rhi, dest->as_register_hi()); | |
3162 #endif | |
3163 } | |
3164 } | |
3165 | |
3166 | |
3167 void LIR_Assembler::fxch(int i) { | |
3168 Unimplemented(); | |
3169 } | |
3170 | |
3171 void LIR_Assembler::fld(int i) { | |
3172 Unimplemented(); | |
3173 } | |
3174 | |
3175 void LIR_Assembler::ffree(int i) { | |
3176 Unimplemented(); | |
3177 } | |
3178 | |
3179 void LIR_Assembler::rt_call(LIR_Opr result, address dest, | |
3180 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3181 | |
3182 // if tmp is invalid, then the function being called doesn't destroy the thread | |
3183 if (tmp->is_valid()) { | |
3184 __ save_thread(tmp->as_register()); | |
3185 } | |
3186 __ call(dest, relocInfo::runtime_call_type); | |
3187 __ delayed()->nop(); | |
3188 if (info != NULL) { | |
3189 add_call_info_here(info); | |
3190 } | |
3191 if (tmp->is_valid()) { | |
3192 __ restore_thread(tmp->as_register()); | |
3193 } | |
3194 | |
3195 #ifdef ASSERT | |
3196 __ verify_thread(); | |
3197 #endif // ASSERT | |
3198 } | |
3199 | |
3200 | |
3201 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3202 #ifdef _LP64 | |
3203 ShouldNotReachHere(); | |
3204 #endif | |
3205 | |
3206 NEEDS_CLEANUP; | |
3207 if (type == T_LONG) { | |
3208 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); | |
3209 | |
3210 // (extended to allow indexed as well as constant displaced for JSR-166) | |
3211 Register idx = noreg; // contains either constant offset or index | |
3212 | |
3213 int disp = mem_addr->disp(); | |
3214 if (mem_addr->index() == LIR_OprFact::illegalOpr) { | |
3215 if (!Assembler::is_simm13(disp)) { | |
3216 idx = O7; | |
3217 __ set(disp, idx); | |
3218 } | |
3219 } else { | |
3220 assert(disp == 0, "not both indexed and disp"); | |
3221 idx = mem_addr->index()->as_register(); | |
3222 } | |
3223 | |
3224 int null_check_offset = -1; | |
3225 | |
3226 Register base = mem_addr->base()->as_register(); | |
3227 if (src->is_register() && dest->is_address()) { | |
3228 // G4 is high half, G5 is low half | |
10997 | 3229 // clear the top bits of G5, and scale up G4 |
3230 __ srl (src->as_register_lo(), 0, G5); | |
3231 __ sllx(src->as_register_hi(), 32, G4); | |
3232 // combine the two halves into the 64 bits of G4 | |
3233 __ or3(G4, G5, G4); | |
3234 null_check_offset = __ offset(); | |
3235 if (idx == noreg) { | |
3236 __ stx(G4, base, disp); | |
0 | 3237 } else { |
10997 | 3238 __ stx(G4, base, idx); |
0 | 3239 } |
3240 } else if (src->is_address() && dest->is_register()) { | |
3241 null_check_offset = __ offset(); | |
10997 | 3242 if (idx == noreg) { |
3243 __ ldx(base, disp, G5); | |
0 | 3244 } else { |
10997 | 3245 __ ldx(base, idx, G5); |
0 | 3246 } |
10997 | 3247 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi |
3248 __ mov (G5, dest->as_register_lo()); // copy low half into lo | |
0 | 3249 } else { |
3250 Unimplemented(); | |
3251 } | |
3252 if (info != NULL) { | |
3253 add_debug_info_for_null_check(null_check_offset, info); | |
3254 } | |
3255 | |
3256 } else { | |
3257 // use normal move for all other volatiles since they don't need | |
3258 // special handling to remain atomic. | |
2002 | 3259 move_op(src, dest, type, lir_patch_none, info, false, false, false); |
0 | 3260 } |
3261 } | |
3262 | |
3263 void LIR_Assembler::membar() { | |
3264 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode | |
3265 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3266 } | |
3267 | |
3268 void LIR_Assembler::membar_acquire() { | |
3269 // no-op on TSO | |
3270 } | |
3271 | |
3272 void LIR_Assembler::membar_release() { | |
3273 // no-op on TSO | |
3274 } | |
3275 | |
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7120481: storeStore barrier in constructor with final field
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3276 void LIR_Assembler::membar_loadload() { |
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7120481: storeStore barrier in constructor with final field
jiangli
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|
3277 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3278 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
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|
3279 } |
701a83c86f28
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|
3280 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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3281 void LIR_Assembler::membar_storestore() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3282 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3283 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3284 } |
701a83c86f28
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|
3285 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3286 void LIR_Assembler::membar_loadstore() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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changeset
|
3287 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3288 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
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|
3289 } |
701a83c86f28
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|
3290 |
701a83c86f28
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jiangli
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|
3291 void LIR_Assembler::membar_storeload() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3292 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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|
3293 } |
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|
3294 |
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|
3295 |
1783 | 3296 // Pack two sequential registers containing 32 bit values |
0 | 3297 // into a single 64 bit register. |
1783 | 3298 // src and src->successor() are packed into dst |
3299 // src and dst may be the same register. | |
3300 // Note: src is destroyed | |
3301 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { | |
3302 Register rs = src->as_register(); | |
3303 Register rd = dst->as_register_lo(); | |
0 | 3304 __ sllx(rs, 32, rs); |
3305 __ srl(rs->successor(), 0, rs->successor()); | |
3306 __ or3(rs, rs->successor(), rd); | |
3307 } | |
3308 | |
1783 | 3309 // Unpack a 64 bit value in a register into |
0 | 3310 // two sequential registers. |
1783 | 3311 // src is unpacked into dst and dst->successor() |
3312 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { | |
3313 Register rs = src->as_register_lo(); | |
3314 Register rd = dst->as_register_hi(); | |
3315 assert_different_registers(rs, rd, rd->successor()); | |
3316 __ srlx(rs, 32, rd); | |
3317 __ srl (rs, 0, rd->successor()); | |
0 | 3318 } |
3319 | |
3320 | |
3321 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { | |
3322 LIR_Address* addr = addr_opr->as_address_ptr(); | |
14909 | 3323 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); |
3324 | |
3325 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); | |
0 | 3326 } |
3327 | |
3328 | |
3329 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
3330 assert(result_reg->is_register(), "check"); | |
3331 __ mov(G2_thread, result_reg->as_register()); | |
3332 } | |
3333 | |
8860 | 3334 #ifdef ASSERT |
3335 // emit run-time assertion | |
3336 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { | |
3337 assert(op->code() == lir_assert, "must be"); | |
3338 | |
3339 if (op->in_opr1()->is_valid()) { | |
3340 assert(op->in_opr2()->is_valid(), "both operands must be valid"); | |
3341 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); | |
3342 } else { | |
3343 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); | |
3344 assert(op->condition() == lir_cond_always, "no other conditions allowed"); | |
3345 } | |
3346 | |
3347 Label ok; | |
3348 if (op->condition() != lir_cond_always) { | |
3349 Assembler::Condition acond; | |
3350 switch (op->condition()) { | |
3351 case lir_cond_equal: acond = Assembler::equal; break; | |
3352 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
3353 case lir_cond_less: acond = Assembler::less; break; | |
3354 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
3355 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
3356 case lir_cond_greater: acond = Assembler::greater; break; | |
3357 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
3358 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
3359 default: ShouldNotReachHere(); | |
3360 }; | |
3361 __ br(acond, false, Assembler::pt, ok); | |
3362 __ delayed()->nop(); | |
3363 } | |
3364 if (op->halt()) { | |
3365 const char* str = __ code_string(op->msg()); | |
3366 __ stop(str); | |
3367 } else { | |
3368 breakpoint(); | |
3369 } | |
3370 __ bind(ok); | |
3371 } | |
3372 #endif | |
0 | 3373 |
3374 void LIR_Assembler::peephole(LIR_List* lir) { | |
3375 LIR_OpList* inst = lir->instructions_list(); | |
3376 for (int i = 0; i < inst->length(); i++) { | |
3377 LIR_Op* op = inst->at(i); | |
3378 switch (op->code()) { | |
3379 case lir_cond_float_branch: | |
3380 case lir_branch: { | |
3381 LIR_OpBranch* branch = op->as_OpBranch(); | |
3382 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); | |
3383 LIR_Op* delay_op = NULL; | |
3384 // we'd like to be able to pull following instructions into | |
3385 // this slot but we don't know enough to do it safely yet so | |
3386 // only optimize block to block control flow. | |
3387 if (LIRFillDelaySlots && branch->block()) { | |
3388 LIR_Op* prev = inst->at(i - 1); | |
3389 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { | |
3390 // swap previous instruction into delay slot | |
3391 inst->at_put(i - 1, op); | |
3392 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3393 #ifndef PRODUCT | |
3394 if (LIRTracePeephole) { | |
3395 tty->print_cr("delayed"); | |
3396 inst->at(i - 1)->print(); | |
3397 inst->at(i)->print(); | |
1564 | 3398 tty->cr(); |
0 | 3399 } |
3400 #endif | |
3401 continue; | |
3402 } | |
3403 } | |
3404 | |
3405 if (!delay_op) { | |
3406 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); | |
3407 } | |
3408 inst->insert_before(i + 1, delay_op); | |
3409 break; | |
3410 } | |
3411 case lir_static_call: | |
3412 case lir_virtual_call: | |
3413 case lir_icvirtual_call: | |
1564 | 3414 case lir_optvirtual_call: |
3415 case lir_dynamic_call: { | |
0 | 3416 LIR_Op* prev = inst->at(i - 1); |
3417 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && | |
3418 (op->code() != lir_virtual_call || | |
3419 !prev->result_opr()->is_single_cpu() || | |
3420 prev->result_opr()->as_register() != O0) && | |
3421 LIR_Assembler::is_single_instruction(prev)) { | |
3422 // Only moves without info can be put into the delay slot. | |
3423 // Also don't allow the setup of the receiver in the delay | |
3424 // slot for vtable calls. | |
3425 inst->at_put(i - 1, op); | |
3426 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3427 #ifndef PRODUCT | |
3428 if (LIRTracePeephole) { | |
3429 tty->print_cr("delayed"); | |
3430 inst->at(i - 1)->print(); | |
3431 inst->at(i)->print(); | |
1564 | 3432 tty->cr(); |
0 | 3433 } |
3434 #endif | |
1783 | 3435 } else { |
3436 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); | |
3437 inst->insert_before(i + 1, delay_op); | |
3438 i++; | |
0 | 3439 } |
3440 | |
1783 | 3441 #if defined(TIERED) && !defined(_LP64) |
3442 // fixup the return value from G1 to O0/O1 for long returns. | |
3443 // It's done here instead of in LIRGenerator because there's | |
3444 // such a mismatch between the single reg and double reg | |
3445 // calling convention. | |
3446 LIR_OpJavaCall* callop = op->as_OpJavaCall(); | |
3447 if (callop->result_opr() == FrameMap::out_long_opr) { | |
3448 LIR_OpJavaCall* call; | |
3449 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); | |
3450 for (int a = 0; a < arguments->length(); a++) { | |
3451 arguments[a] = callop->arguments()[a]; | |
3452 } | |
3453 if (op->code() == lir_virtual_call) { | |
3454 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3455 callop->vtable_offset(), arguments, callop->info()); | |
3456 } else { | |
3457 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3458 callop->addr(), arguments, callop->info()); | |
3459 } | |
3460 inst->at_put(i - 1, call); | |
3461 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), | |
3462 T_LONG, lir_patch_none, NULL)); | |
3463 } | |
3464 #endif | |
0 | 3465 break; |
3466 } | |
3467 } | |
3468 } | |
3469 } | |
3470 | |
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3471 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { |
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3472 LIR_Address* addr = src->as_address_ptr(); |
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3473 |
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3474 assert(data == dest, "swap uses only 2 operands"); |
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3475 assert (code == lir_xchg, "no xadd on sparc"); |
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3476 |
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3477 if (data->type() == T_INT) { |
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3478 __ swap(as_Address(addr), data->as_register()); |
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3479 } else if (data->is_oop()) { |
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3480 Register obj = data->as_register(); |
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3481 Register narrow = tmp->as_register(); |
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3482 #ifdef _LP64 |
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3483 assert(UseCompressedOops, "swap is 32bit only"); |
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3484 __ encode_heap_oop(obj, narrow); |
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3485 __ swap(as_Address(addr), narrow); |
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3486 __ decode_heap_oop(narrow, obj); |
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3487 #else |
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3488 __ swap(as_Address(addr), obj); |
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3489 #endif |
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3490 } else { |
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3491 ShouldNotReachHere(); |
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3492 } |
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3493 } |
0 | 3494 |
3495 #undef __ |