Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 1783:d5d065957597
6953144: Tiered compilation
Summary: Infrastructure for tiered compilation support (interpreter + c1 + c2) for 32 and 64 bit. Simple tiered policy implementation.
Reviewed-by: kvn, never, phh, twisti
| author | iveresov |
|---|---|
| date | Fri, 03 Sep 2010 17:51:07 -0700 |
| parents | e9ff18c4ace7 |
| children | 3a294e483abc |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1378
diff
changeset
|
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1378
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1378
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1378
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 25 # include "incls/_precompiled.incl" | |
| 26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl" | |
| 27 | |
| 28 #define __ _masm-> | |
| 29 | |
| 30 | |
| 31 //------------------------------------------------------------ | |
| 32 | |
| 33 | |
| 34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 35 if (opr->is_constant()) { | |
| 36 LIR_Const* constant = opr->as_constant_ptr(); | |
| 37 switch (constant->type()) { | |
| 38 case T_INT: { | |
| 39 jint value = constant->as_jint(); | |
| 40 return Assembler::is_simm13(value); | |
| 41 } | |
| 42 | |
| 43 default: | |
| 44 return false; | |
| 45 } | |
| 46 } | |
| 47 return false; | |
| 48 } | |
| 49 | |
| 50 | |
| 51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { | |
| 52 switch (op->code()) { | |
| 53 case lir_null_check: | |
| 54 return true; | |
| 55 | |
| 56 | |
| 57 case lir_add: | |
| 58 case lir_ushr: | |
| 59 case lir_shr: | |
| 60 case lir_shl: | |
| 61 // integer shifts and adds are always one instruction | |
| 62 return op->result_opr()->is_single_cpu(); | |
| 63 | |
| 64 | |
| 65 case lir_move: { | |
| 66 LIR_Op1* op1 = op->as_Op1(); | |
| 67 LIR_Opr src = op1->in_opr(); | |
| 68 LIR_Opr dst = op1->result_opr(); | |
| 69 | |
| 70 if (src == dst) { | |
| 71 NEEDS_CLEANUP; | |
| 72 // this works around a problem where moves with the same src and dst | |
| 73 // end up in the delay slot and then the assembler swallows the mov | |
| 74 // since it has no effect and then it complains because the delay slot | |
| 75 // is empty. returning false stops the optimizer from putting this in | |
| 76 // the delay slot | |
| 77 return false; | |
| 78 } | |
| 79 | |
| 80 // don't put moves involving oops into the delay slot since the VerifyOops code | |
| 81 // will make it much larger than a single instruction. | |
| 82 if (VerifyOops) { | |
| 83 return false; | |
| 84 } | |
| 85 | |
| 86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || | |
| 87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { | |
| 88 return false; | |
| 89 } | |
| 90 | |
| 91 if (dst->is_register()) { | |
| 92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { | |
| 93 return !PatchALot; | |
| 94 } else if (src->is_single_stack()) { | |
| 95 return true; | |
| 96 } | |
| 97 } | |
| 98 | |
| 99 if (src->is_register()) { | |
| 100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { | |
| 101 return !PatchALot; | |
| 102 } else if (dst->is_single_stack()) { | |
| 103 return true; | |
| 104 } | |
| 105 } | |
| 106 | |
| 107 if (dst->is_register() && | |
| 108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || | |
| 109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { | |
| 110 return true; | |
| 111 } | |
| 112 | |
| 113 return false; | |
| 114 } | |
| 115 | |
| 116 default: | |
| 117 return false; | |
| 118 } | |
| 119 ShouldNotReachHere(); | |
| 120 } | |
| 121 | |
| 122 | |
| 123 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 124 return FrameMap::O0_oop_opr; | |
| 125 } | |
| 126 | |
| 127 | |
| 128 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
| 129 return FrameMap::I0_oop_opr; | |
| 130 } | |
| 131 | |
| 132 | |
| 133 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 134 return FrameMap::I0_opr; | |
| 135 } | |
| 136 | |
| 137 | |
| 138 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 139 return in_bytes(frame_map()->framesize_in_bytes()); | |
| 140 } | |
| 141 | |
| 142 | |
| 143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); | |
| 144 // we fetch the class of the receiver (O0) and compare it with the cached class. | |
| 145 // If they do not match we jump to slow case. | |
| 146 int LIR_Assembler::check_icache() { | |
| 147 int offset = __ offset(); | |
| 148 __ inline_cache_check(O0, G5_inline_cache_reg); | |
| 149 return offset; | |
| 150 } | |
| 151 | |
| 152 | |
| 153 void LIR_Assembler::osr_entry() { | |
| 154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): | |
| 155 // | |
| 156 // 1. Create a new compiled activation. | |
| 157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty | |
| 158 // at the osr_bci; it is not initialized. | |
| 159 // 3. Jump to the continuation address in compiled code to resume execution. | |
| 160 | |
| 161 // OSR entry point | |
| 162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 163 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 164 ValueStack* entry_state = osr_entry->end()->state(); | |
| 165 int number_of_locks = entry_state->locks_size(); | |
| 166 | |
| 167 // Create a frame for the compiled activation. | |
| 168 __ build_frame(initial_frame_size_in_bytes()); | |
| 169 | |
| 170 // OSR buffer is | |
| 171 // | |
| 172 // locals[nlocals-1..0] | |
| 173 // monitors[number_of_locks-1..0] | |
| 174 // | |
| 175 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 176 // so first slot in the local array is the last local from the interpreter | |
| 177 // and last slot is local[0] (receiver) from the interpreter | |
| 178 // | |
| 179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 181 // in the interpreter frame (the method lock if a sync method) | |
| 182 | |
| 183 // Initialize monitors in the compiled activation. | |
| 184 // I0: pointer to osr buffer | |
| 185 // | |
| 186 // All other registers are dead at this point and the locals will be | |
| 187 // copied into place by code emitted in the IR. | |
| 188 | |
| 189 Register OSR_buf = osrBufferPointer()->as_register(); | |
| 190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); | |
| 191 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 1060 | 192 (2 * BytesPerWord) * (number_of_locks - 1); |
| 193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
| 194 // the OSR buffer using 2 word entries: first the lock and then | |
| 195 // the oop. | |
| 0 | 196 for (int i = 0; i < number_of_locks; i++) { |
| 1060 | 197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
| 0 | 198 #ifdef ASSERT |
| 199 // verify the interpreter's monitor has a non-null object | |
| 200 { | |
| 201 Label L; | |
| 1060 | 202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
| 0 | 203 __ cmp(G0, O7); |
| 204 __ br(Assembler::notEqual, false, Assembler::pt, L); | |
| 205 __ delayed()->nop(); | |
| 206 __ stop("locked object is NULL"); | |
| 207 __ bind(L); | |
| 208 } | |
| 209 #endif // ASSERT | |
| 210 // Copy the lock field into the compiled activation. | |
| 1060 | 211 __ ld_ptr(OSR_buf, slot_offset + 0, O7); |
| 0 | 212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
| 1060 | 213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
| 0 | 214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
| 215 } | |
| 216 } | |
| 217 } | |
| 218 | |
| 219 | |
| 220 // Optimized Library calls | |
| 221 // This is the fast version of java.lang.String.compare; it has not | |
| 222 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { | |
| 224 Register str0 = left->as_register(); | |
| 225 Register str1 = right->as_register(); | |
| 226 | |
| 227 Label Ldone; | |
| 228 | |
| 229 Register result = dst->as_register(); | |
| 230 { | |
| 231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 | |
| 232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 | |
| 233 // Also, get string0.count-string1.count in o7 and get the condition code set | |
| 234 // Note: some instructions have been hoisted for better instruction scheduling | |
| 235 | |
| 236 Register tmp0 = L0; | |
| 237 Register tmp1 = L1; | |
| 238 Register tmp2 = L2; | |
| 239 | |
| 240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array | |
| 241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
| 242 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
| 243 | |
| 727 | 244 __ ld_ptr(str0, value_offset, tmp0); |
| 245 __ ld(str0, offset_offset, tmp2); | |
| 0 | 246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); |
| 727 | 247 __ ld(str0, count_offset, str0); |
| 0 | 248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
| 249 | |
| 250 // str1 may be null | |
| 251 add_debug_info_for_null_check_here(info); | |
| 252 | |
| 727 | 253 __ ld_ptr(str1, value_offset, tmp1); |
| 0 | 254 __ add(tmp0, tmp2, tmp0); |
| 255 | |
| 727 | 256 __ ld(str1, offset_offset, tmp2); |
| 0 | 257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); |
| 727 | 258 __ ld(str1, count_offset, str1); |
| 0 | 259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
| 260 __ subcc(str0, str1, O7); | |
| 261 __ add(tmp1, tmp2, tmp1); | |
| 262 } | |
| 263 | |
| 264 { | |
| 265 // Compute the minimum of the string lengths, scale it and store it in limit | |
| 266 Register count0 = I0; | |
| 267 Register count1 = I1; | |
| 268 Register limit = L3; | |
| 269 | |
| 270 Label Lskip; | |
| 271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter | |
| 272 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
| 273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter | |
| 274 __ bind(Lskip); | |
| 275 | |
| 276 // If either string is empty (or both of them) the result is the difference in lengths | |
| 277 __ cmp(limit, 0); | |
| 278 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 279 __ delayed()->mov(O7, result); // result is difference in lengths | |
| 280 } | |
| 281 | |
| 282 { | |
| 283 // Neither string is empty | |
| 284 Label Lloop; | |
| 285 | |
| 286 Register base0 = L0; | |
| 287 Register base1 = L1; | |
| 288 Register chr0 = I0; | |
| 289 Register chr1 = I1; | |
| 290 Register limit = L3; | |
| 291 | |
| 292 // Shift base0 and base1 to the end of the arrays, negate limit | |
| 293 __ add(base0, limit, base0); | |
| 294 __ add(base1, limit, base1); | |
| 295 __ neg(limit); // limit = -min{string0.count, strin1.count} | |
| 296 | |
| 297 __ lduh(base0, limit, chr0); | |
| 298 __ bind(Lloop); | |
| 299 __ lduh(base1, limit, chr1); | |
| 300 __ subcc(chr0, chr1, chr0); | |
| 301 __ br(Assembler::notZero, false, Assembler::pn, Ldone); | |
| 302 assert(chr0 == result, "result must be pre-placed"); | |
| 303 __ delayed()->inccc(limit, sizeof(jchar)); | |
| 304 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
| 305 __ delayed()->lduh(base0, limit, chr0); | |
| 306 } | |
| 307 | |
| 308 // If strings are equal up to min length, return the length difference. | |
| 309 __ mov(O7, result); | |
| 310 | |
| 311 // Otherwise, return the difference between the first mismatched chars. | |
| 312 __ bind(Ldone); | |
| 313 } | |
| 314 | |
| 315 | |
| 316 // -------------------------------------------------------------------------------------------- | |
| 317 | |
| 318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { | |
| 319 if (!GenerateSynchronizationCode) return; | |
| 320 | |
| 321 Register obj_reg = obj_opr->as_register(); | |
| 322 Register lock_reg = lock_opr->as_register(); | |
| 323 | |
| 324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 325 Register reg = mon_addr.base(); | |
| 326 int offset = mon_addr.disp(); | |
| 327 // compute pointer to BasicLock | |
| 328 if (mon_addr.is_simm13()) { | |
| 329 __ add(reg, offset, lock_reg); | |
| 330 } | |
| 331 else { | |
| 332 __ set(offset, lock_reg); | |
| 333 __ add(reg, lock_reg, lock_reg); | |
| 334 } | |
| 335 // unlock object | |
| 336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); | |
| 337 // _slow_case_stubs->append(slow_case); | |
| 338 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
| 339 _slow_case_stubs->append(slow_case); | |
| 340 if (UseFastLocking) { | |
| 341 // try inlined fast unlocking first, revert to slow locking if it fails | |
| 342 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
| 343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
| 345 } else { | |
| 346 // always do slow unlocking | |
| 347 // note: the slow unlocking code could be inlined here, however if we use | |
| 348 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 349 // simpler and requires less duplicated code - additionally, the | |
| 350 // slow unlocking code is the same in either case which simplifies | |
| 351 // debugging | |
| 352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); | |
| 353 __ delayed()->nop(); | |
| 354 } | |
| 355 // done | |
| 356 __ bind(*slow_case->continuation()); | |
| 357 } | |
| 358 | |
| 359 | |
| 1204 | 360 int LIR_Assembler::emit_exception_handler() { |
| 0 | 361 // if the last instruction is a call (typically to do a throw which |
| 362 // is coming at the end after block reordering) the return address | |
| 363 // must still point into the code area in order to avoid assertion | |
| 364 // failures when searching for the corresponding bci => add a nop | |
| 365 // (was bug 5/14/1999 - gri) | |
| 366 __ nop(); | |
| 367 | |
| 368 // generate code for exception handler | |
| 369 ciMethod* method = compilation()->method(); | |
| 370 | |
| 371 address handler_base = __ start_a_stub(exception_handler_size); | |
| 372 | |
| 373 if (handler_base == NULL) { | |
| 374 // not enough space left for the handler | |
| 375 bailout("exception handler overflow"); | |
| 1204 | 376 return -1; |
| 0 | 377 } |
| 1204 | 378 |
| 0 | 379 int offset = code_offset(); |
| 380 | |
| 1295 | 381 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
| 0 | 382 __ delayed()->nop(); |
| 383 debug_only(__ stop("should have gone to the caller");) | |
| 384 assert(code_offset() - offset <= exception_handler_size, "overflow"); | |
| 385 __ end_a_stub(); | |
| 1204 | 386 |
| 387 return offset; | |
| 0 | 388 } |
| 389 | |
| 1204 | 390 |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
391 // Emit the code to remove the frame from the stack in the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
392 // unwind path. |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
393 int LIR_Assembler::emit_unwind_handler() { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
394 #ifndef PRODUCT |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
395 if (CommentedAssembly) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
396 _masm->block_comment("Unwind handler"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
397 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
398 #endif |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
399 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
400 int offset = code_offset(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
401 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
402 // Fetch the exception from TLS and clear out exception related thread state |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
403 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
404 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
405 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
406 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
407 __ bind(_unwind_handler_entry); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
408 __ verify_not_null_oop(O0); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
409 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
410 __ mov(O0, I0); // Preserve the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
411 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
412 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
413 // Preform needed unlocking |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
414 MonitorExitStub* stub = NULL; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
415 if (method()->is_synchronized()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
416 monitor_address(0, FrameMap::I1_opr); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
417 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
418 __ unlock_object(I3, I2, I1, *stub->entry()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
419 __ bind(*stub->continuation()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
420 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
421 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
422 if (compilation()->env()->dtrace_method_probes()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
423 jobject2reg(method()->constant_encoding(), O0); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
424 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
425 __ delayed()->nop(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
426 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
427 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
428 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
429 __ mov(I0, O0); // Restore the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
430 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
431 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
432 // dispatch to the unwind logic |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
433 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
434 __ delayed()->nop(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
435 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
436 // Emit the slow path assembly |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
437 if (stub != NULL) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
438 stub->emit_code(this); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
439 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
440 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
441 return offset; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
442 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
443 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
444 |
| 1204 | 445 int LIR_Assembler::emit_deopt_handler() { |
| 0 | 446 // if the last instruction is a call (typically to do a throw which |
| 447 // is coming at the end after block reordering) the return address | |
| 448 // must still point into the code area in order to avoid assertion | |
| 449 // failures when searching for the corresponding bci => add a nop | |
| 450 // (was bug 5/14/1999 - gri) | |
| 451 __ nop(); | |
| 452 | |
| 453 // generate code for deopt handler | |
| 454 ciMethod* method = compilation()->method(); | |
| 455 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 456 if (handler_base == NULL) { | |
| 457 // not enough space left for the handler | |
| 458 bailout("deopt handler overflow"); | |
| 1204 | 459 return -1; |
| 0 | 460 } |
| 1204 | 461 |
| 0 | 462 int offset = code_offset(); |
| 727 | 463 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 464 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp | |
| 0 | 465 __ delayed()->nop(); |
| 466 assert(code_offset() - offset <= deopt_handler_size, "overflow"); | |
| 467 debug_only(__ stop("should have gone to the caller");) | |
| 468 __ end_a_stub(); | |
| 1204 | 469 |
| 470 return offset; | |
| 0 | 471 } |
| 472 | |
| 473 | |
| 474 void LIR_Assembler::jobject2reg(jobject o, Register reg) { | |
| 475 if (o == NULL) { | |
| 476 __ set(NULL_WORD, reg); | |
| 477 } else { | |
| 478 int oop_index = __ oop_recorder()->find_index(o); | |
| 479 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
| 480 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created | |
| 481 } | |
| 482 } | |
| 483 | |
| 484 | |
| 485 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { | |
| 486 // Allocate a new index in oop table to hold the oop once it's been patched | |
| 487 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); | |
| 488 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); | |
| 489 | |
| 727 | 490 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); |
| 491 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); | |
| 0 | 492 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
| 493 // NULL will be dynamically patched later and the patched value may be large. We must | |
| 494 // therefore generate the sethi/add as a placeholders | |
| 727 | 495 __ patchable_set(addrlit, reg); |
| 0 | 496 |
| 497 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 498 } | |
| 499 | |
| 500 | |
| 501 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 502 Register Rdividend = op->in_opr1()->as_register(); | |
| 503 Register Rdivisor = noreg; | |
| 504 Register Rscratch = op->in_opr3()->as_register(); | |
| 505 Register Rresult = op->result_opr()->as_register(); | |
| 506 int divisor = -1; | |
| 507 | |
| 508 if (op->in_opr2()->is_register()) { | |
| 509 Rdivisor = op->in_opr2()->as_register(); | |
| 510 } else { | |
| 511 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); | |
| 512 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
| 513 } | |
| 514 | |
| 515 assert(Rdividend != Rscratch, ""); | |
| 516 assert(Rdivisor != Rscratch, ""); | |
| 517 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); | |
| 518 | |
| 519 if (Rdivisor == noreg && is_power_of_2(divisor)) { | |
| 520 // convert division by a power of two into some shifts and logical operations | |
| 521 if (op->code() == lir_idiv) { | |
| 522 if (divisor == 2) { | |
| 523 __ srl(Rdividend, 31, Rscratch); | |
| 524 } else { | |
| 525 __ sra(Rdividend, 31, Rscratch); | |
| 526 __ and3(Rscratch, divisor - 1, Rscratch); | |
| 527 } | |
| 528 __ add(Rdividend, Rscratch, Rscratch); | |
| 529 __ sra(Rscratch, log2_intptr(divisor), Rresult); | |
| 530 return; | |
| 531 } else { | |
| 532 if (divisor == 2) { | |
| 533 __ srl(Rdividend, 31, Rscratch); | |
| 534 } else { | |
| 535 __ sra(Rdividend, 31, Rscratch); | |
| 536 __ and3(Rscratch, divisor - 1,Rscratch); | |
| 537 } | |
| 538 __ add(Rdividend, Rscratch, Rscratch); | |
| 539 __ andn(Rscratch, divisor - 1,Rscratch); | |
| 540 __ sub(Rdividend, Rscratch, Rresult); | |
| 541 return; | |
| 542 } | |
| 543 } | |
| 544 | |
| 545 __ sra(Rdividend, 31, Rscratch); | |
| 546 __ wry(Rscratch); | |
| 547 if (!VM_Version::v9_instructions_work()) { | |
| 548 // v9 doesn't require these nops | |
| 549 __ nop(); | |
| 550 __ nop(); | |
| 551 __ nop(); | |
| 552 __ nop(); | |
| 553 } | |
| 554 | |
| 555 add_debug_info_for_div0_here(op->info()); | |
| 556 | |
| 557 if (Rdivisor != noreg) { | |
| 558 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 559 } else { | |
| 560 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
| 561 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 562 } | |
| 563 | |
| 564 Label skip; | |
| 565 __ br(Assembler::overflowSet, true, Assembler::pn, skip); | |
| 566 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 567 __ bind(skip); | |
| 568 | |
| 569 if (op->code() == lir_irem) { | |
| 570 if (Rdivisor != noreg) { | |
| 571 __ smul(Rscratch, Rdivisor, Rscratch); | |
| 572 } else { | |
| 573 __ smul(Rscratch, divisor, Rscratch); | |
| 574 } | |
| 575 __ sub(Rdividend, Rscratch, Rresult); | |
| 576 } | |
| 577 } | |
| 578 | |
| 579 | |
| 580 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 581 #ifdef ASSERT | |
| 582 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 583 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 584 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 585 #endif | |
| 586 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); | |
| 587 | |
| 588 if (op->cond() == lir_cond_always) { | |
| 589 __ br(Assembler::always, false, Assembler::pt, *(op->label())); | |
| 590 } else if (op->code() == lir_cond_float_branch) { | |
| 591 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 592 bool is_unordered = (op->ublock() == op->block()); | |
| 593 Assembler::Condition acond; | |
| 594 switch (op->cond()) { | |
| 595 case lir_cond_equal: acond = Assembler::f_equal; break; | |
| 596 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; | |
| 597 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; | |
| 598 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; | |
| 599 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; | |
| 600 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; | |
| 601 default : ShouldNotReachHere(); | |
| 602 }; | |
| 603 | |
| 604 if (!VM_Version::v9_instructions_work()) { | |
| 605 __ nop(); | |
| 606 } | |
| 607 __ fb( acond, false, Assembler::pn, *(op->label())); | |
| 608 } else { | |
| 609 assert (op->code() == lir_branch, "just checking"); | |
| 610 | |
| 611 Assembler::Condition acond; | |
| 612 switch (op->cond()) { | |
| 613 case lir_cond_equal: acond = Assembler::equal; break; | |
| 614 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 615 case lir_cond_less: acond = Assembler::less; break; | |
| 616 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 617 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
| 618 case lir_cond_greater: acond = Assembler::greater; break; | |
| 619 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
| 620 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
| 621 default: ShouldNotReachHere(); | |
| 622 }; | |
| 623 | |
| 624 // sparc has different condition codes for testing 32-bit | |
| 625 // vs. 64-bit values. We could always test xcc is we could | |
| 626 // guarantee that 32-bit loads always sign extended but that isn't | |
| 627 // true and since sign extension isn't free, it would impose a | |
| 628 // slight cost. | |
| 629 #ifdef _LP64 | |
| 630 if (op->type() == T_INT) { | |
| 631 __ br(acond, false, Assembler::pn, *(op->label())); | |
| 632 } else | |
| 633 #endif | |
| 634 __ brx(acond, false, Assembler::pn, *(op->label())); | |
| 635 } | |
| 636 // The peephole pass fills the delay slot | |
| 637 } | |
| 638 | |
| 639 | |
| 640 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 641 Bytecodes::Code code = op->bytecode(); | |
| 642 LIR_Opr dst = op->result_opr(); | |
| 643 | |
| 644 switch(code) { | |
| 645 case Bytecodes::_i2l: { | |
| 646 Register rlo = dst->as_register_lo(); | |
| 647 Register rhi = dst->as_register_hi(); | |
| 648 Register rval = op->in_opr()->as_register(); | |
| 649 #ifdef _LP64 | |
| 650 __ sra(rval, 0, rlo); | |
| 651 #else | |
| 652 __ mov(rval, rlo); | |
| 653 __ sra(rval, BitsPerInt-1, rhi); | |
| 654 #endif | |
| 655 break; | |
| 656 } | |
| 657 case Bytecodes::_i2d: | |
| 658 case Bytecodes::_i2f: { | |
| 659 bool is_double = (code == Bytecodes::_i2d); | |
| 660 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
| 661 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
| 662 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
| 663 if (rsrc != rdst) { | |
| 664 __ fmov(FloatRegisterImpl::S, rsrc, rdst); | |
| 665 } | |
| 666 __ fitof(w, rdst, rdst); | |
| 667 break; | |
| 668 } | |
| 669 case Bytecodes::_f2i:{ | |
| 670 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
| 671 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); | |
| 672 Label L; | |
| 673 // result must be 0 if value is NaN; test by comparing value to itself | |
| 674 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); | |
| 675 if (!VM_Version::v9_instructions_work()) { | |
| 676 __ nop(); | |
| 677 } | |
| 678 __ fb(Assembler::f_unordered, true, Assembler::pn, L); | |
| 679 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN | |
| 680 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); | |
| 681 // move integer result from float register to int register | |
| 682 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); | |
| 683 __ bind (L); | |
| 684 break; | |
| 685 } | |
| 686 case Bytecodes::_l2i: { | |
| 687 Register rlo = op->in_opr()->as_register_lo(); | |
| 688 Register rhi = op->in_opr()->as_register_hi(); | |
| 689 Register rdst = dst->as_register(); | |
| 690 #ifdef _LP64 | |
| 691 __ sra(rlo, 0, rdst); | |
| 692 #else | |
| 693 __ mov(rlo, rdst); | |
| 694 #endif | |
| 695 break; | |
| 696 } | |
| 697 case Bytecodes::_d2f: | |
| 698 case Bytecodes::_f2d: { | |
| 699 bool is_double = (code == Bytecodes::_f2d); | |
| 700 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); | |
| 701 LIR_Opr val = op->in_opr(); | |
| 702 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); | |
| 703 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
| 704 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; | |
| 705 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
| 706 __ ftof(vw, dw, rval, rdst); | |
| 707 break; | |
| 708 } | |
| 709 case Bytecodes::_i2s: | |
| 710 case Bytecodes::_i2b: { | |
| 711 Register rval = op->in_opr()->as_register(); | |
| 712 Register rdst = dst->as_register(); | |
| 713 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); | |
| 714 __ sll (rval, shift, rdst); | |
| 715 __ sra (rdst, shift, rdst); | |
| 716 break; | |
| 717 } | |
| 718 case Bytecodes::_i2c: { | |
| 719 Register rval = op->in_opr()->as_register(); | |
| 720 Register rdst = dst->as_register(); | |
| 721 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; | |
| 722 __ sll (rval, shift, rdst); | |
| 723 __ srl (rdst, shift, rdst); | |
| 724 break; | |
| 725 } | |
| 726 | |
| 727 default: ShouldNotReachHere(); | |
| 728 } | |
| 729 } | |
| 730 | |
| 731 | |
| 732 void LIR_Assembler::align_call(LIR_Code) { | |
| 733 // do nothing since all instructions are word aligned on sparc | |
| 734 } | |
| 735 | |
| 736 | |
| 1295 | 737 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
| 738 __ call(op->addr(), rtype); | |
| 1564 | 739 // The peephole pass fills the delay slot, add_call_info is done in |
| 740 // LIR_Assembler::emit_delay. | |
| 0 | 741 } |
| 742 | |
| 743 | |
| 1295 | 744 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
| 0 | 745 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); |
| 746 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); | |
| 747 __ relocate(rspec); | |
| 1295 | 748 __ call(op->addr(), relocInfo::none); |
| 1564 | 749 // The peephole pass fills the delay slot, add_call_info is done in |
| 750 // LIR_Assembler::emit_delay. | |
| 0 | 751 } |
| 752 | |
| 753 | |
| 1295 | 754 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
| 755 add_debug_info_for_null_check_here(op->info()); | |
| 727 | 756 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch); |
| 1295 | 757 if (__ is_simm13(op->vtable_offset())) { |
| 758 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); | |
| 0 | 759 } else { |
| 760 // This will generate 2 instructions | |
| 1295 | 761 __ set(op->vtable_offset(), G5_method); |
| 0 | 762 // ld_ptr, set_hi, set |
| 763 __ ld_ptr(G3_scratch, G5_method, G5_method); | |
| 764 } | |
| 727 | 765 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch); |
| 0 | 766 __ callr(G3_scratch, G0); |
| 767 // the peephole pass fills the delay slot | |
| 768 } | |
| 769 | |
| 770 | |
| 771 // load with 32-bit displacement | |
| 772 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { | |
| 773 int load_offset = code_offset(); | |
| 774 if (Assembler::is_simm13(disp)) { | |
| 775 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 776 switch(ld_type) { | |
| 777 case T_BOOLEAN: // fall through | |
| 778 case T_BYTE : __ ldsb(s, disp, d); break; | |
| 779 case T_CHAR : __ lduh(s, disp, d); break; | |
| 780 case T_SHORT : __ ldsh(s, disp, d); break; | |
| 781 case T_INT : __ ld(s, disp, d); break; | |
| 782 case T_ADDRESS:// fall through | |
| 783 case T_ARRAY : // fall through | |
| 784 case T_OBJECT: __ ld_ptr(s, disp, d); break; | |
| 785 default : ShouldNotReachHere(); | |
| 786 } | |
| 787 } else { | |
| 727 | 788 __ set(disp, O7); |
| 0 | 789 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 790 load_offset = code_offset(); | |
| 791 switch(ld_type) { | |
| 792 case T_BOOLEAN: // fall through | |
| 793 case T_BYTE : __ ldsb(s, O7, d); break; | |
| 794 case T_CHAR : __ lduh(s, O7, d); break; | |
| 795 case T_SHORT : __ ldsh(s, O7, d); break; | |
| 796 case T_INT : __ ld(s, O7, d); break; | |
| 797 case T_ADDRESS:// fall through | |
| 798 case T_ARRAY : // fall through | |
| 799 case T_OBJECT: __ ld_ptr(s, O7, d); break; | |
| 800 default : ShouldNotReachHere(); | |
| 801 } | |
| 802 } | |
| 803 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); | |
| 804 return load_offset; | |
| 805 } | |
| 806 | |
| 807 | |
| 808 // store with 32-bit displacement | |
| 809 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { | |
| 810 if (Assembler::is_simm13(offset)) { | |
| 811 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 812 switch (type) { | |
| 813 case T_BOOLEAN: // fall through | |
| 814 case T_BYTE : __ stb(value, base, offset); break; | |
| 815 case T_CHAR : __ sth(value, base, offset); break; | |
| 816 case T_SHORT : __ sth(value, base, offset); break; | |
| 817 case T_INT : __ stw(value, base, offset); break; | |
| 818 case T_ADDRESS:// fall through | |
| 819 case T_ARRAY : // fall through | |
| 820 case T_OBJECT: __ st_ptr(value, base, offset); break; | |
| 821 default : ShouldNotReachHere(); | |
| 822 } | |
| 823 } else { | |
| 727 | 824 __ set(offset, O7); |
| 0 | 825 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 826 switch (type) { | |
| 827 case T_BOOLEAN: // fall through | |
| 828 case T_BYTE : __ stb(value, base, O7); break; | |
| 829 case T_CHAR : __ sth(value, base, O7); break; | |
| 830 case T_SHORT : __ sth(value, base, O7); break; | |
| 831 case T_INT : __ stw(value, base, O7); break; | |
| 832 case T_ADDRESS:// fall through | |
| 833 case T_ARRAY : //fall through | |
| 834 case T_OBJECT: __ st_ptr(value, base, O7); break; | |
| 835 default : ShouldNotReachHere(); | |
| 836 } | |
| 837 } | |
| 838 // Note: Do the store before verification as the code might be patched! | |
| 839 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); | |
| 840 } | |
| 841 | |
| 842 | |
| 843 // load float with 32-bit displacement | |
| 844 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { | |
| 845 FloatRegisterImpl::Width w; | |
| 846 switch(ld_type) { | |
| 847 case T_FLOAT : w = FloatRegisterImpl::S; break; | |
| 848 case T_DOUBLE: w = FloatRegisterImpl::D; break; | |
| 849 default : ShouldNotReachHere(); | |
| 850 } | |
| 851 | |
| 852 if (Assembler::is_simm13(disp)) { | |
| 853 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 854 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { | |
| 855 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); | |
| 856 __ ldf(FloatRegisterImpl::S, s, disp , d); | |
| 857 } else { | |
| 858 __ ldf(w, s, disp, d); | |
| 859 } | |
| 860 } else { | |
| 727 | 861 __ set(disp, O7); |
| 0 | 862 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 863 __ ldf(w, s, O7, d); | |
| 864 } | |
| 865 } | |
| 866 | |
| 867 | |
| 868 // store float with 32-bit displacement | |
| 869 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { | |
| 870 FloatRegisterImpl::Width w; | |
| 871 switch(type) { | |
| 872 case T_FLOAT : w = FloatRegisterImpl::S; break; | |
| 873 case T_DOUBLE: w = FloatRegisterImpl::D; break; | |
| 874 default : ShouldNotReachHere(); | |
| 875 } | |
| 876 | |
| 877 if (Assembler::is_simm13(offset)) { | |
| 878 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 879 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { | |
| 880 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); | |
| 881 __ stf(FloatRegisterImpl::S, value , base, offset); | |
| 882 } else { | |
| 883 __ stf(w, value, base, offset); | |
| 884 } | |
| 885 } else { | |
| 727 | 886 __ set(offset, O7); |
| 0 | 887 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 888 __ stf(w, value, O7, base); | |
| 889 } | |
| 890 } | |
| 891 | |
| 892 | |
| 893 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { | |
| 894 int store_offset; | |
| 895 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
| 896 assert(!unaligned, "can't handle this"); | |
| 897 // for offsets larger than a simm13 we setup the offset in O7 | |
| 727 | 898 __ set(offset, O7); |
| 0 | 899 store_offset = store(from_reg, base, O7, type); |
| 900 } else { | |
| 901 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); | |
| 902 store_offset = code_offset(); | |
| 903 switch (type) { | |
| 904 case T_BOOLEAN: // fall through | |
| 905 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; | |
| 906 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; | |
| 907 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; | |
| 908 case T_INT : __ stw(from_reg->as_register(), base, offset); break; | |
| 909 case T_LONG : | |
| 910 #ifdef _LP64 | |
| 911 if (unaligned || PatchALot) { | |
| 912 __ srax(from_reg->as_register_lo(), 32, O7); | |
| 913 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
| 914 __ stw(O7, base, offset + hi_word_offset_in_bytes); | |
| 915 } else { | |
| 916 __ stx(from_reg->as_register_lo(), base, offset); | |
| 917 } | |
| 918 #else | |
| 919 assert(Assembler::is_simm13(offset + 4), "must be"); | |
| 920 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
| 921 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); | |
| 922 #endif | |
| 923 break; | |
| 924 case T_ADDRESS:// fall through | |
| 925 case T_ARRAY : // fall through | |
| 926 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; | |
| 927 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; | |
| 928 case T_DOUBLE: | |
| 929 { | |
| 930 FloatRegister reg = from_reg->as_double_reg(); | |
| 931 // split unaligned stores | |
| 932 if (unaligned || PatchALot) { | |
| 933 assert(Assembler::is_simm13(offset + 4), "must be"); | |
| 934 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); | |
| 935 __ stf(FloatRegisterImpl::S, reg, base, offset); | |
| 936 } else { | |
| 937 __ stf(FloatRegisterImpl::D, reg, base, offset); | |
| 938 } | |
| 939 break; | |
| 940 } | |
| 941 default : ShouldNotReachHere(); | |
| 942 } | |
| 943 } | |
| 944 return store_offset; | |
| 945 } | |
| 946 | |
| 947 | |
| 948 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { | |
| 949 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); | |
| 950 int store_offset = code_offset(); | |
| 951 switch (type) { | |
| 952 case T_BOOLEAN: // fall through | |
| 953 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; | |
| 954 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; | |
| 955 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; | |
| 956 case T_INT : __ stw(from_reg->as_register(), base, disp); break; | |
| 957 case T_LONG : | |
| 958 #ifdef _LP64 | |
| 959 __ stx(from_reg->as_register_lo(), base, disp); | |
| 960 #else | |
| 961 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); | |
| 962 __ std(from_reg->as_register_hi(), base, disp); | |
| 963 #endif | |
| 964 break; | |
| 965 case T_ADDRESS:// fall through | |
| 966 case T_ARRAY : // fall through | |
| 967 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; | |
| 968 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; | |
| 969 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; | |
| 970 default : ShouldNotReachHere(); | |
| 971 } | |
| 972 return store_offset; | |
| 973 } | |
| 974 | |
| 975 | |
| 976 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { | |
| 977 int load_offset; | |
| 978 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
| 979 assert(base != O7, "destroying register"); | |
| 980 assert(!unaligned, "can't handle this"); | |
| 981 // for offsets larger than a simm13 we setup the offset in O7 | |
| 727 | 982 __ set(offset, O7); |
| 0 | 983 load_offset = load(base, O7, to_reg, type); |
| 984 } else { | |
| 985 load_offset = code_offset(); | |
| 986 switch(type) { | |
| 987 case T_BOOLEAN: // fall through | |
| 988 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; | |
| 989 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; | |
| 990 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; | |
| 991 case T_INT : __ ld(base, offset, to_reg->as_register()); break; | |
| 992 case T_LONG : | |
| 993 if (!unaligned) { | |
| 994 #ifdef _LP64 | |
| 995 __ ldx(base, offset, to_reg->as_register_lo()); | |
| 996 #else | |
| 997 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
| 998 "must be sequential"); | |
| 999 __ ldd(base, offset, to_reg->as_register_hi()); | |
| 1000 #endif | |
| 1001 } else { | |
| 1002 #ifdef _LP64 | |
| 1003 assert(base != to_reg->as_register_lo(), "can't handle this"); | |
| 1060 | 1004 assert(O7 != to_reg->as_register_lo(), "can't handle this"); |
| 0 | 1005 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); |
| 1060 | 1006 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last |
| 0 | 1007 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); |
| 1060 | 1008 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); |
| 0 | 1009 #else |
| 1010 if (base == to_reg->as_register_lo()) { | |
| 1011 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
| 1012 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 1013 } else { | |
| 1014 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 1015 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
| 1016 } | |
| 1017 #endif | |
| 1018 } | |
| 1019 break; | |
| 1020 case T_ADDRESS:// fall through | |
| 1021 case T_ARRAY : // fall through | |
| 1022 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; | |
| 1023 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; | |
| 1024 case T_DOUBLE: | |
| 1025 { | |
| 1026 FloatRegister reg = to_reg->as_double_reg(); | |
| 1027 // split unaligned loads | |
| 1028 if (unaligned || PatchALot) { | |
| 1060 | 1029 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); |
| 1030 __ ldf(FloatRegisterImpl::S, base, offset, reg); | |
| 0 | 1031 } else { |
| 1032 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); | |
| 1033 } | |
| 1034 break; | |
| 1035 } | |
| 1036 default : ShouldNotReachHere(); | |
| 1037 } | |
| 1038 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); | |
| 1039 } | |
| 1040 return load_offset; | |
| 1041 } | |
| 1042 | |
| 1043 | |
| 1044 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { | |
| 1045 int load_offset = code_offset(); | |
| 1046 switch(type) { | |
| 1047 case T_BOOLEAN: // fall through | |
| 1048 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; | |
| 1049 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; | |
| 1050 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; | |
| 1051 case T_INT : __ ld(base, disp, to_reg->as_register()); break; | |
| 1052 case T_ADDRESS:// fall through | |
| 1053 case T_ARRAY : // fall through | |
| 1054 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; | |
| 1055 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; | |
| 1056 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; | |
| 1057 case T_LONG : | |
| 1058 #ifdef _LP64 | |
| 1059 __ ldx(base, disp, to_reg->as_register_lo()); | |
| 1060 #else | |
| 1061 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
| 1062 "must be sequential"); | |
| 1063 __ ldd(base, disp, to_reg->as_register_hi()); | |
| 1064 #endif | |
| 1065 break; | |
| 1066 default : ShouldNotReachHere(); | |
| 1067 } | |
| 1068 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); | |
| 1069 return load_offset; | |
| 1070 } | |
| 1071 | |
| 1072 | |
| 1073 // load/store with an Address | |
| 1074 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { | |
| 1075 load(a.base(), a.disp() + offset, d, ld_type, info); | |
| 1076 } | |
| 1077 | |
| 1078 | |
| 1079 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { | |
| 1080 store(value, dest.base(), dest.disp() + offset, type, info); | |
| 1081 } | |
| 1082 | |
| 1083 | |
| 1084 // loadf/storef with an Address | |
| 1085 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { | |
| 1086 load(a.base(), a.disp() + offset, d, ld_type, info); | |
| 1087 } | |
| 1088 | |
| 1089 | |
| 1090 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { | |
| 1091 store(value, dest.base(), dest.disp() + offset, type, info); | |
| 1092 } | |
| 1093 | |
| 1094 | |
| 1095 // load/store with an Address | |
| 1096 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { | |
| 1097 load(as_Address(a), d, ld_type, info); | |
| 1098 } | |
| 1099 | |
| 1100 | |
| 1101 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { | |
| 1102 store(value, as_Address(dest), type, info); | |
| 1103 } | |
| 1104 | |
| 1105 | |
| 1106 // loadf/storef with an Address | |
| 1107 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { | |
| 1108 load(as_Address(a), d, ld_type, info); | |
| 1109 } | |
| 1110 | |
| 1111 | |
| 1112 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { | |
| 1113 store(value, as_Address(dest), type, info); | |
| 1114 } | |
| 1115 | |
| 1116 | |
| 1117 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 1118 LIR_Const* c = src->as_constant_ptr(); | |
| 1119 switch (c->type()) { | |
| 1120 case T_INT: | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
1121 case T_FLOAT: |
|
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
1122 case T_ADDRESS: { |
| 0 | 1123 Register src_reg = O7; |
| 1124 int value = c->as_jint_bits(); | |
| 1125 if (value == 0) { | |
| 1126 src_reg = G0; | |
| 1127 } else { | |
| 1128 __ set(value, O7); | |
| 1129 } | |
| 1130 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1131 __ stw(src_reg, addr.base(), addr.disp()); | |
| 1132 break; | |
| 1133 } | |
| 1134 case T_OBJECT: { | |
| 1135 Register src_reg = O7; | |
| 1136 jobject2reg(c->as_jobject(), src_reg); | |
| 1137 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1138 __ st_ptr(src_reg, addr.base(), addr.disp()); | |
| 1139 break; | |
| 1140 } | |
| 1141 case T_LONG: | |
| 1142 case T_DOUBLE: { | |
| 1143 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
| 1144 | |
| 1145 Register tmp = O7; | |
| 1146 int value_lo = c->as_jint_lo_bits(); | |
| 1147 if (value_lo == 0) { | |
| 1148 tmp = G0; | |
| 1149 } else { | |
| 1150 __ set(value_lo, O7); | |
| 1151 } | |
| 1152 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); | |
| 1153 int value_hi = c->as_jint_hi_bits(); | |
| 1154 if (value_hi == 0) { | |
| 1155 tmp = G0; | |
| 1156 } else { | |
| 1157 __ set(value_hi, O7); | |
| 1158 } | |
| 1159 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); | |
| 1160 break; | |
| 1161 } | |
| 1162 default: | |
| 1163 Unimplemented(); | |
| 1164 } | |
| 1165 } | |
| 1166 | |
| 1167 | |
| 1168 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { | |
| 1169 LIR_Const* c = src->as_constant_ptr(); | |
| 1170 LIR_Address* addr = dest->as_address_ptr(); | |
| 1171 Register base = addr->base()->as_pointer_register(); | |
| 1172 | |
| 1173 if (info != NULL) { | |
| 1174 add_debug_info_for_null_check_here(info); | |
| 1175 } | |
| 1176 switch (c->type()) { | |
| 1177 case T_INT: | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
1178 case T_FLOAT: |
|
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
1179 case T_ADDRESS: { |
| 0 | 1180 LIR_Opr tmp = FrameMap::O7_opr; |
| 1181 int value = c->as_jint_bits(); | |
| 1182 if (value == 0) { | |
| 1183 tmp = FrameMap::G0_opr; | |
| 1184 } else if (Assembler::is_simm13(value)) { | |
| 1185 __ set(value, O7); | |
| 1186 } | |
| 1187 if (addr->index()->is_valid()) { | |
| 1188 assert(addr->disp() == 0, "must be zero"); | |
| 1189 store(tmp, base, addr->index()->as_pointer_register(), type); | |
| 1190 } else { | |
| 1191 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
| 1192 store(tmp, base, addr->disp(), type); | |
| 1193 } | |
| 1194 break; | |
| 1195 } | |
| 1196 case T_LONG: | |
| 1197 case T_DOUBLE: { | |
| 1198 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); | |
| 1199 assert(Assembler::is_simm13(addr->disp()) && | |
| 1200 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); | |
| 1201 | |
| 1202 Register tmp = O7; | |
| 1203 int value_lo = c->as_jint_lo_bits(); | |
| 1204 if (value_lo == 0) { | |
| 1205 tmp = G0; | |
| 1206 } else { | |
| 1207 __ set(value_lo, O7); | |
| 1208 } | |
| 1209 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); | |
| 1210 int value_hi = c->as_jint_hi_bits(); | |
| 1211 if (value_hi == 0) { | |
| 1212 tmp = G0; | |
| 1213 } else { | |
| 1214 __ set(value_hi, O7); | |
| 1215 } | |
| 1216 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); | |
| 1217 break; | |
| 1218 } | |
| 1219 case T_OBJECT: { | |
| 1220 jobject obj = c->as_jobject(); | |
| 1221 LIR_Opr tmp; | |
| 1222 if (obj == NULL) { | |
| 1223 tmp = FrameMap::G0_opr; | |
| 1224 } else { | |
| 1225 tmp = FrameMap::O7_opr; | |
| 1226 jobject2reg(c->as_jobject(), O7); | |
| 1227 } | |
| 1228 // handle either reg+reg or reg+disp address | |
| 1229 if (addr->index()->is_valid()) { | |
| 1230 assert(addr->disp() == 0, "must be zero"); | |
| 1231 store(tmp, base, addr->index()->as_pointer_register(), type); | |
| 1232 } else { | |
| 1233 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
| 1234 store(tmp, base, addr->disp(), type); | |
| 1235 } | |
| 1236 | |
| 1237 break; | |
| 1238 } | |
| 1239 default: | |
| 1240 Unimplemented(); | |
| 1241 } | |
| 1242 } | |
| 1243 | |
| 1244 | |
| 1245 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 1246 LIR_Const* c = src->as_constant_ptr(); | |
| 1247 LIR_Opr to_reg = dest; | |
| 1248 | |
| 1249 switch (c->type()) { | |
| 1250 case T_INT: | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
1251 case T_ADDRESS: |
| 0 | 1252 { |
| 1253 jint con = c->as_jint(); | |
| 1254 if (to_reg->is_single_cpu()) { | |
| 1255 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 1256 __ set(con, to_reg->as_register()); | |
| 1257 } else { | |
| 1258 ShouldNotReachHere(); | |
| 1259 assert(to_reg->is_single_fpu(), "wrong register kind"); | |
| 1260 | |
| 1261 __ set(con, O7); | |
| 727 | 1262 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); |
| 0 | 1263 __ st(O7, temp_slot); |
| 1264 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); | |
| 1265 } | |
| 1266 } | |
| 1267 break; | |
| 1268 | |
| 1269 case T_LONG: | |
| 1270 { | |
| 1271 jlong con = c->as_jlong(); | |
| 1272 | |
| 1273 if (to_reg->is_double_cpu()) { | |
| 1274 #ifdef _LP64 | |
| 1275 __ set(con, to_reg->as_register_lo()); | |
| 1276 #else | |
| 1277 __ set(low(con), to_reg->as_register_lo()); | |
| 1278 __ set(high(con), to_reg->as_register_hi()); | |
| 1279 #endif | |
| 1280 #ifdef _LP64 | |
| 1281 } else if (to_reg->is_single_cpu()) { | |
| 1282 __ set(con, to_reg->as_register()); | |
| 1283 #endif | |
| 1284 } else { | |
| 1285 ShouldNotReachHere(); | |
| 1286 assert(to_reg->is_double_fpu(), "wrong register kind"); | |
| 727 | 1287 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
| 1288 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); | |
| 0 | 1289 __ set(low(con), O7); |
| 1290 __ st(O7, temp_slot_lo); | |
| 1291 __ set(high(con), O7); | |
| 1292 __ st(O7, temp_slot_hi); | |
| 1293 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); | |
| 1294 } | |
| 1295 } | |
| 1296 break; | |
| 1297 | |
| 1298 case T_OBJECT: | |
| 1299 { | |
| 1300 if (patch_code == lir_patch_none) { | |
| 1301 jobject2reg(c->as_jobject(), to_reg->as_register()); | |
| 1302 } else { | |
| 1303 jobject2reg_with_patching(to_reg->as_register(), info); | |
| 1304 } | |
| 1305 } | |
| 1306 break; | |
| 1307 | |
| 1308 case T_FLOAT: | |
| 1309 { | |
| 1310 address const_addr = __ float_constant(c->as_jfloat()); | |
| 1311 if (const_addr == NULL) { | |
| 1312 bailout("const section overflow"); | |
| 1313 break; | |
| 1314 } | |
| 1315 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
| 727 | 1316 AddressLiteral const_addrlit(const_addr, rspec); |
| 0 | 1317 if (to_reg->is_single_fpu()) { |
| 727 | 1318 __ patchable_sethi(const_addrlit, O7); |
| 0 | 1319 __ relocate(rspec); |
| 727 | 1320 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); |
| 0 | 1321 |
| 1322 } else { | |
| 1323 assert(to_reg->is_single_cpu(), "Must be a cpu register."); | |
| 1324 | |
| 727 | 1325 __ set(const_addrlit, O7); |
| 0 | 1326 load(O7, 0, to_reg->as_register(), T_INT); |
| 1327 } | |
| 1328 } | |
| 1329 break; | |
| 1330 | |
| 1331 case T_DOUBLE: | |
| 1332 { | |
| 1333 address const_addr = __ double_constant(c->as_jdouble()); | |
| 1334 if (const_addr == NULL) { | |
| 1335 bailout("const section overflow"); | |
| 1336 break; | |
| 1337 } | |
| 1338 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
| 1339 | |
| 1340 if (to_reg->is_double_fpu()) { | |
| 727 | 1341 AddressLiteral const_addrlit(const_addr, rspec); |
| 1342 __ patchable_sethi(const_addrlit, O7); | |
| 0 | 1343 __ relocate(rspec); |
| 727 | 1344 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); |
| 0 | 1345 } else { |
| 1346 assert(to_reg->is_double_cpu(), "Must be a long register."); | |
| 1347 #ifdef _LP64 | |
| 1348 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); | |
| 1349 #else | |
| 1350 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); | |
| 1351 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); | |
| 1352 #endif | |
| 1353 } | |
| 1354 | |
| 1355 } | |
| 1356 break; | |
| 1357 | |
| 1358 default: | |
| 1359 ShouldNotReachHere(); | |
| 1360 } | |
| 1361 } | |
| 1362 | |
| 1363 Address LIR_Assembler::as_Address(LIR_Address* addr) { | |
| 1364 Register reg = addr->base()->as_register(); | |
| 727 | 1365 return Address(reg, addr->disp()); |
| 0 | 1366 } |
| 1367 | |
| 1368 | |
| 1369 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1370 switch (type) { | |
| 1371 case T_INT: | |
| 1372 case T_FLOAT: { | |
| 1373 Register tmp = O7; | |
| 1374 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1375 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1376 __ lduw(from.base(), from.disp(), tmp); | |
| 1377 __ stw(tmp, to.base(), to.disp()); | |
| 1378 break; | |
| 1379 } | |
| 1380 case T_OBJECT: { | |
| 1381 Register tmp = O7; | |
| 1382 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1383 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1384 __ ld_ptr(from.base(), from.disp(), tmp); | |
| 1385 __ st_ptr(tmp, to.base(), to.disp()); | |
| 1386 break; | |
| 1387 } | |
| 1388 case T_LONG: | |
| 1389 case T_DOUBLE: { | |
| 1390 Register tmp = O7; | |
| 1391 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
| 1392 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
| 1393 __ lduw(from.base(), from.disp(), tmp); | |
| 1394 __ stw(tmp, to.base(), to.disp()); | |
| 1395 __ lduw(from.base(), from.disp() + 4, tmp); | |
| 1396 __ stw(tmp, to.base(), to.disp() + 4); | |
| 1397 break; | |
| 1398 } | |
| 1399 | |
| 1400 default: | |
| 1401 ShouldNotReachHere(); | |
| 1402 } | |
| 1403 } | |
| 1404 | |
| 1405 | |
| 1406 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 1407 Address base = as_Address(addr); | |
| 727 | 1408 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); |
| 0 | 1409 } |
| 1410 | |
| 1411 | |
| 1412 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 1413 Address base = as_Address(addr); | |
| 727 | 1414 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); |
| 0 | 1415 } |
| 1416 | |
| 1417 | |
| 1418 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, | |
| 1419 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { | |
| 1420 | |
| 1421 LIR_Address* addr = src_opr->as_address_ptr(); | |
| 1422 LIR_Opr to_reg = dest; | |
| 1423 | |
| 1424 Register src = addr->base()->as_pointer_register(); | |
| 1425 Register disp_reg = noreg; | |
| 1426 int disp_value = addr->disp(); | |
| 1427 bool needs_patching = (patch_code != lir_patch_none); | |
| 1428 | |
| 1429 if (addr->base()->type() == T_OBJECT) { | |
| 1430 __ verify_oop(src); | |
| 1431 } | |
| 1432 | |
| 1433 PatchingStub* patch = NULL; | |
| 1434 if (needs_patching) { | |
| 1435 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1436 assert(!to_reg->is_double_cpu() || | |
| 1437 patch_code == lir_patch_none || | |
| 1438 patch_code == lir_patch_normal, "patching doesn't match register"); | |
| 1439 } | |
| 1440 | |
| 1441 if (addr->index()->is_illegal()) { | |
| 1442 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
| 1443 if (needs_patching) { | |
| 727 | 1444 __ patchable_set(0, O7); |
| 0 | 1445 } else { |
| 1446 __ set(disp_value, O7); | |
| 1447 } | |
| 1448 disp_reg = O7; | |
| 1449 } | |
| 1450 } else if (unaligned || PatchALot) { | |
| 1451 __ add(src, addr->index()->as_register(), O7); | |
| 1452 src = O7; | |
| 1453 } else { | |
| 1454 disp_reg = addr->index()->as_pointer_register(); | |
| 1455 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
| 1456 } | |
| 1457 | |
| 1458 // remember the offset of the load. The patching_epilog must be done | |
| 1459 // before the call to add_debug_info, otherwise the PcDescs don't get | |
| 1460 // entered in increasing order. | |
| 1461 int offset = code_offset(); | |
| 1462 | |
| 1463 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
| 1464 if (disp_reg == noreg) { | |
| 1465 offset = load(src, disp_value, to_reg, type, unaligned); | |
| 1466 } else { | |
| 1467 assert(!unaligned, "can't handle this"); | |
| 1468 offset = load(src, disp_reg, to_reg, type); | |
| 1469 } | |
| 1470 | |
| 1471 if (patch != NULL) { | |
| 1472 patching_epilog(patch, patch_code, src, info); | |
| 1473 } | |
| 1474 | |
| 1475 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
| 1476 } | |
| 1477 | |
| 1478 | |
| 1479 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1480 LIR_Address* addr = src->as_address_ptr(); | |
| 1481 Address from_addr = as_Address(addr); | |
| 1482 | |
| 1483 if (VM_Version::has_v9()) { | |
| 1484 __ prefetch(from_addr, Assembler::severalReads); | |
| 1485 } | |
| 1486 } | |
| 1487 | |
| 1488 | |
| 1489 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1490 LIR_Address* addr = src->as_address_ptr(); | |
| 1491 Address from_addr = as_Address(addr); | |
| 1492 | |
| 1493 if (VM_Version::has_v9()) { | |
| 1494 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); | |
| 1495 } | |
| 1496 } | |
| 1497 | |
| 1498 | |
| 1499 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1500 Address addr; | |
| 1501 if (src->is_single_word()) { | |
| 1502 addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1503 } else if (src->is_double_word()) { | |
| 1504 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
| 1505 } | |
| 1506 | |
| 1507 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
| 1508 load(addr.base(), addr.disp(), dest, dest->type(), unaligned); | |
| 1509 } | |
| 1510 | |
| 1511 | |
| 1512 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 1513 Address addr; | |
| 1514 if (dest->is_single_word()) { | |
| 1515 addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1516 } else if (dest->is_double_word()) { | |
| 1517 addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 1518 } | |
| 1519 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
| 1520 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); | |
| 1521 } | |
| 1522 | |
| 1523 | |
| 1524 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { | |
| 1525 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { | |
| 1526 if (from_reg->is_double_fpu()) { | |
| 1527 // double to double moves | |
| 1528 assert(to_reg->is_double_fpu(), "should match"); | |
| 1529 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); | |
| 1530 } else { | |
| 1531 // float to float moves | |
| 1532 assert(to_reg->is_single_fpu(), "should match"); | |
| 1533 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); | |
| 1534 } | |
| 1535 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { | |
| 1536 if (from_reg->is_double_cpu()) { | |
| 1537 #ifdef _LP64 | |
| 1538 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); | |
| 1539 #else | |
| 1540 assert(to_reg->is_double_cpu() && | |
| 1541 from_reg->as_register_hi() != to_reg->as_register_lo() && | |
| 1542 from_reg->as_register_lo() != to_reg->as_register_hi(), | |
| 1543 "should both be long and not overlap"); | |
| 1544 // long to long moves | |
| 1545 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); | |
| 1546 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); | |
| 1547 #endif | |
| 1548 #ifdef _LP64 | |
| 1549 } else if (to_reg->is_double_cpu()) { | |
| 1550 // int to int moves | |
| 1551 __ mov(from_reg->as_register(), to_reg->as_register_lo()); | |
| 1552 #endif | |
| 1553 } else { | |
| 1554 // int to int moves | |
| 1555 __ mov(from_reg->as_register(), to_reg->as_register()); | |
| 1556 } | |
| 1557 } else { | |
| 1558 ShouldNotReachHere(); | |
| 1559 } | |
| 1560 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { | |
| 1561 __ verify_oop(to_reg->as_register()); | |
| 1562 } | |
| 1563 } | |
| 1564 | |
| 1565 | |
| 1566 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, | |
| 1567 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, | |
| 1568 bool unaligned) { | |
| 1569 LIR_Address* addr = dest->as_address_ptr(); | |
| 1570 | |
| 1571 Register src = addr->base()->as_pointer_register(); | |
| 1572 Register disp_reg = noreg; | |
| 1573 int disp_value = addr->disp(); | |
| 1574 bool needs_patching = (patch_code != lir_patch_none); | |
| 1575 | |
| 1576 if (addr->base()->is_oop_register()) { | |
| 1577 __ verify_oop(src); | |
| 1578 } | |
| 1579 | |
| 1580 PatchingStub* patch = NULL; | |
| 1581 if (needs_patching) { | |
| 1582 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1583 assert(!from_reg->is_double_cpu() || | |
| 1584 patch_code == lir_patch_none || | |
| 1585 patch_code == lir_patch_normal, "patching doesn't match register"); | |
| 1586 } | |
| 1587 | |
| 1588 if (addr->index()->is_illegal()) { | |
| 1589 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
| 1590 if (needs_patching) { | |
| 727 | 1591 __ patchable_set(0, O7); |
| 0 | 1592 } else { |
| 1593 __ set(disp_value, O7); | |
| 1594 } | |
| 1595 disp_reg = O7; | |
| 1596 } | |
| 1597 } else if (unaligned || PatchALot) { | |
| 1598 __ add(src, addr->index()->as_register(), O7); | |
| 1599 src = O7; | |
| 1600 } else { | |
| 1601 disp_reg = addr->index()->as_pointer_register(); | |
| 1602 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
| 1603 } | |
| 1604 | |
| 1605 // remember the offset of the store. The patching_epilog must be done | |
| 1606 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get | |
| 1607 // entered in increasing order. | |
| 1608 int offset; | |
| 1609 | |
| 1610 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
| 1611 if (disp_reg == noreg) { | |
| 1612 offset = store(from_reg, src, disp_value, type, unaligned); | |
| 1613 } else { | |
| 1614 assert(!unaligned, "can't handle this"); | |
| 1615 offset = store(from_reg, src, disp_reg, type); | |
| 1616 } | |
| 1617 | |
| 1618 if (patch != NULL) { | |
| 1619 patching_epilog(patch, patch_code, src, info); | |
| 1620 } | |
| 1621 | |
| 1622 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
| 1623 } | |
| 1624 | |
| 1625 | |
| 1626 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 1627 // the poll may need a register so just pick one that isn't the return register | |
| 1783 | 1628 #if defined(TIERED) && !defined(_LP64) |
| 0 | 1629 if (result->type_field() == LIR_OprDesc::long_type) { |
| 1630 // Must move the result to G1 | |
| 1631 // Must leave proper result in O0,O1 and G1 (TIERED only) | |
| 1632 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
| 1633 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
| 1634 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
| 1783 | 1635 #ifdef ASSERT |
| 1636 // mangle it so any problems will show up | |
| 1637 __ set(0xdeadbeef, I0); | |
| 1638 __ set(0xdeadbeef, I1); | |
| 1639 #endif | |
| 0 | 1640 } |
| 1641 #endif // TIERED | |
| 1642 __ set((intptr_t)os::get_polling_page(), L0); | |
| 1643 __ relocate(relocInfo::poll_return_type); | |
| 1644 __ ld_ptr(L0, 0, G0); | |
| 1645 __ ret(); | |
| 1646 __ delayed()->restore(); | |
| 1647 } | |
| 1648 | |
| 1649 | |
| 1650 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1651 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); | |
| 1652 if (info != NULL) { | |
| 1653 add_debug_info_for_branch(info); | |
| 1654 } else { | |
| 1655 __ relocate(relocInfo::poll_type); | |
| 1656 } | |
| 1657 | |
| 1658 int offset = __ offset(); | |
| 1659 __ ld_ptr(tmp->as_register(), 0, G0); | |
| 1660 | |
| 1661 return offset; | |
| 1662 } | |
| 1663 | |
| 1664 | |
| 1665 void LIR_Assembler::emit_static_call_stub() { | |
| 1666 address call_pc = __ pc(); | |
| 1667 address stub = __ start_a_stub(call_stub_size); | |
| 1668 if (stub == NULL) { | |
| 1669 bailout("static call stub overflow"); | |
| 1670 return; | |
| 1671 } | |
| 1672 | |
| 1673 int start = __ offset(); | |
| 1674 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 1675 | |
| 1676 __ set_oop(NULL, G5); | |
| 1677 // must be set to -1 at code generation time | |
| 727 | 1678 AddressLiteral addrlit(-1); |
| 1679 __ jump_to(addrlit, G3); | |
| 0 | 1680 __ delayed()->nop(); |
| 1681 | |
| 1682 assert(__ offset() - start <= call_stub_size, "stub too big"); | |
| 1683 __ end_a_stub(); | |
| 1684 } | |
| 1685 | |
| 1686 | |
| 1687 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 1688 if (opr1->is_single_fpu()) { | |
| 1689 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); | |
| 1690 } else if (opr1->is_double_fpu()) { | |
| 1691 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); | |
| 1692 } else if (opr1->is_single_cpu()) { | |
| 1693 if (opr2->is_constant()) { | |
| 1694 switch (opr2->as_constant_ptr()->type()) { | |
| 1695 case T_INT: | |
| 1696 { jint con = opr2->as_constant_ptr()->as_jint(); | |
| 1697 if (Assembler::is_simm13(con)) { | |
| 1698 __ cmp(opr1->as_register(), con); | |
| 1699 } else { | |
| 1700 __ set(con, O7); | |
| 1701 __ cmp(opr1->as_register(), O7); | |
| 1702 } | |
| 1703 } | |
| 1704 break; | |
| 1705 | |
| 1706 case T_OBJECT: | |
| 1707 // there are only equal/notequal comparisions on objects | |
| 1708 { jobject con = opr2->as_constant_ptr()->as_jobject(); | |
| 1709 if (con == NULL) { | |
| 1710 __ cmp(opr1->as_register(), 0); | |
| 1711 } else { | |
| 1712 jobject2reg(con, O7); | |
| 1713 __ cmp(opr1->as_register(), O7); | |
| 1714 } | |
| 1715 } | |
| 1716 break; | |
| 1717 | |
| 1718 default: | |
| 1719 ShouldNotReachHere(); | |
| 1720 break; | |
| 1721 } | |
| 1722 } else { | |
| 1723 if (opr2->is_address()) { | |
| 1724 LIR_Address * addr = opr2->as_address_ptr(); | |
| 1725 BasicType type = addr->type(); | |
| 1726 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
| 1727 else __ ld(as_Address(addr), O7); | |
| 1728 __ cmp(opr1->as_register(), O7); | |
| 1729 } else { | |
| 1730 __ cmp(opr1->as_register(), opr2->as_register()); | |
| 1731 } | |
| 1732 } | |
| 1733 } else if (opr1->is_double_cpu()) { | |
| 1734 Register xlo = opr1->as_register_lo(); | |
| 1735 Register xhi = opr1->as_register_hi(); | |
| 1736 if (opr2->is_constant() && opr2->as_jlong() == 0) { | |
| 1737 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); | |
| 1738 #ifdef _LP64 | |
| 1739 __ orcc(xhi, G0, G0); | |
| 1740 #else | |
| 1741 __ orcc(xhi, xlo, G0); | |
| 1742 #endif | |
| 1743 } else if (opr2->is_register()) { | |
| 1744 Register ylo = opr2->as_register_lo(); | |
| 1745 Register yhi = opr2->as_register_hi(); | |
| 1746 #ifdef _LP64 | |
| 1747 __ cmp(xlo, ylo); | |
| 1748 #else | |
| 1749 __ subcc(xlo, ylo, xlo); | |
| 1750 __ subccc(xhi, yhi, xhi); | |
| 1751 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 1752 __ orcc(xhi, xlo, G0); | |
| 1753 } | |
| 1754 #endif | |
| 1755 } else { | |
| 1756 ShouldNotReachHere(); | |
| 1757 } | |
| 1758 } else if (opr1->is_address()) { | |
| 1759 LIR_Address * addr = opr1->as_address_ptr(); | |
| 1760 BasicType type = addr->type(); | |
| 1761 assert (opr2->is_constant(), "Checking"); | |
| 1762 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
| 1763 else __ ld(as_Address(addr), O7); | |
| 1764 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); | |
| 1765 } else { | |
| 1766 ShouldNotReachHere(); | |
| 1767 } | |
| 1768 } | |
| 1769 | |
| 1770 | |
| 1771 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ | |
| 1772 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 1773 bool is_unordered_less = (code == lir_ucmp_fd2i); | |
| 1774 if (left->is_single_fpu()) { | |
| 1775 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); | |
| 1776 } else if (left->is_double_fpu()) { | |
| 1777 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); | |
| 1778 } else { | |
| 1779 ShouldNotReachHere(); | |
| 1780 } | |
| 1781 } else if (code == lir_cmp_l2i) { | |
| 1369 | 1782 #ifdef _LP64 |
| 1783 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); | |
| 1784 #else | |
| 0 | 1785 __ lcmp(left->as_register_hi(), left->as_register_lo(), |
| 1786 right->as_register_hi(), right->as_register_lo(), | |
| 1787 dst->as_register()); | |
| 1369 | 1788 #endif |
| 0 | 1789 } else { |
| 1790 ShouldNotReachHere(); | |
| 1791 } | |
| 1792 } | |
| 1793 | |
| 1794 | |
| 1795 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { | |
| 1796 | |
| 1797 Assembler::Condition acond; | |
| 1798 switch (condition) { | |
| 1799 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1800 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1801 case lir_cond_less: acond = Assembler::less; break; | |
| 1802 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1803 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
| 1804 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1805 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
| 1806 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
| 1807 default: ShouldNotReachHere(); | |
| 1808 }; | |
| 1809 | |
| 1810 if (opr1->is_constant() && opr1->type() == T_INT) { | |
| 1811 Register dest = result->as_register(); | |
| 1812 // load up first part of constant before branch | |
| 1813 // and do the rest in the delay slot. | |
| 1814 if (!Assembler::is_simm13(opr1->as_jint())) { | |
| 1815 __ sethi(opr1->as_jint(), dest); | |
| 1816 } | |
| 1817 } else if (opr1->is_constant()) { | |
| 1818 const2reg(opr1, result, lir_patch_none, NULL); | |
| 1819 } else if (opr1->is_register()) { | |
| 1820 reg2reg(opr1, result); | |
| 1821 } else if (opr1->is_stack()) { | |
| 1822 stack2reg(opr1, result, result->type()); | |
| 1823 } else { | |
| 1824 ShouldNotReachHere(); | |
| 1825 } | |
| 1826 Label skip; | |
| 1827 __ br(acond, false, Assembler::pt, skip); | |
| 1828 if (opr1->is_constant() && opr1->type() == T_INT) { | |
| 1829 Register dest = result->as_register(); | |
| 1830 if (Assembler::is_simm13(opr1->as_jint())) { | |
| 1831 __ delayed()->or3(G0, opr1->as_jint(), dest); | |
| 1832 } else { | |
| 1833 // the sethi has been done above, so just put in the low 10 bits | |
| 1834 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); | |
| 1835 } | |
| 1836 } else { | |
| 1837 // can't do anything useful in the delay slot | |
| 1838 __ delayed()->nop(); | |
| 1839 } | |
| 1840 if (opr2->is_constant()) { | |
| 1841 const2reg(opr2, result, lir_patch_none, NULL); | |
| 1842 } else if (opr2->is_register()) { | |
| 1843 reg2reg(opr2, result); | |
| 1844 } else if (opr2->is_stack()) { | |
| 1845 stack2reg(opr2, result, result->type()); | |
| 1846 } else { | |
| 1847 ShouldNotReachHere(); | |
| 1848 } | |
| 1849 __ bind(skip); | |
| 1850 } | |
| 1851 | |
| 1852 | |
| 1853 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 1854 assert(info == NULL, "unused on this code path"); | |
| 1855 assert(left->is_register(), "wrong items state"); | |
| 1856 assert(dest->is_register(), "wrong items state"); | |
| 1857 | |
| 1858 if (right->is_register()) { | |
| 1859 if (dest->is_float_kind()) { | |
| 1860 | |
| 1861 FloatRegister lreg, rreg, res; | |
| 1862 FloatRegisterImpl::Width w; | |
| 1863 if (right->is_single_fpu()) { | |
| 1864 w = FloatRegisterImpl::S; | |
| 1865 lreg = left->as_float_reg(); | |
| 1866 rreg = right->as_float_reg(); | |
| 1867 res = dest->as_float_reg(); | |
| 1868 } else { | |
| 1869 w = FloatRegisterImpl::D; | |
| 1870 lreg = left->as_double_reg(); | |
| 1871 rreg = right->as_double_reg(); | |
| 1872 res = dest->as_double_reg(); | |
| 1873 } | |
| 1874 | |
| 1875 switch (code) { | |
| 1876 case lir_add: __ fadd(w, lreg, rreg, res); break; | |
| 1877 case lir_sub: __ fsub(w, lreg, rreg, res); break; | |
| 1878 case lir_mul: // fall through | |
| 1879 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; | |
| 1880 case lir_div: // fall through | |
| 1881 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; | |
| 1882 default: ShouldNotReachHere(); | |
| 1883 } | |
| 1884 | |
| 1885 } else if (dest->is_double_cpu()) { | |
| 1886 #ifdef _LP64 | |
| 1887 Register dst_lo = dest->as_register_lo(); | |
| 1888 Register op1_lo = left->as_pointer_register(); | |
| 1889 Register op2_lo = right->as_pointer_register(); | |
| 1890 | |
| 1891 switch (code) { | |
| 1892 case lir_add: | |
| 1893 __ add(op1_lo, op2_lo, dst_lo); | |
| 1894 break; | |
| 1895 | |
| 1896 case lir_sub: | |
| 1897 __ sub(op1_lo, op2_lo, dst_lo); | |
| 1898 break; | |
| 1899 | |
| 1900 default: ShouldNotReachHere(); | |
| 1901 } | |
| 1902 #else | |
| 1903 Register op1_lo = left->as_register_lo(); | |
| 1904 Register op1_hi = left->as_register_hi(); | |
| 1905 Register op2_lo = right->as_register_lo(); | |
| 1906 Register op2_hi = right->as_register_hi(); | |
| 1907 Register dst_lo = dest->as_register_lo(); | |
| 1908 Register dst_hi = dest->as_register_hi(); | |
| 1909 | |
| 1910 switch (code) { | |
| 1911 case lir_add: | |
| 1912 __ addcc(op1_lo, op2_lo, dst_lo); | |
| 1913 __ addc (op1_hi, op2_hi, dst_hi); | |
| 1914 break; | |
| 1915 | |
| 1916 case lir_sub: | |
| 1917 __ subcc(op1_lo, op2_lo, dst_lo); | |
| 1918 __ subc (op1_hi, op2_hi, dst_hi); | |
| 1919 break; | |
| 1920 | |
| 1921 default: ShouldNotReachHere(); | |
| 1922 } | |
| 1923 #endif | |
| 1924 } else { | |
| 1925 assert (right->is_single_cpu(), "Just Checking"); | |
| 1926 | |
| 1927 Register lreg = left->as_register(); | |
| 1928 Register res = dest->as_register(); | |
| 1929 Register rreg = right->as_register(); | |
| 1930 switch (code) { | |
| 1931 case lir_add: __ add (lreg, rreg, res); break; | |
| 1932 case lir_sub: __ sub (lreg, rreg, res); break; | |
| 1933 case lir_mul: __ mult (lreg, rreg, res); break; | |
| 1934 default: ShouldNotReachHere(); | |
| 1935 } | |
| 1936 } | |
| 1937 } else { | |
| 1938 assert (right->is_constant(), "must be constant"); | |
| 1939 | |
| 1940 if (dest->is_single_cpu()) { | |
| 1941 Register lreg = left->as_register(); | |
| 1942 Register res = dest->as_register(); | |
| 1943 int simm13 = right->as_constant_ptr()->as_jint(); | |
| 1944 | |
| 1945 switch (code) { | |
| 1946 case lir_add: __ add (lreg, simm13, res); break; | |
| 1947 case lir_sub: __ sub (lreg, simm13, res); break; | |
| 1948 case lir_mul: __ mult (lreg, simm13, res); break; | |
| 1949 default: ShouldNotReachHere(); | |
| 1950 } | |
| 1951 } else { | |
| 1952 Register lreg = left->as_pointer_register(); | |
| 1953 Register res = dest->as_register_lo(); | |
| 1954 long con = right->as_constant_ptr()->as_jlong(); | |
| 1955 assert(Assembler::is_simm13(con), "must be simm13"); | |
| 1956 | |
| 1957 switch (code) { | |
| 1958 case lir_add: __ add (lreg, (int)con, res); break; | |
| 1959 case lir_sub: __ sub (lreg, (int)con, res); break; | |
| 1960 case lir_mul: __ mult (lreg, (int)con, res); break; | |
| 1961 default: ShouldNotReachHere(); | |
| 1962 } | |
| 1963 } | |
| 1964 } | |
| 1965 } | |
| 1966 | |
| 1967 | |
| 1968 void LIR_Assembler::fpop() { | |
| 1969 // do nothing | |
| 1970 } | |
| 1971 | |
| 1972 | |
| 1973 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { | |
| 1974 switch (code) { | |
| 1975 case lir_sin: | |
| 1976 case lir_tan: | |
| 1977 case lir_cos: { | |
| 1978 assert(thread->is_valid(), "preserve the thread object for performance reasons"); | |
| 1979 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); | |
| 1980 break; | |
| 1981 } | |
| 1982 case lir_sqrt: { | |
| 1983 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); | |
| 1984 FloatRegister src_reg = value->as_double_reg(); | |
| 1985 FloatRegister dst_reg = dest->as_double_reg(); | |
| 1986 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); | |
| 1987 break; | |
| 1988 } | |
| 1989 case lir_abs: { | |
| 1990 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); | |
| 1991 FloatRegister src_reg = value->as_double_reg(); | |
| 1992 FloatRegister dst_reg = dest->as_double_reg(); | |
| 1993 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); | |
| 1994 break; | |
| 1995 } | |
| 1996 default: { | |
| 1997 ShouldNotReachHere(); | |
| 1998 break; | |
| 1999 } | |
| 2000 } | |
| 2001 } | |
| 2002 | |
| 2003 | |
| 2004 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { | |
| 2005 if (right->is_constant()) { | |
| 2006 if (dest->is_single_cpu()) { | |
| 2007 int simm13 = right->as_constant_ptr()->as_jint(); | |
| 2008 switch (code) { | |
| 2009 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; | |
| 2010 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; | |
| 2011 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; | |
| 2012 default: ShouldNotReachHere(); | |
| 2013 } | |
| 2014 } else { | |
| 2015 long c = right->as_constant_ptr()->as_jlong(); | |
| 2016 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); | |
| 2017 int simm13 = (int)c; | |
| 2018 switch (code) { | |
| 2019 case lir_logic_and: | |
| 2020 #ifndef _LP64 | |
| 2021 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 2022 #endif | |
| 2023 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 2024 break; | |
| 2025 | |
| 2026 case lir_logic_or: | |
| 2027 #ifndef _LP64 | |
| 2028 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 2029 #endif | |
| 2030 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 2031 break; | |
| 2032 | |
| 2033 case lir_logic_xor: | |
| 2034 #ifndef _LP64 | |
| 2035 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 2036 #endif | |
| 2037 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 2038 break; | |
| 2039 | |
| 2040 default: ShouldNotReachHere(); | |
| 2041 } | |
| 2042 } | |
| 2043 } else { | |
| 2044 assert(right->is_register(), "right should be in register"); | |
| 2045 | |
| 2046 if (dest->is_single_cpu()) { | |
| 2047 switch (code) { | |
| 2048 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 2049 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 2050 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 2051 default: ShouldNotReachHere(); | |
| 2052 } | |
| 2053 } else { | |
| 2054 #ifdef _LP64 | |
| 2055 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : | |
| 2056 left->as_register_lo(); | |
| 2057 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : | |
| 2058 right->as_register_lo(); | |
| 2059 | |
| 2060 switch (code) { | |
| 2061 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; | |
| 2062 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; | |
| 2063 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; | |
| 2064 default: ShouldNotReachHere(); | |
| 2065 } | |
| 2066 #else | |
| 2067 switch (code) { | |
| 2068 case lir_logic_and: | |
| 2069 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2070 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2071 break; | |
| 2072 | |
| 2073 case lir_logic_or: | |
| 2074 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2075 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2076 break; | |
| 2077 | |
| 2078 case lir_logic_xor: | |
| 2079 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2080 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2081 break; | |
| 2082 | |
| 2083 default: ShouldNotReachHere(); | |
| 2084 } | |
| 2085 #endif | |
| 2086 } | |
| 2087 } | |
| 2088 } | |
| 2089 | |
| 2090 | |
| 2091 int LIR_Assembler::shift_amount(BasicType t) { | |
|
29
d5fc211aea19
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
0
diff
changeset
|
2092 int elem_size = type2aelembytes(t); |
| 0 | 2093 switch (elem_size) { |
| 2094 case 1 : return 0; | |
| 2095 case 2 : return 1; | |
| 2096 case 4 : return 2; | |
| 2097 case 8 : return 3; | |
| 2098 } | |
| 2099 ShouldNotReachHere(); | |
| 2100 return -1; | |
| 2101 } | |
| 2102 | |
| 2103 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2104 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
| 0 | 2105 assert(exceptionOop->as_register() == Oexception, "should match"); |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2106 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); |
| 0 | 2107 |
| 2108 info->add_register_oop(exceptionOop); | |
| 2109 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2110 // reuse the debug info from the safepoint poll for the throw op itself |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2111 address pc_for_athrow = __ pc(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2112 int pc_for_athrow_offset = __ offset(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2113 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2114 __ set(pc_for_athrow, Oissuing_pc, rspec); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2115 add_call_info(pc_for_athrow_offset, info); // for exception handler |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2116 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2117 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2118 __ delayed()->nop(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2119 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2120 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2121 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2122 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2123 assert(exceptionOop->as_register() == Oexception, "should match"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2124 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2125 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2126 __ delayed()->nop(); |
| 0 | 2127 } |
| 2128 | |
| 2129 | |
| 2130 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 2131 Register src = op->src()->as_register(); | |
| 2132 Register dst = op->dst()->as_register(); | |
| 2133 Register src_pos = op->src_pos()->as_register(); | |
| 2134 Register dst_pos = op->dst_pos()->as_register(); | |
| 2135 Register length = op->length()->as_register(); | |
| 2136 Register tmp = op->tmp()->as_register(); | |
| 2137 Register tmp2 = O7; | |
| 2138 | |
| 2139 int flags = op->flags(); | |
| 2140 ciArrayKlass* default_type = op->expected_type(); | |
| 2141 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 2142 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 2143 | |
| 2144 // set up the arraycopy stub information | |
| 2145 ArrayCopyStub* stub = op->stub(); | |
| 2146 | |
| 2147 // always do stub if no type information is available. it's ok if | |
| 2148 // the known type isn't loaded since the code sanity checks | |
| 2149 // in debug mode and the type isn't required when we know the exact type | |
| 2150 // also check that the type is an array type. | |
|
342
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
29
diff
changeset
|
2151 // We also, for now, always call the stub if the barrier set requires a |
|
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
29
diff
changeset
|
2152 // write_ref_pre barrier (which the stub does, but none of the optimized |
|
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
29
diff
changeset
|
2153 // cases currently does). |
|
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
29
diff
changeset
|
2154 if (op->expected_type() == NULL || |
|
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
29
diff
changeset
|
2155 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) { |
| 0 | 2156 __ mov(src, O0); |
| 2157 __ mov(src_pos, O1); | |
| 2158 __ mov(dst, O2); | |
| 2159 __ mov(dst_pos, O3); | |
| 2160 __ mov(length, O4); | |
| 2161 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); | |
| 2162 | |
| 2163 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); | |
| 2164 __ delayed()->nop(); | |
| 2165 __ bind(*stub->continuation()); | |
| 2166 return; | |
| 2167 } | |
| 2168 | |
| 2169 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); | |
| 2170 | |
| 2171 // make sure src and dst are non-null and load array length | |
| 2172 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 2173 __ tst(src); | |
| 2174 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2175 __ delayed()->nop(); | |
| 2176 } | |
| 2177 | |
| 2178 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 2179 __ tst(dst); | |
| 2180 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2181 __ delayed()->nop(); | |
| 2182 } | |
| 2183 | |
| 2184 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 2185 // test src_pos register | |
| 2186 __ tst(src_pos); | |
| 2187 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2188 __ delayed()->nop(); | |
| 2189 } | |
| 2190 | |
| 2191 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 2192 // test dst_pos register | |
| 2193 __ tst(dst_pos); | |
| 2194 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2195 __ delayed()->nop(); | |
| 2196 } | |
| 2197 | |
| 2198 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
| 2199 // make sure length isn't negative | |
| 2200 __ tst(length); | |
| 2201 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2202 __ delayed()->nop(); | |
| 2203 } | |
| 2204 | |
| 2205 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 2206 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
| 2207 __ add(length, src_pos, tmp); | |
| 2208 __ cmp(tmp2, tmp); | |
| 2209 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
| 2210 __ delayed()->nop(); | |
| 2211 } | |
| 2212 | |
| 2213 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 2214 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
| 2215 __ add(length, dst_pos, tmp); | |
| 2216 __ cmp(tmp2, tmp); | |
| 2217 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
| 2218 __ delayed()->nop(); | |
| 2219 } | |
| 2220 | |
| 2221 if (flags & LIR_OpArrayCopy::type_check) { | |
| 2222 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); | |
| 2223 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
| 2224 __ cmp(tmp, tmp2); | |
| 2225 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
| 2226 __ delayed()->nop(); | |
| 2227 } | |
| 2228 | |
| 2229 #ifdef ASSERT | |
| 2230 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 2231 // Sanity check the known type with the incoming class. For the | |
| 2232 // primitive case the types must match exactly with src.klass and | |
| 2233 // dst.klass each exactly matching the default type. For the | |
| 2234 // object array case, if no type check is needed then either the | |
| 2235 // dst type is exactly the expected type and the src type is a | |
| 2236 // subtype which we can't check or src is the same array as dst | |
| 2237 // but not necessarily exactly of type default_type. | |
| 2238 Label known_ok, halt; | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
2239 jobject2reg(op->expected_type()->constant_encoding(), tmp); |
| 0 | 2240 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
| 2241 if (basic_type != T_OBJECT) { | |
| 2242 __ cmp(tmp, tmp2); | |
| 2243 __ br(Assembler::notEqual, false, Assembler::pn, halt); | |
| 2244 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
| 2245 __ cmp(tmp, tmp2); | |
| 2246 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2247 __ delayed()->nop(); | |
| 2248 } else { | |
| 2249 __ cmp(tmp, tmp2); | |
| 2250 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2251 __ delayed()->cmp(src, dst); | |
| 2252 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2253 __ delayed()->nop(); | |
| 2254 } | |
| 2255 __ bind(halt); | |
| 2256 __ stop("incorrect type information in arraycopy"); | |
| 2257 __ bind(known_ok); | |
| 2258 } | |
| 2259 #endif | |
| 2260 | |
| 2261 int shift = shift_amount(basic_type); | |
| 2262 | |
| 2263 Register src_ptr = O0; | |
| 2264 Register dst_ptr = O1; | |
| 2265 Register len = O2; | |
| 2266 | |
| 2267 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
| 1060 | 2268 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null |
| 0 | 2269 if (shift == 0) { |
| 2270 __ add(src_ptr, src_pos, src_ptr); | |
| 2271 } else { | |
| 2272 __ sll(src_pos, shift, tmp); | |
| 2273 __ add(src_ptr, tmp, src_ptr); | |
| 2274 } | |
| 2275 | |
| 2276 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
| 1060 | 2277 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null |
| 0 | 2278 if (shift == 0) { |
| 2279 __ add(dst_ptr, dst_pos, dst_ptr); | |
| 2280 } else { | |
| 2281 __ sll(dst_pos, shift, tmp); | |
| 2282 __ add(dst_ptr, tmp, dst_ptr); | |
| 2283 } | |
| 2284 | |
| 2285 if (basic_type != T_OBJECT) { | |
| 2286 if (shift == 0) { | |
| 2287 __ mov(length, len); | |
| 2288 } else { | |
| 2289 __ sll(length, shift, len); | |
| 2290 } | |
| 2291 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); | |
| 2292 } else { | |
| 2293 // oop_arraycopy takes a length in number of elements, so don't scale it. | |
| 2294 __ mov(length, len); | |
| 2295 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); | |
| 2296 } | |
| 2297 | |
| 2298 __ bind(*stub->continuation()); | |
| 2299 } | |
| 2300 | |
| 2301 | |
| 2302 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
| 2303 if (dest->is_single_cpu()) { | |
| 2304 #ifdef _LP64 | |
| 2305 if (left->type() == T_OBJECT) { | |
| 2306 switch (code) { | |
| 2307 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2308 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2309 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2310 default: ShouldNotReachHere(); | |
| 2311 } | |
| 2312 } else | |
| 2313 #endif | |
| 2314 switch (code) { | |
| 2315 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2316 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2317 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2318 default: ShouldNotReachHere(); | |
| 2319 } | |
| 2320 } else { | |
| 2321 #ifdef _LP64 | |
| 2322 switch (code) { | |
| 2323 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2324 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2325 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2326 default: ShouldNotReachHere(); | |
| 2327 } | |
| 2328 #else | |
| 2329 switch (code) { | |
| 2330 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2331 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2332 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2333 default: ShouldNotReachHere(); | |
| 2334 } | |
| 2335 #endif | |
| 2336 } | |
| 2337 } | |
| 2338 | |
| 2339 | |
| 2340 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 2341 #ifdef _LP64 | |
| 2342 if (left->type() == T_OBJECT) { | |
| 2343 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) | |
| 2344 Register l = left->as_register(); | |
| 2345 Register d = dest->as_register_lo(); | |
| 2346 switch (code) { | |
| 2347 case lir_shl: __ sllx (l, count, d); break; | |
| 2348 case lir_shr: __ srax (l, count, d); break; | |
| 2349 case lir_ushr: __ srlx (l, count, d); break; | |
| 2350 default: ShouldNotReachHere(); | |
| 2351 } | |
| 2352 return; | |
| 2353 } | |
| 2354 #endif | |
| 2355 | |
| 2356 if (dest->is_single_cpu()) { | |
| 2357 count = count & 0x1F; // Java spec | |
| 2358 switch (code) { | |
| 2359 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; | |
| 2360 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; | |
| 2361 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; | |
| 2362 default: ShouldNotReachHere(); | |
| 2363 } | |
| 2364 } else if (dest->is_double_cpu()) { | |
| 2365 count = count & 63; // Java spec | |
| 2366 switch (code) { | |
| 2367 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2368 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2369 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2370 default: ShouldNotReachHere(); | |
| 2371 } | |
| 2372 } else { | |
| 2373 ShouldNotReachHere(); | |
| 2374 } | |
| 2375 } | |
| 2376 | |
| 2377 | |
| 2378 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 2379 assert(op->tmp1()->as_register() == G1 && | |
| 2380 op->tmp2()->as_register() == G3 && | |
| 2381 op->tmp3()->as_register() == G4 && | |
| 2382 op->obj()->as_register() == O0 && | |
| 2383 op->klass()->as_register() == G5, "must be"); | |
| 2384 if (op->init_check()) { | |
| 2385 __ ld(op->klass()->as_register(), | |
| 2386 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), | |
| 2387 op->tmp1()->as_register()); | |
| 2388 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 2389 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); | |
| 2390 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); | |
| 2391 __ delayed()->nop(); | |
| 2392 } | |
| 2393 __ allocate_object(op->obj()->as_register(), | |
| 2394 op->tmp1()->as_register(), | |
| 2395 op->tmp2()->as_register(), | |
| 2396 op->tmp3()->as_register(), | |
| 2397 op->header_size(), | |
| 2398 op->object_size(), | |
| 2399 op->klass()->as_register(), | |
| 2400 *op->stub()->entry()); | |
| 2401 __ bind(*op->stub()->continuation()); | |
| 2402 __ verify_oop(op->obj()->as_register()); | |
| 2403 } | |
| 2404 | |
| 2405 | |
| 2406 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
| 2407 assert(op->tmp1()->as_register() == G1 && | |
| 2408 op->tmp2()->as_register() == G3 && | |
| 2409 op->tmp3()->as_register() == G4 && | |
| 2410 op->tmp4()->as_register() == O1 && | |
| 2411 op->klass()->as_register() == G5, "must be"); | |
| 2412 if (UseSlowPath || | |
| 2413 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 2414 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2415 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
| 0 | 2416 __ delayed()->nop(); |
| 2417 } else { | |
| 2418 __ allocate_array(op->obj()->as_register(), | |
| 2419 op->len()->as_register(), | |
| 2420 op->tmp1()->as_register(), | |
| 2421 op->tmp2()->as_register(), | |
| 2422 op->tmp3()->as_register(), | |
| 2423 arrayOopDesc::header_size(op->type()), | |
|
29
d5fc211aea19
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
0
diff
changeset
|
2424 type2aelembytes(op->type()), |
| 0 | 2425 op->klass()->as_register(), |
| 2426 *op->stub()->entry()); | |
| 2427 } | |
| 2428 __ bind(*op->stub()->continuation()); | |
| 2429 } | |
| 2430 | |
| 2431 | |
| 1783 | 2432 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, |
| 2433 ciMethodData *md, ciProfileData *data, | |
| 2434 Register recv, Register tmp1, Label* update_done) { | |
| 2435 uint i; | |
| 2436 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2437 Label next_test; | |
| 2438 // See if the receiver is receiver[n]. | |
| 2439 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
| 2440 mdo_offset_bias); | |
| 2441 __ ld_ptr(receiver_addr, tmp1); | |
| 2442 __ verify_oop(tmp1); | |
| 2443 __ cmp(recv, tmp1); | |
| 2444 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); | |
| 2445 __ delayed()->nop(); | |
| 2446 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
| 2447 mdo_offset_bias); | |
| 2448 __ ld_ptr(data_addr, tmp1); | |
| 2449 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
| 2450 __ st_ptr(tmp1, data_addr); | |
| 2451 __ ba(false, *update_done); | |
| 2452 __ delayed()->nop(); | |
| 2453 __ bind(next_test); | |
| 2454 } | |
| 2455 | |
| 2456 // Didn't find receiver; find next empty slot and fill it in | |
| 2457 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2458 Label next_test; | |
| 2459 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
| 2460 mdo_offset_bias); | |
| 2461 load(recv_addr, tmp1, T_OBJECT); | |
| 2462 __ br_notnull(tmp1, false, Assembler::pt, next_test); | |
| 2463 __ delayed()->nop(); | |
| 2464 __ st_ptr(recv, recv_addr); | |
| 2465 __ set(DataLayout::counter_increment, tmp1); | |
| 2466 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
| 2467 mdo_offset_bias); | |
| 2468 __ ba(false, *update_done); | |
| 2469 __ delayed()->nop(); | |
| 2470 __ bind(next_test); | |
| 2471 } | |
| 2472 } | |
| 2473 | |
| 2474 void LIR_Assembler::emit_checkcast(LIR_OpTypeCheck *op) { | |
| 2475 assert(op->code() == lir_checkcast, "Invalid operation"); | |
| 2476 // we always need a stub for the failure case. | |
| 2477 CodeStub* stub = op->stub(); | |
| 2478 Register obj = op->object()->as_register(); | |
| 2479 Register k_RInfo = op->tmp1()->as_register(); | |
| 2480 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2481 Register dst = op->result_opr()->as_register(); | |
| 2482 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2483 ciKlass* k = op->klass(); | |
| 2484 | |
| 2485 | |
| 2486 if (obj == k_RInfo) { | |
| 2487 k_RInfo = klass_RInfo; | |
| 2488 klass_RInfo = obj; | |
| 2489 } | |
| 2490 | |
| 2491 ciMethodData* md; | |
| 2492 ciProfileData* data; | |
| 2493 int mdo_offset_bias = 0; | |
| 2494 if (op->should_profile()) { | |
| 2495 ciMethod* method = op->profiled_method(); | |
| 2496 assert(method != NULL, "Should have method"); | |
| 2497 int bci = op->profiled_bci(); | |
| 2498 md = method->method_data(); | |
| 2499 if (md == NULL) { | |
| 2500 bailout("out of memory building methodDataOop"); | |
| 2501 return; | |
| 2502 } | |
| 2503 data = md->bci_to_data(bci); | |
| 2504 assert(data != NULL, "need data for checkcast"); | |
| 2505 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for checkcast"); | |
| 2506 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { | |
| 2507 // The offset is large so bias the mdo by the base of the slot so | |
| 2508 // that the ld can use simm13s to reference the slots of the data | |
| 2509 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); | |
| 2510 } | |
| 2511 | |
| 2512 // We need two temporaries to perform this operation on SPARC, | |
| 2513 // so to keep things simple we perform a redundant test here | |
| 2514 Label profile_done; | |
| 2515 __ br_notnull(obj, false, Assembler::pn, profile_done); | |
| 2516 __ delayed()->nop(); | |
| 2517 Register mdo = k_RInfo; | |
| 2518 Register data_val = Rtmp1; | |
| 2519 jobject2reg(md->constant_encoding(), mdo); | |
| 2520 if (mdo_offset_bias > 0) { | |
| 2521 __ set(mdo_offset_bias, data_val); | |
| 2522 __ add(mdo, data_val, mdo); | |
| 2523 } | |
| 2524 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); | |
| 2525 __ ldub(flags_addr, data_val); | |
| 2526 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); | |
| 2527 __ stb(data_val, flags_addr); | |
| 2528 __ bind(profile_done); | |
| 2529 } | |
| 2530 Label profile_cast_failure; | |
| 2531 | |
| 2532 Label done, done_null; | |
| 2533 // Where to go in case of cast failure | |
| 2534 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); | |
| 2535 | |
| 2536 // patching may screw with our temporaries on sparc, | |
| 2537 // so let's do it before loading the class | |
| 2538 if (k->is_loaded()) { | |
| 2539 jobject2reg(k->constant_encoding(), k_RInfo); | |
| 2540 } else { | |
| 2541 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 2542 } | |
| 2543 assert(obj != k_RInfo, "must be different"); | |
| 2544 __ br_null(obj, false, Assembler::pn, done_null); | |
| 2545 __ delayed()->nop(); | |
| 2546 | |
| 2547 // get object class | |
| 2548 // not a safepoint as obj null check happens earlier | |
| 2549 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2550 if (op->fast_check()) { | |
| 2551 assert_different_registers(klass_RInfo, k_RInfo); | |
| 2552 __ cmp(k_RInfo, klass_RInfo); | |
| 2553 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); | |
| 2554 __ delayed()->nop(); | |
| 2555 } else { | |
| 2556 bool need_slow_path = true; | |
| 2557 if (k->is_loaded()) { | |
| 2558 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) | |
| 2559 need_slow_path = false; | |
| 2560 // perform the fast part of the checking logic | |
| 2561 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, | |
| 2562 (need_slow_path ? &done : NULL), | |
| 2563 failure_target, NULL, | |
| 2564 RegisterOrConstant(k->super_check_offset())); | |
| 2565 } else { | |
| 2566 // perform the fast part of the checking logic | |
| 2567 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, | |
| 2568 failure_target, NULL); | |
| 2569 } | |
| 2570 if (need_slow_path) { | |
| 2571 // call out-of-line instance of __ check_klass_subtype_slow_path(...): | |
| 2572 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); | |
| 2573 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
| 2574 __ delayed()->nop(); | |
| 2575 __ cmp(G3, 0); | |
| 2576 __ br(Assembler::equal, false, Assembler::pn, *failure_target); | |
| 2577 __ delayed()->nop(); | |
| 2578 } | |
| 2579 } | |
| 2580 __ bind(done); | |
| 2581 | |
| 2582 if (op->should_profile()) { | |
| 2583 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; | |
| 2584 assert_different_registers(obj, mdo, recv, tmp1); | |
| 2585 | |
| 2586 jobject2reg(md->constant_encoding(), mdo); | |
| 2587 if (mdo_offset_bias > 0) { | |
| 2588 __ set(mdo_offset_bias, tmp1); | |
| 2589 __ add(mdo, tmp1, mdo); | |
| 2590 } | |
| 2591 Label update_done; | |
| 2592 load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); | |
| 2593 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); | |
| 2594 // Jump over the failure case | |
| 2595 __ ba(false, update_done); | |
| 2596 __ delayed()->nop(); | |
| 2597 | |
| 2598 | |
| 2599 // Cast failure case | |
| 2600 __ bind(profile_cast_failure); | |
| 2601 jobject2reg(md->constant_encoding(), mdo); | |
| 2602 if (mdo_offset_bias > 0) { | |
| 2603 __ set(mdo_offset_bias, tmp1); | |
| 2604 __ add(mdo, tmp1, mdo); | |
| 2605 } | |
| 2606 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); | |
| 2607 __ ld_ptr(data_addr, tmp1); | |
| 2608 __ sub(tmp1, DataLayout::counter_increment, tmp1); | |
| 2609 __ st_ptr(tmp1, data_addr); | |
| 2610 __ ba(false, *stub->entry()); | |
| 2611 __ delayed()->nop(); | |
| 2612 | |
| 2613 __ bind(update_done); | |
| 2614 } | |
| 2615 | |
| 2616 __ bind(done_null); | |
| 2617 __ mov(obj, dst); | |
| 2618 } | |
| 2619 | |
| 2620 | |
| 0 | 2621 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
| 2622 LIR_Code code = op->code(); | |
| 2623 if (code == lir_store_check) { | |
| 2624 Register value = op->object()->as_register(); | |
| 2625 Register array = op->array()->as_register(); | |
| 2626 Register k_RInfo = op->tmp1()->as_register(); | |
| 2627 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2628 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2629 | |
| 2630 __ verify_oop(value); | |
| 2631 | |
| 2632 CodeStub* stub = op->stub(); | |
| 2633 Label done; | |
| 1783 | 2634 __ br_null(value, false, Assembler::pn, done); |
| 0 | 2635 __ delayed()->nop(); |
| 2636 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); | |
| 2637 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2638 | |
| 2639 // get instance klass | |
| 2640 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2641 // perform the fast part of the checking logic |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2642 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2643 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2644 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2645 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
| 0 | 2646 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
| 2647 __ delayed()->nop(); | |
| 2648 __ cmp(G3, 0); | |
| 2649 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2650 __ delayed()->nop(); | |
| 2651 __ bind(done); | |
| 2652 } else if (code == lir_instanceof) { | |
| 2653 Register obj = op->object()->as_register(); | |
| 2654 Register k_RInfo = op->tmp1()->as_register(); | |
| 2655 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2656 Register dst = op->result_opr()->as_register(); | |
| 2657 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2658 ciKlass* k = op->klass(); | |
| 2659 | |
| 2660 Label done; | |
| 2661 if (obj == k_RInfo) { | |
| 2662 k_RInfo = klass_RInfo; | |
| 2663 klass_RInfo = obj; | |
| 2664 } | |
| 2665 // patching may screw with our temporaries on sparc, | |
| 2666 // so let's do it before loading the class | |
| 2667 if (k->is_loaded()) { | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
2668 jobject2reg(k->constant_encoding(), k_RInfo); |
| 0 | 2669 } else { |
| 2670 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 2671 } | |
| 2672 assert(obj != k_RInfo, "must be different"); | |
| 1783 | 2673 __ br_null(obj, true, Assembler::pn, done); |
| 0 | 2674 __ delayed()->set(0, dst); |
| 2675 | |
| 2676 // get object class | |
| 2677 // not a safepoint as obj null check happens earlier | |
| 2678 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2679 if (op->fast_check()) { | |
| 2680 __ cmp(k_RInfo, klass_RInfo); | |
| 1783 | 2681 __ brx(Assembler::equal, true, Assembler::pt, done); |
| 0 | 2682 __ delayed()->set(1, dst); |
| 2683 __ set(0, dst); | |
| 2684 __ bind(done); | |
| 2685 } else { | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2686 bool need_slow_path = true; |
| 0 | 2687 if (k->is_loaded()) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2688 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2689 need_slow_path = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2690 // perform the fast part of the checking logic |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2691 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2692 (need_slow_path ? &done : NULL), |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2693 (need_slow_path ? &done : NULL), NULL, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
2694 RegisterOrConstant(k->super_check_offset()), |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2695 dst); |
| 0 | 2696 } else { |
| 2697 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2698 // perform the fast part of the checking logic |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2699 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2700 &done, &done, NULL, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
2701 RegisterOrConstant(-1), |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2702 dst); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2703 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2704 if (need_slow_path) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2705 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2706 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
| 0 | 2707 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
| 2708 __ delayed()->nop(); | |
| 2709 __ mov(G3, dst); | |
| 2710 } | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
356
diff
changeset
|
2711 __ bind(done); |
| 0 | 2712 } |
| 2713 } else { | |
| 2714 ShouldNotReachHere(); | |
| 2715 } | |
| 2716 | |
| 2717 } | |
| 2718 | |
| 2719 | |
| 2720 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 2721 if (op->code() == lir_cas_long) { | |
| 2722 assert(VM_Version::supports_cx8(), "wrong machine"); | |
| 2723 Register addr = op->addr()->as_pointer_register(); | |
| 2724 Register cmp_value_lo = op->cmp_value()->as_register_lo(); | |
| 2725 Register cmp_value_hi = op->cmp_value()->as_register_hi(); | |
| 2726 Register new_value_lo = op->new_value()->as_register_lo(); | |
| 2727 Register new_value_hi = op->new_value()->as_register_hi(); | |
| 2728 Register t1 = op->tmp1()->as_register(); | |
| 2729 Register t2 = op->tmp2()->as_register(); | |
| 2730 #ifdef _LP64 | |
| 2731 __ mov(cmp_value_lo, t1); | |
| 2732 __ mov(new_value_lo, t2); | |
| 2733 #else | |
| 2734 // move high and low halves of long values into single registers | |
| 2735 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg | |
| 2736 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half | |
| 2737 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value | |
| 2738 __ sllx(new_value_hi, 32, t2); | |
| 2739 __ srl(new_value_lo, 0, new_value_lo); | |
| 2740 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap | |
| 2741 #endif | |
| 2742 // perform the compare and swap operation | |
| 2743 __ casx(addr, t1, t2); | |
| 2744 // generate condition code - if the swap succeeded, t2 ("new value" reg) was | |
| 2745 // overwritten with the original value in "addr" and will be equal to t1. | |
| 2746 __ cmp(t1, t2); | |
| 2747 | |
| 2748 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { | |
| 2749 Register addr = op->addr()->as_pointer_register(); | |
| 2750 Register cmp_value = op->cmp_value()->as_register(); | |
| 2751 Register new_value = op->new_value()->as_register(); | |
| 2752 Register t1 = op->tmp1()->as_register(); | |
| 2753 Register t2 = op->tmp2()->as_register(); | |
| 2754 __ mov(cmp_value, t1); | |
| 2755 __ mov(new_value, t2); | |
| 2756 #ifdef _LP64 | |
| 2757 if (op->code() == lir_cas_obj) { | |
| 2758 __ casx(addr, t1, t2); | |
| 2759 } else | |
| 2760 #endif | |
| 2761 { | |
| 2762 __ cas(addr, t1, t2); | |
| 2763 } | |
| 2764 __ cmp(t1, t2); | |
| 2765 } else { | |
| 2766 Unimplemented(); | |
| 2767 } | |
| 2768 } | |
| 2769 | |
| 2770 void LIR_Assembler::set_24bit_FPU() { | |
| 2771 Unimplemented(); | |
| 2772 } | |
| 2773 | |
| 2774 | |
| 2775 void LIR_Assembler::reset_FPU() { | |
| 2776 Unimplemented(); | |
| 2777 } | |
| 2778 | |
| 2779 | |
| 2780 void LIR_Assembler::breakpoint() { | |
| 2781 __ breakpoint_trap(); | |
| 2782 } | |
| 2783 | |
| 2784 | |
| 2785 void LIR_Assembler::push(LIR_Opr opr) { | |
| 2786 Unimplemented(); | |
| 2787 } | |
| 2788 | |
| 2789 | |
| 2790 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 2791 Unimplemented(); | |
| 2792 } | |
| 2793 | |
| 2794 | |
| 2795 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { | |
| 2796 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 2797 Register dst = dst_opr->as_register(); | |
| 2798 Register reg = mon_addr.base(); | |
| 2799 int offset = mon_addr.disp(); | |
| 2800 // compute pointer to BasicLock | |
| 2801 if (mon_addr.is_simm13()) { | |
| 2802 __ add(reg, offset, dst); | |
| 2803 } else { | |
| 2804 __ set(offset, dst); | |
| 2805 __ add(dst, reg, dst); | |
| 2806 } | |
| 2807 } | |
| 2808 | |
| 2809 | |
| 2810 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 2811 Register obj = op->obj_opr()->as_register(); | |
| 2812 Register hdr = op->hdr_opr()->as_register(); | |
| 2813 Register lock = op->lock_opr()->as_register(); | |
| 2814 | |
| 2815 // obj may not be an oop | |
| 2816 if (op->code() == lir_lock) { | |
| 2817 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); | |
| 2818 if (UseFastLocking) { | |
| 2819 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 2820 // add debug info for NullPointerException only if one is possible | |
| 2821 if (op->info() != NULL) { | |
| 2822 add_debug_info_for_null_check_here(op->info()); | |
| 2823 } | |
| 2824 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); | |
| 2825 } else { | |
| 2826 // always do slow locking | |
| 2827 // note: the slow locking code could be inlined here, however if we use | |
| 2828 // slow locking, speed doesn't matter anyway and this solution is | |
| 2829 // simpler and requires less duplicated code - additionally, the | |
| 2830 // slow locking code is the same in either case which simplifies | |
| 2831 // debugging | |
| 2832 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
| 2833 __ delayed()->nop(); | |
| 2834 } | |
| 2835 } else { | |
| 2836 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); | |
| 2837 if (UseFastLocking) { | |
| 2838 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 2839 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 2840 } else { | |
| 2841 // always do slow unlocking | |
| 2842 // note: the slow unlocking code could be inlined here, however if we use | |
| 2843 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 2844 // simpler and requires less duplicated code - additionally, the | |
| 2845 // slow unlocking code is the same in either case which simplifies | |
| 2846 // debugging | |
| 2847 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
| 2848 __ delayed()->nop(); | |
| 2849 } | |
| 2850 } | |
| 2851 __ bind(*op->stub()->continuation()); | |
| 2852 } | |
| 2853 | |
| 2854 | |
| 2855 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 2856 ciMethod* method = op->profiled_method(); | |
| 2857 int bci = op->profiled_bci(); | |
| 2858 | |
| 2859 // Update counter for all call types | |
| 2860 ciMethodData* md = method->method_data(); | |
| 2861 if (md == NULL) { | |
| 2862 bailout("out of memory building methodDataOop"); | |
| 2863 return; | |
| 2864 } | |
| 2865 ciProfileData* data = md->bci_to_data(bci); | |
| 2866 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 2867 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 1783 | 2868 Register mdo = op->mdo()->as_register(); |
| 2869 #ifdef _LP64 | |
| 2870 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); | |
| 2871 Register tmp1 = op->tmp1()->as_register_lo(); | |
| 2872 #else | |
| 0 | 2873 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); |
| 2874 Register tmp1 = op->tmp1()->as_register(); | |
| 1783 | 2875 #endif |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
2876 jobject2reg(md->constant_encoding(), mdo); |
| 0 | 2877 int mdo_offset_bias = 0; |
| 2878 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + | |
| 2879 data->size_in_bytes())) { | |
| 2880 // The offset is large so bias the mdo by the base of the slot so | |
| 2881 // that the ld can use simm13s to reference the slots of the data | |
| 2882 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); | |
| 2883 __ set(mdo_offset_bias, O7); | |
| 2884 __ add(mdo, O7, mdo); | |
| 2885 } | |
| 2886 | |
| 727 | 2887 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
| 0 | 2888 Bytecodes::Code bc = method->java_code_at_bci(bci); |
| 2889 // Perform additional virtual call profiling for invokevirtual and | |
| 2890 // invokeinterface bytecodes | |
| 2891 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 1783 | 2892 C1ProfileVirtualCalls) { |
| 0 | 2893 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
| 2894 Register recv = op->recv()->as_register(); | |
| 2895 assert_different_registers(mdo, tmp1, recv); | |
| 2896 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 2897 ciKlass* known_klass = op->known_holder(); | |
| 1783 | 2898 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
| 0 | 2899 // We know the type that will be seen at this call site; we can |
| 2900 // statically update the methodDataOop rather than needing to do | |
| 2901 // dynamic tests on the receiver type | |
| 2902 | |
| 2903 // NOTE: we should probably put a lock around this search to | |
| 2904 // avoid collisions by concurrent compilations | |
| 2905 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 2906 uint i; | |
| 2907 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2908 ciKlass* receiver = vc_data->receiver(i); | |
| 2909 if (known_klass->equals(receiver)) { | |
| 727 | 2910 Address data_addr(mdo, md->byte_offset_of_slot(data, |
| 2911 VirtualCallData::receiver_count_offset(i)) - | |
| 0 | 2912 mdo_offset_bias); |
| 1783 | 2913 __ ld_ptr(data_addr, tmp1); |
| 0 | 2914 __ add(tmp1, DataLayout::counter_increment, tmp1); |
| 1783 | 2915 __ st_ptr(tmp1, data_addr); |
| 0 | 2916 return; |
| 2917 } | |
| 2918 } | |
| 2919 | |
| 2920 // Receiver type not found in profile data; select an empty slot | |
| 2921 | |
| 2922 // Note that this is less efficient than it should be because it | |
| 2923 // always does a write to the receiver part of the | |
| 2924 // VirtualCallData rather than just the first time | |
| 2925 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2926 ciKlass* receiver = vc_data->receiver(i); | |
| 2927 if (receiver == NULL) { | |
| 727 | 2928 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
| 0 | 2929 mdo_offset_bias); |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
2930 jobject2reg(known_klass->constant_encoding(), tmp1); |
| 0 | 2931 __ st_ptr(tmp1, recv_addr); |
| 727 | 2932 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
| 0 | 2933 mdo_offset_bias); |
| 1783 | 2934 __ ld_ptr(data_addr, tmp1); |
| 0 | 2935 __ add(tmp1, DataLayout::counter_increment, tmp1); |
| 1783 | 2936 __ st_ptr(tmp1, data_addr); |
| 0 | 2937 return; |
| 2938 } | |
| 2939 } | |
| 2940 } else { | |
| 727 | 2941 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); |
| 0 | 2942 Label update_done; |
| 1783 | 2943 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2944 // Receiver did not match any saved receiver and there is no empty row for it. |
|
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2945 // Increment total counter to indicate polymorphic case. |
| 1783 | 2946 __ ld_ptr(counter_addr, tmp1); |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2947 __ add(tmp1, DataLayout::counter_increment, tmp1); |
| 1783 | 2948 __ st_ptr(tmp1, counter_addr); |
| 0 | 2949 |
| 2950 __ bind(update_done); | |
| 2951 } | |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2952 } else { |
|
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2953 // Static call |
| 1783 | 2954 __ ld_ptr(counter_addr, tmp1); |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
2955 __ add(tmp1, DataLayout::counter_increment, tmp1); |
| 1783 | 2956 __ st_ptr(tmp1, counter_addr); |
| 0 | 2957 } |
| 2958 } | |
| 2959 | |
| 2960 void LIR_Assembler::align_backward_branch_target() { | |
| 1365 | 2961 __ align(OptoLoopAlignment); |
| 0 | 2962 } |
| 2963 | |
| 2964 | |
| 2965 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { | |
| 2966 // make sure we are expecting a delay | |
| 2967 // this has the side effect of clearing the delay state | |
| 2968 // so we can use _masm instead of _masm->delayed() to do the | |
| 2969 // code generation. | |
| 2970 __ delayed(); | |
| 2971 | |
| 2972 // make sure we only emit one instruction | |
| 2973 int offset = code_offset(); | |
| 2974 op->delay_op()->emit_code(this); | |
| 2975 #ifdef ASSERT | |
| 2976 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { | |
| 2977 op->delay_op()->print(); | |
| 2978 } | |
| 2979 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, | |
| 2980 "only one instruction can go in a delay slot"); | |
| 2981 #endif | |
| 2982 | |
| 2983 // we may also be emitting the call info for the instruction | |
| 2984 // which we are the delay slot of. | |
| 1564 | 2985 CodeEmitInfo* call_info = op->call_info(); |
| 0 | 2986 if (call_info) { |
| 2987 add_call_info(code_offset(), call_info); | |
| 2988 } | |
| 2989 | |
| 2990 if (VerifyStackAtCalls) { | |
| 2991 _masm->sub(FP, SP, O7); | |
| 2992 _masm->cmp(O7, initial_frame_size_in_bytes()); | |
| 2993 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); | |
| 2994 } | |
| 2995 } | |
| 2996 | |
| 2997 | |
| 2998 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 2999 assert(left->is_register(), "can only handle registers"); | |
| 3000 | |
| 3001 if (left->is_single_cpu()) { | |
| 3002 __ neg(left->as_register(), dest->as_register()); | |
| 3003 } else if (left->is_single_fpu()) { | |
| 3004 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); | |
| 3005 } else if (left->is_double_fpu()) { | |
| 3006 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); | |
| 3007 } else { | |
| 3008 assert (left->is_double_cpu(), "Must be a long"); | |
| 3009 Register Rlow = left->as_register_lo(); | |
| 3010 Register Rhi = left->as_register_hi(); | |
| 3011 #ifdef _LP64 | |
| 3012 __ sub(G0, Rlow, dest->as_register_lo()); | |
| 3013 #else | |
| 3014 __ subcc(G0, Rlow, dest->as_register_lo()); | |
| 3015 __ subc (G0, Rhi, dest->as_register_hi()); | |
| 3016 #endif | |
| 3017 } | |
| 3018 } | |
| 3019 | |
| 3020 | |
| 3021 void LIR_Assembler::fxch(int i) { | |
| 3022 Unimplemented(); | |
| 3023 } | |
| 3024 | |
| 3025 void LIR_Assembler::fld(int i) { | |
| 3026 Unimplemented(); | |
| 3027 } | |
| 3028 | |
| 3029 void LIR_Assembler::ffree(int i) { | |
| 3030 Unimplemented(); | |
| 3031 } | |
| 3032 | |
| 3033 void LIR_Assembler::rt_call(LIR_Opr result, address dest, | |
| 3034 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 3035 | |
| 3036 // if tmp is invalid, then the function being called doesn't destroy the thread | |
| 3037 if (tmp->is_valid()) { | |
| 3038 __ save_thread(tmp->as_register()); | |
| 3039 } | |
| 3040 __ call(dest, relocInfo::runtime_call_type); | |
| 3041 __ delayed()->nop(); | |
| 3042 if (info != NULL) { | |
| 3043 add_call_info_here(info); | |
| 3044 } | |
| 3045 if (tmp->is_valid()) { | |
| 3046 __ restore_thread(tmp->as_register()); | |
| 3047 } | |
| 3048 | |
| 3049 #ifdef ASSERT | |
| 3050 __ verify_thread(); | |
| 3051 #endif // ASSERT | |
| 3052 } | |
| 3053 | |
| 3054 | |
| 3055 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 3056 #ifdef _LP64 | |
| 3057 ShouldNotReachHere(); | |
| 3058 #endif | |
| 3059 | |
| 3060 NEEDS_CLEANUP; | |
| 3061 if (type == T_LONG) { | |
| 3062 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); | |
| 3063 | |
| 3064 // (extended to allow indexed as well as constant displaced for JSR-166) | |
| 3065 Register idx = noreg; // contains either constant offset or index | |
| 3066 | |
| 3067 int disp = mem_addr->disp(); | |
| 3068 if (mem_addr->index() == LIR_OprFact::illegalOpr) { | |
| 3069 if (!Assembler::is_simm13(disp)) { | |
| 3070 idx = O7; | |
| 3071 __ set(disp, idx); | |
| 3072 } | |
| 3073 } else { | |
| 3074 assert(disp == 0, "not both indexed and disp"); | |
| 3075 idx = mem_addr->index()->as_register(); | |
| 3076 } | |
| 3077 | |
| 3078 int null_check_offset = -1; | |
| 3079 | |
| 3080 Register base = mem_addr->base()->as_register(); | |
| 3081 if (src->is_register() && dest->is_address()) { | |
| 3082 // G4 is high half, G5 is low half | |
| 3083 if (VM_Version::v9_instructions_work()) { | |
| 3084 // clear the top bits of G5, and scale up G4 | |
| 3085 __ srl (src->as_register_lo(), 0, G5); | |
| 3086 __ sllx(src->as_register_hi(), 32, G4); | |
| 3087 // combine the two halves into the 64 bits of G4 | |
| 3088 __ or3(G4, G5, G4); | |
| 3089 null_check_offset = __ offset(); | |
| 3090 if (idx == noreg) { | |
| 3091 __ stx(G4, base, disp); | |
| 3092 } else { | |
| 3093 __ stx(G4, base, idx); | |
| 3094 } | |
| 3095 } else { | |
| 3096 __ mov (src->as_register_hi(), G4); | |
| 3097 __ mov (src->as_register_lo(), G5); | |
| 3098 null_check_offset = __ offset(); | |
| 3099 if (idx == noreg) { | |
| 3100 __ std(G4, base, disp); | |
| 3101 } else { | |
| 3102 __ std(G4, base, idx); | |
| 3103 } | |
| 3104 } | |
| 3105 } else if (src->is_address() && dest->is_register()) { | |
| 3106 null_check_offset = __ offset(); | |
| 3107 if (VM_Version::v9_instructions_work()) { | |
| 3108 if (idx == noreg) { | |
| 3109 __ ldx(base, disp, G5); | |
| 3110 } else { | |
| 3111 __ ldx(base, idx, G5); | |
| 3112 } | |
| 3113 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi | |
| 3114 __ mov (G5, dest->as_register_lo()); // copy low half into lo | |
| 3115 } else { | |
| 3116 if (idx == noreg) { | |
| 3117 __ ldd(base, disp, G4); | |
| 3118 } else { | |
| 3119 __ ldd(base, idx, G4); | |
| 3120 } | |
| 3121 // G4 is high half, G5 is low half | |
| 3122 __ mov (G4, dest->as_register_hi()); | |
| 3123 __ mov (G5, dest->as_register_lo()); | |
| 3124 } | |
| 3125 } else { | |
| 3126 Unimplemented(); | |
| 3127 } | |
| 3128 if (info != NULL) { | |
| 3129 add_debug_info_for_null_check(null_check_offset, info); | |
| 3130 } | |
| 3131 | |
| 3132 } else { | |
| 3133 // use normal move for all other volatiles since they don't need | |
| 3134 // special handling to remain atomic. | |
| 3135 move_op(src, dest, type, lir_patch_none, info, false, false); | |
| 3136 } | |
| 3137 } | |
| 3138 | |
| 3139 void LIR_Assembler::membar() { | |
| 3140 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode | |
| 3141 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3142 } | |
| 3143 | |
| 3144 void LIR_Assembler::membar_acquire() { | |
| 3145 // no-op on TSO | |
| 3146 } | |
| 3147 | |
| 3148 void LIR_Assembler::membar_release() { | |
| 3149 // no-op on TSO | |
| 3150 } | |
| 3151 | |
| 1783 | 3152 // Pack two sequential registers containing 32 bit values |
| 0 | 3153 // into a single 64 bit register. |
| 1783 | 3154 // src and src->successor() are packed into dst |
| 3155 // src and dst may be the same register. | |
| 3156 // Note: src is destroyed | |
| 3157 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { | |
| 3158 Register rs = src->as_register(); | |
| 3159 Register rd = dst->as_register_lo(); | |
| 0 | 3160 __ sllx(rs, 32, rs); |
| 3161 __ srl(rs->successor(), 0, rs->successor()); | |
| 3162 __ or3(rs, rs->successor(), rd); | |
| 3163 } | |
| 3164 | |
| 1783 | 3165 // Unpack a 64 bit value in a register into |
| 0 | 3166 // two sequential registers. |
| 1783 | 3167 // src is unpacked into dst and dst->successor() |
| 3168 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { | |
| 3169 Register rs = src->as_register_lo(); | |
| 3170 Register rd = dst->as_register_hi(); | |
| 3171 assert_different_registers(rs, rd, rd->successor()); | |
| 3172 __ srlx(rs, 32, rd); | |
| 3173 __ srl (rs, 0, rd->successor()); | |
| 0 | 3174 } |
| 3175 | |
| 3176 | |
| 3177 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { | |
| 3178 LIR_Address* addr = addr_opr->as_address_ptr(); | |
| 3179 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); | |
| 1783 | 3180 |
| 3181 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); | |
| 0 | 3182 } |
| 3183 | |
| 3184 | |
| 3185 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
| 3186 assert(result_reg->is_register(), "check"); | |
| 3187 __ mov(G2_thread, result_reg->as_register()); | |
| 3188 } | |
| 3189 | |
| 3190 | |
| 3191 void LIR_Assembler::peephole(LIR_List* lir) { | |
| 3192 LIR_OpList* inst = lir->instructions_list(); | |
| 3193 for (int i = 0; i < inst->length(); i++) { | |
| 3194 LIR_Op* op = inst->at(i); | |
| 3195 switch (op->code()) { | |
| 3196 case lir_cond_float_branch: | |
| 3197 case lir_branch: { | |
| 3198 LIR_OpBranch* branch = op->as_OpBranch(); | |
| 3199 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); | |
| 3200 LIR_Op* delay_op = NULL; | |
| 3201 // we'd like to be able to pull following instructions into | |
| 3202 // this slot but we don't know enough to do it safely yet so | |
| 3203 // only optimize block to block control flow. | |
| 3204 if (LIRFillDelaySlots && branch->block()) { | |
| 3205 LIR_Op* prev = inst->at(i - 1); | |
| 3206 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { | |
| 3207 // swap previous instruction into delay slot | |
| 3208 inst->at_put(i - 1, op); | |
| 3209 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
| 3210 #ifndef PRODUCT | |
| 3211 if (LIRTracePeephole) { | |
| 3212 tty->print_cr("delayed"); | |
| 3213 inst->at(i - 1)->print(); | |
| 3214 inst->at(i)->print(); | |
| 1564 | 3215 tty->cr(); |
| 0 | 3216 } |
| 3217 #endif | |
| 3218 continue; | |
| 3219 } | |
| 3220 } | |
| 3221 | |
| 3222 if (!delay_op) { | |
| 3223 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); | |
| 3224 } | |
| 3225 inst->insert_before(i + 1, delay_op); | |
| 3226 break; | |
| 3227 } | |
| 3228 case lir_static_call: | |
| 3229 case lir_virtual_call: | |
| 3230 case lir_icvirtual_call: | |
| 1564 | 3231 case lir_optvirtual_call: |
| 3232 case lir_dynamic_call: { | |
| 0 | 3233 LIR_Op* prev = inst->at(i - 1); |
| 3234 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && | |
| 3235 (op->code() != lir_virtual_call || | |
| 3236 !prev->result_opr()->is_single_cpu() || | |
| 3237 prev->result_opr()->as_register() != O0) && | |
| 3238 LIR_Assembler::is_single_instruction(prev)) { | |
| 3239 // Only moves without info can be put into the delay slot. | |
| 3240 // Also don't allow the setup of the receiver in the delay | |
| 3241 // slot for vtable calls. | |
| 3242 inst->at_put(i - 1, op); | |
| 3243 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
| 3244 #ifndef PRODUCT | |
| 3245 if (LIRTracePeephole) { | |
| 3246 tty->print_cr("delayed"); | |
| 3247 inst->at(i - 1)->print(); | |
| 3248 inst->at(i)->print(); | |
| 1564 | 3249 tty->cr(); |
| 0 | 3250 } |
| 3251 #endif | |
| 1783 | 3252 } else { |
| 3253 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); | |
| 3254 inst->insert_before(i + 1, delay_op); | |
| 3255 i++; | |
| 0 | 3256 } |
| 3257 | |
| 1783 | 3258 #if defined(TIERED) && !defined(_LP64) |
| 3259 // fixup the return value from G1 to O0/O1 for long returns. | |
| 3260 // It's done here instead of in LIRGenerator because there's | |
| 3261 // such a mismatch between the single reg and double reg | |
| 3262 // calling convention. | |
| 3263 LIR_OpJavaCall* callop = op->as_OpJavaCall(); | |
| 3264 if (callop->result_opr() == FrameMap::out_long_opr) { | |
| 3265 LIR_OpJavaCall* call; | |
| 3266 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); | |
| 3267 for (int a = 0; a < arguments->length(); a++) { | |
| 3268 arguments[a] = callop->arguments()[a]; | |
| 3269 } | |
| 3270 if (op->code() == lir_virtual_call) { | |
| 3271 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
| 3272 callop->vtable_offset(), arguments, callop->info()); | |
| 3273 } else { | |
| 3274 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
| 3275 callop->addr(), arguments, callop->info()); | |
| 3276 } | |
| 3277 inst->at_put(i - 1, call); | |
| 3278 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), | |
| 3279 T_LONG, lir_patch_none, NULL)); | |
| 3280 } | |
| 3281 #endif | |
| 0 | 3282 break; |
| 3283 } | |
| 3284 } | |
| 3285 } | |
| 3286 } | |
| 3287 | |
| 3288 | |
| 3289 | |
| 3290 | |
| 3291 #undef __ |