Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 9790:6b515c453646
CompilationTask: print exception of compilation also when we don't exit the VM
for example, this is useful for CTW, in order to see on which methods the compiler bails out
| author | Bernhard Urban <bernhard.urban@jku.at> |
|---|---|
| date | Wed, 22 May 2013 16:28:12 +0200 |
| parents | 4a916f2ce331 |
| children | 46c544b8fbfc |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
| 1972 | 27 #include "memory/resourceArea.hpp" |
| 28 #include "runtime/java.hpp" | |
| 29 #include "runtime/stubCodeGenerator.hpp" | |
| 30 #include "vm_version_sparc.hpp" | |
| 31 #ifdef TARGET_OS_FAMILY_linux | |
| 32 # include "os_linux.inline.hpp" | |
| 33 #endif | |
| 34 #ifdef TARGET_OS_FAMILY_solaris | |
| 35 # include "os_solaris.inline.hpp" | |
| 36 #endif | |
| 0 | 37 |
| 38 int VM_Version::_features = VM_Version::unknown_m; | |
| 39 const char* VM_Version::_features_str = ""; | |
| 40 | |
| 41 void VM_Version::initialize() { | |
| 42 _features = determine_features(); | |
| 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
| 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
| 45 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
| 46 | |
| 3854 | 47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
| 48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
| 49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; | |
| 50 | |
| 0 | 51 // Allocation prefetch settings |
| 3854 | 52 intx cache_line_size = prefetch_data_size(); |
| 0 | 53 if( cache_line_size > AllocatePrefetchStepSize ) |
| 54 AllocatePrefetchStepSize = cache_line_size; | |
| 3854 | 55 |
| 56 assert(AllocatePrefetchLines > 0, "invalid value"); | |
| 57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
| 58 AllocatePrefetchLines = 3; | |
| 59 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
| 60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
| 61 AllocateInstancePrefetchLines = 1; | |
| 0 | 62 |
| 63 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
| 64 AllocatePrefetchStyle = allocate_prefetch_style(); | |
| 65 | |
| 3854 | 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
| 67 (AllocatePrefetchDistance > 0), "invalid value"); | |
| 68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || | |
| 69 (AllocatePrefetchDistance <= 0)) { | |
| 70 AllocatePrefetchDistance = AllocatePrefetchStepSize; | |
| 71 } | |
| 0 | 72 |
| 3839 | 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
| 74 warning("BIS instructions are not available on this CPU"); | |
| 75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
| 76 } | |
| 77 | |
| 3903 | 78 if (has_v9()) { |
| 79 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); | |
| 80 if (ArraycopySrcPrefetchDistance >= 4096) | |
| 81 ArraycopySrcPrefetchDistance = 4064; | |
| 82 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); | |
| 83 if (ArraycopyDstPrefetchDistance >= 4096) | |
| 84 ArraycopyDstPrefetchDistance = 4064; | |
| 85 } else { | |
| 86 if (ArraycopySrcPrefetchDistance > 0) { | |
| 87 warning("prefetch instructions are not available on this CPU"); | |
| 88 FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0); | |
| 89 } | |
| 90 if (ArraycopyDstPrefetchDistance > 0) { | |
| 91 warning("prefetch instructions are not available on this CPU"); | |
| 92 FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0); | |
| 93 } | |
| 94 } | |
| 95 | |
| 0 | 96 UseSSE = 0; // Only on x86 and x64 |
| 97 | |
| 3854 | 98 _supports_cx8 = has_v9(); |
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99 _supports_atomic_getset4 = true; // swap instruction |
| 0 | 100 |
| 2080 | 101 if (is_niagara()) { |
| 0 | 102 // Indirect branch is the same cost as direct |
| 103 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
| 675 | 104 FLAG_SET_DEFAULT(UseInlineCaches, false); |
| 0 | 105 } |
| 2080 | 106 // Align loops on a single instruction boundary. |
| 107 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
| 108 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
| 109 } | |
| 6610 | 110 // When using CMS or G1, we cannot use memset() in BOT updates |
| 111 // because the sun4v/CMT version in libc_psr uses BIS which | |
| 112 // exposes "phantom zeros" to concurrent readers. See 6948537. | |
| 113 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { | |
| 2080 | 114 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
| 115 } | |
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116 #ifdef _LP64 |
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117 // 32-bit oops don't make sense for the 64-bit VM on sparc |
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118 // since the 32-bit VM has the same registers and smaller objects. |
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119 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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120 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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121 #endif // _LP64 |
| 0 | 122 #ifdef COMPILER2 |
| 123 // Indirect branch is the same cost as direct | |
| 124 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
| 675 | 125 FLAG_SET_DEFAULT(UseJumpTables, true); |
| 0 | 126 } |
| 127 // Single-issue, so entry and loop tops are | |
| 128 // aligned on a single instruction boundary | |
| 129 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
| 675 | 130 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
| 0 | 131 } |
| 2080 | 132 if (is_niagara_plus()) { |
| 3854 | 133 if (has_blk_init() && UseTLAB && |
| 134 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | |
| 135 // Use BIS instruction for TLAB allocation prefetch. | |
| 136 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); | |
| 137 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { | |
| 138 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); | |
| 139 } | |
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140 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
| 3854 | 141 // Use smaller prefetch distance with BIS |
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142 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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143 } |
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144 } |
| 3854 | 145 if (is_T4()) { |
| 146 // Double number of prefetched cache lines on T4 | |
| 147 // since L2 cache line size is smaller (32 bytes). | |
| 148 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { | |
| 149 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); | |
| 150 } | |
| 151 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { | |
| 152 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); | |
| 153 } | |
| 154 } | |
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155 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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156 // Use different prefetch distance without BIS |
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157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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158 } |
| 3854 | 159 if (AllocatePrefetchInstr == 1) { |
| 160 // Need a space at the end of TLAB for BIS since it | |
| 161 // will fault when accessing memory outside of heap. | |
| 162 | |
| 163 // +1 for rounding up to next cache line, +1 to be safe | |
| 164 int lines = AllocatePrefetchLines + 2; | |
| 165 int step_size = AllocatePrefetchStepSize; | |
| 166 int distance = AllocatePrefetchDistance; | |
| 167 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; | |
| 168 } | |
| 0 | 169 } |
| 170 #endif | |
| 171 } | |
| 172 | |
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173 // Use hardware population count instruction if available. |
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174 if (has_hardware_popc()) { |
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175 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
| 675 | 176 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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177 } |
| 3839 | 178 } else if (UsePopCountInstruction) { |
| 179 warning("POPC instruction is not available on this CPU"); | |
| 180 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
| 181 } | |
| 182 | |
| 183 // T4 and newer Sparc cpus have new compare and branch instruction. | |
| 184 if (has_cbcond()) { | |
| 185 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
| 186 FLAG_SET_DEFAULT(UseCBCond, true); | |
| 187 } | |
| 188 } else if (UseCBCond) { | |
| 189 warning("CBCOND instruction is not available on this CPU"); | |
| 190 FLAG_SET_DEFAULT(UseCBCond, false); | |
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191 } |
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192 |
| 3892 | 193 assert(BlockZeroingLowLimit > 0, "invalid value"); |
| 194 if (has_block_zeroing()) { | |
| 195 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { | |
| 196 FLAG_SET_DEFAULT(UseBlockZeroing, true); | |
| 197 } | |
| 198 } else if (UseBlockZeroing) { | |
| 199 warning("BIS zeroing instructions are not available on this CPU"); | |
| 200 FLAG_SET_DEFAULT(UseBlockZeroing, false); | |
| 201 } | |
| 202 | |
| 3903 | 203 assert(BlockCopyLowLimit > 0, "invalid value"); |
| 204 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache | |
| 205 if (FLAG_IS_DEFAULT(UseBlockCopy)) { | |
| 206 FLAG_SET_DEFAULT(UseBlockCopy, true); | |
| 207 } | |
| 208 } else if (UseBlockCopy) { | |
| 209 warning("BIS instructions are not available or expensive on this CPU"); | |
| 210 FLAG_SET_DEFAULT(UseBlockCopy, false); | |
| 211 } | |
| 212 | |
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213 #ifdef COMPILER2 |
| 3839 | 214 // T4 and newer Sparc cpus have fast RDPC. |
| 215 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
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216 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
| 3839 | 217 } |
| 218 | |
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219 // Currently not supported anywhere. |
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220 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
| 3851 | 221 |
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222 MaxVectorSize = 8; |
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223 |
| 3851 | 224 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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225 #endif |
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226 |
| 3851 | 227 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
| 228 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); | |
| 229 | |
| 0 | 230 char buf[512]; |
| 3839 | 231 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| 232 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), | |
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233 (has_hardware_popc() ? ", popc" : ""), |
| 3839 | 234 (has_vis1() ? ", vis1" : ""), |
| 235 (has_vis2() ? ", vis2" : ""), | |
| 236 (has_vis3() ? ", vis3" : ""), | |
| 237 (has_blk_init() ? ", blk_init" : ""), | |
| 238 (has_cbcond() ? ", cbcond" : ""), | |
| 239 (is_ultra3() ? ", ultra3" : ""), | |
| 240 (is_sun4v() ? ", sun4v" : ""), | |
| 241 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
| 242 (is_sparc64() ? ", sparc64" : ""), | |
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243 (!has_hardware_mul32() ? ", no-mul32" : ""), |
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244 (!has_hardware_div32() ? ", no-div32" : ""), |
| 0 | 245 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
| 246 | |
| 247 // buf is started with ", " or is empty | |
| 248 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
| 249 | |
| 3804 | 250 // UseVIS is set to the smallest of what hardware supports and what |
| 251 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
| 252 // older UltraSparc which do not support it. | |
| 253 if (UseVIS > 3) UseVIS=3; | |
| 254 if (UseVIS < 0) UseVIS=0; | |
| 255 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
| 256 UseVIS = MIN2((intx)2,UseVIS); | |
| 257 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
| 258 UseVIS = MIN2((intx)1,UseVIS); | |
| 259 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
| 260 UseVIS = 0; | |
| 261 | |
| 7587 | 262 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
| 263 (cache_line_size > ContendedPaddingWidth)) | |
| 264 ContendedPaddingWidth = cache_line_size; | |
| 265 | |
| 0 | 266 #ifndef PRODUCT |
| 267 if (PrintMiscellaneous && Verbose) { | |
| 3854 | 268 tty->print("Allocation"); |
| 0 | 269 if (AllocatePrefetchStyle <= 0) { |
| 3854 | 270 tty->print_cr(": no prefetching"); |
| 0 | 271 } else { |
| 3854 | 272 tty->print(" prefetching: "); |
| 273 if (AllocatePrefetchInstr == 0) { | |
| 274 tty->print("PREFETCH"); | |
| 275 } else if (AllocatePrefetchInstr == 1) { | |
| 276 tty->print("BIS"); | |
| 277 } | |
| 0 | 278 if (AllocatePrefetchLines > 1) { |
| 3854 | 279 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
| 0 | 280 } else { |
| 3854 | 281 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
| 0 | 282 } |
| 283 } | |
| 284 if (PrefetchCopyIntervalInBytes > 0) { | |
| 285 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
| 286 } | |
| 287 if (PrefetchScanIntervalInBytes > 0) { | |
| 288 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
| 289 } | |
| 290 if (PrefetchFieldsAhead > 0) { | |
| 291 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
| 292 } | |
| 7587 | 293 if (ContendedPaddingWidth > 0) { |
| 294 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth); | |
| 295 } | |
| 0 | 296 } |
| 297 #endif // PRODUCT | |
| 298 } | |
| 299 | |
| 300 void VM_Version::print_features() { | |
| 301 tty->print_cr("Version:%s", cpu_features()); | |
| 302 } | |
| 303 | |
| 304 int VM_Version::determine_features() { | |
| 305 if (UseV8InstrsOnly) { | |
| 306 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
| 307 return generic_v8_m; | |
| 308 } | |
| 309 | |
| 310 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
| 311 | |
| 312 if (features == unknown_m) { | |
| 313 features = generic_v9_m; | |
| 314 warning("Cannot recognize SPARC version. Default to V9"); | |
| 315 } | |
| 316 | |
| 2080 | 317 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
| 318 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
| 319 if (is_T_family(features)) { | |
| 0 | 320 // Happy to accomodate... |
| 321 } else { | |
| 322 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
| 2080 | 323 features |= T_family_m; |
| 0 | 324 } |
| 325 } else { | |
| 2080 | 326 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
| 0 | 327 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
| 2080 | 328 features &= ~(T_family_m | T1_model_m); |
| 0 | 329 } else { |
| 330 // Happy to accomodate... | |
| 331 } | |
| 332 } | |
| 333 | |
| 334 return features; | |
| 335 } | |
| 336 | |
| 337 static int saved_features = 0; | |
| 338 | |
| 339 void VM_Version::allow_all() { | |
| 340 saved_features = _features; | |
| 341 _features = all_features_m; | |
| 342 } | |
| 343 | |
| 344 void VM_Version::revert() { | |
| 345 _features = saved_features; | |
| 346 } | |
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347 |
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348 unsigned int VM_Version::calc_parallel_worker_threads() { |
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349 unsigned int result; |
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350 if (is_M_series()) { |
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351 // for now, use same gc thread calculation for M-series as for niagara-plus |
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352 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
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353 result = nof_parallel_worker_threads(5, 16, 8); |
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354 } else if (is_niagara_plus()) { |
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355 result = nof_parallel_worker_threads(5, 16, 8); |
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356 } else { |
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357 result = nof_parallel_worker_threads(5, 8, 8); |
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358 } |
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359 return result; |
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360 } |