Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 2080:c04052fd6ae1
7006505: Use kstat info to identify SPARC processor
Summary: read Solaris kstat data to get more precise CPU information
Reviewed-by: iveresov, never, twisti, dholmes
| author | kvn |
|---|---|
| date | Thu, 16 Dec 2010 14:15:12 -0800 |
| parents | f95d63e2154a |
| children | faa472957b38 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_sparc.inline.hpp" | |
| 27 #include "memory/resourceArea.hpp" | |
| 28 #include "runtime/java.hpp" | |
| 29 #include "runtime/stubCodeGenerator.hpp" | |
| 30 #include "vm_version_sparc.hpp" | |
| 31 #ifdef TARGET_OS_FAMILY_linux | |
| 32 # include "os_linux.inline.hpp" | |
| 33 #endif | |
| 34 #ifdef TARGET_OS_FAMILY_solaris | |
| 35 # include "os_solaris.inline.hpp" | |
| 36 #endif | |
| 0 | 37 |
| 38 int VM_Version::_features = VM_Version::unknown_m; | |
| 39 const char* VM_Version::_features_str = ""; | |
| 40 | |
| 41 void VM_Version::initialize() { | |
| 42 _features = determine_features(); | |
| 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
| 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
| 45 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
| 46 | |
| 47 // Allocation prefetch settings | |
| 48 intx cache_line_size = L1_data_cache_line_size(); | |
| 49 if( cache_line_size > AllocatePrefetchStepSize ) | |
| 50 AllocatePrefetchStepSize = cache_line_size; | |
| 51 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
| 52 AllocatePrefetchLines = 3; // Optimistic value | |
| 53 assert( AllocatePrefetchLines > 0, "invalid value"); | |
| 54 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
| 55 AllocatePrefetchLines = 1; // Conservative value | |
| 56 | |
| 57 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
| 58 AllocatePrefetchStyle = allocate_prefetch_style(); | |
| 59 | |
| 60 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
| 61 | |
| 62 UseSSE = 0; // Only on x86 and x64 | |
| 63 | |
| 64 _supports_cx8 = has_v9(); | |
| 65 | |
| 2080 | 66 if (is_niagara()) { |
| 0 | 67 // Indirect branch is the same cost as direct |
| 68 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
| 675 | 69 FLAG_SET_DEFAULT(UseInlineCaches, false); |
| 0 | 70 } |
| 2080 | 71 // Align loops on a single instruction boundary. |
| 72 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
| 73 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
| 74 } | |
| 75 // When using CMS, we cannot use memset() in BOT updates because | |
| 76 // the sun4v/CMT version in libc_psr uses BIS which exposes | |
| 77 // "phantom zeros" to concurrent readers. See 6948537. | |
| 78 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) { | |
| 79 FLAG_SET_DEFAULT(UseMemSetInBOT, false); | |
| 80 } | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
81 #ifdef _LP64 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
82 // 32-bit oops don't make sense for the 64-bit VM on sparc |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
83 // since the 32-bit VM has the same registers and smaller objects. |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
84 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
85 #endif // _LP64 |
| 0 | 86 #ifdef COMPILER2 |
| 87 // Indirect branch is the same cost as direct | |
| 88 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
| 675 | 89 FLAG_SET_DEFAULT(UseJumpTables, true); |
| 0 | 90 } |
| 91 // Single-issue, so entry and loop tops are | |
| 92 // aligned on a single instruction boundary | |
| 93 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
| 675 | 94 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
| 0 | 95 } |
| 2080 | 96 if (is_niagara_plus()) { |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
97 if (has_blk_init() && AllocatePrefetchStyle > 0 && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
98 FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
|
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
99 // Use BIS instruction for allocation prefetch. |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
100 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
101 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
102 // Use smaller prefetch distance on N2 with BIS |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
103 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
104 } |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
105 } |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
106 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
107 // Use different prefetch distance without BIS |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
108 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
|
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
109 } |
| 0 | 110 } |
| 111 #endif | |
| 112 } | |
| 113 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
114 // Use hardware population count instruction if available. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
115 if (has_hardware_popc()) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
116 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
| 675 | 117 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
118 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
119 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
120 |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
121 #ifdef COMPILER2 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
122 // Currently not supported anywhere. |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
123 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
124 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
125 |
| 0 | 126 char buf[512]; |
| 2080 | 127 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| 0 | 128 (has_v8() ? ", has_v8" : ""), |
| 129 (has_v9() ? ", has_v9" : ""), | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
130 (has_hardware_popc() ? ", popc" : ""), |
| 0 | 131 (has_vis1() ? ", has_vis1" : ""), |
| 132 (has_vis2() ? ", has_vis2" : ""), | |
| 2080 | 133 (has_vis3() ? ", has_vis3" : ""), |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
134 (has_blk_init() ? ", has_blk_init" : ""), |
| 0 | 135 (is_ultra3() ? ", is_ultra3" : ""), |
| 136 (is_sun4v() ? ", is_sun4v" : ""), | |
| 2080 | 137 (is_niagara() ? ", is_niagara" : ""), |
| 138 (is_niagara_plus() ? ", is_niagara_plus" : ""), | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
139 (is_sparc64() ? ", is_sparc64" : ""), |
|
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
140 (!has_hardware_mul32() ? ", no-mul32" : ""), |
|
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
141 (!has_hardware_div32() ? ", no-div32" : ""), |
| 0 | 142 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
| 143 | |
| 144 // buf is started with ", " or is empty | |
| 145 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
| 146 | |
| 147 #ifndef PRODUCT | |
| 148 if (PrintMiscellaneous && Verbose) { | |
| 149 tty->print("Allocation: "); | |
| 150 if (AllocatePrefetchStyle <= 0) { | |
| 151 tty->print_cr("no prefetching"); | |
| 152 } else { | |
| 153 if (AllocatePrefetchLines > 1) { | |
| 154 tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
| 155 } else { | |
| 156 tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance); | |
| 157 } | |
| 158 } | |
| 159 if (PrefetchCopyIntervalInBytes > 0) { | |
| 160 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
| 161 } | |
| 162 if (PrefetchScanIntervalInBytes > 0) { | |
| 163 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
| 164 } | |
| 165 if (PrefetchFieldsAhead > 0) { | |
| 166 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
| 167 } | |
| 168 } | |
| 169 #endif // PRODUCT | |
| 170 } | |
| 171 | |
| 172 void VM_Version::print_features() { | |
| 173 tty->print_cr("Version:%s", cpu_features()); | |
| 174 } | |
| 175 | |
| 176 int VM_Version::determine_features() { | |
| 177 if (UseV8InstrsOnly) { | |
| 178 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
| 179 return generic_v8_m; | |
| 180 } | |
| 181 | |
| 182 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
| 183 | |
| 184 if (features == unknown_m) { | |
| 185 features = generic_v9_m; | |
| 186 warning("Cannot recognize SPARC version. Default to V9"); | |
| 187 } | |
| 188 | |
| 2080 | 189 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
| 190 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
| 191 if (is_T_family(features)) { | |
| 0 | 192 // Happy to accomodate... |
| 193 } else { | |
| 194 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
| 2080 | 195 features |= T_family_m; |
| 0 | 196 } |
| 197 } else { | |
| 2080 | 198 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
| 0 | 199 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
| 2080 | 200 features &= ~(T_family_m | T1_model_m); |
| 0 | 201 } else { |
| 202 // Happy to accomodate... | |
| 203 } | |
| 204 } | |
| 205 | |
| 206 return features; | |
| 207 } | |
| 208 | |
| 209 static int saved_features = 0; | |
| 210 | |
| 211 void VM_Version::allow_all() { | |
| 212 saved_features = _features; | |
| 213 _features = all_features_m; | |
| 214 } | |
| 215 | |
| 216 void VM_Version::revert() { | |
| 217 _features = saved_features; | |
| 218 } | |
|
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
219 |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
220 unsigned int VM_Version::calc_parallel_worker_threads() { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
221 unsigned int result; |
| 2080 | 222 if (is_niagara_plus()) { |
|
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
223 result = nof_parallel_worker_threads(5, 16, 8); |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
224 } else { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
225 result = nof_parallel_worker_threads(5, 8, 8); |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
226 } |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
227 return result; |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
228 } |