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annotate src/cpu/x86/vm/x86_32.ad @ 14726:92aa6797d639
Backed out merge changeset: b51e29501f30
Backed out merge revision to its first parent (8f483e200405)
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Mon, 24 Mar 2014 21:30:43 +0100 |
| parents | 9e9af3aa4278 |
| children |
| rev | line source |
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| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
| 126 // Class for all registers | |
| 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 128 // Class for general registers | |
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129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
| 0 | 130 // Class for general registers which may be used for implicit null checks on win95 |
| 131 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
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132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); |
| 0 | 133 // Class of "X" registers |
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134 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
| 0 | 135 // Class of registers that can appear in an address with no offset. |
| 136 // EBP and ESP require an extra instruction byte for zero offset. | |
| 137 // Used in fast-unlock | |
| 138 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 139 // Class for general registers not including ECX | |
| 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 141 // Class for general registers not including EAX | |
| 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 143 // Class for general registers not including EAX or EBX. | |
| 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 145 // Class of EAX (for multiply and divide operations) | |
| 146 reg_class eax_reg(EAX); | |
| 147 // Class of EBX (for atomic add) | |
| 148 reg_class ebx_reg(EBX); | |
| 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 150 reg_class ecx_reg(ECX); | |
| 151 // Class of EDX (for multiply and divide operations) | |
| 152 reg_class edx_reg(EDX); | |
| 153 // Class of EDI (for synchronization) | |
| 154 reg_class edi_reg(EDI); | |
| 155 // Class of ESI (for synchronization) | |
| 156 reg_class esi_reg(ESI); | |
| 157 // Singleton class for interpreter's stack pointer | |
| 158 reg_class ebp_reg(EBP); | |
| 159 // Singleton class for stack pointer | |
| 160 reg_class sp_reg(ESP); | |
| 161 // Singleton class for instruction pointer | |
| 162 // reg_class ip_reg(EIP); | |
| 163 // Class of integer register pairs | |
| 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 165 // Class of integer register pairs that aligns with calling convention | |
| 166 reg_class eadx_reg( EAX,EDX ); | |
| 167 reg_class ebcx_reg( ECX,EBX ); | |
| 168 // Not AX or DX, used in divides | |
| 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 170 | |
| 171 // Floating point registers. Notice FPR0 is not a choice. | |
| 172 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 173 // a 2-address instructions out of Intels FP stack. | |
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174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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175 |
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176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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178 FPR7L,FPR7H ); |
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179 |
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180 reg_class fp_flt_reg0( FPR1L ); |
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181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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185 |
| 0 | 186 %} |
| 187 | |
| 188 | |
| 189 //----------SOURCE BLOCK------------------------------------------------------- | |
| 190 // This is a block of C++ code which provides values, functions, and | |
| 191 // definitions necessary in the rest of the architecture description | |
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192 source_hpp %{ |
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193 // Must be visible to the DFA in dfa_x86_32.cpp |
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194 extern bool is_operand_hi32_zero(Node* n); |
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195 %} |
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196 |
| 0 | 197 source %{ |
| 304 | 198 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 199 #define RELOC_DISP32 Assembler::disp32_operand |
| 200 | |
| 201 #define __ _masm. | |
| 202 | |
| 203 // How to find the high register of a Long pair, given the low register | |
| 204 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 205 | |
| 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 207 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 208 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 209 | |
| 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 213 // of 128-bits operands for SSE instructions. | |
| 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 215 // Store the value to a 128-bits operand. | |
| 216 operand[0] = lo; | |
| 217 operand[1] = hi; | |
| 218 return operand; | |
| 219 } | |
| 220 | |
| 221 // Buffer for 128-bits masks used by SSE instructions. | |
| 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 223 | |
| 224 // Static initialization during VM startup. | |
| 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 229 | |
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230 // Offset hacking within calls. |
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231 static int pre_call_resets_size() { |
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232 int size = 0; |
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233 Compile* C = Compile::current(); |
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234 if (C->in_24_bit_fp_mode()) { |
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235 size += 6; // fldcw |
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236 } |
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237 if (C->max_vector_size() > 16) { |
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238 size += 3; // vzeroupper |
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239 } |
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240 return size; |
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241 } |
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242 |
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243 static int preserve_SP_size() { |
| 4759 | 244 return 2; // op, rm(reg/reg) |
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245 } |
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246 |
| 0 | 247 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 248 // from the start of the call to the point where the return address | |
| 249 // will point. | |
| 250 int MachCallStaticJavaNode::ret_addr_offset() { | |
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251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
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252 if (_method_handle_invoke) |
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253 offset += preserve_SP_size(); |
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254 return offset; |
| 0 | 255 } |
| 256 | |
| 257 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 259 } |
| 260 | |
| 261 static int sizeof_FFree_Float_Stack_All = -1; | |
| 262 | |
| 263 int MachCallRuntimeNode::ret_addr_offset() { | |
| 264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 266 } |
| 267 | |
| 268 // Indicate if the safepoint node needs the polling page as an input. | |
| 269 // Since x86 does have absolute addressing, it doesn't. | |
| 270 bool SafePointNode::needs_polling_address_input() { | |
| 271 return false; | |
| 272 } | |
| 273 | |
| 274 // | |
| 275 // Compute padding required for nodes which need alignment | |
| 276 // | |
| 277 | |
| 278 // The address of the call instruction needs to be 4-byte aligned to | |
| 279 // ensure that it does not span a cache line so that it can be patched. | |
| 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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281 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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282 current_offset += 1; // skip call opcode byte |
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283 return round_to(current_offset, alignment_required()) - current_offset; |
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284 } |
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285 |
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286 // The address of the call instruction needs to be 4-byte aligned to |
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287 // ensure that it does not span a cache line so that it can be patched. |
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288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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289 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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290 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 291 current_offset += 1; // skip call opcode byte |
| 292 return round_to(current_offset, alignment_required()) - current_offset; | |
| 293 } | |
| 294 | |
| 295 // The address of the call instruction needs to be 4-byte aligned to | |
| 296 // ensure that it does not span a cache line so that it can be patched. | |
| 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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298 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 299 current_offset += 5; // skip MOV instruction |
| 300 current_offset += 1; // skip call opcode byte | |
| 301 return round_to(current_offset, alignment_required()) - current_offset; | |
| 302 } | |
| 303 | |
| 304 // EMIT_RM() | |
| 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 307 cbuf.insts()->emit_int8(c); |
| 0 | 308 } |
| 309 | |
| 310 // EMIT_CC() | |
| 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 312 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 313 cbuf.insts()->emit_int8(c); |
| 0 | 314 } |
| 315 | |
| 316 // EMIT_OPCODE() | |
| 317 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 318 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 319 } |
| 320 | |
| 321 // EMIT_OPCODE() w/ relocation information | |
| 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 323 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 324 emit_opcode(cbuf, code); |
| 325 } | |
| 326 | |
| 327 // EMIT_D8() | |
| 328 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 329 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 330 } |
| 331 | |
| 332 // EMIT_D16() | |
| 333 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 334 cbuf.insts()->emit_int16(d16); |
| 0 | 335 } |
| 336 | |
| 337 // EMIT_D32() | |
| 338 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 339 cbuf.insts()->emit_int32(d32); |
| 0 | 340 } |
| 341 | |
| 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 344 int format) { | |
| 1748 | 345 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 346 cbuf.insts()->emit_int32(d32); | |
| 0 | 347 } |
| 348 | |
| 349 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 351 int format) { | |
| 352 #ifdef ASSERT | |
| 353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 355 } |
| 356 #endif | |
| 1748 | 357 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 358 cbuf.insts()->emit_int32(d32); | |
| 0 | 359 } |
| 360 | |
| 361 // Access stack slot for load or store | |
| 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 364 if( -128 <= disp && disp <= 127 ) { | |
| 365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 367 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 368 } else { | |
| 369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 371 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 372 } | |
| 373 } | |
| 374 | |
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375 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 377 // There is no index & no scale, use form without SIB byte |
| 378 if ((index == 0x4) && | |
| 379 (scale == 0) && (base != ESP_enc)) { | |
| 380 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 381 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 382 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 383 } | |
| 384 else { // If 8-bit displacement, mode 0x1 | |
| 385 if ((displace >= -128) && (displace <= 127) | |
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386 && (disp_reloc == relocInfo::none) ) { |
| 0 | 387 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 388 emit_d8(cbuf, displace); | |
| 389 } | |
| 390 else { // If 32-bit displacement | |
| 391 if (base == -1) { // Special flag for absolute address | |
| 392 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 393 // (manual lies; no SIB needed here) | |
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394 if ( disp_reloc != relocInfo::none ) { |
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395 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 396 } else { |
| 397 emit_d32 (cbuf, displace); | |
| 398 } | |
| 399 } | |
| 400 else { // Normal base + offset | |
| 401 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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402 if ( disp_reloc != relocInfo::none ) { |
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403 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 404 } else { |
| 405 emit_d32 (cbuf, displace); | |
| 406 } | |
| 407 } | |
| 408 } | |
| 409 } | |
| 410 } | |
| 411 else { // Else, encode with the SIB byte | |
| 412 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 413 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 414 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 415 emit_rm(cbuf, scale, index, base); | |
| 416 } | |
| 417 else { // If 8-bit displacement, mode 0x1 | |
| 418 if ((displace >= -128) && (displace <= 127) | |
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419 && (disp_reloc == relocInfo::none) ) { |
| 0 | 420 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 421 emit_rm(cbuf, scale, index, base); | |
| 422 emit_d8(cbuf, displace); | |
| 423 } | |
| 424 else { // If 32-bit displacement | |
| 425 if (base == 0x04 ) { | |
| 426 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 427 emit_rm(cbuf, scale, index, 0x04); | |
| 428 } else { | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 430 emit_rm(cbuf, scale, index, base); | |
| 431 } | |
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432 if ( disp_reloc != relocInfo::none ) { |
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433 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 434 } else { |
| 435 emit_d32 (cbuf, displace); | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 } | |
| 440 } | |
| 441 | |
| 442 | |
| 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 444 if( dst_encoding == src_encoding ) { | |
| 445 // reg-reg copy, use an empty encoding | |
| 446 } else { | |
| 447 emit_opcode( cbuf, 0x8B ); | |
| 448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 449 } | |
| 450 } | |
| 451 | |
| 4759 | 452 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 453 Label exit; | |
| 454 __ jccb(Assembler::noParity, exit); | |
| 455 __ pushf(); | |
| 456 // | |
| 457 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 458 // zero OF,AF,SF for NaN values. | |
| 459 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 460 // values returns 'less than' result (CF is set). | |
| 461 // Leave the rest of flags unchanged. | |
| 462 // | |
| 463 // 7 6 5 4 3 2 1 0 | |
| 464 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 465 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 466 // | |
| 467 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 468 __ popf(); | |
| 469 __ bind(exit); | |
| 470 } | |
| 471 | |
| 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 473 Label done; | |
| 474 __ movl(dst, -1); | |
| 475 __ jcc(Assembler::parity, done); | |
| 476 __ jcc(Assembler::below, done); | |
| 477 __ setb(Assembler::notEqual, dst); | |
| 478 __ movzbl(dst, dst); | |
| 479 __ bind(done); | |
| 0 | 480 } |
| 481 | |
| 482 | |
| 483 //============================================================================= | |
| 2008 | 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 485 | |
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486 int Compile::ConstantTable::calculate_table_base_offset() const { |
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487 return 0; // absolute addressing, no offset |
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488 } |
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489 |
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490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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492 ShouldNotReachHere(); |
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493 } |
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494 |
| 2008 | 495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 496 // Empty encoding | |
| 497 } | |
| 498 | |
| 499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 500 return 0; | |
| 501 } | |
| 502 | |
| 503 #ifndef PRODUCT | |
| 504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 505 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 506 } | |
| 507 #endif | |
| 508 | |
| 509 | |
| 510 //============================================================================= | |
| 0 | 511 #ifndef PRODUCT |
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512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 513 Compile* C = ra_->C; |
| 514 | |
| 515 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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517 // Remove wordSize for return addr which is already pushed. |
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518 framesize -= wordSize; |
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519 |
| 0 | 520 if (C->need_stack_bang(framesize)) { |
| 521 framesize -= wordSize; | |
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522 st->print("# stack bang"); |
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523 st->print("\n\t"); |
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524 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 525 if (framesize) { |
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526 st->print("\n\t"); |
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527 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 528 } |
| 529 } else { | |
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530 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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531 st->print("\n\t"); |
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532 framesize -= wordSize; |
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533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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534 } |
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535 |
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536 if (VerifyStackAtCalls) { |
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537 st->print("\n\t"); |
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538 framesize -= wordSize; |
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539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 540 } |
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541 |
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542 if( C->in_24_bit_fp_mode() ) { |
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543 st->print("\n\t"); |
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544 st->print("FLDCW \t# load 24 bit fpu control word"); |
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545 } |
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546 if (UseSSE >= 2 && VerifyFPU) { |
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547 st->print("\n\t"); |
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548 st->print("# verify FPU stack (must be clean on entry)"); |
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549 } |
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550 |
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551 #ifdef ASSERT |
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552 if (VerifyStackAtCalls) { |
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553 st->print("\n\t"); |
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554 st->print("# stack alignment check"); |
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555 } |
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556 #endif |
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557 st->cr(); |
| 0 | 558 } |
| 559 #endif | |
| 560 | |
| 561 | |
| 562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 563 Compile* C = ra_->C; | |
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564 MacroAssembler _masm(&cbuf); |
| 0 | 565 |
| 566 int framesize = C->frame_slots() << LogBytesPerInt; | |
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567 |
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568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); |
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569 |
| 1748 | 570 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 571 |
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572 if (C->has_mach_constant_base_node()) { |
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573 // NOTE: We set the table base offset here because users might be |
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574 // emitted before MachConstantBaseNode. |
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575 Compile::ConstantTable& constant_table = C->constant_table(); |
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576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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577 } |
| 0 | 578 } |
| 579 | |
| 580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 581 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 582 } | |
| 583 | |
| 584 int MachPrologNode::reloc() const { | |
| 585 return 0; // a large enough number | |
| 586 } | |
| 587 | |
| 588 //============================================================================= | |
| 589 #ifndef PRODUCT | |
| 590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 591 Compile *C = ra_->C; | |
| 592 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 594 // Remove two words for return addr and rbp, | |
| 595 framesize -= 2*wordSize; | |
| 596 | |
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597 if (C->max_vector_size() > 16) { |
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598 st->print("VZEROUPPER"); |
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599 st->cr(); st->print("\t"); |
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600 } |
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601 if (C->in_24_bit_fp_mode()) { |
| 0 | 602 st->print("FLDCW standard control word"); |
| 603 st->cr(); st->print("\t"); | |
| 604 } | |
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605 if (framesize) { |
| 0 | 606 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 607 st->cr(); st->print("\t"); | |
| 608 } | |
| 609 st->print_cr("POPL EBP"); st->print("\t"); | |
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610 if (do_polling() && C->is_method_compilation()) { |
| 0 | 611 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 612 st->cr(); st->print("\t"); | |
| 613 } | |
| 614 } | |
| 615 #endif | |
| 616 | |
| 617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 618 Compile *C = ra_->C; | |
| 619 | |
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620 if (C->max_vector_size() > 16) { |
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621 // Clear upper bits of YMM registers when current compiled code uses |
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622 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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623 MacroAssembler masm(&cbuf); |
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624 masm.vzeroupper(); |
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625 } |
| 0 | 626 // If method set FPU control word, restore to standard control word |
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627 if (C->in_24_bit_fp_mode()) { |
| 0 | 628 MacroAssembler masm(&cbuf); |
| 629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 630 } | |
| 631 | |
| 632 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 634 // Remove two words for return addr and rbp, | |
| 635 framesize -= 2*wordSize; | |
| 636 | |
| 637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 638 | |
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639 if (framesize >= 128) { |
| 0 | 640 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 641 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 642 emit_d32(cbuf, framesize); | |
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643 } else if (framesize) { |
| 0 | 644 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 645 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 646 emit_d8(cbuf, framesize); | |
| 647 } | |
| 648 | |
| 649 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 650 | |
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651 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 653 emit_opcode(cbuf,0x85); |
| 654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 655 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 656 } | |
| 657 } | |
| 658 | |
| 659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 660 Compile *C = ra_->C; | |
| 661 // If method set FPU control word, restore to standard control word | |
| 662 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
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663 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
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664 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 665 |
| 666 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 668 // Remove two words for return addr and rbp, | |
| 669 framesize -= 2*wordSize; | |
| 670 | |
| 671 size++; // popl rbp, | |
| 672 | |
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673 if (framesize >= 128) { |
| 0 | 674 size += 6; |
| 675 } else { | |
| 676 size += framesize ? 3 : 0; | |
| 677 } | |
| 678 return size; | |
| 679 } | |
| 680 | |
| 681 int MachEpilogNode::reloc() const { | |
| 682 return 0; // a large enough number | |
| 683 } | |
| 684 | |
| 685 const Pipeline * MachEpilogNode::pipeline() const { | |
| 686 return MachNode::pipeline_class(); | |
| 687 } | |
| 688 | |
| 689 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 690 | |
| 691 //============================================================================= | |
| 692 | |
| 693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 694 static enum RC rc_class( OptoReg::Name reg ) { | |
| 695 | |
| 696 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 697 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 698 | |
| 699 VMReg r = OptoReg::as_VMReg(reg); | |
| 700 if (r->is_Register()) return rc_int; | |
| 701 if (r->is_FloatRegister()) { | |
| 702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 703 return rc_float; | |
| 704 } | |
| 705 assert(r->is_XMMRegister(), "must be"); | |
| 706 return rc_xmm; | |
| 707 } | |
| 708 | |
|
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709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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710 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 711 if( cbuf ) { |
| 712 emit_opcode (*cbuf, opcode ); | |
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713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 714 #ifndef PRODUCT |
| 715 } else if( !do_size ) { | |
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716 if( size != 0 ) st->print("\n\t"); |
| 0 | 717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
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718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 720 } else { // FLD, FST, PUSH, POP |
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721 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 722 } |
| 723 #endif | |
| 724 } | |
| 725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 726 return size+3+offset_size; | |
| 727 } | |
| 728 | |
| 729 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
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731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 732 if (cbuf) { |
| 733 MacroAssembler _masm(cbuf); | |
| 734 if (reg_lo+1 == reg_hi) { // double move? | |
| 735 if (is_load) { | |
| 736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 737 } else { | |
| 738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 739 } | |
| 0 | 740 } else { |
| 4759 | 741 if (is_load) { |
| 742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 743 } else { | |
| 744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 745 } | |
| 0 | 746 } |
| 747 #ifndef PRODUCT | |
| 4759 | 748 } else if (!do_size) { |
| 749 if (size != 0) st->print("\n\t"); | |
| 750 if (reg_lo+1 == reg_hi) { // double move? | |
| 751 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 753 Matcher::regName[reg_lo], offset); | |
| 754 else st->print("MOVSD [ESP + #%d],%s", | |
| 755 offset, Matcher::regName[reg_lo]); | |
| 0 | 756 } else { |
| 4759 | 757 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 758 Matcher::regName[reg_lo], offset); | |
| 759 else st->print("MOVSS [ESP + #%d],%s", | |
| 760 offset, Matcher::regName[reg_lo]); | |
| 0 | 761 } |
| 762 #endif | |
| 763 } | |
| 764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
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765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 766 return size+5+offset_size; |
| 767 } | |
| 768 | |
| 769 | |
| 770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
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771 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 772 if (cbuf) { |
| 773 MacroAssembler _masm(cbuf); | |
| 774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 776 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 777 } else { | |
| 778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 779 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 780 } | |
| 0 | 781 #ifndef PRODUCT |
| 4759 | 782 } else if (!do_size) { |
| 783 if (size != 0) st->print("\n\t"); | |
| 784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
|
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786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 787 } else { |
|
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788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 789 } |
| 4759 | 790 } else { |
| 0 | 791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 793 } else { |
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794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 795 } |
| 4759 | 796 } |
| 0 | 797 #endif |
| 798 } | |
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799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 800 // Only MOVAPS SSE prefix uses 1 byte. |
| 801 int sz = 4; | |
| 802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 804 return size + sz; | |
| 0 | 805 } |
| 806 | |
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807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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808 int src_hi, int dst_hi, int size, outputStream* st ) { |
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809 // 32-bit |
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810 if (cbuf) { |
| 4759 | 811 MacroAssembler _masm(cbuf); |
| 812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 813 as_Register(Matcher::_regEncode[src_lo])); | |
|
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814 #ifndef PRODUCT |
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815 } else if (!do_size) { |
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816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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817 #endif |
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818 } |
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819 return 4; |
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820 } |
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821 |
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822 |
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823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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824 int src_hi, int dst_hi, int size, outputStream* st ) { |
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825 // 32-bit |
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826 if (cbuf) { |
| 4759 | 827 MacroAssembler _masm(cbuf); |
| 828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 829 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
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830 #ifndef PRODUCT |
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831 } else if (!do_size) { |
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832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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833 #endif |
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834 } |
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835 return 4; |
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parents:
1579
diff
changeset
|
836 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
837 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 839 if( cbuf ) { |
| 840 emit_opcode(*cbuf, 0x8B ); | |
| 841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 842 #ifndef PRODUCT | |
| 843 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
844 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 846 #endif |
| 847 } | |
| 848 return size+2; | |
| 849 } | |
| 850 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
852 int offset, int size, outputStream* st ) { |
| 0 | 853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 854 if( cbuf ) { | |
| 855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 857 #ifndef PRODUCT | |
| 858 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
859 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
860 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 861 #endif |
| 862 } | |
| 863 size += 2; | |
| 864 } | |
| 865 | |
| 866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 867 const char *op_str; | |
| 868 int op; | |
| 869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 871 op = 0xDD; | |
| 872 } else { // 32-bit store | |
| 873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 874 op = 0xD9; | |
| 875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 876 } | |
| 877 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 879 } |
| 880 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
883 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
884 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
886 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
887 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
889 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
890 int calc_size = 0; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
893 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
894 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
895 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
896 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
897 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
898 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
899 src_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
900 dst_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
903 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
904 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
905 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
907 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
908 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
910 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
911 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
912 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
913 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
914 if (cbuf) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
915 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
916 int offset = __ offset(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
917 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
918 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
919 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
920 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
921 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
922 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
923 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
924 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
925 __ pushl(Address(rsp, src_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
926 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
927 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
928 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
929 __ movdqu(Address(rsp, -16), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
930 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
931 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
932 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
933 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
934 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
935 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
936 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
937 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
938 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
939 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
940 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
941 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
942 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
943 int size = __ offset() - offset; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
944 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
945 return size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
946 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
947 } else if (!do_size) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
948 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
949 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
951 "popl [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
952 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
956 "popq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
957 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
958 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
959 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
960 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
961 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
963 "movdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
964 "movdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
965 "movdqu xmm0, [rsp - #16]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
966 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
967 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
968 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
970 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
971 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
972 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
973 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
974 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
975 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
976 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
977 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
978 #endif |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
979 } |
|
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980 return calc_size; |
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981 } |
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982 |
| 0 | 983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 984 // Get registers to move | |
| 985 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 986 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 987 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 988 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 989 | |
| 990 enum RC src_second_rc = rc_class(src_second); | |
| 991 enum RC src_first_rc = rc_class(src_first); | |
| 992 enum RC dst_second_rc = rc_class(dst_second); | |
| 993 enum RC dst_first_rc = rc_class(dst_first); | |
| 994 | |
| 995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 996 | |
| 997 // Generate spill code! | |
| 998 int size = 0; | |
| 999 | |
| 1000 if( src_first == dst_first && src_second == dst_second ) | |
| 1001 return size; // Self copy, no move | |
| 1002 | |
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1003 if (bottom_type()->isa_vect() != NULL) { |
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1004 uint ireg = ideal_reg(); |
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1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
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1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
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1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
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1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
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1009 // mem -> mem |
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1010 int src_offset = ra_->reg2offset(src_first); |
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1011 int dst_offset = ra_->reg2offset(dst_first); |
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1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
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1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
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1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
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1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
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1016 int stack_offset = ra_->reg2offset(dst_first); |
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1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
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1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
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1019 int stack_offset = ra_->reg2offset(src_first); |
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1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
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1021 } else { |
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1022 ShouldNotReachHere(); |
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1023 } |
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1024 } |
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1025 |
| 0 | 1026 // -------------------------------------- |
| 1027 // Check for mem-mem move. push/pop to move. | |
| 1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1029 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
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1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1034 } | |
| 1035 // move low bits | |
|
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1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
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1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1041 } |
| 1042 return size; | |
| 1043 } | |
| 1044 | |
| 1045 // -------------------------------------- | |
| 1046 // Check for integer reg-reg copy | |
| 1047 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
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1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1049 |
| 1050 // Check for integer store | |
| 1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
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1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1053 |
| 1054 // Check for integer load | |
| 1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1057 |
|
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1058 // Check for integer reg-xmm reg copy |
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1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1061 "no 64 bit integer-float reg moves" ); |
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1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1063 } |
| 0 | 1064 // -------------------------------------- |
| 1065 // Check for float reg-reg copy | |
| 1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1069 if( cbuf ) { | |
| 1070 | |
| 1071 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1072 // indexing issue mentioned in a comment in the reg_def sections | |
| 1073 // for FPR registers many lines above here. | |
| 1074 | |
| 1075 if( src_first != FPR1L_num ) { | |
| 1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1080 } else { | |
| 1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1083 } | |
| 1084 #ifndef PRODUCT | |
| 1085 } else if( !do_size ) { | |
| 1086 if( size != 0 ) st->print("\n\t"); | |
| 1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1088 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1089 #endif | |
| 1090 } | |
| 1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1092 } | |
| 1093 | |
| 1094 // Check for float store | |
| 1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
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1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1097 } |
| 1098 | |
| 1099 // Check for float load | |
| 1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1101 int offset = ra_->reg2offset(src_first); | |
| 1102 const char *op_str; | |
| 1103 int op; | |
| 1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1105 op_str = "FLD_D"; | |
| 1106 op = 0xDD; | |
| 1107 } else { // 32-bit load | |
| 1108 op_str = "FLD_S"; | |
| 1109 op = 0xD9; | |
| 1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1111 } | |
| 1112 if( cbuf ) { | |
| 1113 emit_opcode (*cbuf, op ); | |
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1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1117 #ifndef PRODUCT | |
| 1118 } else if( !do_size ) { | |
| 1119 if( size != 0 ) st->print("\n\t"); | |
| 1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1121 #endif | |
| 1122 } | |
| 1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1124 return size + 3+offset_size+2; | |
| 1125 } | |
| 1126 | |
| 1127 // Check for xmm reg-reg copy | |
| 1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1130 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1131 "no non-adjacent float-moves" ); | |
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1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1133 } |
| 1134 | |
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1135 // Check for xmm reg-integer reg copy |
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1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1138 "no 64 bit float-integer reg moves" ); |
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1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1140 } |
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1141 |
| 0 | 1142 // Check for xmm store |
| 1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
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1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1145 } |
| 1146 | |
| 1147 // Check for float xmm load | |
| 1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1150 } |
| 1151 | |
| 1152 // Copy from float reg to xmm reg | |
| 1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1154 // copy to the top of stack from floating point reg | |
| 1155 // and use LEA to preserve flags | |
| 1156 if( cbuf ) { | |
| 1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1160 emit_d8(*cbuf,0xF8); | |
| 1161 #ifndef PRODUCT | |
| 1162 } else if( !do_size ) { | |
| 1163 if( size != 0 ) st->print("\n\t"); | |
| 1164 st->print("LEA ESP,[ESP-8]"); | |
| 1165 #endif | |
| 1166 } | |
| 1167 size += 4; | |
| 1168 | |
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1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1170 |
| 1171 // Copy from the temp memory to the xmm reg. | |
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1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1173 |
| 1174 if( cbuf ) { | |
| 1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1178 emit_d8(*cbuf,0x08); | |
| 1179 #ifndef PRODUCT | |
| 1180 } else if( !do_size ) { | |
| 1181 if( size != 0 ) st->print("\n\t"); | |
| 1182 st->print("LEA ESP,[ESP+8]"); | |
| 1183 #endif | |
| 1184 } | |
| 1185 size += 4; | |
| 1186 return size; | |
| 1187 } | |
| 1188 | |
| 1189 assert( size > 0, "missed a case" ); | |
| 1190 | |
| 1191 // -------------------------------------------------------------------- | |
| 1192 // Check for second bits still needing moving. | |
| 1193 if( src_second == dst_second ) | |
| 1194 return size; // Self copy; no move | |
| 1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1196 | |
| 1197 // Check for second word int-int move | |
| 1198 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1200 |
| 1201 // Check for second word integer store | |
| 1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1204 |
| 1205 // Check for second word integer load | |
| 1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1208 |
| 1209 | |
| 1210 Unimplemented(); | |
| 1211 } | |
| 1212 | |
| 1213 #ifndef PRODUCT | |
| 4950 | 1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1215 implementation( NULL, ra_, false, st ); |
| 1216 } | |
| 1217 #endif | |
| 1218 | |
| 1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1220 implementation( &cbuf, ra_, false, NULL ); | |
| 1221 } | |
| 1222 | |
| 1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1224 return implementation( NULL, ra_, true, NULL ); | |
| 1225 } | |
| 1226 | |
| 1227 | |
| 1228 //============================================================================= | |
| 1229 #ifndef PRODUCT | |
| 1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1232 int reg = ra_->get_reg_first(this); | |
| 1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1234 } | |
| 1235 #endif | |
| 1236 | |
| 1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1239 int reg = ra_->get_encode(this); | |
| 1240 if( offset >= 128 ) { | |
| 1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1242 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1244 emit_d32(cbuf, offset); | |
| 1245 } | |
| 1246 else { | |
| 1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1248 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1250 emit_d8(cbuf, offset); | |
| 1251 } | |
| 1252 } | |
| 1253 | |
| 1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1256 if( offset >= 128 ) { | |
| 1257 return 7; | |
| 1258 } | |
| 1259 else { | |
| 1260 return 4; | |
| 1261 } | |
| 1262 } | |
| 1263 | |
| 1264 //============================================================================= | |
| 1265 #ifndef PRODUCT | |
| 1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1269 st->print_cr("\tNOP"); | |
| 1270 st->print_cr("\tNOP"); | |
| 1271 if( !OptoBreakpoint ) | |
| 1272 st->print_cr("\tNOP"); | |
| 1273 } | |
| 1274 #endif | |
| 1275 | |
| 1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1277 MacroAssembler masm(&cbuf); | |
| 1278 #ifdef ASSERT | |
| 1748 | 1279 uint insts_size = cbuf.insts_size(); |
| 0 | 1280 #endif |
| 304 | 1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1282 masm.jump_cc(Assembler::notEqual, |
| 1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1284 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1285 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1286 int nops_cnt = 2; | |
| 1287 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1288 nops_cnt += 1; | |
| 1289 masm.nop(nops_cnt); | |
| 1290 | |
| 1748 | 1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1292 } |
| 1293 | |
| 1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1295 return OptoBreakpoint ? 11 : 12; | |
| 1296 } | |
| 1297 | |
| 1298 | |
| 1299 //============================================================================= | |
| 1300 uint size_exception_handler() { | |
| 1301 // NativeCall instruction size is the same as NativeJump. | |
| 1302 // exception handler starts out as jump and can be patched to | |
| 1303 // a call be deoptimization. (4932387) | |
| 1304 // Note that this value is also credited (in output.cpp) to | |
| 1305 // the size of the code section. | |
| 1306 return NativeJump::instruction_size; | |
| 1307 } | |
| 1308 | |
| 1309 // Emit exception handler code. Stuff framesize into a register | |
| 1310 // and call a VM stub routine. | |
| 1311 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1312 | |
| 1748 | 1313 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1314 // That's why we must use the macroassembler to generate a handler. |
| 1315 MacroAssembler _masm(&cbuf); | |
| 1316 address base = | |
| 1317 __ start_a_stub(size_exception_handler()); | |
| 1318 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1319 int offset = __ offset(); | |
| 1748 | 1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1322 __ end_a_stub(); | |
| 1323 return offset; | |
| 1324 } | |
| 1325 | |
| 1326 uint size_deopt_handler() { | |
| 1327 // NativeCall instruction size is the same as NativeJump. | |
| 1328 // exception handler starts out as jump and can be patched to | |
| 1329 // a call be deoptimization. (4932387) | |
| 1330 // Note that this value is also credited (in output.cpp) to | |
| 1331 // the size of the code section. | |
| 1332 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1333 } | |
| 1334 | |
| 1335 // Emit deopt handler code. | |
| 1336 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1337 | |
| 1748 | 1338 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1339 // That's why we must use the macroassembler to generate a handler. |
| 1340 MacroAssembler _masm(&cbuf); | |
| 1341 address base = | |
| 1342 __ start_a_stub(size_exception_handler()); | |
| 1343 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1344 int offset = __ offset(); | |
| 1345 InternalAddress here(__ pc()); | |
| 1346 __ pushptr(here.addr()); | |
| 1347 | |
| 1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1350 __ end_a_stub(); | |
| 1351 return offset; | |
| 1352 } | |
| 1353 | |
| 1354 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1355 return regnum - 32; // The FP registers are in the second chunk | |
| 1356 } | |
| 1357 | |
| 1358 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1359 const bool Matcher::convL2FSupported(void) { | |
| 1360 return true; | |
| 1361 } | |
| 1362 | |
| 1363 // Is this branch offset short enough that a short branch can be used? | |
| 1364 // | |
| 1365 // NOTE: If the platform does not provide any short branch variants, then | |
| 1366 // this method should return false for offset 0. | |
| 3851 | 1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1368 // The passed offset is relative to address of the branch. | |
| 1369 // On 86 a branch displacement is calculated relative to address | |
| 1370 // of a next instruction. | |
| 1371 offset -= br_size; | |
| 1372 | |
|
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1373 // the short version of jmpConUCF2 contains multiple branches, |
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1374 // making the reach slightly less |
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1375 if (rule == jmpConUCF2_rule) |
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1376 return (-126 <= offset && offset <= 125); |
| 0 | 1377 return (-128 <= offset && offset <= 127); |
| 1378 } | |
| 1379 | |
| 1380 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1382 return false; | |
| 1383 } | |
| 1384 | |
| 1385 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1386 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1387 | |
| 1388 // Threshold size for cleararray. | |
| 1389 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1390 | |
| 4047 | 1391 // Needs 2 CMOV's for longs. |
| 1392 const int Matcher::long_cmove_cost() { return 1; } | |
| 1393 | |
| 1394 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1396 | |
|
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1397 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
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1398 const bool Matcher::require_postalloc_expand = false; |
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1399 |
| 0 | 1400 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1401 // be subsumed into complex addressing expressions or compute them into | |
| 1402 // registers? True for Intel but false for most RISCs | |
| 1403 const bool Matcher::clone_shift_expressions = true; | |
| 1404 | |
|
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1405 // Do we need to mask the count passed to shift instructions or does |
|
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1406 // the cpu only look at the lower 5/6 bits anyway? |
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1407 const bool Matcher::need_masked_shift_count = false; |
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1408 |
|
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1409 bool Matcher::narrow_oop_use_complex_address() { |
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1410 ShouldNotCallThis(); |
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1411 return true; |
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1412 } |
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1413 |
|
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1414 bool Matcher::narrow_klass_use_complex_address() { |
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1415 ShouldNotCallThis(); |
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1416 return true; |
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|
1417 } |
|
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1418 |
|
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1419 |
| 0 | 1420 // Is it better to copy float constants, or load them directly from memory? |
| 1421 // Intel can load a float constant from a direct address, requiring no | |
| 1422 // extra registers. Most RISCs will have to materialize an address into a | |
| 1423 // register first, so they would do better to copy the constant from stack. | |
| 1424 const bool Matcher::rematerialize_float_constants = true; | |
| 1425 | |
| 1426 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1427 // needed. Else we split the double into 2 integer pieces and move it | |
| 1428 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1429 // Java calling convention forces doubles to be aligned. | |
| 1430 const bool Matcher::misaligned_doubles_ok = true; | |
| 1431 | |
| 1432 | |
| 1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1434 // Get the memory operand from the node | |
| 1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1438 uint opcnt = 1; // First operand | |
| 1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1440 while( idx >= skipped+num_edges ) { | |
| 1441 skipped += num_edges; | |
| 1442 opcnt++; // Bump operand count | |
| 1443 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1445 } | |
| 1446 | |
| 1447 MachOper *memory = node->_opnds[opcnt]; | |
| 1448 MachOper *new_memory = NULL; | |
| 1449 switch (memory->opcode()) { | |
| 1450 case DIRECT: | |
| 1451 case INDOFFSET32X: | |
| 1452 // No transformation necessary. | |
| 1453 return; | |
| 1454 case INDIRECT: | |
| 1455 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1456 break; | |
| 1457 case INDOFFSET8: | |
| 1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1459 break; | |
| 1460 case INDOFFSET32: | |
| 1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1462 break; | |
| 1463 case INDINDEXOFFSET: | |
| 1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1465 break; | |
| 1466 case INDINDEXSCALE: | |
| 1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1468 break; | |
| 1469 case INDINDEXSCALEOFFSET: | |
| 1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1471 break; | |
| 1472 case LOAD_LONG_INDIRECT: | |
| 1473 case LOAD_LONG_INDOFFSET32: | |
| 1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1475 return; | |
| 1476 default: | |
| 1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1478 return; | |
| 1479 } | |
| 1480 node->_opnds[opcnt] = new_memory; | |
| 1481 } | |
| 1482 | |
| 1483 // Advertise here if the CPU requires explicit rounding operations | |
| 1484 // to implement the UseStrictFP mode. | |
| 1485 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1486 | |
|
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1487 // Are floats conerted to double when stored to stack during deoptimization? |
|
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1488 // On x32 it is stored with convertion only when FPU is used for floats. |
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1489 bool Matcher::float_in_double() { return (UseSSE == 0); } |
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1490 |
| 0 | 1491 // Do ints take an entire long register or just half? |
| 1492 const bool Matcher::int_in_long = false; | |
| 1493 | |
| 1494 // Return whether or not this register is ever used as an argument. This | |
| 1495 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1496 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1497 // arguments in those registers not be available to the callee. | |
| 1498 bool Matcher::can_be_java_arg( int reg ) { | |
| 1499 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
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1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1502 return false; | |
| 1503 } | |
| 1504 | |
| 1505 bool Matcher::is_spillable_arg( int reg ) { | |
| 1506 return can_be_java_arg(reg); | |
| 1507 } | |
| 1508 | |
|
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1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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1510 // Use hardware integer DIV instruction when |
|
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1511 // it is faster than a code which use multiply. |
|
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1512 // Only when constant divisor fits into 32 bit |
|
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1513 // (min_jint is excluded to get only correct |
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1514 // positive 32 bit values from negative). |
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1515 return VM_Version::has_fast_idiv() && |
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1516 (divisor == (int)divisor && divisor != min_jint); |
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1517 } |
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1518 |
| 0 | 1519 // Register for DIVI projection of divmodI |
| 1520 RegMask Matcher::divI_proj_mask() { | |
|
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1521 return EAX_REG_mask(); |
| 0 | 1522 } |
| 1523 | |
| 1524 // Register for MODI projection of divmodI | |
| 1525 RegMask Matcher::modI_proj_mask() { | |
|
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1526 return EDX_REG_mask(); |
| 0 | 1527 } |
| 1528 | |
| 1529 // Register for DIVL projection of divmodL | |
| 1530 RegMask Matcher::divL_proj_mask() { | |
| 1531 ShouldNotReachHere(); | |
| 1532 return RegMask(); | |
| 1533 } | |
| 1534 | |
| 1535 // Register for MODL projection of divmodL | |
| 1536 RegMask Matcher::modL_proj_mask() { | |
| 1537 ShouldNotReachHere(); | |
| 1538 return RegMask(); | |
| 1539 } | |
| 1540 | |
|
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1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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1542 return EBP_REG_mask(); |
|
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1543 } |
|
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1544 |
|
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1545 // Returns true if the high 32 bits of the value is known to be zero. |
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1546 bool is_operand_hi32_zero(Node* n) { |
|
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1547 int opc = n->Opcode(); |
|
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1548 if (opc == Op_AndL) { |
|
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1549 Node* o2 = n->in(2); |
|
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1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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1551 return true; |
|
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|
1552 } |
|
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1553 } |
|
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1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
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1555 return true; |
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1556 } |
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1557 return false; |
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1558 } |
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1559 |
| 0 | 1560 %} |
| 1561 | |
| 1562 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1563 // This block specifies the encoding classes used by the compiler to output | |
| 1564 // byte streams. Encoding classes generate functions which are called by | |
| 1565 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1566 // instruction. Operands specify their base encoding interface with the | |
| 1567 // interface keyword. There are currently supported four interfaces, | |
| 1568 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1569 // operand to generate a function which returns its register number when | |
| 1570 // queried. CONST_INTER causes an operand to generate a function which | |
| 1571 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1572 // operand to generate four functions which return the Base Register, the | |
| 1573 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1574 // queried. COND_INTER causes an operand to generate six functions which | |
| 1575 // return the encoding code (ie - encoding bits for the instruction) | |
| 1576 // associated with each basic boolean condition for a conditional instruction. | |
| 1577 // Instructions specify two basic values for encoding. They use the | |
| 1578 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1579 // the class names specified in the encoding block), and they use the | |
| 1580 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1581 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1582 // needs for encoding need to be specified. | |
| 1583 encode %{ | |
| 1584 // Build emit functions for each basic byte or larger field in the intel | |
| 1585 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1586 // code in the enc_class source block. Emit functions will live in the | |
| 1587 // main source block for now. In future, we can generalize this by | |
| 1588 // adding a syntax that specifies the sizes of fields in an order, | |
| 1589 // so that the adlc can build the emit functions automagically | |
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1590 |
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1591 // Emit primary opcode |
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1592 enc_class OpcP %{ |
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1593 emit_opcode(cbuf, $primary); |
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1594 %} |
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1595 |
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1596 // Emit secondary opcode |
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1597 enc_class OpcS %{ |
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1598 emit_opcode(cbuf, $secondary); |
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1599 %} |
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1600 |
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1601 // Emit opcode directly |
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1602 enc_class Opcode(immI d8) %{ |
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1603 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1604 %} |
| 1605 | |
| 1606 enc_class SizePrefix %{ | |
| 1607 emit_opcode(cbuf,0x66); | |
| 1608 %} | |
| 1609 | |
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1610 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1611 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1612 %} | |
| 1613 | |
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1614 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1615 emit_opcode(cbuf,$opcode$$constant); |
| 1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1617 %} | |
| 1618 | |
|
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1619 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1620 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1621 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1622 %} | |
| 1623 | |
| 1624 enc_class cdq_enc %{ | |
| 1625 // Full implementation of Java idiv and irem; checks for | |
| 1626 // special case as described in JVM spec., p.243 & p.271. | |
| 1627 // | |
| 1628 // normal case special case | |
| 1629 // | |
| 1630 // input : rax,: dividend min_int | |
| 1631 // reg: divisor -1 | |
| 1632 // | |
| 1633 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1634 // rdx: remainder (= rax, irem reg) 0 | |
| 1635 // | |
| 1636 // Code sequnce: | |
| 1637 // | |
| 1638 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1639 // 0F 85 0B 00 00 00 jne normal_case | |
| 1640 // 33 D2 xor rdx,edx | |
| 1641 // 83 F9 FF cmp rcx,0FFh | |
| 1642 // 0F 84 03 00 00 00 je done | |
| 1643 // normal_case: | |
| 1644 // 99 cdq | |
| 1645 // F7 F9 idiv rax,ecx | |
| 1646 // done: | |
| 1647 // | |
| 1648 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1649 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1651 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1652 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1653 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1654 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1655 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1657 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1659 // normal_case: | |
| 1660 emit_opcode(cbuf,0x99); // cdq | |
| 1661 // idiv (note: must be emitted by the user of this rule) | |
| 1662 // normal: | |
| 1663 %} | |
| 1664 | |
| 1665 // Dense encoding for older common ops | |
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1666 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1667 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1668 %} | |
| 1669 | |
| 1670 | |
| 1671 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1672 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1673 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1675 emit_opcode(cbuf, $primary | 0x02); | |
| 1676 } | |
| 1677 else { // If 32-bit immediate | |
| 1678 emit_opcode(cbuf, $primary); | |
| 1679 } | |
| 1680 %} | |
| 1681 | |
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1682 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1683 // Emit primary opcode and set sign-extend bit |
| 1684 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1686 emit_opcode(cbuf, $primary | 0x02); } | |
| 1687 else { // If 32-bit immediate | |
| 1688 emit_opcode(cbuf, $primary); | |
| 1689 } | |
| 1690 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1691 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1692 %} | |
| 1693 | |
| 1694 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1695 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1697 $$$emit8$imm$$constant; | |
| 1698 } | |
| 1699 else { // If 32-bit immediate | |
| 1700 // Output immediate | |
| 1701 $$$emit32$imm$$constant; | |
| 1702 } | |
| 1703 %} | |
| 1704 | |
| 1705 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1706 // Emit primary opcode and set sign-extend bit | |
| 1707 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1708 int con = (int)$imm$$constant; // Throw away top bits | |
| 1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1710 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1711 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1713 else emit_d32(cbuf,con); | |
| 1714 %} | |
| 1715 | |
| 1716 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1717 // Emit primary opcode and set sign-extend bit | |
| 1718 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1719 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1721 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1722 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1724 else emit_d32(cbuf,con); | |
| 1725 %} | |
| 1726 | |
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1727 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1728 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1729 %} | |
| 1730 | |
| 1731 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1732 int destlo = $dst$$reg; | |
| 1733 int desthi = HIGH_FROM_LOW(destlo); | |
| 1734 // bswap lo | |
| 1735 emit_opcode(cbuf, 0x0F); | |
| 1736 emit_cc(cbuf, 0xC8, destlo); | |
| 1737 // bswap hi | |
| 1738 emit_opcode(cbuf, 0x0F); | |
| 1739 emit_cc(cbuf, 0xC8, desthi); | |
| 1740 // xchg lo and hi | |
| 1741 emit_opcode(cbuf, 0x87); | |
| 1742 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1743 %} | |
| 1744 | |
|
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1745 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1746 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1747 %} | |
| 1748 | |
| 1749 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1750 $$$emit8$primary; | |
| 1751 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1752 %} | |
| 1753 | |
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1754 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1755 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1756 emit_d8(cbuf, op >> 8 ); | |
| 1757 emit_d8(cbuf, op & 255); | |
| 1758 %} | |
| 1759 | |
| 1760 // emulate a CMOV with a conditional branch around a MOV | |
| 1761 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1762 // Invert sense of branch from sense of CMOV | |
| 1763 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1764 emit_d8( cbuf, $brOffs$$constant ); | |
| 1765 %} | |
| 1766 | |
| 1767 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1768 Register Redi = as_Register(EDI_enc); // result register | |
| 1769 Register Reax = as_Register(EAX_enc); // super class | |
| 1770 Register Recx = as_Register(ECX_enc); // killed | |
| 1771 Register Resi = as_Register(ESI_enc); // sub class | |
|
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1772 Label miss; |
| 0 | 1773 |
| 1774 MacroAssembler _masm(&cbuf); | |
|
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1775 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1776 NULL, &miss, |
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1777 /*set_cond_codes:*/ true); |
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1778 if ($primary) { |
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1779 __ xorptr(Redi, Redi); |
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1780 } |
| 0 | 1781 __ bind(miss); |
| 1782 %} | |
| 1783 | |
| 1784 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1785 MacroAssembler masm(&cbuf); | |
| 1786 int start = masm.offset(); | |
| 1787 if (UseSSE >= 2) { | |
| 1788 if (VerifyFPU) { | |
| 1789 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1790 } | |
| 1791 } else { | |
| 1792 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1793 // Compiled code leaves it dirty. Do cleanup now. | |
| 1794 masm.empty_FPU_stack(); | |
| 1795 } | |
| 1796 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1797 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1798 } else { | |
| 1799 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1800 } | |
| 1801 %} | |
| 1802 | |
| 1803 enc_class Verify_FPU_For_Leaf %{ | |
| 1804 if( VerifyFPU ) { | |
| 1805 MacroAssembler masm(&cbuf); | |
| 1806 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1807 } | |
| 1808 %} | |
| 1809 | |
| 1810 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1811 // This is the instruction starting address for relocation info. | |
| 1748 | 1812 cbuf.set_insts_mark(); |
| 0 | 1813 $$$emit8$primary; |
| 1814 // CALL directly to the runtime | |
| 1748 | 1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1816 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1817 | |
| 1818 if (UseSSE >= 2) { | |
| 1819 MacroAssembler _masm(&cbuf); | |
| 1820 BasicType rt = tf()->return_type(); | |
| 1821 | |
| 1822 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1823 // A C runtime call where the return value is unused. In SSE2+ | |
| 1824 // mode the result needs to be removed from the FPU stack. It's | |
| 1825 // likely that this function call could be removed by the | |
| 1826 // optimizer if the C function is a pure function. | |
| 1827 __ ffree(0); | |
| 1828 } else if (rt == T_FLOAT) { | |
| 304 | 1829 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1830 __ fstp_s(Address(rsp, 0)); |
| 1831 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1832 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1833 } else if (rt == T_DOUBLE) { |
| 304 | 1834 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1835 __ fstp_d(Address(rsp, 0)); |
| 1836 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1837 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1838 } |
| 1839 } | |
| 1840 %} | |
| 1841 | |
| 1842 | |
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1843 enc_class pre_call_resets %{ |
| 0 | 1844 // If method sets FPU control word restore it here |
| 1748 | 1845 debug_only(int off0 = cbuf.insts_size()); |
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1846 if (ra_->C->in_24_bit_fp_mode()) { |
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1847 MacroAssembler _masm(&cbuf); |
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1848 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
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1849 } |
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1850 if (ra_->C->max_vector_size() > 16) { |
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1851 // Clear upper bits of YMM registers when current compiled code uses |
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1852 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1853 MacroAssembler _masm(&cbuf); |
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1854 __ vzeroupper(); |
| 0 | 1855 } |
| 1748 | 1856 debug_only(int off1 = cbuf.insts_size()); |
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1857 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1858 %} |
| 1859 | |
| 1860 enc_class post_call_FPU %{ | |
| 1861 // If method sets FPU control word do it here also | |
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1862 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1863 MacroAssembler masm(&cbuf); |
| 1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1865 } | |
| 1866 %} | |
| 1867 | |
| 1868 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1869 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1870 // who we intended to call. | |
| 1748 | 1871 cbuf.set_insts_mark(); |
| 0 | 1872 $$$emit8$primary; |
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1873 if (!_method) { |
| 1748 | 1874 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1875 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
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1876 } else if (_optimized_virtual) { |
| 1748 | 1877 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1878 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1879 } else { | |
| 1748 | 1880 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1881 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1882 } | |
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1883 if (_method) { // Emit stub for static call. |
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1884 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 1885 } |
| 1886 %} | |
| 1887 | |
| 1888 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1889 MacroAssembler _masm(&cbuf); |
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1890 __ ic_call((address)$meth$$method); |
| 0 | 1891 %} |
| 1892 | |
| 1893 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1894 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1895 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1896 | |
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1897 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1898 cbuf.set_insts_mark(); |
| 0 | 1899 $$$emit8$primary; |
| 1900 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1901 emit_d8(cbuf, disp); // Displacement | |
| 1902 | |
| 1903 %} | |
| 1904 | |
| 1905 // Following encoding is no longer used, but may be restored if calling | |
| 1906 // convention changes significantly. | |
| 1907 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1908 // | |
| 1909 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1910 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1911 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1912 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1913 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1914 // | |
| 1915 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1916 // // // so we load it immediately before the call | |
| 1917 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1918 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1919 // | |
| 1920 // // xor rbp,ebp | |
| 1921 // emit_opcode(cbuf, 0x33); | |
| 1922 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1923 // | |
| 1924 // // CALL to interpreter. | |
| 1748 | 1925 // cbuf.set_insts_mark(); |
| 0 | 1926 // $$$emit8$primary; |
| 1748 | 1927 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1928 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1929 // %} | |
| 1930 | |
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1931 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1932 $$$emit8$primary; |
| 1933 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1934 $$$emit8$shift$$constant; | |
| 1935 %} | |
| 1936 | |
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1937 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1938 // Load immediate does not have a zero or sign extended version |
| 1939 // for 8-bit immediates | |
| 1940 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1941 $$$emit32$src$$constant; | |
| 1942 %} | |
| 1943 | |
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1944 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1945 // Load immediate does not have a zero or sign extended version |
| 1946 // for 8-bit immediates | |
| 1947 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1948 $$$emit32$src$$constant; | |
| 1949 %} | |
| 1950 | |
| 1951 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1952 // Load immediate does not have a zero or sign extended version | |
| 1953 // for 8-bit immediates | |
| 1954 int dst_enc = $dst$$reg; | |
| 1955 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1956 if (src_con == 0) { | |
| 1957 // xor dst, dst | |
| 1958 emit_opcode(cbuf, 0x33); | |
| 1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1960 } else { | |
| 1961 emit_opcode(cbuf, $primary + dst_enc); | |
| 1962 emit_d32(cbuf, src_con); | |
| 1963 } | |
| 1964 %} | |
| 1965 | |
| 1966 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1967 // Load immediate does not have a zero or sign extended version | |
| 1968 // for 8-bit immediates | |
| 1969 int dst_enc = $dst$$reg + 2; | |
| 1970 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1971 if (src_con == 0) { | |
| 1972 // xor dst, dst | |
| 1973 emit_opcode(cbuf, 0x33); | |
| 1974 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1975 } else { | |
| 1976 emit_opcode(cbuf, $primary + dst_enc); | |
| 1977 emit_d32(cbuf, src_con); | |
| 1978 } | |
| 1979 %} | |
| 1980 | |
| 1981 | |
| 1982 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1983 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1984 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1985 %} | |
| 1986 | |
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1987 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1988 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1989 %} | |
| 1990 | |
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1991 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1993 %} | |
| 1994 | |
| 1995 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1996 $$$emit8$primary; | |
| 1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1998 %} | |
| 1999 | |
| 2000 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2001 $$$emit8$secondary; | |
| 2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2003 %} | |
| 2004 | |
| 2005 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2006 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2007 %} | |
| 2008 | |
| 2009 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2010 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2011 %} | |
| 2012 | |
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2013 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 2014 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2015 %} | |
| 2016 | |
| 2017 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2018 // Output immediate | |
| 2019 $$$emit32$src$$constant; | |
| 2020 %} | |
| 2021 | |
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2022 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2023 // Output Float immediate bits |
| 2024 jfloat jf = $src$$constant; | |
| 2025 int jf_as_bits = jint_cast( jf ); | |
| 2026 emit_d32(cbuf, jf_as_bits); | |
| 2027 %} | |
| 2028 | |
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2029 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2030 // Output Float immediate bits |
| 2031 jfloat jf = $src$$constant; | |
| 2032 int jf_as_bits = jint_cast( jf ); | |
| 2033 emit_d32(cbuf, jf_as_bits); | |
| 2034 %} | |
| 2035 | |
| 2036 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2037 // Output immediate | |
| 2038 $$$emit16$src$$constant; | |
| 2039 %} | |
| 2040 | |
| 2041 enc_class Con_d32(immI src) %{ | |
| 2042 emit_d32(cbuf,$src$$constant); | |
| 2043 %} | |
| 2044 | |
| 2045 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2046 // Output immediate memory reference | |
| 2047 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2048 emit_d32(cbuf, 0x00); | |
| 2049 %} | |
| 2050 | |
| 2051 enc_class lock_prefix( ) %{ | |
| 2052 if( os::is_MP() ) | |
| 2053 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2054 %} | |
| 2055 | |
| 2056 // Cmp-xchg long value. | |
| 2057 // Note: we need to swap rbx, and rcx before and after the | |
| 2058 // cmpxchg8 instruction because the instruction uses | |
| 2059 // rcx as the high order word of the new value to store but | |
| 2060 // our register encoding uses rbx,. | |
| 2061 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2062 | |
| 2063 // XCHG rbx,ecx | |
| 2064 emit_opcode(cbuf,0x87); | |
| 2065 emit_opcode(cbuf,0xD9); | |
| 2066 // [Lock] | |
| 2067 if( os::is_MP() ) | |
| 2068 emit_opcode(cbuf,0xF0); | |
| 2069 // CMPXCHG8 [Eptr] | |
| 2070 emit_opcode(cbuf,0x0F); | |
| 2071 emit_opcode(cbuf,0xC7); | |
| 2072 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2073 // XCHG rbx,ecx | |
| 2074 emit_opcode(cbuf,0x87); | |
| 2075 emit_opcode(cbuf,0xD9); | |
| 2076 %} | |
| 2077 | |
| 2078 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2079 // [Lock] | |
| 2080 if( os::is_MP() ) | |
| 2081 emit_opcode(cbuf,0xF0); | |
| 2082 | |
| 2083 // CMPXCHG [Eptr] | |
| 2084 emit_opcode(cbuf,0x0F); | |
| 2085 emit_opcode(cbuf,0xB1); | |
| 2086 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2087 %} | |
| 2088 | |
| 2089 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2090 int res_encoding = $res$$reg; | |
| 2091 | |
| 2092 // MOV res,0 | |
| 2093 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2094 emit_d32( cbuf, 0 ); | |
| 2095 // JNE,s fail | |
| 2096 emit_opcode(cbuf,0x75); | |
| 2097 emit_d8(cbuf, 5 ); | |
| 2098 // MOV res,1 | |
| 2099 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2100 emit_d32( cbuf, 1 ); | |
| 2101 // fail: | |
| 2102 %} | |
| 2103 | |
| 2104 enc_class set_instruction_start( ) %{ | |
| 1748 | 2105 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2106 %} |
| 2107 | |
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2108 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2109 int reg_encoding = $ereg$$reg; |
| 2110 int base = $mem$$base; | |
| 2111 int index = $mem$$index; | |
| 2112 int scale = $mem$$scale; | |
| 2113 int displace = $mem$$disp; | |
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2114 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2115 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2116 %} |
| 2117 | |
| 2118 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2119 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2120 int base = $mem$$base; | |
| 2121 int index = $mem$$index; | |
| 2122 int scale = $mem$$scale; | |
| 2123 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2124 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2125 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2126 %} |
| 2127 | |
| 2128 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2129 int r1, r2; | |
| 2130 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2131 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2132 emit_opcode(cbuf,0x0F); | |
| 2133 emit_opcode(cbuf,$tertiary); | |
| 2134 emit_rm(cbuf, 0x3, r1, r2); | |
| 2135 emit_d8(cbuf,$cnt$$constant); | |
| 2136 emit_d8(cbuf,$primary); | |
| 2137 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2138 emit_d8(cbuf,$cnt$$constant); | |
| 2139 %} | |
| 2140 | |
| 2141 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2142 emit_opcode( cbuf, 0x8B ); // Move | |
| 2143 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2144 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2145 emit_d8(cbuf,$primary); |
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2146 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2147 emit_d8(cbuf,$cnt$$constant-32); |
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2148 } |
| 0 | 2149 emit_d8(cbuf,$primary); |
| 2150 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2151 emit_d8(cbuf,31); | |
| 2152 %} | |
| 2153 | |
| 2154 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2155 int r1, r2; | |
| 2156 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2157 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2158 | |
| 2159 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2160 emit_rm(cbuf, 0x3, r1, r2); | |
| 2161 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2162 emit_opcode(cbuf,$primary); | |
| 2163 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2164 emit_d8(cbuf,$cnt$$constant-32); | |
| 2165 } | |
| 2166 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2167 emit_rm(cbuf, 0x3, r2, r2); | |
| 2168 %} | |
| 2169 | |
| 2170 // Clone of RegMem but accepts an extra parameter to access each | |
| 2171 // half of a double in memory; it never needs relocation info. | |
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2172 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2173 emit_opcode(cbuf,$opcode$$constant); |
| 2174 int reg_encoding = $rm_reg$$reg; | |
| 2175 int base = $mem$$base; | |
| 2176 int index = $mem$$index; | |
| 2177 int scale = $mem$$scale; | |
| 2178 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2179 relocInfo::relocType disp_reloc = relocInfo::none; |
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2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2181 %} |
| 2182 | |
| 2183 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2184 // | |
| 2185 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2186 // and it never needs relocation information. | |
| 2187 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2188 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2189 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2190 int base = $mem$$base; | |
| 2191 int index = $mem$$index; | |
| 2192 int scale = $mem$$scale; | |
| 2193 int displace = $mem$$disp; | |
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2194 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2195 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2196 %} |
| 2197 | |
| 2198 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2199 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2200 int base = $mem$$base; | |
| 2201 int index = $mem$$index; | |
| 2202 int scale = $mem$$scale; | |
| 2203 int displace = $mem$$disp; | |
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2204 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2205 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2206 %} |
| 2207 | |
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2208 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2209 int reg_encoding = $dst$$reg; |
| 2210 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2211 int index = 0x04; // 0x04 indicates no index | |
| 2212 int scale = 0x00; // 0x00 indicates no scale | |
| 2213 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2214 relocInfo::relocType disp_reloc = relocInfo::none; |
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2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2216 %} |
| 2217 | |
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2218 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2219 // Compare dst,src |
| 2220 emit_opcode(cbuf,0x3B); | |
| 2221 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2222 // jmp dst < src around move | |
| 2223 emit_opcode(cbuf,0x7C); | |
| 2224 emit_d8(cbuf,2); | |
| 2225 // move dst,src | |
| 2226 emit_opcode(cbuf,0x8B); | |
| 2227 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2228 %} | |
| 2229 | |
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2230 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2231 // Compare dst,src |
| 2232 emit_opcode(cbuf,0x3B); | |
| 2233 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2234 // jmp dst > src around move | |
| 2235 emit_opcode(cbuf,0x7F); | |
| 2236 emit_d8(cbuf,2); | |
| 2237 // move dst,src | |
| 2238 emit_opcode(cbuf,0x8B); | |
| 2239 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2240 %} | |
| 2241 | |
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2242 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2243 // If src is FPR1, we can just FST to store it. |
| 2244 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2245 int reg_encoding = 0x2; // Just store | |
| 2246 int base = $mem$$base; | |
| 2247 int index = $mem$$index; | |
| 2248 int scale = $mem$$scale; | |
| 2249 int displace = $mem$$disp; | |
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2250 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2251 if( $src$$reg != FPR1L_enc ) { |
| 2252 reg_encoding = 0x3; // Store & pop | |
| 2253 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2254 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2255 } | |
| 1748 | 2256 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2257 emit_opcode(cbuf,$primary); |
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2258 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2259 %} |
| 2260 | |
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2261 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2262 // NEG $dst |
| 2263 emit_opcode(cbuf,0xF7); | |
| 2264 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2265 %} | |
| 2266 | |
| 2267 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2268 // SETLT $dst | |
| 2269 emit_opcode(cbuf,0x0F); | |
| 2270 emit_opcode(cbuf,0x9C); | |
| 2271 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2272 %} | |
| 2273 | |
| 2274 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2275 int tmpReg = $tmp$$reg; | |
| 2276 | |
| 2277 // SUB $p,$q | |
| 2278 emit_opcode(cbuf,0x2B); | |
| 2279 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2280 // SBB $tmp,$tmp | |
| 2281 emit_opcode(cbuf,0x1B); | |
| 2282 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2283 // AND $tmp,$y | |
| 2284 emit_opcode(cbuf,0x23); | |
| 2285 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2286 // ADD $p,$tmp | |
| 2287 emit_opcode(cbuf,0x03); | |
| 2288 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2289 %} | |
| 2290 | |
| 2291 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2292 // TEST shift,32 | |
| 2293 emit_opcode(cbuf,0xF7); | |
| 2294 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2295 emit_d32(cbuf,0x20); | |
| 2296 // JEQ,s small | |
| 2297 emit_opcode(cbuf, 0x74); | |
| 2298 emit_d8(cbuf, 0x04); | |
| 2299 // MOV $dst.hi,$dst.lo | |
| 2300 emit_opcode( cbuf, 0x8B ); | |
| 2301 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2302 // CLR $dst.lo | |
| 2303 emit_opcode(cbuf, 0x33); | |
| 2304 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2305 // small: | |
| 2306 // SHLD $dst.hi,$dst.lo,$shift | |
| 2307 emit_opcode(cbuf,0x0F); | |
| 2308 emit_opcode(cbuf,0xA5); | |
| 2309 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2310 // SHL $dst.lo,$shift" | |
| 2311 emit_opcode(cbuf,0xD3); | |
| 2312 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2313 %} | |
| 2314 | |
| 2315 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2316 // TEST shift,32 | |
| 2317 emit_opcode(cbuf,0xF7); | |
| 2318 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2319 emit_d32(cbuf,0x20); | |
| 2320 // JEQ,s small | |
| 2321 emit_opcode(cbuf, 0x74); | |
| 2322 emit_d8(cbuf, 0x04); | |
| 2323 // MOV $dst.lo,$dst.hi | |
| 2324 emit_opcode( cbuf, 0x8B ); | |
| 2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2326 // CLR $dst.hi | |
| 2327 emit_opcode(cbuf, 0x33); | |
| 2328 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2329 // small: | |
| 2330 // SHRD $dst.lo,$dst.hi,$shift | |
| 2331 emit_opcode(cbuf,0x0F); | |
| 2332 emit_opcode(cbuf,0xAD); | |
| 2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2334 // SHR $dst.hi,$shift" | |
| 2335 emit_opcode(cbuf,0xD3); | |
| 2336 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2337 %} | |
| 2338 | |
| 2339 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2340 // TEST shift,32 | |
| 2341 emit_opcode(cbuf,0xF7); | |
| 2342 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2343 emit_d32(cbuf,0x20); | |
| 2344 // JEQ,s small | |
| 2345 emit_opcode(cbuf, 0x74); | |
| 2346 emit_d8(cbuf, 0x05); | |
| 2347 // MOV $dst.lo,$dst.hi | |
| 2348 emit_opcode( cbuf, 0x8B ); | |
| 2349 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2350 // SAR $dst.hi,31 | |
| 2351 emit_opcode(cbuf, 0xC1); | |
| 2352 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2353 emit_d8(cbuf, 0x1F ); | |
| 2354 // small: | |
| 2355 // SHRD $dst.lo,$dst.hi,$shift | |
| 2356 emit_opcode(cbuf,0x0F); | |
| 2357 emit_opcode(cbuf,0xAD); | |
| 2358 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2359 // SAR $dst.hi,$shift" | |
| 2360 emit_opcode(cbuf,0xD3); | |
| 2361 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2362 %} | |
| 2363 | |
| 2364 | |
| 2365 // ----------------- Encodings for floating point unit ----------------- | |
| 2366 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2367 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2368 $$$emit8$primary; |
| 2369 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2370 %} | |
| 2371 | |
| 2372 // Pop argument in FPR0 with FSTP ST(0) | |
| 2373 enc_class PopFPU() %{ | |
| 2374 emit_opcode( cbuf, 0xDD ); | |
| 2375 emit_d8( cbuf, 0xD8 ); | |
| 2376 %} | |
| 2377 | |
| 2378 // !!!!! equivalent to Pop_Reg_F | |
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2379 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2380 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2381 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2382 %} | |
| 2383 | |
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2384 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2385 emit_opcode( cbuf, 0xD9 ); |
| 2386 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2387 %} | |
| 2388 | |
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2389 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2390 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2391 emit_opcode( cbuf, 0x2D ); | |
| 2392 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2393 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2394 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2395 %} | |
| 2396 | |
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2397 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2398 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2399 emit_opcode( cbuf, 0x2D ); | |
| 2400 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2401 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2402 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2403 %} | |
| 2404 | |
| 2405 // Special case for moving an integer register to a stack slot. | |
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2406 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2407 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2408 %} | |
| 2409 | |
| 2410 // Special case for moving a register to a stack slot. | |
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2411 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2412 // Opcode already emitted |
| 2413 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2414 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2415 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2416 %} | |
| 2417 | |
| 2418 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2419 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2420 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2421 %} | |
| 2422 | |
| 2423 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2424 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2425 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2426 %} | |
| 2427 | |
| 2428 // Same as Pop_Mem_F except for opcode | |
| 2429 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2430 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2431 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2432 %} | |
| 2433 | |
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2434 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2435 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2436 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2437 %} | |
| 2438 | |
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2439 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2440 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2441 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2442 %} | |
| 2443 | |
| 2444 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2445 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2446 int pop = 0x02; |
| 2447 if ($src$$reg != FPR1L_enc) { | |
| 2448 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2449 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2450 pop = 0x03; | |
| 2451 } | |
| 2452 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2453 %} | |
| 2454 | |
| 2455 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2456 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2457 int pop = 0x02; |
| 2458 if ($src$$reg != FPR1L_enc) { | |
| 2459 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2460 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2461 pop = 0x03; | |
| 2462 } | |
| 2463 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2464 %} | |
| 2465 | |
| 2466 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2467 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2468 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2469 if ($src$$reg != FPR1L_enc) { | |
| 2470 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2471 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2472 pop = 0xD8; | |
| 2473 } | |
| 2474 emit_opcode( cbuf, 0xDD ); | |
| 2475 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2476 %} | |
| 2477 | |
| 2478 | |
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2479 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2480 // load dst in FPR0 |
| 2481 emit_opcode( cbuf, 0xD9 ); | |
| 2482 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2483 if ($src$$reg != FPR1L_enc) { | |
| 2484 // fincstp | |
| 2485 emit_opcode (cbuf, 0xD9); | |
| 2486 emit_opcode (cbuf, 0xF7); | |
| 2487 // swap src with FPR1: | |
| 2488 // FXCH FPR1 with src | |
| 2489 emit_opcode(cbuf, 0xD9); | |
| 2490 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2491 // fdecstp | |
| 2492 emit_opcode (cbuf, 0xD9); | |
| 2493 emit_opcode (cbuf, 0xF6); | |
| 2494 } | |
| 2495 %} | |
| 2496 | |
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2497 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2498 MacroAssembler _masm(&cbuf); |
| 2499 __ subptr(rsp, 8); | |
| 2500 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2501 __ fld_d(Address(rsp, 0)); | |
| 2502 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2503 __ fld_d(Address(rsp, 0)); | |
| 2504 %} | |
| 2505 | |
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2506 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2507 MacroAssembler _masm(&cbuf); |
| 2508 __ subptr(rsp, 4); | |
| 2509 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2510 __ fld_s(Address(rsp, 0)); | |
| 2511 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2512 __ fld_s(Address(rsp, 0)); | |
| 0 | 2513 %} |
| 2514 | |
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2515 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2516 MacroAssembler _masm(&cbuf); |
| 2517 __ fstp_d(Address(rsp, 0)); | |
| 2518 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2519 __ addptr(rsp, 8); | |
| 0 | 2520 %} |
| 2521 | |
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2522 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2523 MacroAssembler _masm(&cbuf); |
| 2524 __ fstp_s(Address(rsp, 0)); | |
| 2525 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2526 __ addptr(rsp, $d8$$constant); | |
| 0 | 2527 %} |
| 2528 | |
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2529 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2530 MacroAssembler _masm(&cbuf); |
| 2531 __ subptr(rsp, 8); | |
| 2532 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2533 __ fld_d(Address(rsp, 0)); | |
| 0 | 2534 %} |
| 2535 | |
| 2536 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2537 MacroAssembler _masm(&cbuf); |
| 2538 __ subptr(rsp, 8); | |
| 0 | 2539 %} |
| 2540 | |
| 2541 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2542 MacroAssembler _masm(&cbuf); |
| 2543 __ addptr(rsp, 8); | |
| 2544 %} | |
| 2545 | |
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2546 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2547 MacroAssembler _masm(&cbuf); |
| 2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2549 __ fld_d(Address(rsp, 0)); | |
| 0 | 2550 %} |
| 2551 | |
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2552 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2553 if ($src$$reg != FPR1L_enc) { |
| 2554 // fincstp | |
| 2555 emit_opcode (cbuf, 0xD9); | |
| 2556 emit_opcode (cbuf, 0xF7); | |
| 2557 // FXCH FPR1 with src | |
| 2558 emit_opcode(cbuf, 0xD9); | |
| 2559 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2560 // fdecstp | |
| 2561 emit_opcode (cbuf, 0xD9); | |
| 2562 emit_opcode (cbuf, 0xF6); | |
| 2563 } | |
| 2564 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2565 // // FSTP FPR$dst$$reg | |
| 2566 // emit_opcode( cbuf, 0xDD ); | |
| 2567 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2568 %} | |
| 2569 | |
| 2570 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2571 // fnstsw ax | |
| 2572 emit_opcode( cbuf, 0xDF ); | |
| 2573 emit_opcode( cbuf, 0xE0 ); | |
| 2574 // sahf | |
| 2575 emit_opcode( cbuf, 0x9E ); | |
| 2576 // jnp ::skip | |
| 2577 emit_opcode( cbuf, 0x7B ); | |
| 2578 emit_opcode( cbuf, 0x05 ); | |
| 2579 %} | |
| 2580 | |
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2581 enc_class emitModDPR() %{ |
| 0 | 2582 // fprem must be iterative |
| 2583 // :: loop | |
| 2584 // fprem | |
| 2585 emit_opcode( cbuf, 0xD9 ); | |
| 2586 emit_opcode( cbuf, 0xF8 ); | |
| 2587 // wait | |
| 2588 emit_opcode( cbuf, 0x9b ); | |
| 2589 // fnstsw ax | |
| 2590 emit_opcode( cbuf, 0xDF ); | |
| 2591 emit_opcode( cbuf, 0xE0 ); | |
| 2592 // sahf | |
| 2593 emit_opcode( cbuf, 0x9E ); | |
| 2594 // jp ::loop | |
| 2595 emit_opcode( cbuf, 0x0F ); | |
| 2596 emit_opcode( cbuf, 0x8A ); | |
| 2597 emit_opcode( cbuf, 0xF4 ); | |
| 2598 emit_opcode( cbuf, 0xFF ); | |
| 2599 emit_opcode( cbuf, 0xFF ); | |
| 2600 emit_opcode( cbuf, 0xFF ); | |
| 2601 %} | |
| 2602 | |
| 2603 enc_class fpu_flags() %{ | |
| 2604 // fnstsw_ax | |
| 2605 emit_opcode( cbuf, 0xDF); | |
| 2606 emit_opcode( cbuf, 0xE0); | |
| 2607 // test ax,0x0400 | |
| 2608 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2609 emit_opcode( cbuf, 0xA9 ); | |
| 2610 emit_d16 ( cbuf, 0x0400 ); | |
| 2611 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2612 // // test rax,0x0400 | |
| 2613 // emit_opcode( cbuf, 0xA9 ); | |
| 2614 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2615 // | |
| 2616 // jz exit (no unordered comparison) | |
| 2617 emit_opcode( cbuf, 0x74 ); | |
| 2618 emit_d8 ( cbuf, 0x02 ); | |
| 2619 // mov ah,1 - treat as LT case (set carry flag) | |
| 2620 emit_opcode( cbuf, 0xB4 ); | |
| 2621 emit_d8 ( cbuf, 0x01 ); | |
| 2622 // sahf | |
| 2623 emit_opcode( cbuf, 0x9E); | |
| 2624 %} | |
| 2625 | |
| 2626 enc_class cmpF_P6_fixup() %{ | |
| 2627 // Fixup the integer flags in case comparison involved a NaN | |
| 2628 // | |
| 2629 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2630 emit_opcode( cbuf, 0x7B ); | |
| 2631 emit_d8 ( cbuf, 0x03 ); | |
| 2632 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2633 emit_opcode( cbuf, 0xB4 ); | |
| 2634 emit_d8 ( cbuf, 0x01 ); | |
| 2635 // SAHF | |
| 2636 emit_opcode( cbuf, 0x9E); | |
| 2637 // NOP // target for branch to avoid branch to branch | |
| 2638 emit_opcode( cbuf, 0x90); | |
| 2639 %} | |
| 2640 | |
| 2641 // fnstsw_ax(); | |
| 2642 // sahf(); | |
| 2643 // movl(dst, nan_result); | |
| 2644 // jcc(Assembler::parity, exit); | |
| 2645 // movl(dst, less_result); | |
| 2646 // jcc(Assembler::below, exit); | |
| 2647 // movl(dst, equal_result); | |
| 2648 // jcc(Assembler::equal, exit); | |
| 2649 // movl(dst, greater_result); | |
| 2650 | |
| 2651 // less_result = 1; | |
| 2652 // greater_result = -1; | |
| 2653 // equal_result = 0; | |
| 2654 // nan_result = -1; | |
| 2655 | |
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2656 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2657 // fnstsw_ax(); |
| 2658 emit_opcode( cbuf, 0xDF); | |
| 2659 emit_opcode( cbuf, 0xE0); | |
| 2660 // sahf | |
| 2661 emit_opcode( cbuf, 0x9E); | |
| 2662 // movl(dst, nan_result); | |
| 2663 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2664 emit_d32( cbuf, -1 ); | |
| 2665 // jcc(Assembler::parity, exit); | |
| 2666 emit_opcode( cbuf, 0x7A ); | |
| 2667 emit_d8 ( cbuf, 0x13 ); | |
| 2668 // movl(dst, less_result); | |
| 2669 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2670 emit_d32( cbuf, -1 ); | |
| 2671 // jcc(Assembler::below, exit); | |
| 2672 emit_opcode( cbuf, 0x72 ); | |
| 2673 emit_d8 ( cbuf, 0x0C ); | |
| 2674 // movl(dst, equal_result); | |
| 2675 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2676 emit_d32( cbuf, 0 ); | |
| 2677 // jcc(Assembler::equal, exit); | |
| 2678 emit_opcode( cbuf, 0x74 ); | |
| 2679 emit_d8 ( cbuf, 0x05 ); | |
| 2680 // movl(dst, greater_result); | |
| 2681 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2682 emit_d32( cbuf, 1 ); | |
| 2683 %} | |
| 2684 | |
| 2685 | |
| 2686 // Compare the longs and set flags | |
| 2687 // BROKEN! Do Not use as-is | |
| 2688 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2689 // CMP $src1.hi,$src2.hi | |
| 2690 emit_opcode( cbuf, 0x3B ); | |
| 2691 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2692 // JNE,s done | |
| 2693 emit_opcode(cbuf,0x75); | |
| 2694 emit_d8(cbuf, 2 ); | |
| 2695 // CMP $src1.lo,$src2.lo | |
| 2696 emit_opcode( cbuf, 0x3B ); | |
| 2697 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2698 // done: | |
| 2699 %} | |
| 2700 | |
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2701 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2702 // mov $dst.lo,$src |
| 2703 int dst_encoding = $dst$$reg; | |
| 2704 int src_encoding = $src$$reg; | |
| 2705 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2706 // mov $dst.hi,$src | |
| 2707 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2708 // sar $dst.hi,31 | |
| 2709 emit_opcode( cbuf, 0xC1 ); | |
| 2710 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2711 emit_d8(cbuf, 0x1F ); | |
| 2712 %} | |
| 2713 | |
| 2714 enc_class convert_long_double( eRegL src ) %{ | |
| 2715 // push $src.hi | |
| 2716 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2717 // push $src.lo | |
| 2718 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2719 // fild 64-bits at [SP] | |
| 2720 emit_opcode(cbuf,0xdf); | |
| 2721 emit_d8(cbuf, 0x6C); | |
| 2722 emit_d8(cbuf, 0x24); | |
| 2723 emit_d8(cbuf, 0x00); | |
| 2724 // pop stack | |
| 2725 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2726 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2727 emit_d8(cbuf, 0x8); | |
| 2728 %} | |
| 2729 | |
| 2730 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2731 // IMUL EDX:EAX,$src1 | |
| 2732 emit_opcode( cbuf, 0xF7 ); | |
| 2733 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2734 // SAR EDX,$cnt-32 | |
| 2735 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2736 if (shift_count > 0) { | |
| 2737 emit_opcode(cbuf, 0xC1); | |
| 2738 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2739 emit_d8(cbuf, shift_count); | |
| 2740 } | |
| 2741 %} | |
| 2742 | |
| 2743 // this version doesn't have add sp, 8 | |
| 2744 enc_class convert_long_double2( eRegL src ) %{ | |
| 2745 // push $src.hi | |
| 2746 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2747 // push $src.lo | |
| 2748 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2749 // fild 64-bits at [SP] | |
| 2750 emit_opcode(cbuf,0xdf); | |
| 2751 emit_d8(cbuf, 0x6C); | |
| 2752 emit_d8(cbuf, 0x24); | |
| 2753 emit_d8(cbuf, 0x00); | |
| 2754 %} | |
| 2755 | |
| 2756 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2757 // Basic idea: long = (long)int * (long)int | |
| 2758 // IMUL EDX:EAX, src | |
| 2759 emit_opcode( cbuf, 0xF7 ); | |
| 2760 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2764 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2765 // MUL EDX:EAX, src | |
| 2766 emit_opcode( cbuf, 0xF7 ); | |
| 2767 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2768 %} | |
| 2769 | |
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2770 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2771 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2772 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2773 // MOV $tmp,$src.lo | |
| 2774 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2775 // IMUL $tmp,EDX | |
| 2776 emit_opcode( cbuf, 0x0F ); | |
| 2777 emit_opcode( cbuf, 0xAF ); | |
| 2778 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2779 // MOV EDX,$src.hi | |
| 2780 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2781 // IMUL EDX,EAX | |
| 2782 emit_opcode( cbuf, 0x0F ); | |
| 2783 emit_opcode( cbuf, 0xAF ); | |
| 2784 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2785 // ADD $tmp,EDX | |
| 2786 emit_opcode( cbuf, 0x03 ); | |
| 2787 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2788 // MUL EDX:EAX,$src.lo | |
| 2789 emit_opcode( cbuf, 0xF7 ); | |
| 2790 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2791 // ADD EDX,ESI | |
| 2792 emit_opcode( cbuf, 0x03 ); | |
| 2793 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2794 %} | |
| 2795 | |
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2796 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2797 // Basic idea: lo(result) = lo(src * y_lo) |
| 2798 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2799 // IMUL $tmp,EDX,$src | |
| 2800 emit_opcode( cbuf, 0x6B ); | |
| 2801 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2802 emit_d8( cbuf, (int)$src$$constant ); | |
| 2803 // MOV EDX,$src | |
| 2804 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2805 emit_d32( cbuf, (int)$src$$constant ); | |
| 2806 // MUL EDX:EAX,EDX | |
| 2807 emit_opcode( cbuf, 0xF7 ); | |
| 2808 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2809 // ADD EDX,ESI | |
| 2810 emit_opcode( cbuf, 0x03 ); | |
| 2811 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2812 %} | |
| 2813 | |
| 2814 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2815 // PUSH src1.hi | |
| 2816 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2817 // PUSH src1.lo | |
| 2818 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2819 // PUSH src2.hi | |
| 2820 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2821 // PUSH src2.lo | |
| 2822 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2823 // CALL directly to the runtime | |
| 1748 | 2824 cbuf.set_insts_mark(); |
| 0 | 2825 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2826 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2827 // Restore stack |
| 2828 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2829 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2830 emit_d8(cbuf, 4*4); | |
| 2831 %} | |
| 2832 | |
| 2833 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2834 // PUSH src1.hi | |
| 2835 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2836 // PUSH src1.lo | |
| 2837 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2838 // PUSH src2.hi | |
| 2839 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2840 // PUSH src2.lo | |
| 2841 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2842 // CALL directly to the runtime | |
| 1748 | 2843 cbuf.set_insts_mark(); |
| 0 | 2844 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2845 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2846 // Restore stack |
| 2847 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2848 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2849 emit_d8(cbuf, 4*4); | |
| 2850 %} | |
| 2851 | |
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2852 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2853 // MOV $tmp,$src.lo |
| 2854 emit_opcode(cbuf, 0x8B); | |
| 2855 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2856 // OR $tmp,$src.hi | |
| 2857 emit_opcode(cbuf, 0x0B); | |
| 2858 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2859 %} | |
| 2860 | |
| 2861 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2862 // CMP $src1.lo,$src2.lo | |
| 2863 emit_opcode( cbuf, 0x3B ); | |
| 2864 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2865 // JNE,s skip | |
| 2866 emit_cc(cbuf, 0x70, 0x5); | |
| 2867 emit_d8(cbuf,2); | |
| 2868 // CMP $src1.hi,$src2.hi | |
| 2869 emit_opcode( cbuf, 0x3B ); | |
| 2870 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2871 %} | |
| 2872 | |
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2873 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2874 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2875 emit_opcode( cbuf, 0x3B ); | |
| 2876 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2877 // MOV $tmp,$src1.hi | |
| 2878 emit_opcode( cbuf, 0x8B ); | |
| 2879 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2880 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2881 emit_opcode( cbuf, 0x1B ); | |
| 2882 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2883 %} | |
| 2884 | |
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2885 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2886 // XOR $tmp,$tmp |
| 2887 emit_opcode(cbuf,0x33); // XOR | |
| 2888 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2889 // CMP $tmp,$src.lo | |
| 2890 emit_opcode( cbuf, 0x3B ); | |
| 2891 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2892 // SBB $tmp,$src.hi | |
| 2893 emit_opcode( cbuf, 0x1B ); | |
| 2894 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2895 %} | |
| 2896 | |
| 2897 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2898 enc_class neg_long( eRegL dst ) %{ | |
| 2899 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2900 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2901 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2902 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2903 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2904 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2905 emit_d8 (cbuf,0 ); | |
| 2906 %} | |
| 2907 | |
| 2908 enc_class enc_pop_rdx() %{ | |
| 2909 emit_opcode(cbuf,0x5A); | |
| 2910 %} | |
| 2911 | |
| 2912 enc_class enc_rethrow() %{ | |
| 1748 | 2913 cbuf.set_insts_mark(); |
| 0 | 2914 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 2915 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 2916 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 2917 %} | |
| 2918 | |
| 2919 | |
| 2920 // Convert a double to an int. Java semantics require we do complex | |
| 2921 // manglelations in the corner cases. So we set the rounding mode to | |
| 2922 // 'zero', store the darned double down as an int, and reset the | |
| 2923 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 2924 // patches up the correct value directly to the stack. | |
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2925 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 2926 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 2927 // exceptions here, so that a NAN or other corner-case value will | |
| 2928 // thrown an exception (but normal values get converted at full speed). | |
| 2929 // However, I2C adapters and other float-stack manglers leave pending | |
| 2930 // invalid-op exceptions hanging. We would have to clear them before | |
| 2931 // enabling them and that is more expensive than just testing for the | |
| 2932 // invalid value Intel stores down in the corner cases. | |
| 2933 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 2934 emit_opcode(cbuf,0x2D); | |
| 2935 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2936 // Allocate a word | |
| 2937 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2938 emit_opcode(cbuf,0xEC); | |
| 2939 emit_d8(cbuf,0x04); | |
| 2940 // Encoding assumes a double has been pushed into FPR0. | |
| 2941 // Store down the double as an int, popping the FPU stack | |
| 2942 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 2943 emit_opcode(cbuf,0x1C); | |
| 2944 emit_d8(cbuf,0x24); | |
| 2945 // Restore the rounding mode; mask the exception | |
| 2946 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2947 emit_opcode(cbuf,0x2D); | |
| 2948 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2949 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2950 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2951 | |
| 2952 // Load the converted int; adjust CPU stack | |
| 2953 emit_opcode(cbuf,0x58); // POP EAX | |
| 2954 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 2955 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2956 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2957 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2958 // Push src onto stack slow-path | |
| 2959 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2960 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2961 // CALL directly to the runtime | |
| 1748 | 2962 cbuf.set_insts_mark(); |
| 0 | 2963 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2964 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2965 // Carry on here... |
| 2966 %} | |
| 2967 | |
|
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2968 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 2969 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 2970 emit_opcode(cbuf,0x2D); | |
| 2971 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2972 // Allocate a word | |
| 2973 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2974 emit_opcode(cbuf,0xEC); | |
| 2975 emit_d8(cbuf,0x08); | |
| 2976 // Encoding assumes a double has been pushed into FPR0. | |
| 2977 // Store down the double as a long, popping the FPU stack | |
| 2978 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 2979 emit_opcode(cbuf,0x3C); | |
| 2980 emit_d8(cbuf,0x24); | |
| 2981 // Restore the rounding mode; mask the exception | |
| 2982 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2983 emit_opcode(cbuf,0x2D); | |
| 2984 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2985 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2986 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2987 | |
| 2988 // Load the converted int; adjust CPU stack | |
| 2989 emit_opcode(cbuf,0x58); // POP EAX | |
| 2990 emit_opcode(cbuf,0x5A); // POP EDX | |
| 2991 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 2992 emit_d8 (cbuf,0xFA); // rdx | |
| 2993 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2994 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2995 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 2996 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 2997 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 2998 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2999 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3000 // Push src onto stack slow-path | |
| 3001 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3002 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3003 // CALL directly to the runtime | |
| 1748 | 3004 cbuf.set_insts_mark(); |
| 0 | 3005 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3006 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3007 // Carry on here... |
| 3008 %} | |
| 3009 | |
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3010 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3011 // Operand was loaded from memory into fp ST (stack top) |
| 3012 // FMUL ST,$src /* D8 C8+i */ | |
| 3013 emit_opcode(cbuf, 0xD8); | |
| 3014 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3015 %} | |
| 3016 | |
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3017 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3018 // FADDP ST,src2 /* D8 C0+i */ |
| 3019 emit_opcode(cbuf, 0xD8); | |
| 3020 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3021 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3022 %} | |
| 3023 | |
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3024 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3025 // FADDP src2,ST /* DE C0+i */ |
| 3026 emit_opcode(cbuf, 0xDE); | |
| 3027 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3028 %} | |
| 3029 | |
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3030 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3031 // Operand has been loaded into fp ST (stack top) |
| 3032 // FSUB ST,$src1 | |
| 3033 emit_opcode(cbuf, 0xD8); | |
| 3034 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3035 | |
| 3036 // FDIV | |
| 3037 emit_opcode(cbuf, 0xD8); | |
| 3038 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3039 %} | |
| 3040 | |
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3041 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3042 // Operand was loaded from memory into fp ST (stack top) |
| 3043 // FADD ST,$src /* D8 C0+i */ | |
| 3044 emit_opcode(cbuf, 0xD8); | |
| 3045 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3046 | |
| 3047 // FMUL ST,src2 /* D8 C*+i */ | |
| 3048 emit_opcode(cbuf, 0xD8); | |
| 3049 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3050 %} | |
| 3051 | |
| 3052 | |
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3053 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3054 // Operand was loaded from memory into fp ST (stack top) |
| 3055 // FADD ST,$src /* D8 C0+i */ | |
| 3056 emit_opcode(cbuf, 0xD8); | |
| 3057 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3058 | |
| 3059 // FMULP src2,ST /* DE C8+i */ | |
| 3060 emit_opcode(cbuf, 0xDE); | |
| 3061 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3062 %} | |
| 3063 | |
| 3064 // Atomically load the volatile long | |
| 3065 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3066 emit_opcode(cbuf,0xDF); | |
| 3067 int rm_byte_opcode = 0x05; | |
| 3068 int base = $mem$$base; | |
| 3069 int index = $mem$$index; | |
| 3070 int scale = $mem$$scale; | |
| 3071 int displace = $mem$$disp; | |
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3072 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3073 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3074 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3075 %} | |
| 3076 | |
| 3077 // Volatile Store Long. Must be atomic, so move it into | |
| 3078 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3079 // target address before the store (for null-ptr checks) | |
| 3080 // so the memory operand is used twice in the encoding. | |
| 3081 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3082 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3083 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3084 emit_opcode(cbuf,0xDF); |
| 3085 int rm_byte_opcode = 0x07; | |
| 3086 int base = $mem$$base; | |
| 3087 int index = $mem$$index; | |
| 3088 int scale = $mem$$scale; | |
| 3089 int displace = $mem$$disp; | |
|
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3090 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3091 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3092 %} |
| 3093 | |
| 3094 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3095 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3096 // in the process | |
| 3097 // We current use TESTL [spp],EDI | |
| 3098 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3099 | |
| 3100 enc_class Safepoint_Poll() %{ | |
| 1748 | 3101 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3102 emit_opcode(cbuf,0x85); |
| 3103 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3104 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3105 %} | |
| 3106 %} | |
| 3107 | |
| 3108 | |
| 3109 //----------FRAME-------------------------------------------------------------- | |
| 3110 // Definition of frame structure and management information. | |
| 3111 // | |
| 3112 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3113 // | (to get allocators register number | |
| 3114 // G Owned by | | v add OptoReg::stack0()) | |
| 3115 // r CALLER | | | |
| 3116 // o | +--------+ pad to even-align allocators stack-slot | |
| 3117 // w V | pad0 | numbers; owned by CALLER | |
| 3118 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3119 // h ^ | in | 5 | |
| 3120 // | | args | 4 Holes in incoming args owned by SELF | |
| 3121 // | | | | 3 | |
| 3122 // | | +--------+ | |
| 3123 // V | | old out| Empty on Intel, window on Sparc | |
| 3124 // | old |preserve| Must be even aligned. | |
| 3125 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3126 // | | in | 3 area for Intel ret address | |
| 3127 // Owned by |preserve| Empty on Sparc. | |
| 3128 // SELF +--------+ | |
| 3129 // | | pad2 | 2 pad to align old SP | |
| 3130 // | +--------+ 1 | |
| 3131 // | | locks | 0 | |
| 3132 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3133 // | | pad1 | 11 pad to align new SP | |
| 3134 // | +--------+ | |
| 3135 // | | | 10 | |
| 3136 // | | spills | 9 spills | |
| 3137 // V | | 8 (pad0 slot for callee) | |
| 3138 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3139 // ^ | out | 7 | |
| 3140 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3141 // Owned by +--------+ | |
| 3142 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3143 // | new |preserve| Must be even-aligned. | |
| 3144 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3145 // | | | | |
| 3146 // | |
| 3147 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3148 // known from SELF's arguments and the Java calling convention. | |
| 3149 // Region 6-7 is determined per call site. | |
| 3150 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3151 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3152 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3153 // incoming area, as the Java calling convention is completely under | |
| 3154 // the control of the AD file. Doubles can be sorted and packed to | |
| 3155 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3156 // varargs C calling conventions. | |
| 3157 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3158 // even aligned with pad0 as needed. | |
| 3159 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3160 // region 6-11 is even aligned; it may be padded out more so that | |
| 3161 // the region from SP to FP meets the minimum stack alignment. | |
| 3162 | |
| 3163 frame %{ | |
| 3164 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3165 stack_direction(TOWARDS_LOW); | |
| 3166 | |
| 3167 // These three registers define part of the calling convention | |
| 3168 // between compiled code and the interpreter. | |
| 3169 inline_cache_reg(EAX); // Inline Cache Register | |
| 3170 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3171 | |
| 3172 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3173 cisc_spilling_operand_name(indOffset32); | |
| 3174 | |
| 3175 // Number of stack slots consumed by locking an object | |
| 3176 sync_stack_slots(1); | |
| 3177 | |
| 3178 // Compiled code's Frame Pointer | |
| 3179 frame_pointer(ESP); | |
| 3180 // Interpreter stores its frame pointer in a register which is | |
| 3181 // stored to the stack by I2CAdaptors. | |
| 3182 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3183 interpreter_frame_pointer(EBP); | |
| 3184 | |
| 3185 // Stack alignment requirement | |
| 3186 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3187 stack_alignment(StackAlignmentInBytes); | |
| 3188 | |
| 3189 // Number of stack slots between incoming argument block and the start of | |
| 3190 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3191 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3192 // return address and one for rbp, (must save rbp) | |
| 3193 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3194 | |
| 3195 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3196 // for calls to C. Supports the var-args backing area for register parms. | |
| 3197 varargs_C_out_slots_killed(0); | |
| 3198 | |
| 3199 // The after-PROLOG location of the return address. Location of | |
| 3200 // return address specifies a type (REG or STACK) and a number | |
| 3201 // representing the register number (i.e. - use a register name) or | |
| 3202 // stack slot. | |
| 3203 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3204 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3205 return_addr(STACK - 1 + | |
| 4950 | 3206 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3207 Compile::current()->fixed_slots()), | |
| 3208 stack_alignment_in_slots())); | |
| 0 | 3209 |
| 3210 // Body of function which returns an integer array locating | |
| 3211 // arguments either in registers or in stack slots. Passed an array | |
| 3212 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3213 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3214 // arguments for a CALLEE. Incoming stack arguments are | |
| 3215 // automatically biased by the preserve_stack_slots field above. | |
| 3216 calling_convention %{ | |
| 3217 // No difference between ingoing/outgoing just pass false | |
| 3218 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3219 %} | |
| 3220 | |
| 3221 | |
| 3222 // Body of function which returns an integer array locating | |
| 3223 // arguments either in registers or in stack slots. Passed an array | |
| 3224 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3225 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3226 // arguments for a CALLEE. Incoming stack arguments are | |
| 3227 // automatically biased by the preserve_stack_slots field above. | |
| 3228 c_calling_convention %{ | |
| 3229 // This is obviously always outgoing | |
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3230 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3231 %} |
| 3232 | |
| 3233 // Location of C & interpreter return values | |
| 3234 c_return_value %{ | |
| 3235 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3236 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3237 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3238 |
| 3239 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3240 // that C functions return float and double results in XMM0. | |
| 3241 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
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3242 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3243 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
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3244 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3245 |
| 3246 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3247 %} | |
| 3248 | |
| 3249 // Location of return values | |
| 3250 return_value %{ | |
| 3251 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3252 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3253 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3254 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
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3255 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3256 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
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3257 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3258 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3259 %} | |
| 3260 | |
| 3261 %} | |
| 3262 | |
| 3263 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3264 //----------Operand Attributes------------------------------------------------- | |
| 3265 op_attrib op_cost(0); // Required cost attribute | |
| 3266 | |
| 3267 //----------Instruction Attributes--------------------------------------------- | |
| 3268 ins_attrib ins_cost(100); // Required cost attribute | |
| 3269 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3270 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3271 // non-matching short branch variant of some | |
| 3272 // long branch? | |
| 3273 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3274 // specifies the alignment that some part of the instruction (not | |
| 3275 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3276 // function must be provided for the instruction | |
| 3277 | |
| 3278 //----------OPERANDS----------------------------------------------------------- | |
| 3279 // Operand definitions must precede instruction definitions for correct parsing | |
| 3280 // in the ADLC because operands constitute user defined types which are used in | |
| 3281 // instruction definitions. | |
| 3282 | |
| 3283 //----------Simple Operands---------------------------------------------------- | |
| 3284 // Immediate Operands | |
| 3285 // Integer Immediate | |
| 3286 operand immI() %{ | |
| 3287 match(ConI); | |
| 3288 | |
| 3289 op_cost(10); | |
| 3290 format %{ %} | |
| 3291 interface(CONST_INTER); | |
| 3292 %} | |
| 3293 | |
| 3294 // Constant for test vs zero | |
| 3295 operand immI0() %{ | |
| 3296 predicate(n->get_int() == 0); | |
| 3297 match(ConI); | |
| 3298 | |
| 3299 op_cost(0); | |
| 3300 format %{ %} | |
| 3301 interface(CONST_INTER); | |
| 3302 %} | |
| 3303 | |
| 3304 // Constant for increment | |
| 3305 operand immI1() %{ | |
| 3306 predicate(n->get_int() == 1); | |
| 3307 match(ConI); | |
| 3308 | |
| 3309 op_cost(0); | |
| 3310 format %{ %} | |
| 3311 interface(CONST_INTER); | |
| 3312 %} | |
| 3313 | |
| 3314 // Constant for decrement | |
| 3315 operand immI_M1() %{ | |
| 3316 predicate(n->get_int() == -1); | |
| 3317 match(ConI); | |
| 3318 | |
| 3319 op_cost(0); | |
| 3320 format %{ %} | |
| 3321 interface(CONST_INTER); | |
| 3322 %} | |
| 3323 | |
| 3324 // Valid scale values for addressing modes | |
| 3325 operand immI2() %{ | |
| 3326 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3327 match(ConI); | |
| 3328 | |
| 3329 format %{ %} | |
| 3330 interface(CONST_INTER); | |
| 3331 %} | |
| 3332 | |
| 3333 operand immI8() %{ | |
| 3334 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3335 match(ConI); | |
| 3336 | |
| 3337 op_cost(5); | |
| 3338 format %{ %} | |
| 3339 interface(CONST_INTER); | |
| 3340 %} | |
| 3341 | |
| 3342 operand immI16() %{ | |
| 3343 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3344 match(ConI); | |
| 3345 | |
| 3346 op_cost(10); | |
| 3347 format %{ %} | |
| 3348 interface(CONST_INTER); | |
| 3349 %} | |
| 3350 | |
|
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|
3351 // Int Immediate non-negative |
|
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|
3352 operand immU31() |
|
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|
3353 %{ |
|
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|
3354 predicate(n->get_int() >= 0); |
|
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|
3355 match(ConI); |
|
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|
3356 |
|
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|
3357 op_cost(0); |
|
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|
3358 format %{ %} |
|
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|
3359 interface(CONST_INTER); |
|
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|
3360 %} |
|
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|
3361 |
| 0 | 3362 // Constant for long shifts |
| 3363 operand immI_32() %{ | |
| 3364 predicate( n->get_int() == 32 ); | |
| 3365 match(ConI); | |
| 3366 | |
| 3367 op_cost(0); | |
| 3368 format %{ %} | |
| 3369 interface(CONST_INTER); | |
| 3370 %} | |
| 3371 | |
| 3372 operand immI_1_31() %{ | |
| 3373 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3374 match(ConI); | |
| 3375 | |
| 3376 op_cost(0); | |
| 3377 format %{ %} | |
| 3378 interface(CONST_INTER); | |
| 3379 %} | |
| 3380 | |
| 3381 operand immI_32_63() %{ | |
| 3382 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3383 match(ConI); | |
| 3384 op_cost(0); | |
| 3385 | |
| 3386 format %{ %} | |
| 3387 interface(CONST_INTER); | |
| 3388 %} | |
| 3389 | |
| 219 | 3390 operand immI_1() %{ |
| 3391 predicate( n->get_int() == 1 ); | |
| 3392 match(ConI); | |
| 3393 | |
| 3394 op_cost(0); | |
| 3395 format %{ %} | |
| 3396 interface(CONST_INTER); | |
| 3397 %} | |
| 3398 | |
| 3399 operand immI_2() %{ | |
| 3400 predicate( n->get_int() == 2 ); | |
| 3401 match(ConI); | |
| 3402 | |
| 3403 op_cost(0); | |
| 3404 format %{ %} | |
| 3405 interface(CONST_INTER); | |
| 3406 %} | |
| 3407 | |
| 3408 operand immI_3() %{ | |
| 3409 predicate( n->get_int() == 3 ); | |
| 3410 match(ConI); | |
| 3411 | |
| 3412 op_cost(0); | |
| 3413 format %{ %} | |
| 3414 interface(CONST_INTER); | |
| 3415 %} | |
| 3416 | |
| 0 | 3417 // Pointer Immediate |
| 3418 operand immP() %{ | |
| 3419 match(ConP); | |
| 3420 | |
| 3421 op_cost(10); | |
| 3422 format %{ %} | |
| 3423 interface(CONST_INTER); | |
| 3424 %} | |
| 3425 | |
| 3426 // NULL Pointer Immediate | |
| 3427 operand immP0() %{ | |
| 3428 predicate( n->get_ptr() == 0 ); | |
| 3429 match(ConP); | |
| 3430 op_cost(0); | |
| 3431 | |
| 3432 format %{ %} | |
| 3433 interface(CONST_INTER); | |
| 3434 %} | |
| 3435 | |
| 3436 // Long Immediate | |
| 3437 operand immL() %{ | |
| 3438 match(ConL); | |
| 3439 | |
| 3440 op_cost(20); | |
| 3441 format %{ %} | |
| 3442 interface(CONST_INTER); | |
| 3443 %} | |
| 3444 | |
| 3445 // Long Immediate zero | |
| 3446 operand immL0() %{ | |
| 3447 predicate( n->get_long() == 0L ); | |
| 3448 match(ConL); | |
| 3449 op_cost(0); | |
| 3450 | |
| 3451 format %{ %} | |
| 3452 interface(CONST_INTER); | |
| 3453 %} | |
| 3454 | |
| 403 | 3455 // Long Immediate zero |
| 3456 operand immL_M1() %{ | |
| 3457 predicate( n->get_long() == -1L ); | |
| 3458 match(ConL); | |
| 3459 op_cost(0); | |
| 3460 | |
| 3461 format %{ %} | |
| 3462 interface(CONST_INTER); | |
| 3463 %} | |
| 3464 | |
| 0 | 3465 // Long immediate from 0 to 127. |
| 3466 // Used for a shorter form of long mul by 10. | |
| 3467 operand immL_127() %{ | |
| 3468 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3469 match(ConL); | |
| 3470 op_cost(0); | |
| 3471 | |
| 3472 format %{ %} | |
| 3473 interface(CONST_INTER); | |
| 3474 %} | |
| 3475 | |
| 3476 // Long Immediate: low 32-bit mask | |
| 3477 operand immL_32bits() %{ | |
| 3478 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3479 match(ConL); | |
| 3480 op_cost(0); | |
| 3481 | |
| 3482 format %{ %} | |
| 3483 interface(CONST_INTER); | |
| 3484 %} | |
| 3485 | |
| 3486 // Long Immediate: low 32-bit mask | |
| 3487 operand immL32() %{ | |
| 3488 predicate(n->get_long() == (int)(n->get_long())); | |
| 3489 match(ConL); | |
| 3490 op_cost(20); | |
| 3491 | |
| 3492 format %{ %} | |
| 3493 interface(CONST_INTER); | |
| 3494 %} | |
| 3495 | |
| 3496 //Double Immediate zero | |
|
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3497 operand immDPR0() %{ |
| 0 | 3498 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3499 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3500 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3501 match(ConD); | |
| 3502 | |
| 3503 op_cost(5); | |
| 3504 format %{ %} | |
| 3505 interface(CONST_INTER); | |
| 3506 %} | |
| 3507 | |
| 2008 | 3508 // Double Immediate one |
|
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3509 operand immDPR1() %{ |
| 0 | 3510 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 3511 match(ConD); | |
| 3512 | |
| 3513 op_cost(5); | |
| 3514 format %{ %} | |
| 3515 interface(CONST_INTER); | |
| 3516 %} | |
| 3517 | |
| 3518 // Double Immediate | |
|
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|
3519 operand immDPR() %{ |
| 0 | 3520 predicate(UseSSE<=1); |
| 3521 match(ConD); | |
| 3522 | |
| 3523 op_cost(5); | |
| 3524 format %{ %} | |
| 3525 interface(CONST_INTER); | |
| 3526 %} | |
| 3527 | |
|
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|
3528 operand immD() %{ |
| 0 | 3529 predicate(UseSSE>=2); |
| 3530 match(ConD); | |
| 3531 | |
| 3532 op_cost(5); | |
| 3533 format %{ %} | |
| 3534 interface(CONST_INTER); | |
| 3535 %} | |
| 3536 | |
| 3537 // Double Immediate zero | |
|
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3538 operand immD0() %{ |
| 0 | 3539 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3540 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 3541 // compare equal to -0.0. | |
| 3542 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 3543 match(ConD); | |
| 3544 | |
| 3545 format %{ %} | |
| 3546 interface(CONST_INTER); | |
| 3547 %} | |
| 3548 | |
| 3549 // Float Immediate zero | |
|
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3550 operand immFPR0() %{ |
| 2008 | 3551 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 3552 match(ConF); | |
| 3553 | |
| 3554 op_cost(5); | |
| 3555 format %{ %} | |
| 3556 interface(CONST_INTER); | |
| 3557 %} | |
| 3558 | |
| 3559 // Float Immediate one | |
|
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3560 operand immFPR1() %{ |
| 2008 | 3561 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 3562 match(ConF); |
| 3563 | |
| 3564 op_cost(5); | |
| 3565 format %{ %} | |
| 3566 interface(CONST_INTER); | |
| 3567 %} | |
| 3568 | |
| 3569 // Float Immediate | |
|
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|
3570 operand immFPR() %{ |
|
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|
3571 predicate( UseSSE == 0 ); |
|
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|
3572 match(ConF); |
|
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|
3573 |
|
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|
3574 op_cost(5); |
|
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|
3575 format %{ %} |
|
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|
3576 interface(CONST_INTER); |
|
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|
3577 %} |
|
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|
3578 |
|
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3579 // Float Immediate |
| 0 | 3580 operand immF() %{ |
| 3581 predicate(UseSSE >= 1); | |
| 3582 match(ConF); | |
| 3583 | |
| 3584 op_cost(5); | |
| 3585 format %{ %} | |
| 3586 interface(CONST_INTER); | |
| 3587 %} | |
| 3588 | |
| 3589 // Float Immediate zero. Zero and not -0.0 | |
|
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3590 operand immF0() %{ |
| 0 | 3591 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 3592 match(ConF); | |
| 3593 | |
| 3594 op_cost(5); | |
| 3595 format %{ %} | |
| 3596 interface(CONST_INTER); | |
| 3597 %} | |
| 3598 | |
| 3599 // Immediates for special shifts (sign extend) | |
| 3600 | |
| 3601 // Constants for increment | |
| 3602 operand immI_16() %{ | |
| 3603 predicate( n->get_int() == 16 ); | |
| 3604 match(ConI); | |
| 3605 | |
| 3606 format %{ %} | |
| 3607 interface(CONST_INTER); | |
| 3608 %} | |
| 3609 | |
| 3610 operand immI_24() %{ | |
| 3611 predicate( n->get_int() == 24 ); | |
| 3612 match(ConI); | |
| 3613 | |
| 3614 format %{ %} | |
| 3615 interface(CONST_INTER); | |
| 3616 %} | |
| 3617 | |
| 3618 // Constant for byte-wide masking | |
| 3619 operand immI_255() %{ | |
| 3620 predicate( n->get_int() == 255 ); | |
| 3621 match(ConI); | |
| 3622 | |
| 3623 format %{ %} | |
| 3624 interface(CONST_INTER); | |
| 3625 %} | |
| 3626 | |
| 785 | 3627 // Constant for short-wide masking |
| 3628 operand immI_65535() %{ | |
| 3629 predicate(n->get_int() == 65535); | |
| 3630 match(ConI); | |
| 3631 | |
| 3632 format %{ %} | |
| 3633 interface(CONST_INTER); | |
| 3634 %} | |
| 3635 | |
| 0 | 3636 // Register Operands |
| 3637 // Integer Register | |
|
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|
3638 operand rRegI() %{ |
|
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|
3639 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3640 match(RegI); |
| 3641 match(xRegI); | |
| 3642 match(eAXRegI); | |
| 3643 match(eBXRegI); | |
| 3644 match(eCXRegI); | |
| 3645 match(eDXRegI); | |
| 3646 match(eDIRegI); | |
| 3647 match(eSIRegI); | |
| 3648 | |
| 3649 format %{ %} | |
| 3650 interface(REG_INTER); | |
| 3651 %} | |
| 3652 | |
| 3653 // Subset of Integer Register | |
|
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|
3654 operand xRegI(rRegI reg) %{ |
|
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|
3655 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 3656 match(reg); |
| 3657 match(eAXRegI); | |
| 3658 match(eBXRegI); | |
| 3659 match(eCXRegI); | |
| 3660 match(eDXRegI); | |
| 3661 | |
| 3662 format %{ %} | |
| 3663 interface(REG_INTER); | |
| 3664 %} | |
| 3665 | |
| 3666 // Special Registers | |
| 3667 operand eAXRegI(xRegI reg) %{ | |
| 3668 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3669 match(reg); | |
|
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|
3670 match(rRegI); |
| 0 | 3671 |
| 3672 format %{ "EAX" %} | |
| 3673 interface(REG_INTER); | |
| 3674 %} | |
| 3675 | |
| 3676 // Special Registers | |
| 3677 operand eBXRegI(xRegI reg) %{ | |
| 3678 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3679 match(reg); | |
|
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|
3680 match(rRegI); |
| 0 | 3681 |
| 3682 format %{ "EBX" %} | |
| 3683 interface(REG_INTER); | |
| 3684 %} | |
| 3685 | |
| 3686 operand eCXRegI(xRegI reg) %{ | |
| 3687 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3688 match(reg); | |
|
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|
3689 match(rRegI); |
| 0 | 3690 |
| 3691 format %{ "ECX" %} | |
| 3692 interface(REG_INTER); | |
| 3693 %} | |
| 3694 | |
| 3695 operand eDXRegI(xRegI reg) %{ | |
| 3696 constraint(ALLOC_IN_RC(edx_reg)); | |
| 3697 match(reg); | |
|
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|
3698 match(rRegI); |
| 0 | 3699 |
| 3700 format %{ "EDX" %} | |
| 3701 interface(REG_INTER); | |
| 3702 %} | |
| 3703 | |
| 3704 operand eDIRegI(xRegI reg) %{ | |
| 3705 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3706 match(reg); | |
|
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3707 match(rRegI); |
| 0 | 3708 |
| 3709 format %{ "EDI" %} | |
| 3710 interface(REG_INTER); | |
| 3711 %} | |
| 3712 | |
| 3713 operand naxRegI() %{ | |
| 3714 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3715 match(RegI); | |
| 3716 match(eCXRegI); | |
| 3717 match(eDXRegI); | |
| 3718 match(eSIRegI); | |
| 3719 match(eDIRegI); | |
| 3720 | |
| 3721 format %{ %} | |
| 3722 interface(REG_INTER); | |
| 3723 %} | |
| 3724 | |
| 3725 operand nadxRegI() %{ | |
| 3726 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 3727 match(RegI); | |
| 3728 match(eBXRegI); | |
| 3729 match(eCXRegI); | |
| 3730 match(eSIRegI); | |
| 3731 match(eDIRegI); | |
| 3732 | |
| 3733 format %{ %} | |
| 3734 interface(REG_INTER); | |
| 3735 %} | |
| 3736 | |
| 3737 operand ncxRegI() %{ | |
| 3738 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 3739 match(RegI); | |
| 3740 match(eAXRegI); | |
| 3741 match(eDXRegI); | |
| 3742 match(eSIRegI); | |
| 3743 match(eDIRegI); | |
| 3744 | |
| 3745 format %{ %} | |
| 3746 interface(REG_INTER); | |
| 3747 %} | |
| 3748 | |
| 3749 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 3750 // // | |
| 3751 operand eSIRegI(xRegI reg) %{ | |
| 3752 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3753 match(reg); | |
|
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3754 match(rRegI); |
| 0 | 3755 |
| 3756 format %{ "ESI" %} | |
| 3757 interface(REG_INTER); | |
| 3758 %} | |
| 3759 | |
| 3760 // Pointer Register | |
| 3761 operand anyRegP() %{ | |
| 3762 constraint(ALLOC_IN_RC(any_reg)); | |
| 3763 match(RegP); | |
| 3764 match(eAXRegP); | |
| 3765 match(eBXRegP); | |
| 3766 match(eCXRegP); | |
| 3767 match(eDIRegP); | |
| 3768 match(eRegP); | |
| 3769 | |
| 3770 format %{ %} | |
| 3771 interface(REG_INTER); | |
| 3772 %} | |
| 3773 | |
| 3774 operand eRegP() %{ | |
|
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|
3775 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3776 match(RegP); |
| 3777 match(eAXRegP); | |
| 3778 match(eBXRegP); | |
| 3779 match(eCXRegP); | |
| 3780 match(eDIRegP); | |
| 3781 | |
| 3782 format %{ %} | |
| 3783 interface(REG_INTER); | |
| 3784 %} | |
| 3785 | |
| 3786 // On windows95, EBP is not safe to use for implicit null tests. | |
| 3787 operand eRegP_no_EBP() %{ | |
|
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3788 constraint(ALLOC_IN_RC(int_reg_no_rbp)); |
| 0 | 3789 match(RegP); |
| 3790 match(eAXRegP); | |
| 3791 match(eBXRegP); | |
| 3792 match(eCXRegP); | |
| 3793 match(eDIRegP); | |
| 3794 | |
| 3795 op_cost(100); | |
| 3796 format %{ %} | |
| 3797 interface(REG_INTER); | |
| 3798 %} | |
| 3799 | |
| 3800 operand naxRegP() %{ | |
| 3801 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3802 match(RegP); | |
| 3803 match(eBXRegP); | |
| 3804 match(eDXRegP); | |
| 3805 match(eCXRegP); | |
| 3806 match(eSIRegP); | |
| 3807 match(eDIRegP); | |
| 3808 | |
| 3809 format %{ %} | |
| 3810 interface(REG_INTER); | |
| 3811 %} | |
| 3812 | |
| 3813 operand nabxRegP() %{ | |
| 3814 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 3815 match(RegP); | |
| 3816 match(eCXRegP); | |
| 3817 match(eDXRegP); | |
| 3818 match(eSIRegP); | |
| 3819 match(eDIRegP); | |
| 3820 | |
| 3821 format %{ %} | |
| 3822 interface(REG_INTER); | |
| 3823 %} | |
| 3824 | |
| 3825 operand pRegP() %{ | |
| 3826 constraint(ALLOC_IN_RC(p_reg)); | |
| 3827 match(RegP); | |
| 3828 match(eBXRegP); | |
| 3829 match(eDXRegP); | |
| 3830 match(eSIRegP); | |
| 3831 match(eDIRegP); | |
| 3832 | |
| 3833 format %{ %} | |
| 3834 interface(REG_INTER); | |
| 3835 %} | |
| 3836 | |
| 3837 // Special Registers | |
| 3838 // Return a pointer value | |
| 3839 operand eAXRegP(eRegP reg) %{ | |
| 3840 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3841 match(reg); | |
| 3842 format %{ "EAX" %} | |
| 3843 interface(REG_INTER); | |
| 3844 %} | |
| 3845 | |
| 3846 // Used in AtomicAdd | |
| 3847 operand eBXRegP(eRegP reg) %{ | |
| 3848 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3849 match(reg); | |
| 3850 format %{ "EBX" %} | |
| 3851 interface(REG_INTER); | |
| 3852 %} | |
| 3853 | |
| 3854 // Tail-call (interprocedural jump) to interpreter | |
| 3855 operand eCXRegP(eRegP reg) %{ | |
| 3856 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3857 match(reg); | |
| 3858 format %{ "ECX" %} | |
| 3859 interface(REG_INTER); | |
| 3860 %} | |
| 3861 | |
| 3862 operand eSIRegP(eRegP reg) %{ | |
| 3863 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3864 match(reg); | |
| 3865 format %{ "ESI" %} | |
| 3866 interface(REG_INTER); | |
| 3867 %} | |
| 3868 | |
| 3869 // Used in rep stosw | |
| 3870 operand eDIRegP(eRegP reg) %{ | |
| 3871 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3872 match(reg); | |
| 3873 format %{ "EDI" %} | |
| 3874 interface(REG_INTER); | |
| 3875 %} | |
| 3876 | |
| 3877 operand eBPRegP() %{ | |
| 3878 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 3879 match(RegP); | |
| 3880 format %{ "EBP" %} | |
| 3881 interface(REG_INTER); | |
| 3882 %} | |
| 3883 | |
| 3884 operand eRegL() %{ | |
| 3885 constraint(ALLOC_IN_RC(long_reg)); | |
| 3886 match(RegL); | |
| 3887 match(eADXRegL); | |
| 3888 | |
| 3889 format %{ %} | |
| 3890 interface(REG_INTER); | |
| 3891 %} | |
| 3892 | |
| 3893 operand eADXRegL( eRegL reg ) %{ | |
| 3894 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3895 match(reg); | |
| 3896 | |
| 3897 format %{ "EDX:EAX" %} | |
| 3898 interface(REG_INTER); | |
| 3899 %} | |
| 3900 | |
| 3901 operand eBCXRegL( eRegL reg ) %{ | |
| 3902 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 3903 match(reg); | |
| 3904 | |
| 3905 format %{ "EBX:ECX" %} | |
| 3906 interface(REG_INTER); | |
| 3907 %} | |
| 3908 | |
| 3909 // Special case for integer high multiply | |
| 3910 operand eADXRegL_low_only() %{ | |
| 3911 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3912 match(RegL); | |
| 3913 | |
| 3914 format %{ "EAX" %} | |
| 3915 interface(REG_INTER); | |
| 3916 %} | |
| 3917 | |
| 3918 // Flags register, used as output of compare instructions | |
| 3919 operand eFlagsReg() %{ | |
| 3920 constraint(ALLOC_IN_RC(int_flags)); | |
| 3921 match(RegFlags); | |
| 3922 | |
| 3923 format %{ "EFLAGS" %} | |
| 3924 interface(REG_INTER); | |
| 3925 %} | |
| 3926 | |
| 3927 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3928 operand eFlagsRegU() %{ | |
| 3929 constraint(ALLOC_IN_RC(int_flags)); | |
| 3930 match(RegFlags); | |
| 3931 | |
| 3932 format %{ "EFLAGS_U" %} | |
| 3933 interface(REG_INTER); | |
| 3934 %} | |
| 3935 | |
|
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|
3936 operand eFlagsRegUCF() %{ |
|
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|
3937 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3938 match(RegFlags); |
|
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|
3939 predicate(false); |
|
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|
3940 |
|
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|
3941 format %{ "EFLAGS_U_CF" %} |
|
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|
3942 interface(REG_INTER); |
|
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|
3943 %} |
|
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|
3944 |
| 0 | 3945 // Condition Code Register used by long compare |
| 3946 operand flagsReg_long_LTGE() %{ | |
| 3947 constraint(ALLOC_IN_RC(int_flags)); | |
| 3948 match(RegFlags); | |
| 3949 format %{ "FLAGS_LTGE" %} | |
| 3950 interface(REG_INTER); | |
| 3951 %} | |
| 3952 operand flagsReg_long_EQNE() %{ | |
| 3953 constraint(ALLOC_IN_RC(int_flags)); | |
| 3954 match(RegFlags); | |
| 3955 format %{ "FLAGS_EQNE" %} | |
| 3956 interface(REG_INTER); | |
| 3957 %} | |
| 3958 operand flagsReg_long_LEGT() %{ | |
| 3959 constraint(ALLOC_IN_RC(int_flags)); | |
| 3960 match(RegFlags); | |
| 3961 format %{ "FLAGS_LEGT" %} | |
| 3962 interface(REG_INTER); | |
| 3963 %} | |
| 3964 | |
| 3965 // Float register operands | |
|
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|
3966 operand regDPR() %{ |
| 0 | 3967 predicate( UseSSE < 2 ); |
|
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|
3968 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 3969 match(RegD); |
| 3970 match(regDPR1); | |
| 3971 match(regDPR2); | |
| 3972 format %{ %} | |
| 3973 interface(REG_INTER); | |
| 3974 %} | |
| 3975 | |
|
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|
3976 operand regDPR1(regDPR reg) %{ |
| 0 | 3977 predicate( UseSSE < 2 ); |
|
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|
3978 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 3979 match(reg); |
| 3980 format %{ "FPR1" %} | |
| 3981 interface(REG_INTER); | |
| 3982 %} | |
| 3983 | |
|
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|
3984 operand regDPR2(regDPR reg) %{ |
| 0 | 3985 predicate( UseSSE < 2 ); |
|
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|
3986 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 3987 match(reg); |
| 3988 format %{ "FPR2" %} | |
| 3989 interface(REG_INTER); | |
| 3990 %} | |
| 3991 | |
|
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3992 operand regnotDPR1(regDPR reg) %{ |
| 0 | 3993 predicate( UseSSE < 2 ); |
|
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3994 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 3995 match(reg); |
| 3996 format %{ %} | |
| 3997 interface(REG_INTER); | |
| 3998 %} | |
| 3999 | |
| 4000 // Float register operands | |
|
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|
4001 operand regFPR() %{ |
| 0 | 4002 predicate( UseSSE < 2 ); |
|
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|
4003 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 4004 match(RegF); |
| 4005 match(regFPR1); | |
| 4006 format %{ %} | |
| 4007 interface(REG_INTER); | |
| 4008 %} | |
| 4009 | |
| 4010 // Float register operands | |
|
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|
4011 operand regFPR1(regFPR reg) %{ |
| 0 | 4012 predicate( UseSSE < 2 ); |
|
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|
4013 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 4014 match(reg); |
| 4015 format %{ "FPR1" %} | |
| 4016 interface(REG_INTER); | |
| 4017 %} | |
| 4018 | |
|
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|
4019 // XMM Float register operands |
|
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4020 operand regF() %{ |
| 0 | 4021 predicate( UseSSE>=1 ); |
|
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|
4022 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4023 match(RegF); |
| 4024 format %{ %} | |
| 4025 interface(REG_INTER); | |
| 4026 %} | |
| 4027 | |
|
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|
4028 // XMM Double register operands |
|
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|
4029 operand regD() %{ |
|
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|
4030 predicate( UseSSE>=2 ); |
|
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|
4031 constraint(ALLOC_IN_RC(double_reg)); |
|
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|
4032 match(RegD); |
|
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|
4033 format %{ %} |
|
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|
4034 interface(REG_INTER); |
|
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|
4035 %} |
|
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|
4036 |
| 0 | 4037 |
| 4038 //----------Memory Operands---------------------------------------------------- | |
| 4039 // Direct Memory Operand | |
| 4040 operand direct(immP addr) %{ | |
| 4041 match(addr); | |
| 4042 | |
| 4043 format %{ "[$addr]" %} | |
| 4044 interface(MEMORY_INTER) %{ | |
| 4045 base(0xFFFFFFFF); | |
| 4046 index(0x4); | |
| 4047 scale(0x0); | |
| 4048 disp($addr); | |
| 4049 %} | |
| 4050 %} | |
| 4051 | |
| 4052 // Indirect Memory Operand | |
| 4053 operand indirect(eRegP reg) %{ | |
|
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|
4054 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4055 match(reg); |
| 4056 | |
| 4057 format %{ "[$reg]" %} | |
| 4058 interface(MEMORY_INTER) %{ | |
| 4059 base($reg); | |
| 4060 index(0x4); | |
| 4061 scale(0x0); | |
| 4062 disp(0x0); | |
| 4063 %} | |
| 4064 %} | |
| 4065 | |
| 4066 // Indirect Memory Plus Short Offset Operand | |
| 4067 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4068 match(AddP reg off); | |
| 4069 | |
| 4070 format %{ "[$reg + $off]" %} | |
| 4071 interface(MEMORY_INTER) %{ | |
| 4072 base($reg); | |
| 4073 index(0x4); | |
| 4074 scale(0x0); | |
| 4075 disp($off); | |
| 4076 %} | |
| 4077 %} | |
| 4078 | |
| 4079 // Indirect Memory Plus Long Offset Operand | |
| 4080 operand indOffset32(eRegP reg, immI off) %{ | |
| 4081 match(AddP reg off); | |
| 4082 | |
| 4083 format %{ "[$reg + $off]" %} | |
| 4084 interface(MEMORY_INTER) %{ | |
| 4085 base($reg); | |
| 4086 index(0x4); | |
| 4087 scale(0x0); | |
| 4088 disp($off); | |
| 4089 %} | |
| 4090 %} | |
| 4091 | |
| 4092 // Indirect Memory Plus Long Offset Operand | |
|
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|
4093 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4094 match(AddP off reg); |
| 4095 | |
| 4096 format %{ "[$reg + $off]" %} | |
| 4097 interface(MEMORY_INTER) %{ | |
| 4098 base($reg); | |
| 4099 index(0x4); | |
| 4100 scale(0x0); | |
| 4101 disp($off); | |
| 4102 %} | |
| 4103 %} | |
| 4104 | |
| 4105 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4106 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4107 match(AddP (AddP reg ireg) off); |
| 4108 | |
| 4109 op_cost(10); | |
| 4110 format %{"[$reg + $off + $ireg]" %} | |
| 4111 interface(MEMORY_INTER) %{ | |
| 4112 base($reg); | |
| 4113 index($ireg); | |
| 4114 scale(0x0); | |
| 4115 disp($off); | |
| 4116 %} | |
| 4117 %} | |
| 4118 | |
| 4119 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4120 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4121 match(AddP reg ireg); |
| 4122 | |
| 4123 op_cost(10); | |
| 4124 format %{"[$reg + $ireg]" %} | |
| 4125 interface(MEMORY_INTER) %{ | |
| 4126 base($reg); | |
| 4127 index($ireg); | |
| 4128 scale(0x0); | |
| 4129 disp(0x0); | |
| 4130 %} | |
| 4131 %} | |
| 4132 | |
| 4133 // // ------------------------------------------------------------------------- | |
| 4134 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4135 // // ------------------------------------------------------------------------- | |
| 4136 // // Scaled Memory Operands | |
| 4137 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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|
4138 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4139 // match(AddP off (LShiftI ireg scale)); |
| 4140 // | |
| 4141 // op_cost(10); | |
| 4142 // format %{"[$off + $ireg << $scale]" %} | |
| 4143 // interface(MEMORY_INTER) %{ | |
| 4144 // base(0x4); | |
| 4145 // index($ireg); | |
| 4146 // scale($scale); | |
| 4147 // disp($off); | |
| 4148 // %} | |
| 4149 // %} | |
| 4150 | |
| 4151 // Indirect Memory Times Scale Plus Index Register | |
|
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|
4152 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4153 match(AddP reg (LShiftI ireg scale)); |
| 4154 | |
| 4155 op_cost(10); | |
| 4156 format %{"[$reg + $ireg << $scale]" %} | |
| 4157 interface(MEMORY_INTER) %{ | |
| 4158 base($reg); | |
| 4159 index($ireg); | |
| 4160 scale($scale); | |
| 4161 disp(0x0); | |
| 4162 %} | |
| 4163 %} | |
| 4164 | |
| 4165 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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|
4166 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4167 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4168 | |
| 4169 op_cost(10); | |
| 4170 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4171 interface(MEMORY_INTER) %{ | |
| 4172 base($reg); | |
| 4173 index($ireg); | |
| 4174 scale($scale); | |
| 4175 disp($off); | |
| 4176 %} | |
| 4177 %} | |
| 4178 | |
| 4179 //----------Load Long Memory Operands------------------------------------------ | |
| 4180 // The load-long idiom will use it's address expression again after loading | |
| 4181 // the first word of the long. If the load-long destination overlaps with | |
| 4182 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4183 // from a clobbered address. Fix this by requiring that load-long use | |
| 4184 // address registers that do not overlap with the load-long target. | |
| 4185 | |
| 4186 // load-long support | |
| 4187 operand load_long_RegP() %{ | |
| 4188 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4189 match(RegP); | |
| 4190 match(eSIRegP); | |
| 4191 op_cost(100); | |
| 4192 format %{ %} | |
| 4193 interface(REG_INTER); | |
| 4194 %} | |
| 4195 | |
| 4196 // Indirect Memory Operand Long | |
| 4197 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4198 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4199 match(reg); | |
| 4200 | |
| 4201 format %{ "[$reg]" %} | |
| 4202 interface(MEMORY_INTER) %{ | |
| 4203 base($reg); | |
| 4204 index(0x4); | |
| 4205 scale(0x0); | |
| 4206 disp(0x0); | |
| 4207 %} | |
| 4208 %} | |
| 4209 | |
| 4210 // Indirect Memory Plus Long Offset Operand | |
| 4211 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4212 match(AddP reg off); | |
| 4213 | |
| 4214 format %{ "[$reg + $off]" %} | |
| 4215 interface(MEMORY_INTER) %{ | |
| 4216 base($reg); | |
| 4217 index(0x4); | |
| 4218 scale(0x0); | |
| 4219 disp($off); | |
| 4220 %} | |
| 4221 %} | |
| 4222 | |
| 4223 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4224 | |
| 4225 | |
| 4226 //----------Special Memory Operands-------------------------------------------- | |
| 4227 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4228 // values on the stack where a match requires a value to | |
| 4229 // flow through memory. | |
| 4230 operand stackSlotP(sRegP reg) %{ | |
| 4231 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4232 // No match rule because this operand is only generated in matching | |
| 4233 format %{ "[$reg]" %} | |
| 4234 interface(MEMORY_INTER) %{ | |
| 4235 base(0x4); // ESP | |
| 4236 index(0x4); // No Index | |
| 4237 scale(0x0); // No Scale | |
| 4238 disp($reg); // Stack Offset | |
| 4239 %} | |
| 4240 %} | |
| 4241 | |
| 4242 operand stackSlotI(sRegI reg) %{ | |
| 4243 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4244 // No match rule because this operand is only generated in matching | |
| 4245 format %{ "[$reg]" %} | |
| 4246 interface(MEMORY_INTER) %{ | |
| 4247 base(0x4); // ESP | |
| 4248 index(0x4); // No Index | |
| 4249 scale(0x0); // No Scale | |
| 4250 disp($reg); // Stack Offset | |
| 4251 %} | |
| 4252 %} | |
| 4253 | |
| 4254 operand stackSlotF(sRegF reg) %{ | |
| 4255 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4256 // No match rule because this operand is only generated in matching | |
| 4257 format %{ "[$reg]" %} | |
| 4258 interface(MEMORY_INTER) %{ | |
| 4259 base(0x4); // ESP | |
| 4260 index(0x4); // No Index | |
| 4261 scale(0x0); // No Scale | |
| 4262 disp($reg); // Stack Offset | |
| 4263 %} | |
| 4264 %} | |
| 4265 | |
| 4266 operand stackSlotD(sRegD reg) %{ | |
| 4267 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4268 // No match rule because this operand is only generated in matching | |
| 4269 format %{ "[$reg]" %} | |
| 4270 interface(MEMORY_INTER) %{ | |
| 4271 base(0x4); // ESP | |
| 4272 index(0x4); // No Index | |
| 4273 scale(0x0); // No Scale | |
| 4274 disp($reg); // Stack Offset | |
| 4275 %} | |
| 4276 %} | |
| 4277 | |
| 4278 operand stackSlotL(sRegL reg) %{ | |
| 4279 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4280 // No match rule because this operand is only generated in matching | |
| 4281 format %{ "[$reg]" %} | |
| 4282 interface(MEMORY_INTER) %{ | |
| 4283 base(0x4); // ESP | |
| 4284 index(0x4); // No Index | |
| 4285 scale(0x0); // No Scale | |
| 4286 disp($reg); // Stack Offset | |
| 4287 %} | |
| 4288 %} | |
| 4289 | |
| 4290 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4291 // Indirect Memory Operand | |
| 4292 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4293 %{ | |
|
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|
4294 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4295 match(reg); |
| 4296 | |
| 4297 op_cost(100); | |
| 4298 format %{ "[$reg]" %} | |
| 4299 interface(MEMORY_INTER) %{ | |
| 4300 base($reg); | |
| 4301 index(0x4); | |
| 4302 scale(0x0); | |
| 4303 disp(0x0); | |
| 4304 %} | |
| 4305 %} | |
| 4306 | |
| 4307 // Indirect Memory Plus Short Offset Operand | |
| 4308 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4309 %{ | |
| 4310 match(AddP reg off); | |
| 4311 | |
| 4312 op_cost(100); | |
| 4313 format %{ "[$reg + $off]" %} | |
| 4314 interface(MEMORY_INTER) %{ | |
| 4315 base($reg); | |
| 4316 index(0x4); | |
| 4317 scale(0x0); | |
| 4318 disp($off); | |
| 4319 %} | |
| 4320 %} | |
| 4321 | |
| 4322 // Indirect Memory Plus Long Offset Operand | |
| 4323 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4324 %{ | |
| 4325 match(AddP reg off); | |
| 4326 | |
| 4327 op_cost(100); | |
| 4328 format %{ "[$reg + $off]" %} | |
| 4329 interface(MEMORY_INTER) %{ | |
| 4330 base($reg); | |
| 4331 index(0x4); | |
| 4332 scale(0x0); | |
| 4333 disp($off); | |
| 4334 %} | |
| 4335 %} | |
| 4336 | |
| 4337 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4338 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4339 %{ |
| 4340 match(AddP (AddP reg ireg) off); | |
| 4341 | |
| 4342 op_cost(100); | |
| 4343 format %{"[$reg + $off + $ireg]" %} | |
| 4344 interface(MEMORY_INTER) %{ | |
| 4345 base($reg); | |
| 4346 index($ireg); | |
| 4347 scale(0x0); | |
| 4348 disp($off); | |
| 4349 %} | |
| 4350 %} | |
| 4351 | |
| 4352 // Indirect Memory Times Scale Plus Index Register | |
|
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4353 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4354 %{ |
| 4355 match(AddP reg (LShiftI ireg scale)); | |
| 4356 | |
| 4357 op_cost(100); | |
| 4358 format %{"[$reg + $ireg << $scale]" %} | |
| 4359 interface(MEMORY_INTER) %{ | |
| 4360 base($reg); | |
| 4361 index($ireg); | |
| 4362 scale($scale); | |
| 4363 disp(0x0); | |
| 4364 %} | |
| 4365 %} | |
| 4366 | |
| 4367 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4368 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4369 %{ |
| 4370 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4371 | |
| 4372 op_cost(100); | |
| 4373 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4374 interface(MEMORY_INTER) %{ | |
| 4375 base($reg); | |
| 4376 index($ireg); | |
| 4377 scale($scale); | |
| 4378 disp($off); | |
| 4379 %} | |
| 4380 %} | |
| 4381 | |
| 4382 //----------Conditional Branch Operands---------------------------------------- | |
| 4383 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4384 // the following set of codes: | |
| 4385 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4386 // | |
| 4387 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4388 // by the comparison instruction that sets a condition code flags register. | |
| 4389 // That result is represented by a flags operand whose subtype is appropriate | |
| 4390 // to the unsignedness (etc.) of the comparison. | |
| 4391 // | |
| 4392 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4393 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4394 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4395 | |
| 4396 // Comparision Code | |
| 4397 operand cmpOp() %{ | |
| 4398 match(Bool); | |
| 4399 | |
| 4400 format %{ "" %} | |
| 4401 interface(COND_INTER) %{ | |
|
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4402 equal(0x4, "e"); |
|
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|
4403 not_equal(0x5, "ne"); |
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|
4404 less(0xC, "l"); |
|
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|
4405 greater_equal(0xD, "ge"); |
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|
4406 less_equal(0xE, "le"); |
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|
4407 greater(0xF, "g"); |
| 12323 | 4408 overflow(0x0, "o"); |
| 4409 no_overflow(0x1, "no"); | |
| 0 | 4410 %} |
| 4411 %} | |
| 4412 | |
| 4413 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4414 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4415 // C0 and C3 are turned into Carry & Zero flags. | |
| 4416 operand cmpOpU() %{ | |
| 4417 match(Bool); | |
| 4418 | |
| 4419 format %{ "" %} | |
| 4420 interface(COND_INTER) %{ | |
|
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|
4421 equal(0x4, "e"); |
|
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|
4422 not_equal(0x5, "ne"); |
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|
4423 less(0x2, "b"); |
|
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|
4424 greater_equal(0x3, "nb"); |
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|
4425 less_equal(0x6, "be"); |
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|
4426 greater(0x7, "nbe"); |
| 12323 | 4427 overflow(0x0, "o"); |
| 4428 no_overflow(0x1, "no"); | |
|
415
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|
4429 %} |
|
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|
4430 %} |
|
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|
4431 |
|
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|
4432 // Floating comparisons that don't require any fixup for the unordered case |
|
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4433 operand cmpOpUCF() %{ |
|
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|
4434 match(Bool); |
|
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|
4435 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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|
4436 n->as_Bool()->_test._test == BoolTest::ge || |
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|
4437 n->as_Bool()->_test._test == BoolTest::le || |
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|
4438 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4439 format %{ "" %} |
|
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|
4440 interface(COND_INTER) %{ |
|
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|
4441 equal(0x4, "e"); |
|
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|
4442 not_equal(0x5, "ne"); |
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|
4443 less(0x2, "b"); |
|
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|
4444 greater_equal(0x3, "nb"); |
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|
4445 less_equal(0x6, "be"); |
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|
4446 greater(0x7, "nbe"); |
| 12323 | 4447 overflow(0x0, "o"); |
| 4448 no_overflow(0x1, "no"); | |
|
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|
4449 %} |
|
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|
4450 %} |
|
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|
4451 |
|
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|
4452 |
|
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|
4453 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4454 operand cmpOpUCF2() %{ |
|
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|
4455 match(Bool); |
|
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|
4456 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
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|
4457 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4458 format %{ "" %} |
|
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|
4459 interface(COND_INTER) %{ |
|
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changeset
|
4460 equal(0x4, "e"); |
|
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|
4461 not_equal(0x5, "ne"); |
|
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|
4462 less(0x2, "b"); |
|
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|
4463 greater_equal(0x3, "nb"); |
|
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|
4464 less_equal(0x6, "be"); |
|
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|
4465 greater(0x7, "nbe"); |
| 12323 | 4466 overflow(0x0, "o"); |
| 4467 no_overflow(0x1, "no"); | |
| 0 | 4468 %} |
| 4469 %} | |
| 4470 | |
| 4471 // Comparison Code for FP conditional move | |
| 4472 operand cmpOp_fcmov() %{ | |
| 4473 match(Bool); | |
| 4474 | |
| 12323 | 4475 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4476 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4477 format %{ "" %} |
| 4478 interface(COND_INTER) %{ | |
| 4479 equal (0x0C8); | |
| 4480 not_equal (0x1C8); | |
| 4481 less (0x0C0); | |
| 4482 greater_equal(0x1C0); | |
| 4483 less_equal (0x0D0); | |
| 4484 greater (0x1D0); | |
| 12323 | 4485 overflow(0x0, "o"); // not really supported by the instruction |
| 4486 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4487 %} |
| 4488 %} | |
| 4489 | |
| 4490 // Comparision Code used in long compares | |
| 4491 operand cmpOp_commute() %{ | |
| 4492 match(Bool); | |
| 4493 | |
| 4494 format %{ "" %} | |
| 4495 interface(COND_INTER) %{ | |
|
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|
4496 equal(0x4, "e"); |
|
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changeset
|
4497 not_equal(0x5, "ne"); |
|
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|
4498 less(0xF, "g"); |
|
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|
4499 greater_equal(0xE, "le"); |
|
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|
4500 less_equal(0xD, "ge"); |
|
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|
4501 greater(0xC, "l"); |
| 12323 | 4502 overflow(0x0, "o"); |
| 4503 no_overflow(0x1, "no"); | |
| 0 | 4504 %} |
| 4505 %} | |
| 4506 | |
| 4507 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4508 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4509 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4510 // instructions for every form of operand when the instruction accepts |
| 4511 // multiple operand types with the same basic encoding and format. The classic | |
| 4512 // case of this is memory operands. | |
| 4513 | |
| 4514 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 4515 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4516 | |
| 4517 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 4518 // This means some kind of offset is always required and you cannot use | |
| 4519 // an oop as the offset (done when working on static globals). | |
| 4520 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 4521 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4522 | |
| 4523 | |
| 4524 //----------PIPELINE----------------------------------------------------------- | |
| 4525 // Rules which define the behavior of the target architectures pipeline. | |
| 4526 pipeline %{ | |
| 4527 | |
| 4528 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4529 attributes %{ | |
| 4530 variable_size_instructions; // Fixed size instructions | |
| 4531 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4532 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4533 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4534 instruction_fetch_units = 1; // of 16 bytes | |
| 4535 | |
| 4536 // List of nop instructions | |
| 4537 nops( MachNop ); | |
| 4538 %} | |
| 4539 | |
| 4540 //----------RESOURCES---------------------------------------------------------- | |
| 4541 // Resources are the functional units available to the machine | |
| 4542 | |
| 4543 // Generic P2/P3 pipeline | |
| 4544 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4545 // 3 instructions decoded per cycle. | |
| 4546 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4547 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 4548 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4549 MS0, MS1, MEM = MS0 | MS1, | |
| 4550 BR, FPU, | |
| 4551 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 4552 | |
| 4553 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4554 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4555 | |
| 4556 // Generic P2/P3 pipeline | |
| 4557 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4558 | |
| 4559 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4560 // Pipeline Classes describe the stages in which input and output are | |
| 4561 // referenced by the hardware pipeline. | |
| 4562 | |
| 4563 // Naming convention: ialu or fpu | |
| 4564 // Then: _reg | |
| 4565 // Then: _reg if there is a 2nd register | |
| 4566 // Then: _long if it's a pair of instructions implementing a long | |
| 4567 // Then: _fat if it requires the big decoder | |
| 4568 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4569 | |
| 4570 // Integer ALU reg operation | |
|
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|
4571 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 4572 single_instruction; |
| 4573 dst : S4(write); | |
| 4574 dst : S3(read); | |
| 4575 DECODE : S0; // any decoder | |
| 4576 ALU : S3; // any alu | |
| 4577 %} | |
| 4578 | |
| 4579 // Long ALU reg operation | |
| 4580 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 4581 instruction_count(2); | |
| 4582 dst : S4(write); | |
| 4583 dst : S3(read); | |
| 4584 DECODE : S0(2); // any 2 decoders | |
| 4585 ALU : S3(2); // both alus | |
| 4586 %} | |
| 4587 | |
| 4588 // Integer ALU reg operation using big decoder | |
|
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|
4589 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 4590 single_instruction; |
| 4591 dst : S4(write); | |
| 4592 dst : S3(read); | |
| 4593 D0 : S0; // big decoder only | |
| 4594 ALU : S3; // any alu | |
| 4595 %} | |
| 4596 | |
| 4597 // Long ALU reg operation using big decoder | |
| 4598 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 4599 instruction_count(2); | |
| 4600 dst : S4(write); | |
| 4601 dst : S3(read); | |
| 4602 D0 : S0(2); // big decoder only; twice | |
| 4603 ALU : S3(2); // any 2 alus | |
| 4604 %} | |
| 4605 | |
| 4606 // Integer ALU reg-reg operation | |
|
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4607 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 4608 single_instruction; |
| 4609 dst : S4(write); | |
| 4610 src : S3(read); | |
| 4611 DECODE : S0; // any decoder | |
| 4612 ALU : S3; // any alu | |
| 4613 %} | |
| 4614 | |
| 4615 // Long ALU reg-reg operation | |
| 4616 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 4617 instruction_count(2); | |
| 4618 dst : S4(write); | |
| 4619 src : S3(read); | |
| 4620 DECODE : S0(2); // any 2 decoders | |
| 4621 ALU : S3(2); // both alus | |
| 4622 %} | |
| 4623 | |
| 4624 // Integer ALU reg-reg operation | |
|
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4625 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 4626 single_instruction; |
| 4627 dst : S4(write); | |
| 4628 src : S3(read); | |
| 4629 D0 : S0; // big decoder only | |
| 4630 ALU : S3; // any alu | |
| 4631 %} | |
| 4632 | |
| 4633 // Long ALU reg-reg operation | |
| 4634 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 4635 instruction_count(2); | |
| 4636 dst : S4(write); | |
| 4637 src : S3(read); | |
| 4638 D0 : S0(2); // big decoder only; twice | |
| 4639 ALU : S3(2); // both alus | |
| 4640 %} | |
| 4641 | |
| 4642 // Integer ALU reg-mem operation | |
|
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4643 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 4644 single_instruction; |
| 4645 dst : S5(write); | |
| 4646 mem : S3(read); | |
| 4647 D0 : S0; // big decoder only | |
| 4648 ALU : S4; // any alu | |
| 4649 MEM : S3; // any mem | |
| 4650 %} | |
| 4651 | |
| 4652 // Long ALU reg-mem operation | |
| 4653 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 4654 instruction_count(2); | |
| 4655 dst : S5(write); | |
| 4656 mem : S3(read); | |
| 4657 D0 : S0(2); // big decoder only; twice | |
| 4658 ALU : S4(2); // any 2 alus | |
| 4659 MEM : S3(2); // both mems | |
| 4660 %} | |
| 4661 | |
| 4662 // Integer mem operation (prefetch) | |
| 4663 pipe_class ialu_mem(memory mem) | |
| 4664 %{ | |
| 4665 single_instruction; | |
| 4666 mem : S3(read); | |
| 4667 D0 : S0; // big decoder only | |
| 4668 MEM : S3; // any mem | |
| 4669 %} | |
| 4670 | |
| 4671 // Integer Store to Memory | |
|
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4672 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 4673 single_instruction; |
| 4674 mem : S3(read); | |
| 4675 src : S5(read); | |
| 4676 D0 : S0; // big decoder only | |
| 4677 ALU : S4; // any alu | |
| 4678 MEM : S3; | |
| 4679 %} | |
| 4680 | |
| 4681 // Long Store to Memory | |
| 4682 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 4683 instruction_count(2); | |
| 4684 mem : S3(read); | |
| 4685 src : S5(read); | |
| 4686 D0 : S0(2); // big decoder only; twice | |
| 4687 ALU : S4(2); // any 2 alus | |
| 4688 MEM : S3(2); // Both mems | |
| 4689 %} | |
| 4690 | |
| 4691 // Integer Store to Memory | |
| 4692 pipe_class ialu_mem_imm(memory mem) %{ | |
| 4693 single_instruction; | |
| 4694 mem : S3(read); | |
| 4695 D0 : S0; // big decoder only | |
| 4696 ALU : S4; // any alu | |
| 4697 MEM : S3; | |
| 4698 %} | |
| 4699 | |
| 4700 // Integer ALU0 reg-reg operation | |
|
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4701 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 4702 single_instruction; |
| 4703 dst : S4(write); | |
| 4704 src : S3(read); | |
| 4705 D0 : S0; // Big decoder only | |
| 4706 ALU0 : S3; // only alu0 | |
| 4707 %} | |
| 4708 | |
| 4709 // Integer ALU0 reg-mem operation | |
|
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4710 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 4711 single_instruction; |
| 4712 dst : S5(write); | |
| 4713 mem : S3(read); | |
| 4714 D0 : S0; // big decoder only | |
| 4715 ALU0 : S4; // ALU0 only | |
| 4716 MEM : S3; // any mem | |
| 4717 %} | |
| 4718 | |
| 4719 // Integer ALU reg-reg operation | |
|
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4720 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 4721 single_instruction; |
| 4722 cr : S4(write); | |
| 4723 src1 : S3(read); | |
| 4724 src2 : S3(read); | |
| 4725 DECODE : S0; // any decoder | |
| 4726 ALU : S3; // any alu | |
| 4727 %} | |
| 4728 | |
| 4729 // Integer ALU reg-imm operation | |
|
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4730 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 4731 single_instruction; |
| 4732 cr : S4(write); | |
| 4733 src1 : S3(read); | |
| 4734 DECODE : S0; // any decoder | |
| 4735 ALU : S3; // any alu | |
| 4736 %} | |
| 4737 | |
| 4738 // Integer ALU reg-mem operation | |
|
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4739 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 4740 single_instruction; |
| 4741 cr : S4(write); | |
| 4742 src1 : S3(read); | |
| 4743 src2 : S3(read); | |
| 4744 D0 : S0; // big decoder only | |
| 4745 ALU : S4; // any alu | |
| 4746 MEM : S3; | |
| 4747 %} | |
| 4748 | |
| 4749 // Conditional move reg-reg | |
|
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4750 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 4751 instruction_count(4); |
| 4752 y : S4(read); | |
| 4753 q : S3(read); | |
| 4754 p : S3(read); | |
| 4755 DECODE : S0(4); // any decoder | |
| 4756 %} | |
| 4757 | |
| 4758 // Conditional move reg-reg | |
|
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4759 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 4760 single_instruction; |
| 4761 dst : S4(write); | |
| 4762 src : S3(read); | |
| 4763 cr : S3(read); | |
| 4764 DECODE : S0; // any decoder | |
| 4765 %} | |
| 4766 | |
| 4767 // Conditional move reg-mem | |
|
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4768 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 4769 single_instruction; |
| 4770 dst : S4(write); | |
| 4771 src : S3(read); | |
| 4772 cr : S3(read); | |
| 4773 DECODE : S0; // any decoder | |
| 4774 MEM : S3; | |
| 4775 %} | |
| 4776 | |
| 4777 // Conditional move reg-reg long | |
| 4778 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 4779 single_instruction; | |
| 4780 dst : S4(write); | |
| 4781 src : S3(read); | |
| 4782 cr : S3(read); | |
| 4783 DECODE : S0(2); // any 2 decoders | |
| 4784 %} | |
| 4785 | |
| 4786 // Conditional move double reg-reg | |
|
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4787 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 4788 single_instruction; |
| 4789 dst : S4(write); | |
| 4790 src : S3(read); | |
| 4791 cr : S3(read); | |
| 4792 DECODE : S0; // any decoder | |
| 4793 %} | |
| 4794 | |
| 4795 // Float reg-reg operation | |
|
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4796 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 4797 instruction_count(2); |
| 4798 dst : S3(read); | |
| 4799 DECODE : S0(2); // any 2 decoders | |
| 4800 FPU : S3; | |
| 4801 %} | |
| 4802 | |
| 4803 // Float reg-reg operation | |
|
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4804 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 4805 instruction_count(2); |
| 4806 dst : S4(write); | |
| 4807 src : S3(read); | |
| 4808 DECODE : S0(2); // any 2 decoders | |
| 4809 FPU : S3; | |
| 4810 %} | |
| 4811 | |
| 4812 // Float reg-reg operation | |
|
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4813 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 4814 instruction_count(3); |
| 4815 dst : S4(write); | |
| 4816 src1 : S3(read); | |
| 4817 src2 : S3(read); | |
| 4818 DECODE : S0(3); // any 3 decoders | |
| 4819 FPU : S3(2); | |
| 4820 %} | |
| 4821 | |
| 4822 // Float reg-reg operation | |
|
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4823 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 4824 instruction_count(4); |
| 4825 dst : S4(write); | |
| 4826 src1 : S3(read); | |
| 4827 src2 : S3(read); | |
| 4828 src3 : S3(read); | |
| 4829 DECODE : S0(4); // any 3 decoders | |
| 4830 FPU : S3(2); | |
| 4831 %} | |
| 4832 | |
| 4833 // Float reg-reg operation | |
|
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4834 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 4835 instruction_count(4); |
| 4836 dst : S4(write); | |
| 4837 src1 : S3(read); | |
| 4838 src2 : S3(read); | |
| 4839 src3 : S3(read); | |
| 4840 DECODE : S1(3); // any 3 decoders | |
| 4841 D0 : S0; // Big decoder only | |
| 4842 FPU : S3(2); | |
| 4843 MEM : S3; | |
| 4844 %} | |
| 4845 | |
| 4846 // Float reg-mem operation | |
|
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4847 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 4848 instruction_count(2); |
| 4849 dst : S5(write); | |
| 4850 mem : S3(read); | |
| 4851 D0 : S0; // big decoder only | |
| 4852 DECODE : S1; // any decoder for FPU POP | |
| 4853 FPU : S4; | |
| 4854 MEM : S3; // any mem | |
| 4855 %} | |
| 4856 | |
| 4857 // Float reg-mem operation | |
|
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4858 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 4859 instruction_count(3); |
| 4860 dst : S5(write); | |
| 4861 src1 : S3(read); | |
| 4862 mem : S3(read); | |
| 4863 D0 : S0; // big decoder only | |
| 4864 DECODE : S1(2); // any decoder for FPU POP | |
| 4865 FPU : S4; | |
| 4866 MEM : S3; // any mem | |
| 4867 %} | |
| 4868 | |
| 4869 // Float mem-reg operation | |
|
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4870 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 4871 instruction_count(2); |
| 4872 src : S5(read); | |
| 4873 mem : S3(read); | |
| 4874 DECODE : S0; // any decoder for FPU PUSH | |
| 4875 D0 : S1; // big decoder only | |
| 4876 FPU : S4; | |
| 4877 MEM : S3; // any mem | |
| 4878 %} | |
| 4879 | |
|
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4880 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 4881 instruction_count(3); |
| 4882 src1 : S3(read); | |
| 4883 src2 : S3(read); | |
| 4884 mem : S3(read); | |
| 4885 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4886 D0 : S1; // big decoder only | |
| 4887 FPU : S4; | |
| 4888 MEM : S3; // any mem | |
| 4889 %} | |
| 4890 | |
|
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4891 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 4892 instruction_count(3); |
| 4893 src1 : S3(read); | |
| 4894 src2 : S3(read); | |
| 4895 mem : S4(read); | |
| 4896 DECODE : S0; // any decoder for FPU PUSH | |
| 4897 D0 : S0(2); // big decoder only | |
| 4898 FPU : S4; | |
| 4899 MEM : S3(2); // any mem | |
| 4900 %} | |
| 4901 | |
| 4902 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 4903 instruction_count(2); | |
| 4904 src1 : S3(read); | |
| 4905 dst : S4(read); | |
| 4906 D0 : S0(2); // big decoder only | |
| 4907 MEM : S3(2); // any mem | |
| 4908 %} | |
| 4909 | |
| 4910 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 4911 instruction_count(3); | |
| 4912 src1 : S3(read); | |
| 4913 src2 : S3(read); | |
| 4914 dst : S4(read); | |
| 4915 D0 : S0(3); // big decoder only | |
| 4916 FPU : S4; | |
| 4917 MEM : S3(3); // any mem | |
| 4918 %} | |
| 4919 | |
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4920 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 4921 instruction_count(3); |
| 4922 src1 : S4(read); | |
| 4923 mem : S4(read); | |
| 4924 DECODE : S0; // any decoder for FPU PUSH | |
| 4925 D0 : S0(2); // big decoder only | |
| 4926 FPU : S4; | |
| 4927 MEM : S3(2); // any mem | |
| 4928 %} | |
| 4929 | |
| 4930 // Float load constant | |
|
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4931 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 4932 instruction_count(2); |
| 4933 dst : S5(write); | |
| 4934 D0 : S0; // big decoder only for the load | |
| 4935 DECODE : S1; // any decoder for FPU POP | |
| 4936 FPU : S4; | |
| 4937 MEM : S3; // any mem | |
| 4938 %} | |
| 4939 | |
| 4940 // Float load constant | |
|
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4941 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 4942 instruction_count(3); |
| 4943 dst : S5(write); | |
| 4944 src : S3(read); | |
| 4945 D0 : S0; // big decoder only for the load | |
| 4946 DECODE : S1(2); // any decoder for FPU POP | |
| 4947 FPU : S4; | |
| 4948 MEM : S3; // any mem | |
| 4949 %} | |
| 4950 | |
| 4951 // UnConditional branch | |
| 4952 pipe_class pipe_jmp( label labl ) %{ | |
| 4953 single_instruction; | |
| 4954 BR : S3; | |
| 4955 %} | |
| 4956 | |
| 4957 // Conditional branch | |
| 4958 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 4959 single_instruction; | |
| 4960 cr : S1(read); | |
| 4961 BR : S3; | |
| 4962 %} | |
| 4963 | |
| 4964 // Allocation idiom | |
| 4965 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 4966 instruction_count(1); force_serialization; | |
| 4967 fixed_latency(6); | |
| 4968 heap_ptr : S3(read); | |
| 4969 DECODE : S0(3); | |
| 4970 D0 : S2; | |
| 4971 MEM : S3; | |
| 4972 ALU : S3(2); | |
| 4973 dst : S5(write); | |
| 4974 BR : S5; | |
| 4975 %} | |
| 4976 | |
| 4977 // Generic big/slow expanded idiom | |
| 4978 pipe_class pipe_slow( ) %{ | |
| 4979 instruction_count(10); multiple_bundles; force_serialization; | |
| 4980 fixed_latency(100); | |
| 4981 D0 : S0(2); | |
| 4982 MEM : S3(2); | |
| 4983 %} | |
| 4984 | |
| 4985 // The real do-nothing guy | |
| 4986 pipe_class empty( ) %{ | |
| 4987 instruction_count(0); | |
| 4988 %} | |
| 4989 | |
| 4990 // Define the class for the Nop node | |
| 4991 define %{ | |
| 4992 MachNop = empty; | |
| 4993 %} | |
| 4994 | |
| 4995 %} | |
| 4996 | |
| 4997 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4998 // | |
| 4999 // match -- States which machine-independent subtree may be replaced | |
| 5000 // by this instruction. | |
| 5001 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5002 // selection to identify a minimum cost tree of machine | |
| 5003 // instructions that matches a tree of machine-independent | |
| 5004 // instructions. | |
| 5005 // format -- A string providing the disassembly for this instruction. | |
| 5006 // The value of an instruction's operand may be inserted | |
| 5007 // by referring to it with a '$' prefix. | |
| 5008 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5009 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5010 // respectively. The primary opcode is commonly used to | |
| 5011 // indicate the type of machine instruction, while secondary | |
| 5012 // and tertiary are often used for prefix options or addressing | |
| 5013 // modes. | |
| 5014 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5015 // name must have been defined in an 'enc_class' specification | |
| 5016 // in the encode section of the architecture description. | |
| 5017 | |
| 5018 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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5019 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5020 match(Set dst (ReverseBytesI dst)); |
| 5021 | |
| 5022 format %{ "BSWAP $dst" %} | |
| 5023 opcode(0x0F, 0xC8); | |
| 5024 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5025 ins_pipe( ialu_reg ); | |
| 5026 %} | |
| 5027 | |
| 5028 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5029 match(Set dst (ReverseBytesL dst)); | |
| 5030 | |
| 5031 format %{ "BSWAP $dst.lo\n\t" | |
| 5032 "BSWAP $dst.hi\n\t" | |
| 5033 "XCHG $dst.lo $dst.hi" %} | |
| 5034 | |
| 5035 ins_cost(125); | |
| 5036 ins_encode( bswap_long_bytes(dst) ); | |
| 5037 ins_pipe( ialu_reg_reg); | |
| 5038 %} | |
| 5039 | |
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changeset
|
5040 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5041 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5042 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5043 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5044 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5045 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5046 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5047 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5048 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5049 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5050 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5051 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5052 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5053 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5054 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5055 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5056 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5057 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5058 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5059 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5060 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5061 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5062 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5063 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5064 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5065 |
| 0 | 5066 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5067 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5068 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5069 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5070 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5071 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5072 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5073 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5074 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5075 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5076 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5077 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5078 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5079 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5080 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5081 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5082 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5083 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5084 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5085 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5086 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5087 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5088 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5089 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5090 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5091 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5092 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5093 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5094 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5095 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5096 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5097 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5098 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5099 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5100 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5101 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5102 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5103 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5104 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5105 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5106 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5107 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5108 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5109 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5110 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5111 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5112 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5113 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5114 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5115 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5116 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5117 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5118 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5119 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5120 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5121 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5122 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5123 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5124 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5125 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5126 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5127 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5128 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5129 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5130 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5131 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5132 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5133 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5134 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5135 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5136 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5137 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5138 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5139 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5140 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5141 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5142 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5143 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5144 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5145 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5146 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5147 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5148 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5149 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5150 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5151 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5152 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5153 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5154 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5155 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5156 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5157 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5158 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5159 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5160 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5161 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5162 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5163 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5164 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5165 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5166 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5167 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5168 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5169 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5170 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5171 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5172 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5173 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5174 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5175 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5176 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5177 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5178 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5179 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5180 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5181 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5182 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5183 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5184 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5185 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5186 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5187 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5188 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5189 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5190 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5191 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5192 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5193 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5194 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5195 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5196 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5197 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5198 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5199 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5200 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5201 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5202 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5203 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5204 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5205 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5206 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5207 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5208 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5209 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5210 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5211 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5212 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5213 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5214 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5215 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5216 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5217 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5218 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5219 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5220 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5221 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5222 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5223 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5224 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5225 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5226 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5227 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5228 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5229 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5230 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5231 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5232 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5233 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5234 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5235 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5236 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5237 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5238 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5239 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5240 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5241 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5242 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5243 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5244 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5245 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5246 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5247 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5248 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5249 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5250 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5251 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5252 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5253 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5254 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5255 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5256 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5257 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
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5258 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
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5259 predicate(UsePopCountInstruction); |
|
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5260 match(Set dst (PopCountL (LoadL mem))); |
|
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|
5261 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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5262 |
|
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|
5263 format %{ "POPCNT $dst, $mem\n\t" |
|
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5264 "POPCNT $tmp, $mem+4\n\t" |
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5265 "ADD $dst, $tmp" %} |
|
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|
5266 ins_encode %{ |
|
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5267 //__ popcntl($dst$$Register, $mem$$Address$$first); |
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5268 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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5269 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
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5270 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
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5271 __ addl($dst$$Register, $tmp$$Register); |
|
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|
5272 %} |
|
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|
5273 ins_pipe(ialu_reg); |
|
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|
5274 %} |
|
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|
5275 |
|
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|
5276 |
| 0 | 5277 //----------Load/Store/Move Instructions--------------------------------------- |
| 5278 //----------Load Instructions-------------------------------------------------- | |
| 5279 // Load Byte (8bit signed) | |
| 5280 instruct loadB(xRegI dst, memory mem) %{ | |
| 5281 match(Set dst (LoadB mem)); | |
| 5282 | |
| 5283 ins_cost(125); | |
| 624 | 5284 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5285 | |
| 5286 ins_encode %{ | |
| 5287 __ movsbl($dst$$Register, $mem$$Address); | |
| 5288 %} | |
| 5289 | |
| 5290 ins_pipe(ialu_reg_mem); | |
| 5291 %} | |
| 5292 | |
| 5293 // Load Byte (8bit signed) into Long Register | |
| 824 | 5294 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5295 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5296 effect(KILL cr); |
| 624 | 5297 |
| 5298 ins_cost(375); | |
| 5299 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5300 "MOV $dst.hi,$dst.lo\n\t" | |
| 5301 "SAR $dst.hi,7" %} | |
| 5302 | |
| 5303 ins_encode %{ | |
| 5304 __ movsbl($dst$$Register, $mem$$Address); | |
| 5305 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5306 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5307 %} | |
| 5308 | |
| 5309 ins_pipe(ialu_reg_mem); | |
| 5310 %} | |
| 5311 | |
| 5312 // Load Unsigned Byte (8bit UNsigned) | |
| 5313 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5314 match(Set dst (LoadUB mem)); | |
| 0 | 5315 |
| 5316 ins_cost(125); | |
| 624 | 5317 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5318 | |
| 5319 ins_encode %{ | |
| 5320 __ movzbl($dst$$Register, $mem$$Address); | |
| 5321 %} | |
| 5322 | |
| 5323 ins_pipe(ialu_reg_mem); | |
| 5324 %} | |
| 5325 | |
| 5326 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5327 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5328 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5329 effect(KILL cr); |
| 624 | 5330 |
| 5331 ins_cost(250); | |
| 5332 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5333 "XOR $dst.hi,$dst.hi" %} | |
| 5334 | |
| 5335 ins_encode %{ | |
| 824 | 5336 Register Rdst = $dst$$Register; |
| 5337 __ movzbl(Rdst, $mem$$Address); | |
| 5338 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5339 %} | |
| 5340 | |
| 5341 ins_pipe(ialu_reg_mem); | |
| 5342 %} | |
| 5343 | |
| 5344 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5345 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5346 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5347 effect(KILL cr); | |
| 5348 | |
| 5349 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5350 "XOR $dst.hi,$dst.hi\n\t" | |
| 5351 "AND $dst.lo,$mask" %} | |
| 5352 ins_encode %{ | |
| 5353 Register Rdst = $dst$$Register; | |
| 5354 __ movzbl(Rdst, $mem$$Address); | |
| 5355 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5356 __ andl(Rdst, $mask$$constant); | |
| 5357 %} | |
| 624 | 5358 ins_pipe(ialu_reg_mem); |
| 5359 %} | |
| 5360 | |
| 5361 // Load Short (16bit signed) | |
|
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5362 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5363 match(Set dst (LoadS mem)); |
| 5364 | |
| 5365 ins_cost(125); | |
| 5366 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5367 | |
| 5368 ins_encode %{ | |
| 5369 __ movswl($dst$$Register, $mem$$Address); | |
| 5370 %} | |
| 5371 | |
| 5372 ins_pipe(ialu_reg_mem); | |
| 5373 %} | |
| 5374 | |
| 785 | 5375 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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|
5376 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5377 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5378 | |
| 5379 ins_cost(125); | |
| 5380 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5381 ins_encode %{ | |
| 5382 __ movsbl($dst$$Register, $mem$$Address); | |
| 5383 %} | |
| 5384 ins_pipe(ialu_reg_mem); | |
| 5385 %} | |
| 5386 | |
| 624 | 5387 // Load Short (16bit signed) into Long Register |
| 824 | 5388 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5389 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5390 effect(KILL cr); |
| 624 | 5391 |
| 5392 ins_cost(375); | |
| 5393 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5394 "MOV $dst.hi,$dst.lo\n\t" | |
| 5395 "SAR $dst.hi,15" %} | |
| 5396 | |
| 5397 ins_encode %{ | |
| 5398 __ movswl($dst$$Register, $mem$$Address); | |
| 5399 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5400 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5401 %} | |
| 5402 | |
| 5403 ins_pipe(ialu_reg_mem); | |
| 0 | 5404 %} |
| 5405 | |
|
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|
5406 // Load Unsigned Short/Char (16bit unsigned) |
|
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|
5407 instruct loadUS(rRegI dst, memory mem) %{ |
|
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|
5408 match(Set dst (LoadUS mem)); |
| 0 | 5409 |
| 5410 ins_cost(125); | |
| 624 | 5411 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5412 | |
| 5413 ins_encode %{ | |
| 5414 __ movzwl($dst$$Register, $mem$$Address); | |
| 5415 %} | |
| 5416 | |
| 5417 ins_pipe(ialu_reg_mem); | |
| 5418 %} | |
| 5419 | |
| 785 | 5420 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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|
5421 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5422 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5423 | |
| 5424 ins_cost(125); | |
| 5425 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5426 ins_encode %{ | |
| 5427 __ movsbl($dst$$Register, $mem$$Address); | |
| 5428 %} | |
| 5429 ins_pipe(ialu_reg_mem); | |
| 5430 %} | |
| 5431 | |
| 624 | 5432 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5433 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5434 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5435 effect(KILL cr); |
| 624 | 5436 |
| 5437 ins_cost(250); | |
| 5438 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5439 "XOR $dst.hi,$dst.hi" %} | |
| 5440 | |
| 5441 ins_encode %{ | |
| 5442 __ movzwl($dst$$Register, $mem$$Address); | |
| 5443 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5444 %} | |
| 5445 | |
| 5446 ins_pipe(ialu_reg_mem); | |
| 0 | 5447 %} |
| 5448 | |
| 824 | 5449 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5450 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5451 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5452 effect(KILL cr); | |
| 5453 | |
| 5454 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5455 "XOR $dst.hi,$dst.hi" %} | |
| 5456 ins_encode %{ | |
| 5457 Register Rdst = $dst$$Register; | |
| 5458 __ movzbl(Rdst, $mem$$Address); | |
| 5459 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5460 %} | |
| 5461 ins_pipe(ialu_reg_mem); | |
| 5462 %} | |
| 5463 | |
| 5464 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5465 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5466 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5467 effect(KILL cr); | |
| 5468 | |
| 5469 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5470 "XOR $dst.hi,$dst.hi\n\t" | |
| 5471 "AND $dst.lo,$mask" %} | |
| 5472 ins_encode %{ | |
| 5473 Register Rdst = $dst$$Register; | |
| 5474 __ movzwl(Rdst, $mem$$Address); | |
| 5475 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5476 __ andl(Rdst, $mask$$constant); | |
| 5477 %} | |
| 5478 ins_pipe(ialu_reg_mem); | |
| 5479 %} | |
| 5480 | |
| 0 | 5481 // Load Integer |
|
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|
5482 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5483 match(Set dst (LoadI mem)); |
| 5484 | |
| 5485 ins_cost(125); | |
| 624 | 5486 format %{ "MOV $dst,$mem\t# int" %} |
| 5487 | |
| 5488 ins_encode %{ | |
| 5489 __ movl($dst$$Register, $mem$$Address); | |
| 5490 %} | |
| 5491 | |
| 5492 ins_pipe(ialu_reg_mem); | |
| 5493 %} | |
| 5494 | |
| 785 | 5495 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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|
5496 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5497 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5498 | |
| 5499 ins_cost(125); | |
| 5500 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5501 ins_encode %{ | |
| 5502 __ movsbl($dst$$Register, $mem$$Address); | |
| 5503 %} | |
| 5504 ins_pipe(ialu_reg_mem); | |
| 5505 %} | |
| 5506 | |
| 5507 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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|
5508 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 5509 match(Set dst (AndI (LoadI mem) mask)); |
| 5510 | |
| 5511 ins_cost(125); | |
| 5512 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 5513 ins_encode %{ | |
| 5514 __ movzbl($dst$$Register, $mem$$Address); | |
| 5515 %} | |
| 5516 ins_pipe(ialu_reg_mem); | |
| 5517 %} | |
| 5518 | |
| 5519 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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|
5520 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 5521 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 5522 | |
| 5523 ins_cost(125); | |
| 5524 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 5525 ins_encode %{ | |
| 5526 __ movswl($dst$$Register, $mem$$Address); | |
| 5527 %} | |
| 5528 ins_pipe(ialu_reg_mem); | |
| 5529 %} | |
| 5530 | |
| 5531 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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|
5532 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 5533 match(Set dst (AndI (LoadI mem) mask)); |
| 5534 | |
| 5535 ins_cost(125); | |
| 5536 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 5537 ins_encode %{ | |
| 5538 __ movzwl($dst$$Register, $mem$$Address); | |
| 5539 %} | |
| 5540 ins_pipe(ialu_reg_mem); | |
| 5541 %} | |
| 5542 | |
| 624 | 5543 // Load Integer into Long Register |
| 824 | 5544 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5545 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 5546 effect(KILL cr); |
| 624 | 5547 |
| 5548 ins_cost(375); | |
| 5549 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 5550 "MOV $dst.hi,$dst.lo\n\t" | |
| 5551 "SAR $dst.hi,31" %} | |
| 5552 | |
| 5553 ins_encode %{ | |
| 5554 __ movl($dst$$Register, $mem$$Address); | |
| 5555 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5556 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 5557 %} | |
| 5558 | |
| 5559 ins_pipe(ialu_reg_mem); | |
| 5560 %} | |
| 5561 | |
| 824 | 5562 // Load Integer with mask 0xFF into Long Register |
| 5563 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5564 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5565 effect(KILL cr); | |
| 5566 | |
| 5567 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 5568 "XOR $dst.hi,$dst.hi" %} | |
| 5569 ins_encode %{ | |
| 5570 Register Rdst = $dst$$Register; | |
| 5571 __ movzbl(Rdst, $mem$$Address); | |
| 5572 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5573 %} | |
| 5574 ins_pipe(ialu_reg_mem); | |
| 5575 %} | |
| 5576 | |
| 5577 // Load Integer with mask 0xFFFF into Long Register | |
| 5578 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 5579 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5580 effect(KILL cr); | |
| 5581 | |
| 5582 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 5583 "XOR $dst.hi,$dst.hi" %} | |
| 5584 ins_encode %{ | |
| 5585 Register Rdst = $dst$$Register; | |
| 5586 __ movzwl(Rdst, $mem$$Address); | |
| 5587 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5588 %} | |
| 5589 ins_pipe(ialu_reg_mem); | |
| 5590 %} | |
| 5591 | |
|
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|
5592 // Load Integer with 31-bit mask into Long Register |
|
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|
5593 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 5594 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5595 effect(KILL cr); | |
| 5596 | |
|
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|
5597 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5598 "XOR $dst.hi,$dst.hi\n\t" |
| 5599 "AND $dst.lo,$mask" %} | |
| 5600 ins_encode %{ | |
| 5601 Register Rdst = $dst$$Register; | |
| 5602 __ movl(Rdst, $mem$$Address); | |
| 5603 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5604 __ andl(Rdst, $mask$$constant); | |
| 5605 %} | |
| 5606 ins_pipe(ialu_reg_mem); | |
| 5607 %} | |
| 5608 | |
| 624 | 5609 // Load Unsigned Integer into Long Register |
| 6849 | 5610 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 5611 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 5612 effect(KILL cr); |
| 624 | 5613 |
| 5614 ins_cost(250); | |
| 5615 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 5616 "XOR $dst.hi,$dst.hi" %} | |
| 5617 | |
| 5618 ins_encode %{ | |
| 5619 __ movl($dst$$Register, $mem$$Address); | |
| 5620 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5621 %} | |
| 5622 | |
| 5623 ins_pipe(ialu_reg_mem); | |
| 0 | 5624 %} |
| 5625 | |
| 5626 // Load Long. Cannot clobber address while loading, so restrict address | |
| 5627 // register to ESI | |
| 5628 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 5629 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 5630 match(Set dst (LoadL mem)); | |
| 5631 | |
| 5632 ins_cost(250); | |
| 624 | 5633 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 5634 "MOV $dst.hi,$mem+4" %} |
| 624 | 5635 |
| 5636 ins_encode %{ | |
|
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5637 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
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5638 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 5639 __ movl($dst$$Register, Amemlo); |
| 5640 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 5641 %} | |
| 5642 | |
| 5643 ins_pipe(ialu_reg_long_mem); | |
| 0 | 5644 %} |
| 5645 | |
| 5646 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 5647 // then store it down to the stack and reload on the int | |
| 5648 // side. | |
| 5649 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 5650 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 5651 match(Set dst (LoadL mem)); | |
| 5652 | |
| 5653 ins_cost(200); | |
| 5654 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 5655 "FISTp $dst" %} | |
| 5656 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 5657 ins_pipe( fpu_reg_mem ); | |
| 5658 %} | |
| 5659 | |
|
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5660 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 5661 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5662 match(Set dst (LoadL mem)); | |
| 5663 effect(TEMP tmp); | |
| 5664 ins_cost(180); | |
| 5665 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5666 "MOVSD $dst,$tmp" %} | |
| 4759 | 5667 ins_encode %{ |
| 5668 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5669 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 5670 %} | |
| 0 | 5671 ins_pipe( pipe_slow ); |
| 5672 %} | |
| 5673 | |
|
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5674 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 5675 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5676 match(Set dst (LoadL mem)); | |
| 5677 effect(TEMP tmp); | |
| 5678 ins_cost(160); | |
| 5679 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5680 "MOVD $dst.lo,$tmp\n\t" | |
| 5681 "PSRLQ $tmp,32\n\t" | |
| 5682 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 5683 ins_encode %{ |
| 5684 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5685 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 5686 __ psrlq($tmp$$XMMRegister, 32); | |
| 5687 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 5688 %} | |
| 0 | 5689 ins_pipe( pipe_slow ); |
| 5690 %} | |
| 5691 | |
| 5692 // Load Range | |
|
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5693 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 5694 match(Set dst (LoadRange mem)); |
| 5695 | |
| 5696 ins_cost(125); | |
| 5697 format %{ "MOV $dst,$mem" %} | |
| 5698 opcode(0x8B); | |
| 5699 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5700 ins_pipe( ialu_reg_mem ); | |
| 5701 %} | |
| 5702 | |
| 5703 | |
| 5704 // Load Pointer | |
| 5705 instruct loadP(eRegP dst, memory mem) %{ | |
| 5706 match(Set dst (LoadP mem)); | |
| 5707 | |
| 5708 ins_cost(125); | |
| 5709 format %{ "MOV $dst,$mem" %} | |
| 5710 opcode(0x8B); | |
| 5711 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5712 ins_pipe( ialu_reg_mem ); | |
| 5713 %} | |
| 5714 | |
| 5715 // Load Klass Pointer | |
| 5716 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 5717 match(Set dst (LoadKlass mem)); | |
| 5718 | |
| 5719 ins_cost(125); | |
| 5720 format %{ "MOV $dst,$mem" %} | |
| 5721 opcode(0x8B); | |
| 5722 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5723 ins_pipe( ialu_reg_mem ); | |
| 5724 %} | |
| 5725 | |
| 5726 // Load Double | |
|
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5727 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 5728 predicate(UseSSE<=1); |
| 5729 match(Set dst (LoadD mem)); | |
| 5730 | |
| 5731 ins_cost(150); | |
| 5732 format %{ "FLD_D ST,$mem\n\t" | |
| 5733 "FSTP $dst" %} | |
| 5734 opcode(0xDD); /* DD /0 */ | |
| 5735 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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5736 Pop_Reg_DPR(dst) ); |
| 0 | 5737 ins_pipe( fpu_reg_mem ); |
| 5738 %} | |
| 5739 | |
| 5740 // Load Double to XMM | |
|
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5741 instruct loadD(regD dst, memory mem) %{ |
| 0 | 5742 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 5743 match(Set dst (LoadD mem)); | |
| 5744 ins_cost(145); | |
| 5745 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 5746 ins_encode %{ |
| 5747 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5748 %} | |
| 0 | 5749 ins_pipe( pipe_slow ); |
| 5750 %} | |
| 5751 | |
|
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5752 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 5753 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 5754 match(Set dst (LoadD mem)); | |
| 5755 ins_cost(145); | |
| 5756 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 5757 ins_encode %{ |
| 5758 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5759 %} | |
| 0 | 5760 ins_pipe( pipe_slow ); |
| 5761 %} | |
| 5762 | |
| 5763 // Load to XMM register (single-precision floating point) | |
| 5764 // MOVSS instruction | |
|
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5765 instruct loadF(regF dst, memory mem) %{ |
| 0 | 5766 predicate(UseSSE>=1); |
| 5767 match(Set dst (LoadF mem)); | |
| 5768 ins_cost(145); | |
| 5769 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 5770 ins_encode %{ |
| 5771 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 5772 %} | |
| 0 | 5773 ins_pipe( pipe_slow ); |
| 5774 %} | |
| 5775 | |
| 5776 // Load Float | |
|
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5777 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 5778 predicate(UseSSE==0); |
| 5779 match(Set dst (LoadF mem)); | |
| 5780 | |
| 5781 ins_cost(150); | |
| 5782 format %{ "FLD_S ST,$mem\n\t" | |
| 5783 "FSTP $dst" %} | |
| 5784 opcode(0xD9); /* D9 /0 */ | |
| 5785 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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5786 Pop_Reg_FPR(dst) ); |
| 0 | 5787 ins_pipe( fpu_reg_mem ); |
| 5788 %} | |
| 5789 | |
| 5790 // Load Effective Address | |
| 5791 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 5792 match(Set dst mem); | |
| 5793 | |
| 5794 ins_cost(110); | |
| 5795 format %{ "LEA $dst,$mem" %} | |
| 5796 opcode(0x8D); | |
| 5797 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5798 ins_pipe( ialu_reg_reg_fat ); | |
| 5799 %} | |
| 5800 | |
| 5801 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 5802 match(Set dst mem); | |
| 5803 | |
| 5804 ins_cost(110); | |
| 5805 format %{ "LEA $dst,$mem" %} | |
| 5806 opcode(0x8D); | |
| 5807 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5808 ins_pipe( ialu_reg_reg_fat ); | |
| 5809 %} | |
| 5810 | |
| 5811 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 5812 match(Set dst mem); | |
| 5813 | |
| 5814 ins_cost(110); | |
| 5815 format %{ "LEA $dst,$mem" %} | |
| 5816 opcode(0x8D); | |
| 5817 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5818 ins_pipe( ialu_reg_reg_fat ); | |
| 5819 %} | |
| 5820 | |
| 5821 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 5822 match(Set dst mem); | |
| 5823 | |
| 5824 ins_cost(110); | |
| 5825 format %{ "LEA $dst,$mem" %} | |
| 5826 opcode(0x8D); | |
| 5827 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5828 ins_pipe( ialu_reg_reg_fat ); | |
| 5829 %} | |
| 5830 | |
| 5831 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 5832 match(Set dst mem); | |
| 5833 | |
| 5834 ins_cost(110); | |
| 5835 format %{ "LEA $dst,$mem" %} | |
| 5836 opcode(0x8D); | |
| 5837 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5838 ins_pipe( ialu_reg_reg_fat ); | |
| 5839 %} | |
| 5840 | |
| 5841 // Load Constant | |
|
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5842 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 5843 match(Set dst src); |
| 5844 | |
| 5845 format %{ "MOV $dst,$src" %} | |
| 5846 ins_encode( LdImmI(dst, src) ); | |
| 5847 ins_pipe( ialu_reg_fat ); | |
| 5848 %} | |
| 5849 | |
| 5850 // Load Constant zero | |
|
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5851 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 5852 match(Set dst src); |
| 5853 effect(KILL cr); | |
| 5854 | |
| 5855 ins_cost(50); | |
| 5856 format %{ "XOR $dst,$dst" %} | |
| 5857 opcode(0x33); /* + rd */ | |
| 5858 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 5859 ins_pipe( ialu_reg ); | |
| 5860 %} | |
| 5861 | |
| 5862 instruct loadConP(eRegP dst, immP src) %{ | |
| 5863 match(Set dst src); | |
| 5864 | |
| 5865 format %{ "MOV $dst,$src" %} | |
| 5866 opcode(0xB8); /* + rd */ | |
| 5867 ins_encode( LdImmP(dst, src) ); | |
| 5868 ins_pipe( ialu_reg_fat ); | |
| 5869 %} | |
| 5870 | |
| 5871 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 5872 match(Set dst src); | |
| 5873 effect(KILL cr); | |
| 5874 ins_cost(200); | |
| 5875 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 5876 "MOV $dst.hi,$src.hi" %} | |
| 5877 opcode(0xB8); | |
| 5878 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 5879 ins_pipe( ialu_reg_long_fat ); | |
| 5880 %} | |
| 5881 | |
| 5882 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 5883 match(Set dst src); | |
| 5884 effect(KILL cr); | |
| 5885 ins_cost(150); | |
| 5886 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 5887 "XOR $dst.hi,$dst.hi" %} | |
| 5888 opcode(0x33,0x33); | |
| 5889 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 5890 ins_pipe( ialu_reg_long ); | |
| 5891 %} | |
| 5892 | |
|
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5893 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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5894 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 5895 match(Set dst con); |
| 5896 ins_cost(125); | |
| 5897 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 5898 "FSTP $dst" %} | |
| 5899 ins_encode %{ | |
| 5900 __ fld_s($constantaddress($con)); | |
| 5901 __ fstp_d($dst$$reg); | |
| 5902 %} | |
| 5903 ins_pipe(fpu_reg_con); | |
| 5904 %} | |
| 5905 | |
|
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5906 // The instruction usage is guarded by predicate in operand immFPR0(). |
|
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5907 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 5908 match(Set dst con); |
| 0 | 5909 ins_cost(125); |
| 2008 | 5910 format %{ "FLDZ ST\n\t" |
| 0 | 5911 "FSTP $dst" %} |
| 2008 | 5912 ins_encode %{ |
| 5913 __ fldz(); | |
| 5914 __ fstp_d($dst$$reg); | |
| 5915 %} | |
| 5916 ins_pipe(fpu_reg_con); | |
| 5917 %} | |
| 5918 | |
|
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5919 // The instruction usage is guarded by predicate in operand immFPR1(). |
|
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5920 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 5921 match(Set dst con); |
| 5922 ins_cost(125); | |
| 5923 format %{ "FLD1 ST\n\t" | |
| 5924 "FSTP $dst" %} | |
| 5925 ins_encode %{ | |
| 5926 __ fld1(); | |
| 5927 __ fstp_d($dst$$reg); | |
| 5928 %} | |
| 5929 ins_pipe(fpu_reg_con); | |
| 0 | 5930 %} |
| 5931 | |
|
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5932 // The instruction usage is guarded by predicate in operand immF(). |
|
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|
5933 instruct loadConF(regF dst, immF con) %{ |
| 0 | 5934 match(Set dst con); |
| 5935 ins_cost(125); | |
| 2008 | 5936 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 5937 ins_encode %{ | |
| 5938 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5939 %} | |
| 5940 ins_pipe(pipe_slow); | |
| 0 | 5941 %} |
| 5942 | |
|
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5943 // The instruction usage is guarded by predicate in operand immF0(). |
|
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5944 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 5945 match(Set dst src); |
| 5946 ins_cost(100); | |
| 5947 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 5948 ins_encode %{ |
| 5949 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5950 %} | |
| 5951 ins_pipe(pipe_slow); | |
| 0 | 5952 %} |
| 5953 | |
|
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5954 // The instruction usage is guarded by predicate in operand immDPR(). |
|
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5955 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 5956 match(Set dst con); |
| 5957 ins_cost(125); | |
| 5958 | |
| 5959 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 5960 "FSTP $dst" %} | |
| 5961 ins_encode %{ | |
| 5962 __ fld_d($constantaddress($con)); | |
| 5963 __ fstp_d($dst$$reg); | |
| 5964 %} | |
| 5965 ins_pipe(fpu_reg_con); | |
| 5966 %} | |
| 5967 | |
|
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5968 // The instruction usage is guarded by predicate in operand immDPR0(). |
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|
5969 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 5970 match(Set dst con); |
| 0 | 5971 ins_cost(125); |
| 5972 | |
| 2008 | 5973 format %{ "FLDZ ST\n\t" |
| 0 | 5974 "FSTP $dst" %} |
| 2008 | 5975 ins_encode %{ |
| 5976 __ fldz(); | |
| 5977 __ fstp_d($dst$$reg); | |
| 5978 %} | |
| 5979 ins_pipe(fpu_reg_con); | |
| 5980 %} | |
| 5981 | |
|
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5982 // The instruction usage is guarded by predicate in operand immDPR1(). |
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5983 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 5984 match(Set dst con); |
| 5985 ins_cost(125); | |
| 5986 | |
| 5987 format %{ "FLD1 ST\n\t" | |
| 5988 "FSTP $dst" %} | |
| 5989 ins_encode %{ | |
| 5990 __ fld1(); | |
| 5991 __ fstp_d($dst$$reg); | |
| 5992 %} | |
| 5993 ins_pipe(fpu_reg_con); | |
| 0 | 5994 %} |
| 5995 | |
|
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5996 // The instruction usage is guarded by predicate in operand immD(). |
|
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|
5997 instruct loadConD(regD dst, immD con) %{ |
| 0 | 5998 match(Set dst con); |
| 5999 ins_cost(125); | |
| 2008 | 6000 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6001 ins_encode %{ | |
| 6002 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6003 %} | |
| 6004 ins_pipe(pipe_slow); | |
| 0 | 6005 %} |
| 6006 | |
|
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6007 // The instruction usage is guarded by predicate in operand immD0(). |
|
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6008 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6009 match(Set dst src); |
| 6010 ins_cost(100); | |
| 6011 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6012 ins_encode %{ |
| 6013 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6014 %} | |
| 0 | 6015 ins_pipe( pipe_slow ); |
| 6016 %} | |
| 6017 | |
| 6018 // Load Stack Slot | |
|
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6019 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6020 match(Set dst src); |
| 6021 ins_cost(125); | |
| 6022 | |
| 6023 format %{ "MOV $dst,$src" %} | |
| 6024 opcode(0x8B); | |
| 6025 ins_encode( OpcP, RegMem(dst,src)); | |
| 6026 ins_pipe( ialu_reg_mem ); | |
| 6027 %} | |
| 6028 | |
| 6029 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6030 match(Set dst src); | |
| 6031 | |
| 6032 ins_cost(200); | |
| 6033 format %{ "MOV $dst,$src.lo\n\t" | |
| 6034 "MOV $dst+4,$src.hi" %} | |
| 6035 opcode(0x8B, 0x8B); | |
| 6036 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6037 ins_pipe( ialu_mem_long_reg ); | |
| 6038 %} | |
| 6039 | |
| 6040 // Load Stack Slot | |
| 6041 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6042 match(Set dst src); | |
| 6043 ins_cost(125); | |
| 6044 | |
| 6045 format %{ "MOV $dst,$src" %} | |
| 6046 opcode(0x8B); | |
| 6047 ins_encode( OpcP, RegMem(dst,src)); | |
| 6048 ins_pipe( ialu_reg_mem ); | |
| 6049 %} | |
| 6050 | |
| 6051 // Load Stack Slot | |
|
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6052 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6053 match(Set dst src); |
| 6054 ins_cost(125); | |
| 6055 | |
| 6056 format %{ "FLD_S $src\n\t" | |
| 6057 "FSTP $dst" %} | |
| 6058 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6059 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6060 Pop_Reg_FPR(dst) ); |
| 0 | 6061 ins_pipe( fpu_reg_mem ); |
| 6062 %} | |
| 6063 | |
| 6064 // Load Stack Slot | |
|
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6065 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6066 match(Set dst src); |
| 6067 ins_cost(125); | |
| 6068 | |
| 6069 format %{ "FLD_D $src\n\t" | |
| 6070 "FSTP $dst" %} | |
| 6071 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6072 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6073 Pop_Reg_DPR(dst) ); |
| 0 | 6074 ins_pipe( fpu_reg_mem ); |
| 6075 %} | |
| 6076 | |
| 6077 // Prefetch instructions. | |
| 6078 // Must be safe to execute with invalid address (cannot fault). | |
| 6079 | |
| 6080 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6081 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6082 match(PrefetchRead mem); |
| 6083 ins_cost(0); | |
| 6084 size(0); | |
| 6085 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6086 ins_encode(); | |
| 6087 ins_pipe(empty); | |
| 6088 %} | |
| 6089 | |
| 6090 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6091 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6092 match(PrefetchRead mem); |
| 6093 ins_cost(100); | |
| 6094 | |
| 6095 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6096 ins_encode %{ |
| 6097 __ prefetchr($mem$$Address); | |
| 6098 %} | |
| 0 | 6099 ins_pipe(ialu_mem); |
| 6100 %} | |
| 6101 | |
| 6102 instruct prefetchrNTA( memory mem ) %{ | |
| 6103 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6104 match(PrefetchRead mem); | |
| 6105 ins_cost(100); | |
| 6106 | |
| 6107 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6108 ins_encode %{ |
| 6109 __ prefetchnta($mem$$Address); | |
| 6110 %} | |
| 0 | 6111 ins_pipe(ialu_mem); |
| 6112 %} | |
| 6113 | |
| 6114 instruct prefetchrT0( memory mem ) %{ | |
| 6115 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6116 match(PrefetchRead mem); | |
| 6117 ins_cost(100); | |
| 6118 | |
| 6119 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6120 ins_encode %{ |
| 6121 __ prefetcht0($mem$$Address); | |
| 6122 %} | |
| 0 | 6123 ins_pipe(ialu_mem); |
| 6124 %} | |
| 6125 | |
| 6126 instruct prefetchrT2( memory mem ) %{ | |
| 6127 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6128 match(PrefetchRead mem); | |
| 6129 ins_cost(100); | |
| 6130 | |
| 6131 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6132 ins_encode %{ |
| 6133 __ prefetcht2($mem$$Address); | |
| 6134 %} | |
| 0 | 6135 ins_pipe(ialu_mem); |
| 6136 %} | |
| 6137 | |
| 6138 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6139 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6140 match(PrefetchWrite mem); |
| 6141 ins_cost(0); | |
| 6142 size(0); | |
| 6143 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6144 ins_encode(); | |
| 6145 ins_pipe(empty); | |
| 6146 %} | |
| 6147 | |
| 6148 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6149 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6150 match( PrefetchWrite mem ); |
| 6151 ins_cost(100); | |
| 6152 | |
| 6153 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6154 ins_encode %{ |
| 6155 __ prefetchw($mem$$Address); | |
| 6156 %} | |
| 0 | 6157 ins_pipe(ialu_mem); |
| 6158 %} | |
| 6159 | |
| 6160 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6161 predicate(UseSSE>=1); |
| 0 | 6162 match(PrefetchWrite mem); |
| 6163 ins_cost(100); | |
| 6164 | |
| 6165 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6166 ins_encode %{ |
| 6167 __ prefetchnta($mem$$Address); | |
| 6168 %} | |
| 0 | 6169 ins_pipe(ialu_mem); |
| 6170 %} | |
| 6171 | |
| 3854 | 6172 // Prefetch instructions for allocation. |
| 6173 | |
| 6174 instruct prefetchAlloc0( memory mem ) %{ | |
| 6175 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6176 match(PrefetchAllocation mem); | |
| 6177 ins_cost(0); | |
| 6178 size(0); | |
| 6179 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6180 ins_encode(); | |
| 6181 ins_pipe(empty); | |
| 6182 %} | |
| 6183 | |
| 6184 instruct prefetchAlloc( memory mem ) %{ | |
| 6185 predicate(AllocatePrefetchInstr==3); | |
| 6186 match( PrefetchAllocation mem ); | |
| 0 | 6187 ins_cost(100); |
| 6188 | |
| 3854 | 6189 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6190 ins_encode %{ | |
| 6191 __ prefetchw($mem$$Address); | |
| 6192 %} | |
| 6193 ins_pipe(ialu_mem); | |
| 6194 %} | |
| 6195 | |
| 6196 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6197 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6198 match(PrefetchAllocation mem); | |
| 6199 ins_cost(100); | |
| 6200 | |
| 6201 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6202 ins_encode %{ | |
| 6203 __ prefetchnta($mem$$Address); | |
| 6204 %} | |
| 0 | 6205 ins_pipe(ialu_mem); |
| 6206 %} | |
| 6207 | |
| 3854 | 6208 instruct prefetchAllocT0( memory mem ) %{ |
| 6209 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6210 match(PrefetchAllocation mem); | |
| 0 | 6211 ins_cost(100); |
| 6212 | |
| 3854 | 6213 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6214 ins_encode %{ | |
| 6215 __ prefetcht0($mem$$Address); | |
| 6216 %} | |
| 6217 ins_pipe(ialu_mem); | |
| 6218 %} | |
| 6219 | |
| 6220 instruct prefetchAllocT2( memory mem ) %{ | |
| 6221 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6222 match(PrefetchAllocation mem); | |
| 6223 ins_cost(100); | |
| 6224 | |
| 6225 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6226 ins_encode %{ | |
| 6227 __ prefetcht2($mem$$Address); | |
| 6228 %} | |
| 0 | 6229 ins_pipe(ialu_mem); |
| 6230 %} | |
| 6231 | |
| 6232 //----------Store Instructions------------------------------------------------- | |
| 6233 | |
| 6234 // Store Byte | |
| 6235 instruct storeB(memory mem, xRegI src) %{ | |
| 6236 match(Set mem (StoreB mem src)); | |
| 6237 | |
| 6238 ins_cost(125); | |
| 6239 format %{ "MOV8 $mem,$src" %} | |
| 6240 opcode(0x88); | |
| 6241 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6242 ins_pipe( ialu_mem_reg ); | |
| 6243 %} | |
| 6244 | |
| 6245 // Store Char/Short | |
|
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6246 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6247 match(Set mem (StoreC mem src)); |
| 6248 | |
| 6249 ins_cost(125); | |
| 6250 format %{ "MOV16 $mem,$src" %} | |
| 6251 opcode(0x89, 0x66); | |
| 6252 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6253 ins_pipe( ialu_mem_reg ); | |
| 6254 %} | |
| 6255 | |
| 6256 // Store Integer | |
|
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6257 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6258 match(Set mem (StoreI mem src)); |
| 6259 | |
| 6260 ins_cost(125); | |
| 6261 format %{ "MOV $mem,$src" %} | |
| 6262 opcode(0x89); | |
| 6263 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6264 ins_pipe( ialu_mem_reg ); | |
| 6265 %} | |
| 6266 | |
| 6267 // Store Long | |
| 6268 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6269 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6270 match(Set mem (StoreL mem src)); | |
| 6271 | |
| 6272 ins_cost(200); | |
| 6273 format %{ "MOV $mem,$src.lo\n\t" | |
| 6274 "MOV $mem+4,$src.hi" %} | |
| 6275 opcode(0x89, 0x89); | |
| 6276 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6277 ins_pipe( ialu_mem_long_reg ); | |
| 6278 %} | |
| 6279 | |
| 824 | 6280 // Store Long to Integer |
| 6281 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6282 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6283 | |
| 6284 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6285 ins_encode %{ | |
| 6286 __ movl($mem$$Address, $src$$Register); | |
| 6287 %} | |
| 6288 ins_pipe(ialu_mem_reg); | |
| 6289 %} | |
| 6290 | |
| 0 | 6291 // Volatile Store Long. Must be atomic, so move it into |
| 6292 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6293 // target address before the store (for null-ptr checks) | |
| 6294 // so the memory operand is used twice in the encoding. | |
| 6295 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6296 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6297 match(Set mem (StoreL mem src)); | |
| 6298 effect( KILL cr ); | |
| 6299 ins_cost(400); | |
| 6300 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6301 "FILD $src\n\t" | |
| 6302 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6303 opcode(0x3B); | |
| 6304 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6305 ins_pipe( fpu_reg_mem ); | |
| 6306 %} | |
| 6307 | |
|
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6308 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6309 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6310 match(Set mem (StoreL mem src)); | |
| 6311 effect( TEMP tmp, KILL cr ); | |
| 6312 ins_cost(380); | |
| 6313 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6314 "MOVSD $tmp,$src\n\t" | |
| 6315 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6316 ins_encode %{ |
| 6317 __ cmpl(rax, $mem$$Address); | |
| 6318 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6319 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6320 %} | |
| 0 | 6321 ins_pipe( pipe_slow ); |
| 6322 %} | |
| 6323 | |
|
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6324 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6325 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6326 match(Set mem (StoreL mem src)); | |
| 6327 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6328 ins_cost(360); | |
| 6329 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6330 "MOVD $tmp,$src.lo\n\t" | |
| 6331 "MOVD $tmp2,$src.hi\n\t" | |
| 6332 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6333 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6334 ins_encode %{ |
| 6335 __ cmpl(rax, $mem$$Address); | |
| 6336 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6337 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6338 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6339 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6340 %} | |
| 0 | 6341 ins_pipe( pipe_slow ); |
| 6342 %} | |
| 6343 | |
| 6344 // Store Pointer; for storing unknown oops and raw pointers | |
| 6345 instruct storeP(memory mem, anyRegP src) %{ | |
| 6346 match(Set mem (StoreP mem src)); | |
| 6347 | |
| 6348 ins_cost(125); | |
| 6349 format %{ "MOV $mem,$src" %} | |
| 6350 opcode(0x89); | |
| 6351 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6352 ins_pipe( ialu_mem_reg ); | |
| 6353 %} | |
| 6354 | |
| 6355 // Store Integer Immediate | |
| 6356 instruct storeImmI(memory mem, immI src) %{ | |
| 6357 match(Set mem (StoreI mem src)); | |
| 6358 | |
| 6359 ins_cost(150); | |
| 6360 format %{ "MOV $mem,$src" %} | |
| 6361 opcode(0xC7); /* C7 /0 */ | |
| 6362 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6363 ins_pipe( ialu_mem_imm ); | |
| 6364 %} | |
| 6365 | |
| 6366 // Store Short/Char Immediate | |
| 6367 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6368 predicate(UseStoreImmI16); | |
| 6369 match(Set mem (StoreC mem src)); | |
| 6370 | |
| 6371 ins_cost(150); | |
| 6372 format %{ "MOV16 $mem,$src" %} | |
| 6373 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6374 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6375 ins_pipe( ialu_mem_imm ); | |
| 6376 %} | |
| 6377 | |
| 6378 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6379 // need card-mark barriers. | |
| 6380 instruct storeImmP(memory mem, immP src) %{ | |
| 6381 match(Set mem (StoreP mem src)); | |
| 6382 | |
| 6383 ins_cost(150); | |
| 6384 format %{ "MOV $mem,$src" %} | |
| 6385 opcode(0xC7); /* C7 /0 */ | |
| 6386 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6387 ins_pipe( ialu_mem_imm ); | |
| 6388 %} | |
| 6389 | |
| 6390 // Store Byte Immediate | |
| 6391 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6392 match(Set mem (StoreB mem src)); | |
| 6393 | |
| 6394 ins_cost(150); | |
| 6395 format %{ "MOV8 $mem,$src" %} | |
| 6396 opcode(0xC6); /* C6 /0 */ | |
| 6397 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6398 ins_pipe( ialu_mem_imm ); | |
| 6399 %} | |
| 6400 | |
| 6401 // Store CMS card-mark Immediate | |
| 6402 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6403 match(Set mem (StoreCM mem src)); | |
| 6404 | |
| 6405 ins_cost(150); | |
| 6406 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6407 opcode(0xC6); /* C6 /0 */ | |
| 6408 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6409 ins_pipe( ialu_mem_imm ); | |
| 6410 %} | |
| 6411 | |
| 6412 // Store Double | |
|
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6413 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6414 predicate(UseSSE<=1); |
| 6415 match(Set mem (StoreD mem src)); | |
| 6416 | |
| 6417 ins_cost(100); | |
| 6418 format %{ "FST_D $mem,$src" %} | |
| 6419 opcode(0xDD); /* DD /2 */ | |
|
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6420 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6421 ins_pipe( fpu_mem_reg ); |
| 6422 %} | |
| 6423 | |
| 6424 // Store double does rounding on x86 | |
|
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6425 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6426 predicate(UseSSE<=1); |
| 6427 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6428 | |
| 6429 ins_cost(100); | |
| 6430 format %{ "FST_D $mem,$src\t# round" %} | |
| 6431 opcode(0xDD); /* DD /2 */ | |
|
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6432 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6433 ins_pipe( fpu_mem_reg ); |
| 6434 %} | |
| 6435 | |
| 6436 // Store XMM register to memory (double-precision floating points) | |
| 6437 // MOVSD instruction | |
|
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6438 instruct storeD(memory mem, regD src) %{ |
| 0 | 6439 predicate(UseSSE>=2); |
| 6440 match(Set mem (StoreD mem src)); | |
| 6441 ins_cost(95); | |
| 6442 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6443 ins_encode %{ |
| 6444 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6445 %} | |
| 0 | 6446 ins_pipe( pipe_slow ); |
| 6447 %} | |
| 6448 | |
| 6449 // Store XMM register to memory (single-precision floating point) | |
| 6450 // MOVSS instruction | |
|
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6451 instruct storeF(memory mem, regF src) %{ |
| 0 | 6452 predicate(UseSSE>=1); |
| 6453 match(Set mem (StoreF mem src)); | |
| 6454 ins_cost(95); | |
| 6455 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6456 ins_encode %{ |
| 6457 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6458 %} | |
| 0 | 6459 ins_pipe( pipe_slow ); |
| 6460 %} | |
| 6461 | |
| 6462 // Store Float | |
|
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6463 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6464 predicate(UseSSE==0); |
| 6465 match(Set mem (StoreF mem src)); | |
| 6466 | |
| 6467 ins_cost(100); | |
| 6468 format %{ "FST_S $mem,$src" %} | |
| 6469 opcode(0xD9); /* D9 /2 */ | |
|
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6470 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6471 ins_pipe( fpu_mem_reg ); |
| 6472 %} | |
| 6473 | |
| 6474 // Store Float does rounding on x86 | |
|
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6475 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6476 predicate(UseSSE==0); |
| 6477 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6478 | |
| 6479 ins_cost(100); | |
| 6480 format %{ "FST_S $mem,$src\t# round" %} | |
| 6481 opcode(0xD9); /* D9 /2 */ | |
|
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6482 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6483 ins_pipe( fpu_mem_reg ); |
| 6484 %} | |
| 6485 | |
| 6486 // Store Float does rounding on x86 | |
|
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6487 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6488 predicate(UseSSE<=1); |
| 6489 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6490 | |
| 6491 ins_cost(100); | |
| 6492 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6493 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6494 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6495 ins_pipe( fpu_mem_reg ); |
| 6496 %} | |
| 6497 | |
| 6498 // Store immediate Float value (it is faster than store from FPU register) | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
6499 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6500 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6501 match(Set mem (StoreF mem src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6502 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6503 ins_cost(50); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6504 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6505 opcode(0xC7); /* C7 /0 */ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6506 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6507 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6508 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6509 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6510 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 6511 // The instruction usage is guarded by predicate in operand immF(). |
| 6512 instruct storeF_imm( memory mem, immF src) %{ | |
| 6513 match(Set mem (StoreF mem src)); | |
| 6514 | |
| 6515 ins_cost(50); | |
| 6516 format %{ "MOV $mem,$src\t# store float" %} | |
| 6517 opcode(0xC7); /* C7 /0 */ | |
| 6518 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 6519 ins_pipe( ialu_mem_imm ); | |
| 6520 %} | |
| 6521 | |
| 6522 // Store Integer to stack slot | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6523 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 6524 match(Set dst src); |
| 6525 | |
| 6526 ins_cost(100); | |
| 6527 format %{ "MOV $dst,$src" %} | |
| 6528 opcode(0x89); | |
| 6529 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6530 ins_pipe( ialu_mem_reg ); | |
| 6531 %} | |
| 6532 | |
| 6533 // Store Integer to stack slot | |
| 6534 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 6535 match(Set dst src); | |
| 6536 | |
| 6537 ins_cost(100); | |
| 6538 format %{ "MOV $dst,$src" %} | |
| 6539 opcode(0x89); | |
| 6540 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6541 ins_pipe( ialu_mem_reg ); | |
| 6542 %} | |
| 6543 | |
| 6544 // Store Long to stack slot | |
| 6545 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 6546 match(Set dst src); | |
| 6547 | |
| 6548 ins_cost(200); | |
| 6549 format %{ "MOV $dst,$src.lo\n\t" | |
| 6550 "MOV $dst+4,$src.hi" %} | |
| 6551 opcode(0x89, 0x89); | |
| 6552 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 6553 ins_pipe( ialu_mem_long_reg ); | |
| 6554 %} | |
| 6555 | |
| 6556 //----------MemBar Instructions----------------------------------------------- | |
| 6557 // Memory barrier flavors | |
| 6558 | |
| 6559 instruct membar_acquire() %{ | |
| 6560 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6561 match(LoadFence); |
| 0 | 6562 ins_cost(400); |
| 6563 | |
| 6564 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6565 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6566 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6567 ins_pipe(empty); |
| 0 | 6568 %} |
| 6569 | |
| 6570 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6571 match(MemBarAcquireLock); |
| 0 | 6572 ins_cost(0); |
| 6573 | |
| 6574 size(0); | |
| 6575 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6576 ins_encode( ); | |
| 6577 ins_pipe(empty); | |
| 6578 %} | |
| 6579 | |
| 6580 instruct membar_release() %{ | |
| 6581 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6582 match(StoreFence); |
| 0 | 6583 ins_cost(400); |
| 6584 | |
| 6585 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6586 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6587 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6588 ins_pipe(empty); |
| 0 | 6589 %} |
| 6590 | |
| 6591 instruct membar_release_lock() %{ | |
|
3849
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6592 match(MemBarReleaseLock); |
| 0 | 6593 ins_cost(0); |
| 6594 | |
| 6595 size(0); | |
| 6596 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6597 ins_encode( ); | |
| 6598 ins_pipe(empty); | |
| 6599 %} | |
| 6600 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6601 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 6602 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6603 effect(KILL cr); |
| 0 | 6604 ins_cost(400); |
| 6605 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6606 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6607 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6608 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6609 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6610 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6611 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6612 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6613 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6614 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6615 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6616 %} |
| 0 | 6617 ins_pipe(pipe_slow); |
| 6618 %} | |
| 6619 | |
| 6620 instruct unnecessary_membar_volatile() %{ | |
| 6621 match(MemBarVolatile); | |
| 6622 predicate(Matcher::post_store_load_barrier(n)); | |
| 6623 ins_cost(0); | |
| 6624 | |
| 6625 size(0); | |
| 6626 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6627 ins_encode( ); | |
| 6628 ins_pipe(empty); | |
| 6629 %} | |
| 6630 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6631 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6632 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6633 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6634 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6635 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6636 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6637 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6638 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6639 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6640 |
| 0 | 6641 //----------Move Instructions-------------------------------------------------- |
| 6642 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 6643 match(Set dst (CastX2P src)); | |
| 6644 format %{ "# X2P $dst, $src" %} | |
| 6645 ins_encode( /*empty encoding*/ ); | |
| 6646 ins_cost(0); | |
| 6647 ins_pipe(empty); | |
| 6648 %} | |
| 6649 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6650 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 6651 match(Set dst (CastP2X src)); |
| 6652 ins_cost(50); | |
| 6653 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 6654 ins_encode( enc_Copy( dst, src) ); | |
| 6655 ins_pipe( ialu_reg_reg ); | |
| 6656 %} | |
| 6657 | |
| 6658 //----------Conditional Move--------------------------------------------------- | |
| 6659 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6660 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 6661 predicate(!VM_Version::supports_cmov() ); |
| 6662 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6663 ins_cost(200); | |
| 6664 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 6665 "MOV $dst,$src\n" | |
| 6666 "skip:" %} | |
| 6667 ins_encode %{ | |
| 6668 Label Lskip; | |
| 6669 // Invert sense of branch from sense of CMOV | |
| 6670 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6671 __ movl($dst$$Register, $src$$Register); | |
| 6672 __ bind(Lskip); | |
| 6673 %} | |
| 6674 ins_pipe( pipe_cmov_reg ); | |
| 6675 %} | |
| 6676 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6677 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 6678 predicate(!VM_Version::supports_cmov() ); |
| 6679 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6680 ins_cost(200); | |
| 6681 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 6682 "MOV $dst,$src\n" | |
| 6683 "skip:" %} | |
| 6684 ins_encode %{ | |
| 6685 Label Lskip; | |
| 6686 // Invert sense of branch from sense of CMOV | |
| 6687 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6688 __ movl($dst$$Register, $src$$Register); | |
| 6689 __ bind(Lskip); | |
| 6690 %} | |
| 6691 ins_pipe( pipe_cmov_reg ); | |
| 6692 %} | |
| 6693 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6694 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 6695 predicate(VM_Version::supports_cmov() ); |
| 6696 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6697 ins_cost(200); | |
| 6698 format %{ "CMOV$cop $dst,$src" %} | |
| 6699 opcode(0x0F,0x40); | |
| 6700 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6701 ins_pipe( pipe_cmov_reg ); | |
| 6702 %} | |
| 6703 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6704 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 6705 predicate(VM_Version::supports_cmov() ); |
| 6706 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6707 ins_cost(200); | |
| 6708 format %{ "CMOV$cop $dst,$src" %} | |
| 6709 opcode(0x0F,0x40); | |
| 6710 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6711 ins_pipe( pipe_cmov_reg ); | |
| 6712 %} | |
| 6713 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6714 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6715 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6716 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6717 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6718 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6719 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6720 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6721 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6722 |
| 0 | 6723 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6724 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6725 predicate(VM_Version::supports_cmov() ); |
| 6726 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6727 ins_cost(250); | |
| 6728 format %{ "CMOV$cop $dst,$src" %} | |
| 6729 opcode(0x0F,0x40); | |
| 6730 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6731 ins_pipe( pipe_cmov_mem ); | |
| 6732 %} | |
| 6733 | |
| 6734 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6735 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 6736 predicate(VM_Version::supports_cmov() ); |
| 6737 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6738 ins_cost(250); | |
| 6739 format %{ "CMOV$cop $dst,$src" %} | |
| 6740 opcode(0x0F,0x40); | |
| 6741 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6742 ins_pipe( pipe_cmov_mem ); | |
| 6743 %} | |
| 6744 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6745 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6746 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6747 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6748 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6749 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6750 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6751 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6752 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6753 |
| 0 | 6754 // Conditional move |
| 6755 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6756 predicate(VM_Version::supports_cmov() ); | |
| 6757 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6758 ins_cost(200); | |
| 6759 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6760 opcode(0x0F,0x40); | |
| 6761 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6762 ins_pipe( pipe_cmov_reg ); | |
| 6763 %} | |
| 6764 | |
| 6765 // Conditional move (non-P6 version) | |
| 6766 // Note: a CMoveP is generated for stubs and native wrappers | |
| 6767 // regardless of whether we are on a P6, so we | |
| 6768 // emulate a cmov here | |
| 6769 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6770 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6771 ins_cost(300); | |
| 6772 format %{ "Jn$cop skip\n\t" | |
| 6773 "MOV $dst,$src\t# pointer\n" | |
| 6774 "skip:" %} | |
| 6775 opcode(0x8b); | |
| 6776 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 6777 ins_pipe( pipe_cmov_reg ); | |
| 6778 %} | |
| 6779 | |
| 6780 // Conditional move | |
|
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|
6781 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 6782 predicate(VM_Version::supports_cmov() ); |
| 6783 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6784 ins_cost(200); | |
| 6785 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6786 opcode(0x0F,0x40); | |
| 6787 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6788 ins_pipe( pipe_cmov_reg ); | |
| 6789 %} | |
| 6790 | |
|
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|
6791 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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|
6792 predicate(VM_Version::supports_cmov() ); |
|
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|
6793 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
6794 ins_cost(200); |
|
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diff
changeset
|
6795 expand %{ |
|
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diff
changeset
|
6796 cmovP_regU(cop, cr, dst, src); |
|
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|
6797 %} |
|
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|
6798 %} |
|
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diff
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|
6799 |
| 0 | 6800 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6801 // correctly meets the two pointer arguments; one is an incoming | |
| 6802 // register but the other is a memory operand. ALSO appears to | |
| 6803 // be buggy with implicit null checks. | |
| 6804 // | |
| 6805 //// Conditional move | |
| 6806 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 6807 // predicate(VM_Version::supports_cmov() ); | |
| 6808 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6809 // ins_cost(250); | |
| 6810 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6811 // opcode(0x0F,0x40); | |
| 6812 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6813 // ins_pipe( pipe_cmov_mem ); | |
| 6814 //%} | |
| 6815 // | |
| 6816 //// Conditional move | |
| 6817 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 6818 // predicate(VM_Version::supports_cmov() ); | |
| 6819 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6820 // ins_cost(250); | |
| 6821 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6822 // opcode(0x0F,0x40); | |
| 6823 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6824 // ins_pipe( pipe_cmov_mem ); | |
| 6825 //%} | |
| 6826 | |
| 6827 // Conditional move | |
|
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|
6828 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 6829 predicate(UseSSE<=1); |
| 6830 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6831 ins_cost(200); | |
| 6832 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 6833 opcode(0xDA); | |
|
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|
6834 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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|
6835 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6836 %} |
| 6837 | |
| 6838 // Conditional move | |
|
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|
6839 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 6840 predicate(UseSSE==0); |
| 6841 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6842 ins_cost(200); | |
| 6843 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 6844 opcode(0xDA); | |
|
4761
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|
6845 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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diff
changeset
|
6846 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6847 %} |
| 6848 | |
| 6849 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6850 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 6851 predicate(UseSSE<=1); |
| 6852 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6853 ins_cost(200); | |
| 6854 format %{ "Jn$cop skip\n\t" | |
| 6855 "MOV $dst,$src\t# double\n" | |
| 6856 "skip:" %} | |
| 6857 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
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diff
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|
6858 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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diff
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|
6859 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6860 %} |
| 6861 | |
| 6862 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6863 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 6864 predicate(UseSSE==0); |
| 6865 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6866 ins_cost(200); | |
| 6867 format %{ "Jn$cop skip\n\t" | |
| 6868 "MOV $dst,$src\t# float\n" | |
| 6869 "skip:" %} | |
| 6870 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
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diff
changeset
|
6871 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
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diff
changeset
|
6872 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6873 %} |
| 6874 | |
| 6875 // No CMOVE with SSE/SSE2 | |
|
4761
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|
6876 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 6877 predicate (UseSSE>=1); |
| 6878 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6879 ins_cost(200); | |
| 6880 format %{ "Jn$cop skip\n\t" | |
| 6881 "MOVSS $dst,$src\t# float\n" | |
| 6882 "skip:" %} | |
| 6883 ins_encode %{ | |
| 6884 Label skip; | |
| 6885 // Invert sense of branch from sense of CMOV | |
| 6886 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6887 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6888 __ bind(skip); | |
| 6889 %} | |
| 6890 ins_pipe( pipe_slow ); | |
| 6891 %} | |
| 6892 | |
| 6893 // No CMOVE with SSE/SSE2 | |
|
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changeset
|
6894 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 6895 predicate (UseSSE>=2); |
| 6896 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6897 ins_cost(200); | |
| 6898 format %{ "Jn$cop skip\n\t" | |
| 6899 "MOVSD $dst,$src\t# float\n" | |
| 6900 "skip:" %} | |
| 6901 ins_encode %{ | |
| 6902 Label skip; | |
| 6903 // Invert sense of branch from sense of CMOV | |
| 6904 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6905 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6906 __ bind(skip); | |
| 6907 %} | |
| 6908 ins_pipe( pipe_slow ); | |
| 6909 %} | |
| 6910 | |
| 6911 // unsigned version | |
|
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changeset
|
6912 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 6913 predicate (UseSSE>=1); |
| 6914 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6915 ins_cost(200); | |
| 6916 format %{ "Jn$cop skip\n\t" | |
| 6917 "MOVSS $dst,$src\t# float\n" | |
| 6918 "skip:" %} | |
| 6919 ins_encode %{ | |
| 6920 Label skip; | |
| 6921 // Invert sense of branch from sense of CMOV | |
| 6922 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6923 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6924 __ bind(skip); | |
| 6925 %} | |
| 6926 ins_pipe( pipe_slow ); | |
| 6927 %} | |
| 6928 | |
|
4761
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diff
changeset
|
6929 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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changeset
|
6930 predicate (UseSSE>=1); |
|
4d9884b01ba6
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diff
changeset
|
6931 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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403
diff
changeset
|
6932 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
6933 expand %{ |
|
4761
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diff
changeset
|
6934 fcmovF_regU(cop, cr, dst, src); |
|
415
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diff
changeset
|
6935 %} |
|
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diff
changeset
|
6936 %} |
|
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diff
changeset
|
6937 |
| 0 | 6938 // unsigned version |
|
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diff
changeset
|
6939 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 6940 predicate (UseSSE>=2); |
| 6941 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6942 ins_cost(200); | |
| 6943 format %{ "Jn$cop skip\n\t" | |
| 6944 "MOVSD $dst,$src\t# float\n" | |
| 6945 "skip:" %} | |
| 6946 ins_encode %{ | |
| 6947 Label skip; | |
| 6948 // Invert sense of branch from sense of CMOV | |
| 6949 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6950 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6951 __ bind(skip); | |
| 6952 %} | |
| 6953 ins_pipe( pipe_slow ); | |
| 6954 %} | |
| 6955 | |
|
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diff
changeset
|
6956 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
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changeset
|
6957 predicate (UseSSE>=2); |
|
4d9884b01ba6
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diff
changeset
|
6958 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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changeset
|
6959 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
6960 expand %{ |
|
4761
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diff
changeset
|
6961 fcmovD_regU(cop, cr, dst, src); |
|
415
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changeset
|
6962 %} |
|
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diff
changeset
|
6963 %} |
|
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diff
changeset
|
6964 |
| 0 | 6965 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 6966 predicate(VM_Version::supports_cmov() ); | |
| 6967 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6968 ins_cost(200); | |
| 6969 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6970 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6971 opcode(0x0F,0x40); | |
| 6972 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6973 ins_pipe( pipe_cmov_reg_long ); | |
| 6974 %} | |
| 6975 | |
| 6976 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 6977 predicate(VM_Version::supports_cmov() ); | |
| 6978 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6979 ins_cost(200); | |
| 6980 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6981 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6982 opcode(0x0F,0x40); | |
| 6983 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6984 ins_pipe( pipe_cmov_reg_long ); | |
| 6985 %} | |
| 6986 | |
|
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changeset
|
6987 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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changeset
|
6988 predicate(VM_Version::supports_cmov() ); |
|
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diff
changeset
|
6989 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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diff
changeset
|
6990 ins_cost(200); |
|
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diff
changeset
|
6991 expand %{ |
|
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changeset
|
6992 cmovL_regU(cop, cr, dst, src); |
|
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diff
changeset
|
6993 %} |
|
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changeset
|
6994 %} |
|
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diff
changeset
|
6995 |
| 0 | 6996 //----------Arithmetic Instructions-------------------------------------------- |
| 6997 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 6998 |
| 0 | 6999 // Integer Addition Instructions |
|
6179
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changeset
|
7000 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7001 match(Set dst (AddI dst src)); |
| 7002 effect(KILL cr); | |
| 7003 | |
| 7004 size(2); | |
| 7005 format %{ "ADD $dst,$src" %} | |
| 7006 opcode(0x03); | |
| 7007 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7008 ins_pipe( ialu_reg_reg ); | |
| 7009 %} | |
| 7010 | |
|
6179
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diff
changeset
|
7011 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7012 match(Set dst (AddI dst src)); |
| 7013 effect(KILL cr); | |
| 7014 | |
| 7015 format %{ "ADD $dst,$src" %} | |
| 7016 opcode(0x81, 0x00); /* /0 id */ | |
| 7017 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7018 ins_pipe( ialu_reg ); | |
| 7019 %} | |
| 7020 | |
|
6179
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changeset
|
7021 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7022 predicate(UseIncDec); |
| 7023 match(Set dst (AddI dst src)); | |
| 7024 effect(KILL cr); | |
| 7025 | |
| 7026 size(1); | |
| 7027 format %{ "INC $dst" %} | |
| 7028 opcode(0x40); /* */ | |
| 7029 ins_encode( Opc_plus( primary, dst ) ); | |
| 7030 ins_pipe( ialu_reg ); | |
| 7031 %} | |
| 7032 | |
|
6179
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|
7033 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7034 match(Set dst (AddI src0 src1)); |
| 7035 ins_cost(110); | |
| 7036 | |
| 7037 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7038 opcode(0x8D); /* 0x8D /r */ | |
| 7039 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7040 ins_pipe( ialu_reg_reg ); | |
| 7041 %} | |
| 7042 | |
| 7043 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7044 match(Set dst (AddP src0 src1)); | |
| 7045 ins_cost(110); | |
| 7046 | |
| 7047 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7048 opcode(0x8D); /* 0x8D /r */ | |
| 7049 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7050 ins_pipe( ialu_reg_reg ); | |
| 7051 %} | |
| 7052 | |
|
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|
7053 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7054 predicate(UseIncDec); |
| 7055 match(Set dst (AddI dst src)); | |
| 7056 effect(KILL cr); | |
| 7057 | |
| 7058 size(1); | |
| 7059 format %{ "DEC $dst" %} | |
| 7060 opcode(0x48); /* */ | |
| 7061 ins_encode( Opc_plus( primary, dst ) ); | |
| 7062 ins_pipe( ialu_reg ); | |
| 7063 %} | |
| 7064 | |
|
6179
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|
7065 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7066 match(Set dst (AddP dst src)); |
| 7067 effect(KILL cr); | |
| 7068 | |
| 7069 size(2); | |
| 7070 format %{ "ADD $dst,$src" %} | |
| 7071 opcode(0x03); | |
| 7072 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7073 ins_pipe( ialu_reg_reg ); | |
| 7074 %} | |
| 7075 | |
| 7076 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7077 match(Set dst (AddP dst src)); | |
| 7078 effect(KILL cr); | |
| 7079 | |
| 7080 format %{ "ADD $dst,$src" %} | |
| 7081 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7082 // ins_encode( RegImm( dst, src) ); | |
| 7083 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7084 ins_pipe( ialu_reg ); | |
| 7085 %} | |
| 7086 | |
|
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|
7087 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7088 match(Set dst (AddI dst (LoadI src))); |
| 7089 effect(KILL cr); | |
| 7090 | |
| 7091 ins_cost(125); | |
| 7092 format %{ "ADD $dst,$src" %} | |
| 7093 opcode(0x03); | |
| 7094 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7095 ins_pipe( ialu_reg_mem ); | |
| 7096 %} | |
| 7097 | |
|
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|
7098 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7099 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7100 effect(KILL cr); | |
| 7101 | |
| 7102 ins_cost(150); | |
| 7103 format %{ "ADD $dst,$src" %} | |
| 7104 opcode(0x01); /* Opcode 01 /r */ | |
| 7105 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7106 ins_pipe( ialu_mem_reg ); | |
| 7107 %} | |
| 7108 | |
| 7109 // Add Memory with Immediate | |
| 7110 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7111 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7112 effect(KILL cr); | |
| 7113 | |
| 7114 ins_cost(125); | |
| 7115 format %{ "ADD $dst,$src" %} | |
| 7116 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7117 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7118 ins_pipe( ialu_mem_imm ); | |
| 7119 %} | |
| 7120 | |
| 7121 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7122 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7123 effect(KILL cr); | |
| 7124 | |
| 7125 ins_cost(125); | |
| 7126 format %{ "INC $dst" %} | |
| 7127 opcode(0xFF); /* Opcode FF /0 */ | |
| 7128 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7129 ins_pipe( ialu_mem_imm ); | |
| 7130 %} | |
| 7131 | |
| 7132 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7133 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7134 effect(KILL cr); | |
| 7135 | |
| 7136 ins_cost(125); | |
| 7137 format %{ "DEC $dst" %} | |
| 7138 opcode(0xFF); /* Opcode FF /1 */ | |
| 7139 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7140 ins_pipe( ialu_mem_imm ); | |
| 7141 %} | |
| 7142 | |
| 7143 | |
| 7144 instruct checkCastPP( eRegP dst ) %{ | |
| 7145 match(Set dst (CheckCastPP dst)); | |
| 7146 | |
| 7147 size(0); | |
| 7148 format %{ "#checkcastPP of $dst" %} | |
| 7149 ins_encode( /*empty encoding*/ ); | |
| 7150 ins_pipe( empty ); | |
| 7151 %} | |
| 7152 | |
| 7153 instruct castPP( eRegP dst ) %{ | |
| 7154 match(Set dst (CastPP dst)); | |
| 7155 format %{ "#castPP of $dst" %} | |
| 7156 ins_encode( /*empty encoding*/ ); | |
| 7157 ins_pipe( empty ); | |
| 7158 %} | |
| 7159 | |
|
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|
7160 instruct castII( rRegI dst ) %{ |
| 0 | 7161 match(Set dst (CastII dst)); |
| 7162 format %{ "#castII of $dst" %} | |
| 7163 ins_encode( /*empty encoding*/ ); | |
| 7164 ins_cost(0); | |
| 7165 ins_pipe( empty ); | |
| 7166 %} | |
| 7167 | |
| 7168 | |
| 7169 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7170 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7171 match(Set dst (LoadPLocked mem)); | |
| 7172 | |
| 7173 ins_cost(125); | |
| 7174 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7175 opcode(0x8B); | |
| 7176 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7177 ins_pipe( ialu_reg_mem ); | |
| 7178 %} | |
| 7179 | |
| 7180 // Conditional-store of the updated heap-top. | |
| 7181 // Used during allocation of the shared heap. | |
| 7182 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7183 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7184 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7185 // EAX is killed if there is contention, but then it's also unused. | |
| 7186 // In the common case of no contention, EAX holds the new oop address. | |
| 7187 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7188 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7189 ins_pipe( pipe_cmpxchg ); | |
| 7190 %} | |
| 7191 | |
|
420
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|
7192 // Conditional-store of an int value. |
|
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|
7193 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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|
7194 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
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|
7195 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
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|
7196 effect(KILL oldval); |
|
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changeset
|
7197 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
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|
7198 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7199 ins_pipe( pipe_cmpxchg ); |
| 7200 %} | |
| 7201 | |
|
420
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changeset
|
7202 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7203 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
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|
7204 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
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|
7205 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
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changeset
|
7206 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7207 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
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|
7208 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
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changeset
|
7209 "XCHG EBX,ECX" |
|
a1980da045cc
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|
7210 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7211 ins_encode %{ |
|
a1980da045cc
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|
7212 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
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changeset
|
7213 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
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|
7214 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7215 // our register encoding uses rbx. |
|
a1980da045cc
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changeset
|
7216 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7217 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7218 __ lock(); |
| 624 | 7219 __ cmpxchg8($mem$$Address); |
|
420
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changeset
|
7220 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
7221 %} |
| 0 | 7222 ins_pipe( pipe_cmpxchg ); |
| 7223 %} | |
| 7224 | |
| 7225 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7226 | |
|
6179
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|
7227 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
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|
7228 predicate(VM_Version::supports_cx8()); |
| 0 | 7229 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7230 effect(KILL cr, KILL oldval); | |
| 7231 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7232 "MOV $res,0\n\t" | |
| 7233 "JNE,s fail\n\t" | |
| 7234 "MOV $res,1\n" | |
| 7235 "fail:" %} | |
| 7236 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7237 enc_flags_ne_to_boolean(res) ); | |
| 7238 ins_pipe( pipe_cmpxchg ); | |
| 7239 %} | |
| 7240 | |
|
6179
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|
7241 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7242 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7243 effect(KILL cr, KILL oldval); | |
| 7244 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7245 "MOV $res,0\n\t" | |
| 7246 "JNE,s fail\n\t" | |
| 7247 "MOV $res,1\n" | |
| 7248 "fail:" %} | |
| 7249 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7250 ins_pipe( pipe_cmpxchg ); | |
| 7251 %} | |
| 7252 | |
|
6179
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|
7253 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7254 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7255 effect(KILL cr, KILL oldval); | |
| 7256 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7257 "MOV $res,0\n\t" | |
| 7258 "JNE,s fail\n\t" | |
| 7259 "MOV $res,1\n" | |
| 7260 "fail:" %} | |
| 7261 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7262 ins_pipe( pipe_cmpxchg ); | |
| 7263 %} | |
| 7264 | |
|
6795
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changeset
|
7265 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
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changeset
|
7266 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
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|
7267 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7268 effect(KILL cr); |
|
7eca5de9e0b6
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changeset
|
7269 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
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|
7270 ins_encode %{ |
|
7eca5de9e0b6
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|
7271 if (os::is_MP()) { __ lock(); } |
|
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|
7272 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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|
7273 %} |
|
7eca5de9e0b6
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changeset
|
7274 ins_pipe( pipe_cmpxchg ); |
|
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|
7275 %} |
|
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changeset
|
7276 |
|
7eca5de9e0b6
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changeset
|
7277 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
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|
7278 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
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|
7279 effect(KILL cr); |
|
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changeset
|
7280 format %{ "XADDL [$mem],$newval" %} |
|
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|
7281 ins_encode %{ |
|
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|
7282 if (os::is_MP()) { __ lock(); } |
|
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|
7283 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7284 %} |
|
7eca5de9e0b6
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changeset
|
7285 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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changeset
|
7286 %} |
|
7eca5de9e0b6
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changeset
|
7287 |
|
7eca5de9e0b6
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changeset
|
7288 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
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changeset
|
7289 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
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|
7290 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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changeset
|
7291 ins_encode %{ |
|
7eca5de9e0b6
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changeset
|
7292 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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changeset
|
7293 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7294 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7295 %} |
|
7eca5de9e0b6
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changeset
|
7296 |
|
7eca5de9e0b6
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changeset
|
7297 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
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changeset
|
7298 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
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changeset
|
7299 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7300 ins_encode %{ |
|
7eca5de9e0b6
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6725
diff
changeset
|
7301 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7302 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7303 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7304 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7305 |
| 0 | 7306 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
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parents:
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diff
changeset
|
7307 |
| 0 | 7308 // Integer Subtraction Instructions |
|
6179
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diff
changeset
|
7309 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7310 match(Set dst (SubI dst src)); |
| 7311 effect(KILL cr); | |
| 7312 | |
| 7313 size(2); | |
| 7314 format %{ "SUB $dst,$src" %} | |
| 7315 opcode(0x2B); | |
| 7316 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7317 ins_pipe( ialu_reg_reg ); | |
| 7318 %} | |
| 7319 | |
|
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changeset
|
7320 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7321 match(Set dst (SubI dst src)); |
| 7322 effect(KILL cr); | |
| 7323 | |
| 7324 format %{ "SUB $dst,$src" %} | |
| 7325 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7326 // ins_encode( RegImm( dst, src) ); | |
| 7327 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7328 ins_pipe( ialu_reg ); | |
| 7329 %} | |
| 7330 | |
|
6179
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diff
changeset
|
7331 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7332 match(Set dst (SubI dst (LoadI src))); |
| 7333 effect(KILL cr); | |
| 7334 | |
| 7335 ins_cost(125); | |
| 7336 format %{ "SUB $dst,$src" %} | |
| 7337 opcode(0x2B); | |
| 7338 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7339 ins_pipe( ialu_reg_mem ); | |
| 7340 %} | |
| 7341 | |
|
6179
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diff
changeset
|
7342 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7343 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7344 effect(KILL cr); | |
| 7345 | |
| 7346 ins_cost(150); | |
| 7347 format %{ "SUB $dst,$src" %} | |
| 7348 opcode(0x29); /* Opcode 29 /r */ | |
| 7349 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7350 ins_pipe( ialu_mem_reg ); | |
| 7351 %} | |
| 7352 | |
| 7353 // Subtract from a pointer | |
|
6179
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diff
changeset
|
7354 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7355 match(Set dst (AddP dst (SubI zero src))); |
| 7356 effect(KILL cr); | |
| 7357 | |
| 7358 size(2); | |
| 7359 format %{ "SUB $dst,$src" %} | |
| 7360 opcode(0x2B); | |
| 7361 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7362 ins_pipe( ialu_reg_reg ); | |
| 7363 %} | |
| 7364 | |
|
6179
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diff
changeset
|
7365 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7366 match(Set dst (SubI zero dst)); |
| 7367 effect(KILL cr); | |
| 7368 | |
| 7369 size(2); | |
| 7370 format %{ "NEG $dst" %} | |
| 7371 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7372 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7373 ins_pipe( ialu_reg ); | |
| 7374 %} | |
| 7375 | |
| 7376 //----------Multiplication/Division Instructions------------------------------- | |
| 7377 // Integer Multiplication Instructions | |
| 7378 // Multiply Register | |
|
6179
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diff
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|
7379 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7380 match(Set dst (MulI dst src)); |
| 7381 effect(KILL cr); | |
| 7382 | |
| 7383 size(3); | |
| 7384 ins_cost(300); | |
| 7385 format %{ "IMUL $dst,$src" %} | |
| 7386 opcode(0xAF, 0x0F); | |
| 7387 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7388 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7389 %} | |
| 7390 | |
| 7391 // Multiply 32-bit Immediate | |
|
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|
7392 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7393 match(Set dst (MulI src imm)); |
| 7394 effect(KILL cr); | |
| 7395 | |
| 7396 ins_cost(300); | |
| 7397 format %{ "IMUL $dst,$src,$imm" %} | |
| 7398 opcode(0x69); /* 69 /r id */ | |
| 7399 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7400 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7401 %} | |
| 7402 | |
| 7403 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7404 match(Set dst src); | |
| 7405 effect(KILL cr); | |
| 7406 | |
| 7407 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7408 ins_cost(250); | |
| 7409 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7410 opcode(0xB8); | |
| 7411 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7412 ins_pipe( ialu_reg_fat ); | |
| 7413 %} | |
| 7414 | |
| 7415 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7416 // (special case for shift by 32) | |
| 7417 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7418 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7419 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7420 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7421 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7422 effect(USE src1, KILL cr); | |
| 7423 | |
| 7424 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7425 ins_cost(0*100 + 1*400 - 150); | |
| 7426 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7427 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7428 ins_pipe( pipe_slow ); | |
| 7429 %} | |
| 7430 | |
| 7431 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7432 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7433 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7434 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7435 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7436 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7437 effect(USE src1, KILL cr); | |
| 7438 | |
| 7439 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7440 ins_cost(1*100 + 1*400 - 150); | |
| 7441 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7442 "SAR EDX,$cnt-32" %} | |
| 7443 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7444 ins_pipe( pipe_slow ); | |
| 7445 %} | |
| 7446 | |
| 7447 // Multiply Memory 32-bit Immediate | |
|
6179
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changeset
|
7448 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7449 match(Set dst (MulI (LoadI src) imm)); |
| 7450 effect(KILL cr); | |
| 7451 | |
| 7452 ins_cost(300); | |
| 7453 format %{ "IMUL $dst,$src,$imm" %} | |
| 7454 opcode(0x69); /* 69 /r id */ | |
| 7455 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7456 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7457 %} | |
| 7458 | |
| 7459 // Multiply Memory | |
|
6179
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kvn
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6143
diff
changeset
|
7460 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7461 match(Set dst (MulI dst (LoadI src))); |
| 7462 effect(KILL cr); | |
| 7463 | |
| 7464 ins_cost(350); | |
| 7465 format %{ "IMUL $dst,$src" %} | |
| 7466 opcode(0xAF, 0x0F); | |
| 7467 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7468 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7469 %} | |
| 7470 | |
| 7471 // Multiply Register Int to Long | |
| 7472 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7473 // Basic Idea: long = (long)int * (long)int | |
| 7474 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7475 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7476 | |
| 7477 ins_cost(300); | |
| 7478 format %{ "IMUL $dst,$src1" %} | |
| 7479 | |
| 7480 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7481 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7482 %} | |
| 7483 | |
| 7484 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7485 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7486 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7487 effect(KILL flags); | |
| 7488 | |
| 7489 ins_cost(300); | |
| 7490 format %{ "MUL $dst,$src1" %} | |
| 7491 | |
| 7492 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7493 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7494 %} | |
| 7495 | |
| 7496 // Multiply Register Long | |
|
6179
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diff
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|
7497 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7498 match(Set dst (MulL dst src)); |
| 7499 effect(KILL cr, TEMP tmp); | |
| 7500 ins_cost(4*100+3*400); | |
| 7501 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7502 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7503 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7504 "IMUL $tmp,EDX\n\t" | |
| 7505 "MOV EDX,$src.hi\n\t" | |
| 7506 "IMUL EDX,EAX\n\t" | |
| 7507 "ADD $tmp,EDX\n\t" | |
| 7508 "MUL EDX:EAX,$src.lo\n\t" | |
| 7509 "ADD EDX,$tmp" %} | |
| 7510 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 7511 ins_pipe( pipe_slow ); | |
| 7512 %} | |
| 7513 | |
|
1209
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1137
diff
changeset
|
7514 // Multiply Register Long where the left operand's high 32 bits are zero |
|
6179
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|
7515 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
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diff
changeset
|
7516 predicate(is_operand_hi32_zero(n->in(1))); |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7517 match(Set dst (MulL dst src)); |
|
e8443c7be117
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never
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1137
diff
changeset
|
7518 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7519 ins_cost(2*100+2*400); |
|
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parents:
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diff
changeset
|
7520 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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parents:
1137
diff
changeset
|
7521 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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diff
changeset
|
7522 format %{ "MOV $tmp,$src.hi\n\t" |
|
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diff
changeset
|
7523 "IMUL $tmp,EAX\n\t" |
|
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diff
changeset
|
7524 "MUL EDX:EAX,$src.lo\n\t" |
|
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1137
diff
changeset
|
7525 "ADD EDX,$tmp" %} |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
7526 ins_encode %{ |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
7527 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7528 __ imull($tmp$$Register, rax); |
|
e8443c7be117
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never
parents:
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diff
changeset
|
7529 __ mull($src$$Register); |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7530 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
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never
parents:
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diff
changeset
|
7531 %} |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
7532 ins_pipe( pipe_slow ); |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
7533 %} |
|
e8443c7be117
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parents:
1137
diff
changeset
|
7534 |
|
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diff
changeset
|
7535 // Multiply Register Long where the right operand's high 32 bits are zero |
|
6179
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|
7536 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
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diff
changeset
|
7537 predicate(is_operand_hi32_zero(n->in(2))); |
|
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1137
diff
changeset
|
7538 match(Set dst (MulL dst src)); |
|
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never
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diff
changeset
|
7539 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
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diff
changeset
|
7540 ins_cost(2*100+2*400); |
|
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diff
changeset
|
7541 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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diff
changeset
|
7542 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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diff
changeset
|
7543 format %{ "MOV $tmp,$src.lo\n\t" |
|
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diff
changeset
|
7544 "IMUL $tmp,EDX\n\t" |
|
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diff
changeset
|
7545 "MUL EDX:EAX,$src.lo\n\t" |
|
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diff
changeset
|
7546 "ADD EDX,$tmp" %} |
|
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diff
changeset
|
7547 ins_encode %{ |
|
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changeset
|
7548 __ movl($tmp$$Register, $src$$Register); |
|
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diff
changeset
|
7549 __ imull($tmp$$Register, rdx); |
|
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diff
changeset
|
7550 __ mull($src$$Register); |
|
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|
7551 __ addl(rdx, $tmp$$Register); |
|
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changeset
|
7552 %} |
|
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diff
changeset
|
7553 ins_pipe( pipe_slow ); |
|
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changeset
|
7554 %} |
|
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diff
changeset
|
7555 |
|
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diff
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|
7556 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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|
7557 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
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|
7558 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
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changeset
|
7559 match(Set dst (MulL dst src)); |
|
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changeset
|
7560 effect(KILL cr); |
|
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changeset
|
7561 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7562 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7563 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7564 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7565 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7566 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7567 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7568 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7569 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7570 |
| 0 | 7571 // Multiply Register Long by small constant |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7572 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7573 match(Set dst (MulL dst src)); |
| 7574 effect(KILL cr, TEMP tmp); | |
| 7575 ins_cost(2*100+2*400); | |
| 7576 size(12); | |
| 7577 // Basic idea: lo(result) = lo(src * EAX) | |
| 7578 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 7579 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 7580 "MOV EDX,$src\n\t" | |
| 7581 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 7582 "ADD EDX,$tmp" %} | |
| 7583 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 7584 ins_pipe( pipe_slow ); | |
| 7585 %} | |
| 7586 | |
| 7587 // Integer DIV with Register | |
| 7588 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7589 match(Set rax (DivI rax div)); | |
| 7590 effect(KILL rdx, KILL cr); | |
| 7591 size(26); | |
| 7592 ins_cost(30*100+10*100); | |
| 7593 format %{ "CMP EAX,0x80000000\n\t" | |
| 7594 "JNE,s normal\n\t" | |
| 7595 "XOR EDX,EDX\n\t" | |
| 7596 "CMP ECX,-1\n\t" | |
| 7597 "JE,s done\n" | |
| 7598 "normal: CDQ\n\t" | |
| 7599 "IDIV $div\n\t" | |
| 7600 "done:" %} | |
| 7601 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7602 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7603 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7604 %} | |
| 7605 | |
| 7606 // Divide Register Long | |
| 7607 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7608 match(Set dst (DivL src1 src2)); | |
| 7609 effect( KILL cr, KILL cx, KILL bx ); | |
| 7610 ins_cost(10000); | |
| 7611 format %{ "PUSH $src1.hi\n\t" | |
| 7612 "PUSH $src1.lo\n\t" | |
| 7613 "PUSH $src2.hi\n\t" | |
| 7614 "PUSH $src2.lo\n\t" | |
| 7615 "CALL SharedRuntime::ldiv\n\t" | |
| 7616 "ADD ESP,16" %} | |
| 7617 ins_encode( long_div(src1,src2) ); | |
| 7618 ins_pipe( pipe_slow ); | |
| 7619 %} | |
| 7620 | |
| 7621 // Integer DIVMOD with Register, both quotient and mod results | |
| 7622 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7623 match(DivModI rax div); | |
| 7624 effect(KILL cr); | |
| 7625 size(26); | |
| 7626 ins_cost(30*100+10*100); | |
| 7627 format %{ "CMP EAX,0x80000000\n\t" | |
| 7628 "JNE,s normal\n\t" | |
| 7629 "XOR EDX,EDX\n\t" | |
| 7630 "CMP ECX,-1\n\t" | |
| 7631 "JE,s done\n" | |
| 7632 "normal: CDQ\n\t" | |
| 7633 "IDIV $div\n\t" | |
| 7634 "done:" %} | |
| 7635 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7636 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7637 ins_pipe( pipe_slow ); | |
| 7638 %} | |
| 7639 | |
| 7640 // Integer MOD with Register | |
| 7641 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 7642 match(Set rdx (ModI rax div)); | |
| 7643 effect(KILL rax, KILL cr); | |
| 7644 | |
| 7645 size(26); | |
| 7646 ins_cost(300); | |
| 7647 format %{ "CDQ\n\t" | |
| 7648 "IDIV $div" %} | |
| 7649 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7650 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7651 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7652 %} | |
| 7653 | |
| 7654 // Remainder Register Long | |
| 7655 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7656 match(Set dst (ModL src1 src2)); | |
| 7657 effect( KILL cr, KILL cx, KILL bx ); | |
| 7658 ins_cost(10000); | |
| 7659 format %{ "PUSH $src1.hi\n\t" | |
| 7660 "PUSH $src1.lo\n\t" | |
| 7661 "PUSH $src2.hi\n\t" | |
| 7662 "PUSH $src2.lo\n\t" | |
| 7663 "CALL SharedRuntime::lrem\n\t" | |
| 7664 "ADD ESP,16" %} | |
| 7665 ins_encode( long_mod(src1,src2) ); | |
| 7666 ins_pipe( pipe_slow ); | |
| 7667 %} | |
| 7668 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7669 // Divide Register Long (no special case since divisor != -1) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7670 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7671 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7672 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7673 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7674 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 7675 "XOR $tmp2,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7676 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7677 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7678 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7679 "MOV EAX,EDX\n\t" |
| 1920 | 7680 "MOV EDX,0\n\t" |
| 7681 "JLE,s pos\n\t" | |
| 7682 "LNEG EAX : $tmp2\n\t" | |
| 7683 "DIV $tmp # unsigned division\n\t" | |
| 7684 "XCHG EAX,$tmp2\n\t" | |
| 7685 "DIV $tmp\n\t" | |
| 7686 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7687 "JMP,s done\n" |
| 1920 | 7688 "pos:\n\t" |
| 7689 "DIV $tmp\n\t" | |
| 7690 "XCHG EAX,$tmp2\n" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7691 "fast:\n\t" |
| 1920 | 7692 "DIV $tmp\n" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7693 "done:\n\t" |
| 1920 | 7694 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7695 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7696 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7697 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7698 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7699 int pcon = (con > 0) ? con : -con; |
| 1920 | 7700 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7701 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7702 __ movl($tmp$$Register, pcon); |
| 1920 | 7703 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7704 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7705 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7706 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7707 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7708 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7709 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7710 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7711 | |
| 7712 // Negative dividend. | |
| 7713 // convert value to positive to use unsigned division | |
| 7714 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7715 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7716 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 7717 __ divl($tmp$$Register); |
| 7718 // revert result back to negative | |
| 7719 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7720 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7721 |
| 1920 | 7722 __ bind(Lpos); |
| 7723 __ divl($tmp$$Register); // Use unsigned division | |
| 7724 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 7725 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 7726 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7727 __ bind(Lfast); |
| 1920 | 7728 // fast path: src is positive |
| 7729 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7730 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7731 __ bind(Ldone); |
| 1920 | 7732 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7733 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7734 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7735 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7736 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7737 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7738 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7739 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7740 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7741 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7742 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7743 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7744 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7745 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7746 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7747 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7748 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7749 "MOV EAX,EDX\n\t" |
| 1920 | 7750 "MOV EDX,0\n\t" |
| 7751 "JLE,s pos\n\t" | |
| 7752 "LNEG EAX : $tmp2\n\t" | |
| 7753 "DIV $tmp # unsigned division\n\t" | |
| 7754 "MOV EAX,$tmp2\n\t" | |
| 7755 "DIV $tmp\n\t" | |
| 7756 "NEG EDX\n\t" | |
| 7757 "JMP,s done\n" | |
| 7758 "pos:\n\t" | |
| 7759 "DIV $tmp\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7760 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7761 "fast:\n\t" |
| 1920 | 7762 "DIV $tmp\n" |
| 7763 "done:\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7764 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7765 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7766 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7767 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7768 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7769 int pcon = (con > 0) ? con : -con; |
| 1920 | 7770 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7771 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7772 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7773 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7774 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7775 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7776 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7777 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7778 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7779 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7780 | |
| 7781 // Negative dividend. | |
| 7782 // convert value to positive to use unsigned division | |
| 7783 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7784 __ divl($tmp$$Register); | |
| 7785 __ movl($dst$$Register, $tmp2$$Register); | |
| 7786 __ divl($tmp$$Register); | |
| 7787 // revert remainder back to negative | |
| 7788 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 7789 __ jmpb(Ldone); | |
| 7790 | |
| 7791 __ bind(Lpos); | |
| 7792 __ divl($tmp$$Register); | |
|
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|
7793 __ movl($dst$$Register, $tmp2$$Register); |
|
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|
7794 |
|
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|
7795 __ bind(Lfast); |
| 1920 | 7796 // fast path: src is positive |
| 7797 __ divl($tmp$$Register); | |
| 7798 | |
| 7799 __ bind(Ldone); | |
|
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|
7800 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
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|
7801 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
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|
7802 |
|
ae065c367d93
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|
7803 %} |
|
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|
7804 ins_pipe( pipe_slow ); |
|
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|
7805 %} |
|
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|
7806 |
| 0 | 7807 // Integer Shift Instructions |
| 7808 // Shift Left by one | |
|
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|
7809 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7810 match(Set dst (LShiftI dst shift)); |
| 7811 effect(KILL cr); | |
| 7812 | |
| 7813 size(2); | |
| 7814 format %{ "SHL $dst,$shift" %} | |
| 7815 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7816 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7817 ins_pipe( ialu_reg ); | |
| 7818 %} | |
| 7819 | |
| 7820 // Shift Left by 8-bit immediate | |
|
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|
7821 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7822 match(Set dst (LShiftI dst shift)); |
| 7823 effect(KILL cr); | |
| 7824 | |
| 7825 size(3); | |
| 7826 format %{ "SHL $dst,$shift" %} | |
| 7827 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7828 ins_encode( RegOpcImm( dst, shift) ); | |
| 7829 ins_pipe( ialu_reg ); | |
| 7830 %} | |
| 7831 | |
| 7832 // Shift Left by variable | |
|
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7833 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7834 match(Set dst (LShiftI dst shift)); |
| 7835 effect(KILL cr); | |
| 7836 | |
| 7837 size(2); | |
| 7838 format %{ "SHL $dst,$shift" %} | |
| 7839 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7840 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7841 ins_pipe( ialu_reg_reg ); | |
| 7842 %} | |
| 7843 | |
| 7844 // Arithmetic shift right by one | |
|
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|
7845 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7846 match(Set dst (RShiftI dst shift)); |
| 7847 effect(KILL cr); | |
| 7848 | |
| 7849 size(2); | |
| 7850 format %{ "SAR $dst,$shift" %} | |
| 7851 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7852 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7853 ins_pipe( ialu_reg ); | |
| 7854 %} | |
| 7855 | |
| 7856 // Arithmetic shift right by one | |
| 7857 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 7858 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7859 effect(KILL cr); | |
| 7860 format %{ "SAR $dst,$shift" %} | |
| 7861 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7862 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 7863 ins_pipe( ialu_mem_imm ); | |
| 7864 %} | |
| 7865 | |
| 7866 // Arithmetic Shift Right by 8-bit immediate | |
|
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7867 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7868 match(Set dst (RShiftI dst shift)); |
| 7869 effect(KILL cr); | |
| 7870 | |
| 7871 size(3); | |
| 7872 format %{ "SAR $dst,$shift" %} | |
| 7873 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7874 ins_encode( RegOpcImm( dst, shift ) ); | |
| 7875 ins_pipe( ialu_mem_imm ); | |
| 7876 %} | |
| 7877 | |
| 7878 // Arithmetic Shift Right by 8-bit immediate | |
| 7879 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 7880 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7881 effect(KILL cr); | |
| 7882 | |
| 7883 format %{ "SAR $dst,$shift" %} | |
| 7884 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7885 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 7886 ins_pipe( ialu_mem_imm ); | |
| 7887 %} | |
| 7888 | |
| 7889 // Arithmetic Shift Right by variable | |
|
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|
7890 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7891 match(Set dst (RShiftI dst shift)); |
| 7892 effect(KILL cr); | |
| 7893 | |
| 7894 size(2); | |
| 7895 format %{ "SAR $dst,$shift" %} | |
| 7896 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7897 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7898 ins_pipe( ialu_reg_reg ); | |
| 7899 %} | |
| 7900 | |
| 7901 // Logical shift right by one | |
|
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|
7902 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7903 match(Set dst (URShiftI dst shift)); |
| 7904 effect(KILL cr); | |
| 7905 | |
| 7906 size(2); | |
| 7907 format %{ "SHR $dst,$shift" %} | |
| 7908 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7909 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7910 ins_pipe( ialu_reg ); | |
| 7911 %} | |
| 7912 | |
| 7913 // Logical Shift Right by 8-bit immediate | |
|
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|
7914 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7915 match(Set dst (URShiftI dst shift)); |
| 7916 effect(KILL cr); | |
| 7917 | |
| 7918 size(3); | |
| 7919 format %{ "SHR $dst,$shift" %} | |
| 7920 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7921 ins_encode( RegOpcImm( dst, shift) ); | |
| 7922 ins_pipe( ialu_reg ); | |
| 7923 %} | |
| 7924 | |
|
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|
7925 |
| 0 | 7926 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 7927 // This idiom is used by the compiler for the i2b bytecode. | |
|
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7928 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 7929 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 7930 | |
| 7931 size(3); | |
| 7932 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 7933 ins_encode %{ |
| 7934 __ movsbl($dst$$Register, $src$$Register); | |
| 7935 %} | |
| 7936 ins_pipe(ialu_reg_reg); | |
| 0 | 7937 %} |
| 7938 | |
| 7939 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 7940 // This idiom is used by the compiler the i2s bytecode. | |
|
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|
7941 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 7942 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 7943 | |
| 7944 size(3); | |
| 7945 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 7946 ins_encode %{ |
| 7947 __ movswl($dst$$Register, $src$$Register); | |
| 7948 %} | |
| 7949 ins_pipe(ialu_reg_reg); | |
| 0 | 7950 %} |
| 7951 | |
| 7952 | |
| 7953 // Logical Shift Right by variable | |
|
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|
7954 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7955 match(Set dst (URShiftI dst shift)); |
| 7956 effect(KILL cr); | |
| 7957 | |
| 7958 size(2); | |
| 7959 format %{ "SHR $dst,$shift" %} | |
| 7960 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7961 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7962 ins_pipe( ialu_reg_reg ); | |
| 7963 %} | |
| 7964 | |
| 7965 | |
| 7966 //----------Logical Instructions----------------------------------------------- | |
| 7967 //----------Integer Logical Instructions--------------------------------------- | |
| 7968 // And Instructions | |
| 7969 // And Register with Register | |
|
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|
7970 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7971 match(Set dst (AndI dst src)); |
| 7972 effect(KILL cr); | |
| 7973 | |
| 7974 size(2); | |
| 7975 format %{ "AND $dst,$src" %} | |
| 7976 opcode(0x23); | |
| 7977 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7978 ins_pipe( ialu_reg_reg ); | |
| 7979 %} | |
| 7980 | |
| 7981 // And Register with Immediate | |
|
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|
7982 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7983 match(Set dst (AndI dst src)); |
| 7984 effect(KILL cr); | |
| 7985 | |
| 7986 format %{ "AND $dst,$src" %} | |
| 7987 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 7988 // ins_encode( RegImm( dst, src) ); | |
| 7989 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7990 ins_pipe( ialu_reg ); | |
| 7991 %} | |
| 7992 | |
| 7993 // And Register with Memory | |
|
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|
7994 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7995 match(Set dst (AndI dst (LoadI src))); |
| 7996 effect(KILL cr); | |
| 7997 | |
| 7998 ins_cost(125); | |
| 7999 format %{ "AND $dst,$src" %} | |
| 8000 opcode(0x23); | |
| 8001 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8002 ins_pipe( ialu_reg_mem ); | |
| 8003 %} | |
| 8004 | |
| 8005 // And Memory with Register | |
|
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|
8006 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8007 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8008 effect(KILL cr); | |
| 8009 | |
| 8010 ins_cost(150); | |
| 8011 format %{ "AND $dst,$src" %} | |
| 8012 opcode(0x21); /* Opcode 21 /r */ | |
| 8013 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8014 ins_pipe( ialu_mem_reg ); | |
| 8015 %} | |
| 8016 | |
| 8017 // And Memory with Immediate | |
| 8018 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8019 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8020 effect(KILL cr); | |
| 8021 | |
| 8022 ins_cost(125); | |
| 8023 format %{ "AND $dst,$src" %} | |
| 8024 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8025 // ins_encode( MemImm( dst, src) ); | |
| 8026 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8027 ins_pipe( ialu_mem_imm ); | |
| 8028 %} | |
| 8029 | |
| 8030 // Or Instructions | |
| 8031 // Or Register with Register | |
|
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|
8032 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8033 match(Set dst (OrI dst src)); |
| 8034 effect(KILL cr); | |
| 8035 | |
| 8036 size(2); | |
| 8037 format %{ "OR $dst,$src" %} | |
| 8038 opcode(0x0B); | |
| 8039 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8040 ins_pipe( ialu_reg_reg ); | |
| 8041 %} | |
| 8042 | |
|
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|
8043 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
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|
8044 match(Set dst (OrI dst (CastP2X src))); |
|
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|
8045 effect(KILL cr); |
|
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|
8046 |
|
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|
8047 size(2); |
|
a1980da045cc
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|
8048 format %{ "OR $dst,$src" %} |
|
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|
8049 opcode(0x0B); |
|
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|
8050 ins_encode( OpcP, RegReg( dst, src) ); |
|
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|
8051 ins_pipe( ialu_reg_reg ); |
|
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|
8052 %} |
|
a1980da045cc
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|
8053 |
|
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|
8054 |
| 0 | 8055 // Or Register with Immediate |
|
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|
8056 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8057 match(Set dst (OrI dst src)); |
| 8058 effect(KILL cr); | |
| 8059 | |
| 8060 format %{ "OR $dst,$src" %} | |
| 8061 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8062 // ins_encode( RegImm( dst, src) ); | |
| 8063 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8064 ins_pipe( ialu_reg ); | |
| 8065 %} | |
| 8066 | |
| 8067 // Or Register with Memory | |
|
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8068 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8069 match(Set dst (OrI dst (LoadI src))); |
| 8070 effect(KILL cr); | |
| 8071 | |
| 8072 ins_cost(125); | |
| 8073 format %{ "OR $dst,$src" %} | |
| 8074 opcode(0x0B); | |
| 8075 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8076 ins_pipe( ialu_reg_mem ); | |
| 8077 %} | |
| 8078 | |
| 8079 // Or Memory with Register | |
|
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8080 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8081 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8082 effect(KILL cr); | |
| 8083 | |
| 8084 ins_cost(150); | |
| 8085 format %{ "OR $dst,$src" %} | |
| 8086 opcode(0x09); /* Opcode 09 /r */ | |
| 8087 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8088 ins_pipe( ialu_mem_reg ); | |
| 8089 %} | |
| 8090 | |
| 8091 // Or Memory with Immediate | |
| 8092 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8093 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8094 effect(KILL cr); | |
| 8095 | |
| 8096 ins_cost(125); | |
| 8097 format %{ "OR $dst,$src" %} | |
| 8098 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8099 // ins_encode( MemImm( dst, src) ); | |
| 8100 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8101 ins_pipe( ialu_mem_imm ); | |
| 8102 %} | |
| 8103 | |
| 8104 // ROL/ROR | |
| 8105 // ROL expand | |
|
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8106 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8107 effect(USE_DEF dst, USE shift, KILL cr); |
| 8108 | |
| 8109 format %{ "ROL $dst, $shift" %} | |
| 8110 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8111 ins_encode( OpcP, RegOpc( dst )); | |
| 8112 ins_pipe( ialu_reg ); | |
| 8113 %} | |
| 8114 | |
|
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8115 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8116 effect(USE_DEF dst, USE shift, KILL cr); |
| 8117 | |
| 8118 format %{ "ROL $dst, $shift" %} | |
| 8119 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8120 ins_encode( RegOpcImm(dst, shift) ); | |
| 8121 ins_pipe(ialu_reg); | |
| 8122 %} | |
| 8123 | |
| 8124 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8125 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8126 | |
| 8127 format %{ "ROL $dst, $shift" %} | |
| 8128 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8129 ins_encode(OpcP, RegOpc(dst)); | |
| 8130 ins_pipe( ialu_reg_reg ); | |
| 8131 %} | |
| 8132 // end of ROL expand | |
| 8133 | |
| 8134 // ROL 32bit by one once | |
|
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8135 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8136 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8137 | |
| 8138 expand %{ | |
| 8139 rolI_eReg_imm1(dst, lshift, cr); | |
| 8140 %} | |
| 8141 %} | |
| 8142 | |
| 8143 // ROL 32bit var by imm8 once | |
|
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8144 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8145 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8146 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8147 | |
| 8148 expand %{ | |
| 8149 rolI_eReg_imm8(dst, lshift, cr); | |
| 8150 %} | |
| 8151 %} | |
| 8152 | |
| 8153 // ROL 32bit var by var once | |
| 8154 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8155 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8156 | |
| 8157 expand %{ | |
| 8158 rolI_eReg_CL(dst, shift, cr); | |
| 8159 %} | |
| 8160 %} | |
| 8161 | |
| 8162 // ROL 32bit var by var once | |
| 8163 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8164 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8165 | |
| 8166 expand %{ | |
| 8167 rolI_eReg_CL(dst, shift, cr); | |
| 8168 %} | |
| 8169 %} | |
| 8170 | |
| 8171 // ROR expand | |
|
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8172 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8173 effect(USE_DEF dst, USE shift, KILL cr); |
| 8174 | |
| 8175 format %{ "ROR $dst, $shift" %} | |
| 8176 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8177 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8178 ins_pipe( ialu_reg ); | |
| 8179 %} | |
| 8180 | |
|
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8181 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8182 effect (USE_DEF dst, USE shift, KILL cr); |
| 8183 | |
| 8184 format %{ "ROR $dst, $shift" %} | |
| 8185 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8186 ins_encode( RegOpcImm(dst, shift) ); | |
| 8187 ins_pipe( ialu_reg ); | |
| 8188 %} | |
| 8189 | |
| 8190 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8191 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8192 | |
| 8193 format %{ "ROR $dst, $shift" %} | |
| 8194 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8195 ins_encode(OpcP, RegOpc(dst)); | |
| 8196 ins_pipe( ialu_reg_reg ); | |
| 8197 %} | |
| 8198 // end of ROR expand | |
| 8199 | |
| 8200 // ROR right once | |
|
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8201 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8202 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8203 | |
| 8204 expand %{ | |
| 8205 rorI_eReg_imm1(dst, rshift, cr); | |
| 8206 %} | |
| 8207 %} | |
| 8208 | |
| 8209 // ROR 32bit by immI8 once | |
|
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8210 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8211 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8212 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8213 | |
| 8214 expand %{ | |
| 8215 rorI_eReg_imm8(dst, rshift, cr); | |
| 8216 %} | |
| 8217 %} | |
| 8218 | |
| 8219 // ROR 32bit var by var once | |
| 8220 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8221 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8222 | |
| 8223 expand %{ | |
| 8224 rorI_eReg_CL(dst, shift, cr); | |
| 8225 %} | |
| 8226 %} | |
| 8227 | |
| 8228 // ROR 32bit var by var once | |
| 8229 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8230 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8231 | |
| 8232 expand %{ | |
| 8233 rorI_eReg_CL(dst, shift, cr); | |
| 8234 %} | |
| 8235 %} | |
| 8236 | |
| 8237 // Xor Instructions | |
| 8238 // Xor Register with Register | |
|
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8239 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8240 match(Set dst (XorI dst src)); |
| 8241 effect(KILL cr); | |
| 8242 | |
| 8243 size(2); | |
| 8244 format %{ "XOR $dst,$src" %} | |
| 8245 opcode(0x33); | |
| 8246 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8247 ins_pipe( ialu_reg_reg ); | |
| 8248 %} | |
| 8249 | |
| 403 | 8250 // Xor Register with Immediate -1 |
|
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8251 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8252 match(Set dst (XorI dst imm)); |
| 8253 | |
| 8254 size(2); | |
| 8255 format %{ "NOT $dst" %} | |
| 8256 ins_encode %{ | |
| 8257 __ notl($dst$$Register); | |
| 8258 %} | |
| 8259 ins_pipe( ialu_reg ); | |
| 8260 %} | |
| 8261 | |
| 0 | 8262 // Xor Register with Immediate |
|
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8263 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8264 match(Set dst (XorI dst src)); |
| 8265 effect(KILL cr); | |
| 8266 | |
| 8267 format %{ "XOR $dst,$src" %} | |
| 8268 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8269 // ins_encode( RegImm( dst, src) ); | |
| 8270 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8271 ins_pipe( ialu_reg ); | |
| 8272 %} | |
| 8273 | |
| 8274 // Xor Register with Memory | |
|
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8275 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8276 match(Set dst (XorI dst (LoadI src))); |
| 8277 effect(KILL cr); | |
| 8278 | |
| 8279 ins_cost(125); | |
| 8280 format %{ "XOR $dst,$src" %} | |
| 8281 opcode(0x33); | |
| 8282 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8283 ins_pipe( ialu_reg_mem ); | |
| 8284 %} | |
| 8285 | |
| 8286 // Xor Memory with Register | |
|
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8287 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8288 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8289 effect(KILL cr); | |
| 8290 | |
| 8291 ins_cost(150); | |
| 8292 format %{ "XOR $dst,$src" %} | |
| 8293 opcode(0x31); /* Opcode 31 /r */ | |
| 8294 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8295 ins_pipe( ialu_mem_reg ); | |
| 8296 %} | |
| 8297 | |
| 8298 // Xor Memory with Immediate | |
| 8299 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8300 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8301 effect(KILL cr); | |
| 8302 | |
| 8303 ins_cost(125); | |
| 8304 format %{ "XOR $dst,$src" %} | |
| 8305 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8306 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8307 ins_pipe( ialu_mem_imm ); | |
| 8308 %} | |
| 8309 | |
| 8310 //----------Convert Int to Boolean--------------------------------------------- | |
| 8311 | |
|
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8312 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8313 effect( DEF dst, USE src ); |
| 8314 format %{ "MOV $dst,$src" %} | |
| 8315 ins_encode( enc_Copy( dst, src) ); | |
| 8316 ins_pipe( ialu_reg_reg ); | |
| 8317 %} | |
| 8318 | |
|
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8319 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8320 effect( USE_DEF dst, USE src, KILL cr ); |
| 8321 | |
| 8322 size(4); | |
| 8323 format %{ "NEG $dst\n\t" | |
| 8324 "ADC $dst,$src" %} | |
| 8325 ins_encode( neg_reg(dst), | |
| 8326 OpcRegReg(0x13,dst,src) ); | |
| 8327 ins_pipe( ialu_reg_reg_long ); | |
| 8328 %} | |
| 8329 | |
|
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8330 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8331 match(Set dst (Conv2B src)); |
| 8332 | |
| 8333 expand %{ | |
| 8334 movI_nocopy(dst,src); | |
| 8335 ci2b(dst,src,cr); | |
| 8336 %} | |
| 8337 %} | |
| 8338 | |
|
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8339 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8340 effect( DEF dst, USE src ); |
| 8341 format %{ "MOV $dst,$src" %} | |
| 8342 ins_encode( enc_Copy( dst, src) ); | |
| 8343 ins_pipe( ialu_reg_reg ); | |
| 8344 %} | |
| 8345 | |
|
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8346 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8347 effect( USE_DEF dst, USE src, KILL cr ); |
| 8348 format %{ "NEG $dst\n\t" | |
| 8349 "ADC $dst,$src" %} | |
| 8350 ins_encode( neg_reg(dst), | |
| 8351 OpcRegReg(0x13,dst,src) ); | |
| 8352 ins_pipe( ialu_reg_reg_long ); | |
| 8353 %} | |
| 8354 | |
|
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8355 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8356 match(Set dst (Conv2B src)); |
| 8357 | |
| 8358 expand %{ | |
| 8359 movP_nocopy(dst,src); | |
| 8360 cp2b(dst,src,cr); | |
| 8361 %} | |
| 8362 %} | |
| 8363 | |
| 9154 | 8364 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8365 match(Set dst (CmpLTMask p q)); |
| 9154 | 8366 effect(KILL cr); |
| 0 | 8367 ins_cost(400); |
| 8368 | |
| 8369 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8370 format %{ "XOR $dst,$dst\n\t" | |
| 8371 "CMP $p,$q\n\t" | |
| 8372 "SETlt $dst\n\t" | |
| 8373 "NEG $dst" %} | |
| 9154 | 8374 ins_encode %{ |
| 8375 Register Rp = $p$$Register; | |
| 8376 Register Rq = $q$$Register; | |
| 8377 Register Rd = $dst$$Register; | |
| 8378 Label done; | |
| 8379 __ xorl(Rd, Rd); | |
| 8380 __ cmpl(Rp, Rq); | |
| 8381 __ setb(Assembler::less, Rd); | |
| 8382 __ negl(Rd); | |
| 8383 %} | |
| 8384 | |
| 8385 ins_pipe(pipe_slow); | |
| 8386 %} | |
| 8387 | |
| 8388 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 8389 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 8390 effect(DEF dst, KILL cr); |
| 0 | 8391 ins_cost(100); |
| 8392 | |
| 9154 | 8393 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 8394 ins_encode %{ | |
| 8395 __ sarl($dst$$Register, 31); | |
| 8396 %} | |
| 8397 ins_pipe(ialu_reg); | |
| 8398 %} | |
| 8399 | |
| 8400 /* better to save a register than avoid a branch */ | |
| 8401 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 8402 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 8403 effect(KILL cr); |
| 0 | 8404 ins_cost(400); |
| 9154 | 8405 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 8406 "JGE done\n\t" | |
| 8407 "ADD $p,$y\n" | |
| 8408 "done: " %} | |
| 8409 ins_encode %{ | |
| 8410 Register Rp = $p$$Register; | |
| 8411 Register Rq = $q$$Register; | |
| 8412 Register Ry = $y$$Register; | |
| 8413 Label done; | |
| 8414 __ subl(Rp, Rq); | |
| 8415 __ jccb(Assembler::greaterEqual, done); | |
| 8416 __ addl(Rp, Ry); | |
| 8417 __ bind(done); | |
| 8418 %} | |
| 8419 | |
| 8420 ins_pipe(pipe_cmplt); | |
| 8421 %} | |
| 8422 | |
| 8423 /* better to save a register than avoid a branch */ | |
| 8424 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 8425 match(Set y (AndI (CmpLTMask p q) y)); | |
| 8426 effect(KILL cr); | |
| 8427 | |
| 8428 ins_cost(300); | |
| 8429 | |
| 8430 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 8431 "JLT done\n\t" | |
| 8432 "XORL $y, $y\n" | |
| 8433 "done: " %} | |
| 8434 ins_encode %{ | |
| 8435 Register Rp = $p$$Register; | |
| 8436 Register Rq = $q$$Register; | |
| 8437 Register Ry = $y$$Register; | |
| 8438 Label done; | |
| 8439 __ cmpl(Rp, Rq); | |
| 8440 __ jccb(Assembler::less, done); | |
| 8441 __ xorl(Ry, Ry); | |
| 8442 __ bind(done); | |
| 8443 %} | |
| 8444 | |
| 8445 ins_pipe(pipe_cmplt); | |
| 0 | 8446 %} |
| 8447 | |
| 8448 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 8449 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 8450 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 8451 */ | |
|
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8452 //----------Overflow Math Instructions----------------------------------------- |
|
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8453 |
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8454 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
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8455 %{ |
|
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8456 match(Set cr (OverflowAddI op1 op2)); |
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8457 effect(DEF cr, USE_KILL op1, USE op2); |
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8458 |
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8459 format %{ "ADD $op1, $op2\t# overflow check int" %} |
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8460 |
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8461 ins_encode %{ |
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8462 __ addl($op1$$Register, $op2$$Register); |
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8463 %} |
|
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8464 ins_pipe(ialu_reg_reg); |
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8465 %} |
|
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|
8466 |
|
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8467 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
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8468 %{ |
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8469 match(Set cr (OverflowAddI op1 op2)); |
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8470 effect(DEF cr, USE_KILL op1, USE op2); |
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8471 |
|
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8472 format %{ "ADD $op1, $op2\t# overflow check int" %} |
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8473 |
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8474 ins_encode %{ |
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|
8475 __ addl($op1$$Register, $op2$$constant); |
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8476 %} |
|
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|
8477 ins_pipe(ialu_reg_reg); |
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8478 %} |
|
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|
8479 |
|
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8480 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
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8481 %{ |
|
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8482 match(Set cr (OverflowSubI op1 op2)); |
|
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|
8483 |
|
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8484 format %{ "CMP $op1, $op2\t# overflow check int" %} |
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8485 ins_encode %{ |
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8486 __ cmpl($op1$$Register, $op2$$Register); |
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8487 %} |
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8488 ins_pipe(ialu_reg_reg); |
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8489 %} |
|
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|
8490 |
|
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|
8491 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
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8492 %{ |
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8493 match(Set cr (OverflowSubI op1 op2)); |
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8494 |
|
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8495 format %{ "CMP $op1, $op2\t# overflow check int" %} |
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8496 ins_encode %{ |
|
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8497 __ cmpl($op1$$Register, $op2$$constant); |
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8498 %} |
|
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8499 ins_pipe(ialu_reg_reg); |
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8500 %} |
|
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8501 |
|
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8502 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
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8503 %{ |
|
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8504 match(Set cr (OverflowSubI zero op2)); |
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8505 effect(DEF cr, USE_KILL op2); |
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8506 |
|
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8507 format %{ "NEG $op2\t# overflow check int" %} |
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8508 ins_encode %{ |
|
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|
8509 __ negl($op2$$Register); |
|
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|
8510 %} |
|
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|
8511 ins_pipe(ialu_reg_reg); |
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8512 %} |
|
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|
8513 |
|
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8514 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
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8515 %{ |
|
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8516 match(Set cr (OverflowMulI op1 op2)); |
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8517 effect(DEF cr, USE_KILL op1, USE op2); |
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8518 |
|
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8519 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
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8520 ins_encode %{ |
|
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8521 __ imull($op1$$Register, $op2$$Register); |
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|
8522 %} |
|
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8523 ins_pipe(ialu_reg_reg_alu0); |
|
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8524 %} |
|
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|
8525 |
|
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8526 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
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8527 %{ |
|
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8528 match(Set cr (OverflowMulI op1 op2)); |
|
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8529 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
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|
8530 |
|
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8531 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
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8532 ins_encode %{ |
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8533 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
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8534 %} |
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8535 ins_pipe(ialu_reg_reg_alu0); |
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8536 %} |
| 0 | 8537 |
| 8538 //----------Long Instructions------------------------------------------------ | |
| 8539 // Add Long Register with Register | |
| 8540 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8541 match(Set dst (AddL dst src)); | |
| 8542 effect(KILL cr); | |
| 8543 ins_cost(200); | |
| 8544 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8545 "ADC $dst.hi,$src.hi" %} | |
| 8546 opcode(0x03, 0x13); | |
| 8547 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8548 ins_pipe( ialu_reg_reg_long ); | |
| 8549 %} | |
| 8550 | |
| 8551 // Add Long Register with Immediate | |
| 8552 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8553 match(Set dst (AddL dst src)); | |
| 8554 effect(KILL cr); | |
| 8555 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8556 "ADC $dst.hi,$src.hi" %} | |
| 8557 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8558 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8559 ins_pipe( ialu_reg_long ); | |
| 8560 %} | |
| 8561 | |
| 8562 // Add Long Register with Memory | |
| 8563 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8564 match(Set dst (AddL dst (LoadL mem))); | |
| 8565 effect(KILL cr); | |
| 8566 ins_cost(125); | |
| 8567 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8568 "ADC $dst.hi,$mem+4" %} | |
| 8569 opcode(0x03, 0x13); | |
| 8570 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8571 ins_pipe( ialu_reg_long_mem ); | |
| 8572 %} | |
| 8573 | |
| 8574 // Subtract Long Register with Register. | |
| 8575 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8576 match(Set dst (SubL dst src)); | |
| 8577 effect(KILL cr); | |
| 8578 ins_cost(200); | |
| 8579 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8580 "SBB $dst.hi,$src.hi" %} | |
| 8581 opcode(0x2B, 0x1B); | |
| 8582 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8583 ins_pipe( ialu_reg_reg_long ); | |
| 8584 %} | |
| 8585 | |
| 8586 // Subtract Long Register with Immediate | |
| 8587 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8588 match(Set dst (SubL dst src)); | |
| 8589 effect(KILL cr); | |
| 8590 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8591 "SBB $dst.hi,$src.hi" %} | |
| 8592 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8593 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8594 ins_pipe( ialu_reg_long ); | |
| 8595 %} | |
| 8596 | |
| 8597 // Subtract Long Register with Memory | |
| 8598 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8599 match(Set dst (SubL dst (LoadL mem))); | |
| 8600 effect(KILL cr); | |
| 8601 ins_cost(125); | |
| 8602 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8603 "SBB $dst.hi,$mem+4" %} | |
| 8604 opcode(0x2B, 0x1B); | |
| 8605 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8606 ins_pipe( ialu_reg_long_mem ); | |
| 8607 %} | |
| 8608 | |
| 8609 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8610 match(Set dst (SubL zero dst)); | |
| 8611 effect(KILL cr); | |
| 8612 ins_cost(300); | |
| 8613 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8614 ins_encode( neg_long(dst) ); | |
| 8615 ins_pipe( ialu_reg_reg_long ); | |
| 8616 %} | |
| 8617 | |
| 8618 // And Long Register with Register | |
| 8619 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8620 match(Set dst (AndL dst src)); | |
| 8621 effect(KILL cr); | |
| 8622 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8623 "AND $dst.hi,$src.hi" %} | |
| 8624 opcode(0x23,0x23); | |
| 8625 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8626 ins_pipe( ialu_reg_reg_long ); | |
| 8627 %} | |
| 8628 | |
| 8629 // And Long Register with Immediate | |
| 8630 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8631 match(Set dst (AndL dst src)); | |
| 8632 effect(KILL cr); | |
| 8633 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8634 "AND $dst.hi,$src.hi" %} | |
| 8635 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 8636 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8637 ins_pipe( ialu_reg_long ); | |
| 8638 %} | |
| 8639 | |
| 8640 // And Long Register with Memory | |
| 8641 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8642 match(Set dst (AndL dst (LoadL mem))); | |
| 8643 effect(KILL cr); | |
| 8644 ins_cost(125); | |
| 8645 format %{ "AND $dst.lo,$mem\n\t" | |
| 8646 "AND $dst.hi,$mem+4" %} | |
| 8647 opcode(0x23, 0x23); | |
| 8648 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8649 ins_pipe( ialu_reg_long_mem ); | |
| 8650 %} | |
| 8651 | |
| 8652 // Or Long Register with Register | |
| 8653 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8654 match(Set dst (OrL dst src)); | |
| 8655 effect(KILL cr); | |
| 8656 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8657 "OR $dst.hi,$src.hi" %} | |
| 8658 opcode(0x0B,0x0B); | |
| 8659 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8660 ins_pipe( ialu_reg_reg_long ); | |
| 8661 %} | |
| 8662 | |
| 8663 // Or Long Register with Immediate | |
| 8664 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8665 match(Set dst (OrL dst src)); | |
| 8666 effect(KILL cr); | |
| 8667 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8668 "OR $dst.hi,$src.hi" %} | |
| 8669 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 8670 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8671 ins_pipe( ialu_reg_long ); | |
| 8672 %} | |
| 8673 | |
| 8674 // Or Long Register with Memory | |
| 8675 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8676 match(Set dst (OrL dst (LoadL mem))); | |
| 8677 effect(KILL cr); | |
| 8678 ins_cost(125); | |
| 8679 format %{ "OR $dst.lo,$mem\n\t" | |
| 8680 "OR $dst.hi,$mem+4" %} | |
| 8681 opcode(0x0B,0x0B); | |
| 8682 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8683 ins_pipe( ialu_reg_long_mem ); | |
| 8684 %} | |
| 8685 | |
| 8686 // Xor Long Register with Register | |
| 8687 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8688 match(Set dst (XorL dst src)); | |
| 8689 effect(KILL cr); | |
| 8690 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 8691 "XOR $dst.hi,$src.hi" %} | |
| 8692 opcode(0x33,0x33); | |
| 8693 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8694 ins_pipe( ialu_reg_reg_long ); | |
| 8695 %} | |
| 8696 | |
| 403 | 8697 // Xor Long Register with Immediate -1 |
| 8698 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 8699 match(Set dst (XorL dst imm)); | |
| 8700 format %{ "NOT $dst.lo\n\t" | |
| 8701 "NOT $dst.hi" %} | |
| 8702 ins_encode %{ | |
| 8703 __ notl($dst$$Register); | |
| 8704 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 8705 %} | |
| 8706 ins_pipe( ialu_reg_long ); | |
| 8707 %} | |
| 8708 | |
| 0 | 8709 // Xor Long Register with Immediate |
| 8710 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8711 match(Set dst (XorL dst src)); | |
| 8712 effect(KILL cr); | |
| 8713 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 8714 "XOR $dst.hi,$src.hi" %} | |
| 8715 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 8716 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8717 ins_pipe( ialu_reg_long ); | |
| 8718 %} | |
| 8719 | |
| 8720 // Xor Long Register with Memory | |
| 8721 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8722 match(Set dst (XorL dst (LoadL mem))); | |
| 8723 effect(KILL cr); | |
| 8724 ins_cost(125); | |
| 8725 format %{ "XOR $dst.lo,$mem\n\t" | |
| 8726 "XOR $dst.hi,$mem+4" %} | |
| 8727 opcode(0x33,0x33); | |
| 8728 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8729 ins_pipe( ialu_reg_long_mem ); | |
| 8730 %} | |
| 8731 | |
| 219 | 8732 // Shift Left Long by 1 |
| 8733 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 8734 predicate(UseNewLongLShift); | |
| 8735 match(Set dst (LShiftL dst cnt)); | |
| 8736 effect(KILL cr); | |
| 8737 ins_cost(100); | |
| 8738 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 8739 "ADC $dst.hi,$dst.hi" %} | |
| 8740 ins_encode %{ | |
| 8741 __ addl($dst$$Register,$dst$$Register); | |
| 8742 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8743 %} | |
| 8744 ins_pipe( ialu_reg_long ); | |
| 8745 %} | |
| 8746 | |
| 8747 // Shift Left Long by 2 | |
| 8748 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 8749 predicate(UseNewLongLShift); | |
| 8750 match(Set dst (LShiftL dst cnt)); | |
| 8751 effect(KILL cr); | |
| 8752 ins_cost(100); | |
| 8753 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 8754 "ADC $dst.hi,$dst.hi\n\t" | |
| 8755 "ADD $dst.lo,$dst.lo\n\t" | |
| 8756 "ADC $dst.hi,$dst.hi" %} | |
| 8757 ins_encode %{ | |
| 8758 __ addl($dst$$Register,$dst$$Register); | |
| 8759 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8760 __ addl($dst$$Register,$dst$$Register); | |
| 8761 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8762 %} | |
| 8763 ins_pipe( ialu_reg_long ); | |
| 8764 %} | |
| 8765 | |
| 8766 // Shift Left Long by 3 | |
| 8767 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 8768 predicate(UseNewLongLShift); | |
| 8769 match(Set dst (LShiftL dst cnt)); | |
| 8770 effect(KILL cr); | |
| 8771 ins_cost(100); | |
| 8772 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 8773 "ADC $dst.hi,$dst.hi\n\t" | |
| 8774 "ADD $dst.lo,$dst.lo\n\t" | |
| 8775 "ADC $dst.hi,$dst.hi\n\t" | |
| 8776 "ADD $dst.lo,$dst.lo\n\t" | |
| 8777 "ADC $dst.hi,$dst.hi" %} | |
| 8778 ins_encode %{ | |
| 8779 __ addl($dst$$Register,$dst$$Register); | |
| 8780 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8781 __ addl($dst$$Register,$dst$$Register); | |
| 8782 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8783 __ addl($dst$$Register,$dst$$Register); | |
| 8784 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 8785 %} | |
| 8786 ins_pipe( ialu_reg_long ); | |
| 8787 %} | |
| 8788 | |
| 0 | 8789 // Shift Left Long by 1-31 |
| 8790 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 8791 match(Set dst (LShiftL dst cnt)); | |
| 8792 effect(KILL cr); | |
| 8793 ins_cost(200); | |
| 8794 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 8795 "SHL $dst.lo,$cnt" %} | |
| 8796 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 8797 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 8798 ins_pipe( ialu_reg_long ); | |
| 8799 %} | |
| 8800 | |
| 8801 // Shift Left Long by 32-63 | |
| 8802 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8803 match(Set dst (LShiftL dst cnt)); | |
| 8804 effect(KILL cr); | |
| 8805 ins_cost(300); | |
| 8806 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 8807 "\tSHL $dst.hi,$cnt-32\n" | |
| 8808 "\tXOR $dst.lo,$dst.lo" %} | |
| 8809 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8810 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 8811 ins_pipe( ialu_reg_long ); | |
| 8812 %} | |
| 8813 | |
| 8814 // Shift Left Long by variable | |
| 8815 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8816 match(Set dst (LShiftL dst shift)); | |
| 8817 effect(KILL cr); | |
| 8818 ins_cost(500+200); | |
| 8819 size(17); | |
| 8820 format %{ "TEST $shift,32\n\t" | |
| 8821 "JEQ,s small\n\t" | |
| 8822 "MOV $dst.hi,$dst.lo\n\t" | |
| 8823 "XOR $dst.lo,$dst.lo\n" | |
| 8824 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 8825 "SHL $dst.lo,$shift" %} | |
| 8826 ins_encode( shift_left_long( dst, shift ) ); | |
| 8827 ins_pipe( pipe_slow ); | |
| 8828 %} | |
| 8829 | |
| 8830 // Shift Right Long by 1-31 | |
| 8831 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 8832 match(Set dst (URShiftL dst cnt)); | |
| 8833 effect(KILL cr); | |
| 8834 ins_cost(200); | |
| 8835 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 8836 "SHR $dst.hi,$cnt" %} | |
| 8837 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 8838 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 8839 ins_pipe( ialu_reg_long ); | |
| 8840 %} | |
| 8841 | |
| 8842 // Shift Right Long by 32-63 | |
| 8843 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8844 match(Set dst (URShiftL dst cnt)); | |
| 8845 effect(KILL cr); | |
| 8846 ins_cost(300); | |
| 8847 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 8848 "\tSHR $dst.lo,$cnt-32\n" | |
| 8849 "\tXOR $dst.hi,$dst.hi" %} | |
| 8850 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8851 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 8852 ins_pipe( ialu_reg_long ); | |
| 8853 %} | |
| 8854 | |
| 8855 // Shift Right Long by variable | |
| 8856 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8857 match(Set dst (URShiftL dst shift)); | |
| 8858 effect(KILL cr); | |
| 8859 ins_cost(600); | |
| 8860 size(17); | |
| 8861 format %{ "TEST $shift,32\n\t" | |
| 8862 "JEQ,s small\n\t" | |
| 8863 "MOV $dst.lo,$dst.hi\n\t" | |
| 8864 "XOR $dst.hi,$dst.hi\n" | |
| 8865 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 8866 "SHR $dst.hi,$shift" %} | |
| 8867 ins_encode( shift_right_long( dst, shift ) ); | |
| 8868 ins_pipe( pipe_slow ); | |
| 8869 %} | |
| 8870 | |
| 8871 // Shift Right Long by 1-31 | |
| 8872 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 8873 match(Set dst (RShiftL dst cnt)); | |
| 8874 effect(KILL cr); | |
| 8875 ins_cost(200); | |
| 8876 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 8877 "SAR $dst.hi,$cnt" %} | |
| 8878 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 8879 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 8880 ins_pipe( ialu_reg_long ); | |
| 8881 %} | |
| 8882 | |
| 8883 // Shift Right Long by 32-63 | |
| 8884 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8885 match(Set dst (RShiftL dst cnt)); | |
| 8886 effect(KILL cr); | |
| 8887 ins_cost(300); | |
| 8888 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 8889 "\tSAR $dst.lo,$cnt-32\n" | |
| 8890 "\tSAR $dst.hi,31" %} | |
| 8891 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8892 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 8893 ins_pipe( ialu_reg_long ); | |
| 8894 %} | |
| 8895 | |
| 8896 // Shift Right arithmetic Long by variable | |
| 8897 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8898 match(Set dst (RShiftL dst shift)); | |
| 8899 effect(KILL cr); | |
| 8900 ins_cost(600); | |
| 8901 size(18); | |
| 8902 format %{ "TEST $shift,32\n\t" | |
| 8903 "JEQ,s small\n\t" | |
| 8904 "MOV $dst.lo,$dst.hi\n\t" | |
| 8905 "SAR $dst.hi,31\n" | |
| 8906 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 8907 "SAR $dst.hi,$shift" %} | |
| 8908 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 8909 ins_pipe( pipe_slow ); | |
| 8910 %} | |
| 8911 | |
| 8912 | |
| 8913 //----------Double Instructions------------------------------------------------ | |
| 8914 // Double Math | |
| 8915 | |
| 8916 // Compare & branch | |
| 8917 | |
| 8918 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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8919 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 8920 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 8921 match(Set cr (CmpD src1 src2)); | |
| 8922 effect(KILL rax); | |
| 8923 ins_cost(150); | |
| 8924 format %{ "FLD $src1\n\t" | |
| 8925 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 8926 "JNP exit\n\t" | |
| 8927 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 8928 "SAHF\n" | |
| 8929 "exit:\tNOP // avoid branch to branch" %} | |
| 8930 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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8931 ins_encode( Push_Reg_DPR(src1), |
| 0 | 8932 OpcP, RegOpc(src2), |
| 8933 cmpF_P6_fixup ); | |
| 8934 ins_pipe( pipe_slow ); | |
| 8935 %} | |
| 8936 | |
|
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8937 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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|
8938 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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|
8939 match(Set cr (CmpD src1 src2)); |
|
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|
8940 ins_cost(150); |
|
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|
8941 format %{ "FLD $src1\n\t" |
|
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|
8942 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
8943 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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8944 ins_encode( Push_Reg_DPR(src1), |
|
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|
8945 OpcP, RegOpc(src2)); |
|
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|
8946 ins_pipe( pipe_slow ); |
|
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|
8947 %} |
|
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|
8948 |
| 0 | 8949 // Compare & branch |
|
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8950 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 8951 predicate(UseSSE<=1); |
| 8952 match(Set cr (CmpD src1 src2)); | |
| 8953 effect(KILL rax); | |
| 8954 ins_cost(200); | |
| 8955 format %{ "FLD $src1\n\t" | |
| 8956 "FCOMp $src2\n\t" | |
| 8957 "FNSTSW AX\n\t" | |
| 8958 "TEST AX,0x400\n\t" | |
| 8959 "JZ,s flags\n\t" | |
| 8960 "MOV AH,1\t# unordered treat as LT\n" | |
| 8961 "flags:\tSAHF" %} | |
| 8962 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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8963 ins_encode( Push_Reg_DPR(src1), |
| 0 | 8964 OpcP, RegOpc(src2), |
| 8965 fpu_flags); | |
| 8966 ins_pipe( pipe_slow ); | |
| 8967 %} | |
| 8968 | |
| 8969 // Compare vs zero into -1,0,1 | |
|
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8970 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 8971 predicate(UseSSE<=1); |
| 8972 match(Set dst (CmpD3 src1 zero)); | |
| 8973 effect(KILL cr, KILL rax); | |
| 8974 ins_cost(280); | |
| 8975 format %{ "FTSTD $dst,$src1" %} | |
| 8976 opcode(0xE4, 0xD9); | |
|
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8977 ins_encode( Push_Reg_DPR(src1), |
| 0 | 8978 OpcS, OpcP, PopFPU, |
| 8979 CmpF_Result(dst)); | |
| 8980 ins_pipe( pipe_slow ); | |
| 8981 %} | |
| 8982 | |
| 8983 // Compare into -1,0,1 | |
|
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8984 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 8985 predicate(UseSSE<=1); |
| 8986 match(Set dst (CmpD3 src1 src2)); | |
| 8987 effect(KILL cr, KILL rax); | |
| 8988 ins_cost(300); | |
| 8989 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 8990 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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8991 ins_encode( Push_Reg_DPR(src1), |
| 0 | 8992 OpcP, RegOpc(src2), |
| 8993 CmpF_Result(dst)); | |
| 8994 ins_pipe( pipe_slow ); | |
| 8995 %} | |
| 8996 | |
| 8997 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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8998 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 8999 predicate(UseSSE>=2); |
| 4759 | 9000 match(Set cr (CmpD src1 src2)); |
| 9001 ins_cost(145); | |
| 9002 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9003 "JNP,s exit\n\t" | |
| 9004 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9005 "AND [rsp], #0xffffff2b\n\t" | |
| 9006 "POPF\n" | |
| 9007 "exit:" %} | |
| 9008 ins_encode %{ | |
| 9009 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9010 emit_cmpfp_fixup(_masm); | |
| 9011 %} | |
| 9012 ins_pipe( pipe_slow ); | |
| 9013 %} | |
| 9014 | |
|
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9015 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9016 predicate(UseSSE>=2); |
| 4759 | 9017 match(Set cr (CmpD src1 src2)); |
|
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|
9018 ins_cost(100); |
| 4759 | 9019 format %{ "UCOMISD $src1,$src2" %} |
| 9020 ins_encode %{ | |
| 9021 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9022 %} | |
|
415
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|
9023 ins_pipe( pipe_slow ); |
|
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diff
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|
9024 %} |
|
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|
9025 |
| 0 | 9026 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
9027 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9028 predicate(UseSSE>=2); |
| 4759 | 9029 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9030 ins_cost(145); |
| 4759 | 9031 format %{ "UCOMISD $src1,$src2\n\t" |
| 9032 "JNP,s exit\n\t" | |
| 9033 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9034 "AND [rsp], #0xffffff2b\n\t" | |
| 9035 "POPF\n" | |
| 9036 "exit:" %} | |
| 9037 ins_encode %{ | |
| 9038 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9039 emit_cmpfp_fixup(_masm); | |
| 9040 %} | |
| 9041 ins_pipe( pipe_slow ); | |
| 9042 %} | |
| 9043 | |
|
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|
9044 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9045 predicate(UseSSE>=2); |
| 4759 | 9046 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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|
9047 ins_cost(100); |
| 4759 | 9048 format %{ "UCOMISD $src1,$src2" %} |
| 9049 ins_encode %{ | |
| 9050 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9051 %} | |
|
415
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|
9052 ins_pipe( pipe_slow ); |
|
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diff
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|
9053 %} |
|
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|
9054 |
| 0 | 9055 // Compare into -1,0,1 in XMM |
|
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9056 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9057 predicate(UseSSE>=2); |
| 9058 match(Set dst (CmpD3 src1 src2)); | |
| 9059 effect(KILL cr); | |
| 9060 ins_cost(255); | |
| 4759 | 9061 format %{ "UCOMISD $src1, $src2\n\t" |
| 9062 "MOV $dst, #-1\n\t" | |
| 9063 "JP,s done\n\t" | |
| 9064 "JB,s done\n\t" | |
| 9065 "SETNE $dst\n\t" | |
| 9066 "MOVZB $dst, $dst\n" | |
| 9067 "done:" %} | |
| 9068 ins_encode %{ | |
| 9069 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9070 emit_cmpfp3(_masm, $dst$$Register); | |
| 9071 %} | |
| 0 | 9072 ins_pipe( pipe_slow ); |
| 9073 %} | |
| 9074 | |
| 9075 // Compare into -1,0,1 in XMM and memory | |
|
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|
9076 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9077 predicate(UseSSE>=2); |
| 4759 | 9078 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9079 effect(KILL cr); |
| 9080 ins_cost(275); | |
| 4759 | 9081 format %{ "UCOMISD $src1, $src2\n\t" |
| 9082 "MOV $dst, #-1\n\t" | |
| 9083 "JP,s done\n\t" | |
| 9084 "JB,s done\n\t" | |
| 9085 "SETNE $dst\n\t" | |
| 9086 "MOVZB $dst, $dst\n" | |
| 9087 "done:" %} | |
| 9088 ins_encode %{ | |
| 9089 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9090 emit_cmpfp3(_masm, $dst$$Register); | |
| 9091 %} | |
| 0 | 9092 ins_pipe( pipe_slow ); |
| 9093 %} | |
| 9094 | |
| 9095 | |
|
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|
9096 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9097 predicate (UseSSE <=1); |
| 9098 match(Set dst (SubD dst src)); | |
| 9099 | |
| 9100 format %{ "FLD $src\n\t" | |
| 9101 "DSUBp $dst,ST" %} | |
| 9102 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9103 ins_cost(150); | |
|
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|
9104 ins_encode( Push_Reg_DPR(src), |
| 0 | 9105 OpcP, RegOpc(dst) ); |
| 9106 ins_pipe( fpu_reg_reg ); | |
| 9107 %} | |
| 9108 | |
|
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9109 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9110 predicate (UseSSE <=1); |
| 9111 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9112 ins_cost(250); | |
| 9113 | |
| 9114 format %{ "FLD $src2\n\t" | |
| 9115 "DSUB ST,$src1\n\t" | |
| 9116 "FSTP_D $dst\t# D-round" %} | |
| 9117 opcode(0xD8, 0x5); | |
|
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|
9118 ins_encode( Push_Reg_DPR(src2), |
|
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|
9119 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9120 ins_pipe( fpu_mem_reg_reg ); |
| 9121 %} | |
| 9122 | |
| 9123 | |
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9124 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9125 predicate (UseSSE <=1); |
| 9126 match(Set dst (SubD dst (LoadD src))); | |
| 9127 ins_cost(150); | |
| 9128 | |
| 9129 format %{ "FLD $src\n\t" | |
| 9130 "DSUBp $dst,ST" %} | |
| 9131 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9132 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9133 OpcP, RegOpc(dst) ); | |
| 9134 ins_pipe( fpu_reg_mem ); | |
| 9135 %} | |
| 9136 | |
|
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9137 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9138 predicate (UseSSE<=1); |
| 9139 match(Set dst (AbsD src)); | |
| 9140 ins_cost(100); | |
| 9141 format %{ "FABS" %} | |
| 9142 opcode(0xE1, 0xD9); | |
| 9143 ins_encode( OpcS, OpcP ); | |
| 9144 ins_pipe( fpu_reg_reg ); | |
| 9145 %} | |
| 9146 | |
|
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9147 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9148 predicate(UseSSE<=1); |
| 9149 match(Set dst (NegD src)); | |
| 9150 ins_cost(100); | |
| 9151 format %{ "FCHS" %} | |
| 9152 opcode(0xE0, 0xD9); | |
| 9153 ins_encode( OpcS, OpcP ); | |
| 9154 ins_pipe( fpu_reg_reg ); | |
| 9155 %} | |
| 9156 | |
|
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9157 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9158 predicate(UseSSE<=1); |
| 9159 match(Set dst (AddD dst src)); | |
| 9160 format %{ "FLD $src\n\t" | |
| 9161 "DADD $dst,ST" %} | |
| 9162 size(4); | |
| 9163 ins_cost(150); | |
| 9164 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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9165 ins_encode( Push_Reg_DPR(src), |
| 0 | 9166 OpcP, RegOpc(dst) ); |
| 9167 ins_pipe( fpu_reg_reg ); | |
| 9168 %} | |
| 9169 | |
| 9170 | |
|
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9171 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9172 predicate(UseSSE<=1); |
| 9173 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9174 ins_cost(250); | |
| 9175 | |
| 9176 format %{ "FLD $src2\n\t" | |
| 9177 "DADD ST,$src1\n\t" | |
| 9178 "FSTP_D $dst\t# D-round" %} | |
| 9179 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
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9180 ins_encode( Push_Reg_DPR(src2), |
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9181 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9182 ins_pipe( fpu_mem_reg_reg ); |
| 9183 %} | |
| 9184 | |
| 9185 | |
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9186 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9187 predicate(UseSSE<=1); |
| 9188 match(Set dst (AddD dst (LoadD src))); | |
| 9189 ins_cost(150); | |
| 9190 | |
| 9191 format %{ "FLD $src\n\t" | |
| 9192 "DADDp $dst,ST" %} | |
| 9193 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9194 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9195 OpcP, RegOpc(dst) ); | |
| 9196 ins_pipe( fpu_reg_mem ); | |
| 9197 %} | |
| 9198 | |
| 9199 // add-to-memory | |
|
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9200 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9201 predicate(UseSSE<=1); |
| 9202 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9203 ins_cost(150); | |
| 9204 | |
| 9205 format %{ "FLD_D $dst\n\t" | |
| 9206 "DADD ST,$src\n\t" | |
| 9207 "FST_D $dst" %} | |
| 9208 opcode(0xDD, 0x0); | |
| 9209 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9210 Opcode(0xD8), RegOpc(src), | |
| 9211 set_instruction_start, | |
| 9212 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9213 ins_pipe( fpu_reg_mem ); | |
| 9214 %} | |
| 9215 | |
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9216 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9217 predicate(UseSSE<=1); |
| 2008 | 9218 match(Set dst (AddD dst con)); |
| 0 | 9219 ins_cost(125); |
| 9220 format %{ "FLD1\n\t" | |
| 9221 "DADDp $dst,ST" %} | |
| 2008 | 9222 ins_encode %{ |
| 9223 __ fld1(); | |
| 9224 __ faddp($dst$$reg); | |
| 9225 %} | |
| 9226 ins_pipe(fpu_reg); | |
| 9227 %} | |
| 9228 | |
|
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9229 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9230 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9231 match(Set dst (AddD dst con)); |
| 0 | 9232 ins_cost(200); |
| 2008 | 9233 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9234 "DADDp $dst,ST" %} |
| 2008 | 9235 ins_encode %{ |
| 9236 __ fld_d($constantaddress($con)); | |
| 9237 __ faddp($dst$$reg); | |
| 9238 %} | |
| 9239 ins_pipe(fpu_reg_mem); | |
| 0 | 9240 %} |
| 9241 | |
|
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9242 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9243 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9244 match(Set dst (RoundDouble (AddD src con))); | |
| 9245 ins_cost(200); | |
| 2008 | 9246 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9247 "DADD ST,$src\n\t" |
| 9248 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9249 ins_encode %{ |
| 9250 __ fld_d($constantaddress($con)); | |
| 9251 __ fadd($src$$reg); | |
| 9252 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9253 %} | |
| 9254 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9255 %} |
| 9256 | |
|
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9257 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9258 predicate(UseSSE<=1); |
| 9259 match(Set dst (MulD dst src)); | |
| 9260 format %{ "FLD $src\n\t" | |
| 9261 "DMULp $dst,ST" %} | |
| 9262 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9263 ins_cost(150); | |
|
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9264 ins_encode( Push_Reg_DPR(src), |
| 0 | 9265 OpcP, RegOpc(dst) ); |
| 9266 ins_pipe( fpu_reg_reg ); | |
| 9267 %} | |
| 9268 | |
| 9269 // Strict FP instruction biases argument before multiply then | |
| 9270 // biases result to avoid double rounding of subnormals. | |
| 9271 // | |
| 9272 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9273 // load arg2 | |
| 9274 // multiply scaled arg1 by arg2 | |
| 9275 // rescale product by 2^(15360) | |
| 9276 // | |
|
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9277 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9278 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9279 match(Set dst (MulD dst src)); | |
| 9280 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9281 | |
| 9282 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9283 "DMULp $dst,ST\n\t" | |
| 9284 "FLD $src\n\t" | |
| 9285 "DMULp $dst,ST\n\t" | |
| 9286 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9287 "DMULp $dst,ST\n\t" %} | |
| 9288 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9289 ins_encode( strictfp_bias1(dst), | |
|
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9290 Push_Reg_DPR(src), |
| 0 | 9291 OpcP, RegOpc(dst), |
| 9292 strictfp_bias2(dst) ); | |
| 9293 ins_pipe( fpu_reg_reg ); | |
| 9294 %} | |
| 9295 | |
|
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9296 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9297 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9298 match(Set dst (MulD dst con)); |
| 0 | 9299 ins_cost(200); |
| 2008 | 9300 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9301 "DMULp $dst,ST" %} |
| 2008 | 9302 ins_encode %{ |
| 9303 __ fld_d($constantaddress($con)); | |
| 9304 __ fmulp($dst$$reg); | |
| 9305 %} | |
| 9306 ins_pipe(fpu_reg_mem); | |
| 0 | 9307 %} |
| 9308 | |
| 9309 | |
|
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9310 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9311 predicate( UseSSE<=1 ); |
| 9312 match(Set dst (MulD dst (LoadD src))); | |
| 9313 ins_cost(200); | |
| 9314 format %{ "FLD_D $src\n\t" | |
| 9315 "DMULp $dst,ST" %} | |
| 9316 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9317 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9318 OpcP, RegOpc(dst) ); | |
| 9319 ins_pipe( fpu_reg_mem ); | |
| 9320 %} | |
| 9321 | |
| 9322 // | |
| 9323 // Cisc-alternate to reg-reg multiply | |
|
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9324 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9325 predicate( UseSSE<=1 ); |
| 9326 match(Set dst (MulD src (LoadD mem))); | |
| 9327 ins_cost(250); | |
| 9328 format %{ "FLD_D $mem\n\t" | |
| 9329 "DMUL ST,$src\n\t" | |
| 9330 "FSTP_D $dst" %} | |
| 9331 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9332 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9333 OpcReg_FPR(src), |
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9334 Pop_Reg_DPR(dst) ); |
| 0 | 9335 ins_pipe( fpu_reg_reg_mem ); |
| 9336 %} | |
| 9337 | |
| 9338 | |
|
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9339 // MACRO3 -- addDPR a mulDPR |
| 0 | 9340 // This instruction is a '2-address' instruction in that the result goes |
| 9341 // back to src2. This eliminates a move from the macro; possibly the | |
| 9342 // register allocator will have to add it back (and maybe not). | |
|
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9343 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9344 predicate( UseSSE<=1 ); |
| 9345 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9346 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9347 "DMUL ST,$src1\n\t" | |
| 9348 "DADDp $src2,ST" %} | |
| 9349 ins_cost(250); | |
| 9350 opcode(0xDD); /* LoadD DD /0 */ | |
|
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9351 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9352 FMul_ST_reg(src1), |
| 9353 FAddP_reg_ST(src2) ); | |
| 9354 ins_pipe( fpu_reg_reg_reg ); | |
| 9355 %} | |
| 9356 | |
| 9357 | |
|
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9358 // MACRO3 -- subDPR a mulDPR |
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9359 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9360 predicate( UseSSE<=1 ); |
| 9361 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9362 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9363 "DMUL ST,$src1\n\t" | |
| 9364 "DSUBRp $src2,ST" %} | |
| 9365 ins_cost(250); | |
|
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9366 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9367 FMul_ST_reg(src1), |
| 9368 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9369 ins_pipe( fpu_reg_reg_reg ); | |
| 9370 %} | |
| 9371 | |
| 9372 | |
|
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9373 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9374 predicate( UseSSE<=1 ); |
| 9375 match(Set dst (DivD dst src)); | |
| 9376 | |
| 9377 format %{ "FLD $src\n\t" | |
| 9378 "FDIVp $dst,ST" %} | |
| 9379 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9380 ins_cost(150); | |
|
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9381 ins_encode( Push_Reg_DPR(src), |
| 0 | 9382 OpcP, RegOpc(dst) ); |
| 9383 ins_pipe( fpu_reg_reg ); | |
| 9384 %} | |
| 9385 | |
| 9386 // Strict FP instruction biases argument before division then | |
| 9387 // biases result, to avoid double rounding of subnormals. | |
| 9388 // | |
| 9389 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9390 // load divisor | |
| 9391 // divide scaled dividend by divisor | |
| 9392 // rescale quotient by 2^(15360) | |
| 9393 // | |
|
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9394 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9395 predicate (UseSSE<=1); |
| 9396 match(Set dst (DivD dst src)); | |
| 9397 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9398 ins_cost(01); | |
| 9399 | |
| 9400 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9401 "DMULp $dst,ST\n\t" | |
| 9402 "FLD $src\n\t" | |
| 9403 "FDIVp $dst,ST\n\t" | |
| 9404 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9405 "DMULp $dst,ST\n\t" %} | |
| 9406 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9407 ins_encode( strictfp_bias1(dst), | |
|
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9408 Push_Reg_DPR(src), |
| 0 | 9409 OpcP, RegOpc(dst), |
| 9410 strictfp_bias2(dst) ); | |
| 9411 ins_pipe( fpu_reg_reg ); | |
| 9412 %} | |
| 9413 | |
|
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9414 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9415 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9416 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9417 | |
| 9418 format %{ "FLD $src1\n\t" | |
| 9419 "FDIV ST,$src2\n\t" | |
| 9420 "FSTP_D $dst\t# D-round" %} | |
| 9421 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
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9422 ins_encode( Push_Reg_DPR(src1), |
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9423 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9424 ins_pipe( fpu_mem_reg_reg ); |
| 9425 %} | |
| 9426 | |
| 9427 | |
|
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9428 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9429 predicate(UseSSE<=1); |
| 9430 match(Set dst (ModD dst src)); | |
|
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9431 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9432 |
| 9433 format %{ "DMOD $dst,$src" %} | |
| 9434 ins_cost(250); | |
|
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9435 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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9436 emitModDPR(), |
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9437 Push_Result_Mod_DPR(src), |
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9438 Pop_Reg_DPR(dst)); |
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9439 ins_pipe( pipe_slow ); |
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9440 %} |
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9441 |
|
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9442 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9443 predicate(UseSSE>=2); |
| 9444 match(Set dst (ModD src0 src1)); | |
| 9445 effect(KILL rax, KILL cr); | |
| 9446 | |
| 9447 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9448 "\tMOVSD [ESP+0],$src1\n" | |
| 9449 "\tFLD_D [ESP+0]\n" | |
| 9450 "\tMOVSD [ESP+0],$src0\n" | |
| 9451 "\tFLD_D [ESP+0]\n" | |
| 9452 "loop:\tFPREM\n" | |
| 9453 "\tFWAIT\n" | |
| 9454 "\tFNSTSW AX\n" | |
| 9455 "\tSAHF\n" | |
| 9456 "\tJP loop\n" | |
| 9457 "\tFSTP_D [ESP+0]\n" | |
| 9458 "\tMOVSD $dst,[ESP+0]\n" | |
| 9459 "\tADD ESP,8\n" | |
| 9460 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9461 %} | |
| 9462 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
9463 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
9464 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
9465 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
9466 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
9467 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9468 predicate (UseSSE<=1); |
| 9469 match(Set dst (SinD src)); | |
| 9470 ins_cost(1800); | |
| 9471 format %{ "DSIN $dst" %} | |
| 9472 opcode(0xD9, 0xFE); | |
| 9473 ins_encode( OpcP, OpcS ); | |
| 9474 ins_pipe( pipe_slow ); | |
| 9475 %} | |
| 9476 | |
|
4761
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
9477 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9478 predicate (UseSSE>=2); |
| 9479 match(Set dst (SinD dst)); | |
|
4761
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diff
changeset
|
9480 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9481 ins_cost(1800); |
| 9482 format %{ "DSIN $dst" %} | |
| 9483 opcode(0xD9, 0xFE); | |
|
4761
65149e74c706
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4759
diff
changeset
|
9484 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9485 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9486 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9487 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
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diff
changeset
|
9488 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9489 predicate (UseSSE<=1); |
| 9490 match(Set dst (CosD src)); | |
| 9491 ins_cost(1800); | |
| 9492 format %{ "DCOS $dst" %} | |
| 9493 opcode(0xD9, 0xFF); | |
| 9494 ins_encode( OpcP, OpcS ); | |
| 9495 ins_pipe( pipe_slow ); | |
| 9496 %} | |
| 9497 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9498 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9499 predicate (UseSSE>=2); |
| 9500 match(Set dst (CosD dst)); | |
|
4761
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diff
changeset
|
9501 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9502 ins_cost(1800); |
| 9503 format %{ "DCOS $dst" %} | |
| 9504 opcode(0xD9, 0xFF); | |
|
4761
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diff
changeset
|
9505 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
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changeset
|
9506 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9507 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9508 |
|
65149e74c706
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parents:
4759
diff
changeset
|
9509 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9510 predicate (UseSSE<=1); |
| 9511 match(Set dst(TanD src)); | |
| 9512 format %{ "DTAN $dst" %} | |
| 9513 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9514 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9515 ins_pipe( pipe_slow ); | |
| 9516 %} | |
| 9517 | |
|
4761
65149e74c706
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diff
changeset
|
9518 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9519 predicate (UseSSE>=2); |
| 9520 match(Set dst(TanD dst)); | |
|
4761
65149e74c706
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parents:
4759
diff
changeset
|
9521 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9522 format %{ "DTAN $dst" %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
9523 ins_encode( Push_SrcD(dst), |
| 0 | 9524 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9525 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
9526 Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9527 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9528 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9529 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9530 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9531 predicate (UseSSE<=1); |
| 9532 match(Set dst(AtanD dst src)); | |
| 9533 format %{ "DATA $dst,$src" %} | |
| 9534 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9535 ins_encode( Push_Reg_DPR(src), |
| 0 | 9536 OpcP, OpcS, RegOpc(dst) ); |
| 9537 ins_pipe( pipe_slow ); | |
| 9538 %} | |
| 9539 | |
|
4761
65149e74c706
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parents:
4759
diff
changeset
|
9540 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9541 predicate (UseSSE>=2); |
| 9542 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9543 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9544 format %{ "DATA $dst,$src" %} |
| 9545 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9546 ins_encode( Push_SrcD(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9547 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9548 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9549 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9550 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9551 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9552 predicate (UseSSE<=1); |
| 9553 match(Set dst (SqrtD src)); | |
| 9554 format %{ "DSQRT $dst,$src" %} | |
| 9555 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9556 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9557 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9558 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9559 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9560 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9561 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9562 predicate (UseSSE<=1); |
| 9563 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9564 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9565 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9566 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9567 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9568 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9569 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9570 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9571 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9572 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9573 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9574 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9575 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9576 predicate (UseSSE>=2); |
| 9577 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9578 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9579 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9580 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9581 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9582 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9583 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9584 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9585 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9586 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9587 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9588 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9589 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9590 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9591 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9592 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9593 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9594 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9595 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9596 predicate (UseSSE<=1); |
| 9597 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9598 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9599 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9600 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9601 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9602 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9603 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9604 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9605 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9606 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9607 predicate (UseSSE>=2); |
| 9608 match(Set dst (ExpD src)); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9609 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9610 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9611 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9612 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9613 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9614 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9615 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9616 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9617 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9618 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9619 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9620 ins_pipe( pipe_slow ); |
|
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9621 %} |
|
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9622 |
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|
9623 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9624 predicate (UseSSE<=1); |
| 9625 // The source Double operand on FPU stack | |
| 9626 match(Set dst (Log10D src)); | |
| 9627 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9628 // fxch ; swap ST(0) with ST(1) | |
| 9629 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9630 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9631 "FXCH \n\t" | |
| 9632 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9633 %} | |
| 9634 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9635 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9636 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9637 | |
| 9638 ins_pipe( pipe_slow ); | |
| 9639 %} | |
| 9640 | |
|
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|
9641 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9642 predicate (UseSSE>=2); |
| 9643 effect(KILL cr); | |
| 9644 match(Set dst (Log10D src)); | |
| 9645 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9646 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9647 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9648 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9649 %} | |
| 9650 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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|
9651 Push_SrcD(src), |
| 0 | 9652 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9653 Push_ResultD(dst)); |
|
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|
9654 |
|
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|
9655 ins_pipe( pipe_slow ); |
|
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|
9656 %} |
|
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|
9657 |
|
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|
9658 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9659 predicate (UseSSE<=1); |
| 9660 // The source Double operand on FPU stack | |
| 9661 match(Set dst (LogD src)); | |
| 9662 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9663 // fxch ; swap ST(0) with ST(1) | |
| 9664 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9665 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 9666 "FXCH \n\t" | |
| 9667 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 9668 %} | |
| 9669 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9670 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9671 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9672 | |
| 9673 ins_pipe( pipe_slow ); | |
| 9674 %} | |
| 9675 | |
|
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|
9676 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9677 predicate (UseSSE>=2); |
| 9678 effect(KILL cr); | |
| 9679 // The source and result Double operands in XMM registers | |
| 9680 match(Set dst (LogD src)); | |
| 9681 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9682 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9683 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 9684 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 9685 %} | |
| 9686 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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|
9687 Push_SrcD(src), |
| 0 | 9688 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9689 Push_ResultD(dst)); |
| 0 | 9690 ins_pipe( pipe_slow ); |
| 9691 %} | |
| 9692 | |
| 9693 //-------------Float Instructions------------------------------- | |
| 9694 // Float Math | |
| 9695 | |
| 9696 // Code for float compare: | |
| 9697 // fcompp(); | |
| 9698 // fwait(); fnstsw_ax(); | |
| 9699 // sahf(); | |
| 9700 // movl(dst, unordered_result); | |
| 9701 // jcc(Assembler::parity, exit); | |
| 9702 // movl(dst, less_result); | |
| 9703 // jcc(Assembler::below, exit); | |
| 9704 // movl(dst, equal_result); | |
| 9705 // jcc(Assembler::equal, exit); | |
| 9706 // movl(dst, greater_result); | |
| 9707 // exit: | |
| 9708 | |
| 9709 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
9710 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 9711 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 9712 match(Set cr (CmpF src1 src2)); | |
| 9713 effect(KILL rax); | |
| 9714 ins_cost(150); | |
| 9715 format %{ "FLD $src1\n\t" | |
| 9716 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9717 "JNP exit\n\t" | |
| 9718 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 9719 "SAHF\n" | |
| 9720 "exit:\tNOP // avoid branch to branch" %} | |
| 9721 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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|
9722 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9723 OpcP, RegOpc(src2), |
| 9724 cmpF_P6_fixup ); | |
| 9725 ins_pipe( pipe_slow ); | |
| 9726 %} | |
| 9727 | |
|
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9728 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
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|
9729 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
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|
9730 match(Set cr (CmpF src1 src2)); |
|
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9731 ins_cost(100); |
|
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|
9732 format %{ "FLD $src1\n\t" |
|
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|
9733 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
9734 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9735 ins_encode( Push_Reg_DPR(src1), |
|
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|
9736 OpcP, RegOpc(src2)); |
|
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|
9737 ins_pipe( pipe_slow ); |
|
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|
9738 %} |
|
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|
9739 |
| 0 | 9740 |
| 9741 // Compare & branch | |
|
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|
9742 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 9743 predicate(UseSSE == 0); |
| 9744 match(Set cr (CmpF src1 src2)); | |
| 9745 effect(KILL rax); | |
| 9746 ins_cost(200); | |
| 9747 format %{ "FLD $src1\n\t" | |
| 9748 "FCOMp $src2\n\t" | |
| 9749 "FNSTSW AX\n\t" | |
| 9750 "TEST AX,0x400\n\t" | |
| 9751 "JZ,s flags\n\t" | |
| 9752 "MOV AH,1\t# unordered treat as LT\n" | |
| 9753 "flags:\tSAHF" %} | |
| 9754 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
9755 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9756 OpcP, RegOpc(src2), |
| 9757 fpu_flags); | |
| 9758 ins_pipe( pipe_slow ); | |
| 9759 %} | |
| 9760 | |
| 9761 // Compare vs zero into -1,0,1 | |
|
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|
9762 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9763 predicate(UseSSE == 0); |
| 9764 match(Set dst (CmpF3 src1 zero)); | |
| 9765 effect(KILL cr, KILL rax); | |
| 9766 ins_cost(280); | |
| 9767 format %{ "FTSTF $dst,$src1" %} | |
| 9768 opcode(0xE4, 0xD9); | |
|
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|
9769 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9770 OpcS, OpcP, PopFPU, |
| 9771 CmpF_Result(dst)); | |
| 9772 ins_pipe( pipe_slow ); | |
| 9773 %} | |
| 9774 | |
| 9775 // Compare into -1,0,1 | |
|
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|
9776 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9777 predicate(UseSSE == 0); |
| 9778 match(Set dst (CmpF3 src1 src2)); | |
| 9779 effect(KILL cr, KILL rax); | |
| 9780 ins_cost(300); | |
| 9781 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 9782 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
9783 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9784 OpcP, RegOpc(src2), |
| 9785 CmpF_Result(dst)); | |
| 9786 ins_pipe( pipe_slow ); | |
| 9787 %} | |
| 9788 | |
| 9789 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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|
9790 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 9791 predicate(UseSSE>=1); |
| 4759 | 9792 match(Set cr (CmpF src1 src2)); |
| 0 | 9793 ins_cost(145); |
| 4759 | 9794 format %{ "UCOMISS $src1,$src2\n\t" |
| 9795 "JNP,s exit\n\t" | |
| 9796 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9797 "AND [rsp], #0xffffff2b\n\t" | |
| 9798 "POPF\n" | |
| 9799 "exit:" %} | |
| 9800 ins_encode %{ | |
| 9801 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9802 emit_cmpfp_fixup(_masm); | |
| 9803 %} | |
| 9804 ins_pipe( pipe_slow ); | |
| 9805 %} | |
| 9806 | |
|
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|
9807 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
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changeset
|
9808 predicate(UseSSE>=1); |
| 4759 | 9809 match(Set cr (CmpF src1 src2)); |
|
415
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diff
changeset
|
9810 ins_cost(100); |
| 4759 | 9811 format %{ "UCOMISS $src1,$src2" %} |
| 9812 ins_encode %{ | |
| 9813 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9814 %} | |
|
415
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diff
changeset
|
9815 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9816 %} |
|
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diff
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|
9817 |
| 0 | 9818 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
9819 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 9820 predicate(UseSSE>=1); |
| 4759 | 9821 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 9822 ins_cost(165); |
| 4759 | 9823 format %{ "UCOMISS $src1,$src2\n\t" |
| 9824 "JNP,s exit\n\t" | |
| 9825 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9826 "AND [rsp], #0xffffff2b\n\t" | |
| 9827 "POPF\n" | |
| 9828 "exit:" %} | |
| 9829 ins_encode %{ | |
| 9830 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9831 emit_cmpfp_fixup(_masm); | |
| 9832 %} | |
| 9833 ins_pipe( pipe_slow ); | |
| 9834 %} | |
| 9835 | |
|
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|
9836 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
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diff
changeset
|
9837 predicate(UseSSE>=1); |
| 4759 | 9838 match(Set cr (CmpF src1 (LoadF src2))); |
|
415
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diff
changeset
|
9839 ins_cost(100); |
| 4759 | 9840 format %{ "UCOMISS $src1,$src2" %} |
| 9841 ins_encode %{ | |
| 9842 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9843 %} | |
|
415
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changeset
|
9844 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9845 %} |
|
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|
9846 |
| 0 | 9847 // Compare into -1,0,1 in XMM |
|
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|
9848 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 9849 predicate(UseSSE>=1); |
| 9850 match(Set dst (CmpF3 src1 src2)); | |
| 9851 effect(KILL cr); | |
| 9852 ins_cost(255); | |
| 4759 | 9853 format %{ "UCOMISS $src1, $src2\n\t" |
| 9854 "MOV $dst, #-1\n\t" | |
| 9855 "JP,s done\n\t" | |
| 9856 "JB,s done\n\t" | |
| 9857 "SETNE $dst\n\t" | |
| 9858 "MOVZB $dst, $dst\n" | |
| 9859 "done:" %} | |
| 9860 ins_encode %{ | |
| 9861 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9862 emit_cmpfp3(_masm, $dst$$Register); | |
| 9863 %} | |
| 0 | 9864 ins_pipe( pipe_slow ); |
| 9865 %} | |
| 9866 | |
| 9867 // Compare into -1,0,1 in XMM and memory | |
|
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|
9868 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9869 predicate(UseSSE>=1); |
| 4759 | 9870 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 9871 effect(KILL cr); |
| 9872 ins_cost(275); | |
| 4759 | 9873 format %{ "UCOMISS $src1, $src2\n\t" |
| 9874 "MOV $dst, #-1\n\t" | |
| 9875 "JP,s done\n\t" | |
| 9876 "JB,s done\n\t" | |
| 9877 "SETNE $dst\n\t" | |
| 9878 "MOVZB $dst, $dst\n" | |
| 9879 "done:" %} | |
| 9880 ins_encode %{ | |
| 9881 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9882 emit_cmpfp3(_masm, $dst$$Register); | |
| 9883 %} | |
| 0 | 9884 ins_pipe( pipe_slow ); |
| 9885 %} | |
| 9886 | |
| 9887 // Spill to obtain 24-bit precision | |
|
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|
9888 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 9889 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 9890 match(Set dst (SubF src1 src2)); | |
| 9891 | |
| 9892 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 9893 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
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|
9894 ins_encode( Push_Reg_FPR(src1), |
|
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|
9895 OpcReg_FPR(src2), |
|
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|
9896 Pop_Mem_FPR(dst) ); |
| 0 | 9897 ins_pipe( fpu_mem_reg_reg ); |
| 9898 %} | |
| 9899 // | |
| 9900 // This instruction does not round to 24-bits | |
|
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|
9901 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 9902 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 9903 match(Set dst (SubF dst src)); | |
| 9904 | |
| 9905 format %{ "FSUB $dst,$src" %} | |
| 9906 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
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9907 ins_encode( Push_Reg_FPR(src), |
| 0 | 9908 OpcP, RegOpc(dst) ); |
| 9909 ins_pipe( fpu_reg_reg ); | |
| 9910 %} | |
| 9911 | |
| 9912 // Spill to obtain 24-bit precision | |
|
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9913 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 9914 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 9915 match(Set dst (AddF src1 src2)); | |
| 9916 | |
| 9917 format %{ "FADD $dst,$src1,$src2" %} | |
| 9918 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
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9919 ins_encode( Push_Reg_FPR(src2), |
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9920 OpcReg_FPR(src1), |
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9921 Pop_Mem_FPR(dst) ); |
| 0 | 9922 ins_pipe( fpu_mem_reg_reg ); |
| 9923 %} | |
| 9924 // | |
| 9925 // This instruction does not round to 24-bits | |
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9926 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 9927 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 9928 match(Set dst (AddF dst src)); | |
| 9929 | |
| 9930 format %{ "FLD $src\n\t" | |
| 9931 "FADDp $dst,ST" %} | |
| 9932 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
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9933 ins_encode( Push_Reg_FPR(src), |
| 0 | 9934 OpcP, RegOpc(dst) ); |
| 9935 ins_pipe( fpu_reg_reg ); | |
| 9936 %} | |
| 9937 | |
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9938 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 9939 predicate(UseSSE==0); |
| 9940 match(Set dst (AbsF src)); | |
| 9941 ins_cost(100); | |
| 9942 format %{ "FABS" %} | |
| 9943 opcode(0xE1, 0xD9); | |
| 9944 ins_encode( OpcS, OpcP ); | |
| 9945 ins_pipe( fpu_reg_reg ); | |
| 9946 %} | |
| 9947 | |
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9948 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 9949 predicate(UseSSE==0); |
| 9950 match(Set dst (NegF src)); | |
| 9951 ins_cost(100); | |
| 9952 format %{ "FCHS" %} | |
| 9953 opcode(0xE0, 0xD9); | |
| 9954 ins_encode( OpcS, OpcP ); | |
| 9955 ins_pipe( fpu_reg_reg ); | |
| 9956 %} | |
| 9957 | |
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9958 // Cisc-alternate to addFPR_reg |
| 0 | 9959 // Spill to obtain 24-bit precision |
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9960 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 9961 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 9962 match(Set dst (AddF src1 (LoadF src2))); | |
| 9963 | |
| 9964 format %{ "FLD $src2\n\t" | |
| 9965 "FADD ST,$src1\n\t" | |
| 9966 "FSTP_S $dst" %} | |
| 9967 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 9968 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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9969 OpcReg_FPR(src1), |
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9970 Pop_Mem_FPR(dst) ); |
| 0 | 9971 ins_pipe( fpu_mem_reg_mem ); |
| 9972 %} | |
| 9973 // | |
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9974 // Cisc-alternate to addFPR_reg |
| 0 | 9975 // This instruction does not round to 24-bits |
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9976 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 9977 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 9978 match(Set dst (AddF dst (LoadF src))); | |
| 9979 | |
| 9980 format %{ "FADD $dst,$src" %} | |
| 9981 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 9982 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9983 OpcP, RegOpc(dst) ); | |
| 9984 ins_pipe( fpu_reg_mem ); | |
| 9985 %} | |
| 9986 | |
| 9987 // // Following two instructions for _222_mpegaudio | |
| 9988 // Spill to obtain 24-bit precision | |
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9989 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 9990 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 9991 match(Set dst (AddF src1 src2)); | |
| 9992 | |
| 9993 format %{ "FADD $dst,$src1,$src2" %} | |
| 9994 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 9995 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
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9996 OpcReg_FPR(src2), |
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9997 Pop_Mem_FPR(dst) ); |
| 0 | 9998 ins_pipe( fpu_mem_reg_mem ); |
| 9999 %} | |
| 10000 | |
| 10001 // Cisc-spill variant | |
| 10002 // Spill to obtain 24-bit precision | |
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10003 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10004 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10005 match(Set dst (AddF src1 (LoadF src2))); | |
| 10006 | |
| 10007 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10008 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10009 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10010 set_instruction_start, | |
| 10011 OpcP, RMopc_Mem(secondary,src1), | |
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10012 Pop_Mem_FPR(dst) ); |
| 0 | 10013 ins_pipe( fpu_mem_mem_mem ); |
| 10014 %} | |
| 10015 | |
| 10016 // Spill to obtain 24-bit precision | |
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10017 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10018 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10019 match(Set dst (AddF src1 src2)); | |
| 10020 | |
| 10021 format %{ "FADD $dst,$src1,$src2" %} | |
| 10022 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10023 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10024 set_instruction_start, | |
| 10025 OpcP, RMopc_Mem(secondary,src1), | |
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10026 Pop_Mem_FPR(dst) ); |
| 0 | 10027 ins_pipe( fpu_mem_mem_mem ); |
| 10028 %} | |
| 10029 | |
| 10030 | |
| 10031 // Spill to obtain 24-bit precision | |
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10032 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10033 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10034 match(Set dst (AddF src con)); |
| 10035 format %{ "FLD $src\n\t" | |
| 10036 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10037 "FSTP_S $dst" %} |
| 2008 | 10038 ins_encode %{ |
| 10039 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10040 __ fadd_s($constantaddress($con)); | |
| 10041 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10042 %} | |
| 10043 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10044 %} |
| 10045 // | |
| 10046 // This instruction does not round to 24-bits | |
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10047 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10048 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10049 match(Set dst (AddF src con)); |
| 10050 format %{ "FLD $src\n\t" | |
| 10051 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10052 "FSTP $dst" %} | |
| 10053 ins_encode %{ | |
| 10054 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10055 __ fadd_s($constantaddress($con)); | |
| 10056 __ fstp_d($dst$$reg); | |
| 10057 %} | |
| 10058 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10059 %} |
| 10060 | |
| 10061 // Spill to obtain 24-bit precision | |
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10062 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10063 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10064 match(Set dst (MulF src1 src2)); | |
| 10065 | |
| 10066 format %{ "FLD $src1\n\t" | |
| 10067 "FMUL $src2\n\t" | |
| 10068 "FSTP_S $dst" %} | |
| 10069 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
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10070 ins_encode( Push_Reg_FPR(src1), |
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10071 OpcReg_FPR(src2), |
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10072 Pop_Mem_FPR(dst) ); |
| 0 | 10073 ins_pipe( fpu_mem_reg_reg ); |
| 10074 %} | |
| 10075 // | |
| 10076 // This instruction does not round to 24-bits | |
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10077 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10078 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10079 match(Set dst (MulF src1 src2)); | |
| 10080 | |
| 10081 format %{ "FLD $src1\n\t" | |
| 10082 "FMUL $src2\n\t" | |
| 10083 "FSTP_S $dst" %} | |
| 10084 opcode(0xD8, 0x1); /* D8 C8+i */ | |
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10085 ins_encode( Push_Reg_FPR(src2), |
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10086 OpcReg_FPR(src1), |
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10087 Pop_Reg_FPR(dst) ); |
| 0 | 10088 ins_pipe( fpu_reg_reg_reg ); |
| 10089 %} | |
| 10090 | |
| 10091 | |
| 10092 // Spill to obtain 24-bit precision | |
| 10093 // Cisc-alternate to reg-reg multiply | |
|
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10094 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10095 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10096 match(Set dst (MulF src1 (LoadF src2))); | |
| 10097 | |
| 10098 format %{ "FLD_S $src2\n\t" | |
| 10099 "FMUL $src1\n\t" | |
| 10100 "FSTP_S $dst" %} | |
| 10101 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10102 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10103 OpcReg_FPR(src1), |
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10104 Pop_Mem_FPR(dst) ); |
| 0 | 10105 ins_pipe( fpu_mem_reg_mem ); |
| 10106 %} | |
| 10107 // | |
| 10108 // This instruction does not round to 24-bits | |
| 10109 // Cisc-alternate to reg-reg multiply | |
|
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10110 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10111 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10112 match(Set dst (MulF src1 (LoadF src2))); | |
| 10113 | |
| 10114 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10115 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10116 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10117 OpcReg_FPR(src1), |
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10118 Pop_Reg_FPR(dst) ); |
| 0 | 10119 ins_pipe( fpu_reg_reg_mem ); |
| 10120 %} | |
| 10121 | |
| 10122 // Spill to obtain 24-bit precision | |
|
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10123 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10124 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10125 match(Set dst (MulF src1 src2)); | |
| 10126 | |
| 10127 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10128 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10129 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10130 set_instruction_start, | |
| 10131 OpcP, RMopc_Mem(secondary,src1), | |
|
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10132 Pop_Mem_FPR(dst) ); |
| 0 | 10133 ins_pipe( fpu_mem_mem_mem ); |
| 10134 %} | |
| 10135 | |
| 10136 // Spill to obtain 24-bit precision | |
|
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10137 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10138 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10139 match(Set dst (MulF src con)); |
| 10140 | |
| 10141 format %{ "FLD $src\n\t" | |
| 10142 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10143 "FSTP_S $dst" %} | |
| 10144 ins_encode %{ | |
| 10145 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10146 __ fmul_s($constantaddress($con)); | |
| 10147 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10148 %} | |
| 10149 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10150 %} |
| 10151 // | |
| 10152 // This instruction does not round to 24-bits | |
|
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10153 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10154 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10155 match(Set dst (MulF src con)); |
| 10156 | |
| 10157 format %{ "FLD $src\n\t" | |
| 10158 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10159 "FSTP $dst" %} | |
| 10160 ins_encode %{ | |
| 10161 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10162 __ fmul_s($constantaddress($con)); | |
| 10163 __ fstp_d($dst$$reg); | |
| 10164 %} | |
| 10165 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10166 %} |
| 10167 | |
| 10168 | |
| 10169 // | |
|
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10170 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10171 // This instruction does not round to 24-bits |
|
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10172 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10173 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10174 match(Set dst (MulF (LoadF mem1) src)); | |
| 10175 | |
| 10176 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10177 "FMUL ST,$src\n\t" | |
| 10178 "FSTP $dst" %} | |
| 10179 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10180 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10181 OpcReg_FPR(src), |
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10182 Pop_Reg_FPR(dst) ); |
| 0 | 10183 ins_pipe( fpu_reg_reg_mem ); |
| 10184 %} | |
| 10185 // | |
|
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10186 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10187 // This instruction does not round to 24-bits |
|
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10188 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10189 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10190 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10191 ins_cost(95); | |
| 10192 | |
| 10193 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10194 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10195 "FADD ST,$src2\n\t" |
| 10196 "FSTP $dst" %} | |
| 10197 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10198 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10199 FMul_ST_reg(src1), | |
| 10200 FAdd_ST_reg(src2), | |
|
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10201 Pop_Reg_FPR(dst) ); |
| 0 | 10202 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10203 %} | |
| 10204 | |
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10205 // MACRO3 -- addFPR a mulFPR |
| 0 | 10206 // This instruction does not round to 24-bits. It is a '2-address' |
| 10207 // instruction in that the result goes back to src2. This eliminates | |
| 10208 // a move from the macro; possibly the register allocator will have | |
| 10209 // to add it back (and maybe not). | |
|
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10210 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10211 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10212 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10213 | |
| 10214 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10215 "FMUL ST,$src1\n\t" | |
| 10216 "FADDP $src2,ST" %} | |
| 10217 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10218 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10219 FMul_ST_reg(src1), |
| 10220 FAddP_reg_ST(src2) ); | |
| 10221 ins_pipe( fpu_reg_reg_reg ); | |
| 10222 %} | |
| 10223 | |
|
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10224 // MACRO4 -- divFPR subFPR |
| 0 | 10225 // This instruction does not round to 24-bits |
|
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10226 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10227 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10228 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10229 | |
| 10230 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10231 "FSUB ST,$src1\n\t" | |
| 10232 "FDIV ST,$src3\n\t" | |
| 10233 "FSTP $dst" %} | |
| 10234 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10235 ins_encode( Push_Reg_FPR(src2), |
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10236 subFPR_divFPR_encode(src1,src3), |
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10237 Pop_Reg_FPR(dst) ); |
| 0 | 10238 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10239 %} | |
| 10240 | |
| 10241 // Spill to obtain 24-bit precision | |
|
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10242 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10243 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10244 match(Set dst (DivF src1 src2)); | |
| 10245 | |
| 10246 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10247 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10248 ins_encode( Push_Reg_FPR(src1), |
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10249 OpcReg_FPR(src2), |
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10250 Pop_Mem_FPR(dst) ); |
| 0 | 10251 ins_pipe( fpu_mem_reg_reg ); |
| 10252 %} | |
| 10253 // | |
| 10254 // This instruction does not round to 24-bits | |
|
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10255 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10256 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10257 match(Set dst (DivF dst src)); | |
| 10258 | |
| 10259 format %{ "FDIV $dst,$src" %} | |
| 10260 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10261 ins_encode( Push_Reg_FPR(src), |
| 0 | 10262 OpcP, RegOpc(dst) ); |
| 10263 ins_pipe( fpu_reg_reg ); | |
| 10264 %} | |
| 10265 | |
| 10266 | |
| 10267 // Spill to obtain 24-bit precision | |
|
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10268 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10269 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10270 match(Set dst (ModF src1 src2)); | |
|
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10271 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10272 |
| 10273 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10274 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10275 emitModDPR(), |
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10276 Push_Result_Mod_DPR(src2), |
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10277 Pop_Mem_FPR(dst)); |
| 0 | 10278 ins_pipe( pipe_slow ); |
| 10279 %} | |
| 10280 // | |
| 10281 // This instruction does not round to 24-bits | |
|
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10282 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10283 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10284 match(Set dst (ModF dst src)); | |
|
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10285 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10286 |
| 10287 format %{ "FMOD $dst,$src" %} | |
|
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10288 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10289 emitModDPR(), |
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10290 Push_Result_Mod_DPR(src), |
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10291 Pop_Reg_FPR(dst)); |
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10292 ins_pipe( pipe_slow ); |
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10293 %} |
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10294 |
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10295 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10296 predicate(UseSSE>=1); |
| 10297 match(Set dst (ModF src0 src1)); | |
| 10298 effect(KILL rax, KILL cr); | |
| 10299 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10300 "\tMOVSS [ESP+0],$src1\n" | |
| 10301 "\tFLD_S [ESP+0]\n" | |
| 10302 "\tMOVSS [ESP+0],$src0\n" | |
| 10303 "\tFLD_S [ESP+0]\n" | |
| 10304 "loop:\tFPREM\n" | |
| 10305 "\tFWAIT\n" | |
| 10306 "\tFNSTSW AX\n" | |
| 10307 "\tSAHF\n" | |
| 10308 "\tJP loop\n" | |
| 10309 "\tFSTP_S [ESP+0]\n" | |
| 10310 "\tMOVSS $dst,[ESP+0]\n" | |
| 10311 "\tADD ESP,4\n" | |
| 10312 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10313 %} | |
| 10314 ins_cost(250); | |
|
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10315 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10316 ins_pipe( pipe_slow ); |
| 10317 %} | |
| 10318 | |
| 10319 | |
| 10320 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10321 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10322 | |
|
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10323 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10324 predicate(UseSSE==0); |
| 10325 match(Set dst (RoundFloat src)); | |
| 10326 ins_cost(125); | |
| 10327 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10328 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10329 ins_pipe( fpu_mem_reg ); |
| 10330 %} | |
| 10331 | |
|
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10332 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10333 predicate(UseSSE<=1); |
| 10334 match(Set dst (RoundDouble src)); | |
| 10335 ins_cost(125); | |
| 10336 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10337 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10338 ins_pipe( fpu_mem_reg ); |
| 10339 %} | |
| 10340 | |
| 10341 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10342 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10343 predicate(UseSSE==0); |
| 10344 match(Set dst (ConvD2F src)); | |
| 10345 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10346 expand %{ | |
| 10347 roundFloat_mem_reg(dst,src); | |
| 10348 %} | |
| 10349 %} | |
| 10350 | |
| 10351 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10352 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10353 predicate(UseSSE==1); |
| 10354 match(Set dst (ConvD2F src)); | |
| 10355 effect( KILL cr ); | |
| 10356 format %{ "SUB ESP,4\n\t" | |
| 10357 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10358 "MOVSS $dst,[ESP]\n\t" | |
| 10359 "ADD ESP,4" %} | |
| 4759 | 10360 ins_encode %{ |
| 10361 __ subptr(rsp, 4); | |
| 10362 if ($src$$reg != FPR1L_enc) { | |
| 10363 __ fld_s($src$$reg-1); | |
| 10364 __ fstp_s(Address(rsp, 0)); | |
| 10365 } else { | |
| 10366 __ fst_s(Address(rsp, 0)); | |
| 10367 } | |
| 10368 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10369 __ addptr(rsp, 4); | |
| 10370 %} | |
| 0 | 10371 ins_pipe( pipe_slow ); |
| 10372 %} | |
| 10373 | |
| 10374 // Force rounding double precision to single precision | |
|
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10375 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10376 predicate(UseSSE>=2); |
| 10377 match(Set dst (ConvD2F src)); | |
| 10378 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10379 ins_encode %{ |
| 10380 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10381 %} | |
| 0 | 10382 ins_pipe( pipe_slow ); |
| 10383 %} | |
| 10384 | |
|
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10385 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10386 predicate(UseSSE==0); |
| 10387 match(Set dst (ConvF2D src)); | |
| 10388 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10389 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10390 ins_pipe( fpu_reg_reg ); |
| 10391 %} | |
| 10392 | |
|
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10393 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10394 predicate(UseSSE==1); |
| 10395 match(Set dst (ConvF2D src)); | |
| 10396 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10397 expand %{ | |
| 10398 roundDouble_mem_reg(dst,src); | |
| 10399 %} | |
| 10400 %} | |
| 10401 | |
|
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10402 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10403 predicate(UseSSE==1); |
| 10404 match(Set dst (ConvF2D src)); | |
| 10405 effect( KILL cr ); | |
| 10406 format %{ "SUB ESP,4\n\t" | |
| 10407 "MOVSS [ESP] $src\n\t" | |
| 10408 "FLD_S [ESP]\n\t" | |
| 10409 "ADD ESP,4\n\t" | |
| 10410 "FSTP $dst\t# D-round" %} | |
| 4759 | 10411 ins_encode %{ |
| 10412 __ subptr(rsp, 4); | |
| 10413 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10414 __ fld_s(Address(rsp, 0)); | |
| 10415 __ addptr(rsp, 4); | |
| 10416 __ fstp_d($dst$$reg); | |
| 10417 %} | |
| 0 | 10418 ins_pipe( pipe_slow ); |
| 10419 %} | |
| 10420 | |
|
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10421 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10422 predicate(UseSSE>=2); |
| 10423 match(Set dst (ConvF2D src)); | |
| 10424 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10425 ins_encode %{ |
| 10426 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10427 %} | |
| 0 | 10428 ins_pipe( pipe_slow ); |
| 10429 %} | |
| 10430 | |
| 10431 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10432 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10433 predicate(UseSSE<=1); |
| 10434 match(Set dst (ConvD2I src)); | |
| 10435 effect( KILL tmp, KILL cr ); | |
| 10436 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10437 "FLDCW trunc mode\n\t" | |
| 10438 "SUB ESP,4\n\t" | |
| 10439 "FISTp [ESP + #0]\n\t" | |
| 10440 "FLDCW std/24-bit mode\n\t" | |
| 10441 "POP EAX\n\t" | |
| 10442 "CMP EAX,0x80000000\n\t" | |
| 10443 "JNE,s fast\n\t" | |
| 10444 "FLD_D $src\n\t" | |
| 10445 "CALL d2i_wrapper\n" | |
| 10446 "fast:" %} | |
|
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10447 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10448 ins_pipe( pipe_slow ); |
| 10449 %} | |
| 10450 | |
| 10451 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10452 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10453 predicate(UseSSE>=2); |
| 10454 match(Set dst (ConvD2I src)); | |
| 10455 effect( KILL tmp, KILL cr ); | |
| 10456 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10457 "CMP $dst,0x80000000\n\t" | |
| 10458 "JNE,s fast\n\t" | |
| 10459 "SUB ESP, 8\n\t" | |
| 10460 "MOVSD [ESP], $src\n\t" | |
| 10461 "FLD_D [ESP]\n\t" | |
| 10462 "ADD ESP, 8\n\t" | |
| 10463 "CALL d2i_wrapper\n" | |
| 10464 "fast:" %} | |
| 4759 | 10465 ins_encode %{ |
| 10466 Label fast; | |
| 10467 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10468 __ cmpl($dst$$Register, 0x80000000); | |
| 10469 __ jccb(Assembler::notEqual, fast); | |
| 10470 __ subptr(rsp, 8); | |
| 10471 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10472 __ fld_d(Address(rsp, 0)); | |
| 10473 __ addptr(rsp, 8); | |
| 10474 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10475 __ bind(fast); | |
| 10476 %} | |
| 0 | 10477 ins_pipe( pipe_slow ); |
| 10478 %} | |
| 10479 | |
|
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10480 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10481 predicate(UseSSE<=1); |
| 10482 match(Set dst (ConvD2L src)); | |
| 10483 effect( KILL cr ); | |
| 10484 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10485 "FLDCW trunc mode\n\t" | |
| 10486 "SUB ESP,8\n\t" | |
| 10487 "FISTp [ESP + #0]\n\t" | |
| 10488 "FLDCW std/24-bit mode\n\t" | |
| 10489 "POP EAX\n\t" | |
| 10490 "POP EDX\n\t" | |
| 10491 "CMP EDX,0x80000000\n\t" | |
| 10492 "JNE,s fast\n\t" | |
| 10493 "TEST EAX,EAX\n\t" | |
| 10494 "JNE,s fast\n\t" | |
| 10495 "FLD $src\n\t" | |
| 10496 "CALL d2l_wrapper\n" | |
| 10497 "fast:" %} | |
|
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10498 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10499 ins_pipe( pipe_slow ); |
| 10500 %} | |
| 10501 | |
| 10502 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
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10503 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10504 predicate (UseSSE>=2); |
| 10505 match(Set dst (ConvD2L src)); | |
| 10506 effect( KILL cr ); | |
| 10507 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10508 "MOVSD [ESP],$src\n\t" | |
| 10509 "FLD_D [ESP]\n\t" | |
| 10510 "FLDCW trunc mode\n\t" | |
| 10511 "FISTp [ESP + #0]\n\t" | |
| 10512 "FLDCW std/24-bit mode\n\t" | |
| 10513 "POP EAX\n\t" | |
| 10514 "POP EDX\n\t" | |
| 10515 "CMP EDX,0x80000000\n\t" | |
| 10516 "JNE,s fast\n\t" | |
| 10517 "TEST EAX,EAX\n\t" | |
| 10518 "JNE,s fast\n\t" | |
| 10519 "SUB ESP,8\n\t" | |
| 10520 "MOVSD [ESP],$src\n\t" | |
| 10521 "FLD_D [ESP]\n\t" | |
| 4759 | 10522 "ADD ESP,8\n\t" |
| 0 | 10523 "CALL d2l_wrapper\n" |
| 10524 "fast:" %} | |
| 4759 | 10525 ins_encode %{ |
| 10526 Label fast; | |
| 10527 __ subptr(rsp, 8); | |
| 10528 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10529 __ fld_d(Address(rsp, 0)); | |
| 10530 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10531 __ fistp_d(Address(rsp, 0)); | |
| 10532 // Restore the rounding mode, mask the exception | |
| 10533 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10534 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10535 } else { | |
| 10536 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10537 } | |
| 10538 // Load the converted long, adjust CPU stack | |
| 10539 __ pop(rax); | |
| 10540 __ pop(rdx); | |
| 10541 __ cmpl(rdx, 0x80000000); | |
| 10542 __ jccb(Assembler::notEqual, fast); | |
| 10543 __ testl(rax, rax); | |
| 10544 __ jccb(Assembler::notEqual, fast); | |
| 10545 __ subptr(rsp, 8); | |
| 10546 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10547 __ fld_d(Address(rsp, 0)); | |
| 10548 __ addptr(rsp, 8); | |
| 10549 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10550 __ bind(fast); | |
| 10551 %} | |
| 0 | 10552 ins_pipe( pipe_slow ); |
| 10553 %} | |
| 10554 | |
| 10555 // Convert a double to an int. Java semantics require we do complex | |
| 10556 // manglations in the corner cases. So we set the rounding mode to | |
| 10557 // 'zero', store the darned double down as an int, and reset the | |
| 10558 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10559 // if we would overflow or converted a NAN; we check for this and | |
| 10560 // and go the slow path if needed. | |
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10561 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10562 predicate(UseSSE==0); |
| 10563 match(Set dst (ConvF2I src)); | |
| 10564 effect( KILL tmp, KILL cr ); | |
| 10565 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10566 "FLDCW trunc mode\n\t" | |
| 10567 "SUB ESP,4\n\t" | |
| 10568 "FISTp [ESP + #0]\n\t" | |
| 10569 "FLDCW std/24-bit mode\n\t" | |
| 10570 "POP EAX\n\t" | |
| 10571 "CMP EAX,0x80000000\n\t" | |
| 10572 "JNE,s fast\n\t" | |
| 10573 "FLD $src\n\t" | |
| 10574 "CALL d2i_wrapper\n" | |
| 10575 "fast:" %} | |
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10576 // DPR2I_encoding works for FPR2I |
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10577 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10578 ins_pipe( pipe_slow ); |
| 10579 %} | |
| 10580 | |
| 10581 // Convert a float in xmm to an int reg. | |
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10582 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10583 predicate(UseSSE>=1); |
| 10584 match(Set dst (ConvF2I src)); | |
| 10585 effect( KILL tmp, KILL cr ); | |
| 10586 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10587 "CMP $dst,0x80000000\n\t" | |
| 10588 "JNE,s fast\n\t" | |
| 10589 "SUB ESP, 4\n\t" | |
| 10590 "MOVSS [ESP], $src\n\t" | |
| 10591 "FLD [ESP]\n\t" | |
| 10592 "ADD ESP, 4\n\t" | |
| 10593 "CALL d2i_wrapper\n" | |
| 10594 "fast:" %} | |
| 4759 | 10595 ins_encode %{ |
| 10596 Label fast; | |
| 10597 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10598 __ cmpl($dst$$Register, 0x80000000); | |
| 10599 __ jccb(Assembler::notEqual, fast); | |
| 10600 __ subptr(rsp, 4); | |
| 10601 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10602 __ fld_s(Address(rsp, 0)); | |
| 10603 __ addptr(rsp, 4); | |
| 10604 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10605 __ bind(fast); | |
| 10606 %} | |
| 0 | 10607 ins_pipe( pipe_slow ); |
| 10608 %} | |
| 10609 | |
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10610 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10611 predicate(UseSSE==0); |
| 10612 match(Set dst (ConvF2L src)); | |
| 10613 effect( KILL cr ); | |
| 10614 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10615 "FLDCW trunc mode\n\t" | |
| 10616 "SUB ESP,8\n\t" | |
| 10617 "FISTp [ESP + #0]\n\t" | |
| 10618 "FLDCW std/24-bit mode\n\t" | |
| 10619 "POP EAX\n\t" | |
| 10620 "POP EDX\n\t" | |
| 10621 "CMP EDX,0x80000000\n\t" | |
| 10622 "JNE,s fast\n\t" | |
| 10623 "TEST EAX,EAX\n\t" | |
| 10624 "JNE,s fast\n\t" | |
| 10625 "FLD $src\n\t" | |
| 10626 "CALL d2l_wrapper\n" | |
| 10627 "fast:" %} | |
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10628 // DPR2L_encoding works for FPR2L |
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10629 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 10630 ins_pipe( pipe_slow ); |
| 10631 %} | |
| 10632 | |
| 10633 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10634 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 10635 predicate (UseSSE>=1); |
| 10636 match(Set dst (ConvF2L src)); | |
| 10637 effect( KILL cr ); | |
| 10638 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 10639 "MOVSS [ESP],$src\n\t" | |
| 10640 "FLD_S [ESP]\n\t" | |
| 10641 "FLDCW trunc mode\n\t" | |
| 10642 "FISTp [ESP + #0]\n\t" | |
| 10643 "FLDCW std/24-bit mode\n\t" | |
| 10644 "POP EAX\n\t" | |
| 10645 "POP EDX\n\t" | |
| 10646 "CMP EDX,0x80000000\n\t" | |
| 10647 "JNE,s fast\n\t" | |
| 10648 "TEST EAX,EAX\n\t" | |
| 10649 "JNE,s fast\n\t" | |
| 10650 "SUB ESP,4\t# Convert float to long\n\t" | |
| 10651 "MOVSS [ESP],$src\n\t" | |
| 10652 "FLD_S [ESP]\n\t" | |
| 10653 "ADD ESP,4\n\t" | |
| 10654 "CALL d2l_wrapper\n" | |
| 10655 "fast:" %} | |
| 4759 | 10656 ins_encode %{ |
| 10657 Label fast; | |
| 10658 __ subptr(rsp, 8); | |
| 10659 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10660 __ fld_s(Address(rsp, 0)); | |
| 10661 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10662 __ fistp_d(Address(rsp, 0)); | |
| 10663 // Restore the rounding mode, mask the exception | |
| 10664 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10665 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10666 } else { | |
| 10667 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10668 } | |
| 10669 // Load the converted long, adjust CPU stack | |
| 10670 __ pop(rax); | |
| 10671 __ pop(rdx); | |
| 10672 __ cmpl(rdx, 0x80000000); | |
| 10673 __ jccb(Assembler::notEqual, fast); | |
| 10674 __ testl(rax, rax); | |
| 10675 __ jccb(Assembler::notEqual, fast); | |
| 10676 __ subptr(rsp, 4); | |
| 10677 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10678 __ fld_s(Address(rsp, 0)); | |
| 10679 __ addptr(rsp, 4); | |
| 10680 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10681 __ bind(fast); | |
| 10682 %} | |
| 0 | 10683 ins_pipe( pipe_slow ); |
| 10684 %} | |
| 10685 | |
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10686 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 10687 predicate( UseSSE<=1 ); |
| 10688 match(Set dst (ConvI2D src)); | |
| 10689 format %{ "FILD $src\n\t" | |
| 10690 "FSTP $dst" %} | |
| 10691 opcode(0xDB, 0x0); /* DB /0 */ | |
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10692 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 10693 ins_pipe( fpu_reg_mem ); |
| 10694 %} | |
| 10695 | |
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10696 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 10697 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 10698 match(Set dst (ConvI2D src)); |
| 10699 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 10700 ins_encode %{ |
| 10701 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10702 %} | |
| 0 | 10703 ins_pipe( pipe_slow ); |
| 10704 %} | |
| 10705 | |
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10706 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 10707 predicate( UseSSE>=2 ); |
| 10708 match(Set dst (ConvI2D (LoadI mem))); | |
| 10709 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 10710 ins_encode %{ |
| 10711 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 10712 %} | |
| 0 | 10713 ins_pipe( pipe_slow ); |
| 10714 %} | |
| 10715 | |
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10716 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 10717 %{ |
| 10718 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 10719 match(Set dst (ConvI2D src)); | |
| 10720 | |
| 10721 format %{ "MOVD $dst,$src\n\t" | |
| 10722 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 10723 ins_encode %{ | |
| 304 | 10724 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 10725 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 10726 %} | |
| 10727 ins_pipe(pipe_slow); // XXX | |
| 10728 %} | |
| 10729 | |
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10730 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 10731 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 10732 match(Set dst (ConvI2D (LoadI mem))); | |
| 10733 format %{ "FILD $mem\n\t" | |
| 10734 "FSTP $dst" %} | |
| 10735 opcode(0xDB); /* DB /0 */ | |
| 10736 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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10737 Pop_Reg_DPR(dst)); |
| 0 | 10738 ins_pipe( fpu_reg_mem ); |
| 10739 %} | |
| 10740 | |
| 10741 // Convert a byte to a float; no rounding step needed. | |
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10742 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 10743 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 10744 match(Set dst (ConvI2F src)); | |
| 10745 format %{ "FILD $src\n\t" | |
| 10746 "FSTP $dst" %} | |
| 10747 | |
| 10748 opcode(0xDB, 0x0); /* DB /0 */ | |
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10749 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 10750 ins_pipe( fpu_reg_mem ); |
| 10751 %} | |
| 10752 | |
| 10753 // In 24-bit mode, force exponent rounding by storing back out | |
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10754 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 10755 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10756 match(Set dst (ConvI2F src)); | |
| 10757 ins_cost(200); | |
| 10758 format %{ "FILD $src\n\t" | |
| 10759 "FSTP_S $dst" %} | |
| 10760 opcode(0xDB, 0x0); /* DB /0 */ | |
| 10761 ins_encode( Push_Mem_I(src), | |
|
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10762 Pop_Mem_FPR(dst)); |
| 0 | 10763 ins_pipe( fpu_mem_mem ); |
| 10764 %} | |
| 10765 | |
| 10766 // In 24-bit mode, force exponent rounding by storing back out | |
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10767 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 10768 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10769 match(Set dst (ConvI2F (LoadI mem))); | |
| 10770 ins_cost(200); | |
| 10771 format %{ "FILD $mem\n\t" | |
| 10772 "FSTP_S $dst" %} | |
| 10773 opcode(0xDB); /* DB /0 */ | |
| 10774 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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10775 Pop_Mem_FPR(dst)); |
| 0 | 10776 ins_pipe( fpu_mem_mem ); |
| 10777 %} | |
| 10778 | |
| 10779 // This instruction does not round to 24-bits | |
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10780 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 10781 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10782 match(Set dst (ConvI2F src)); | |
| 10783 format %{ "FILD $src\n\t" | |
| 10784 "FSTP $dst" %} | |
| 10785 opcode(0xDB, 0x0); /* DB /0 */ | |
| 10786 ins_encode( Push_Mem_I(src), | |
|
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10787 Pop_Reg_FPR(dst)); |
| 0 | 10788 ins_pipe( fpu_reg_mem ); |
| 10789 %} | |
| 10790 | |
| 10791 // This instruction does not round to 24-bits | |
|
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10792 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 10793 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10794 match(Set dst (ConvI2F (LoadI mem))); | |
| 10795 format %{ "FILD $mem\n\t" | |
| 10796 "FSTP $dst" %} | |
| 10797 opcode(0xDB); /* DB /0 */ | |
| 10798 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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10799 Pop_Reg_FPR(dst)); |
| 0 | 10800 ins_pipe( fpu_reg_mem ); |
| 10801 %} | |
| 10802 | |
| 10803 // Convert an int to a float in xmm; no rounding step needed. | |
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10804 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 10805 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 10806 match(Set dst (ConvI2F src)); |
| 10807 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 10808 ins_encode %{ |
| 10809 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10810 %} | |
| 0 | 10811 ins_pipe( pipe_slow ); |
| 10812 %} | |
| 10813 | |
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10814 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 10815 %{ |
| 10816 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 10817 match(Set dst (ConvI2F src)); | |
| 10818 | |
| 10819 format %{ "MOVD $dst,$src\n\t" | |
| 10820 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 10821 ins_encode %{ | |
| 304 | 10822 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 10823 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 10824 %} | |
| 10825 ins_pipe(pipe_slow); // XXX | |
| 10826 %} | |
| 10827 | |
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10828 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 10829 match(Set dst (ConvI2L src)); |
| 10830 effect(KILL cr); | |
| 624 | 10831 ins_cost(375); |
| 0 | 10832 format %{ "MOV $dst.lo,$src\n\t" |
| 10833 "MOV $dst.hi,$src\n\t" | |
| 10834 "SAR $dst.hi,31" %} | |
| 10835 ins_encode(convert_int_long(dst,src)); | |
| 10836 ins_pipe( ialu_reg_reg_long ); | |
| 10837 %} | |
| 10838 | |
| 10839 // Zero-extend convert int to long | |
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10840 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 10841 match(Set dst (AndL (ConvI2L src) mask) ); |
| 10842 effect( KILL flags ); | |
| 624 | 10843 ins_cost(250); |
| 0 | 10844 format %{ "MOV $dst.lo,$src\n\t" |
| 10845 "XOR $dst.hi,$dst.hi" %} | |
| 10846 opcode(0x33); // XOR | |
| 10847 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 10848 ins_pipe( ialu_reg_reg_long ); | |
| 10849 %} | |
| 10850 | |
| 10851 // Zero-extend long | |
| 10852 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 10853 match(Set dst (AndL src mask) ); | |
| 10854 effect( KILL flags ); | |
| 624 | 10855 ins_cost(250); |
| 0 | 10856 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 10857 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 10858 opcode(0x33); // XOR | |
| 10859 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 10860 ins_pipe( ialu_reg_reg_long ); | |
| 10861 %} | |
| 10862 | |
|
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10863 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 10864 predicate (UseSSE<=1); |
| 10865 match(Set dst (ConvL2D src)); | |
| 10866 effect( KILL cr ); | |
| 10867 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 10868 "PUSH $src.lo\n\t" | |
| 10869 "FILD ST,[ESP + #0]\n\t" | |
| 10870 "ADD ESP,8\n\t" | |
| 10871 "FSTP_D $dst\t# D-round" %} | |
| 10872 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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10873 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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10874 ins_pipe( pipe_slow ); |
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10875 %} |
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10876 |
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10877 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 10878 predicate (UseSSE>=2); |
| 10879 match(Set dst (ConvL2D src)); | |
| 10880 effect( KILL cr ); | |
| 10881 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 10882 "PUSH $src.lo\n\t" | |
| 10883 "FILD_D [ESP]\n\t" | |
| 10884 "FSTP_D [ESP]\n\t" | |
| 10885 "MOVSD $dst,[ESP]\n\t" | |
| 10886 "ADD ESP,8" %} | |
| 10887 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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10888 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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10889 ins_pipe( pipe_slow ); |
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10890 %} |
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10891 |
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10892 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 10893 predicate (UseSSE>=1); |
| 10894 match(Set dst (ConvL2F src)); | |
| 10895 effect( KILL cr ); | |
| 10896 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 10897 "PUSH $src.lo\n\t" | |
| 10898 "FILD_D [ESP]\n\t" | |
| 10899 "FSTP_S [ESP]\n\t" | |
| 10900 "MOVSS $dst,[ESP]\n\t" | |
| 10901 "ADD ESP,8" %} | |
| 10902 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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10903 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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10904 ins_pipe( pipe_slow ); |
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10905 %} |
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10906 |
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10907 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 10908 match(Set dst (ConvL2F src)); |
| 10909 effect( KILL cr ); | |
| 10910 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 10911 "PUSH $src.lo\n\t" | |
| 10912 "FILD ST,[ESP + #0]\n\t" | |
| 10913 "ADD ESP,8\n\t" | |
| 10914 "FSTP_S $dst\t# F-round" %} | |
| 10915 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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10916 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 10917 ins_pipe( pipe_slow ); |
| 10918 %} | |
| 10919 | |
|
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10920 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 10921 match(Set dst (ConvL2I src)); |
| 10922 effect( DEF dst, USE src ); | |
| 10923 format %{ "MOV $dst,$src.lo" %} | |
| 10924 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 10925 ins_pipe( ialu_reg_reg ); | |
| 10926 %} | |
| 10927 | |
| 10928 | |
|
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10929 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 10930 match(Set dst (MoveF2I src)); |
| 10931 effect( DEF dst, USE src ); | |
| 10932 ins_cost(100); | |
| 10933 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10934 ins_encode %{ |
| 10935 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10936 %} | |
| 0 | 10937 ins_pipe( ialu_reg_mem ); |
| 10938 %} | |
| 10939 | |
|
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10940 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 10941 predicate(UseSSE==0); |
| 10942 match(Set dst (MoveF2I src)); | |
| 10943 effect( DEF dst, USE src ); | |
| 10944 | |
| 10945 ins_cost(125); | |
| 10946 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
|
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10947 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10948 ins_pipe( fpu_mem_reg ); |
| 10949 %} | |
| 10950 | |
|
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10951 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 10952 predicate(UseSSE>=1); |
| 10953 match(Set dst (MoveF2I src)); | |
| 10954 effect( DEF dst, USE src ); | |
| 10955 | |
| 10956 ins_cost(95); | |
| 10957 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 10958 ins_encode %{ |
| 10959 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10960 %} | |
| 0 | 10961 ins_pipe( pipe_slow ); |
| 10962 %} | |
| 10963 | |
|
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10964 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 10965 predicate(UseSSE>=2); |
| 10966 match(Set dst (MoveF2I src)); | |
| 10967 effect( DEF dst, USE src ); | |
| 10968 ins_cost(85); | |
| 10969 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 10970 ins_encode %{ |
| 10971 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10972 %} | |
| 0 | 10973 ins_pipe( pipe_slow ); |
| 10974 %} | |
| 10975 | |
|
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10976 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 10977 match(Set dst (MoveI2F src)); |
| 10978 effect( DEF dst, USE src ); | |
| 10979 | |
| 10980 ins_cost(100); | |
| 10981 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10982 ins_encode %{ |
| 10983 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10984 %} | |
| 0 | 10985 ins_pipe( ialu_mem_reg ); |
| 10986 %} | |
| 10987 | |
| 10988 | |
|
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10989 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 10990 predicate(UseSSE==0); |
| 10991 match(Set dst (MoveI2F src)); | |
| 10992 effect(DEF dst, USE src); | |
| 10993 | |
| 10994 ins_cost(125); | |
| 10995 format %{ "FLD_S $src\n\t" | |
| 10996 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 10997 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 10998 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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10999 Pop_Reg_FPR(dst) ); |
| 0 | 11000 ins_pipe( fpu_reg_mem ); |
| 11001 %} | |
| 11002 | |
|
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11003 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11004 predicate(UseSSE>=1); |
| 11005 match(Set dst (MoveI2F src)); | |
| 11006 effect( DEF dst, USE src ); | |
| 11007 | |
| 11008 ins_cost(95); | |
| 11009 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11010 ins_encode %{ |
| 11011 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11012 %} | |
| 0 | 11013 ins_pipe( pipe_slow ); |
| 11014 %} | |
| 11015 | |
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11016 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11017 predicate(UseSSE>=2); |
| 11018 match(Set dst (MoveI2F src)); | |
| 11019 effect( DEF dst, USE src ); | |
| 11020 | |
| 11021 ins_cost(85); | |
| 11022 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11023 ins_encode %{ |
| 11024 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11025 %} | |
| 0 | 11026 ins_pipe( pipe_slow ); |
| 11027 %} | |
| 11028 | |
| 11029 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11030 match(Set dst (MoveD2L src)); | |
| 11031 effect(DEF dst, USE src); | |
| 11032 | |
| 11033 ins_cost(250); | |
| 11034 format %{ "MOV $dst.lo,$src\n\t" | |
| 11035 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11036 opcode(0x8B, 0x8B); | |
| 11037 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11038 ins_pipe( ialu_mem_long_reg ); | |
| 11039 %} | |
| 11040 | |
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11041 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11042 predicate(UseSSE<=1); |
| 11043 match(Set dst (MoveD2L src)); | |
| 11044 effect(DEF dst, USE src); | |
| 11045 | |
| 11046 ins_cost(125); | |
| 11047 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
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11048 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11049 ins_pipe( fpu_mem_reg ); |
| 11050 %} | |
| 11051 | |
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11052 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11053 predicate(UseSSE>=2); |
| 11054 match(Set dst (MoveD2L src)); | |
| 11055 effect(DEF dst, USE src); | |
| 11056 ins_cost(95); | |
| 11057 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11058 ins_encode %{ |
| 11059 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11060 %} | |
| 0 | 11061 ins_pipe( pipe_slow ); |
| 11062 %} | |
| 11063 | |
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11064 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11065 predicate(UseSSE>=2); |
| 11066 match(Set dst (MoveD2L src)); | |
| 11067 effect(DEF dst, USE src, TEMP tmp); | |
| 11068 ins_cost(85); | |
| 11069 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11070 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11071 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11072 ins_encode %{ |
| 11073 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11074 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11075 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11076 %} | |
| 0 | 11077 ins_pipe( pipe_slow ); |
| 11078 %} | |
| 11079 | |
| 11080 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11081 match(Set dst (MoveL2D src)); | |
| 11082 effect(DEF dst, USE src); | |
| 11083 | |
| 11084 ins_cost(200); | |
| 11085 format %{ "MOV $dst,$src.lo\n\t" | |
| 11086 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11087 opcode(0x89, 0x89); | |
| 11088 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11089 ins_pipe( ialu_mem_long_reg ); | |
| 11090 %} | |
| 11091 | |
| 11092 | |
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11093 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11094 predicate(UseSSE<=1); |
| 11095 match(Set dst (MoveL2D src)); | |
| 11096 effect(DEF dst, USE src); | |
| 11097 ins_cost(125); | |
| 11098 | |
| 11099 format %{ "FLD_D $src\n\t" | |
| 11100 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11101 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11102 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11103 Pop_Reg_DPR(dst) ); |
| 0 | 11104 ins_pipe( fpu_reg_mem ); |
| 11105 %} | |
| 11106 | |
| 11107 | |
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11108 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11109 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11110 match(Set dst (MoveL2D src)); | |
| 11111 effect(DEF dst, USE src); | |
| 11112 | |
| 11113 ins_cost(95); | |
| 11114 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11115 ins_encode %{ |
| 11116 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11117 %} | |
| 0 | 11118 ins_pipe( pipe_slow ); |
| 11119 %} | |
| 11120 | |
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11121 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11122 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11123 match(Set dst (MoveL2D src)); | |
| 11124 effect(DEF dst, USE src); | |
| 11125 | |
| 11126 ins_cost(95); | |
| 11127 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11128 ins_encode %{ |
| 11129 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11130 %} | |
| 0 | 11131 ins_pipe( pipe_slow ); |
| 11132 %} | |
| 11133 | |
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11134 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11135 predicate(UseSSE>=2); |
| 11136 match(Set dst (MoveL2D src)); | |
| 11137 effect(TEMP dst, USE src, TEMP tmp); | |
| 11138 ins_cost(85); | |
| 11139 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11140 "MOVD $tmp,$src.hi\n\t" | |
| 11141 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11142 ins_encode %{ |
| 11143 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11144 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11145 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11146 %} | |
| 0 | 11147 ins_pipe( pipe_slow ); |
| 11148 %} | |
| 11149 | |
| 11150 | |
| 11151 // ======================================================================= | |
| 11152 // fast clearing of an array | |
| 11153 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
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11154 predicate(!UseFastStosb); |
| 0 | 11155 match(Set dummy (ClearArray cnt base)); |
| 11156 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
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11157 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
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11158 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11159 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
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11160 ins_encode %{ |
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11161 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
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11162 %} |
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11163 ins_pipe( pipe_slow ); |
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11164 %} |
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11165 |
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11166 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
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11167 predicate(UseFastStosb); |
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|
11168 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11169 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11170 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11171 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11172 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11173 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11174 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11175 %} |
| 0 | 11176 ins_pipe( pipe_slow ); |
| 11177 %} | |
| 11178 | |
| 2262 | 11179 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11180 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11181 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11182 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11183 | |
| 11184 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11185 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11186 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11187 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11188 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11189 %} |
| 681 | 11190 ins_pipe( pipe_slow ); |
| 11191 %} | |
| 11192 | |
| 11193 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11194 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11195 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11196 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11197 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11198 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11199 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11200 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11201 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11202 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11203 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11204 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11205 ins_pipe( pipe_slow ); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11206 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11207 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11208 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11209 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11210 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11211 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11212 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11213 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11214 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11215 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11216 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11217 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11218 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11219 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11220 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11221 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11222 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11223 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11224 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11225 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11226 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11227 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11228 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11229 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11230 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11231 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11232 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11233 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11234 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11235 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11236 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11237 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11238 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11239 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11240 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11241 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11242 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11243 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11244 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11245 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11246 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11247 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11248 %} |
| 0 | 11249 ins_pipe( pipe_slow ); |
| 11250 %} | |
| 11251 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11252 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11253 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11254 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11255 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11256 match(Set result (AryEq ary1 ary2)); |
| 681 | 11257 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11258 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11259 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11260 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11261 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11262 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11263 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11264 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11265 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11266 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11267 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11268 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11269 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11270 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11271 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11272 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11273 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11274 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11275 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11276 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11277 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11278 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11279 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11280 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11281 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11282 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11283 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11284 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11285 |
| 0 | 11286 //----------Control Flow Instructions------------------------------------------ |
| 11287 // Signed compare Instructions | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11288 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11289 match(Set cr (CmpI op1 op2)); |
| 11290 effect( DEF cr, USE op1, USE op2 ); | |
| 11291 format %{ "CMP $op1,$op2" %} | |
| 11292 opcode(0x3B); /* Opcode 3B /r */ | |
| 11293 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11294 ins_pipe( ialu_cr_reg_reg ); | |
| 11295 %} | |
| 11296 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11297 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11298 match(Set cr (CmpI op1 op2)); |
| 11299 effect( DEF cr, USE op1 ); | |
| 11300 format %{ "CMP $op1,$op2" %} | |
| 11301 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11302 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11303 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11304 ins_pipe( ialu_cr_reg_imm ); | |
| 11305 %} | |
| 11306 | |
| 11307 // Cisc-spilled version of cmpI_eReg | |
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11308 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11309 match(Set cr (CmpI op1 (LoadI op2))); |
| 11310 | |
| 11311 format %{ "CMP $op1,$op2" %} | |
| 11312 ins_cost(500); | |
| 11313 opcode(0x3B); /* Opcode 3B /r */ | |
| 11314 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11315 ins_pipe( ialu_cr_reg_mem ); | |
| 11316 %} | |
| 11317 | |
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11318 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11319 match(Set cr (CmpI src zero)); |
| 11320 effect( DEF cr, USE src ); | |
| 11321 | |
| 11322 format %{ "TEST $src,$src" %} | |
| 11323 opcode(0x85); | |
| 11324 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11325 ins_pipe( ialu_cr_reg_imm ); | |
| 11326 %} | |
| 11327 | |
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11328 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11329 match(Set cr (CmpI (AndI src con) zero)); |
| 11330 | |
| 11331 format %{ "TEST $src,$con" %} | |
| 11332 opcode(0xF7,0x00); | |
| 11333 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11334 ins_pipe( ialu_cr_reg_imm ); | |
| 11335 %} | |
| 11336 | |
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11337 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11338 match(Set cr (CmpI (AndI src mem) zero)); |
| 11339 | |
| 11340 format %{ "TEST $src,$mem" %} | |
| 11341 opcode(0x85); | |
| 11342 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11343 ins_pipe( ialu_cr_reg_mem ); | |
| 11344 %} | |
| 11345 | |
| 11346 // Unsigned compare Instructions; really, same as signed except they | |
| 11347 // produce an eFlagsRegU instead of eFlagsReg. | |
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11348 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11349 match(Set cr (CmpU op1 op2)); |
| 11350 | |
| 11351 format %{ "CMPu $op1,$op2" %} | |
| 11352 opcode(0x3B); /* Opcode 3B /r */ | |
| 11353 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11354 ins_pipe( ialu_cr_reg_reg ); | |
| 11355 %} | |
| 11356 | |
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11357 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11358 match(Set cr (CmpU op1 op2)); |
| 11359 | |
| 11360 format %{ "CMPu $op1,$op2" %} | |
| 11361 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11362 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11363 ins_pipe( ialu_cr_reg_imm ); | |
| 11364 %} | |
| 11365 | |
| 11366 // // Cisc-spilled version of cmpU_eReg | |
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11367 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11368 match(Set cr (CmpU op1 (LoadI op2))); |
| 11369 | |
| 11370 format %{ "CMPu $op1,$op2" %} | |
| 11371 ins_cost(500); | |
| 11372 opcode(0x3B); /* Opcode 3B /r */ | |
| 11373 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11374 ins_pipe( ialu_cr_reg_mem ); | |
| 11375 %} | |
| 11376 | |
| 11377 // // Cisc-spilled version of cmpU_eReg | |
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11378 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11379 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11380 // | |
| 11381 // format %{ "CMPu $op1,$op2" %} | |
| 11382 // ins_cost(500); | |
| 11383 // opcode(0x39); /* Opcode 39 /r */ | |
| 11384 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11385 //%} | |
| 11386 | |
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11387 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11388 match(Set cr (CmpU src zero)); |
| 11389 | |
| 11390 format %{ "TESTu $src,$src" %} | |
| 11391 opcode(0x85); | |
| 11392 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11393 ins_pipe( ialu_cr_reg_imm ); | |
| 11394 %} | |
| 11395 | |
| 11396 // Unsigned pointer compare Instructions | |
| 11397 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11398 match(Set cr (CmpP op1 op2)); | |
| 11399 | |
| 11400 format %{ "CMPu $op1,$op2" %} | |
| 11401 opcode(0x3B); /* Opcode 3B /r */ | |
| 11402 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11403 ins_pipe( ialu_cr_reg_reg ); | |
| 11404 %} | |
| 11405 | |
| 11406 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11407 match(Set cr (CmpP op1 op2)); | |
| 11408 | |
| 11409 format %{ "CMPu $op1,$op2" %} | |
| 11410 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11411 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11412 ins_pipe( ialu_cr_reg_imm ); | |
| 11413 %} | |
| 11414 | |
| 11415 // // Cisc-spilled version of cmpP_eReg | |
| 11416 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11417 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11418 | |
| 11419 format %{ "CMPu $op1,$op2" %} | |
| 11420 ins_cost(500); | |
| 11421 opcode(0x3B); /* Opcode 3B /r */ | |
| 11422 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11423 ins_pipe( ialu_cr_reg_mem ); | |
| 11424 %} | |
| 11425 | |
| 11426 // // Cisc-spilled version of cmpP_eReg | |
| 11427 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11428 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11429 // | |
| 11430 // format %{ "CMPu $op1,$op2" %} | |
| 11431 // ins_cost(500); | |
| 11432 // opcode(0x39); /* Opcode 39 /r */ | |
| 11433 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11434 //%} | |
| 11435 | |
| 11436 // Compare raw pointer (used in out-of-heap check). | |
| 11437 // Only works because non-oop pointers must be raw pointers | |
| 11438 // and raw pointers have no anti-dependencies. | |
| 11439 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
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11440 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11441 match(Set cr (CmpP op1 (LoadP op2))); |
| 11442 | |
| 11443 format %{ "CMPu $op1,$op2" %} | |
| 11444 opcode(0x3B); /* Opcode 3B /r */ | |
| 11445 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11446 ins_pipe( ialu_cr_reg_mem ); | |
| 11447 %} | |
| 11448 | |
| 11449 // | |
| 11450 // This will generate a signed flags result. This should be ok | |
| 11451 // since any compare to a zero should be eq/neq. | |
| 11452 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11453 match(Set cr (CmpP src zero)); | |
| 11454 | |
| 11455 format %{ "TEST $src,$src" %} | |
| 11456 opcode(0x85); | |
| 11457 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11458 ins_pipe( ialu_cr_reg_imm ); | |
| 11459 %} | |
| 11460 | |
| 11461 // Cisc-spilled version of testP_reg | |
| 11462 // This will generate a signed flags result. This should be ok | |
| 11463 // since any compare to a zero should be eq/neq. | |
| 11464 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11465 match(Set cr (CmpP (LoadP op) zero)); | |
| 11466 | |
| 11467 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11468 ins_cost(500); | |
| 11469 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11470 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11471 ins_pipe( ialu_cr_reg_imm ); | |
| 11472 %} | |
| 11473 | |
| 11474 // Yanked all unsigned pointer compare operations. | |
| 11475 // Pointer compares are done with CmpP which is already unsigned. | |
| 11476 | |
| 11477 //----------Max and Min-------------------------------------------------------- | |
| 11478 // Min Instructions | |
| 11479 //// | |
| 11480 // *** Min and Max using the conditional move are slower than the | |
| 11481 // *** branch version on a Pentium III. | |
| 11482 // // Conditional move for min | |
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11483 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11484 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11485 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11486 // opcode(0x4C,0x0F); | |
| 11487 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11488 // ins_pipe( pipe_cmov_reg ); | |
| 11489 //%} | |
| 11490 // | |
| 11491 //// Min Register with Register (P6 version) | |
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11492 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11493 // predicate(VM_Version::supports_cmov() ); |
| 11494 // match(Set op2 (MinI op1 op2)); | |
| 11495 // ins_cost(200); | |
| 11496 // expand %{ | |
| 11497 // eFlagsReg cr; | |
| 11498 // compI_eReg(cr,op1,op2); | |
| 11499 // cmovI_reg_lt(op2,op1,cr); | |
| 11500 // %} | |
| 11501 //%} | |
| 11502 | |
| 11503 // Min Register with Register (generic version) | |
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11504 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11505 match(Set dst (MinI dst src)); |
| 11506 effect(KILL flags); | |
| 11507 ins_cost(300); | |
| 11508 | |
| 11509 format %{ "MIN $dst,$src" %} | |
| 11510 opcode(0xCC); | |
| 11511 ins_encode( min_enc(dst,src) ); | |
| 11512 ins_pipe( pipe_slow ); | |
| 11513 %} | |
| 11514 | |
| 11515 // Max Register with Register | |
| 11516 // *** Min and Max using the conditional move are slower than the | |
| 11517 // *** branch version on a Pentium III. | |
| 11518 // // Conditional move for max | |
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11519 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11520 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11521 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11522 // opcode(0x4F,0x0F); | |
| 11523 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11524 // ins_pipe( pipe_cmov_reg ); | |
| 11525 //%} | |
| 11526 // | |
| 11527 // // Max Register with Register (P6 version) | |
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11528 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11529 // predicate(VM_Version::supports_cmov() ); |
| 11530 // match(Set op2 (MaxI op1 op2)); | |
| 11531 // ins_cost(200); | |
| 11532 // expand %{ | |
| 11533 // eFlagsReg cr; | |
| 11534 // compI_eReg(cr,op1,op2); | |
| 11535 // cmovI_reg_gt(op2,op1,cr); | |
| 11536 // %} | |
| 11537 //%} | |
| 11538 | |
| 11539 // Max Register with Register (generic version) | |
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11540 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11541 match(Set dst (MaxI dst src)); |
| 11542 effect(KILL flags); | |
| 11543 ins_cost(300); | |
| 11544 | |
| 11545 format %{ "MAX $dst,$src" %} | |
| 11546 opcode(0xCC); | |
| 11547 ins_encode( max_enc(dst,src) ); | |
| 11548 ins_pipe( pipe_slow ); | |
| 11549 %} | |
| 11550 | |
| 11551 // ============================================================================ | |
| 3345 | 11552 // Counted Loop limit node which represents exact final iterator value. |
| 11553 // Note: the resulting value should fit into integer range since | |
| 11554 // counted loops have limit check on overflow. | |
| 11555 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11556 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11557 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11558 ins_cost(300); | |
| 11559 | |
| 11560 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11561 ins_encode %{ | |
| 11562 int strd = (int)$stride$$constant; | |
| 11563 assert(strd != 1 && strd != -1, "sanity"); | |
| 11564 int m1 = (strd > 0) ? 1 : -1; | |
| 11565 // Convert limit to long (EAX:EDX) | |
| 11566 __ cdql(); | |
| 11567 // Convert init to long (init:tmp) | |
| 11568 __ movl($tmp$$Register, $init$$Register); | |
| 11569 __ sarl($tmp$$Register, 31); | |
| 11570 // $limit - $init | |
| 11571 __ subl($limit$$Register, $init$$Register); | |
| 11572 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11573 // + ($stride - 1) | |
| 11574 if (strd > 0) { | |
| 11575 __ addl($limit$$Register, (strd - 1)); | |
| 11576 __ adcl($limit_hi$$Register, 0); | |
| 11577 __ movl($tmp$$Register, strd); | |
| 11578 } else { | |
| 11579 __ addl($limit$$Register, (strd + 1)); | |
| 11580 __ adcl($limit_hi$$Register, -1); | |
| 11581 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11582 __ movl($tmp$$Register, -strd); | |
| 11583 } | |
| 11584 // signed devision: (EAX:EDX) / pos_stride | |
| 11585 __ idivl($tmp$$Register); | |
| 11586 if (strd < 0) { | |
| 11587 // restore sign | |
| 11588 __ negl($tmp$$Register); | |
| 11589 } | |
| 11590 // (EAX) * stride | |
| 11591 __ mull($tmp$$Register); | |
| 11592 // + init (ignore upper bits) | |
| 11593 __ addl($limit$$Register, $init$$Register); | |
| 11594 %} | |
| 11595 ins_pipe( pipe_slow ); | |
| 11596 %} | |
| 11597 | |
| 11598 // ============================================================================ | |
| 0 | 11599 // Branch Instructions |
| 11600 // Jump Table | |
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11601 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11602 match(Jump switch_val); |
| 11603 ins_cost(350); | |
| 2008 | 11604 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11605 ins_encode %{ | |
| 0 | 11606 // Jump to Address(table_base + switch_reg) |
| 11607 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11608 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11609 %} |
| 11610 ins_pipe(pipe_jmp); | |
| 11611 %} | |
| 11612 | |
| 11613 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11614 instruct jmpDir(label labl) %{ | |
| 11615 match(Goto); | |
| 11616 effect(USE labl); | |
| 11617 | |
| 11618 ins_cost(300); | |
| 11619 format %{ "JMP $labl" %} | |
| 11620 size(5); | |
| 3851 | 11621 ins_encode %{ |
| 11622 Label* L = $labl$$label; | |
| 11623 __ jmp(*L, false); // Always long jump | |
| 11624 %} | |
| 0 | 11625 ins_pipe( pipe_jmp ); |
| 11626 %} | |
| 11627 | |
| 11628 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11629 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11630 match(If cop cr); | |
| 11631 effect(USE labl); | |
| 11632 | |
| 11633 ins_cost(300); | |
| 11634 format %{ "J$cop $labl" %} | |
| 11635 size(6); | |
| 3851 | 11636 ins_encode %{ |
| 11637 Label* L = $labl$$label; | |
| 11638 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11639 %} | |
| 0 | 11640 ins_pipe( pipe_jcc ); |
| 11641 %} | |
| 11642 | |
| 11643 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11644 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11645 match(CountedLoopEnd cop cr); | |
| 11646 effect(USE labl); | |
| 11647 | |
| 11648 ins_cost(300); | |
| 11649 format %{ "J$cop $labl\t# Loop end" %} | |
| 11650 size(6); | |
| 3851 | 11651 ins_encode %{ |
| 11652 Label* L = $labl$$label; | |
| 11653 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11654 %} | |
| 0 | 11655 ins_pipe( pipe_jcc ); |
| 11656 %} | |
| 11657 | |
| 11658 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11659 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11660 match(CountedLoopEnd cop cmp); | |
| 11661 effect(USE labl); | |
| 11662 | |
| 11663 ins_cost(300); | |
| 11664 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 11665 size(6); | |
| 3851 | 11666 ins_encode %{ |
| 11667 Label* L = $labl$$label; | |
| 11668 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11669 %} | |
| 0 | 11670 ins_pipe( pipe_jcc ); |
| 11671 %} | |
| 11672 | |
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11673 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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11674 match(CountedLoopEnd cop cmp); |
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11675 effect(USE labl); |
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11676 |
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11677 ins_cost(200); |
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11678 format %{ "J$cop,u $labl\t# Loop end" %} |
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11679 size(6); |
| 3851 | 11680 ins_encode %{ |
| 11681 Label* L = $labl$$label; | |
| 11682 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11683 %} | |
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11684 ins_pipe( pipe_jcc ); |
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11685 %} |
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11686 |
| 0 | 11687 // Jump Direct Conditional - using unsigned comparison |
| 11688 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11689 match(If cop cmp); | |
| 11690 effect(USE labl); | |
| 11691 | |
| 11692 ins_cost(300); | |
| 11693 format %{ "J$cop,u $labl" %} | |
| 11694 size(6); | |
| 3851 | 11695 ins_encode %{ |
| 11696 Label* L = $labl$$label; | |
| 11697 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11698 %} | |
|
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|
11699 ins_pipe(pipe_jcc); |
|
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|
11700 %} |
|
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changeset
|
11701 |
|
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diff
changeset
|
11702 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
11703 match(If cop cmp); |
|
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diff
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|
11704 effect(USE labl); |
|
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diff
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|
11705 |
|
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diff
changeset
|
11706 ins_cost(200); |
|
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diff
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|
11707 format %{ "J$cop,u $labl" %} |
|
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|
11708 size(6); |
| 3851 | 11709 ins_encode %{ |
| 11710 Label* L = $labl$$label; | |
| 11711 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11712 %} | |
|
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|
11713 ins_pipe(pipe_jcc); |
|
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changeset
|
11714 %} |
|
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changeset
|
11715 |
|
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diff
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|
11716 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
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|
11717 match(If cop cmp); |
|
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never
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diff
changeset
|
11718 effect(USE labl); |
|
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diff
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|
11719 |
|
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changeset
|
11720 ins_cost(200); |
|
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diff
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|
11721 format %{ $$template |
|
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|
11722 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11723 $$emit$$"JP,u $labl\n\t" |
|
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|
11724 $$emit$$"J$cop,u $labl" |
|
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|
11725 } else { |
|
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changeset
|
11726 $$emit$$"JP,u done\n\t" |
|
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|
11727 $$emit$$"J$cop,u $labl\n\t" |
|
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|
11728 $$emit$$"done:" |
|
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diff
changeset
|
11729 } |
|
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diff
changeset
|
11730 %} |
|
4d9884b01ba6
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never
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403
diff
changeset
|
11731 ins_encode %{ |
|
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changeset
|
11732 Label* l = $labl$$label; |
|
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|
11733 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11734 __ jcc(Assembler::parity, *l, false); |
| 11735 __ jcc(Assembler::notEqual, *l, false); | |
|
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|
11736 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11737 Label done; |
| 11738 __ jccb(Assembler::parity, done); | |
| 11739 __ jcc(Assembler::equal, *l, false); | |
| 11740 __ bind(done); | |
|
415
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|
11741 } else { |
|
4d9884b01ba6
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changeset
|
11742 ShouldNotReachHere(); |
|
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|
11743 } |
|
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changeset
|
11744 %} |
|
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|
11745 ins_pipe(pipe_jcc); |
| 0 | 11746 %} |
| 11747 | |
| 11748 // ============================================================================ | |
| 11749 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 11750 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 11751 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 11752 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 11753 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 11754 match(Set result (PartialSubtypeCheck sub super)); | |
| 11755 effect( KILL rcx, KILL cr ); | |
| 11756 | |
| 11757 ins_cost(1100); // slightly larger than the next version | |
|
644
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changeset
|
11758 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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6795
diff
changeset
|
11759 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
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coleenp
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6795
diff
changeset
|
11760 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11761 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 11762 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 11763 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 11764 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 11765 "miss:\t" %} | |
| 11766 | |
| 11767 opcode(0x1); // Force a XOR of EDI | |
| 11768 ins_encode( enc_PartialSubtypeCheck() ); | |
| 11769 ins_pipe( pipe_slow ); | |
| 11770 %} | |
| 11771 | |
| 11772 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 11773 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11774 effect( KILL rcx, KILL result ); | |
| 11775 | |
| 11776 ins_cost(1000); | |
|
644
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parents:
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diff
changeset
|
11777 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
11778 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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6795
diff
changeset
|
11779 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11780 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 11781 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 11782 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 11783 "miss:\t" %} | |
| 11784 | |
| 11785 opcode(0x0); // No need to XOR EDI | |
| 11786 ins_encode( enc_PartialSubtypeCheck() ); | |
| 11787 ins_pipe( pipe_slow ); | |
| 11788 %} | |
| 11789 | |
| 11790 // ============================================================================ | |
| 11791 // Branch Instructions -- short offset versions | |
| 11792 // | |
| 11793 // These instructions are used to replace jumps of a long offset (the default | |
| 11794 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11795 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11796 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11797 // method in the MachNode which can be used to do in-place replacement of the | |
| 11798 // long variant with the shorter variant. The compiler will determine if a | |
| 11799 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11800 // specific code section of the file. | |
| 11801 | |
| 11802 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11803 instruct jmpDir_short(label labl) %{ | |
| 11804 match(Goto); | |
| 11805 effect(USE labl); | |
| 11806 | |
| 11807 ins_cost(300); | |
| 11808 format %{ "JMP,s $labl" %} | |
| 11809 size(2); | |
| 3851 | 11810 ins_encode %{ |
| 11811 Label* L = $labl$$label; | |
| 11812 __ jmpb(*L); | |
| 11813 %} | |
| 0 | 11814 ins_pipe( pipe_jmp ); |
| 11815 ins_short_branch(1); | |
| 11816 %} | |
| 11817 | |
| 11818 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11819 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11820 match(If cop cr); | |
| 11821 effect(USE labl); | |
| 11822 | |
| 11823 ins_cost(300); | |
| 11824 format %{ "J$cop,s $labl" %} | |
| 11825 size(2); | |
| 3851 | 11826 ins_encode %{ |
| 11827 Label* L = $labl$$label; | |
| 11828 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11829 %} | |
| 0 | 11830 ins_pipe( pipe_jcc ); |
| 11831 ins_short_branch(1); | |
| 11832 %} | |
| 11833 | |
| 11834 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11835 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11836 match(CountedLoopEnd cop cr); | |
| 11837 effect(USE labl); | |
| 11838 | |
| 11839 ins_cost(300); | |
|
415
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diff
changeset
|
11840 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 11841 size(2); |
| 3851 | 11842 ins_encode %{ |
| 11843 Label* L = $labl$$label; | |
| 11844 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11845 %} | |
| 0 | 11846 ins_pipe( pipe_jcc ); |
| 11847 ins_short_branch(1); | |
| 11848 %} | |
| 11849 | |
| 11850 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11851 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11852 match(CountedLoopEnd cop cmp); | |
| 11853 effect(USE labl); | |
| 11854 | |
| 11855 ins_cost(300); | |
|
415
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403
diff
changeset
|
11856 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
11857 size(2); |
| 3851 | 11858 ins_encode %{ |
| 11859 Label* L = $labl$$label; | |
| 11860 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11861 %} | |
|
415
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diff
changeset
|
11862 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
11863 ins_short_branch(1); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
11864 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11865 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11866 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
11867 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
11868 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11869 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11870 ins_cost(300); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11871 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 11872 size(2); |
| 3851 | 11873 ins_encode %{ |
| 11874 Label* L = $labl$$label; | |
| 11875 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11876 %} | |
| 0 | 11877 ins_pipe( pipe_jcc ); |
| 11878 ins_short_branch(1); | |
| 11879 %} | |
| 11880 | |
| 11881 // Jump Direct Conditional - using unsigned comparison | |
| 11882 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11883 match(If cop cmp); | |
| 11884 effect(USE labl); | |
| 11885 | |
| 11886 ins_cost(300); | |
| 11887 format %{ "J$cop,us $labl" %} | |
| 11888 size(2); | |
| 3851 | 11889 ins_encode %{ |
| 11890 Label* L = $labl$$label; | |
| 11891 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11892 %} | |
| 0 | 11893 ins_pipe( pipe_jcc ); |
| 11894 ins_short_branch(1); | |
| 11895 %} | |
| 11896 | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
11897 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
11898 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11899 effect(USE labl); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
11900 |
|
4d9884b01ba6
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diff
changeset
|
11901 ins_cost(300); |
|
4d9884b01ba6
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403
diff
changeset
|
11902 format %{ "J$cop,us $labl" %} |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
11903 size(2); |
| 3851 | 11904 ins_encode %{ |
| 11905 Label* L = $labl$$label; | |
| 11906 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11907 %} | |
|
415
4d9884b01ba6
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changeset
|
11908 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
11909 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
11910 %} |
|
4d9884b01ba6
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never
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403
diff
changeset
|
11911 |
|
4d9884b01ba6
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never
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403
diff
changeset
|
11912 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
11913 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
11914 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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diff
changeset
|
11915 |
|
4d9884b01ba6
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403
diff
changeset
|
11916 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
11917 format %{ $$template |
|
4d9884b01ba6
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diff
changeset
|
11918 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
11919 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
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never
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403
diff
changeset
|
11920 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
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403
diff
changeset
|
11921 } else { |
|
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diff
changeset
|
11922 $$emit$$"JP,u,s done\n\t" |
|
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|
11923 $$emit$$"J$cop,u,s $labl\n\t" |
|
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11924 $$emit$$"done:" |
|
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|
11925 } |
|
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|
11926 %} |
|
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|
11927 size(4); |
|
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|
11928 ins_encode %{ |
|
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|
11929 Label* l = $labl$$label; |
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|
11930 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11931 __ jccb(Assembler::parity, *l); |
| 11932 __ jccb(Assembler::notEqual, *l); | |
|
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|
11933 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11934 Label done; |
| 11935 __ jccb(Assembler::parity, done); | |
| 11936 __ jccb(Assembler::equal, *l); | |
| 11937 __ bind(done); | |
|
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|
11938 } else { |
| 3851 | 11939 ShouldNotReachHere(); |
| 11940 } | |
|
415
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|
11941 %} |
|
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|
11942 ins_pipe(pipe_jcc); |
|
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|
11943 ins_short_branch(1); |
|
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|
11944 %} |
|
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|
11945 |
| 0 | 11946 // ============================================================================ |
| 11947 // Long Compare | |
| 11948 // | |
| 11949 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 11950 // is tricky. The flavor of compare used depends on whether we are testing | |
| 11951 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 11952 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 11953 // the operands (yielding a GE test) and then negating; negate again for the | |
| 11954 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 11955 // NE test is negated from that. | |
| 11956 | |
| 11957 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 11958 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 11959 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 11960 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 11961 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 11962 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 11963 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 11964 // both forms beat the trinary form of long-compare and both are very useful | |
| 11965 // on Intel which has so few registers. | |
| 11966 | |
| 11967 // Manifest a CmpL result in an integer register. Very painful. | |
| 11968 // This is the test to avoid. | |
| 11969 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 11970 match(Set dst (CmpL3 src1 src2)); | |
| 11971 effect( KILL flags ); | |
| 11972 ins_cost(1000); | |
| 11973 format %{ "XOR $dst,$dst\n\t" | |
| 11974 "CMP $src1.hi,$src2.hi\n\t" | |
| 11975 "JLT,s m_one\n\t" | |
| 11976 "JGT,s p_one\n\t" | |
| 11977 "CMP $src1.lo,$src2.lo\n\t" | |
| 11978 "JB,s m_one\n\t" | |
| 11979 "JEQ,s done\n" | |
| 11980 "p_one:\tINC $dst\n\t" | |
| 11981 "JMP,s done\n" | |
| 11982 "m_one:\tDEC $dst\n" | |
| 11983 "done:" %} | |
| 11984 ins_encode %{ | |
| 11985 Label p_one, m_one, done; | |
| 304 | 11986 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 11987 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 11988 __ jccb(Assembler::less, m_one); | |
| 11989 __ jccb(Assembler::greater, p_one); | |
| 11990 __ cmpl($src1$$Register, $src2$$Register); | |
| 11991 __ jccb(Assembler::below, m_one); | |
| 11992 __ jccb(Assembler::equal, done); | |
| 11993 __ bind(p_one); | |
| 304 | 11994 __ incrementl($dst$$Register); |
| 0 | 11995 __ jmpb(done); |
| 11996 __ bind(m_one); | |
| 304 | 11997 __ decrementl($dst$$Register); |
| 0 | 11998 __ bind(done); |
| 11999 %} | |
| 12000 ins_pipe( pipe_slow ); | |
| 12001 %} | |
| 12002 | |
| 12003 //====== | |
| 12004 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12005 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12006 // NOT GOOD FOR EQ/NE tests. | |
| 12007 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12008 match( Set flags (CmpL src zero )); | |
| 12009 ins_cost(100); | |
| 12010 format %{ "TEST $src.hi,$src.hi" %} | |
| 12011 opcode(0x85); | |
| 12012 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12013 ins_pipe( ialu_cr_reg_reg ); | |
| 12014 %} | |
| 12015 | |
| 12016 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12017 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12018 // NOT GOOD FOR EQ/NE tests. | |
|
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12019 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12020 match( Set flags (CmpL src1 src2 )); |
| 12021 effect( TEMP tmp ); | |
| 12022 ins_cost(300); | |
| 12023 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12024 "MOV $tmp,$src1.hi\n\t" | |
| 12025 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12026 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12027 ins_pipe( ialu_cr_reg_reg ); | |
| 12028 %} | |
| 12029 | |
| 12030 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12031 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12032 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12033 match(If cmp flags); | |
| 12034 effect(USE labl); | |
| 12035 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12036 expand %{ | |
| 12037 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12038 %} | |
| 12039 %} | |
| 12040 | |
| 12041 // Compare 2 longs and CMOVE longs. | |
| 12042 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12043 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12044 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12045 ins_cost(400); | |
| 12046 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12047 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12048 opcode(0x0F,0x40); | |
| 12049 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12050 ins_pipe( pipe_cmov_reg_long ); | |
| 12051 %} | |
| 12052 | |
| 12053 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12054 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12055 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12056 ins_cost(500); | |
| 12057 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12058 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12059 opcode(0x0F,0x40); | |
| 12060 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12061 ins_pipe( pipe_cmov_reg_long ); | |
| 12062 %} | |
| 12063 | |
| 12064 // Compare 2 longs and CMOVE ints. | |
|
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12065 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12066 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12067 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12068 ins_cost(200); | |
| 12069 format %{ "CMOV$cmp $dst,$src" %} | |
| 12070 opcode(0x0F,0x40); | |
| 12071 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12072 ins_pipe( pipe_cmov_reg ); | |
| 12073 %} | |
| 12074 | |
|
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12075 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12076 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12077 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12078 ins_cost(250); | |
| 12079 format %{ "CMOV$cmp $dst,$src" %} | |
| 12080 opcode(0x0F,0x40); | |
| 12081 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12082 ins_pipe( pipe_cmov_mem ); | |
| 12083 %} | |
| 12084 | |
| 12085 // Compare 2 longs and CMOVE ints. | |
| 12086 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12087 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12088 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12089 ins_cost(200); | |
| 12090 format %{ "CMOV$cmp $dst,$src" %} | |
| 12091 opcode(0x0F,0x40); | |
| 12092 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12093 ins_pipe( pipe_cmov_reg ); | |
| 12094 %} | |
| 12095 | |
| 12096 // Compare 2 longs and CMOVE doubles | |
|
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12097 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12098 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12099 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12100 ins_cost(200); | |
| 12101 expand %{ | |
|
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|
12102 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12103 %} |
| 12104 %} | |
| 12105 | |
| 12106 // Compare 2 longs and CMOVE doubles | |
|
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|
12107 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12108 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12109 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12110 ins_cost(200); | |
| 12111 expand %{ | |
|
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|
12112 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12113 %} |
|
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|
12114 %} |
|
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|
12115 |
|
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|
12116 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
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|
12117 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
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|
12118 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12119 ins_cost(200); |
|
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|
12120 expand %{ |
|
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|
12121 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12122 %} |
| 12123 %} | |
| 12124 | |
| 12125 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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12126 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12127 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12128 ins_cost(200); | |
| 12129 expand %{ | |
| 12130 fcmovF_regS(cmp,flags,dst,src); | |
| 12131 %} | |
| 12132 %} | |
| 12133 | |
| 12134 //====== | |
| 12135 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12136 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12137 match( Set flags (CmpL src zero )); |
| 12138 effect(TEMP tmp); | |
| 12139 ins_cost(200); | |
| 12140 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12141 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12142 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12143 ins_pipe( ialu_reg_reg_long ); | |
| 12144 %} | |
| 12145 | |
| 12146 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12147 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12148 match( Set flags (CmpL src1 src2 )); | |
| 12149 ins_cost(200+300); | |
| 12150 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12151 "JNE,s skip\n\t" | |
| 12152 "CMP $src1.hi,$src2.hi\n\t" | |
| 12153 "skip:\t" %} | |
| 12154 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12155 ins_pipe( ialu_cr_reg_reg ); | |
| 12156 %} | |
| 12157 | |
| 12158 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12159 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12160 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12161 match(If cmp flags); | |
| 12162 effect(USE labl); | |
| 12163 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12164 expand %{ | |
| 12165 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12166 %} | |
| 12167 %} | |
| 12168 | |
| 12169 // Compare 2 longs and CMOVE longs. | |
| 12170 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12171 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12172 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12173 ins_cost(400); | |
| 12174 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12175 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12176 opcode(0x0F,0x40); | |
| 12177 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12178 ins_pipe( pipe_cmov_reg_long ); | |
| 12179 %} | |
| 12180 | |
| 12181 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12182 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12183 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12184 ins_cost(500); | |
| 12185 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12186 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12187 opcode(0x0F,0x40); | |
| 12188 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12189 ins_pipe( pipe_cmov_reg_long ); | |
| 12190 %} | |
| 12191 | |
| 12192 // Compare 2 longs and CMOVE ints. | |
|
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12193 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12194 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12195 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12196 ins_cost(200); | |
| 12197 format %{ "CMOV$cmp $dst,$src" %} | |
| 12198 opcode(0x0F,0x40); | |
| 12199 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12200 ins_pipe( pipe_cmov_reg ); | |
| 12201 %} | |
| 12202 | |
|
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12203 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12204 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12205 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12206 ins_cost(250); | |
| 12207 format %{ "CMOV$cmp $dst,$src" %} | |
| 12208 opcode(0x0F,0x40); | |
| 12209 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12210 ins_pipe( pipe_cmov_mem ); | |
| 12211 %} | |
| 12212 | |
| 12213 // Compare 2 longs and CMOVE ints. | |
| 12214 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12215 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12216 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12217 ins_cost(200); | |
| 12218 format %{ "CMOV$cmp $dst,$src" %} | |
| 12219 opcode(0x0F,0x40); | |
| 12220 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12221 ins_pipe( pipe_cmov_reg ); | |
| 12222 %} | |
| 12223 | |
| 12224 // Compare 2 longs and CMOVE doubles | |
|
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12225 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12226 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12227 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12228 ins_cost(200); | |
| 12229 expand %{ | |
|
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12230 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12231 %} |
| 12232 %} | |
| 12233 | |
| 12234 // Compare 2 longs and CMOVE doubles | |
|
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12235 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12236 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12237 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12238 ins_cost(200); | |
| 12239 expand %{ | |
|
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12240 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12241 %} |
|
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|
12242 %} |
|
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|
12243 |
|
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12244 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12245 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12246 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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|
12247 ins_cost(200); |
|
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|
12248 expand %{ |
|
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12249 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12250 %} |
| 12251 %} | |
| 12252 | |
| 12253 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12254 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12255 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12256 ins_cost(200); | |
| 12257 expand %{ | |
| 12258 fcmovF_regS(cmp,flags,dst,src); | |
| 12259 %} | |
| 12260 %} | |
| 12261 | |
| 12262 //====== | |
| 12263 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12264 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12265 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12266 match( Set flags (CmpL src zero )); |
| 12267 effect( TEMP tmp ); | |
| 12268 ins_cost(300); | |
| 12269 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12270 "CMP $tmp,$src.lo\n\t" | |
| 12271 "SBB $tmp,$src.hi\n\t" %} | |
| 12272 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12273 ins_pipe( ialu_reg_reg_long ); | |
| 12274 %} | |
| 12275 | |
| 12276 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12277 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12278 // requires a commuted test to get the same result. | |
|
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12279 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12280 match( Set flags (CmpL src1 src2 )); |
| 12281 effect( TEMP tmp ); | |
| 12282 ins_cost(300); | |
| 12283 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12284 "MOV $tmp,$src2.hi\n\t" | |
| 12285 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12286 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12287 ins_pipe( ialu_cr_reg_reg ); | |
| 12288 %} | |
| 12289 | |
| 12290 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12291 // Just a wrapper for a normal branch, plus the predicate test | |
| 12292 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12293 match(If cmp flags); | |
| 12294 effect(USE labl); | |
| 12295 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12296 ins_cost(300); | |
| 12297 expand %{ | |
| 12298 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12299 %} | |
| 12300 %} | |
| 12301 | |
| 12302 // Compare 2 longs and CMOVE longs. | |
| 12303 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12304 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12305 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12306 ins_cost(400); | |
| 12307 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12308 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12309 opcode(0x0F,0x40); | |
| 12310 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12311 ins_pipe( pipe_cmov_reg_long ); | |
| 12312 %} | |
| 12313 | |
| 12314 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12315 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12316 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12317 ins_cost(500); | |
| 12318 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12319 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12320 opcode(0x0F,0x40); | |
| 12321 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12322 ins_pipe( pipe_cmov_reg_long ); | |
| 12323 %} | |
| 12324 | |
| 12325 // Compare 2 longs and CMOVE ints. | |
|
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12326 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12327 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12328 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12329 ins_cost(200); | |
| 12330 format %{ "CMOV$cmp $dst,$src" %} | |
| 12331 opcode(0x0F,0x40); | |
| 12332 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12333 ins_pipe( pipe_cmov_reg ); | |
| 12334 %} | |
| 12335 | |
|
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12336 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12337 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12338 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12339 ins_cost(250); | |
| 12340 format %{ "CMOV$cmp $dst,$src" %} | |
| 12341 opcode(0x0F,0x40); | |
| 12342 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12343 ins_pipe( pipe_cmov_mem ); | |
| 12344 %} | |
| 12345 | |
| 12346 // Compare 2 longs and CMOVE ptrs. | |
| 12347 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12348 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12349 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12350 ins_cost(200); | |
| 12351 format %{ "CMOV$cmp $dst,$src" %} | |
| 12352 opcode(0x0F,0x40); | |
| 12353 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12354 ins_pipe( pipe_cmov_reg ); | |
| 12355 %} | |
| 12356 | |
| 12357 // Compare 2 longs and CMOVE doubles | |
|
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12358 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12359 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12360 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12361 ins_cost(200); | |
| 12362 expand %{ | |
|
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|
12363 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12364 %} |
| 12365 %} | |
| 12366 | |
| 12367 // Compare 2 longs and CMOVE doubles | |
|
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|
12368 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12369 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12370 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12371 ins_cost(200); | |
| 12372 expand %{ | |
|
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|
12373 fcmovD_regS(cmp,flags,dst,src); |
|
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|
12374 %} |
|
65149e74c706
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|
12375 %} |
|
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|
12376 |
|
65149e74c706
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|
12377 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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|
12378 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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|
12379 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
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|
12380 ins_cost(200); |
|
65149e74c706
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|
12381 expand %{ |
|
65149e74c706
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|
12382 fcmovFPR_regS(cmp,flags,dst,src); |
|
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|
12383 %} |
|
65149e74c706
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|
12384 %} |
|
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|
12385 |
| 0 | 12386 |
| 12387 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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|
12388 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12389 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12390 ins_cost(200); | |
| 12391 expand %{ | |
| 12392 fcmovF_regS(cmp,flags,dst,src); | |
| 12393 %} | |
| 12394 %} | |
| 12395 | |
| 12396 | |
| 12397 // ============================================================================ | |
| 12398 // Procedure Call/Return Instructions | |
| 12399 // Call Java Static Instruction | |
| 12400 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12401 // compute_padding() functions will have to be adjusted. | |
| 12402 instruct CallStaticJavaDirect(method meth) %{ | |
| 12403 match(CallStaticJava); | |
|
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|
12404 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 12405 effect(USE meth); |
| 12406 | |
| 12407 ins_cost(300); | |
| 12408 format %{ "CALL,static " %} | |
| 12409 opcode(0xE8); /* E8 cd */ | |
|
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|
12410 ins_encode( pre_call_resets, |
| 0 | 12411 Java_Static_Call( meth ), |
| 12412 call_epilog, | |
| 12413 post_call_FPU ); | |
| 12414 ins_pipe( pipe_slow ); | |
| 12415 ins_alignment(4); | |
| 12416 %} | |
| 12417 | |
|
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|
12418 // Call Java Static Instruction (method handle version) |
|
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|
12419 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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diff
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|
12420 // compute_padding() functions will have to be adjusted. |
| 1567 | 12421 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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|
12422 match(CallStaticJava); |
|
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|
12423 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
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diff
changeset
|
12424 effect(USE meth); |
|
97125851f396
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|
12425 // EBP is saved by all callees (for interpreter stack correction). |
|
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|
12426 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
12427 |
|
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|
12428 ins_cost(300); |
|
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|
12429 format %{ "CALL,static/MethodHandle " %} |
|
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|
12430 opcode(0xE8); /* E8 cd */ |
|
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|
12431 ins_encode( pre_call_resets, |
|
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|
12432 preserve_SP, |
|
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|
12433 Java_Static_Call( meth ), |
|
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|
12434 restore_SP, |
|
97125851f396
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|
12435 call_epilog, |
|
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|
12436 post_call_FPU ); |
|
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|
12437 ins_pipe( pipe_slow ); |
|
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|
12438 ins_alignment(4); |
|
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|
12439 %} |
|
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|
12440 |
| 0 | 12441 // Call Java Dynamic Instruction |
| 12442 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12443 // compute_padding() functions will have to be adjusted. | |
| 12444 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12445 match(CallDynamicJava); | |
| 12446 effect(USE meth); | |
| 12447 | |
| 12448 ins_cost(300); | |
| 12449 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12450 "CALL,dynamic" %} | |
| 12451 opcode(0xE8); /* E8 cd */ | |
|
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12452 ins_encode( pre_call_resets, |
| 0 | 12453 Java_Dynamic_Call( meth ), |
| 12454 call_epilog, | |
| 12455 post_call_FPU ); | |
| 12456 ins_pipe( pipe_slow ); | |
| 12457 ins_alignment(4); | |
| 12458 %} | |
| 12459 | |
| 12460 // Call Runtime Instruction | |
| 12461 instruct CallRuntimeDirect(method meth) %{ | |
| 12462 match(CallRuntime ); | |
| 12463 effect(USE meth); | |
| 12464 | |
| 12465 ins_cost(300); | |
| 12466 format %{ "CALL,runtime " %} | |
| 12467 opcode(0xE8); /* E8 cd */ | |
| 12468 // Use FFREEs to clear entries in float stack | |
|
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|
12469 ins_encode( pre_call_resets, |
| 0 | 12470 FFree_Float_Stack_All, |
| 12471 Java_To_Runtime( meth ), | |
| 12472 post_call_FPU ); | |
| 12473 ins_pipe( pipe_slow ); | |
| 12474 %} | |
| 12475 | |
| 12476 // Call runtime without safepoint | |
| 12477 instruct CallLeafDirect(method meth) %{ | |
| 12478 match(CallLeaf); | |
| 12479 effect(USE meth); | |
| 12480 | |
| 12481 ins_cost(300); | |
| 12482 format %{ "CALL_LEAF,runtime " %} | |
| 12483 opcode(0xE8); /* E8 cd */ | |
|
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12484 ins_encode( pre_call_resets, |
| 0 | 12485 FFree_Float_Stack_All, |
| 12486 Java_To_Runtime( meth ), | |
| 12487 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12488 ins_pipe( pipe_slow ); | |
| 12489 %} | |
| 12490 | |
| 12491 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12492 match(CallLeafNoFP); | |
| 12493 effect(USE meth); | |
| 12494 | |
| 12495 ins_cost(300); | |
| 12496 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12497 opcode(0xE8); /* E8 cd */ | |
| 12498 ins_encode(Java_To_Runtime(meth)); | |
| 12499 ins_pipe( pipe_slow ); | |
| 12500 %} | |
| 12501 | |
| 12502 | |
| 12503 // Return Instruction | |
| 12504 // Remove the return address & jump to it. | |
| 12505 instruct Ret() %{ | |
| 12506 match(Return); | |
| 12507 format %{ "RET" %} | |
| 12508 opcode(0xC3); | |
| 12509 ins_encode(OpcP); | |
| 12510 ins_pipe( pipe_jmp ); | |
| 12511 %} | |
| 12512 | |
| 12513 // Tail Call; Jump from runtime stub to Java code. | |
| 12514 // Also known as an 'interprocedural jump'. | |
| 12515 // Target of jump will eventually return to caller. | |
| 12516 // TailJump below removes the return address. | |
| 12517 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12518 match(TailCall jump_target method_oop ); | |
| 12519 ins_cost(300); | |
| 12520 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12521 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12522 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12523 ins_pipe( pipe_jmp ); | |
| 12524 %} | |
| 12525 | |
| 12526 | |
| 12527 // Tail Jump; remove the return address; jump to target. | |
| 12528 // TailCall above leaves the return address around. | |
| 12529 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12530 match( TailJump jump_target ex_oop ); | |
| 12531 ins_cost(300); | |
| 12532 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12533 "JMP $jump_target " %} | |
| 12534 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12535 ins_encode( enc_pop_rdx, | |
| 12536 OpcP, RegOpc(jump_target) ); | |
| 12537 ins_pipe( pipe_jmp ); | |
| 12538 %} | |
| 12539 | |
| 12540 // Create exception oop: created by stack-crawling runtime code. | |
| 12541 // Created exception is now available to this handler, and is setup | |
| 12542 // just prior to jumping to this handler. No code emitted. | |
| 12543 instruct CreateException( eAXRegP ex_oop ) | |
| 12544 %{ | |
| 12545 match(Set ex_oop (CreateEx)); | |
| 12546 | |
| 12547 size(0); | |
| 12548 // use the following format syntax | |
| 12549 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12550 ins_encode(); | |
| 12551 ins_pipe( empty ); | |
| 12552 %} | |
| 12553 | |
| 12554 | |
| 12555 // Rethrow exception: | |
| 12556 // The exception oop will come in the first argument position. | |
| 12557 // Then JUMP (not call) to the rethrow stub code. | |
| 12558 instruct RethrowException() | |
| 12559 %{ | |
| 12560 match(Rethrow); | |
| 12561 | |
| 12562 // use the following format syntax | |
| 12563 format %{ "JMP rethrow_stub" %} | |
| 12564 ins_encode(enc_rethrow); | |
| 12565 ins_pipe( pipe_jmp ); | |
| 12566 %} | |
| 12567 | |
| 12568 // inlined locking and unlocking | |
| 12569 | |
|
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12570 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
|
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12571 match(Set cr (FastLock object box)); |
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12572 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 12573 ins_cost(300); |
| 4777 | 12574 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
|
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12575 ins_encode %{ |
|
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12576 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters); |
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12577 %} |
|
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12578 ins_pipe(pipe_slow); |
|
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12579 %} |
|
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12580 |
|
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12581 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ |
|
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12582 match(Set cr (FastUnlock object box)); |
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12583 effect(TEMP tmp, USE_KILL box); |
| 0 | 12584 ins_cost(300); |
| 4777 | 12585 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
|
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12586 ins_encode %{ |
|
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12587 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register); |
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12588 %} |
|
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|
12589 ins_pipe(pipe_slow); |
| 0 | 12590 %} |
| 12591 | |
| 12592 | |
| 12593 | |
| 12594 // ============================================================================ | |
| 12595 // Safepoint Instruction | |
| 12596 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12597 match(SafePoint); | |
| 12598 effect(KILL cr); | |
| 12599 | |
| 12600 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12601 // On SPARC that might be acceptable as we can generate the address with | |
| 12602 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12603 // putting additional pressure on the index-0 in the D$. Because of | |
| 12604 // alignment (just like the situation at hand) the lower indices tend | |
| 12605 // to see more traffic. It'd be better to change the polling address | |
| 12606 // to offset 0 of the last $line in the polling page. | |
| 12607 | |
| 12608 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12609 ins_cost(125); | |
| 12610 size(6) ; | |
| 12611 ins_encode( Safepoint_Poll() ); | |
| 12612 ins_pipe( ialu_reg_mem ); | |
| 12613 %} | |
| 12614 | |
| 4950 | 12615 |
| 12616 // ============================================================================ | |
| 12617 // This name is KNOWN by the ADLC and cannot be changed. | |
| 12618 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 12619 // for this guy. | |
| 12620 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 12621 match(Set dst (ThreadLocal)); | |
| 12622 effect(DEF dst, KILL cr); | |
| 12623 | |
| 12624 format %{ "MOV $dst, Thread::current()" %} | |
| 12625 ins_encode %{ | |
| 12626 Register dstReg = as_Register($dst$$reg); | |
| 12627 __ get_thread(dstReg); | |
| 12628 %} | |
| 12629 ins_pipe( ialu_reg_fat ); | |
| 12630 %} | |
| 12631 | |
| 12632 | |
| 12633 | |
| 0 | 12634 //----------PEEPHOLE RULES----------------------------------------------------- |
| 12635 // These must follow all instruction definitions as they use the names | |
| 12636 // defined in the instructions definitions. | |
| 12637 // | |
| 605 | 12638 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12639 // |
| 12640 // peepconstraint %{ | |
| 12641 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12642 // [, ...] ); | |
| 12643 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12644 // | |
| 12645 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12646 // // provide an instruction_number.operand_name for each operand that appears | |
| 12647 // // in the replacement instruction's match rule | |
| 12648 // | |
| 12649 // ---------VM FLAGS--------------------------------------------------------- | |
| 12650 // | |
| 12651 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12652 // | |
| 12653 // Each peephole rule is given an identifying number starting with zero and | |
| 12654 // increasing by one in the order seen by the parser. An individual peephole | |
| 12655 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12656 // on the command-line. | |
| 12657 // | |
| 12658 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12659 // | |
| 12660 // Only match adjacent instructions in same basic block | |
| 12661 // Only equality constraints | |
| 12662 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 12663 // Only one replacement instruction | |
| 12664 // | |
| 12665 // ---------EXAMPLE---------------------------------------------------------- | |
| 12666 // | |
| 12667 // // pertinent parts of existing instructions in architecture description | |
|
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12668 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 12669 // match(Set dst (CopyI src)); |
| 12670 // %} | |
| 12671 // | |
|
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12672 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 12673 // match(Set dst (AddI dst src)); |
| 12674 // effect(KILL cr); | |
| 12675 // %} | |
| 12676 // | |
| 12677 // // Change (inc mov) to lea | |
| 12678 // peephole %{ | |
| 12679 // // increment preceeded by register-register move | |
| 12680 // peepmatch ( incI_eReg movI ); | |
| 12681 // // require that the destination register of the increment | |
| 12682 // // match the destination register of the move | |
| 12683 // peepconstraint ( 0.dst == 1.dst ); | |
| 12684 // // construct a replacement instruction that sets | |
| 12685 // // the destination to ( move's source register + one ) | |
| 12686 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12687 // %} | |
| 12688 // | |
| 12689 // Implementation no longer uses movX instructions since | |
| 12690 // machine-independent system no longer uses CopyX nodes. | |
| 12691 // | |
| 12692 // peephole %{ | |
| 12693 // peepmatch ( incI_eReg movI ); | |
| 12694 // peepconstraint ( 0.dst == 1.dst ); | |
| 12695 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12696 // %} | |
| 12697 // | |
| 12698 // peephole %{ | |
| 12699 // peepmatch ( decI_eReg movI ); | |
| 12700 // peepconstraint ( 0.dst == 1.dst ); | |
| 12701 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12702 // %} | |
| 12703 // | |
| 12704 // peephole %{ | |
| 12705 // peepmatch ( addI_eReg_imm movI ); | |
| 12706 // peepconstraint ( 0.dst == 1.dst ); | |
| 12707 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12708 // %} | |
| 12709 // | |
| 12710 // peephole %{ | |
| 12711 // peepmatch ( addP_eReg_imm movP ); | |
| 12712 // peepconstraint ( 0.dst == 1.dst ); | |
| 12713 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12714 // %} | |
| 12715 | |
| 12716 // // Change load of spilled value to only a spill | |
|
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12717 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 12718 // match(Set mem (StoreI mem src)); |
| 12719 // %} | |
| 12720 // | |
|
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12721 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 12722 // match(Set dst (LoadI mem)); |
| 12723 // %} | |
| 12724 // | |
| 12725 peephole %{ | |
| 12726 peepmatch ( loadI storeI ); | |
| 12727 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 12728 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 12729 %} | |
| 12730 | |
| 12731 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12732 // These must follow all instruction definitions as they use the names | |
| 12733 // defined in the instructions definitions. |