Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 20194:a0ea36509b7b
8046769: Set T family feature bit on Niagara systems
Reviewed-by: kvn, iveresov
author | mikael |
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date | Mon, 16 Jun 2014 16:27:41 -0700 |
parents | 78bbf4d43a14 |
children | 52b4284cb496 b20a35eae442 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
1972 | 27 #include "memory/resourceArea.hpp" |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_sparc.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
0 | 37 |
38 int VM_Version::_features = VM_Version::unknown_m; | |
39 const char* VM_Version::_features_str = ""; | |
40 | |
41 void VM_Version::initialize() { | |
42 _features = determine_features(); | |
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
45 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
46 | |
3854 | 47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; | |
50 | |
0 | 51 // Allocation prefetch settings |
3854 | 52 intx cache_line_size = prefetch_data_size(); |
0 | 53 if( cache_line_size > AllocatePrefetchStepSize ) |
54 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 55 |
56 assert(AllocatePrefetchLines > 0, "invalid value"); | |
57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
58 AllocatePrefetchLines = 3; | |
59 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
61 AllocateInstancePrefetchLines = 1; | |
0 | 62 |
63 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
64 AllocatePrefetchStyle = allocate_prefetch_style(); | |
65 | |
3854 | 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
67 (AllocatePrefetchDistance > 0), "invalid value"); | |
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || | |
69 (AllocatePrefetchDistance <= 0)) { | |
70 AllocatePrefetchDistance = AllocatePrefetchStepSize; | |
71 } | |
0 | 72 |
3839 | 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
74 warning("BIS instructions are not available on this CPU"); | |
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
76 } | |
77 | |
10997 | 78 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
79 | |
80 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); | |
81 if (ArraycopySrcPrefetchDistance >= 4096) | |
82 ArraycopySrcPrefetchDistance = 4064; | |
83 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); | |
84 if (ArraycopyDstPrefetchDistance >= 4096) | |
85 ArraycopyDstPrefetchDistance = 4064; | |
3903 | 86 |
0 | 87 UseSSE = 0; // Only on x86 and x64 |
88 | |
3854 | 89 _supports_cx8 = has_v9(); |
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90 _supports_atomic_getset4 = true; // swap instruction |
0 | 91 |
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92 // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
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93 // we have to take this check out of the 'is_niagara()' block below. |
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94 if (has_blk_init()) { |
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95 // When using CMS or G1, we cannot use memset() in BOT updates |
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96 // because the sun4v/CMT version in libc_psr uses BIS which |
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97 // exposes "phantom zeros" to concurrent readers. See 6948537. |
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98 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
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99 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
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100 } |
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101 // Issue a stern warning if the user has explicitly set |
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102 // UseMemSetInBOT (it is known to cause issues), but allow |
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103 // use for experimentation and debugging. |
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104 if (UseConcMarkSweepGC || UseG1GC) { |
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105 if (UseMemSetInBOT) { |
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106 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
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107 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
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108 " on sun4v; please understand that you are using at your own risk!"); |
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109 } |
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110 } |
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111 } |
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112 |
2080 | 113 if (is_niagara()) { |
0 | 114 // Indirect branch is the same cost as direct |
115 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
675 | 116 FLAG_SET_DEFAULT(UseInlineCaches, false); |
0 | 117 } |
2080 | 118 // Align loops on a single instruction boundary. |
119 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
120 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
121 } | |
113
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122 #ifdef _LP64 |
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123 // 32-bit oops don't make sense for the 64-bit VM on sparc |
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124 // since the 32-bit VM has the same registers and smaller objects. |
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125 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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126 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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127 #endif // _LP64 |
0 | 128 #ifdef COMPILER2 |
129 // Indirect branch is the same cost as direct | |
130 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
675 | 131 FLAG_SET_DEFAULT(UseJumpTables, true); |
0 | 132 } |
133 // Single-issue, so entry and loop tops are | |
134 // aligned on a single instruction boundary | |
135 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
675 | 136 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
0 | 137 } |
2080 | 138 if (is_niagara_plus()) { |
3854 | 139 if (has_blk_init() && UseTLAB && |
140 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | |
141 // Use BIS instruction for TLAB allocation prefetch. | |
142 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); | |
143 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { | |
144 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); | |
145 } | |
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146 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
3854 | 147 // Use smaller prefetch distance with BIS |
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148 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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149 } |
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150 } |
3854 | 151 if (is_T4()) { |
152 // Double number of prefetched cache lines on T4 | |
153 // since L2 cache line size is smaller (32 bytes). | |
154 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { | |
155 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); | |
156 } | |
157 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { | |
158 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); | |
159 } | |
160 } | |
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161 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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162 // Use different prefetch distance without BIS |
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163 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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164 } |
3854 | 165 if (AllocatePrefetchInstr == 1) { |
166 // Need a space at the end of TLAB for BIS since it | |
167 // will fault when accessing memory outside of heap. | |
168 | |
169 // +1 for rounding up to next cache line, +1 to be safe | |
170 int lines = AllocatePrefetchLines + 2; | |
171 int step_size = AllocatePrefetchStepSize; | |
172 int distance = AllocatePrefetchDistance; | |
173 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; | |
174 } | |
0 | 175 } |
176 #endif | |
177 } | |
178 | |
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179 // Use hardware population count instruction if available. |
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180 if (has_hardware_popc()) { |
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181 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
675 | 182 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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183 } |
3839 | 184 } else if (UsePopCountInstruction) { |
185 warning("POPC instruction is not available on this CPU"); | |
186 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
187 } | |
188 | |
189 // T4 and newer Sparc cpus have new compare and branch instruction. | |
190 if (has_cbcond()) { | |
191 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
192 FLAG_SET_DEFAULT(UseCBCond, true); | |
193 } | |
194 } else if (UseCBCond) { | |
195 warning("CBCOND instruction is not available on this CPU"); | |
196 FLAG_SET_DEFAULT(UseCBCond, false); | |
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197 } |
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198 |
3892 | 199 assert(BlockZeroingLowLimit > 0, "invalid value"); |
200 if (has_block_zeroing()) { | |
201 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { | |
202 FLAG_SET_DEFAULT(UseBlockZeroing, true); | |
203 } | |
204 } else if (UseBlockZeroing) { | |
205 warning("BIS zeroing instructions are not available on this CPU"); | |
206 FLAG_SET_DEFAULT(UseBlockZeroing, false); | |
207 } | |
208 | |
3903 | 209 assert(BlockCopyLowLimit > 0, "invalid value"); |
210 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache | |
211 if (FLAG_IS_DEFAULT(UseBlockCopy)) { | |
212 FLAG_SET_DEFAULT(UseBlockCopy, true); | |
213 } | |
214 } else if (UseBlockCopy) { | |
215 warning("BIS instructions are not available or expensive on this CPU"); | |
216 FLAG_SET_DEFAULT(UseBlockCopy, false); | |
217 } | |
218 | |
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219 #ifdef COMPILER2 |
3839 | 220 // T4 and newer Sparc cpus have fast RDPC. |
221 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
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222 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
3839 | 223 } |
224 | |
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225 // Currently not supported anywhere. |
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226 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
3851 | 227 |
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228 MaxVectorSize = 8; |
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229 |
3851 | 230 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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231 #endif |
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232 |
3851 | 233 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
234 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); | |
235 | |
0 | 236 char buf[512]; |
17670 | 237 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
3839 | 238 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
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239 (has_hardware_popc() ? ", popc" : ""), |
3839 | 240 (has_vis1() ? ", vis1" : ""), |
241 (has_vis2() ? ", vis2" : ""), | |
242 (has_vis3() ? ", vis3" : ""), | |
243 (has_blk_init() ? ", blk_init" : ""), | |
244 (has_cbcond() ? ", cbcond" : ""), | |
17670 | 245 (has_aes() ? ", aes" : ""), |
3839 | 246 (is_ultra3() ? ", ultra3" : ""), |
247 (is_sun4v() ? ", sun4v" : ""), | |
248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
249 (is_sparc64() ? ", sparc64" : ""), | |
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250 (!has_hardware_mul32() ? ", no-mul32" : ""), |
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251 (!has_hardware_div32() ? ", no-div32" : ""), |
0 | 252 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
253 | |
254 // buf is started with ", " or is empty | |
255 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
256 | |
3804 | 257 // UseVIS is set to the smallest of what hardware supports and what |
258 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
259 // older UltraSparc which do not support it. | |
260 if (UseVIS > 3) UseVIS=3; | |
261 if (UseVIS < 0) UseVIS=0; | |
262 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
263 UseVIS = MIN2((intx)2,UseVIS); | |
264 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
265 UseVIS = MIN2((intx)1,UseVIS); | |
266 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
267 UseVIS = 0; | |
268 | |
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269 // SPARC T4 and above should have support for AES instructions |
17670 | 270 if (has_aes()) { |
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271 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 |
17670 | 272 if (FLAG_IS_DEFAULT(UseAES)) { |
273 FLAG_SET_DEFAULT(UseAES, true); | |
274 } | |
275 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { | |
276 FLAG_SET_DEFAULT(UseAESIntrinsics, true); | |
277 } | |
278 // we disable both the AES flags if either of them is disabled on the command line | |
279 if (!UseAES || !UseAESIntrinsics) { | |
280 FLAG_SET_DEFAULT(UseAES, false); | |
281 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
282 } | |
283 } else { | |
284 if (UseAES || UseAESIntrinsics) { | |
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285 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
17670 | 286 if (UseAES) { |
287 FLAG_SET_DEFAULT(UseAES, false); | |
288 } | |
289 if (UseAESIntrinsics) { | |
290 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
291 } | |
292 } | |
293 } | |
294 } else if (UseAES || UseAESIntrinsics) { | |
295 warning("AES instructions are not available on this CPU"); | |
296 if (UseAES) { | |
297 FLAG_SET_DEFAULT(UseAES, false); | |
298 } | |
299 if (UseAESIntrinsics) { | |
300 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
301 } | |
302 } | |
303 | |
7587 | 304 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
305 (cache_line_size > ContendedPaddingWidth)) | |
306 ContendedPaddingWidth = cache_line_size; | |
307 | |
0 | 308 #ifndef PRODUCT |
309 if (PrintMiscellaneous && Verbose) { | |
3854 | 310 tty->print("Allocation"); |
0 | 311 if (AllocatePrefetchStyle <= 0) { |
3854 | 312 tty->print_cr(": no prefetching"); |
0 | 313 } else { |
3854 | 314 tty->print(" prefetching: "); |
315 if (AllocatePrefetchInstr == 0) { | |
316 tty->print("PREFETCH"); | |
317 } else if (AllocatePrefetchInstr == 1) { | |
318 tty->print("BIS"); | |
319 } | |
0 | 320 if (AllocatePrefetchLines > 1) { |
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321 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
0 | 322 } else { |
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323 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
0 | 324 } |
325 } | |
326 if (PrefetchCopyIntervalInBytes > 0) { | |
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327 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
0 | 328 } |
329 if (PrefetchScanIntervalInBytes > 0) { | |
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330 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
0 | 331 } |
332 if (PrefetchFieldsAhead > 0) { | |
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333 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
0 | 334 } |
7587 | 335 if (ContendedPaddingWidth > 0) { |
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336 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
7587 | 337 } |
0 | 338 } |
339 #endif // PRODUCT | |
340 } | |
341 | |
342 void VM_Version::print_features() { | |
343 tty->print_cr("Version:%s", cpu_features()); | |
344 } | |
345 | |
346 int VM_Version::determine_features() { | |
347 if (UseV8InstrsOnly) { | |
348 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
349 return generic_v8_m; | |
350 } | |
351 | |
352 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
353 | |
354 if (features == unknown_m) { | |
355 features = generic_v9_m; | |
356 warning("Cannot recognize SPARC version. Default to V9"); | |
357 } | |
358 | |
2080 | 359 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
360 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
361 if (is_T_family(features)) { | |
0 | 362 // Happy to accomodate... |
363 } else { | |
364 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
2080 | 365 features |= T_family_m; |
0 | 366 } |
367 } else { | |
2080 | 368 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
0 | 369 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
2080 | 370 features &= ~(T_family_m | T1_model_m); |
0 | 371 } else { |
372 // Happy to accomodate... | |
373 } | |
374 } | |
375 | |
376 return features; | |
377 } | |
378 | |
379 static int saved_features = 0; | |
380 | |
381 void VM_Version::allow_all() { | |
382 saved_features = _features; | |
383 _features = all_features_m; | |
384 } | |
385 | |
386 void VM_Version::revert() { | |
387 _features = saved_features; | |
388 } | |
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389 |
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390 unsigned int VM_Version::calc_parallel_worker_threads() { |
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391 unsigned int result; |
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392 if (is_M_series()) { |
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393 // for now, use same gc thread calculation for M-series as for niagara-plus |
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394 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
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395 result = nof_parallel_worker_threads(5, 16, 8); |
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396 } else if (is_niagara_plus()) { |
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397 result = nof_parallel_worker_threads(5, 16, 8); |
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398 } else { |
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399 result = nof_parallel_worker_threads(5, 8, 8); |
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400 } |
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401 return result; |
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402 } |