Mercurial > hg > graal-compiler
annotate src/share/vm/c1/c1_LIR.cpp @ 11080:b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
Summary: add intrinsics using new instruction to interpreter, C1, C2, for suitable x86; add test
Reviewed-by: kvn, twisti
| author | drchase |
|---|---|
| date | Tue, 02 Jul 2013 20:42:12 -0400 |
| parents | 87a6f2df28e2 |
| children | d13d7aba8c12 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "c1/c1_InstructionPrinter.hpp" | |
| 27 #include "c1/c1_LIR.hpp" | |
| 28 #include "c1/c1_LIRAssembler.hpp" | |
| 29 #include "c1/c1_ValueStack.hpp" | |
| 30 #include "ci/ciInstance.hpp" | |
| 31 #include "runtime/sharedRuntime.hpp" | |
| 0 | 32 |
| 33 Register LIR_OprDesc::as_register() const { | |
| 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); | |
| 35 } | |
| 36 | |
| 37 Register LIR_OprDesc::as_register_lo() const { | |
| 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); | |
| 39 } | |
| 40 | |
| 41 Register LIR_OprDesc::as_register_hi() const { | |
| 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); | |
| 43 } | |
| 44 | |
| 304 | 45 #if defined(X86) |
| 0 | 46 |
| 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { | |
| 48 return FrameMap::nr2xmmreg(xmm_regnr()); | |
| 49 } | |
| 50 | |
| 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { | |
| 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); | |
| 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); | |
| 54 } | |
| 55 | |
| 304 | 56 #endif // X86 |
| 0 | 57 |
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58 #if defined(SPARC) || defined(PPC) |
| 0 | 59 |
| 60 FloatRegister LIR_OprDesc::as_float_reg() const { | |
| 61 return FrameMap::nr2floatreg(fpu_regnr()); | |
| 62 } | |
| 63 | |
| 64 FloatRegister LIR_OprDesc::as_double_reg() const { | |
| 65 return FrameMap::nr2floatreg(fpu_regnrHi()); | |
| 66 } | |
| 67 | |
| 68 #endif | |
| 69 | |
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70 #ifdef ARM |
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71 |
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72 FloatRegister LIR_OprDesc::as_float_reg() const { |
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73 return as_FloatRegister(fpu_regnr()); |
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74 } |
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75 |
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76 FloatRegister LIR_OprDesc::as_double_reg() const { |
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77 return as_FloatRegister(fpu_regnrLo()); |
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78 } |
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79 |
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80 #endif |
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81 |
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82 |
| 0 | 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
| 84 | |
| 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { | |
| 86 ValueTag tag = type->tag(); | |
| 87 switch (tag) { | |
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88 case metaDataTag : { |
| 0 | 89 ClassConstant* c = type->as_ClassConstant(); |
| 90 if (c != NULL && !c->value()->is_loaded()) { | |
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91 return LIR_OprFact::metadataConst(NULL); |
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92 } else if (c != NULL) { |
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93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); |
| 0 | 94 } else { |
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95 MethodConstant* m = type->as_MethodConstant(); |
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96 assert (m != NULL, "not a class or a method?"); |
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97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); |
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98 } |
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99 } |
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100 case objectTag : { |
| 0 | 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); |
| 102 } | |
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103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
| 0 | 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
| 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); | |
| 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); | |
| 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); | |
| 304 | 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
| 0 | 109 } |
| 110 } | |
| 111 | |
| 112 | |
| 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { | |
| 114 switch (type->tag()) { | |
| 115 case objectTag: return LIR_OprFact::oopConst(NULL); | |
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116 case addressTag:return LIR_OprFact::addressConst(0); |
| 0 | 117 case intTag: return LIR_OprFact::intConst(0); |
| 118 case floatTag: return LIR_OprFact::floatConst(0.0); | |
| 119 case longTag: return LIR_OprFact::longConst(0); | |
| 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); | |
| 304 | 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
| 0 | 122 } |
| 123 return illegalOpr; | |
| 124 } | |
| 125 | |
| 126 | |
| 127 | |
| 128 //--------------------------------------------------- | |
| 129 | |
| 130 | |
| 131 LIR_Address::Scale LIR_Address::scale(BasicType type) { | |
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132 int elem_size = type2aelembytes(type); |
| 0 | 133 switch (elem_size) { |
| 134 case 1: return LIR_Address::times_1; | |
| 135 case 2: return LIR_Address::times_2; | |
| 136 case 4: return LIR_Address::times_4; | |
| 137 case 8: return LIR_Address::times_8; | |
| 138 } | |
| 139 ShouldNotReachHere(); | |
| 140 return LIR_Address::times_1; | |
| 141 } | |
| 142 | |
| 143 | |
| 144 #ifndef PRODUCT | |
| 145 void LIR_Address::verify() const { | |
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146 #if defined(SPARC) || defined(PPC) |
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147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
| 0 | 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
| 149 #endif | |
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150 #ifdef ARM |
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151 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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152 // Note: offsets higher than 4096 must not be rejected here. They can |
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153 // be handled by the back-end or will be rejected if not. |
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154 #endif |
| 0 | 155 #ifdef _LP64 |
| 156 assert(base()->is_cpu_register(), "wrong base operand"); | |
| 157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); | |
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158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
| 0 | 159 "wrong type for addresses"); |
| 160 #else | |
| 161 assert(base()->is_single_cpu(), "wrong base operand"); | |
| 162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); | |
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163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
| 0 | 164 "wrong type for addresses"); |
| 165 #endif | |
| 166 } | |
| 167 #endif | |
| 168 | |
| 169 | |
| 170 //--------------------------------------------------- | |
| 171 | |
| 172 char LIR_OprDesc::type_char(BasicType t) { | |
| 173 switch (t) { | |
| 174 case T_ARRAY: | |
| 175 t = T_OBJECT; | |
| 176 case T_BOOLEAN: | |
| 177 case T_CHAR: | |
| 178 case T_FLOAT: | |
| 179 case T_DOUBLE: | |
| 180 case T_BYTE: | |
| 181 case T_SHORT: | |
| 182 case T_INT: | |
| 183 case T_LONG: | |
| 184 case T_OBJECT: | |
| 185 case T_ADDRESS: | |
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186 case T_METADATA: |
| 0 | 187 case T_VOID: |
| 188 return ::type2char(t); | |
| 189 | |
| 190 case T_ILLEGAL: | |
| 191 return '?'; | |
| 192 | |
| 193 default: | |
| 194 ShouldNotReachHere(); | |
| 304 | 195 return '?'; |
| 0 | 196 } |
| 197 } | |
| 198 | |
| 199 #ifndef PRODUCT | |
| 200 void LIR_OprDesc::validate_type() const { | |
| 201 | |
| 202 #ifdef ASSERT | |
| 203 if (!is_pointer() && !is_illegal()) { | |
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204 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 |
| 0 | 205 switch (as_BasicType(type_field())) { |
| 206 case T_LONG: | |
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207 assert((kindfield == cpu_register || kindfield == stack_value) && |
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208 size_field() == double_size, "must match"); |
| 0 | 209 break; |
| 210 case T_FLOAT: | |
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211 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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212 assert((kindfield == fpu_register || kindfield == stack_value |
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213 ARM_ONLY(|| kindfield == cpu_register) |
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214 PPC_ONLY(|| kindfield == cpu_register) ) && |
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215 size_field() == single_size, "must match"); |
| 0 | 216 break; |
| 217 case T_DOUBLE: | |
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218 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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219 assert((kindfield == fpu_register || kindfield == stack_value |
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220 ARM_ONLY(|| kindfield == cpu_register) |
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221 PPC_ONLY(|| kindfield == cpu_register) ) && |
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222 size_field() == double_size, "must match"); |
| 0 | 223 break; |
| 224 case T_BOOLEAN: | |
| 225 case T_CHAR: | |
| 226 case T_BYTE: | |
| 227 case T_SHORT: | |
| 228 case T_INT: | |
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229 case T_ADDRESS: |
| 0 | 230 case T_OBJECT: |
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231 case T_METADATA: |
| 0 | 232 case T_ARRAY: |
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233 assert((kindfield == cpu_register || kindfield == stack_value) && |
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234 size_field() == single_size, "must match"); |
| 0 | 235 break; |
| 236 | |
| 237 case T_ILLEGAL: | |
| 238 // XXX TKR also means unknown right now | |
| 239 // assert(is_illegal(), "must match"); | |
| 240 break; | |
| 241 | |
| 242 default: | |
| 243 ShouldNotReachHere(); | |
| 244 } | |
| 245 } | |
| 246 #endif | |
| 247 | |
| 248 } | |
| 249 #endif // PRODUCT | |
| 250 | |
| 251 | |
| 252 bool LIR_OprDesc::is_oop() const { | |
| 253 if (is_pointer()) { | |
| 254 return pointer()->is_oop_pointer(); | |
| 255 } else { | |
| 256 OprType t= type_field(); | |
| 257 assert(t != unknown_type, "not set"); | |
| 258 return t == object_type; | |
| 259 } | |
| 260 } | |
| 261 | |
| 262 | |
| 263 | |
| 264 void LIR_Op2::verify() const { | |
| 265 #ifdef ASSERT | |
| 266 switch (code()) { | |
| 267 case lir_cmove: | |
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268 case lir_xchg: |
| 0 | 269 break; |
| 270 | |
| 271 default: | |
| 272 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), | |
| 273 "can't produce oops from arith"); | |
| 274 } | |
| 275 | |
| 276 if (TwoOperandLIRForm) { | |
| 277 switch (code()) { | |
| 278 case lir_add: | |
| 279 case lir_sub: | |
| 280 case lir_mul: | |
| 281 case lir_mul_strictfp: | |
| 282 case lir_div: | |
| 283 case lir_div_strictfp: | |
| 284 case lir_rem: | |
| 285 case lir_logic_and: | |
| 286 case lir_logic_or: | |
| 287 case lir_logic_xor: | |
| 288 case lir_shl: | |
| 289 case lir_shr: | |
| 290 assert(in_opr1() == result_opr(), "opr1 and result must match"); | |
| 291 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
| 292 break; | |
| 293 | |
| 294 // special handling for lir_ushr because of write barriers | |
| 295 case lir_ushr: | |
| 296 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); | |
| 297 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
| 298 break; | |
| 299 | |
| 300 } | |
| 301 } | |
| 302 #endif | |
| 303 } | |
| 304 | |
| 305 | |
| 306 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) | |
| 307 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 308 , _cond(cond) | |
| 309 , _type(type) | |
| 310 , _label(block->label()) | |
| 311 , _block(block) | |
| 312 , _ublock(NULL) | |
| 313 , _stub(NULL) { | |
| 314 } | |
| 315 | |
| 316 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : | |
| 317 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 318 , _cond(cond) | |
| 319 , _type(type) | |
| 320 , _label(stub->entry()) | |
| 321 , _block(NULL) | |
| 322 , _ublock(NULL) | |
| 323 , _stub(stub) { | |
| 324 } | |
| 325 | |
| 326 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) | |
| 327 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 328 , _cond(cond) | |
| 329 , _type(type) | |
| 330 , _label(block->label()) | |
| 331 , _block(block) | |
| 332 , _ublock(ublock) | |
| 333 , _stub(NULL) | |
| 334 { | |
| 335 } | |
| 336 | |
| 337 void LIR_OpBranch::change_block(BlockBegin* b) { | |
| 338 assert(_block != NULL, "must have old block"); | |
| 339 assert(_block->label() == label(), "must be equal"); | |
| 340 | |
| 341 _block = b; | |
| 342 _label = b->label(); | |
| 343 } | |
| 344 | |
| 345 void LIR_OpBranch::change_ublock(BlockBegin* b) { | |
| 346 assert(_ublock != NULL, "must have old block"); | |
| 347 _ublock = b; | |
| 348 } | |
| 349 | |
| 350 void LIR_OpBranch::negate_cond() { | |
| 351 switch (_cond) { | |
| 352 case lir_cond_equal: _cond = lir_cond_notEqual; break; | |
| 353 case lir_cond_notEqual: _cond = lir_cond_equal; break; | |
| 354 case lir_cond_less: _cond = lir_cond_greaterEqual; break; | |
| 355 case lir_cond_lessEqual: _cond = lir_cond_greater; break; | |
| 356 case lir_cond_greaterEqual: _cond = lir_cond_less; break; | |
| 357 case lir_cond_greater: _cond = lir_cond_lessEqual; break; | |
| 358 default: ShouldNotReachHere(); | |
| 359 } | |
| 360 } | |
| 361 | |
| 362 | |
| 363 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
| 364 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, | |
| 365 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, | |
| 1783 | 366 CodeStub* stub) |
| 367 | |
| 0 | 368 : LIR_Op(code, result, NULL) |
| 369 , _object(object) | |
| 370 , _array(LIR_OprFact::illegalOpr) | |
| 371 , _klass(klass) | |
| 372 , _tmp1(tmp1) | |
| 373 , _tmp2(tmp2) | |
| 374 , _tmp3(tmp3) | |
| 375 , _fast_check(fast_check) | |
| 376 , _stub(stub) | |
| 377 , _info_for_patch(info_for_patch) | |
| 378 , _info_for_exception(info_for_exception) | |
| 1783 | 379 , _profiled_method(NULL) |
| 380 , _profiled_bci(-1) | |
| 381 , _should_profile(false) | |
| 382 { | |
| 0 | 383 if (code == lir_checkcast) { |
| 384 assert(info_for_exception != NULL, "checkcast throws exceptions"); | |
| 385 } else if (code == lir_instanceof) { | |
| 386 assert(info_for_exception == NULL, "instanceof throws no exceptions"); | |
| 387 } else { | |
| 388 ShouldNotReachHere(); | |
| 389 } | |
| 390 } | |
| 391 | |
| 392 | |
| 393 | |
| 1783 | 394 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) |
| 0 | 395 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) |
| 396 , _object(object) | |
| 397 , _array(array) | |
| 398 , _klass(NULL) | |
| 399 , _tmp1(tmp1) | |
| 400 , _tmp2(tmp2) | |
| 401 , _tmp3(tmp3) | |
| 402 , _fast_check(false) | |
| 403 , _stub(NULL) | |
| 404 , _info_for_patch(NULL) | |
| 405 , _info_for_exception(info_for_exception) | |
| 1783 | 406 , _profiled_method(NULL) |
| 407 , _profiled_bci(-1) | |
| 408 , _should_profile(false) | |
| 409 { | |
| 0 | 410 if (code == lir_store_check) { |
|
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411 _stub = new ArrayStoreExceptionStub(object, info_for_exception); |
| 0 | 412 assert(info_for_exception != NULL, "store_check throws exceptions"); |
| 413 } else { | |
| 414 ShouldNotReachHere(); | |
| 415 } | |
| 416 } | |
| 417 | |
| 418 | |
| 419 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, | |
| 420 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) | |
| 421 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) | |
| 422 , _tmp(tmp) | |
| 423 , _src(src) | |
| 424 , _src_pos(src_pos) | |
| 425 , _dst(dst) | |
| 426 , _dst_pos(dst_pos) | |
| 427 , _flags(flags) | |
| 428 , _expected_type(expected_type) | |
| 429 , _length(length) { | |
| 430 _stub = new ArrayCopyStub(this); | |
| 431 } | |
| 432 | |
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433 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) |
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434 : LIR_Op(lir_updatecrc32, res, NULL) |
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435 , _crc(crc) |
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436 , _val(val) { |
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437 } |
| 0 | 438 |
| 439 //-------------------verify-------------------------- | |
| 440 | |
| 441 void LIR_Op1::verify() const { | |
| 442 switch(code()) { | |
| 443 case lir_move: | |
| 444 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); | |
| 445 break; | |
| 446 case lir_null_check: | |
| 447 assert(in_opr()->is_register(), "must be"); | |
| 448 break; | |
| 449 case lir_return: | |
| 450 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); | |
| 451 break; | |
| 452 } | |
| 453 } | |
| 454 | |
| 455 void LIR_OpRTCall::verify() const { | |
| 456 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); | |
| 457 } | |
| 458 | |
| 459 //-------------------visits-------------------------- | |
| 460 | |
| 461 // complete rework of LIR instruction visitor. | |
| 462 // The virtual calls for each instruction type is replaced by a big | |
| 463 // switch that adds the operands for each instruction | |
| 464 | |
| 465 void LIR_OpVisitState::visit(LIR_Op* op) { | |
| 466 // copy information from the LIR_Op | |
| 467 reset(); | |
| 468 set_op(op); | |
| 469 | |
| 470 switch (op->code()) { | |
| 471 | |
| 472 // LIR_Op0 | |
| 473 case lir_word_align: // result and info always invalid | |
| 474 case lir_backwardbranch_target: // result and info always invalid | |
| 475 case lir_build_frame: // result and info always invalid | |
| 476 case lir_fpop_raw: // result and info always invalid | |
| 477 case lir_24bit_FPU: // result and info always invalid | |
| 478 case lir_reset_FPU: // result and info always invalid | |
| 479 case lir_breakpoint: // result and info always invalid | |
| 480 case lir_membar: // result and info always invalid | |
| 481 case lir_membar_acquire: // result and info always invalid | |
| 482 case lir_membar_release: // result and info always invalid | |
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483 case lir_membar_loadload: // result and info always invalid |
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484 case lir_membar_storestore: // result and info always invalid |
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485 case lir_membar_loadstore: // result and info always invalid |
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486 case lir_membar_storeload: // result and info always invalid |
| 0 | 487 { |
| 488 assert(op->as_Op0() != NULL, "must be"); | |
| 489 assert(op->_info == NULL, "info not used by this instruction"); | |
| 490 assert(op->_result->is_illegal(), "not used"); | |
| 491 break; | |
| 492 } | |
| 493 | |
| 494 case lir_nop: // may have info, result always invalid | |
| 495 case lir_std_entry: // may have result, info always invalid | |
| 496 case lir_osr_entry: // may have result, info always invalid | |
| 497 case lir_get_thread: // may have result, info always invalid | |
| 498 { | |
| 499 assert(op->as_Op0() != NULL, "must be"); | |
| 500 if (op->_info != NULL) do_info(op->_info); | |
| 501 if (op->_result->is_valid()) do_output(op->_result); | |
| 502 break; | |
| 503 } | |
| 504 | |
| 505 | |
| 506 // LIR_OpLabel | |
| 507 case lir_label: // result and info always invalid | |
| 508 { | |
| 509 assert(op->as_OpLabel() != NULL, "must be"); | |
| 510 assert(op->_info == NULL, "info not used by this instruction"); | |
| 511 assert(op->_result->is_illegal(), "not used"); | |
| 512 break; | |
| 513 } | |
| 514 | |
| 515 | |
| 516 // LIR_Op1 | |
| 517 case lir_fxch: // input always valid, result and info always invalid | |
| 518 case lir_fld: // input always valid, result and info always invalid | |
| 519 case lir_ffree: // input always valid, result and info always invalid | |
| 520 case lir_push: // input always valid, result and info always invalid | |
| 521 case lir_pop: // input always valid, result and info always invalid | |
| 522 case lir_return: // input always valid, result and info always invalid | |
| 523 case lir_leal: // input and result always valid, info always invalid | |
| 524 case lir_neg: // input and result always valid, info always invalid | |
| 525 case lir_monaddr: // input and result always valid, info always invalid | |
| 526 case lir_null_check: // input and info always valid, result always invalid | |
| 527 case lir_move: // input and result always valid, may have info | |
| 1783 | 528 case lir_pack64: // input and result always valid |
| 529 case lir_unpack64: // input and result always valid | |
| 0 | 530 case lir_prefetchr: // input always valid, result and info always invalid |
| 531 case lir_prefetchw: // input always valid, result and info always invalid | |
| 532 { | |
| 533 assert(op->as_Op1() != NULL, "must be"); | |
| 534 LIR_Op1* op1 = (LIR_Op1*)op; | |
| 535 | |
| 536 if (op1->_info) do_info(op1->_info); | |
| 537 if (op1->_opr->is_valid()) do_input(op1->_opr); | |
| 538 if (op1->_result->is_valid()) do_output(op1->_result); | |
| 539 | |
| 540 break; | |
| 541 } | |
| 542 | |
| 543 case lir_safepoint: | |
| 544 { | |
| 545 assert(op->as_Op1() != NULL, "must be"); | |
| 546 LIR_Op1* op1 = (LIR_Op1*)op; | |
| 547 | |
| 548 assert(op1->_info != NULL, ""); do_info(op1->_info); | |
| 549 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register | |
| 550 assert(op1->_result->is_illegal(), "safepoint does not produce value"); | |
| 551 | |
| 552 break; | |
| 553 } | |
| 554 | |
| 555 // LIR_OpConvert; | |
| 556 case lir_convert: // input and result always valid, info always invalid | |
| 557 { | |
| 558 assert(op->as_OpConvert() != NULL, "must be"); | |
| 559 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; | |
| 560 | |
| 561 assert(opConvert->_info == NULL, "must be"); | |
| 562 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); | |
| 563 if (opConvert->_result->is_valid()) do_output(opConvert->_result); | |
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564 #ifdef PPC |
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565 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
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566 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
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567 #endif |
| 0 | 568 do_stub(opConvert->_stub); |
| 569 | |
| 570 break; | |
| 571 } | |
| 572 | |
| 573 // LIR_OpBranch; | |
| 574 case lir_branch: // may have info, input and result register always invalid | |
| 575 case lir_cond_float_branch: // may have info, input and result register always invalid | |
| 576 { | |
| 577 assert(op->as_OpBranch() != NULL, "must be"); | |
| 578 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; | |
| 579 | |
| 580 if (opBranch->_info != NULL) do_info(opBranch->_info); | |
| 581 assert(opBranch->_result->is_illegal(), "not used"); | |
| 582 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); | |
| 583 | |
| 584 break; | |
| 585 } | |
| 586 | |
| 587 | |
| 588 // LIR_OpAllocObj | |
| 589 case lir_alloc_object: | |
| 590 { | |
| 591 assert(op->as_OpAllocObj() != NULL, "must be"); | |
| 592 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; | |
| 593 | |
| 594 if (opAllocObj->_info) do_info(opAllocObj->_info); | |
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595 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
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596 do_temp(opAllocObj->_opr); |
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597 } |
| 0 | 598 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
| 599 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); | |
| 600 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); | |
| 601 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); | |
| 602 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); | |
| 603 do_stub(opAllocObj->_stub); | |
| 604 break; | |
| 605 } | |
| 606 | |
| 607 | |
| 608 // LIR_OpRoundFP; | |
| 609 case lir_roundfp: { | |
| 610 assert(op->as_OpRoundFP() != NULL, "must be"); | |
| 611 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; | |
| 612 | |
| 613 assert(op->_info == NULL, "info not used by this instruction"); | |
| 614 assert(opRoundFP->_tmp->is_illegal(), "not used"); | |
| 615 do_input(opRoundFP->_opr); | |
| 616 do_output(opRoundFP->_result); | |
| 617 | |
| 618 break; | |
| 619 } | |
| 620 | |
| 621 | |
| 622 // LIR_Op2 | |
| 623 case lir_cmp: | |
| 624 case lir_cmp_l2i: | |
| 625 case lir_ucmp_fd2i: | |
| 626 case lir_cmp_fd2i: | |
| 627 case lir_add: | |
| 628 case lir_sub: | |
| 629 case lir_mul: | |
| 630 case lir_div: | |
| 631 case lir_rem: | |
| 632 case lir_sqrt: | |
| 633 case lir_abs: | |
| 634 case lir_logic_and: | |
| 635 case lir_logic_or: | |
| 636 case lir_logic_xor: | |
| 637 case lir_shl: | |
| 638 case lir_shr: | |
| 639 case lir_ushr: | |
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640 case lir_xadd: |
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641 case lir_xchg: |
| 8860 | 642 case lir_assert: |
| 0 | 643 { |
| 644 assert(op->as_Op2() != NULL, "must be"); | |
| 645 LIR_Op2* op2 = (LIR_Op2*)op; | |
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646 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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647 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
| 0 | 648 |
| 649 if (op2->_info) do_info(op2->_info); | |
| 650 if (op2->_opr1->is_valid()) do_input(op2->_opr1); | |
| 651 if (op2->_opr2->is_valid()) do_input(op2->_opr2); | |
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652 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
| 0 | 653 if (op2->_result->is_valid()) do_output(op2->_result); |
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654 if (op->code() == lir_xchg || op->code() == lir_xadd) { |
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655 // on ARM and PPC, return value is loaded first so could |
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656 // destroy inputs. On other platforms that implement those |
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657 // (x86, sparc), the extra constrainsts are harmless. |
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658 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
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659 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
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660 } |
| 0 | 661 |
| 662 break; | |
| 663 } | |
| 664 | |
| 665 // special handling for cmove: right input operand must not be equal | |
| 666 // to the result operand, otherwise the backend fails | |
| 667 case lir_cmove: | |
| 668 { | |
| 669 assert(op->as_Op2() != NULL, "must be"); | |
| 670 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 671 | |
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672 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && |
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673 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
| 0 | 674 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); |
| 675 | |
| 676 do_input(op2->_opr1); | |
| 677 do_input(op2->_opr2); | |
| 678 do_temp(op2->_opr2); | |
| 679 do_output(op2->_result); | |
| 680 | |
| 681 break; | |
| 682 } | |
| 683 | |
| 684 // vspecial handling for strict operations: register input operands | |
| 685 // as temp to guarantee that they do not overlap with other | |
| 686 // registers | |
| 687 case lir_mul_strictfp: | |
| 688 case lir_div_strictfp: | |
| 689 { | |
| 690 assert(op->as_Op2() != NULL, "must be"); | |
| 691 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 692 | |
| 693 assert(op2->_info == NULL, "not used"); | |
| 694 assert(op2->_opr1->is_valid(), "used"); | |
| 695 assert(op2->_opr2->is_valid(), "used"); | |
| 696 assert(op2->_result->is_valid(), "used"); | |
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697 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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698 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
| 0 | 699 |
| 700 do_input(op2->_opr1); do_temp(op2->_opr1); | |
| 701 do_input(op2->_opr2); do_temp(op2->_opr2); | |
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702 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
| 0 | 703 do_output(op2->_result); |
| 704 | |
| 705 break; | |
| 706 } | |
| 707 | |
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708 case lir_throw: { |
| 0 | 709 assert(op->as_Op2() != NULL, "must be"); |
| 710 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 711 | |
| 712 if (op2->_info) do_info(op2->_info); | |
| 713 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); | |
| 714 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter | |
| 715 assert(op2->_result->is_illegal(), "no result"); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
716 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
717 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
| 0 | 718 |
| 719 break; | |
| 720 } | |
| 721 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
722 case lir_unwind: { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
723 assert(op->as_Op1() != NULL, "must be"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
724 LIR_Op1* op1 = (LIR_Op1*)op; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
725 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
726 assert(op1->_info == NULL, "no info"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
727 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
728 assert(op1->_result->is_illegal(), "no result"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
729 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
730 break; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
731 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1301
diff
changeset
|
732 |
| 0 | 733 |
| 734 case lir_tan: | |
| 735 case lir_sin: | |
|
953
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
736 case lir_cos: |
|
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
737 case lir_log: |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
738 case lir_log10: |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
739 case lir_exp: { |
| 0 | 740 assert(op->as_Op2() != NULL, "must be"); |
| 741 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 742 | |
|
953
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
743 // On x86 tan/sin/cos need two temporary fpu stack slots and |
|
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
744 // log/log10 need one so handle opr2 and tmp as temp inputs. |
|
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
745 // Register input operand as temp to guarantee that it doesn't |
|
ff1a29907b6c
6855215: Calculation error (NaN) after about 1500 calculations
never
parents:
304
diff
changeset
|
746 // overlap with the input. |
| 0 | 747 assert(op2->_info == NULL, "not used"); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
748 assert(op2->_tmp5->is_illegal(), "not used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
749 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
750 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
751 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); |
| 0 | 752 assert(op2->_opr1->is_valid(), "used"); |
| 753 do_input(op2->_opr1); do_temp(op2->_opr1); | |
| 754 | |
| 755 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
756 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
757 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
758 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
759 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); |
| 0 | 760 if (op2->_result->is_valid()) do_output(op2->_result); |
| 761 | |
| 762 break; | |
| 763 } | |
| 764 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
765 case lir_pow: { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
766 assert(op->as_Op2() != NULL, "must be"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
767 LIR_Op2* op2 = (LIR_Op2*)op; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
768 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
769 // On x86 pow needs two temporary fpu stack slots: tmp1 and |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
770 // tmp2. Register input operands as temps to guarantee that it |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
771 // doesn't overlap with the temporary slots. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
772 assert(op2->_info == NULL, "not used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
773 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
774 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
775 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
776 assert(op2->_result->is_valid(), "used"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
777 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
778 do_input(op2->_opr1); do_temp(op2->_opr1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
779 do_input(op2->_opr2); do_temp(op2->_opr2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
780 do_temp(op2->_tmp1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
781 do_temp(op2->_tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
782 do_temp(op2->_tmp3); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
783 do_temp(op2->_tmp4); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
784 do_temp(op2->_tmp5); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
785 do_output(op2->_result); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
786 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
787 break; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
4966
diff
changeset
|
788 } |
| 0 | 789 |
| 790 // LIR_Op3 | |
| 791 case lir_idiv: | |
| 792 case lir_irem: { | |
| 793 assert(op->as_Op3() != NULL, "must be"); | |
| 794 LIR_Op3* op3= (LIR_Op3*)op; | |
| 795 | |
| 796 if (op3->_info) do_info(op3->_info); | |
| 797 if (op3->_opr1->is_valid()) do_input(op3->_opr1); | |
| 798 | |
| 799 // second operand is input and temp, so ensure that second operand | |
| 800 // and third operand get not the same register | |
| 801 if (op3->_opr2->is_valid()) do_input(op3->_opr2); | |
| 802 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); | |
| 803 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); | |
| 804 | |
| 805 if (op3->_result->is_valid()) do_output(op3->_result); | |
| 806 | |
| 807 break; | |
| 808 } | |
| 809 | |
| 810 | |
| 811 // LIR_OpJavaCall | |
| 812 case lir_static_call: | |
| 813 case lir_optvirtual_call: | |
| 814 case lir_icvirtual_call: | |
| 1295 | 815 case lir_virtual_call: |
| 816 case lir_dynamic_call: { | |
| 817 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); | |
| 818 assert(opJavaCall != NULL, "must be"); | |
| 0 | 819 |
| 820 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); | |
| 821 | |
| 822 // only visit register parameters | |
| 823 int n = opJavaCall->_arguments->length(); | |
|
8084
84a926fe53d0
8005722: Assert in c1_LIR.hpp incorrect wrt to number of register operands
bpittore
parents:
7623
diff
changeset
|
824 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { |
| 0 | 825 if (!opJavaCall->_arguments->at(i)->is_pointer()) { |
| 826 do_input(*opJavaCall->_arguments->adr_at(i)); | |
| 827 } | |
| 828 } | |
| 829 | |
| 830 if (opJavaCall->_info) do_info(opJavaCall->_info); | |
| 1564 | 831 if (opJavaCall->is_method_handle_invoke()) { |
| 832 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); | |
| 833 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); | |
| 834 } | |
| 0 | 835 do_call(); |
| 836 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); | |
| 837 | |
| 838 break; | |
| 839 } | |
| 840 | |
| 841 | |
| 842 // LIR_OpRTCall | |
| 843 case lir_rtcall: { | |
| 844 assert(op->as_OpRTCall() != NULL, "must be"); | |
| 845 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; | |
| 846 | |
| 847 // only visit register parameters | |
| 848 int n = opRTCall->_arguments->length(); | |
| 849 for (int i = 0; i < n; i++) { | |
| 850 if (!opRTCall->_arguments->at(i)->is_pointer()) { | |
| 851 do_input(*opRTCall->_arguments->adr_at(i)); | |
| 852 } | |
| 853 } | |
| 854 if (opRTCall->_info) do_info(opRTCall->_info); | |
| 855 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); | |
| 856 do_call(); | |
| 857 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); | |
| 858 | |
| 859 break; | |
| 860 } | |
| 861 | |
| 862 | |
| 863 // LIR_OpArrayCopy | |
| 864 case lir_arraycopy: { | |
| 865 assert(op->as_OpArrayCopy() != NULL, "must be"); | |
| 866 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; | |
| 867 | |
| 868 assert(opArrayCopy->_result->is_illegal(), "unused"); | |
| 869 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); | |
| 870 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); | |
| 871 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); | |
| 872 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); | |
| 873 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); | |
| 874 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); | |
| 875 if (opArrayCopy->_info) do_info(opArrayCopy->_info); | |
| 876 | |
| 877 // the implementation of arraycopy always has a call into the runtime | |
| 878 do_call(); | |
| 879 | |
| 880 break; | |
| 881 } | |
| 882 | |
| 883 | |
|
11080
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
884 // LIR_OpUpdateCRC32 |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
885 case lir_updatecrc32: { |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
886 assert(op->as_OpUpdateCRC32() != NULL, "must be"); |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
887 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
888 |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
889 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
890 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
891 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
892 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
893 |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
894 break; |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
895 } |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
896 |
|
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
11004
diff
changeset
|
897 |
| 0 | 898 // LIR_OpLock |
| 899 case lir_lock: | |
| 900 case lir_unlock: { | |
| 901 assert(op->as_OpLock() != NULL, "must be"); | |
| 902 LIR_OpLock* opLock = (LIR_OpLock*)op; | |
| 903 | |
| 904 if (opLock->_info) do_info(opLock->_info); | |
| 905 | |
| 906 // TODO: check if these operands really have to be temp | |
| 907 // (or if input is sufficient). This may have influence on the oop map! | |
| 908 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); | |
| 909 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); | |
| 910 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); | |
| 911 | |
| 912 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); | |
| 913 assert(opLock->_result->is_illegal(), "unused"); | |
| 914 | |
| 915 do_stub(opLock->_stub); | |
| 916 | |
| 917 break; | |
| 918 } | |
| 919 | |
| 920 | |
| 921 // LIR_OpDelay | |
| 922 case lir_delay_slot: { | |
| 923 assert(op->as_OpDelay() != NULL, "must be"); | |
| 924 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; | |
| 925 | |
| 926 visit(opDelay->delay_op()); | |
| 927 break; | |
| 928 } | |
| 929 | |
| 930 // LIR_OpTypeCheck | |
| 931 case lir_instanceof: | |
| 932 case lir_checkcast: | |
| 933 case lir_store_check: { | |
| 934 assert(op->as_OpTypeCheck() != NULL, "must be"); | |
| 935 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; | |
| 936 | |
| 937 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); | |
| 938 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); | |
| 939 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); | |
|
4765
b642b49f9738
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
3957
diff
changeset
|
940 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { |
|
b642b49f9738
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
3957
diff
changeset
|
941 do_temp(opTypeCheck->_object); |
|
b642b49f9738
7123253: C1: in store check code, usage of registers may be incorrect
roland
parents:
3957
diff
changeset
|
942 } |
| 0 | 943 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); |
| 944 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); | |
| 945 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); | |
| 946 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); | |
| 947 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); | |
| 948 do_stub(opTypeCheck->_stub); | |
| 949 break; | |
| 950 } | |
| 951 | |
| 952 // LIR_OpCompareAndSwap | |
| 953 case lir_cas_long: | |
| 954 case lir_cas_obj: | |
| 955 case lir_cas_int: { | |
| 956 assert(op->as_OpCompareAndSwap() != NULL, "must be"); | |
| 957 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; | |
| 958 | |
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959 assert(opCompareAndSwap->_addr->is_valid(), "used"); |
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960 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
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961 assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
| 0 | 962 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
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963 do_input(opCompareAndSwap->_addr); |
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964 do_temp(opCompareAndSwap->_addr); |
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965 do_input(opCompareAndSwap->_cmp_value); |
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966 do_temp(opCompareAndSwap->_cmp_value); |
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967 do_input(opCompareAndSwap->_new_value); |
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968 do_temp(opCompareAndSwap->_new_value); |
| 0 | 969 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
| 970 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); | |
| 971 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); | |
| 972 | |
| 973 break; | |
| 974 } | |
| 975 | |
| 976 | |
| 977 // LIR_OpAllocArray; | |
| 978 case lir_alloc_array: { | |
| 979 assert(op->as_OpAllocArray() != NULL, "must be"); | |
| 980 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; | |
| 981 | |
| 982 if (opAllocArray->_info) do_info(opAllocArray->_info); | |
| 983 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); | |
| 984 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); | |
| 985 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); | |
| 986 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); | |
| 987 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); | |
| 988 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); | |
| 989 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); | |
| 990 do_stub(opAllocArray->_stub); | |
| 991 break; | |
| 992 } | |
| 993 | |
| 994 // LIR_OpProfileCall: | |
| 995 case lir_profile_call: { | |
| 996 assert(op->as_OpProfileCall() != NULL, "must be"); | |
| 997 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; | |
| 998 | |
| 999 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); | |
| 1000 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); | |
| 1001 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); | |
| 1002 break; | |
| 1003 } | |
| 1004 default: | |
| 1005 ShouldNotReachHere(); | |
| 1006 } | |
| 1007 } | |
| 1008 | |
| 1009 | |
| 1010 void LIR_OpVisitState::do_stub(CodeStub* stub) { | |
| 1011 if (stub != NULL) { | |
| 1012 stub->visit(this); | |
| 1013 } | |
| 1014 } | |
| 1015 | |
| 1016 XHandlers* LIR_OpVisitState::all_xhandler() { | |
| 1017 XHandlers* result = NULL; | |
| 1018 | |
| 1019 int i; | |
| 1020 for (i = 0; i < info_count(); i++) { | |
| 1021 if (info_at(i)->exception_handlers() != NULL) { | |
| 1022 result = info_at(i)->exception_handlers(); | |
| 1023 break; | |
| 1024 } | |
| 1025 } | |
| 1026 | |
| 1027 #ifdef ASSERT | |
| 1028 for (i = 0; i < info_count(); i++) { | |
| 1029 assert(info_at(i)->exception_handlers() == NULL || | |
| 1030 info_at(i)->exception_handlers() == result, | |
| 1031 "only one xhandler list allowed per LIR-operation"); | |
| 1032 } | |
| 1033 #endif | |
| 1034 | |
| 1035 if (result != NULL) { | |
| 1036 return result; | |
| 1037 } else { | |
| 1038 return new XHandlers(); | |
| 1039 } | |
| 1040 | |
| 1041 return result; | |
| 1042 } | |
| 1043 | |
| 1044 | |
| 1045 #ifdef ASSERT | |
| 1046 bool LIR_OpVisitState::no_operands(LIR_Op* op) { | |
| 1047 visit(op); | |
| 1048 | |
| 1049 return opr_count(inputMode) == 0 && | |
| 1050 opr_count(outputMode) == 0 && | |
| 1051 opr_count(tempMode) == 0 && | |
| 1052 info_count() == 0 && | |
| 1053 !has_call() && | |
| 1054 !has_slow_case(); | |
| 1055 } | |
| 1056 #endif | |
| 1057 | |
| 1058 //--------------------------------------------------- | |
| 1059 | |
| 1060 | |
| 1061 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { | |
| 1062 masm->emit_call(this); | |
| 1063 } | |
| 1064 | |
| 1065 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { | |
| 1066 masm->emit_rtcall(this); | |
| 1067 } | |
| 1068 | |
| 1069 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { | |
| 1070 masm->emit_opLabel(this); | |
| 1071 } | |
| 1072 | |
| 1073 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { | |
| 1074 masm->emit_arraycopy(this); | |
| 1075 masm->emit_code_stub(stub()); | |
| 1076 } | |
| 1077 | |
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1078 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { |
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1079 masm->emit_updatecrc32(this); |
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1080 } |
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1081 |
| 0 | 1082 void LIR_Op0::emit_code(LIR_Assembler* masm) { |
| 1083 masm->emit_op0(this); | |
| 1084 } | |
| 1085 | |
| 1086 void LIR_Op1::emit_code(LIR_Assembler* masm) { | |
| 1087 masm->emit_op1(this); | |
| 1088 } | |
| 1089 | |
| 1090 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { | |
| 1091 masm->emit_alloc_obj(this); | |
| 1092 masm->emit_code_stub(stub()); | |
| 1093 } | |
| 1094 | |
| 1095 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { | |
| 1096 masm->emit_opBranch(this); | |
| 1097 if (stub()) { | |
| 1098 masm->emit_code_stub(stub()); | |
| 1099 } | |
| 1100 } | |
| 1101 | |
| 1102 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { | |
| 1103 masm->emit_opConvert(this); | |
| 1104 if (stub() != NULL) { | |
| 1105 masm->emit_code_stub(stub()); | |
| 1106 } | |
| 1107 } | |
| 1108 | |
| 1109 void LIR_Op2::emit_code(LIR_Assembler* masm) { | |
| 1110 masm->emit_op2(this); | |
| 1111 } | |
| 1112 | |
| 1113 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { | |
| 1114 masm->emit_alloc_array(this); | |
| 1115 masm->emit_code_stub(stub()); | |
| 1116 } | |
| 1117 | |
| 1118 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { | |
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1119 masm->emit_opTypeCheck(this); |
| 0 | 1120 if (stub()) { |
| 1121 masm->emit_code_stub(stub()); | |
| 1122 } | |
| 1123 } | |
| 1124 | |
| 1125 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { | |
| 1126 masm->emit_compare_and_swap(this); | |
| 1127 } | |
| 1128 | |
| 1129 void LIR_Op3::emit_code(LIR_Assembler* masm) { | |
| 1130 masm->emit_op3(this); | |
| 1131 } | |
| 1132 | |
| 1133 void LIR_OpLock::emit_code(LIR_Assembler* masm) { | |
| 1134 masm->emit_lock(this); | |
| 1135 if (stub()) { | |
| 1136 masm->emit_code_stub(stub()); | |
| 1137 } | |
| 1138 } | |
| 1139 | |
| 8860 | 1140 #ifdef ASSERT |
| 1141 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { | |
| 1142 masm->emit_assert(this); | |
| 1143 } | |
| 1144 #endif | |
| 0 | 1145 |
| 1146 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { | |
| 1147 masm->emit_delay(this); | |
| 1148 } | |
| 1149 | |
| 1150 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { | |
| 1151 masm->emit_profile_call(this); | |
| 1152 } | |
| 1153 | |
| 1154 // LIR_List | |
| 1155 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) | |
| 1156 : _operations(8) | |
| 1157 , _compilation(compilation) | |
| 1158 #ifndef PRODUCT | |
| 1159 , _block(block) | |
| 1160 #endif | |
| 1161 #ifdef ASSERT | |
| 1162 , _file(NULL) | |
| 1163 , _line(0) | |
| 1164 #endif | |
| 1165 { } | |
| 1166 | |
| 1167 | |
| 1168 #ifdef ASSERT | |
| 1169 void LIR_List::set_file_and_line(const char * file, int line) { | |
| 1170 const char * f = strrchr(file, '/'); | |
| 1171 if (f == NULL) f = strrchr(file, '\\'); | |
| 1172 if (f == NULL) { | |
| 1173 f = file; | |
| 1174 } else { | |
| 1175 f++; | |
| 1176 } | |
| 1177 _file = f; | |
| 1178 _line = line; | |
| 1179 } | |
| 1180 #endif | |
| 1181 | |
| 1182 | |
| 1183 void LIR_List::append(LIR_InsertionBuffer* buffer) { | |
| 1184 assert(this == buffer->lir_list(), "wrong lir list"); | |
| 1185 const int n = _operations.length(); | |
| 1186 | |
| 1187 if (buffer->number_of_ops() > 0) { | |
| 1188 // increase size of instructions list | |
| 1189 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); | |
| 1190 // insert ops from buffer into instructions list | |
| 1191 int op_index = buffer->number_of_ops() - 1; | |
| 1192 int ip_index = buffer->number_of_insertion_points() - 1; | |
| 1193 int from_index = n - 1; | |
| 1194 int to_index = _operations.length() - 1; | |
| 1195 for (; ip_index >= 0; ip_index --) { | |
| 1196 int index = buffer->index_at(ip_index); | |
| 1197 // make room after insertion point | |
| 1198 while (index < from_index) { | |
| 1199 _operations.at_put(to_index --, _operations.at(from_index --)); | |
| 1200 } | |
| 1201 // insert ops from buffer | |
| 1202 for (int i = buffer->count_at(ip_index); i > 0; i --) { | |
| 1203 _operations.at_put(to_index --, buffer->op_at(op_index --)); | |
| 1204 } | |
| 1205 } | |
| 1206 } | |
| 1207 | |
| 1208 buffer->finish(); | |
| 1209 } | |
| 1210 | |
| 1211 | |
| 1212 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { | |
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1213 assert(reg->type() == T_OBJECT, "bad reg"); |
| 0 | 1214 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); |
| 1215 } | |
| 1216 | |
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1217 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { |
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1218 assert(reg->type() == T_METADATA, "bad reg"); |
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1219 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); |
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1220 } |
| 0 | 1221 |
| 1222 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1223 append(new LIR_Op1( | |
| 1224 lir_move, | |
| 1225 LIR_OprFact::address(addr), | |
| 1226 src, | |
| 1227 addr->type(), | |
| 1228 patch_code, | |
| 1229 info)); | |
| 1230 } | |
| 1231 | |
| 1232 | |
| 1233 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1234 append(new LIR_Op1( | |
| 1235 lir_move, | |
| 1236 LIR_OprFact::address(address), | |
| 1237 dst, | |
| 1238 address->type(), | |
| 1239 patch_code, | |
| 1240 info, lir_move_volatile)); | |
| 1241 } | |
| 1242 | |
| 1243 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1244 append(new LIR_Op1( | |
| 1245 lir_move, | |
| 1246 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
| 1247 dst, | |
| 1248 type, | |
| 1249 patch_code, | |
| 1250 info, lir_move_volatile)); | |
| 1251 } | |
| 1252 | |
| 1253 | |
| 1254 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { | |
| 1255 append(new LIR_Op1( | |
| 1256 is_store ? lir_prefetchw : lir_prefetchr, | |
| 1257 LIR_OprFact::address(addr))); | |
| 1258 } | |
| 1259 | |
| 1260 | |
| 1261 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1262 append(new LIR_Op1( | |
| 1263 lir_move, | |
| 1264 LIR_OprFact::intConst(v), | |
| 1265 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
| 1266 type, | |
| 1267 patch_code, | |
| 1268 info)); | |
| 1269 } | |
| 1270 | |
| 1271 | |
| 1272 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1273 append(new LIR_Op1( | |
| 1274 lir_move, | |
| 1275 LIR_OprFact::oopConst(o), | |
| 1276 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
| 1277 type, | |
| 1278 patch_code, | |
| 1279 info)); | |
| 1280 } | |
| 1281 | |
| 1282 | |
| 1283 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1284 append(new LIR_Op1( | |
| 1285 lir_move, | |
| 1286 src, | |
| 1287 LIR_OprFact::address(addr), | |
| 1288 addr->type(), | |
| 1289 patch_code, | |
| 1290 info)); | |
| 1291 } | |
| 1292 | |
| 1293 | |
| 1294 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1295 append(new LIR_Op1( | |
| 1296 lir_move, | |
| 1297 src, | |
| 1298 LIR_OprFact::address(addr), | |
| 1299 addr->type(), | |
| 1300 patch_code, | |
| 1301 info, | |
| 1302 lir_move_volatile)); | |
| 1303 } | |
| 1304 | |
| 1305 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1306 append(new LIR_Op1( | |
| 1307 lir_move, | |
| 1308 src, | |
| 1309 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
| 1310 type, | |
| 1311 patch_code, | |
| 1312 info, lir_move_volatile)); | |
| 1313 } | |
| 1314 | |
| 1315 | |
| 1316 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1317 append(new LIR_Op3( | |
| 1318 lir_idiv, | |
| 1319 left, | |
| 1320 right, | |
| 1321 tmp, | |
| 1322 res, | |
| 1323 info)); | |
| 1324 } | |
| 1325 | |
| 1326 | |
| 1327 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1328 append(new LIR_Op3( | |
| 1329 lir_idiv, | |
| 1330 left, | |
| 1331 LIR_OprFact::intConst(right), | |
| 1332 tmp, | |
| 1333 res, | |
| 1334 info)); | |
| 1335 } | |
| 1336 | |
| 1337 | |
| 1338 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1339 append(new LIR_Op3( | |
| 1340 lir_irem, | |
| 1341 left, | |
| 1342 right, | |
| 1343 tmp, | |
| 1344 res, | |
| 1345 info)); | |
| 1346 } | |
| 1347 | |
| 1348 | |
| 1349 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1350 append(new LIR_Op3( | |
| 1351 lir_irem, | |
| 1352 left, | |
| 1353 LIR_OprFact::intConst(right), | |
| 1354 tmp, | |
| 1355 res, | |
| 1356 info)); | |
| 1357 } | |
| 1358 | |
| 1359 | |
| 1360 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { | |
| 1361 append(new LIR_Op2( | |
| 1362 lir_cmp, | |
| 1363 condition, | |
| 1364 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), | |
| 1365 LIR_OprFact::intConst(c), | |
| 1366 info)); | |
| 1367 } | |
| 1368 | |
| 1369 | |
| 1370 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { | |
| 1371 append(new LIR_Op2( | |
| 1372 lir_cmp, | |
| 1373 condition, | |
| 1374 reg, | |
| 1375 LIR_OprFact::address(addr), | |
| 1376 info)); | |
| 1377 } | |
| 1378 | |
| 1379 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, | |
| 1380 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { | |
| 1381 append(new LIR_OpAllocObj( | |
| 1382 klass, | |
| 1383 dst, | |
| 1384 t1, | |
| 1385 t2, | |
| 1386 t3, | |
| 1387 t4, | |
| 1388 header_size, | |
| 1389 object_size, | |
| 1390 init_check, | |
| 1391 stub)); | |
| 1392 } | |
| 1393 | |
| 1394 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { | |
| 1395 append(new LIR_OpAllocArray( | |
| 1396 klass, | |
| 1397 len, | |
| 1398 dst, | |
| 1399 t1, | |
| 1400 t2, | |
| 1401 t3, | |
| 1402 t4, | |
| 1403 type, | |
| 1404 stub)); | |
| 1405 } | |
| 1406 | |
| 1407 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1408 append(new LIR_Op2( | |
| 1409 lir_shl, | |
| 1410 value, | |
| 1411 count, | |
| 1412 dst, | |
| 1413 tmp)); | |
| 1414 } | |
| 1415 | |
| 1416 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1417 append(new LIR_Op2( | |
| 1418 lir_shr, | |
| 1419 value, | |
| 1420 count, | |
| 1421 dst, | |
| 1422 tmp)); | |
| 1423 } | |
| 1424 | |
| 1425 | |
| 1426 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1427 append(new LIR_Op2( | |
| 1428 lir_ushr, | |
| 1429 value, | |
| 1430 count, | |
| 1431 dst, | |
| 1432 tmp)); | |
| 1433 } | |
| 1434 | |
| 1435 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { | |
| 1436 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, | |
| 1437 left, | |
| 1438 right, | |
| 1439 dst)); | |
| 1440 } | |
| 1441 | |
| 1442 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { | |
| 1443 append(new LIR_OpLock( | |
| 1444 lir_lock, | |
| 1445 hdr, | |
| 1446 obj, | |
| 1447 lock, | |
| 1448 scratch, | |
| 1449 stub, | |
| 1450 info)); | |
| 1451 } | |
| 1452 | |
|
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1453 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
| 0 | 1454 append(new LIR_OpLock( |
| 1455 lir_unlock, | |
| 1456 hdr, | |
| 1457 obj, | |
| 1458 lock, | |
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1459 scratch, |
| 0 | 1460 stub, |
| 1461 NULL)); | |
| 1462 } | |
| 1463 | |
| 1464 | |
| 1465 void check_LIR() { | |
| 1466 // cannot do the proper checking as PRODUCT and other modes return different results | |
| 1467 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); | |
| 1468 } | |
| 1469 | |
| 1470 | |
| 1471 | |
| 1472 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
| 1473 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, | |
| 1474 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, | |
| 1475 ciMethod* profiled_method, int profiled_bci) { | |
| 1783 | 1476 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, |
| 1477 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); | |
| 1478 if (profiled_method != NULL) { | |
| 1479 c->set_profiled_method(profiled_method); | |
| 1480 c->set_profiled_bci(profiled_bci); | |
| 1481 c->set_should_profile(true); | |
| 1482 } | |
| 1483 append(c); | |
| 0 | 1484 } |
| 1485 | |
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1486 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { |
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1487 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); |
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1488 if (profiled_method != NULL) { |
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1489 c->set_profiled_method(profiled_method); |
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1490 c->set_profiled_bci(profiled_bci); |
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1491 c->set_should_profile(true); |
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1492 } |
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1493 append(c); |
| 0 | 1494 } |
| 1495 | |
| 1496 | |
| 3957 | 1497 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
| 1498 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { | |
| 1499 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); | |
| 1500 if (profiled_method != NULL) { | |
| 1501 c->set_profiled_method(profiled_method); | |
| 1502 c->set_profiled_bci(profiled_bci); | |
| 1503 c->set_should_profile(true); | |
| 1504 } | |
| 1505 append(c); | |
| 0 | 1506 } |
| 1507 | |
| 1508 | |
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1509 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1510 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1511 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1512 } |
| 1513 | |
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1514 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1515 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1516 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1517 } |
| 1518 | |
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1519 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1520 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1521 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1522 } |
| 1523 | |
| 1524 | |
| 1525 #ifdef PRODUCT | |
| 1526 | |
| 1527 void print_LIR(BlockList* blocks) { | |
| 1528 } | |
| 1529 | |
| 1530 #else | |
| 1531 // LIR_OprDesc | |
| 1532 void LIR_OprDesc::print() const { | |
| 1533 print(tty); | |
| 1534 } | |
| 1535 | |
| 1536 void LIR_OprDesc::print(outputStream* out) const { | |
| 1537 if (is_illegal()) { | |
| 1538 return; | |
| 1539 } | |
| 1540 | |
| 1541 out->print("["); | |
| 1542 if (is_pointer()) { | |
| 1543 pointer()->print_value_on(out); | |
| 1544 } else if (is_single_stack()) { | |
| 1545 out->print("stack:%d", single_stack_ix()); | |
| 1546 } else if (is_double_stack()) { | |
| 1547 out->print("dbl_stack:%d",double_stack_ix()); | |
| 1548 } else if (is_virtual()) { | |
| 1549 out->print("R%d", vreg_number()); | |
| 1550 } else if (is_single_cpu()) { | |
| 1551 out->print(as_register()->name()); | |
| 1552 } else if (is_double_cpu()) { | |
| 1553 out->print(as_register_hi()->name()); | |
| 1554 out->print(as_register_lo()->name()); | |
| 304 | 1555 #if defined(X86) |
| 0 | 1556 } else if (is_single_xmm()) { |
| 1557 out->print(as_xmm_float_reg()->name()); | |
| 1558 } else if (is_double_xmm()) { | |
| 1559 out->print(as_xmm_double_reg()->name()); | |
| 1560 } else if (is_single_fpu()) { | |
| 1561 out->print("fpu%d", fpu_regnr()); | |
| 1562 } else if (is_double_fpu()) { | |
| 1563 out->print("fpu%d", fpu_regnrLo()); | |
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1564 #elif defined(ARM) |
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1565 } else if (is_single_fpu()) { |
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1566 out->print("s%d", fpu_regnr()); |
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1567 } else if (is_double_fpu()) { |
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1568 out->print("d%d", fpu_regnrLo() >> 1); |
| 0 | 1569 #else |
| 1570 } else if (is_single_fpu()) { | |
| 1571 out->print(as_float_reg()->name()); | |
| 1572 } else if (is_double_fpu()) { | |
| 1573 out->print(as_double_reg()->name()); | |
| 1574 #endif | |
| 1575 | |
| 1576 } else if (is_illegal()) { | |
| 1577 out->print("-"); | |
| 1578 } else { | |
| 1579 out->print("Unknown Operand"); | |
| 1580 } | |
| 1581 if (!is_illegal()) { | |
| 1582 out->print("|%c", type_char()); | |
| 1583 } | |
| 1584 if (is_register() && is_last_use()) { | |
| 1585 out->print("(last_use)"); | |
| 1586 } | |
| 1587 out->print("]"); | |
| 1588 } | |
| 1589 | |
| 1590 | |
| 1591 // LIR_Address | |
| 1592 void LIR_Const::print_value_on(outputStream* out) const { | |
| 1593 switch (type()) { | |
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1594 case T_ADDRESS:out->print("address:%d",as_jint()); break; |
| 0 | 1595 case T_INT: out->print("int:%d", as_jint()); break; |
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1596 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; |
| 0 | 1597 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; |
| 1598 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; | |
| 1599 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; | |
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1600 case T_METADATA: out->print("metadata:0x%x", as_metadata());break; |
| 0 | 1601 default: out->print("%3d:0x%x",type(), as_jdouble()); break; |
| 1602 } | |
| 1603 } | |
| 1604 | |
| 1605 // LIR_Address | |
| 1606 void LIR_Address::print_value_on(outputStream* out) const { | |
| 1607 out->print("Base:"); _base->print(out); | |
| 1608 if (!_index->is_illegal()) { | |
| 1609 out->print(" Index:"); _index->print(out); | |
| 1610 switch (scale()) { | |
| 1611 case times_1: break; | |
| 1612 case times_2: out->print(" * 2"); break; | |
| 1613 case times_4: out->print(" * 4"); break; | |
| 1614 case times_8: out->print(" * 8"); break; | |
| 1615 } | |
| 1616 } | |
| 1617 out->print(" Disp: %d", _disp); | |
| 1618 } | |
| 1619 | |
| 1620 // debug output of block header without InstructionPrinter | |
| 1621 // (because phi functions are not necessary for LIR) | |
| 1622 static void print_block(BlockBegin* x) { | |
| 1623 // print block id | |
| 1624 BlockEnd* end = x->end(); | |
| 1625 tty->print("B%d ", x->block_id()); | |
| 1626 | |
| 1627 // print flags | |
| 1628 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); | |
| 1629 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); | |
| 1630 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); | |
| 1631 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); | |
| 1632 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); | |
| 1633 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); | |
| 1634 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); | |
| 1635 | |
| 1636 // print block bci range | |
| 1819 | 1637 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); |
| 0 | 1638 |
| 1639 // print predecessors and successors | |
| 1640 if (x->number_of_preds() > 0) { | |
| 1641 tty->print("preds: "); | |
| 1642 for (int i = 0; i < x->number_of_preds(); i ++) { | |
| 1643 tty->print("B%d ", x->pred_at(i)->block_id()); | |
| 1644 } | |
| 1645 } | |
| 1646 | |
| 1647 if (x->number_of_sux() > 0) { | |
| 1648 tty->print("sux: "); | |
| 1649 for (int i = 0; i < x->number_of_sux(); i ++) { | |
| 1650 tty->print("B%d ", x->sux_at(i)->block_id()); | |
| 1651 } | |
| 1652 } | |
| 1653 | |
| 1654 // print exception handlers | |
| 1655 if (x->number_of_exception_handlers() > 0) { | |
| 1656 tty->print("xhandler: "); | |
| 1657 for (int i = 0; i < x->number_of_exception_handlers(); i++) { | |
| 1658 tty->print("B%d ", x->exception_handler_at(i)->block_id()); | |
| 1659 } | |
| 1660 } | |
| 1661 | |
| 1662 tty->cr(); | |
| 1663 } | |
| 1664 | |
| 1665 void print_LIR(BlockList* blocks) { | |
| 1666 tty->print_cr("LIR:"); | |
| 1667 int i; | |
| 1668 for (i = 0; i < blocks->length(); i++) { | |
| 1669 BlockBegin* bb = blocks->at(i); | |
| 1670 print_block(bb); | |
| 1671 tty->print("__id_Instruction___________________________________________"); tty->cr(); | |
| 1672 bb->lir()->print_instructions(); | |
| 1673 } | |
| 1674 } | |
| 1675 | |
| 1676 void LIR_List::print_instructions() { | |
| 1677 for (int i = 0; i < _operations.length(); i++) { | |
| 1678 _operations.at(i)->print(); tty->cr(); | |
| 1679 } | |
| 1680 tty->cr(); | |
| 1681 } | |
| 1682 | |
| 1683 // LIR_Ops printing routines | |
| 1684 // LIR_Op | |
| 1685 void LIR_Op::print_on(outputStream* out) const { | |
| 1686 if (id() != -1 || PrintCFGToFile) { | |
| 1687 out->print("%4d ", id()); | |
| 1688 } else { | |
| 1689 out->print(" "); | |
| 1690 } | |
| 1691 out->print(name()); out->print(" "); | |
| 1692 print_instr(out); | |
| 1819 | 1693 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); |
| 0 | 1694 #ifdef ASSERT |
| 1695 if (Verbose && _file != NULL) { | |
| 1696 out->print(" (%s:%d)", _file, _line); | |
| 1697 } | |
| 1698 #endif | |
| 1699 } | |
| 1700 | |
| 1701 const char * LIR_Op::name() const { | |
| 1702 const char* s = NULL; | |
| 1703 switch(code()) { | |
| 1704 // LIR_Op0 | |
| 1705 case lir_membar: s = "membar"; break; | |
| 1706 case lir_membar_acquire: s = "membar_acquire"; break; | |
| 1707 case lir_membar_release: s = "membar_release"; break; | |
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1708 case lir_membar_loadload: s = "membar_loadload"; break; |
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1709 case lir_membar_storestore: s = "membar_storestore"; break; |
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1710 case lir_membar_loadstore: s = "membar_loadstore"; break; |
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1711 case lir_membar_storeload: s = "membar_storeload"; break; |
| 0 | 1712 case lir_word_align: s = "word_align"; break; |
| 1713 case lir_label: s = "label"; break; | |
| 1714 case lir_nop: s = "nop"; break; | |
| 1715 case lir_backwardbranch_target: s = "backbranch"; break; | |
| 1716 case lir_std_entry: s = "std_entry"; break; | |
| 1717 case lir_osr_entry: s = "osr_entry"; break; | |
| 1718 case lir_build_frame: s = "build_frm"; break; | |
| 1719 case lir_fpop_raw: s = "fpop_raw"; break; | |
| 1720 case lir_24bit_FPU: s = "24bit_FPU"; break; | |
| 1721 case lir_reset_FPU: s = "reset_FPU"; break; | |
| 1722 case lir_breakpoint: s = "breakpoint"; break; | |
| 1723 case lir_get_thread: s = "get_thread"; break; | |
| 1724 // LIR_Op1 | |
| 1725 case lir_fxch: s = "fxch"; break; | |
| 1726 case lir_fld: s = "fld"; break; | |
| 1727 case lir_ffree: s = "ffree"; break; | |
| 1728 case lir_push: s = "push"; break; | |
| 1729 case lir_pop: s = "pop"; break; | |
| 1730 case lir_null_check: s = "null_check"; break; | |
| 1731 case lir_return: s = "return"; break; | |
| 1732 case lir_safepoint: s = "safepoint"; break; | |
| 1733 case lir_neg: s = "neg"; break; | |
| 1734 case lir_leal: s = "leal"; break; | |
| 1735 case lir_branch: s = "branch"; break; | |
| 1736 case lir_cond_float_branch: s = "flt_cond_br"; break; | |
| 1737 case lir_move: s = "move"; break; | |
| 1738 case lir_roundfp: s = "roundfp"; break; | |
| 1739 case lir_rtcall: s = "rtcall"; break; | |
| 1740 case lir_throw: s = "throw"; break; | |
| 1741 case lir_unwind: s = "unwind"; break; | |
| 1742 case lir_convert: s = "convert"; break; | |
| 1743 case lir_alloc_object: s = "alloc_obj"; break; | |
| 1744 case lir_monaddr: s = "mon_addr"; break; | |
| 1783 | 1745 case lir_pack64: s = "pack64"; break; |
| 1746 case lir_unpack64: s = "unpack64"; break; | |
| 0 | 1747 // LIR_Op2 |
| 1748 case lir_cmp: s = "cmp"; break; | |
| 1749 case lir_cmp_l2i: s = "cmp_l2i"; break; | |
| 1750 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; | |
| 1751 case lir_cmp_fd2i: s = "comp_fd2i"; break; | |
| 1752 case lir_cmove: s = "cmove"; break; | |
| 1753 case lir_add: s = "add"; break; | |
| 1754 case lir_sub: s = "sub"; break; | |
| 1755 case lir_mul: s = "mul"; break; | |
| 1756 case lir_mul_strictfp: s = "mul_strictfp"; break; | |
| 1757 case lir_div: s = "div"; break; | |
| 1758 case lir_div_strictfp: s = "div_strictfp"; break; | |
| 1759 case lir_rem: s = "rem"; break; | |
| 1760 case lir_abs: s = "abs"; break; | |
| 1761 case lir_sqrt: s = "sqrt"; break; | |
| 1762 case lir_sin: s = "sin"; break; | |
| 1763 case lir_cos: s = "cos"; break; | |
| 1764 case lir_tan: s = "tan"; break; | |
| 1765 case lir_log: s = "log"; break; | |
| 1766 case lir_log10: s = "log10"; break; | |
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1767 case lir_exp: s = "exp"; break; |
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1768 case lir_pow: s = "pow"; break; |
| 0 | 1769 case lir_logic_and: s = "logic_and"; break; |
| 1770 case lir_logic_or: s = "logic_or"; break; | |
| 1771 case lir_logic_xor: s = "logic_xor"; break; | |
| 1772 case lir_shl: s = "shift_left"; break; | |
| 1773 case lir_shr: s = "shift_right"; break; | |
| 1774 case lir_ushr: s = "ushift_right"; break; | |
| 1775 case lir_alloc_array: s = "alloc_array"; break; | |
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1776 case lir_xadd: s = "xadd"; break; |
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1777 case lir_xchg: s = "xchg"; break; |
| 0 | 1778 // LIR_Op3 |
| 1779 case lir_idiv: s = "idiv"; break; | |
| 1780 case lir_irem: s = "irem"; break; | |
| 1781 // LIR_OpJavaCall | |
| 1782 case lir_static_call: s = "static"; break; | |
| 1783 case lir_optvirtual_call: s = "optvirtual"; break; | |
| 1784 case lir_icvirtual_call: s = "icvirtual"; break; | |
| 1785 case lir_virtual_call: s = "virtual"; break; | |
| 1295 | 1786 case lir_dynamic_call: s = "dynamic"; break; |
| 0 | 1787 // LIR_OpArrayCopy |
| 1788 case lir_arraycopy: s = "arraycopy"; break; | |
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1789 // LIR_OpUpdateCRC32 |
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1790 case lir_updatecrc32: s = "updatecrc32"; break; |
| 0 | 1791 // LIR_OpLock |
| 1792 case lir_lock: s = "lock"; break; | |
| 1793 case lir_unlock: s = "unlock"; break; | |
| 1794 // LIR_OpDelay | |
| 1795 case lir_delay_slot: s = "delay"; break; | |
| 1796 // LIR_OpTypeCheck | |
| 1797 case lir_instanceof: s = "instanceof"; break; | |
| 1798 case lir_checkcast: s = "checkcast"; break; | |
| 1799 case lir_store_check: s = "store_check"; break; | |
| 1800 // LIR_OpCompareAndSwap | |
| 1801 case lir_cas_long: s = "cas_long"; break; | |
| 1802 case lir_cas_obj: s = "cas_obj"; break; | |
| 1803 case lir_cas_int: s = "cas_int"; break; | |
| 1804 // LIR_OpProfileCall | |
| 1805 case lir_profile_call: s = "profile_call"; break; | |
| 8860 | 1806 // LIR_OpAssert |
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1807 #ifdef ASSERT |
| 8860 | 1808 case lir_assert: s = "assert"; break; |
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1809 #endif |
| 0 | 1810 case lir_none: ShouldNotReachHere();break; |
| 1811 default: s = "illegal_op"; break; | |
| 1812 } | |
| 1813 return s; | |
| 1814 } | |
| 1815 | |
| 1816 // LIR_OpJavaCall | |
| 1817 void LIR_OpJavaCall::print_instr(outputStream* out) const { | |
| 1818 out->print("call: "); | |
| 1819 out->print("[addr: 0x%x]", address()); | |
| 1820 if (receiver()->is_valid()) { | |
| 1821 out->print(" [recv: "); receiver()->print(out); out->print("]"); | |
| 1822 } | |
| 1823 if (result_opr()->is_valid()) { | |
| 1824 out->print(" [result: "); result_opr()->print(out); out->print("]"); | |
| 1825 } | |
| 1826 } | |
| 1827 | |
| 1828 // LIR_OpLabel | |
| 1829 void LIR_OpLabel::print_instr(outputStream* out) const { | |
| 1830 out->print("[label:0x%x]", _label); | |
| 1831 } | |
| 1832 | |
| 1833 // LIR_OpArrayCopy | |
| 1834 void LIR_OpArrayCopy::print_instr(outputStream* out) const { | |
| 1835 src()->print(out); out->print(" "); | |
| 1836 src_pos()->print(out); out->print(" "); | |
| 1837 dst()->print(out); out->print(" "); | |
| 1838 dst_pos()->print(out); out->print(" "); | |
| 1839 length()->print(out); out->print(" "); | |
| 1840 tmp()->print(out); out->print(" "); | |
| 1841 } | |
| 1842 | |
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1843 // LIR_OpUpdateCRC32 |
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1844 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { |
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1845 crc()->print(out); out->print(" "); |
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1846 val()->print(out); out->print(" "); |
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1847 result_opr()->print(out); out->print(" "); |
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1848 } |
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1849 |
| 0 | 1850 // LIR_OpCompareAndSwap |
| 1851 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { | |
| 1852 addr()->print(out); out->print(" "); | |
| 1853 cmp_value()->print(out); out->print(" "); | |
| 1854 new_value()->print(out); out->print(" "); | |
| 1855 tmp1()->print(out); out->print(" "); | |
| 1856 tmp2()->print(out); out->print(" "); | |
| 1857 | |
| 1858 } | |
| 1859 | |
| 1860 // LIR_Op0 | |
| 1861 void LIR_Op0::print_instr(outputStream* out) const { | |
| 1862 result_opr()->print(out); | |
| 1863 } | |
| 1864 | |
| 1865 // LIR_Op1 | |
| 1866 const char * LIR_Op1::name() const { | |
| 1867 if (code() == lir_move) { | |
| 1868 switch (move_kind()) { | |
| 1869 case lir_move_normal: | |
| 1870 return "move"; | |
| 1871 case lir_move_unaligned: | |
| 1872 return "unaligned move"; | |
| 1873 case lir_move_volatile: | |
| 1874 return "volatile_move"; | |
| 2002 | 1875 case lir_move_wide: |
| 1876 return "wide_move"; | |
| 0 | 1877 default: |
| 1878 ShouldNotReachHere(); | |
| 1879 return "illegal_op"; | |
| 1880 } | |
| 1881 } else { | |
| 1882 return LIR_Op::name(); | |
| 1883 } | |
| 1884 } | |
| 1885 | |
| 1886 | |
| 1887 void LIR_Op1::print_instr(outputStream* out) const { | |
| 1888 _opr->print(out); out->print(" "); | |
| 1889 result_opr()->print(out); out->print(" "); | |
| 1890 print_patch_code(out, patch_code()); | |
| 1891 } | |
| 1892 | |
| 1893 | |
| 1894 // LIR_Op1 | |
| 1895 void LIR_OpRTCall::print_instr(outputStream* out) const { | |
| 1896 intx a = (intx)addr(); | |
| 1897 out->print(Runtime1::name_for_address(addr())); | |
| 1898 out->print(" "); | |
| 1899 tmp()->print(out); | |
| 1900 } | |
| 1901 | |
| 1902 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { | |
| 1903 switch(code) { | |
| 1904 case lir_patch_none: break; | |
| 1905 case lir_patch_low: out->print("[patch_low]"); break; | |
| 1906 case lir_patch_high: out->print("[patch_high]"); break; | |
| 1907 case lir_patch_normal: out->print("[patch_normal]"); break; | |
| 1908 default: ShouldNotReachHere(); | |
| 1909 } | |
| 1910 } | |
| 1911 | |
| 1912 // LIR_OpBranch | |
| 1913 void LIR_OpBranch::print_instr(outputStream* out) const { | |
| 1914 print_condition(out, cond()); out->print(" "); | |
| 1915 if (block() != NULL) { | |
| 1916 out->print("[B%d] ", block()->block_id()); | |
| 1917 } else if (stub() != NULL) { | |
| 1918 out->print("["); | |
| 1919 stub()->print_name(out); | |
| 1920 out->print(": 0x%x]", stub()); | |
| 1819 | 1921 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); |
| 0 | 1922 } else { |
| 1923 out->print("[label:0x%x] ", label()); | |
| 1924 } | |
| 1925 if (ublock() != NULL) { | |
| 1926 out->print("unordered: [B%d] ", ublock()->block_id()); | |
| 1927 } | |
| 1928 } | |
| 1929 | |
| 1930 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { | |
| 1931 switch(cond) { | |
| 1932 case lir_cond_equal: out->print("[EQ]"); break; | |
| 1933 case lir_cond_notEqual: out->print("[NE]"); break; | |
| 1934 case lir_cond_less: out->print("[LT]"); break; | |
| 1935 case lir_cond_lessEqual: out->print("[LE]"); break; | |
| 1936 case lir_cond_greaterEqual: out->print("[GE]"); break; | |
| 1937 case lir_cond_greater: out->print("[GT]"); break; | |
| 1938 case lir_cond_belowEqual: out->print("[BE]"); break; | |
| 1939 case lir_cond_aboveEqual: out->print("[AE]"); break; | |
| 1940 case lir_cond_always: out->print("[AL]"); break; | |
| 1941 default: out->print("[%d]",cond); break; | |
| 1942 } | |
| 1943 } | |
| 1944 | |
| 1945 // LIR_OpConvert | |
| 1946 void LIR_OpConvert::print_instr(outputStream* out) const { | |
| 1947 print_bytecode(out, bytecode()); | |
| 1948 in_opr()->print(out); out->print(" "); | |
| 1949 result_opr()->print(out); out->print(" "); | |
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1950 #ifdef PPC |
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1951 if(tmp1()->is_valid()) { |
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1952 tmp1()->print(out); out->print(" "); |
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1953 tmp2()->print(out); out->print(" "); |
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1954 } |
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1955 #endif |
| 0 | 1956 } |
| 1957 | |
| 1958 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { | |
| 1959 switch(code) { | |
| 1960 case Bytecodes::_d2f: out->print("[d2f] "); break; | |
| 1961 case Bytecodes::_d2i: out->print("[d2i] "); break; | |
| 1962 case Bytecodes::_d2l: out->print("[d2l] "); break; | |
| 1963 case Bytecodes::_f2d: out->print("[f2d] "); break; | |
| 1964 case Bytecodes::_f2i: out->print("[f2i] "); break; | |
| 1965 case Bytecodes::_f2l: out->print("[f2l] "); break; | |
| 1966 case Bytecodes::_i2b: out->print("[i2b] "); break; | |
| 1967 case Bytecodes::_i2c: out->print("[i2c] "); break; | |
| 1968 case Bytecodes::_i2d: out->print("[i2d] "); break; | |
| 1969 case Bytecodes::_i2f: out->print("[i2f] "); break; | |
| 1970 case Bytecodes::_i2l: out->print("[i2l] "); break; | |
| 1971 case Bytecodes::_i2s: out->print("[i2s] "); break; | |
| 1972 case Bytecodes::_l2i: out->print("[l2i] "); break; | |
| 1973 case Bytecodes::_l2f: out->print("[l2f] "); break; | |
| 1974 case Bytecodes::_l2d: out->print("[l2d] "); break; | |
| 1975 default: | |
| 1976 out->print("[?%d]",code); | |
| 1977 break; | |
| 1978 } | |
| 1979 } | |
| 1980 | |
| 1981 void LIR_OpAllocObj::print_instr(outputStream* out) const { | |
| 1982 klass()->print(out); out->print(" "); | |
| 1983 obj()->print(out); out->print(" "); | |
| 1984 tmp1()->print(out); out->print(" "); | |
| 1985 tmp2()->print(out); out->print(" "); | |
| 1986 tmp3()->print(out); out->print(" "); | |
| 1987 tmp4()->print(out); out->print(" "); | |
| 1988 out->print("[hdr:%d]", header_size()); out->print(" "); | |
| 1989 out->print("[obj:%d]", object_size()); out->print(" "); | |
| 1990 out->print("[lbl:0x%x]", stub()->entry()); | |
| 1991 } | |
| 1992 | |
| 1993 void LIR_OpRoundFP::print_instr(outputStream* out) const { | |
| 1994 _opr->print(out); out->print(" "); | |
| 1995 tmp()->print(out); out->print(" "); | |
| 1996 result_opr()->print(out); out->print(" "); | |
| 1997 } | |
| 1998 | |
| 1999 // LIR_Op2 | |
| 2000 void LIR_Op2::print_instr(outputStream* out) const { | |
| 2001 if (code() == lir_cmove) { | |
| 2002 print_condition(out, condition()); out->print(" "); | |
| 2003 } | |
| 2004 in_opr1()->print(out); out->print(" "); | |
| 2005 in_opr2()->print(out); out->print(" "); | |
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2006 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } |
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2007 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } |
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2008 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } |
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2009 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } |
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2010 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } |
| 0 | 2011 result_opr()->print(out); |
| 2012 } | |
| 2013 | |
| 2014 void LIR_OpAllocArray::print_instr(outputStream* out) const { | |
| 2015 klass()->print(out); out->print(" "); | |
| 2016 len()->print(out); out->print(" "); | |
| 2017 obj()->print(out); out->print(" "); | |
| 2018 tmp1()->print(out); out->print(" "); | |
| 2019 tmp2()->print(out); out->print(" "); | |
| 2020 tmp3()->print(out); out->print(" "); | |
| 2021 tmp4()->print(out); out->print(" "); | |
| 2022 out->print("[type:0x%x]", type()); out->print(" "); | |
| 2023 out->print("[label:0x%x]", stub()->entry()); | |
| 2024 } | |
| 2025 | |
| 2026 | |
| 2027 void LIR_OpTypeCheck::print_instr(outputStream* out) const { | |
| 2028 object()->print(out); out->print(" "); | |
| 2029 if (code() == lir_store_check) { | |
| 2030 array()->print(out); out->print(" "); | |
| 2031 } | |
| 2032 if (code() != lir_store_check) { | |
| 2033 klass()->print_name_on(out); out->print(" "); | |
| 2034 if (fast_check()) out->print("fast_check "); | |
| 2035 } | |
| 2036 tmp1()->print(out); out->print(" "); | |
| 2037 tmp2()->print(out); out->print(" "); | |
| 2038 tmp3()->print(out); out->print(" "); | |
| 2039 result_opr()->print(out); out->print(" "); | |
| 1819 | 2040 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); |
| 0 | 2041 } |
| 2042 | |
| 2043 | |
| 2044 // LIR_Op3 | |
| 2045 void LIR_Op3::print_instr(outputStream* out) const { | |
| 2046 in_opr1()->print(out); out->print(" "); | |
| 2047 in_opr2()->print(out); out->print(" "); | |
| 2048 in_opr3()->print(out); out->print(" "); | |
| 2049 result_opr()->print(out); | |
| 2050 } | |
| 2051 | |
| 2052 | |
| 2053 void LIR_OpLock::print_instr(outputStream* out) const { | |
| 2054 hdr_opr()->print(out); out->print(" "); | |
| 2055 obj_opr()->print(out); out->print(" "); | |
| 2056 lock_opr()->print(out); out->print(" "); | |
| 2057 if (_scratch->is_valid()) { | |
| 2058 _scratch->print(out); out->print(" "); | |
| 2059 } | |
| 2060 out->print("[lbl:0x%x]", stub()->entry()); | |
| 2061 } | |
| 2062 | |
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2063 #ifdef ASSERT |
| 8860 | 2064 void LIR_OpAssert::print_instr(outputStream* out) const { |
| 2065 print_condition(out, condition()); out->print(" "); | |
| 2066 in_opr1()->print(out); out->print(" "); | |
| 2067 in_opr2()->print(out); out->print(", \""); | |
| 2068 out->print(msg()); out->print("\""); | |
| 2069 } | |
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2070 #endif |
| 8860 | 2071 |
| 0 | 2072 |
| 2073 void LIR_OpDelay::print_instr(outputStream* out) const { | |
| 2074 _op->print_on(out); | |
| 2075 } | |
| 2076 | |
| 2077 | |
| 2078 // LIR_OpProfileCall | |
| 2079 void LIR_OpProfileCall::print_instr(outputStream* out) const { | |
| 2080 profiled_method()->name()->print_symbol_on(out); | |
| 2081 out->print("."); | |
| 2082 profiled_method()->holder()->name()->print_symbol_on(out); | |
| 2083 out->print(" @ %d ", profiled_bci()); | |
| 2084 mdo()->print(out); out->print(" "); | |
| 2085 recv()->print(out); out->print(" "); | |
| 2086 tmp1()->print(out); out->print(" "); | |
| 2087 } | |
| 2088 | |
| 2089 #endif // PRODUCT | |
| 2090 | |
| 2091 // Implementation of LIR_InsertionBuffer | |
| 2092 | |
| 2093 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { | |
| 2094 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); | |
| 2095 | |
| 2096 int i = number_of_insertion_points() - 1; | |
| 2097 if (i < 0 || index_at(i) < index) { | |
| 2098 append_new(index, 1); | |
| 2099 } else { | |
| 2100 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); | |
| 2101 assert(count_at(i) > 0, "check"); | |
| 2102 set_count_at(i, count_at(i) + 1); | |
| 2103 } | |
| 2104 _ops.push(op); | |
| 2105 | |
| 2106 DEBUG_ONLY(verify()); | |
| 2107 } | |
| 2108 | |
| 2109 #ifdef ASSERT | |
| 2110 void LIR_InsertionBuffer::verify() { | |
| 2111 int sum = 0; | |
| 2112 int prev_idx = -1; | |
| 2113 | |
| 2114 for (int i = 0; i < number_of_insertion_points(); i++) { | |
| 2115 assert(prev_idx < index_at(i), "index must be ordered ascending"); | |
| 2116 sum += count_at(i); | |
| 2117 } | |
| 2118 assert(sum == number_of_ops(), "wrong total sum"); | |
| 2119 } | |
| 2120 #endif |