Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 3842:c7b60b601eb4
7069452: Cleanup NodeFlags
Summary: Remove flags which duplicate information in Node::NodeClasses.
Reviewed-by: never
author | kvn |
---|---|
date | Wed, 27 Jul 2011 17:28:36 -0700 |
parents | 3d42f82cd811 |
children | 95134e034042 |
rev | line source |
---|---|
0 | 1 /* |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_sparc.inline.hpp" | |
27 #include "memory/resourceArea.hpp" | |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_sparc.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
0 | 37 |
38 int VM_Version::_features = VM_Version::unknown_m; | |
39 const char* VM_Version::_features_str = ""; | |
40 | |
41 void VM_Version::initialize() { | |
42 _features = determine_features(); | |
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
45 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
46 | |
47 // Allocation prefetch settings | |
48 intx cache_line_size = L1_data_cache_line_size(); | |
49 if( cache_line_size > AllocatePrefetchStepSize ) | |
50 AllocatePrefetchStepSize = cache_line_size; | |
51 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
52 AllocatePrefetchLines = 3; // Optimistic value | |
53 assert( AllocatePrefetchLines > 0, "invalid value"); | |
54 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
55 AllocatePrefetchLines = 1; // Conservative value | |
56 | |
57 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
58 AllocatePrefetchStyle = allocate_prefetch_style(); | |
59 | |
60 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
61 | |
3839 | 62 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
63 warning("BIS instructions are not available on this CPU"); | |
64 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
65 } | |
66 | |
0 | 67 UseSSE = 0; // Only on x86 and x64 |
68 | |
69 _supports_cx8 = has_v9(); | |
70 | |
2080 | 71 if (is_niagara()) { |
0 | 72 // Indirect branch is the same cost as direct |
73 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
675 | 74 FLAG_SET_DEFAULT(UseInlineCaches, false); |
0 | 75 } |
2080 | 76 // Align loops on a single instruction boundary. |
77 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
78 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
79 } | |
80 // When using CMS, we cannot use memset() in BOT updates because | |
81 // the sun4v/CMT version in libc_psr uses BIS which exposes | |
82 // "phantom zeros" to concurrent readers. See 6948537. | |
83 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) { | |
84 FLAG_SET_DEFAULT(UseMemSetInBOT, false); | |
85 } | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
86 #ifdef _LP64 |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
87 // 32-bit oops don't make sense for the 64-bit VM on sparc |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
88 // since the 32-bit VM has the same registers and smaller objects. |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
89 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
90 #endif // _LP64 |
0 | 91 #ifdef COMPILER2 |
92 // Indirect branch is the same cost as direct | |
93 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
675 | 94 FLAG_SET_DEFAULT(UseJumpTables, true); |
0 | 95 } |
96 // Single-issue, so entry and loop tops are | |
97 // aligned on a single instruction boundary | |
98 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
675 | 99 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
0 | 100 } |
2080 | 101 if (is_niagara_plus()) { |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
102 if (has_blk_init() && AllocatePrefetchStyle > 0 && |
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1730
diff
changeset
|
103 FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
104 // Use BIS instruction for allocation prefetch. |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
105 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
106 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
107 // Use smaller prefetch distance on N2 with BIS |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
108 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
109 } |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
110 } |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
111 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
112 // Use different prefetch distance without BIS |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
113 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
114 } |
0 | 115 } |
116 #endif | |
117 } | |
118 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
119 // Use hardware population count instruction if available. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
120 if (has_hardware_popc()) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
121 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
675 | 122 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
123 } |
3839 | 124 } else if (UsePopCountInstruction) { |
125 warning("POPC instruction is not available on this CPU"); | |
126 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
127 } | |
128 | |
129 // T4 and newer Sparc cpus have new compare and branch instruction. | |
130 if (has_cbcond()) { | |
131 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
132 FLAG_SET_DEFAULT(UseCBCond, true); | |
133 } | |
134 } else if (UseCBCond) { | |
135 warning("CBCOND instruction is not available on this CPU"); | |
136 FLAG_SET_DEFAULT(UseCBCond, false); | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
137 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
138 |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
139 #ifdef COMPILER2 |
3839 | 140 // T4 and newer Sparc cpus have fast RDPC. |
141 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
142 // FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); | |
143 } | |
144 | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
145 // Currently not supported anywhere. |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
146 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
147 #endif |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
148 |
0 | 149 char buf[512]; |
3839 | 150 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
151 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
152 (has_hardware_popc() ? ", popc" : ""), |
3839 | 153 (has_vis1() ? ", vis1" : ""), |
154 (has_vis2() ? ", vis2" : ""), | |
155 (has_vis3() ? ", vis3" : ""), | |
156 (has_blk_init() ? ", blk_init" : ""), | |
157 (has_cbcond() ? ", cbcond" : ""), | |
158 (is_ultra3() ? ", ultra3" : ""), | |
159 (is_sun4v() ? ", sun4v" : ""), | |
160 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
161 (is_sparc64() ? ", sparc64" : ""), | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
162 (!has_hardware_mul32() ? ", no-mul32" : ""), |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
163 (!has_hardware_div32() ? ", no-div32" : ""), |
0 | 164 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
165 | |
166 // buf is started with ", " or is empty | |
167 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
168 | |
3804 | 169 // UseVIS is set to the smallest of what hardware supports and what |
170 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
171 // older UltraSparc which do not support it. | |
172 if (UseVIS > 3) UseVIS=3; | |
173 if (UseVIS < 0) UseVIS=0; | |
174 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
175 UseVIS = MIN2((intx)2,UseVIS); | |
176 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
177 UseVIS = MIN2((intx)1,UseVIS); | |
178 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
179 UseVIS = 0; | |
180 | |
0 | 181 #ifndef PRODUCT |
182 if (PrintMiscellaneous && Verbose) { | |
183 tty->print("Allocation: "); | |
184 if (AllocatePrefetchStyle <= 0) { | |
185 tty->print_cr("no prefetching"); | |
186 } else { | |
187 if (AllocatePrefetchLines > 1) { | |
188 tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
189 } else { | |
190 tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance); | |
191 } | |
192 } | |
193 if (PrefetchCopyIntervalInBytes > 0) { | |
194 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
195 } | |
196 if (PrefetchScanIntervalInBytes > 0) { | |
197 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
198 } | |
199 if (PrefetchFieldsAhead > 0) { | |
200 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
201 } | |
202 } | |
203 #endif // PRODUCT | |
204 } | |
205 | |
206 void VM_Version::print_features() { | |
207 tty->print_cr("Version:%s", cpu_features()); | |
208 } | |
209 | |
210 int VM_Version::determine_features() { | |
211 if (UseV8InstrsOnly) { | |
212 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
213 return generic_v8_m; | |
214 } | |
215 | |
216 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
217 | |
218 if (features == unknown_m) { | |
219 features = generic_v9_m; | |
220 warning("Cannot recognize SPARC version. Default to V9"); | |
221 } | |
222 | |
2080 | 223 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
224 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
225 if (is_T_family(features)) { | |
0 | 226 // Happy to accomodate... |
227 } else { | |
228 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
2080 | 229 features |= T_family_m; |
0 | 230 } |
231 } else { | |
2080 | 232 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
0 | 233 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
2080 | 234 features &= ~(T_family_m | T1_model_m); |
0 | 235 } else { |
236 // Happy to accomodate... | |
237 } | |
238 } | |
239 | |
240 return features; | |
241 } | |
242 | |
243 static int saved_features = 0; | |
244 | |
245 void VM_Version::allow_all() { | |
246 saved_features = _features; | |
247 _features = all_features_m; | |
248 } | |
249 | |
250 void VM_Version::revert() { | |
251 _features = saved_features; | |
252 } | |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
253 |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
254 unsigned int VM_Version::calc_parallel_worker_threads() { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
255 unsigned int result; |
2080 | 256 if (is_niagara_plus()) { |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
257 result = nof_parallel_worker_threads(5, 16, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
258 } else { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
259 result = nof_parallel_worker_threads(5, 8, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
260 } |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
261 return result; |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
262 } |