Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp @ 1783:d5d065957597
6953144: Tiered compilation
Summary: Infrastructure for tiered compilation support (interpreter + c1 + c2) for 32 and 64 bit. Simple tiered policy implementation.
Reviewed-by: kvn, never, phh, twisti
| author | iveresov |
|---|---|
| date | Fri, 03 Sep 2010 17:51:07 -0700 |
| parents | c18cbe5936b8 |
| children | 3a294e483abc |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1783 | 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 25 private: | |
| 26 | |
| 27 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
| 28 // | |
| 29 // Sparc load/store emission | |
| 30 // | |
| 31 // The sparc ld/st instructions cannot accomodate displacements > 13 bits long. | |
| 32 // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode | |
| 33 // by allowing 32 bit displacements: | |
| 34 // | |
| 35 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]). | |
| 36 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register, | |
| 37 // and then a load or store is emitted with ([O7] + [d]). | |
| 38 // | |
| 39 | |
| 40 // some load/store variants return the code_offset for proper positioning of debug info for null checks | |
| 41 | |
| 42 // load/store with 32 bit displacement | |
| 43 int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL); | |
| 44 void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL); | |
| 45 | |
| 46 // loadf/storef with 32 bit displacement | |
| 47 void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL); | |
| 48 void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL); | |
| 49 | |
| 50 // convienence methods for calling load/store with an Address | |
| 51 void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0); | |
| 52 void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0); | |
| 53 void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0); | |
| 54 void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0); | |
| 55 | |
| 56 // convienence methods for calling load/store with an LIR_Address | |
| 57 void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL); | |
| 58 void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL); | |
| 59 void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL); | |
| 60 void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL); | |
| 61 | |
| 62 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false); | |
| 63 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type); | |
| 64 | |
| 65 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false); | |
| 66 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type); | |
| 67 | |
| 68 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no); | |
| 69 | |
| 70 int shift_amount(BasicType t); | |
| 71 | |
| 72 static bool is_single_instruction(LIR_Op* op); | |
| 73 | |
| 1783 | 74 // Record the type of the receiver in ReceiverTypeData |
| 75 void type_profile_helper(Register mdo, int mdo_offset_bias, | |
| 76 ciMethodData *md, ciProfileData *data, | |
| 77 Register recv, Register tmp1, Label* update_done); | |
| 0 | 78 public: |
| 1783 | 79 void pack64(LIR_Opr src, LIR_Opr dst); |
| 80 void unpack64(LIR_Opr src, LIR_Opr dst); | |
| 0 | 81 |
| 82 enum { | |
| 83 #ifdef _LP64 | |
| 84 call_stub_size = 68, | |
| 85 #else | |
| 86 call_stub_size = 20, | |
| 87 #endif // _LP64 | |
| 88 exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4), | |
| 89 deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) }; |