Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86.hpp @ 6725:da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
| author | coleenp |
|---|---|
| date | Sat, 01 Sep 2012 13:25:18 -0400 |
| parents | 006050192a5a |
| children | 75f33eecc1b3 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
| 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
| 27 | |
| 0 | 28 class BiasedLockingCounters; |
| 29 | |
| 30 // Contains all the definitions needed for x86 assembly code generation. | |
| 31 | |
| 32 // Calling convention | |
| 33 class Argument VALUE_OBJ_CLASS_SPEC { | |
| 34 public: | |
| 35 enum { | |
| 36 #ifdef _LP64 | |
| 37 #ifdef _WIN64 | |
| 38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
| 40 #else | |
| 41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
| 43 #endif // _WIN64 | |
| 44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
| 45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
| 46 #else | |
| 47 n_register_parameters = 0 // 0 registers used to pass arguments | |
| 48 #endif // _LP64 | |
| 49 }; | |
| 50 }; | |
| 51 | |
| 52 | |
| 53 #ifdef _LP64 | |
| 54 // Symbolically name the register arguments used by the c calling convention. | |
| 55 // Windows is different from linux/solaris. So much for standards... | |
| 56 | |
| 57 #ifdef _WIN64 | |
| 58 | |
| 59 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
| 60 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
| 61 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
| 62 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
| 63 | |
| 304 | 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 0 | 68 |
| 69 #else | |
| 70 | |
| 71 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
| 72 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
| 73 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
| 74 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
| 75 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
| 76 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
| 77 | |
| 304 | 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
| 83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
| 84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
| 85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
| 0 | 86 |
| 87 #endif // _WIN64 | |
| 88 | |
| 89 // Symbolically name the register arguments used by the Java calling convention. | |
| 90 // We have control over the convention for java so we can do what we please. | |
| 91 // What pleases us is to offset the java calling convention so that when | |
| 92 // we call a suitable jni method the arguments are lined up and we don't | |
| 93 // have to do little shuffling. A suitable jni method is non-static and a | |
| 94 // small number of arguments (two fewer args on windows) | |
| 95 // | |
| 96 // |-------------------------------------------------------| | |
| 97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
| 98 // |-------------------------------------------------------| | |
| 99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
| 100 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
| 101 // |-------------------------------------------------------| | |
| 102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
| 103 // |-------------------------------------------------------| | |
| 104 | |
| 105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
| 106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
| 107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
| 108 // Windows runs out of register args here | |
| 109 #ifdef _WIN64 | |
| 110 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
| 111 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
| 112 #else | |
| 113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
| 114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
| 115 #endif /* _WIN64 */ | |
| 116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
| 117 | |
| 304 | 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
| 119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
| 120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
| 121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
| 122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
| 123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
| 124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
| 125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
| 0 | 126 |
| 127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
| 128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
| 129 | |
| 304 | 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
| 0 | 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
| 132 | |
| 304 | 133 #else |
| 134 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
| 135 // Using noreg ensures if the dead code is incorrectly live and executed it | |
| 136 // will cause an assertion failure | |
| 137 #define rscratch1 noreg | |
| 2002 | 138 #define rscratch2 noreg |
| 304 | 139 |
| 0 | 140 #endif // _LP64 |
| 141 | |
| 1564 | 142 // JSR 292 fixed register usages: |
| 143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
| 144 | |
| 0 | 145 // Address is an abstraction used to represent a memory location |
| 146 // using any of the amd64 addressing modes with one object. | |
| 147 // | |
| 148 // Note: A register location is represented via a Register, not | |
| 149 // via an address for efficiency & simplicity reasons. | |
| 150 | |
| 151 class ArrayAddress; | |
| 152 | |
| 153 class Address VALUE_OBJ_CLASS_SPEC { | |
| 154 public: | |
| 155 enum ScaleFactor { | |
| 156 no_scale = -1, | |
| 157 times_1 = 0, | |
| 158 times_2 = 1, | |
| 159 times_4 = 2, | |
| 304 | 160 times_8 = 3, |
| 161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
| 0 | 162 }; |
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163 static ScaleFactor times(int size) { |
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164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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165 if (size == 8) return times_8; |
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166 if (size == 4) return times_4; |
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167 if (size == 2) return times_2; |
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168 return times_1; |
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169 } |
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170 static int scale_size(ScaleFactor scale) { |
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171 assert(scale != no_scale, ""); |
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172 assert(((1 << (int)times_1) == 1 && |
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173 (1 << (int)times_2) == 2 && |
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174 (1 << (int)times_4) == 4 && |
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175 (1 << (int)times_8) == 8), ""); |
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176 return (1 << (int)scale); |
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177 } |
| 0 | 178 |
| 179 private: | |
| 180 Register _base; | |
| 181 Register _index; | |
| 182 ScaleFactor _scale; | |
| 183 int _disp; | |
| 184 RelocationHolder _rspec; | |
| 185 | |
| 304 | 186 // Easily misused constructors make them private |
| 187 // %%% can we make these go away? | |
| 188 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
| 189 Address(int disp, address loc, relocInfo::relocType rtype); | |
| 190 Address(int disp, address loc, RelocationHolder spec); | |
| 0 | 191 |
| 192 public: | |
| 304 | 193 |
| 194 int disp() { return _disp; } | |
| 0 | 195 // creation |
| 196 Address() | |
| 197 : _base(noreg), | |
| 198 _index(noreg), | |
| 199 _scale(no_scale), | |
| 200 _disp(0) { | |
| 201 } | |
| 202 | |
| 203 // No default displacement otherwise Register can be implicitly | |
| 204 // converted to 0(Register) which is quite a different animal. | |
| 205 | |
| 206 Address(Register base, int disp) | |
| 207 : _base(base), | |
| 208 _index(noreg), | |
| 209 _scale(no_scale), | |
| 210 _disp(disp) { | |
| 211 } | |
| 212 | |
| 213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
| 214 : _base (base), | |
| 215 _index(index), | |
| 216 _scale(scale), | |
| 217 _disp (disp) { | |
| 218 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 219 "inconsistent address"); | |
| 220 } | |
| 221 | |
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222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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223 : _base (base), |
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224 _index(index.register_or_noreg()), |
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225 _scale(scale), |
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226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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227 if (!index.is_register()) scale = Address::no_scale; |
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228 assert(!_index->is_valid() == (scale == Address::no_scale), |
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229 "inconsistent address"); |
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230 } |
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231 |
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232 Address plus_disp(int disp) const { |
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233 Address a = (*this); |
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234 a._disp += disp; |
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235 return a; |
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236 } |
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237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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238 Address a = (*this); |
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239 a._disp += disp.constant_or_zero() * scale_size(scale); |
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240 if (disp.is_register()) { |
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241 assert(!a.index()->is_valid(), "competing indexes"); |
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242 a._index = disp.as_register(); |
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243 a._scale = scale; |
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244 } |
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245 return a; |
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246 } |
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247 bool is_same_address(Address a) const { |
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248 // disregard _rspec |
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249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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250 } |
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251 |
| 0 | 252 // The following two overloads are used in connection with the |
| 253 // ByteSize type (see sizes.hpp). They simplify the use of | |
| 254 // ByteSize'd arguments in assembly code. Note that their equivalent | |
| 255 // for the optimized build are the member functions with int disp | |
| 256 // argument since ByteSize is mapped to an int type in that case. | |
| 257 // | |
| 258 // Note: DO NOT introduce similar overloaded functions for WordSize | |
| 259 // arguments as in the optimized mode, both ByteSize and WordSize | |
| 260 // are mapped to the same type and thus the compiler cannot make a | |
| 261 // distinction anymore (=> compiler errors). | |
| 262 | |
| 263 #ifdef ASSERT | |
| 264 Address(Register base, ByteSize disp) | |
| 265 : _base(base), | |
| 266 _index(noreg), | |
| 267 _scale(no_scale), | |
| 268 _disp(in_bytes(disp)) { | |
| 269 } | |
| 270 | |
| 271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
| 272 : _base(base), | |
| 273 _index(index), | |
| 274 _scale(scale), | |
| 275 _disp(in_bytes(disp)) { | |
| 276 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 277 "inconsistent address"); | |
| 278 } | |
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279 |
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280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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281 : _base (base), |
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282 _index(index.register_or_noreg()), |
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283 _scale(scale), |
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284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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285 if (!index.is_register()) scale = Address::no_scale; |
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286 assert(!_index->is_valid() == (scale == Address::no_scale), |
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287 "inconsistent address"); |
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288 } |
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289 |
| 0 | 290 #endif // ASSERT |
| 291 | |
| 292 // accessors | |
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293 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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294 Register base() const { return _base; } |
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295 Register index() const { return _index; } |
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296 ScaleFactor scale() const { return _scale; } |
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297 int disp() const { return _disp; } |
| 0 | 298 |
| 299 // Convert the raw encoding form into the form expected by the constructor for | |
| 300 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 301 // that to noreg for the Address constructor. | |
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302 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
| 0 | 303 |
| 304 static Address make_array(ArrayAddress); | |
| 305 | |
| 306 private: | |
| 307 bool base_needs_rex() const { | |
| 308 return _base != noreg && _base->encoding() >= 8; | |
| 309 } | |
| 310 | |
| 311 bool index_needs_rex() const { | |
| 312 return _index != noreg &&_index->encoding() >= 8; | |
| 313 } | |
| 314 | |
| 315 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 316 | |
| 317 friend class Assembler; | |
| 318 friend class MacroAssembler; | |
| 319 friend class LIR_Assembler; // base/index/scale/disp | |
| 320 }; | |
| 321 | |
| 322 // | |
| 323 // AddressLiteral has been split out from Address because operands of this type | |
| 324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
| 325 // the few instructions that need to deal with address literals are unique and the | |
| 326 // MacroAssembler does not have to implement every instruction in the Assembler | |
| 327 // in order to search for address literals that may need special handling depending | |
| 328 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
| 329 // directories. | |
| 330 // | |
| 331 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
| 332 friend class ArrayAddress; | |
| 333 RelocationHolder _rspec; | |
| 334 // Typically we use AddressLiterals we want to use their rval | |
| 335 // However in some situations we want the lval (effect address) of the item. | |
| 336 // We provide a special factory for making those lvals. | |
| 337 bool _is_lval; | |
| 338 | |
| 339 // If the target is far we'll need to load the ea of this to | |
| 340 // a register to reach it. Otherwise if near we can do rip | |
| 341 // relative addressing. | |
| 342 | |
| 343 address _target; | |
| 344 | |
| 345 protected: | |
| 346 // creation | |
| 347 AddressLiteral() | |
| 348 : _is_lval(false), | |
| 349 _target(NULL) | |
| 350 {} | |
| 351 | |
| 352 public: | |
| 353 | |
| 354 | |
| 355 AddressLiteral(address target, relocInfo::relocType rtype); | |
| 356 | |
| 357 AddressLiteral(address target, RelocationHolder const& rspec) | |
| 358 : _rspec(rspec), | |
| 359 _is_lval(false), | |
| 360 _target(target) | |
| 361 {} | |
| 362 | |
| 363 AddressLiteral addr() { | |
| 364 AddressLiteral ret = *this; | |
| 365 ret._is_lval = true; | |
| 366 return ret; | |
| 367 } | |
| 368 | |
| 369 | |
| 370 private: | |
| 371 | |
| 372 address target() { return _target; } | |
| 373 bool is_lval() { return _is_lval; } | |
| 374 | |
| 375 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 376 const RelocationHolder& rspec() const { return _rspec; } | |
| 377 | |
| 378 friend class Assembler; | |
| 379 friend class MacroAssembler; | |
| 380 friend class Address; | |
| 381 friend class LIR_Assembler; | |
| 382 }; | |
| 383 | |
| 384 // Convience classes | |
| 385 class RuntimeAddress: public AddressLiteral { | |
| 386 | |
| 387 public: | |
| 388 | |
| 389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
| 390 | |
| 391 }; | |
| 392 | |
| 393 class ExternalAddress: public AddressLiteral { | |
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394 private: |
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395 static relocInfo::relocType reloc_for_target(address target) { |
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396 // Sometimes ExternalAddress is used for values which aren't |
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397 // exactly addresses, like the card table base. |
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398 // external_word_type can't be used for values in the first page |
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399 // so just skip the reloc in that case. |
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400 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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401 } |
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402 |
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403 public: |
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404 |
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405 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
| 0 | 406 |
| 407 }; | |
| 408 | |
| 409 class InternalAddress: public AddressLiteral { | |
| 410 | |
| 411 public: | |
| 412 | |
| 413 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
| 414 | |
| 415 }; | |
| 416 | |
| 417 // x86 can do array addressing as a single operation since disp can be an absolute | |
| 418 // address amd64 can't. We create a class that expresses the concept but does extra | |
| 419 // magic on amd64 to get the final result | |
| 420 | |
| 421 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
| 422 private: | |
| 423 | |
| 424 AddressLiteral _base; | |
| 425 Address _index; | |
| 426 | |
| 427 public: | |
| 428 | |
| 429 ArrayAddress() {}; | |
| 430 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
| 431 AddressLiteral base() { return _base; } | |
| 432 Address index() { return _index; } | |
| 433 | |
| 434 }; | |
| 435 | |
| 304 | 436 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
| 0 | 437 |
| 438 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
| 439 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
| 440 // is what you get. The Assembler is generating code into a CodeBuffer. | |
| 441 | |
| 442 class Assembler : public AbstractAssembler { | |
| 443 friend class AbstractAssembler; // for the non-virtual hack | |
| 444 friend class LIR_Assembler; // as_Address() | |
| 304 | 445 friend class StubGenerator; |
| 0 | 446 |
| 447 public: | |
| 448 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
| 449 zero = 0x4, | |
| 450 notZero = 0x5, | |
| 451 equal = 0x4, | |
| 452 notEqual = 0x5, | |
| 453 less = 0xc, | |
| 454 lessEqual = 0xe, | |
| 455 greater = 0xf, | |
| 456 greaterEqual = 0xd, | |
| 457 below = 0x2, | |
| 458 belowEqual = 0x6, | |
| 459 above = 0x7, | |
| 460 aboveEqual = 0x3, | |
| 461 overflow = 0x0, | |
| 462 noOverflow = 0x1, | |
| 463 carrySet = 0x2, | |
| 464 carryClear = 0x3, | |
| 465 negative = 0x8, | |
| 466 positive = 0x9, | |
| 467 parity = 0xa, | |
| 468 noParity = 0xb | |
| 469 }; | |
| 470 | |
| 471 enum Prefix { | |
| 472 // segment overrides | |
| 473 CS_segment = 0x2e, | |
| 474 SS_segment = 0x36, | |
| 475 DS_segment = 0x3e, | |
| 476 ES_segment = 0x26, | |
| 477 FS_segment = 0x64, | |
| 478 GS_segment = 0x65, | |
| 479 | |
| 480 REX = 0x40, | |
| 481 | |
| 482 REX_B = 0x41, | |
| 483 REX_X = 0x42, | |
| 484 REX_XB = 0x43, | |
| 485 REX_R = 0x44, | |
| 486 REX_RB = 0x45, | |
| 487 REX_RX = 0x46, | |
| 488 REX_RXB = 0x47, | |
| 489 | |
| 490 REX_W = 0x48, | |
| 491 | |
| 492 REX_WB = 0x49, | |
| 493 REX_WX = 0x4A, | |
| 494 REX_WXB = 0x4B, | |
| 495 REX_WR = 0x4C, | |
| 496 REX_WRB = 0x4D, | |
| 497 REX_WRX = 0x4E, | |
| 4759 | 498 REX_WRXB = 0x4F, |
| 499 | |
| 500 VEX_3bytes = 0xC4, | |
| 501 VEX_2bytes = 0xC5 | |
| 502 }; | |
| 503 | |
| 504 enum VexPrefix { | |
| 505 VEX_B = 0x20, | |
| 506 VEX_X = 0x40, | |
| 507 VEX_R = 0x80, | |
| 508 VEX_W = 0x80 | |
| 509 }; | |
| 510 | |
| 511 enum VexSimdPrefix { | |
| 512 VEX_SIMD_NONE = 0x0, | |
| 513 VEX_SIMD_66 = 0x1, | |
| 514 VEX_SIMD_F3 = 0x2, | |
| 515 VEX_SIMD_F2 = 0x3 | |
| 516 }; | |
| 517 | |
| 518 enum VexOpcode { | |
| 519 VEX_OPCODE_NONE = 0x0, | |
| 520 VEX_OPCODE_0F = 0x1, | |
| 521 VEX_OPCODE_0F_38 = 0x2, | |
| 522 VEX_OPCODE_0F_3A = 0x3 | |
| 0 | 523 }; |
| 524 | |
| 525 enum WhichOperand { | |
| 526 // input to locate_operand, and format code for relocations | |
| 304 | 527 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
| 0 | 528 disp32_operand = 1, // embedded 32-bit displacement or address |
| 529 call32_operand = 2, // embedded 32-bit self-relative displacement | |
| 304 | 530 #ifndef _LP64 |
| 0 | 531 _WhichOperand_limit = 3 |
| 304 | 532 #else |
| 533 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
| 534 _WhichOperand_limit = 4 | |
| 535 #endif | |
| 0 | 536 }; |
| 537 | |
| 304 | 538 |
| 539 | |
| 540 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
| 541 // of instructions are freely declared without the need for wrapping them an ifdef. | |
| 542 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
| 543 // In the .cpp file the implementations are wrapped so that they are dropped out | |
| 544 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
| 545 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
| 546 // | |
| 547 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
| 548 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
| 549 | |
| 550 private: | |
| 551 | |
| 552 | |
| 553 // 64bit prefixes | |
| 554 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
| 555 int prefixq_and_encode(int reg_enc); | |
| 556 | |
| 557 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
| 558 int prefixq_and_encode(int dst_enc, int src_enc); | |
| 559 | |
| 560 void prefix(Register reg); | |
| 561 void prefix(Address adr); | |
| 562 void prefixq(Address adr); | |
| 563 | |
| 564 void prefix(Address adr, Register reg, bool byteinst = false); | |
| 4759 | 565 void prefix(Address adr, XMMRegister reg); |
| 304 | 566 void prefixq(Address adr, Register reg); |
| 4759 | 567 void prefixq(Address adr, XMMRegister reg); |
| 304 | 568 |
| 569 void prefetch_prefix(Address src); | |
| 570 | |
| 4759 | 571 void rex_prefix(Address adr, XMMRegister xreg, |
| 572 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 573 int rex_prefix_and_encode(int dst_enc, int src_enc, | |
| 574 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 575 | |
| 576 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, | |
| 577 int nds_enc, VexSimdPrefix pre, VexOpcode opc, | |
| 578 bool vector256); | |
| 579 | |
| 580 void vex_prefix(Address adr, int nds_enc, int xreg_enc, | |
| 581 VexSimdPrefix pre, VexOpcode opc, | |
| 582 bool vex_w, bool vector256); | |
| 583 | |
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584 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
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585 VexSimdPrefix pre, bool vector256 = false) { |
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586 int dst_enc = dst->encoding(); |
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587 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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588 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); |
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589 } |
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590 |
| 4759 | 591 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
| 592 VexSimdPrefix pre, VexOpcode opc, | |
| 593 bool vex_w, bool vector256); | |
| 594 | |
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595 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
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596 VexSimdPrefix pre, bool vector256 = false, |
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597 VexOpcode opc = VEX_OPCODE_0F) { |
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598 int src_enc = src->encoding(); |
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599 int dst_enc = dst->encoding(); |
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600 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
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601 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); |
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602 } |
| 4759 | 603 |
| 604 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, | |
| 605 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 606 bool rex_w = false, bool vector256 = false); | |
| 607 | |
| 608 void simd_prefix(XMMRegister dst, Address src, | |
| 609 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 610 simd_prefix(dst, xnoreg, src, pre, opc); | |
| 611 } | |
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612 |
| 4759 | 613 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
| 614 simd_prefix(src, dst, pre); | |
| 615 } | |
| 616 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, | |
| 617 VexSimdPrefix pre) { | |
| 618 bool rex_w = true; | |
| 619 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); | |
| 620 } | |
| 621 | |
| 622 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, | |
| 623 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 624 bool rex_w = false, bool vector256 = false); | |
| 625 | |
| 626 // Move/convert 32-bit integer value. | |
| 627 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, | |
| 628 VexSimdPrefix pre) { | |
| 629 // It is OK to cast from Register to XMMRegister to pass argument here | |
| 630 // since only encoding is used in simd_prefix_and_encode() and number of | |
| 631 // Gen and Xmm registers are the same. | |
| 632 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); | |
| 633 } | |
| 634 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 635 return simd_prefix_and_encode(dst, xnoreg, src, pre); | |
| 636 } | |
| 637 int simd_prefix_and_encode(Register dst, XMMRegister src, | |
| 638 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 639 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); | |
| 640 } | |
| 641 | |
| 642 // Move/convert 64-bit integer value. | |
| 643 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, | |
| 644 VexSimdPrefix pre) { | |
| 645 bool rex_w = true; | |
| 646 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); | |
| 647 } | |
| 648 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 649 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); | |
| 650 } | |
| 651 int simd_prefix_and_encode_q(Register dst, XMMRegister src, | |
| 652 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 653 bool rex_w = true; | |
| 654 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); | |
| 655 } | |
| 656 | |
| 304 | 657 // Helper functions for groups of instructions |
| 658 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
| 659 | |
| 660 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
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661 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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662 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
| 304 | 663 void emit_arith(int op1, int op2, Register dst, Register src); |
| 664 | |
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665 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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666 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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667 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
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668 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
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669 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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670 Address src, VexSimdPrefix pre, bool vector256); |
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671 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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672 XMMRegister src, VexSimdPrefix pre, bool vector256); |
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673 |
| 304 | 674 void emit_operand(Register reg, |
| 675 Register base, Register index, Address::ScaleFactor scale, | |
| 676 int disp, | |
| 677 RelocationHolder const& rspec, | |
| 678 int rip_relative_correction = 0); | |
| 679 | |
| 680 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
| 681 | |
| 682 // operands that only take the original 32bit registers | |
| 683 void emit_operand32(Register reg, Address adr); | |
| 684 | |
| 685 void emit_operand(XMMRegister reg, | |
| 686 Register base, Register index, Address::ScaleFactor scale, | |
| 687 int disp, | |
| 688 RelocationHolder const& rspec); | |
| 689 | |
| 690 void emit_operand(XMMRegister reg, Address adr); | |
| 691 | |
| 692 void emit_operand(MMXRegister reg, Address adr); | |
| 693 | |
| 694 // workaround gcc (3.2.1-7) bug | |
| 695 void emit_operand(Address adr, MMXRegister reg); | |
| 696 | |
| 697 | |
| 698 // Immediate-to-memory forms | |
| 699 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
| 700 | |
| 701 void emit_farith(int b1, int b2, int i); | |
| 702 | |
| 703 | |
| 704 protected: | |
| 705 #ifdef ASSERT | |
| 706 void check_relocation(RelocationHolder const& rspec, int format); | |
| 707 #endif | |
| 708 | |
| 709 inline void emit_long64(jlong x); | |
| 710 | |
| 711 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
| 712 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
| 713 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
| 714 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
| 715 | |
| 716 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
| 717 | |
| 718 // These are all easily abused and hence protected | |
| 719 | |
| 720 // 32BIT ONLY SECTION | |
| 721 #ifndef _LP64 | |
| 722 // Make these disappear in 64bit mode since they would never be correct | |
| 723 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 724 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 725 | |
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726 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 304 | 727 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 728 | |
| 729 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 730 #else | |
| 731 // 64BIT ONLY SECTION | |
| 732 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
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733 |
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734 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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735 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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736 |
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737 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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738 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
| 304 | 739 #endif // _LP64 |
| 740 | |
| 741 // These are unique in that we are ensured by the caller that the 32bit | |
| 742 // relative in these instructions will always be able to reach the potentially | |
| 743 // 64bit address described by entry. Since they can take a 64bit address they | |
| 744 // don't have the 32 suffix like the other instructions in this class. | |
| 745 | |
| 746 void call_literal(address entry, RelocationHolder const& rspec); | |
| 747 void jmp_literal(address entry, RelocationHolder const& rspec); | |
| 748 | |
| 749 // Avoid using directly section | |
| 750 // Instructions in this section are actually usable by anyone without danger | |
| 751 // of failure but have performance issues that are addressed my enhanced | |
| 752 // instructions which will do the proper thing base on the particular cpu. | |
| 753 // We protect them because we don't trust you... | |
| 754 | |
| 755 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
| 756 // could cause a partial flag stall since they don't set CF flag. | |
| 757 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
| 758 // which call inc() & dec() or add() & sub() in accordance with | |
| 759 // the product flag UseIncDec value. | |
| 760 | |
| 761 void decl(Register dst); | |
| 762 void decl(Address dst); | |
| 763 void decq(Register dst); | |
| 764 void decq(Address dst); | |
| 765 | |
| 766 void incl(Register dst); | |
| 767 void incl(Address dst); | |
| 768 void incq(Register dst); | |
| 769 void incq(Address dst); | |
| 770 | |
| 771 // New cpus require use of movsd and movss to avoid partial register stall | |
| 772 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 773 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 774 | |
| 775 // Move Scalar Single-Precision Floating-Point Values | |
| 776 void movss(XMMRegister dst, Address src); | |
| 777 void movss(XMMRegister dst, XMMRegister src); | |
| 778 void movss(Address dst, XMMRegister src); | |
| 779 | |
| 780 // Move Scalar Double-Precision Floating-Point Values | |
| 781 void movsd(XMMRegister dst, Address src); | |
| 782 void movsd(XMMRegister dst, XMMRegister src); | |
| 783 void movsd(Address dst, XMMRegister src); | |
| 784 void movlpd(XMMRegister dst, Address src); | |
| 785 | |
| 786 // New cpus require use of movaps and movapd to avoid partial register stall | |
| 787 // when moving between registers. | |
| 788 void movaps(XMMRegister dst, XMMRegister src); | |
| 789 void movapd(XMMRegister dst, XMMRegister src); | |
| 790 | |
| 791 // End avoid using directly | |
| 792 | |
| 793 | |
| 794 // Instruction prefixes | |
| 795 void prefix(Prefix p); | |
| 796 | |
| 0 | 797 public: |
| 798 | |
| 799 // Creation | |
| 800 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
| 801 | |
| 802 // Decoding | |
| 803 static address locate_operand(address inst, WhichOperand which); | |
| 804 static address locate_next_instruction(address inst); | |
| 805 | |
| 304 | 806 // Utilities |
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807 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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808 |
| 304 | 809 // Generic instructions |
| 810 // Does 32bit or 64bit as needed for the platform. In some sense these | |
| 811 // belong in macro assembler but there is no need for both varieties to exist | |
| 812 | |
| 813 void lea(Register dst, Address src); | |
| 814 | |
| 815 void mov(Register dst, Register src); | |
| 816 | |
| 817 void pusha(); | |
| 818 void popa(); | |
| 819 | |
| 820 void pushf(); | |
| 821 void popf(); | |
| 822 | |
| 823 void push(int32_t imm32); | |
| 824 | |
| 825 void push(Register src); | |
| 826 | |
| 827 void pop(Register dst); | |
| 828 | |
| 829 // These are dummies to prevent surprise implicit conversions to Register | |
| 830 void push(void* v); | |
| 831 void pop(void* v); | |
| 832 | |
| 833 // These do register sized moves/scans | |
| 834 void rep_mov(); | |
| 835 void rep_set(); | |
| 836 void repne_scan(); | |
| 837 #ifdef _LP64 | |
| 838 void repne_scanl(); | |
| 839 #endif | |
| 840 | |
| 841 // Vanilla instructions in lexical order | |
| 842 | |
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843 void adcl(Address dst, int32_t imm32); |
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844 void adcl(Address dst, Register src); |
| 304 | 845 void adcl(Register dst, int32_t imm32); |
| 0 | 846 void adcl(Register dst, Address src); |
| 847 void adcl(Register dst, Register src); | |
| 848 | |
| 304 | 849 void adcq(Register dst, int32_t imm32); |
| 850 void adcq(Register dst, Address src); | |
| 851 void adcq(Register dst, Register src); | |
| 852 | |
| 853 void addl(Address dst, int32_t imm32); | |
| 0 | 854 void addl(Address dst, Register src); |
| 304 | 855 void addl(Register dst, int32_t imm32); |
| 0 | 856 void addl(Register dst, Address src); |
| 857 void addl(Register dst, Register src); | |
| 858 | |
| 304 | 859 void addq(Address dst, int32_t imm32); |
| 860 void addq(Address dst, Register src); | |
| 861 void addq(Register dst, int32_t imm32); | |
| 862 void addq(Register dst, Address src); | |
| 863 void addq(Register dst, Register src); | |
| 864 | |
| 0 | 865 void addr_nop_4(); |
| 866 void addr_nop_5(); | |
| 867 void addr_nop_7(); | |
| 868 void addr_nop_8(); | |
| 869 | |
| 304 | 870 // Add Scalar Double-Precision Floating-Point Values |
| 871 void addsd(XMMRegister dst, Address src); | |
| 872 void addsd(XMMRegister dst, XMMRegister src); | |
| 873 | |
| 874 // Add Scalar Single-Precision Floating-Point Values | |
| 875 void addss(XMMRegister dst, Address src); | |
| 876 void addss(XMMRegister dst, XMMRegister src); | |
| 877 | |
| 4759 | 878 void andl(Address dst, int32_t imm32); |
| 304 | 879 void andl(Register dst, int32_t imm32); |
| 880 void andl(Register dst, Address src); | |
| 881 void andl(Register dst, Register src); | |
| 882 | |
| 3783 | 883 void andq(Address dst, int32_t imm32); |
| 304 | 884 void andq(Register dst, int32_t imm32); |
| 885 void andq(Register dst, Address src); | |
| 886 void andq(Register dst, Register src); | |
| 887 | |
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888 void bsfl(Register dst, Register src); |
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889 void bsrl(Register dst, Register src); |
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890 |
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891 #ifdef _LP64 |
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892 void bsfq(Register dst, Register src); |
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893 void bsrq(Register dst, Register src); |
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894 #endif |
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895 |
| 304 | 896 void bswapl(Register reg); |
| 897 | |
| 898 void bswapq(Register reg); | |
| 899 | |
| 0 | 900 void call(Label& L, relocInfo::relocType rtype); |
| 901 void call(Register reg); // push pc; pc <- reg | |
| 902 void call(Address adr); // push pc; pc <- adr | |
| 903 | |
| 304 | 904 void cdql(); |
| 905 | |
| 906 void cdqq(); | |
| 907 | |
| 908 void cld() { emit_byte(0xfc); } | |
| 909 | |
| 910 void clflush(Address adr); | |
| 911 | |
| 912 void cmovl(Condition cc, Register dst, Register src); | |
| 913 void cmovl(Condition cc, Register dst, Address src); | |
| 914 | |
| 915 void cmovq(Condition cc, Register dst, Register src); | |
| 916 void cmovq(Condition cc, Register dst, Address src); | |
| 917 | |
| 918 | |
| 919 void cmpb(Address dst, int imm8); | |
| 920 | |
| 921 void cmpl(Address dst, int32_t imm32); | |
| 922 | |
| 923 void cmpl(Register dst, int32_t imm32); | |
| 924 void cmpl(Register dst, Register src); | |
| 925 void cmpl(Register dst, Address src); | |
| 926 | |
| 927 void cmpq(Address dst, int32_t imm32); | |
| 928 void cmpq(Address dst, Register src); | |
| 929 | |
| 930 void cmpq(Register dst, int32_t imm32); | |
| 931 void cmpq(Register dst, Register src); | |
| 932 void cmpq(Register dst, Address src); | |
| 933 | |
| 934 // these are dummies used to catch attempting to convert NULL to Register | |
| 935 void cmpl(Register dst, void* junk); // dummy | |
| 936 void cmpq(Register dst, void* junk); // dummy | |
| 937 | |
| 938 void cmpw(Address dst, int imm16); | |
| 939 | |
| 940 void cmpxchg8 (Address adr); | |
| 941 | |
| 942 void cmpxchgl(Register reg, Address adr); | |
| 943 | |
| 944 void cmpxchgq(Register reg, Address adr); | |
| 945 | |
| 946 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 947 void comisd(XMMRegister dst, Address src); | |
| 4759 | 948 void comisd(XMMRegister dst, XMMRegister src); |
| 304 | 949 |
| 950 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
| 951 void comiss(XMMRegister dst, Address src); | |
| 4759 | 952 void comiss(XMMRegister dst, XMMRegister src); |
| 304 | 953 |
| 954 // Identify processor type and features | |
| 955 void cpuid() { | |
| 956 emit_byte(0x0F); | |
| 957 emit_byte(0xA2); | |
| 958 } | |
| 959 | |
| 960 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
| 961 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
| 4759 | 962 void cvtsd2ss(XMMRegister dst, Address src); |
| 304 | 963 |
| 964 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
| 965 void cvtsi2sdl(XMMRegister dst, Register src); | |
| 4759 | 966 void cvtsi2sdl(XMMRegister dst, Address src); |
| 304 | 967 void cvtsi2sdq(XMMRegister dst, Register src); |
| 4759 | 968 void cvtsi2sdq(XMMRegister dst, Address src); |
| 304 | 969 |
| 970 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
| 971 void cvtsi2ssl(XMMRegister dst, Register src); | |
| 4759 | 972 void cvtsi2ssl(XMMRegister dst, Address src); |
| 304 | 973 void cvtsi2ssq(XMMRegister dst, Register src); |
| 4759 | 974 void cvtsi2ssq(XMMRegister dst, Address src); |
| 304 | 975 |
| 976 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
| 977 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
| 978 | |
| 979 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
| 980 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
| 981 | |
| 982 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
| 983 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
| 4759 | 984 void cvtss2sd(XMMRegister dst, Address src); |
| 304 | 985 |
| 986 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
| 987 void cvttsd2sil(Register dst, Address src); | |
| 988 void cvttsd2sil(Register dst, XMMRegister src); | |
| 989 void cvttsd2siq(Register dst, XMMRegister src); | |
| 990 | |
| 991 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
| 992 void cvttss2sil(Register dst, XMMRegister src); | |
| 993 void cvttss2siq(Register dst, XMMRegister src); | |
| 994 | |
| 995 // Divide Scalar Double-Precision Floating-Point Values | |
| 996 void divsd(XMMRegister dst, Address src); | |
| 997 void divsd(XMMRegister dst, XMMRegister src); | |
| 998 | |
| 999 // Divide Scalar Single-Precision Floating-Point Values | |
| 1000 void divss(XMMRegister dst, Address src); | |
| 1001 void divss(XMMRegister dst, XMMRegister src); | |
| 1002 | |
| 1003 void emms(); | |
| 1004 | |
| 1005 void fabs(); | |
| 1006 | |
| 1007 void fadd(int i); | |
| 1008 | |
| 1009 void fadd_d(Address src); | |
| 1010 void fadd_s(Address src); | |
| 1011 | |
| 1012 // "Alternate" versions of x87 instructions place result down in FPU | |
| 1013 // stack instead of on TOS | |
| 1014 | |
| 1015 void fadda(int i); // "alternate" fadd | |
| 1016 void faddp(int i = 1); | |
| 1017 | |
| 1018 void fchs(); | |
| 1019 | |
| 1020 void fcom(int i); | |
| 1021 | |
| 1022 void fcomp(int i = 1); | |
| 1023 void fcomp_d(Address src); | |
| 1024 void fcomp_s(Address src); | |
| 1025 | |
| 1026 void fcompp(); | |
| 1027 | |
| 1028 void fcos(); | |
| 1029 | |
| 1030 void fdecstp(); | |
| 1031 | |
| 1032 void fdiv(int i); | |
| 1033 void fdiv_d(Address src); | |
| 1034 void fdivr_s(Address src); | |
| 1035 void fdiva(int i); // "alternate" fdiv | |
| 1036 void fdivp(int i = 1); | |
| 1037 | |
| 1038 void fdivr(int i); | |
| 1039 void fdivr_d(Address src); | |
| 1040 void fdiv_s(Address src); | |
| 1041 | |
| 1042 void fdivra(int i); // "alternate" reversed fdiv | |
| 1043 | |
| 1044 void fdivrp(int i = 1); | |
| 1045 | |
| 1046 void ffree(int i = 0); | |
| 1047 | |
| 1048 void fild_d(Address adr); | |
| 1049 void fild_s(Address adr); | |
| 1050 | |
| 1051 void fincstp(); | |
| 1052 | |
| 1053 void finit(); | |
| 1054 | |
| 1055 void fist_s (Address adr); | |
| 1056 void fistp_d(Address adr); | |
| 1057 void fistp_s(Address adr); | |
| 1058 | |
| 1059 void fld1(); | |
| 1060 | |
| 1061 void fld_d(Address adr); | |
| 1062 void fld_s(Address adr); | |
| 1063 void fld_s(int index); | |
| 1064 void fld_x(Address adr); // extended-precision (80-bit) format | |
| 1065 | |
| 1066 void fldcw(Address src); | |
| 1067 | |
| 1068 void fldenv(Address src); | |
| 1069 | |
| 1070 void fldlg2(); | |
| 1071 | |
| 1072 void fldln2(); | |
| 1073 | |
| 1074 void fldz(); | |
| 1075 | |
| 1076 void flog(); | |
| 1077 void flog10(); | |
| 1078 | |
| 1079 void fmul(int i); | |
| 1080 | |
| 1081 void fmul_d(Address src); | |
| 1082 void fmul_s(Address src); | |
| 1083 | |
| 1084 void fmula(int i); // "alternate" fmul | |
| 1085 | |
| 1086 void fmulp(int i = 1); | |
| 1087 | |
| 1088 void fnsave(Address dst); | |
| 1089 | |
| 1090 void fnstcw(Address src); | |
| 1091 | |
| 1092 void fnstsw_ax(); | |
| 1093 | |
| 1094 void fprem(); | |
| 1095 void fprem1(); | |
| 1096 | |
| 1097 void frstor(Address src); | |
| 1098 | |
| 1099 void fsin(); | |
| 1100 | |
| 1101 void fsqrt(); | |
| 1102 | |
| 1103 void fst_d(Address adr); | |
| 1104 void fst_s(Address adr); | |
| 1105 | |
| 1106 void fstp_d(Address adr); | |
| 1107 void fstp_d(int index); | |
| 1108 void fstp_s(Address adr); | |
| 1109 void fstp_x(Address adr); // extended-precision (80-bit) format | |
| 1110 | |
| 1111 void fsub(int i); | |
| 1112 void fsub_d(Address src); | |
| 1113 void fsub_s(Address src); | |
| 1114 | |
| 1115 void fsuba(int i); // "alternate" fsub | |
| 1116 | |
| 1117 void fsubp(int i = 1); | |
| 1118 | |
| 1119 void fsubr(int i); | |
| 1120 void fsubr_d(Address src); | |
| 1121 void fsubr_s(Address src); | |
| 1122 | |
| 1123 void fsubra(int i); // "alternate" reversed fsub | |
| 1124 | |
| 1125 void fsubrp(int i = 1); | |
| 1126 | |
| 1127 void ftan(); | |
| 1128 | |
| 1129 void ftst(); | |
| 1130 | |
| 1131 void fucomi(int i = 1); | |
| 1132 void fucomip(int i = 1); | |
| 1133 | |
| 1134 void fwait(); | |
| 1135 | |
| 1136 void fxch(int i = 1); | |
| 1137 | |
| 1138 void fxrstor(Address src); | |
| 1139 | |
| 1140 void fxsave(Address dst); | |
| 1141 | |
| 1142 void fyl2x(); | |
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1143 void frndint(); |
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1144 void f2xm1(); |
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1145 void fldl2e(); |
| 304 | 1146 |
| 1147 void hlt(); | |
| 1148 | |
| 1149 void idivl(Register src); | |
| 1920 | 1150 void divl(Register src); // Unsigned division |
| 304 | 1151 |
| 1152 void idivq(Register src); | |
| 1153 | |
| 1154 void imull(Register dst, Register src); | |
| 1155 void imull(Register dst, Register src, int value); | |
| 1156 | |
| 1157 void imulq(Register dst, Register src); | |
| 1158 void imulq(Register dst, Register src, int value); | |
| 1159 | |
| 0 | 1160 |
| 1161 // jcc is the generic conditional branch generator to run- | |
| 1162 // time routines, jcc is used for branches to labels. jcc | |
| 1163 // takes a branch opcode (cc) and a label (L) and generates | |
| 1164 // either a backward branch or a forward branch and links it | |
| 1165 // to the label fixup chain. Usage: | |
| 1166 // | |
| 1167 // Label L; // unbound label | |
| 1168 // jcc(cc, L); // forward branch to unbound label | |
| 1169 // bind(L); // bind label to the current pc | |
| 1170 // jcc(cc, L); // backward branch to bound label | |
| 1171 // bind(L); // illegal: a label may be bound only once | |
| 1172 // | |
| 1173 // Note: The same Label can be used for forward and backward branches | |
| 1174 // but it may be bound only once. | |
| 1175 | |
| 3851 | 1176 void jcc(Condition cc, Label& L, bool maybe_short = true); |
| 0 | 1177 |
| 1178 // Conditional jump to a 8-bit offset to L. | |
| 1179 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1180 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1181 // will occur. | |
| 1182 void jccb(Condition cc, Label& L); | |
| 1183 | |
| 304 | 1184 void jmp(Address entry); // pc <- entry |
| 1185 | |
| 1186 // Label operations & relative jumps (PPUM Appendix D) | |
| 3851 | 1187 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
| 304 | 1188 |
| 1189 void jmp(Register entry); // pc <- entry | |
| 1190 | |
| 1191 // Unconditional 8-bit offset jump to L. | |
| 1192 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1193 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1194 // will occur. | |
| 1195 void jmpb(Label& L); | |
| 1196 | |
| 1197 void ldmxcsr( Address src ); | |
| 1198 | |
| 1199 void leal(Register dst, Address src); | |
| 1200 | |
| 1201 void leaq(Register dst, Address src); | |
| 1202 | |
| 1203 void lfence() { | |
| 1204 emit_byte(0x0F); | |
| 1205 emit_byte(0xAE); | |
| 1206 emit_byte(0xE8); | |
| 1207 } | |
| 1208 | |
| 1209 void lock(); | |
| 1210 | |
|
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1211 void lzcntl(Register dst, Register src); |
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1212 |
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1213 #ifdef _LP64 |
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1214 void lzcntq(Register dst, Register src); |
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1215 #endif |
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1216 |
| 304 | 1217 enum Membar_mask_bits { |
| 1218 StoreStore = 1 << 3, | |
| 1219 LoadStore = 1 << 2, | |
| 1220 StoreLoad = 1 << 1, | |
| 1221 LoadLoad = 1 << 0 | |
| 1222 }; | |
| 1223 | |
|
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1224 // Serializes memory and blows flags |
| 304 | 1225 void membar(Membar_mask_bits order_constraint) { |
|
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1226 if (os::is_MP()) { |
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1227 // We only have to handle StoreLoad |
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1228 if (order_constraint & StoreLoad) { |
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1229 // All usable chips support "locked" instructions which suffice |
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1230 // as barriers, and are much faster than the alternative of |
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1231 // using cpuid instruction. We use here a locked add [esp],0. |
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1232 // This is conveniently otherwise a no-op except for blowing |
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1233 // flags. |
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1234 // Any change to this code may need to revisit other places in |
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1235 // the code where this idiom is used, in particular the |
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|
1236 // orderAccess code. |
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|
1237 lock(); |
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1238 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1239 } |
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|
1240 } |
| 304 | 1241 } |
| 1242 | |
| 1243 void mfence(); | |
| 1244 | |
| 1245 // Moves | |
| 1246 | |
| 1247 void mov64(Register dst, int64_t imm64); | |
| 1248 | |
| 1249 void movb(Address dst, Register src); | |
| 1250 void movb(Address dst, int imm8); | |
| 1251 void movb(Register dst, Address src); | |
| 1252 | |
| 1253 void movdl(XMMRegister dst, Register src); | |
| 1254 void movdl(Register dst, XMMRegister src); | |
|
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1255 void movdl(XMMRegister dst, Address src); |
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1256 void movdl(Address dst, XMMRegister src); |
| 304 | 1257 |
| 1258 // Move Double Quadword | |
| 1259 void movdq(XMMRegister dst, Register src); | |
| 1260 void movdq(Register dst, XMMRegister src); | |
| 1261 | |
| 1262 // Move Aligned Double Quadword | |
| 1263 void movdqa(XMMRegister dst, XMMRegister src); | |
| 1264 | |
| 405 | 1265 // Move Unaligned Double Quadword |
| 1266 void movdqu(Address dst, XMMRegister src); | |
| 1267 void movdqu(XMMRegister dst, Address src); | |
| 1268 void movdqu(XMMRegister dst, XMMRegister src); | |
| 1269 | |
|
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1270 // Move Unaligned 256bit Vector |
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1271 void vmovdqu(Address dst, XMMRegister src); |
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1272 void vmovdqu(XMMRegister dst, Address src); |
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1273 void vmovdqu(XMMRegister dst, XMMRegister src); |
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1274 |
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1275 // Move lower 64bit to high 64bit in 128bit register |
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1276 void movlhps(XMMRegister dst, XMMRegister src); |
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1277 |
| 304 | 1278 void movl(Register dst, int32_t imm32); |
| 1279 void movl(Address dst, int32_t imm32); | |
| 1280 void movl(Register dst, Register src); | |
| 1281 void movl(Register dst, Address src); | |
| 1282 void movl(Address dst, Register src); | |
| 1283 | |
| 1284 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
| 1285 // by giving the compiler two choices it can't resolve | |
| 1286 | |
| 1287 void movl(Address dst, void* junk); | |
| 1288 void movl(Register dst, void* junk); | |
| 1289 | |
| 1290 #ifdef _LP64 | |
| 1291 void movq(Register dst, Register src); | |
| 1292 void movq(Register dst, Address src); | |
|
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1293 void movq(Address dst, Register src); |
| 304 | 1294 #endif |
| 1295 | |
| 1296 void movq(Address dst, MMXRegister src ); | |
| 1297 void movq(MMXRegister dst, Address src ); | |
| 1298 | |
| 1299 #ifdef _LP64 | |
| 1300 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
| 1301 // by giving the compiler two choices it can't resolve | |
| 1302 | |
| 1303 void movq(Address dst, void* dummy); | |
| 1304 void movq(Register dst, void* dummy); | |
| 1305 #endif | |
| 1306 | |
| 1307 // Move Quadword | |
| 1308 void movq(Address dst, XMMRegister src); | |
| 1309 void movq(XMMRegister dst, Address src); | |
| 1310 | |
| 1311 void movsbl(Register dst, Address src); | |
| 1312 void movsbl(Register dst, Register src); | |
| 1313 | |
| 1314 #ifdef _LP64 | |
| 624 | 1315 void movsbq(Register dst, Address src); |
| 1316 void movsbq(Register dst, Register src); | |
| 1317 | |
| 304 | 1318 // Move signed 32bit immediate to 64bit extending sign |
|
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1319 void movslq(Address dst, int32_t imm64); |
| 304 | 1320 void movslq(Register dst, int32_t imm64); |
| 1321 | |
| 1322 void movslq(Register dst, Address src); | |
| 1323 void movslq(Register dst, Register src); | |
| 1324 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
| 1325 #endif | |
| 1326 | |
| 1327 void movswl(Register dst, Address src); | |
| 1328 void movswl(Register dst, Register src); | |
| 1329 | |
| 624 | 1330 #ifdef _LP64 |
| 1331 void movswq(Register dst, Address src); | |
| 1332 void movswq(Register dst, Register src); | |
| 1333 #endif | |
| 1334 | |
| 304 | 1335 void movw(Address dst, int imm16); |
| 1336 void movw(Register dst, Address src); | |
| 1337 void movw(Address dst, Register src); | |
| 1338 | |
| 1339 void movzbl(Register dst, Address src); | |
| 1340 void movzbl(Register dst, Register src); | |
| 1341 | |
| 624 | 1342 #ifdef _LP64 |
| 1343 void movzbq(Register dst, Address src); | |
| 1344 void movzbq(Register dst, Register src); | |
| 1345 #endif | |
| 1346 | |
| 304 | 1347 void movzwl(Register dst, Address src); |
| 1348 void movzwl(Register dst, Register src); | |
| 1349 | |
| 624 | 1350 #ifdef _LP64 |
| 1351 void movzwq(Register dst, Address src); | |
| 1352 void movzwq(Register dst, Register src); | |
| 1353 #endif | |
| 1354 | |
| 304 | 1355 void mull(Address src); |
| 1356 void mull(Register src); | |
| 1357 | |
| 1358 // Multiply Scalar Double-Precision Floating-Point Values | |
| 1359 void mulsd(XMMRegister dst, Address src); | |
| 1360 void mulsd(XMMRegister dst, XMMRegister src); | |
| 1361 | |
| 1362 // Multiply Scalar Single-Precision Floating-Point Values | |
| 1363 void mulss(XMMRegister dst, Address src); | |
| 1364 void mulss(XMMRegister dst, XMMRegister src); | |
| 1365 | |
| 1366 void negl(Register dst); | |
| 1367 | |
| 1368 #ifdef _LP64 | |
| 1369 void negq(Register dst); | |
| 1370 #endif | |
| 1371 | |
| 1372 void nop(int i = 1); | |
| 1373 | |
| 1374 void notl(Register dst); | |
| 1375 | |
| 1376 #ifdef _LP64 | |
| 1377 void notq(Register dst); | |
| 1378 #endif | |
| 1379 | |
| 1380 void orl(Address dst, int32_t imm32); | |
| 1381 void orl(Register dst, int32_t imm32); | |
| 1382 void orl(Register dst, Address src); | |
| 1383 void orl(Register dst, Register src); | |
| 1384 | |
| 1385 void orq(Address dst, int32_t imm32); | |
| 1386 void orq(Register dst, int32_t imm32); | |
| 1387 void orq(Register dst, Address src); | |
| 1388 void orq(Register dst, Register src); | |
| 1389 | |
| 4759 | 1390 // Pack with unsigned saturation |
| 1391 void packuswb(XMMRegister dst, XMMRegister src); | |
| 1392 void packuswb(XMMRegister dst, Address src); | |
| 1393 | |
| 681 | 1394 // SSE4.2 string instructions |
| 1395 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
| 1396 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
| 1397 | |
| 4759 | 1398 // SSE4.1 packed move |
| 1399 void pmovzxbw(XMMRegister dst, XMMRegister src); | |
| 1400 void pmovzxbw(XMMRegister dst, Address src); | |
| 1401 | |
| 1060 | 1402 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1403 void popl(Address dst); |
| 1060 | 1404 #endif |
| 304 | 1405 |
| 1406 #ifdef _LP64 | |
| 1407 void popq(Address dst); | |
| 1408 #endif | |
| 1409 | |
|
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1410 void popcntl(Register dst, Address src); |
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1411 void popcntl(Register dst, Register src); |
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1412 |
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1413 #ifdef _LP64 |
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1414 void popcntq(Register dst, Address src); |
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1415 void popcntq(Register dst, Register src); |
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1416 #endif |
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1417 |
| 304 | 1418 // Prefetches (SSE, SSE2, 3DNOW only) |
| 1419 | |
| 1420 void prefetchnta(Address src); | |
| 1421 void prefetchr(Address src); | |
| 1422 void prefetcht0(Address src); | |
| 1423 void prefetcht1(Address src); | |
| 1424 void prefetcht2(Address src); | |
| 1425 void prefetchw(Address src); | |
| 1426 | |
| 1427 // Shuffle Packed Doublewords | |
| 1428 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
| 1429 void pshufd(XMMRegister dst, Address src, int mode); | |
| 1430 | |
| 1431 // Shuffle Packed Low Words | |
| 1432 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
| 1433 void pshuflw(XMMRegister dst, Address src, int mode); | |
| 1434 | |
|
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1435 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1436 void psrldq(XMMRegister dst, int shift); |
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1437 |
| 681 | 1438 // Logical Compare Double Quadword |
| 1439 void ptest(XMMRegister dst, XMMRegister src); | |
| 1440 void ptest(XMMRegister dst, Address src); | |
| 1441 | |
| 304 | 1442 // Interleave Low Bytes |
| 1443 void punpcklbw(XMMRegister dst, XMMRegister src); | |
| 4759 | 1444 void punpcklbw(XMMRegister dst, Address src); |
| 1445 | |
| 1446 // Interleave Low Doublewords | |
| 1447 void punpckldq(XMMRegister dst, XMMRegister src); | |
| 1448 void punpckldq(XMMRegister dst, Address src); | |
| 304 | 1449 |
| 6225 | 1450 // Interleave Low Quadwords |
| 1451 void punpcklqdq(XMMRegister dst, XMMRegister src); | |
| 1452 | |
| 1060 | 1453 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1454 void pushl(Address src); |
| 1060 | 1455 #endif |
| 304 | 1456 |
| 1457 void pushq(Address src); | |
| 1458 | |
| 1459 void rcll(Register dst, int imm8); | |
| 1460 | |
| 1461 void rclq(Register dst, int imm8); | |
| 1462 | |
| 1463 void ret(int imm16); | |
| 0 | 1464 |
| 1465 void sahf(); | |
| 1466 | |
| 304 | 1467 void sarl(Register dst, int imm8); |
| 1468 void sarl(Register dst); | |
| 1469 | |
| 1470 void sarq(Register dst, int imm8); | |
| 1471 void sarq(Register dst); | |
| 1472 | |
| 1473 void sbbl(Address dst, int32_t imm32); | |
| 1474 void sbbl(Register dst, int32_t imm32); | |
| 1475 void sbbl(Register dst, Address src); | |
| 1476 void sbbl(Register dst, Register src); | |
| 1477 | |
| 1478 void sbbq(Address dst, int32_t imm32); | |
| 1479 void sbbq(Register dst, int32_t imm32); | |
| 1480 void sbbq(Register dst, Address src); | |
| 1481 void sbbq(Register dst, Register src); | |
| 1482 | |
| 1483 void setb(Condition cc, Register dst); | |
| 1484 | |
| 1485 void shldl(Register dst, Register src); | |
| 1486 | |
| 1487 void shll(Register dst, int imm8); | |
| 1488 void shll(Register dst); | |
| 1489 | |
| 1490 void shlq(Register dst, int imm8); | |
| 1491 void shlq(Register dst); | |
| 1492 | |
| 1493 void shrdl(Register dst, Register src); | |
| 1494 | |
| 1495 void shrl(Register dst, int imm8); | |
| 1496 void shrl(Register dst); | |
| 1497 | |
| 1498 void shrq(Register dst, int imm8); | |
| 1499 void shrq(Register dst); | |
| 1500 | |
| 1501 void smovl(); // QQQ generic? | |
| 1502 | |
| 1503 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
| 1504 void sqrtsd(XMMRegister dst, Address src); | |
| 1505 void sqrtsd(XMMRegister dst, XMMRegister src); | |
| 1506 | |
| 2008 | 1507 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
| 1508 void sqrtss(XMMRegister dst, Address src); | |
| 1509 void sqrtss(XMMRegister dst, XMMRegister src); | |
| 1510 | |
| 304 | 1511 void std() { emit_byte(0xfd); } |
| 1512 | |
| 1513 void stmxcsr( Address dst ); | |
| 1514 | |
| 1515 void subl(Address dst, int32_t imm32); | |
| 1516 void subl(Address dst, Register src); | |
| 1517 void subl(Register dst, int32_t imm32); | |
| 1518 void subl(Register dst, Address src); | |
| 1519 void subl(Register dst, Register src); | |
| 1520 | |
| 1521 void subq(Address dst, int32_t imm32); | |
| 1522 void subq(Address dst, Register src); | |
| 1523 void subq(Register dst, int32_t imm32); | |
| 1524 void subq(Register dst, Address src); | |
| 1525 void subq(Register dst, Register src); | |
| 1526 | |
|
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|
1527 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
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|
1528 void subl_imm32(Register dst, int32_t imm32); |
|
fd8114661503
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|
1529 void subq_imm32(Register dst, int32_t imm32); |
| 304 | 1530 |
| 1531 // Subtract Scalar Double-Precision Floating-Point Values | |
| 1532 void subsd(XMMRegister dst, Address src); | |
| 0 | 1533 void subsd(XMMRegister dst, XMMRegister src); |
| 1534 | |
| 304 | 1535 // Subtract Scalar Single-Precision Floating-Point Values |
| 1536 void subss(XMMRegister dst, Address src); | |
| 1537 void subss(XMMRegister dst, XMMRegister src); | |
| 1538 | |
| 1539 void testb(Register dst, int imm8); | |
| 1540 | |
| 1541 void testl(Register dst, int32_t imm32); | |
| 1542 void testl(Register dst, Register src); | |
| 1543 void testl(Register dst, Address src); | |
| 1544 | |
| 1545 void testq(Register dst, int32_t imm32); | |
| 1546 void testq(Register dst, Register src); | |
| 1547 | |
| 1548 | |
| 1549 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 1550 void ucomisd(XMMRegister dst, Address src); | |
| 0 | 1551 void ucomisd(XMMRegister dst, XMMRegister src); |
| 1552 | |
| 304 | 1553 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
| 1554 void ucomiss(XMMRegister dst, Address src); | |
| 1555 void ucomiss(XMMRegister dst, XMMRegister src); | |
| 1556 | |
| 1557 void xaddl(Address dst, Register src); | |
| 1558 | |
| 1559 void xaddq(Address dst, Register src); | |
| 1560 | |
| 1561 void xchgl(Register reg, Address adr); | |
| 1562 void xchgl(Register dst, Register src); | |
| 1563 | |
| 1564 void xchgq(Register reg, Address adr); | |
| 1565 void xchgq(Register dst, Register src); | |
| 1566 | |
| 4759 | 1567 // Get Value of Extended Control Register |
| 1568 void xgetbv() { | |
| 1569 emit_byte(0x0F); | |
| 1570 emit_byte(0x01); | |
| 1571 emit_byte(0xD0); | |
| 1572 } | |
| 1573 | |
| 304 | 1574 void xorl(Register dst, int32_t imm32); |
| 1575 void xorl(Register dst, Address src); | |
| 1576 void xorl(Register dst, Register src); | |
| 1577 | |
| 1578 void xorq(Register dst, Address src); | |
| 1579 void xorq(Register dst, Register src); | |
| 1580 | |
| 1581 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
| 4759 | 1582 |
| 6225 | 1583 // AVX 3-operands scalar instructions (encoded with VEX prefix) |
|
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|
1584 |
|
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|
1585 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
|
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|
1586 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1587 void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
|
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
1588 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
1589 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
|
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
1590 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1591 void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
|
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|
1592 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1593 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
|
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|
1594 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1595 void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
|
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|
1596 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1597 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
|
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changeset
|
1598 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1599 void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
|
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|
1600 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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|
1601 |
|
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|
1602 |
|
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|
1603 //====================VECTOR ARITHMETIC===================================== |
|
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|
1604 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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|
1605 // Add Packed Floating-Point Values |
|
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6340864: Implement vectorization optimizations in hotspot-server
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|
1606 void addpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
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|
1607 void addps(XMMRegister dst, XMMRegister src); |
|
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6340864: Implement vectorization optimizations in hotspot-server
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|
1608 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1609 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1610 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
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changeset
|
1611 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1612 |
|
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6340864: Implement vectorization optimizations in hotspot-server
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|
1613 // Subtract Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1614 void subpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1615 void subps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1616 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1617 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1618 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1619 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1620 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1621 // Multiply Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1622 void mulpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1623 void mulps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1624 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1625 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1626 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1627 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1628 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1629 // Divide Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1630 void divpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1631 void divps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1632 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1633 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1634 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1635 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1636 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1637 // Bitwise Logical AND of Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1638 void andpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1639 void andps(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1640 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1641 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1642 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1643 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1644 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1645 // Bitwise Logical XOR of Packed Floating-Point Values |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1646 void xorpd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1647 void xorps(XMMRegister dst, XMMRegister src); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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6141
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changeset
|
1648 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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6141
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changeset
|
1649 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1650 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1651 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1652 |
|
006050192a5a
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|
1653 // Add packed integers |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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|
1654 void paddb(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1655 void paddw(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1656 void paddd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1657 void paddq(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1658 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1659 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1660 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1661 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1662 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1663 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1664 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1665 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1666 |
|
006050192a5a
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changeset
|
1667 // Sub packed integers |
|
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6340864: Implement vectorization optimizations in hotspot-server
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|
1668 void psubb(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1669 void psubw(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1670 void psubd(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1671 void psubq(XMMRegister dst, XMMRegister src); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1672 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1673 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1674 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1675 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1676 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1677 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1678 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
1679 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1680 |
|
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|
1681 // Multiply packed integers (only shorts and ints) |
|
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|
1682 void pmullw(XMMRegister dst, XMMRegister src); |
|
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|
1683 void pmulld(XMMRegister dst, XMMRegister src); |
|
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|
1684 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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|
1685 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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1686 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1687 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1688 |
|
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|
1689 // Shift left packed integers |
|
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|
1690 void psllw(XMMRegister dst, int shift); |
|
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1691 void pslld(XMMRegister dst, int shift); |
|
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1692 void psllq(XMMRegister dst, int shift); |
|
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|
1693 void psllw(XMMRegister dst, XMMRegister shift); |
|
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|
1694 void pslld(XMMRegister dst, XMMRegister shift); |
|
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|
1695 void psllq(XMMRegister dst, XMMRegister shift); |
|
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|
1696 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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|
1697 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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|
1698 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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|
1699 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1700 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1701 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1702 |
|
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|
1703 // Logical shift right packed integers |
|
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|
1704 void psrlw(XMMRegister dst, int shift); |
|
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|
1705 void psrld(XMMRegister dst, int shift); |
|
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|
1706 void psrlq(XMMRegister dst, int shift); |
|
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|
1707 void psrlw(XMMRegister dst, XMMRegister shift); |
|
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|
1708 void psrld(XMMRegister dst, XMMRegister shift); |
|
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|
1709 void psrlq(XMMRegister dst, XMMRegister shift); |
|
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|
1710 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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1711 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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1712 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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1713 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1714 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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1715 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1716 |
|
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1717 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
|
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1718 void psraw(XMMRegister dst, int shift); |
|
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1719 void psrad(XMMRegister dst, int shift); |
|
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1720 void psraw(XMMRegister dst, XMMRegister shift); |
|
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1721 void psrad(XMMRegister dst, XMMRegister shift); |
|
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1722 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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1723 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
|
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1724 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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1725 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
|
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|
1726 |
|
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1727 // And packed integers |
|
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1728 void pand(XMMRegister dst, XMMRegister src); |
|
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|
1729 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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1730 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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1731 |
|
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1732 // Or packed integers |
|
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|
1733 void por(XMMRegister dst, XMMRegister src); |
|
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1734 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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1735 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1736 |
|
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1737 // Xor packed integers |
|
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|
1738 void pxor(XMMRegister dst, XMMRegister src); |
| 6225 | 1739 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
|
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1740 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
|
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|
1741 |
|
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1742 // Copy low 128bit into high 128bit of YMM registers. |
|
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1743 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
| 6225 | 1744 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
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1745 |
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1746 // AVX instruction which is used to clear upper 128 bits of YMM registers and |
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1747 // to avoid transaction penalty between AVX and SSE states. There is no |
|
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1748 // penalty if legacy SSE instructions are encoded using VEX prefix because |
|
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1749 // they always clear upper 128 bits. It should be used before calling |
|
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1750 // runtime code and native libraries. |
|
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|
1751 void vzeroupper(); |
|
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1752 |
| 4759 | 1753 protected: |
| 1754 // Next instructions require address alignment 16 bytes SSE mode. | |
| 1755 // They should be called only from corresponding MacroAssembler instructions. | |
| 1756 void andpd(XMMRegister dst, Address src); | |
| 1757 void andps(XMMRegister dst, Address src); | |
| 1758 void xorpd(XMMRegister dst, Address src); | |
| 1759 void xorps(XMMRegister dst, Address src); | |
| 1760 | |
| 0 | 1761 }; |
| 1762 | |
| 1763 | |
| 1764 // MacroAssembler extends Assembler by frequently used macros. | |
| 1765 // | |
| 1766 // Instructions for which a 'better' code sequence exists depending | |
| 1767 // on arguments should also go in here. | |
| 1768 | |
| 1769 class MacroAssembler: public Assembler { | |
|
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1770 friend class LIR_Assembler; |
|
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1771 friend class Runtime1; // as_Address() |
|
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1772 |
| 0 | 1773 protected: |
| 1774 | |
| 1775 Address as_Address(AddressLiteral adr); | |
| 1776 Address as_Address(ArrayAddress adr); | |
| 1777 | |
| 1778 // Support for VM calls | |
| 1779 // | |
| 1780 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
| 1781 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
| 1782 // additional registers when doing a VM call). | |
| 1783 #ifdef CC_INTERP | |
| 1784 // c++ interpreter never wants to use interp_masm version of call_VM | |
| 1785 #define VIRTUAL | |
| 1786 #else | |
| 1787 #define VIRTUAL virtual | |
| 1788 #endif | |
| 1789 | |
| 1790 VIRTUAL void call_VM_leaf_base( | |
| 1791 address entry_point, // the entry point | |
| 1792 int number_of_arguments // the number of arguments to pop after the call | |
| 1793 ); | |
| 1794 | |
| 1795 // This is the base routine called by the different versions of call_VM. The interpreter | |
| 1796 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
| 1797 // additional registers when doing a VM call). | |
| 1798 // | |
| 1799 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
| 1800 // returns the register which contains the thread upon return. If a thread register has been | |
| 1801 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
| 1802 // (noreg) than rsp will be used instead. | |
| 1803 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
| 1804 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
| 1805 Register java_thread, // the thread if computed before ; use noreg otherwise | |
| 1806 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
| 1807 address entry_point, // the entry point | |
| 1808 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
| 1809 bool check_exceptions // whether to check for pending exceptions after return | |
| 1810 ); | |
| 1811 | |
| 1812 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
| 1813 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
| 1814 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
| 1815 virtual void check_and_handle_popframe(Register java_thread); | |
| 1816 virtual void check_and_handle_earlyret(Register java_thread); | |
| 1817 | |
| 1818 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
| 1819 | |
| 1820 // helpers for FPU flag access | |
| 1821 // tmp is a temporary register, if none is available use noreg | |
| 1822 void save_rax (Register tmp); | |
| 1823 void restore_rax(Register tmp); | |
| 1824 | |
| 1825 public: | |
| 1826 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
| 1827 | |
| 1828 // Support for NULL-checks | |
| 1829 // | |
| 1830 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
| 1831 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
| 1832 // offset. No explicit code generation is needed if the offset is within a certain | |
| 1833 // range (0 <= offset <= page_size). | |
| 1834 | |
| 1835 void null_check(Register reg, int offset = -1); | |
|
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1836 static bool needs_explicit_null_check(intptr_t offset); |
| 0 | 1837 |
| 1838 // Required platform-specific helpers for Label::patch_instructions. | |
| 1839 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
| 1840 void pd_patch_instruction(address branch, address target); | |
| 1841 #ifndef PRODUCT | |
| 1842 static void pd_print_patched_instruction(address branch); | |
| 1843 #endif | |
| 1844 | |
| 1845 // The following 4 methods return the offset of the appropriate move instruction | |
| 1846 | |
|
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1847 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
| 0 | 1848 int load_unsigned_byte(Register dst, Address src); |
|
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1849 int load_unsigned_short(Register dst, Address src); |
|
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1850 |
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1851 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
| 0 | 1852 int load_signed_byte(Register dst, Address src); |
|
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1853 int load_signed_short(Register dst, Address src); |
| 0 | 1854 |
| 1855 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
| 1856 void extend_sign(Register hi, Register lo); | |
| 1857 | |
|
2258
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|
1858 // Load and store values by size and signed-ness |
|
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|
1859 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
|
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1860 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
|
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1861 |
| 0 | 1862 // Support for inc/dec with optimal instruction selection depending on value |
| 304 | 1863 |
| 1864 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
| 1865 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
| 1866 | |
| 1867 void decrementl(Address dst, int value = 1); | |
| 1868 void decrementl(Register reg, int value = 1); | |
| 1869 | |
| 1870 void decrementq(Register reg, int value = 1); | |
| 1871 void decrementq(Address dst, int value = 1); | |
| 1872 | |
| 1873 void incrementl(Address dst, int value = 1); | |
| 1874 void incrementl(Register reg, int value = 1); | |
| 1875 | |
| 1876 void incrementq(Register reg, int value = 1); | |
| 1877 void incrementq(Address dst, int value = 1); | |
| 1878 | |
| 0 | 1879 |
| 1880 // Support optimal SSE move instructions. | |
| 1881 void movflt(XMMRegister dst, XMMRegister src) { | |
| 1882 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
| 1883 else { movss (dst, src); return; } | |
| 1884 } | |
| 1885 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
| 1886 void movflt(XMMRegister dst, AddressLiteral src); | |
| 1887 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
| 1888 | |
| 1889 void movdbl(XMMRegister dst, XMMRegister src) { | |
| 1890 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
| 1891 else { movsd (dst, src); return; } | |
| 1892 } | |
| 1893 | |
| 1894 void movdbl(XMMRegister dst, AddressLiteral src); | |
| 1895 | |
| 1896 void movdbl(XMMRegister dst, Address src) { | |
| 1897 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
| 1898 else { movlpd(dst, src); return; } | |
| 1899 } | |
| 1900 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
| 1901 | |
| 304 | 1902 void incrementl(AddressLiteral dst); |
| 1903 void incrementl(ArrayAddress dst); | |
| 0 | 1904 |
| 1905 // Alignment | |
| 1906 void align(int modulus); | |
| 1907 | |
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1908 // A 5 byte nop that is safe for patching (see patch_verified_entry) |
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1909 void fat_nop(); |
| 0 | 1910 |
| 1911 // Stack frame creation/removal | |
| 1912 void enter(); | |
| 1913 void leave(); | |
| 1914 | |
| 1915 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
| 1916 // The pointer will be loaded into the thread register. | |
| 1917 void get_thread(Register thread); | |
| 1918 | |
| 362 | 1919 |
| 0 | 1920 // Support for VM calls |
| 1921 // | |
| 1922 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
| 1923 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
| 1924 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
| 1925 | |
| 304 | 1926 |
| 1927 void call_VM(Register oop_result, | |
| 1928 address entry_point, | |
| 1929 bool check_exceptions = true); | |
| 1930 void call_VM(Register oop_result, | |
| 1931 address entry_point, | |
| 1932 Register arg_1, | |
| 1933 bool check_exceptions = true); | |
| 1934 void call_VM(Register oop_result, | |
| 1935 address entry_point, | |
| 1936 Register arg_1, Register arg_2, | |
| 1937 bool check_exceptions = true); | |
| 1938 void call_VM(Register oop_result, | |
| 1939 address entry_point, | |
| 1940 Register arg_1, Register arg_2, Register arg_3, | |
| 1941 bool check_exceptions = true); | |
| 1942 | |
| 1943 // Overloadings with last_Java_sp | |
| 1944 void call_VM(Register oop_result, | |
| 1945 Register last_java_sp, | |
| 1946 address entry_point, | |
| 1947 int number_of_arguments = 0, | |
| 1948 bool check_exceptions = true); | |
| 1949 void call_VM(Register oop_result, | |
| 1950 Register last_java_sp, | |
| 1951 address entry_point, | |
| 1952 Register arg_1, bool | |
| 1953 check_exceptions = true); | |
| 1954 void call_VM(Register oop_result, | |
| 1955 Register last_java_sp, | |
| 1956 address entry_point, | |
| 1957 Register arg_1, Register arg_2, | |
| 1958 bool check_exceptions = true); | |
| 1959 void call_VM(Register oop_result, | |
| 1960 Register last_java_sp, | |
| 1961 address entry_point, | |
| 1962 Register arg_1, Register arg_2, Register arg_3, | |
| 1963 bool check_exceptions = true); | |
| 1964 | |
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1965 void get_vm_result (Register oop_result, Register thread); |
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1966 void get_vm_result_2(Register metadata_result, Register thread); |
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1967 |
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1968 // These always tightly bind to MacroAssembler::call_VM_base |
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1969 // bypassing the virtual implementation |
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1970 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
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1971 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
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1972 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
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1973 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
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1974 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
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1975 |
| 304 | 1976 void call_VM_leaf(address entry_point, |
| 1977 int number_of_arguments = 0); | |
| 1978 void call_VM_leaf(address entry_point, | |
| 1979 Register arg_1); | |
| 1980 void call_VM_leaf(address entry_point, | |
| 1981 Register arg_1, Register arg_2); | |
| 1982 void call_VM_leaf(address entry_point, | |
| 1983 Register arg_1, Register arg_2, Register arg_3); | |
| 0 | 1984 |
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1985 // These always tightly bind to MacroAssembler::call_VM_leaf_base |
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1986 // bypassing the virtual implementation |
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1987 void super_call_VM_leaf(address entry_point); |
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1988 void super_call_VM_leaf(address entry_point, Register arg_1); |
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1989 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
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1990 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
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1991 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
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1992 |
| 0 | 1993 // last Java Frame (fills frame anchor) |
| 304 | 1994 void set_last_Java_frame(Register thread, |
| 1995 Register last_java_sp, | |
| 1996 Register last_java_fp, | |
| 1997 address last_java_pc); | |
| 1998 | |
| 1999 // thread in the default location (r15_thread on 64bit) | |
| 2000 void set_last_Java_frame(Register last_java_sp, | |
| 2001 Register last_java_fp, | |
| 2002 address last_java_pc); | |
| 2003 | |
| 0 | 2004 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
| 2005 | |
| 304 | 2006 // thread in the default location (r15_thread on 64bit) |
| 2007 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
| 2008 | |
| 0 | 2009 // Stores |
| 2010 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
| 2011 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
| 2012 | |
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2013 #ifndef SERIALGC |
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2014 |
| 362 | 2015 void g1_write_barrier_pre(Register obj, |
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2016 Register pre_val, |
| 362 | 2017 Register thread, |
| 2018 Register tmp, | |
|
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2019 bool tosca_live, |
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2020 bool expand_call); |
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2021 |
| 362 | 2022 void g1_write_barrier_post(Register store_addr, |
| 2023 Register new_val, | |
| 2024 Register thread, | |
| 2025 Register tmp, | |
| 2026 Register tmp2); | |
|
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2027 |
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2028 #endif // SERIALGC |
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2029 |
| 0 | 2030 // split store_check(Register obj) to enhance instruction interleaving |
| 2031 void store_check_part_1(Register obj); | |
| 2032 void store_check_part_2(Register obj); | |
| 2033 | |
| 2034 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
| 2035 void c2bool(Register x); | |
| 2036 | |
| 2037 // C++ bool manipulation | |
| 2038 | |
| 2039 void movbool(Register dst, Address src); | |
| 2040 void movbool(Address dst, bool boolconst); | |
| 2041 void movbool(Address dst, Register src); | |
| 2042 void testbool(Register dst); | |
| 2043 | |
| 304 | 2044 // oop manipulations |
| 2045 void load_klass(Register dst, Register src); | |
| 2046 void store_klass(Register dst, Register src); | |
| 2047 | |
| 1846 | 2048 void load_heap_oop(Register dst, Address src); |
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2049 void load_heap_oop_not_null(Register dst, Address src); |
| 1846 | 2050 void store_heap_oop(Address dst, Register src); |
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2051 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); |
| 1846 | 2052 |
| 2053 // Used for storing NULL. All other oop constants should be | |
| 2054 // stored using routines that take a jobject. | |
| 2055 void store_heap_oop_null(Address dst); | |
| 2056 | |
| 304 | 2057 void load_prototype_header(Register dst, Register src); |
| 2058 | |
| 2059 #ifdef _LP64 | |
| 2060 void store_klass_gap(Register dst, Register src); | |
| 2061 | |
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2062 // This dummy is to prevent a call to store_heap_oop from |
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2063 // converting a zero (like NULL) into a Register by giving |
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2064 // the compiler two choices it can't resolve |
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2065 |
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2066 void store_heap_oop(Address dst, void* dummy); |
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2067 |
| 304 | 2068 void encode_heap_oop(Register r); |
| 2069 void decode_heap_oop(Register r); | |
| 2070 void encode_heap_oop_not_null(Register r); | |
| 2071 void decode_heap_oop_not_null(Register r); | |
| 2072 void encode_heap_oop_not_null(Register dst, Register src); | |
| 2073 void decode_heap_oop_not_null(Register dst, Register src); | |
| 2074 | |
| 2075 void set_narrow_oop(Register dst, jobject obj); | |
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2076 void set_narrow_oop(Address dst, jobject obj); |
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2077 void cmp_narrow_oop(Register dst, jobject obj); |
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2078 void cmp_narrow_oop(Address dst, jobject obj); |
| 304 | 2079 |
| 2080 // if heap base register is used - reinit it with the correct value | |
| 2081 void reinit_heapbase(); | |
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2082 |
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2083 DEBUG_ONLY(void verify_heapbase(const char* msg);) |
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2084 |
| 304 | 2085 #endif // _LP64 |
| 2086 | |
| 2087 // Int division/remainder for Java | |
| 0 | 2088 // (as idivl, but checks for special case as described in JVM spec.) |
| 2089 // returns idivl instruction offset for implicit exception handling | |
| 2090 int corrected_idivl(Register reg); | |
| 2091 | |
| 304 | 2092 // Long division/remainder for Java |
| 2093 // (as idivq, but checks for special case as described in JVM spec.) | |
| 2094 // returns idivq instruction offset for implicit exception handling | |
| 2095 int corrected_idivq(Register reg); | |
| 2096 | |
| 0 | 2097 void int3(); |
| 2098 | |
| 304 | 2099 // Long operation macros for a 32bit cpu |
| 0 | 2100 // Long negation for Java |
| 2101 void lneg(Register hi, Register lo); | |
| 2102 | |
| 2103 // Long multiplication for Java | |
| 304 | 2104 // (destroys contents of eax, ebx, ecx and edx) |
| 0 | 2105 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
| 2106 | |
| 2107 // Long shifts for Java | |
| 2108 // (semantics as described in JVM spec.) | |
| 2109 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
| 2110 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
| 2111 | |
| 2112 // Long compare for Java | |
| 2113 // (semantics as described in JVM spec.) | |
| 2114 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
| 2115 | |
| 304 | 2116 |
| 2117 // misc | |
| 2118 | |
| 2119 // Sign extension | |
| 2120 void sign_extend_short(Register reg); | |
| 2121 void sign_extend_byte(Register reg); | |
| 2122 | |
| 2123 // Division by power of 2, rounding towards 0 | |
| 2124 void division_with_shift(Register reg, int shift_value); | |
| 2125 | |
| 0 | 2126 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
| 2127 // | |
| 2128 // CF (corresponds to C0) if x < y | |
| 2129 // PF (corresponds to C2) if unordered | |
| 2130 // ZF (corresponds to C3) if x = y | |
| 2131 // | |
| 2132 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
| 2133 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
| 2134 void fcmp(Register tmp); | |
| 2135 // Variant of the above which allows y to be further down the stack | |
| 2136 // and which only pops x and y if specified. If pop_right is | |
| 2137 // specified then pop_left must also be specified. | |
| 2138 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
| 2139 | |
| 2140 // Floating-point comparison for Java | |
| 2141 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
| 2142 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
| 2143 // (semantics as described in JVM spec.) | |
| 2144 void fcmp2int(Register dst, bool unordered_is_less); | |
| 2145 // Variant of the above which allows y to be further down the stack | |
| 2146 // and which only pops x and y if specified. If pop_right is | |
| 2147 // specified then pop_left must also be specified. | |
| 2148 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
| 2149 | |
| 2150 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
| 2151 // tmp is a temporary register, if none is available use noreg | |
| 2152 void fremr(Register tmp); | |
| 2153 | |
| 2154 | |
| 2155 // same as fcmp2int, but using SSE2 | |
| 2156 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
| 2157 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
| 2158 | |
| 2159 // Inlined sin/cos generator for Java; must not use CPU instruction | |
| 2160 // directly on Intel as it does not have high enough precision | |
| 2161 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
| 2162 // number of FPU stack slots in use; all but the topmost will | |
| 2163 // require saving if a slow case is necessary. Assumes argument is | |
| 2164 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
| 2165 // this code. | |
| 2166 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
| 2167 | |
| 2168 // branch to L if FPU flag C2 is set/not set | |
| 2169 // tmp is a temporary register, if none is available use noreg | |
| 2170 void jC2 (Register tmp, Label& L); | |
| 2171 void jnC2(Register tmp, Label& L); | |
| 2172 | |
| 2173 // Pop ST (ffree & fincstp combined) | |
| 2174 void fpop(); | |
| 2175 | |
| 2176 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
| 2177 void push_fTOS(); | |
| 2178 | |
| 2179 // pops double TOS element from CPU stack and pushes on FPU stack | |
| 2180 void pop_fTOS(); | |
| 2181 | |
| 2182 void empty_FPU_stack(); | |
| 2183 | |
| 2184 void push_IU_state(); | |
| 2185 void pop_IU_state(); | |
| 2186 | |
| 2187 void push_FPU_state(); | |
| 2188 void pop_FPU_state(); | |
| 2189 | |
| 2190 void push_CPU_state(); | |
| 2191 void pop_CPU_state(); | |
| 2192 | |
| 2193 // Round up to a power of two | |
| 2194 void round_to(Register reg, int modulus); | |
| 2195 | |
| 2196 // Callee saved registers handling | |
| 2197 void push_callee_saved_registers(); | |
| 2198 void pop_callee_saved_registers(); | |
| 2199 | |
| 2200 // allocation | |
| 2201 void eden_allocate( | |
| 2202 Register obj, // result: pointer to object after successful allocation | |
| 2203 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
| 2204 int con_size_in_bytes, // object size in bytes if known at compile time | |
| 2205 Register t1, // temp register | |
| 2206 Label& slow_case // continuation point if fast allocation fails | |
| 2207 ); | |
| 2208 void tlab_allocate( | |
| 2209 Register obj, // result: pointer to object after successful allocation | |
| 2210 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
| 2211 int con_size_in_bytes, // object size in bytes if known at compile time | |
| 2212 Register t1, // temp register | |
| 2213 Register t2, // temp register | |
| 2214 Label& slow_case // continuation point if fast allocation fails | |
| 2215 ); | |
|
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2216 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
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2217 void incr_allocated_bytes(Register thread, |
|
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2008
diff
changeset
|
2218 Register var_size_in_bytes, int con_size_in_bytes, |
|
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|
2219 Register t1 = noreg); |
| 0 | 2220 |
|
623
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2221 // interface method calling |
|
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622
diff
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|
2222 void lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2223 Register intf_klass, |
|
665
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6814659: separable cleanups and subroutines for 6655638
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644
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|
2224 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
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622
diff
changeset
|
2225 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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parents:
622
diff
changeset
|
2226 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2227 Label& no_such_interface); |
|
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
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|
2228 |
|
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
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|
2229 // virtual method calling |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
2230 void lookup_virtual_method(Register recv_klass, |
|
1d7922586cf6
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6225
diff
changeset
|
2231 RegisterOrConstant vtable_index, |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
changeset
|
2232 Register method_result); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
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6225
diff
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|
2233 |
|
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643
diff
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|
2234 // Test sub_klass against super_klass, with fast and slow paths. |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
2235 |
|
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|
2236 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
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|
2237 // One of the three labels can be NULL, meaning take the fall-through. |
|
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643
diff
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|
2238 // If super_check_offset is -1, the value is loaded up from super_klass. |
|
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diff
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|
2239 // No registers are killed, except temp_reg. |
|
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jrose
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643
diff
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|
2240 void check_klass_subtype_fast_path(Register sub_klass, |
|
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643
diff
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|
2241 Register super_klass, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
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|
2242 Register temp_reg, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2243 Label* L_success, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
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|
2244 Label* L_failure, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
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|
2245 Label* L_slow_path, |
|
665
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|
2246 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
|
644
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diff
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|
2247 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
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|
2248 // The rest of the type check; must be wired to a corresponding fast path. |
|
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jrose
parents:
643
diff
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|
2249 // It does not repeat the fast path logic, so don't use it standalone. |
|
c517646eef23
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jrose
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643
diff
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|
2250 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
|
c517646eef23
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643
diff
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|
2251 // Updates the sub's secondary super cache as necessary. |
|
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|
2252 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
|
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diff
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|
2253 void check_klass_subtype_slow_path(Register sub_klass, |
|
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643
diff
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|
2254 Register super_klass, |
|
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643
diff
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|
2255 Register temp_reg, |
|
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643
diff
changeset
|
2256 Register temp2_reg, |
|
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643
diff
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|
2257 Label* L_success, |
|
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643
diff
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|
2258 Label* L_failure, |
|
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643
diff
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|
2259 bool set_cond_codes = false); |
|
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diff
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|
2260 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2261 // Simplified, combined version, good for typical uses. |
|
c517646eef23
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diff
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|
2262 // Falls through on failure. |
|
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diff
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|
2263 void check_klass_subtype(Register sub_klass, |
|
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643
diff
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|
2264 Register super_klass, |
|
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643
diff
changeset
|
2265 Register temp_reg, |
|
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643
diff
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|
2266 Label& L_success); |
|
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diff
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|
2267 |
| 710 | 2268 // method handles (JSR 292) |
| 2269 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
| 2270 | |
| 0 | 2271 //---- |
| 2272 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
| 2273 | |
| 2274 // Debugging | |
| 304 | 2275 |
| 2276 // only if +VerifyOops | |
| 2277 void verify_oop(Register reg, const char* s = "broken oop"); | |
| 0 | 2278 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
| 2279 | |
| 304 | 2280 // only if +VerifyFPU |
| 2281 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
| 2282 | |
| 2283 // prints msg, dumps registers and stops execution | |
| 2284 void stop(const char* msg); | |
| 2285 | |
| 2286 // prints msg and continues | |
| 2287 void warn(const char* msg); | |
| 2288 | |
|
6266
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6225
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|
2289 // dumps registers and other state |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
2290 void print_state(); |
|
1d7922586cf6
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6225
diff
changeset
|
2291 |
| 304 | 2292 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); |
| 2293 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
|
6266
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7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
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|
2294 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); |
|
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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6225
diff
changeset
|
2295 static void print_state64(int64_t pc, int64_t regs[]); |
| 304 | 2296 |
| 0 | 2297 void os_breakpoint(); |
| 304 | 2298 |
| 0 | 2299 void untested() { stop("untested"); } |
| 304 | 2300 |
| 1846 | 2301 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
| 304 | 2302 |
| 0 | 2303 void should_not_reach_here() { stop("should not reach here"); } |
| 304 | 2304 |
| 0 | 2305 void print_CPU_state(); |
| 2306 | |
| 2307 // Stack overflow checking | |
| 2308 void bang_stack_with_offset(int offset) { | |
| 2309 // stack grows down, caller passes positive offset | |
| 2310 assert(offset > 0, "must bang with negative offset"); | |
| 2311 movl(Address(rsp, (-offset)), rax); | |
| 2312 } | |
| 2313 | |
| 2314 // Writes to stack successive pages until offset reached to check for | |
| 2315 // stack overflow + shadow pages. Also, clobbers tmp | |
| 2316 void bang_stack_size(Register size, Register tmp); | |
| 2317 | |
|
665
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6814659: separable cleanups and subroutines for 6655638
jrose
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644
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changeset
|
2318 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
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644
diff
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|
2319 Register tmp, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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parents:
644
diff
changeset
|
2320 int offset); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
2321 |
| 0 | 2322 // Support for serializing memory accesses between threads |
| 2323 void serialize_memory(Register thread, Register tmp); | |
| 2324 | |
| 2325 void verify_tlab(); | |
| 2326 | |
| 2327 // Biased locking support | |
| 2328 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
| 2329 // swap_reg must be rax, and is killed. | |
| 2330 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
| 2331 // be killed; if not supplied, push/pop will be used internally to | |
| 2332 // allocate a temporary (inefficient, avoid if possible). | |
| 2333 // Optional slow case is for implementations (interpreter and C1) which branch to | |
| 2334 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
| 2335 // Returns offset of first potentially-faulting instruction for null | |
| 2336 // check info (currently consumed only by C1). If | |
| 2337 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
| 2338 // the calling code has already passed any potential faults. | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
2339 int biased_locking_enter(Register lock_reg, Register obj_reg, |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
2340 Register swap_reg, Register tmp_reg, |
| 0 | 2341 bool swap_reg_contains_mark, |
| 2342 Label& done, Label* slow_case = NULL, | |
| 2343 BiasedLockingCounters* counters = NULL); | |
| 2344 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
| 2345 | |
| 2346 | |
| 2347 Condition negate_condition(Condition cond); | |
| 2348 | |
| 2349 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
| 2350 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
| 2351 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
| 2352 // here in MacroAssembler. The major exception to this rule is call | |
| 2353 | |
| 2354 // Arithmetics | |
| 2355 | |
| 304 | 2356 |
| 2357 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
| 2358 void addptr(Address dst, Register src); | |
| 2359 | |
| 2360 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
| 2361 void addptr(Register dst, int32_t src); | |
| 2362 void addptr(Register dst, Register src); | |
|
3363
167b70ff3abc
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3336
diff
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|
2363 void addptr(Register dst, RegisterOrConstant src) { |
|
167b70ff3abc
6939861: JVM should handle more conversion operations
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changeset
|
2364 if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
|
167b70ff3abc
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|
2365 else addptr(dst, src.as_register()); |
|
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|
2366 } |
| 304 | 2367 |
| 2368 void andptr(Register dst, int32_t src); | |
| 2369 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
| 2370 | |
| 2371 void cmp8(AddressLiteral src1, int imm); | |
| 2372 | |
| 2373 // renamed to drag out the casting of address to int32_t/intptr_t | |
| 0 | 2374 void cmp32(Register src1, int32_t imm); |
| 2375 | |
| 2376 void cmp32(AddressLiteral src1, int32_t imm); | |
| 2377 // compare reg - mem, or reg - &mem | |
| 2378 void cmp32(Register src1, AddressLiteral src2); | |
| 2379 | |
| 2380 void cmp32(Register src1, Address src2); | |
| 2381 | |
| 304 | 2382 #ifndef _LP64 |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
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6614
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|
2383 void cmpklass(Address dst, Metadata* obj); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6614
diff
changeset
|
2384 void cmpklass(Register dst, Metadata* obj); |
| 304 | 2385 void cmpoop(Address dst, jobject obj); |
| 2386 void cmpoop(Register dst, jobject obj); | |
| 2387 #endif // _LP64 | |
| 2388 | |
| 0 | 2389 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
| 2390 void cmpptr(Address src1, AddressLiteral src2); | |
| 2391 | |
| 2392 void cmpptr(Register src1, AddressLiteral src2); | |
| 2393 | |
| 304 | 2394 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
| 2395 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2396 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2397 | |
| 2398 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2399 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2400 | |
| 2401 // cmp64 to avoild hiding cmpq | |
| 2402 void cmp64(Register src1, AddressLiteral src); | |
| 2403 | |
| 2404 void cmpxchgptr(Register reg, Address adr); | |
| 2405 | |
| 2406 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
| 2407 | |
| 2408 | |
| 2409 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
| 2410 | |
| 2411 | |
| 2412 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
| 2413 | |
| 2414 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
| 2415 | |
| 2416 void shlptr(Register dst, int32_t shift); | |
| 2417 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
| 2418 | |
| 2419 void shrptr(Register dst, int32_t shift); | |
| 2420 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
| 2421 | |
| 2422 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
| 2423 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
| 2424 | |
| 2425 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
| 2426 | |
| 2427 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
| 2428 void subptr(Register dst, int32_t src); | |
|
4947
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4761
diff
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|
2429 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
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|
2430 void subptr_imm32(Register dst, int32_t src); |
| 304 | 2431 void subptr(Register dst, Register src); |
|
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|
2432 void subptr(Register dst, RegisterOrConstant src) { |
|
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|
2433 if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
|
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diff
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|
2434 else subptr(dst, src.as_register()); |
|
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diff
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|
2435 } |
| 304 | 2436 |
| 2437 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
| 2438 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
| 2439 | |
| 2440 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
| 2441 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
| 2442 | |
| 2443 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
| 2444 | |
| 2445 | |
| 0 | 2446 |
| 2447 // Helper functions for statistics gathering. | |
| 2448 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
| 2449 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
| 2450 // Unconditional atomic increment. | |
| 2451 void atomic_incl(AddressLiteral counter_addr); | |
| 2452 | |
| 2453 void lea(Register dst, AddressLiteral adr); | |
| 2454 void lea(Address dst, AddressLiteral adr); | |
| 304 | 2455 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
| 2456 | |
| 2457 void leal32(Register dst, Address src) { leal(dst, src); } | |
| 2458 | |
|
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2459 // Import other testl() methods from the parent class or else |
|
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|
2460 // they will be hidden by the following overriding declaration. |
|
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|
2461 using Assembler::testl; |
|
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|
2462 void testl(Register dst, AddressLiteral src); |
| 304 | 2463 |
| 2464 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2465 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2466 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2467 | |
| 2468 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
| 2469 void testptr(Register src1, Register src2); | |
| 2470 | |
| 2471 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
| 2472 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
| 0 | 2473 |
| 2474 // Calls | |
| 2475 | |
| 2476 void call(Label& L, relocInfo::relocType rtype); | |
| 2477 void call(Register entry); | |
| 2478 | |
| 2479 // NOTE: this call tranfers to the effective address of entry NOT | |
| 2480 // the address contained by entry. This is because this is more natural | |
| 2481 // for jumps/calls. | |
| 2482 void call(AddressLiteral entry); | |
| 2483 | |
|
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2484 // Emit the CompiledIC call idiom |
|
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2485 void ic_call(address entry); |
|
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|
2486 |
| 0 | 2487 // Jumps |
| 2488 | |
| 2489 // NOTE: these jumps tranfer to the effective address of dst NOT | |
| 2490 // the address contained by dst. This is because this is more natural | |
| 2491 // for jumps/calls. | |
| 2492 void jump(AddressLiteral dst); | |
| 2493 void jump_cc(Condition cc, AddressLiteral dst); | |
| 2494 | |
| 2495 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 2496 // to be installed in the Address class. This jump will tranfers to the address | |
| 2497 // contained in the location described by entry (not the address of entry) | |
| 2498 void jump(ArrayAddress entry); | |
| 2499 | |
| 2500 // Floating | |
| 2501 | |
| 2502 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
| 2503 void andpd(XMMRegister dst, AddressLiteral src); | |
| 2504 | |
| 4759 | 2505 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } |
| 2506 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } | |
| 2507 void andps(XMMRegister dst, AddressLiteral src); | |
| 2508 | |
| 2509 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } | |
| 0 | 2510 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
| 2511 void comiss(XMMRegister dst, AddressLiteral src); | |
| 2512 | |
| 4759 | 2513 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } |
| 0 | 2514 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
| 2515 void comisd(XMMRegister dst, AddressLiteral src); | |
| 2516 | |
| 2008 | 2517 void fadd_s(Address src) { Assembler::fadd_s(src); } |
| 2518 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } | |
| 2519 | |
| 0 | 2520 void fldcw(Address src) { Assembler::fldcw(src); } |
| 2521 void fldcw(AddressLiteral src); | |
| 2522 | |
| 2523 void fld_s(int index) { Assembler::fld_s(index); } | |
| 2524 void fld_s(Address src) { Assembler::fld_s(src); } | |
| 2525 void fld_s(AddressLiteral src); | |
| 2526 | |
| 2527 void fld_d(Address src) { Assembler::fld_d(src); } | |
| 2528 void fld_d(AddressLiteral src); | |
| 2529 | |
| 2530 void fld_x(Address src) { Assembler::fld_x(src); } | |
| 2531 void fld_x(AddressLiteral src); | |
| 2532 | |
| 2008 | 2533 void fmul_s(Address src) { Assembler::fmul_s(src); } |
| 2534 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } | |
| 2535 | |
| 0 | 2536 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
| 2537 void ldmxcsr(AddressLiteral src); | |
| 2538 | |
|
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2539 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover |
|
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2540 // all corner cases and may result in NaN and require fallback to a |
|
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|
2541 // runtime call. |
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|
2542 void fast_pow(); |
|
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|
2543 void fast_exp(); |
|
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|
2544 void increase_precision(); |
|
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|
2545 void restore_precision(); |
|
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|
2546 |
|
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|
2547 // computes exp(x). Fallback to runtime call included. |
|
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|
2548 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); } |
|
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|
2549 // computes pow(x,y). Fallback to runtime call included. |
|
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|
2550 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); } |
|
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2551 |
| 304 | 2552 private: |
|
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|
2553 |
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|
2554 // call runtime as a fallback for trig functions and pow/exp. |
|
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|
2555 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); |
|
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|
2556 |
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|
2557 // computes 2^(Ylog2X); Ylog2X in ST(0) |
|
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|
2558 void pow_exp_core_encoding(); |
|
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|
2559 |
|
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|
2560 // computes pow(x,y) or exp(x). Fallback to runtime call included. |
|
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|
2561 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use); |
|
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|
2562 |
| 304 | 2563 // these are private because users should be doing movflt/movdbl |
| 2564 | |
| 0 | 2565 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
| 2566 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
| 2567 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
| 2568 void movss(XMMRegister dst, AddressLiteral src); | |
| 2569 | |
| 4759 | 2570 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
| 304 | 2571 void movlpd(XMMRegister dst, AddressLiteral src); |
| 2572 | |
| 2573 public: | |
| 2574 | |
| 2008 | 2575 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
| 2576 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } | |
| 4759 | 2577 void addsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2578 |
| 2579 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } | |
| 2580 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } | |
| 4759 | 2581 void addss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2582 |
| 2583 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } | |
| 2584 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } | |
| 4759 | 2585 void divsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2586 |
| 2587 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } | |
| 2588 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } | |
| 4759 | 2589 void divss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2590 |
|
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|
2591 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
|
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|
2592 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
|
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|
2593 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
| 4759 | 2594 void movsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2595 |
| 2596 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } | |
| 2597 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } | |
| 4759 | 2598 void mulsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2599 |
| 2600 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } | |
| 2601 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } | |
| 4759 | 2602 void mulss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2603 |
| 2604 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } | |
| 2605 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } | |
| 4759 | 2606 void sqrtsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2607 |
| 2608 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } | |
| 2609 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } | |
| 4759 | 2610 void sqrtss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2611 |
| 2612 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } | |
| 2613 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } | |
| 4759 | 2614 void subsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2615 |
| 2616 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } | |
| 2617 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } | |
| 4759 | 2618 void subss(XMMRegister dst, AddressLiteral src); |
| 0 | 2619 |
| 2620 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
| 4759 | 2621 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
| 0 | 2622 void ucomiss(XMMRegister dst, AddressLiteral src); |
| 2623 | |
| 2624 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
| 4759 | 2625 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
| 0 | 2626 void ucomisd(XMMRegister dst, AddressLiteral src); |
| 2627 | |
| 2628 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
| 2629 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
| 2630 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
| 2631 void xorpd(XMMRegister dst, AddressLiteral src); | |
| 2632 | |
| 2633 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
| 2634 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
| 2635 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
| 2636 void xorps(XMMRegister dst, AddressLiteral src); | |
| 2637 | |
|
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2638 // AVX 3-operands instructions |
|
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2639 |
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2640 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } |
|
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2641 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } |
|
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2642 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2643 |
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2644 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } |
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2645 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } |
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2646 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2647 |
|
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|
2648 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } |
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|
2649 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } |
|
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2650 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
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2651 |
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2652 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } |
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2653 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } |
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2654 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
|
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2655 |
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2656 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } |
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2657 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } |
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2658 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2659 |
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2660 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } |
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2661 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } |
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2662 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2663 |
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2664 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } |
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2665 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } |
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2666 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2667 |
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2668 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } |
|
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2669 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } |
|
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2670 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2671 |
|
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2672 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } |
|
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2673 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } |
|
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2674 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
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2675 |
|
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2676 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } |
|
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2677 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } |
|
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2678 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
|
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2679 |
|
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|
2680 // AVX Vector instructions |
|
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|
2681 |
|
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|
2682 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } |
|
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2683 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } |
|
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2684 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
|
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2685 |
|
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|
2686 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } |
|
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2687 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } |
|
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|
2688 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); |
|
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2689 |
| 6225 | 2690 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
| 2691 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 | |
| 2692 Assembler::vpxor(dst, nds, src, vector256); | |
| 2693 else | |
| 2694 Assembler::vxorpd(dst, nds, src, vector256); | |
| 2695 } | |
|
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2696 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
|
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2697 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 |
|
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2698 Assembler::vpxor(dst, nds, src, vector256); |
|
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|
2699 else |
|
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|
2700 Assembler::vxorpd(dst, nds, src, vector256); |
|
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|
2701 } |
| 6225 | 2702 |
| 2703 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. | |
| 2704 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
| 2705 if (UseAVX > 1) // vinserti128h is available only in AVX2 | |
| 2706 Assembler::vinserti128h(dst, nds, src); | |
| 2707 else | |
| 2708 Assembler::vinsertf128h(dst, nds, src); | |
| 2709 } | |
|
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|
2710 |
| 0 | 2711 // Data |
| 2712 | |
|
2415
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|
2713 void cmov32( Condition cc, Register dst, Address src); |
|
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|
2714 void cmov32( Condition cc, Register dst, Register src); |
|
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|
2715 |
|
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|
2716 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
|
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|
2717 |
|
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|
2718 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
|
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|
2719 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
| 304 | 2720 |
| 0 | 2721 void movoop(Register dst, jobject obj); |
| 2722 void movoop(Address dst, jobject obj); | |
| 2723 | |
|
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|
2724 void mov_metadata(Register dst, Metadata* obj); |
|
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|
2725 void mov_metadata(Address dst, Metadata* obj); |
|
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|
2726 |
| 0 | 2727 void movptr(ArrayAddress dst, Register src); |
| 2728 // can this do an lea? | |
| 2729 void movptr(Register dst, ArrayAddress src); | |
| 2730 | |
| 304 | 2731 void movptr(Register dst, Address src); |
| 2732 | |
| 0 | 2733 void movptr(Register dst, AddressLiteral src); |
| 2734 | |
| 304 | 2735 void movptr(Register dst, intptr_t src); |
| 2736 void movptr(Register dst, Register src); | |
| 2737 void movptr(Address dst, intptr_t src); | |
| 2738 | |
| 2739 void movptr(Address dst, Register src); | |
| 2740 | |
|
3363
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|
2741 void movptr(Register dst, RegisterOrConstant src) { |
|
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|
2742 if (src.is_constant()) movptr(dst, src.as_constant()); |
|
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|
2743 else movptr(dst, src.as_register()); |
|
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|
2744 } |
|
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|
2745 |
| 304 | 2746 #ifdef _LP64 |
| 2747 // Generally the next two are only used for moving NULL | |
| 2748 // Although there are situations in initializing the mark word where | |
| 2749 // they could be used. They are dangerous. | |
| 2750 | |
| 2751 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
| 2752 // and we have ambiguous declarations. | |
| 2753 | |
| 2754 void movptr(Address dst, int32_t imm32); | |
| 2755 void movptr(Register dst, int32_t imm32); | |
| 2756 #endif // _LP64 | |
| 2757 | |
| 0 | 2758 // to avoid hiding movl |
| 2759 void mov32(AddressLiteral dst, Register src); | |
| 2760 void mov32(Register dst, AddressLiteral src); | |
| 304 | 2761 |
| 0 | 2762 // to avoid hiding movb |
| 2763 void movbyte(ArrayAddress dst, int src); | |
| 2764 | |
| 6225 | 2765 // Import other mov() methods from the parent class or else |
| 2766 // they will be hidden by the following overriding declaration. | |
| 2767 using Assembler::movdl; | |
| 2768 using Assembler::movq; | |
| 2769 void movdl(XMMRegister dst, AddressLiteral src); | |
| 2770 void movq(XMMRegister dst, AddressLiteral src); | |
| 2771 | |
| 0 | 2772 // Can push value or effective address |
| 2773 void pushptr(AddressLiteral src); | |
| 2774 | |
| 304 | 2775 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
| 2776 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
| 2777 | |
| 2778 void pushoop(jobject obj); | |
|
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|
2779 void pushklass(Metadata* obj); |
| 304 | 2780 |
| 2781 // sign extend as need a l to ptr sized element | |
| 2782 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
| 2783 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
| 2784 | |
|
4947
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|
2785 // C2 compiled method's prolog code. |
|
fd8114661503
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|
2786 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b); |
|
fd8114661503
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|
2787 |
|
986
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|
2788 // IndexOf strings. |
|
2320
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|
2789 // Small strings are loaded through stack if they cross page boundary. |
|
986
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|
2790 void string_indexof(Register str1, Register str2, |
|
2320
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|
2791 Register cnt1, Register cnt2, |
|
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|
2792 int int_cnt2, Register result, |
|
986
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|
2793 XMMRegister vec, Register tmp); |
|
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|
2794 |
|
2320
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|
2795 // IndexOf for constant substrings with size >= 8 elements |
|
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|
2796 // which don't need to be loaded through stack. |
|
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|
2797 void string_indexofC8(Register str1, Register str2, |
|
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|
2798 Register cnt1, Register cnt2, |
|
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|
2799 int int_cnt2, Register result, |
|
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|
2800 XMMRegister vec, Register tmp); |
|
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|
2801 |
|
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|
2802 // Smallest code: we don't need to load through stack, |
|
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|
2803 // check string tail. |
|
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|
2804 |
|
986
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|
2805 // Compare strings. |
|
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|
2806 void string_compare(Register str1, Register str2, |
|
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|
2807 Register cnt1, Register cnt2, Register result, |
| 2262 | 2808 XMMRegister vec1); |
|
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|
2809 |
|
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|
2810 // Compare char[] arrays. |
|
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|
2811 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
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|
2812 Register limit, Register result, Register chr, |
|
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|
2813 XMMRegister vec1, XMMRegister vec2); |
| 304 | 2814 |
| 1763 | 2815 // Fill primitive arrays |
| 2816 void generate_fill(BasicType t, bool aligned, | |
| 2817 Register to, Register value, Register count, | |
| 2818 Register rtmp, XMMRegister xtmp); | |
| 2819 | |
| 0 | 2820 #undef VIRTUAL |
| 2821 | |
| 2822 }; | |
| 2823 | |
| 2824 /** | |
| 2825 * class SkipIfEqual: | |
| 2826 * | |
| 2827 * Instantiating this class will result in assembly code being output that will | |
| 2828 * jump around any code emitted between the creation of the instance and it's | |
| 2829 * automatic destruction at the end of a scope block, depending on the value of | |
| 2830 * the flag passed to the constructor, which will be checked at run-time. | |
| 2831 */ | |
| 2832 class SkipIfEqual { | |
| 2833 private: | |
| 2834 MacroAssembler* _masm; | |
| 2835 Label _label; | |
| 2836 | |
| 2837 public: | |
| 2838 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
| 2839 ~SkipIfEqual(); | |
| 2840 }; | |
| 2841 | |
| 2842 #ifdef ASSERT | |
| 2843 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
| 2844 #endif | |
| 1972 | 2845 |
| 2846 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |