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comparison src/cpu/x86/vm/vm_version_x86.cpp @ 20313:b20a35eae442

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8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC Summary: Add C2 SHA intrinsics on SPARC Reviewed-by: kvn, roland Contributed-by: james.cheng@oracle.com
author kvn
date Wed, 11 Jun 2014 11:05:10 -0700
parents b1bc1af04c6e
children 999824269b71
comparison
equal deleted inserted replaced
20312:922c87c9aed4 20313:b20a35eae442
588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
589 warning("AES intrinsics are not available on this CPU"); 589 warning("AES intrinsics are not available on this CPU");
590 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 590 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
591 } 591 }
592 592
593 if (UseSHA) {
594 warning("SHA instructions are not available on this CPU");
595 FLAG_SET_DEFAULT(UseSHA, false);
596 }
597 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
598 warning("SHA intrinsics are not available on this CPU");
599 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
600 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
601 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
602 }
603
593 // Adjust RTM (Restricted Transactional Memory) flags 604 // Adjust RTM (Restricted Transactional Memory) flags
594 if (!supports_rtm() && UseRTMLocking) { 605 if (!supports_rtm() && UseRTMLocking) {
595 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 606 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
596 // setting during arguments processing. See use_biased_locking(). 607 // setting during arguments processing. See use_biased_locking().
597 // VM_Version_init() is executed after UseBiasedLocking is used 608 // VM_Version_init() is executed after UseBiasedLocking is used