Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 20313:b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
Summary: Add C2 SHA intrinsics on SPARC
Reviewed-by: kvn, roland
Contributed-by: james.cheng@oracle.com
author | kvn |
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date | Wed, 11 Jun 2014 11:05:10 -0700 |
parents | b1bc1af04c6e |
children | 999824269b71 |
rev | line source |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.hpp" |
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27 #include "asm/macroAssembler.inline.hpp" |
1972 | 28 #include "memory/resourceArea.hpp" |
29 #include "runtime/java.hpp" | |
30 #include "runtime/stubCodeGenerator.hpp" | |
31 #include "vm_version_x86.hpp" | |
32 #ifdef TARGET_OS_FAMILY_linux | |
33 # include "os_linux.inline.hpp" | |
34 #endif | |
35 #ifdef TARGET_OS_FAMILY_solaris | |
36 # include "os_solaris.inline.hpp" | |
37 #endif | |
38 #ifdef TARGET_OS_FAMILY_windows | |
39 # include "os_windows.inline.hpp" | |
40 #endif | |
3960 | 41 #ifdef TARGET_OS_FAMILY_bsd |
42 # include "os_bsd.inline.hpp" | |
43 #endif | |
585 | 44 |
45 | |
46 int VM_Version::_cpu; | |
47 int VM_Version::_model; | |
48 int VM_Version::_stepping; | |
49 int VM_Version::_cpuFeatures; | |
50 const char* VM_Version::_features_str = ""; | |
51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
52 | |
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53 // Address of instruction which causes SEGV |
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54 address VM_Version::_cpuinfo_segv_addr = 0; |
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55 // Address of instruction after the one which causes SEGV |
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56 address VM_Version::_cpuinfo_cont_addr = 0; |
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57 |
585 | 58 static BufferBlob* stub_blob; |
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59 static const int stub_size = 600; |
585 | 60 |
61 extern "C" { | |
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62 typedef void (*get_cpu_info_stub_t)(void*); |
585 | 63 } |
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64 static get_cpu_info_stub_t get_cpu_info_stub = NULL; |
585 | 65 |
66 | |
67 class VM_Version_StubGenerator: public StubCodeGenerator { | |
68 public: | |
69 | |
70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
71 | |
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72 address generate_get_cpu_info() { |
585 | 73 // Flags to test CPU type. |
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74 const uint32_t HS_EFL_AC = 0x40000; |
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75 const uint32_t HS_EFL_ID = 0x200000; |
585 | 76 // Values for when we don't have a CPUID instruction. |
77 const int CPU_FAMILY_SHIFT = 8; | |
78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
80 | |
1622 | 81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
4771 | 82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
585 | 83 |
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84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); |
585 | 85 # define __ _masm-> |
86 | |
87 address start = __ pc(); | |
88 | |
89 // | |
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90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); |
585 | 91 // |
92 // LP64: rcx and rdx are first and second argument registers on windows | |
93 | |
94 __ push(rbp); | |
95 #ifdef _LP64 | |
96 __ mov(rbp, c_rarg0); // cpuid_info address | |
97 #else | |
98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
99 #endif | |
100 __ push(rbx); | |
101 __ push(rsi); | |
102 __ pushf(); // preserve rbx, and flags | |
103 __ pop(rax); | |
104 __ push(rax); | |
105 __ mov(rcx, rax); | |
106 // | |
107 // if we are unable to change the AC flag, we have a 386 | |
108 // | |
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109 __ xorl(rax, HS_EFL_AC); |
585 | 110 __ push(rax); |
111 __ popf(); | |
112 __ pushf(); | |
113 __ pop(rax); | |
114 __ cmpptr(rax, rcx); | |
115 __ jccb(Assembler::notEqual, detect_486); | |
116 | |
117 __ movl(rax, CPU_FAMILY_386); | |
118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
119 __ jmp(done); | |
120 | |
121 // | |
122 // If we are unable to change the ID flag, we have a 486 which does | |
123 // not support the "cpuid" instruction. | |
124 // | |
125 __ bind(detect_486); | |
126 __ mov(rax, rcx); | |
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127 __ xorl(rax, HS_EFL_ID); |
585 | 128 __ push(rax); |
129 __ popf(); | |
130 __ pushf(); | |
131 __ pop(rax); | |
132 __ cmpptr(rcx, rax); | |
133 __ jccb(Assembler::notEqual, detect_586); | |
134 | |
135 __ bind(cpu486); | |
136 __ movl(rax, CPU_FAMILY_486); | |
137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
138 __ jmp(done); | |
139 | |
140 // | |
141 // At this point, we have a chip which supports the "cpuid" instruction | |
142 // | |
143 __ bind(detect_586); | |
144 __ xorl(rax, rax); | |
145 __ cpuid(); | |
146 __ orl(rax, rax); | |
147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
148 // value of at least 1, we give up and | |
149 // assume a 486 | |
150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
151 __ movl(Address(rsi, 0), rax); | |
152 __ movl(Address(rsi, 4), rbx); | |
153 __ movl(Address(rsi, 8), rcx); | |
154 __ movl(Address(rsi,12), rdx); | |
155 | |
1622 | 156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
157 __ jccb(Assembler::belowEqual, std_cpuid4); | |
158 | |
159 // | |
160 // cpuid(0xB) Processor Topology | |
161 // | |
162 __ movl(rax, 0xb); | |
163 __ xorl(rcx, rcx); // Threads level | |
164 __ cpuid(); | |
165 | |
166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
167 __ movl(Address(rsi, 0), rax); | |
168 __ movl(Address(rsi, 4), rbx); | |
169 __ movl(Address(rsi, 8), rcx); | |
170 __ movl(Address(rsi,12), rdx); | |
171 | |
172 __ movl(rax, 0xb); | |
173 __ movl(rcx, 1); // Cores level | |
174 __ cpuid(); | |
175 __ push(rax); | |
176 __ andl(rax, 0x1f); // Determine if valid topology level | |
177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
178 __ andl(rax, 0xffff); | |
179 __ pop(rax); | |
180 __ jccb(Assembler::equal, std_cpuid4); | |
181 | |
182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
183 __ movl(Address(rsi, 0), rax); | |
184 __ movl(Address(rsi, 4), rbx); | |
185 __ movl(Address(rsi, 8), rcx); | |
186 __ movl(Address(rsi,12), rdx); | |
187 | |
188 __ movl(rax, 0xb); | |
189 __ movl(rcx, 2); // Packages level | |
190 __ cpuid(); | |
191 __ push(rax); | |
192 __ andl(rax, 0x1f); // Determine if valid topology level | |
193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
194 __ andl(rax, 0xffff); | |
195 __ pop(rax); | |
196 __ jccb(Assembler::equal, std_cpuid4); | |
197 | |
198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
199 __ movl(Address(rsi, 0), rax); | |
200 __ movl(Address(rsi, 4), rbx); | |
201 __ movl(Address(rsi, 8), rcx); | |
202 __ movl(Address(rsi,12), rdx); | |
585 | 203 |
204 // | |
205 // cpuid(0x4) Deterministic cache params | |
206 // | |
1622 | 207 __ bind(std_cpuid4); |
585 | 208 __ movl(rax, 4); |
1622 | 209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
210 __ jccb(Assembler::greater, std_cpuid1); | |
211 | |
585 | 212 __ xorl(rcx, rcx); // L1 cache |
213 __ cpuid(); | |
214 __ push(rax); | |
215 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
217 __ pop(rax); | |
218 __ jccb(Assembler::equal, std_cpuid1); | |
219 | |
220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
221 __ movl(Address(rsi, 0), rax); | |
222 __ movl(Address(rsi, 4), rbx); | |
223 __ movl(Address(rsi, 8), rcx); | |
224 __ movl(Address(rsi,12), rdx); | |
225 | |
226 // | |
227 // Standard cpuid(0x1) | |
228 // | |
229 __ bind(std_cpuid1); | |
230 __ movl(rax, 1); | |
231 __ cpuid(); | |
232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
233 __ movl(Address(rsi, 0), rax); | |
234 __ movl(Address(rsi, 4), rbx); | |
235 __ movl(Address(rsi, 8), rcx); | |
236 __ movl(Address(rsi,12), rdx); | |
237 | |
4759 | 238 // |
239 // Check if OS has enabled XGETBV instruction to access XCR0 | |
240 // (OSXSAVE feature flag) and CPU supports AVX | |
241 // | |
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242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
4759 | 243 __ cmpl(rcx, 0x18000000); |
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244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
4759 | 245 |
246 // | |
247 // XCR0, XFEATURE_ENABLED_MASK register | |
248 // | |
249 __ xorl(rcx, rcx); // zero for XCR0 register | |
250 __ xgetbv(); | |
251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); | |
252 __ movl(Address(rsi, 0), rax); | |
253 __ movl(Address(rsi, 4), rdx); | |
254 | |
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255 __ andl(rax, 0x6); // xcr0 bits sse | ymm |
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256 __ cmpl(rax, 0x6); |
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257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
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258 |
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259 // |
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260 // Some OSs have a bug when upper 128bits of YMM |
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261 // registers are not restored after a signal processing. |
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262 // Generate SEGV here (reference through NULL) |
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263 // and check upper YMM bits after it. |
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264 // |
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265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
17913 | 266 intx saved_useavx = UseAVX; |
267 intx saved_usesse = UseSSE; | |
268 UseAVX = 1; | |
269 UseSSE = 2; | |
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270 |
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271 // load value into all 32 bytes of ymm7 register |
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272 __ movl(rcx, VM_Version::ymm_test_value()); |
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273 |
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274 __ movdl(xmm0, rcx); |
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275 __ pshufd(xmm0, xmm0, 0x00); |
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276 __ vinsertf128h(xmm0, xmm0, xmm0); |
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277 __ vmovdqu(xmm7, xmm0); |
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278 #ifdef _LP64 |
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279 __ vmovdqu(xmm8, xmm0); |
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280 __ vmovdqu(xmm15, xmm0); |
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281 #endif |
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282 |
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283 __ xorl(rsi, rsi); |
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284 VM_Version::set_cpuinfo_segv_addr( __ pc() ); |
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285 // Generate SEGV |
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286 __ movl(rax, Address(rsi, 0)); |
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287 |
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288 VM_Version::set_cpuinfo_cont_addr( __ pc() ); |
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289 // Returns here after signal. Save xmm0 to check it later. |
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290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); |
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291 __ vmovdqu(Address(rsi, 0), xmm0); |
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292 __ vmovdqu(Address(rsi, 32), xmm7); |
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293 #ifdef _LP64 |
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294 __ vmovdqu(Address(rsi, 64), xmm8); |
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295 __ vmovdqu(Address(rsi, 96), xmm15); |
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296 #endif |
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297 |
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298 VM_Version::clean_cpuFeatures(); |
17913 | 299 UseAVX = saved_useavx; |
300 UseSSE = saved_usesse; | |
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301 |
4759 | 302 // |
303 // cpuid(0x7) Structured Extended Features | |
304 // | |
305 __ bind(sef_cpuid); | |
306 __ movl(rax, 7); | |
307 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? | |
308 __ jccb(Assembler::greater, ext_cpuid); | |
309 | |
310 __ xorl(rcx, rcx); | |
311 __ cpuid(); | |
312 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); | |
313 __ movl(Address(rsi, 0), rax); | |
314 __ movl(Address(rsi, 4), rbx); | |
315 | |
316 // | |
317 // Extended cpuid(0x80000000) | |
318 // | |
319 __ bind(ext_cpuid); | |
585 | 320 __ movl(rax, 0x80000000); |
321 __ cpuid(); | |
322 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
323 __ jcc(Assembler::belowEqual, done); | |
324 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
325 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
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326 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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327 __ jccb(Assembler::belowEqual, ext_cpuid5); |
585 | 328 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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329 __ jccb(Assembler::belowEqual, ext_cpuid7); |
585 | 330 // |
331 // Extended cpuid(0x80000008) | |
332 // | |
333 __ movl(rax, 0x80000008); | |
334 __ cpuid(); | |
335 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
336 __ movl(Address(rsi, 0), rax); | |
337 __ movl(Address(rsi, 4), rbx); | |
338 __ movl(Address(rsi, 8), rcx); | |
339 __ movl(Address(rsi,12), rdx); | |
340 | |
341 // | |
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342 // Extended cpuid(0x80000007) |
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343 // |
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344 __ bind(ext_cpuid7); |
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345 __ movl(rax, 0x80000007); |
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346 __ cpuid(); |
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347 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
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348 __ movl(Address(rsi, 0), rax); |
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349 __ movl(Address(rsi, 4), rbx); |
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350 __ movl(Address(rsi, 8), rcx); |
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351 __ movl(Address(rsi,12), rdx); |
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352 |
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353 // |
585 | 354 // Extended cpuid(0x80000005) |
355 // | |
356 __ bind(ext_cpuid5); | |
357 __ movl(rax, 0x80000005); | |
358 __ cpuid(); | |
359 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
360 __ movl(Address(rsi, 0), rax); | |
361 __ movl(Address(rsi, 4), rbx); | |
362 __ movl(Address(rsi, 8), rcx); | |
363 __ movl(Address(rsi,12), rdx); | |
364 | |
365 // | |
366 // Extended cpuid(0x80000001) | |
367 // | |
368 __ bind(ext_cpuid1); | |
369 __ movl(rax, 0x80000001); | |
370 __ cpuid(); | |
371 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
372 __ movl(Address(rsi, 0), rax); | |
373 __ movl(Address(rsi, 4), rbx); | |
374 __ movl(Address(rsi, 8), rcx); | |
375 __ movl(Address(rsi,12), rdx); | |
376 | |
377 // | |
378 // return | |
379 // | |
380 __ bind(done); | |
381 __ popf(); | |
382 __ pop(rsi); | |
383 __ pop(rbx); | |
384 __ pop(rbp); | |
385 __ ret(0); | |
386 | |
387 # undef __ | |
388 | |
389 return start; | |
390 }; | |
391 }; | |
392 | |
393 | |
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394 void VM_Version::get_cpu_info_wrapper() { |
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395 get_cpu_info_stub(&_cpuid_info); |
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396 } |
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397 |
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398 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED |
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399 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() |
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400 #endif |
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401 |
585 | 402 void VM_Version::get_processor_features() { |
403 | |
404 _cpu = 4; // 486 by default | |
405 _model = 0; | |
406 _stepping = 0; | |
407 _cpuFeatures = 0; | |
408 _logical_processors_per_package = 1; | |
409 | |
410 if (!Use486InstrsOnly) { | |
411 // Get raw processor info | |
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412 |
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413 // Some platforms (like Win*) need a wrapper around here |
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414 // in order to properly handle SEGV for YMM registers test. |
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415 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper); |
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416 |
585 | 417 assert_is_initialized(); |
418 _cpu = extended_cpu_family(); | |
419 _model = extended_cpu_model(); | |
420 _stepping = cpu_stepping(); | |
421 | |
422 if (cpu_family() > 4) { // it supports CPUID | |
423 _cpuFeatures = feature_flags(); | |
424 // Logical processors are only available on P4s and above, | |
425 // and only if hyperthreading is available. | |
426 _logical_processors_per_package = logical_processor_count(); | |
427 } | |
428 } | |
429 | |
430 _supports_cx8 = supports_cmpxchg8(); | |
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431 // xchg and xadd instructions |
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432 _supports_atomic_getset4 = true; |
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433 _supports_atomic_getadd4 = true; |
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434 LP64_ONLY(_supports_atomic_getset8 = true); |
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435 LP64_ONLY(_supports_atomic_getadd8 = true); |
585 | 436 |
437 #ifdef _LP64 | |
438 // OS should support SSE for x64 and hardware should support at least SSE2. | |
439 if (!VM_Version::supports_sse2()) { | |
440 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
441 } | |
1060 | 442 // in 64 bit the use of SSE2 is the minimum |
443 if (UseSSE < 2) UseSSE = 2; | |
585 | 444 #endif |
445 | |
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446 #ifdef AMD64 |
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447 // flush_icache_stub have to be generated first. |
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448 // That is why Icache line size is hard coded in ICache class, |
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449 // see icache_x86.hpp. It is also the reason why we can't use |
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450 // clflush instruction in 32-bit VM since it could be running |
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451 // on CPU which does not support it. |
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452 // |
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453 // The only thing we can do is to verify that flushed |
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454 // ICache::line_size has correct value. |
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455 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
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456 // clflush_size is size in quadwords (8 bytes). |
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457 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
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458 #endif |
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459 |
585 | 460 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
461 if (!os::supports_sse()) | |
462 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
463 | |
464 if (UseSSE < 4) { | |
465 _cpuFeatures &= ~CPU_SSE4_1; | |
466 _cpuFeatures &= ~CPU_SSE4_2; | |
467 } | |
468 | |
469 if (UseSSE < 3) { | |
470 _cpuFeatures &= ~CPU_SSE3; | |
471 _cpuFeatures &= ~CPU_SSSE3; | |
472 _cpuFeatures &= ~CPU_SSE4A; | |
473 } | |
474 | |
475 if (UseSSE < 2) | |
476 _cpuFeatures &= ~CPU_SSE2; | |
477 | |
478 if (UseSSE < 1) | |
479 _cpuFeatures &= ~CPU_SSE; | |
480 | |
4759 | 481 if (UseAVX < 2) |
482 _cpuFeatures &= ~CPU_AVX2; | |
483 | |
484 if (UseAVX < 1) | |
485 _cpuFeatures &= ~CPU_AVX; | |
486 | |
6894 | 487 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
488 _cpuFeatures &= ~CPU_AES; | |
489 | |
585 | 490 if (logical_processors_per_package() == 1) { |
491 // HT processor could be installed on a system which doesn't support HT. | |
492 _cpuFeatures &= ~CPU_HT; | |
493 } | |
494 | |
495 char buf[256]; | |
17780 | 496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 497 cores_per_cpu(), threads_per_core(), |
498 cpu_family(), _model, _stepping, | |
499 (supports_cmov() ? ", cmov" : ""), | |
500 (supports_cmpxchg8() ? ", cx8" : ""), | |
501 (supports_fxsr() ? ", fxsr" : ""), | |
502 (supports_mmx() ? ", mmx" : ""), | |
503 (supports_sse() ? ", sse" : ""), | |
504 (supports_sse2() ? ", sse2" : ""), | |
505 (supports_sse3() ? ", sse3" : ""), | |
506 (supports_ssse3()? ", ssse3": ""), | |
507 (supports_sse4_1() ? ", sse4.1" : ""), | |
508 (supports_sse4_2() ? ", sse4.2" : ""), | |
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509 (supports_popcnt() ? ", popcnt" : ""), |
4759 | 510 (supports_avx() ? ", avx" : ""), |
511 (supports_avx2() ? ", avx2" : ""), | |
6894 | 512 (supports_aes() ? ", aes" : ""), |
17780 | 513 (supports_clmul() ? ", clmul" : ""), |
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514 (supports_erms() ? ", erms" : ""), |
17780 | 515 (supports_rtm() ? ", rtm" : ""), |
585 | 516 (supports_mmx_ext() ? ", mmxext" : ""), |
2479 | 517 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
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518 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 519 (supports_sse4a() ? ", sse4a": ""), |
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520 (supports_ht() ? ", ht": ""), |
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521 (supports_tsc() ? ", tsc": ""), |
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522 (supports_tscinv_bit() ? ", tscinvbit": ""), |
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523 (supports_tscinv() ? ", tscinv": ""), |
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524 (supports_bmi1() ? ", bmi1" : ""), |
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525 (supports_bmi2() ? ", bmi2" : "")); |
585 | 526 _features_str = strdup(buf); |
527 | |
528 // UseSSE is set to the smaller of what hardware supports and what | |
529 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
530 // older Pentiums which do not support it. | |
4759 | 531 if (UseSSE > 4) UseSSE=4; |
532 if (UseSSE < 0) UseSSE=0; | |
533 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support | |
585 | 534 UseSSE = MIN2((intx)3,UseSSE); |
4759 | 535 if (!supports_sse3()) // Drop to 2 if no SSE3 support |
585 | 536 UseSSE = MIN2((intx)2,UseSSE); |
4759 | 537 if (!supports_sse2()) // Drop to 1 if no SSE2 support |
585 | 538 UseSSE = MIN2((intx)1,UseSSE); |
4759 | 539 if (!supports_sse ()) // Drop to 0 if no SSE support |
585 | 540 UseSSE = 0; |
541 | |
4759 | 542 if (UseAVX > 2) UseAVX=2; |
543 if (UseAVX < 0) UseAVX=0; | |
544 if (!supports_avx2()) // Drop to 1 if no AVX2 support | |
545 UseAVX = MIN2((intx)1,UseAVX); | |
546 if (!supports_avx ()) // Drop to 0 if no AVX support | |
547 UseAVX = 0; | |
548 | |
6894 | 549 // Use AES instructions if available. |
550 if (supports_aes()) { | |
551 if (FLAG_IS_DEFAULT(UseAES)) { | |
552 UseAES = true; | |
553 } | |
554 } else if (UseAES) { | |
555 if (!FLAG_IS_DEFAULT(UseAES)) | |
17780 | 556 warning("AES instructions are not available on this CPU"); |
6894 | 557 FLAG_SET_DEFAULT(UseAES, false); |
558 } | |
559 | |
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560 // Use CLMUL instructions if available. |
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561 if (supports_clmul()) { |
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562 if (FLAG_IS_DEFAULT(UseCLMUL)) { |
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563 UseCLMUL = true; |
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564 } |
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565 } else if (UseCLMUL) { |
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566 if (!FLAG_IS_DEFAULT(UseCLMUL)) |
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567 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
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568 FLAG_SET_DEFAULT(UseCLMUL, false); |
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569 } |
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570 |
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571 if (UseCLMUL && (UseSSE > 2)) { |
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572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
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573 UseCRC32Intrinsics = true; |
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574 } |
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575 } else if (UseCRC32Intrinsics) { |
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576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
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577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)"); |
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578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
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579 } |
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580 |
6894 | 581 // The AES intrinsic stubs require AES instruction support (of course) |
7427 | 582 // but also require sse3 mode for instructions it use. |
583 if (UseAES && (UseSSE > 2)) { | |
6894 | 584 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
585 UseAESIntrinsics = true; | |
586 } | |
587 } else if (UseAESIntrinsics) { | |
588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) | |
17780 | 589 warning("AES intrinsics are not available on this CPU"); |
6894 | 590 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
591 } | |
592 | |
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593 if (UseSHA) { |
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594 warning("SHA instructions are not available on this CPU"); |
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595 FLAG_SET_DEFAULT(UseSHA, false); |
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596 } |
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597 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { |
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598 warning("SHA intrinsics are not available on this CPU"); |
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599 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
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600 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
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601 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
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602 } |
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603 |
17780 | 604 // Adjust RTM (Restricted Transactional Memory) flags |
605 if (!supports_rtm() && UseRTMLocking) { | |
606 // Can't continue because UseRTMLocking affects UseBiasedLocking flag | |
607 // setting during arguments processing. See use_biased_locking(). | |
608 // VM_Version_init() is executed after UseBiasedLocking is used | |
609 // in Thread::allocate(). | |
610 vm_exit_during_initialization("RTM instructions are not available on this CPU"); | |
611 } | |
612 | |
613 #if INCLUDE_RTM_OPT | |
614 if (UseRTMLocking) { | |
615 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { | |
616 // RTM locking should be used only for applications with | |
617 // high lock contention. For now we do not use it by default. | |
618 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); | |
619 } | |
620 if (!is_power_of_2(RTMTotalCountIncrRate)) { | |
621 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); | |
622 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); | |
623 } | |
624 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { | |
625 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); | |
626 FLAG_SET_DEFAULT(RTMAbortRatio, 50); | |
627 } | |
628 } else { // !UseRTMLocking | |
629 if (UseRTMForStackLocks) { | |
630 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { | |
631 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); | |
632 } | |
633 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); | |
634 } | |
635 if (UseRTMDeopt) { | |
636 FLAG_SET_DEFAULT(UseRTMDeopt, false); | |
637 } | |
638 if (PrintPreciseRTMLockingStatistics) { | |
639 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); | |
640 } | |
641 } | |
642 #else | |
643 if (UseRTMLocking) { | |
644 // Only C2 does RTM locking optimization. | |
645 // Can't continue because UseRTMLocking affects UseBiasedLocking flag | |
646 // setting during arguments processing. See use_biased_locking(). | |
647 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); | |
648 } | |
649 #endif | |
650 | |
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651 #ifdef COMPILER2 |
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652 if (UseFPUForSpilling) { |
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653 if (UseSSE < 2) { |
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654 // Only supported with SSE2+ |
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655 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
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656 } |
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657 } |
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658 if (MaxVectorSize > 0) { |
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659 if (!is_power_of_2(MaxVectorSize)) { |
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660 warning("MaxVectorSize must be a power of 2"); |
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661 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
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662 } |
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663 if (MaxVectorSize > 32) { |
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664 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
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665 } |
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666 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { |
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667 // 32 bytes vectors (in YMM) are only supported with AVX+ |
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668 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
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669 } |
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670 if (UseSSE < 2) { |
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671 // Vectors (in XMM) are only supported with SSE2+ |
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672 FLAG_SET_DEFAULT(MaxVectorSize, 0); |
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673 } |
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674 #ifdef ASSERT |
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675 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { |
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676 tty->print_cr("State of YMM registers after signal handle:"); |
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677 int nreg = 2 LP64_ONLY(+2); |
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678 const char* ymm_name[4] = {"0", "7", "8", "15"}; |
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679 for (int i = 0; i < nreg; i++) { |
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680 tty->print("YMM%s:", ymm_name[i]); |
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681 for (int j = 7; j >=0; j--) { |
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682 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); |
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683 } |
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684 tty->cr(); |
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685 } |
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686 } |
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687 #endif |
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688 } |
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689 #endif |
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690 |
585 | 691 // On new cpus instructions which update whole XMM register should be used |
692 // to prevent partial register stall due to dependencies on high half. | |
693 // | |
694 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
695 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
696 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
697 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
698 | |
699 if( is_amd() ) { // AMD cpus specific settings | |
700 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
701 // Use it on new AMD cpus starting from Opteron. | |
702 UseAddressNop = true; | |
703 } | |
704 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
705 // Use it on new AMD cpus starting from Opteron. | |
706 UseNewLongLShift = true; | |
707 } | |
708 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
709 if( supports_sse4a() ) { | |
710 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
711 } else { | |
712 UseXmmLoadAndClearUpper = false; | |
713 } | |
714 } | |
715 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
716 if( supports_sse4a() ) { | |
717 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
718 } else { | |
719 UseXmmRegToRegMoveAll = false; | |
720 } | |
721 } | |
722 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
723 if( supports_sse4a() ) { | |
724 UseXmmI2F = true; | |
725 } else { | |
726 UseXmmI2F = false; | |
727 } | |
728 } | |
729 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
730 if( supports_sse4a() ) { | |
731 UseXmmI2D = true; | |
732 } else { | |
733 UseXmmI2D = false; | |
734 } | |
735 } | |
2406 | 736 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
737 if( supports_sse4_2() && UseSSE >= 4 ) { | |
738 UseSSE42Intrinsics = true; | |
739 } | |
740 } | |
775
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741 |
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742 // some defaults for AMD family 15h |
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743 if ( cpu_family() == 0x15 ) { |
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744 // On family 15h processors default is no sw prefetch |
2358 | 745 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
746 AllocatePrefetchStyle = 0; | |
747 } | |
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748 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
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749 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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750 AllocatePrefetchInstr = 3; |
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751 } |
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752 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
6794 | 753 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
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754 UseXMMForArrayCopy = true; |
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755 } |
6794 | 756 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
3276
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757 UseUnalignedLoadStores = true; |
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758 } |
2358 | 759 } |
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760 |
6179
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761 #ifdef COMPILER2 |
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762 if (MaxVectorSize > 16) { |
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763 // Limit vectors size to 16 bytes on current AMD cpus. |
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764 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
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765 } |
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766 #endif // COMPILER2 |
585 | 767 } |
768 | |
769 if( is_intel() ) { // Intel cpus specific settings | |
770 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
771 UseStoreImmI16 = false; // don't use it on Intel cpus | |
772 } | |
773 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
774 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
775 // Use it on all Intel cpus starting from PentiumPro | |
776 UseAddressNop = true; | |
777 } | |
778 } | |
779 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
780 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
781 } | |
782 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
783 if( supports_sse3() ) { | |
784 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
785 } else { | |
786 UseXmmRegToRegMoveAll = false; | |
787 } | |
788 } | |
789 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
790 #ifdef COMPILER2 | |
791 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
792 // For new Intel cpus do the next optimization: | |
793 // don't align the beginning of a loop if there are enough instructions | |
794 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
795 // in current fetch line (OptoLoopAlignment) or the padding | |
796 // is big (> MaxLoopPad). | |
797 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
798 // generated NOP instructions. 11 is the largest size of one | |
799 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
800 MaxLoopPad = 11; | |
801 } | |
802 #endif // COMPILER2 | |
6794 | 803 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
585 | 804 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
805 } | |
6794 | 806 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
807 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { | |
585 | 808 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
809 } | |
810 } | |
6794 | 811 if (supports_sse4_2() && UseSSE >= 4) { |
812 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
681 | 813 UseSSE42Intrinsics = true; |
814 } | |
815 } | |
585 | 816 } |
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817 if ((cpu_family() == 0x06) && |
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818 ((extended_cpu_model() == 0x36) || // Centerton |
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819 (extended_cpu_model() == 0x37) || // Silvermont |
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820 (extended_cpu_model() == 0x4D))) { |
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821 #ifdef COMPILER2 |
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822 if (FLAG_IS_DEFAULT(OptoScheduling)) { |
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823 OptoScheduling = true; |
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824 } |
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825 #endif |
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826 if (supports_sse4_2()) { // Silvermont |
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827 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
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828 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
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829 } |
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830 } |
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831 } |
585 | 832 } |
833 | |
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834 // Use count leading zeros count instruction if available. |
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835 if (supports_lzcnt()) { |
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836 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
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837 UseCountLeadingZerosInstruction = true; |
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838 } |
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839 } else if (UseCountLeadingZerosInstruction) { |
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840 warning("lzcnt instruction is not available on this CPU"); |
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841 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
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842 } |
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843 |
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844 if (supports_bmi1()) { |
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845 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
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846 UseBMI1Instructions = true; |
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847 } |
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848 } else if (UseBMI1Instructions) { |
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849 warning("BMI1 instructions are not available on this CPU"); |
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850 FLAG_SET_DEFAULT(UseBMI1Instructions, false); |
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851 } |
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852 |
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853 // Use count trailing zeros instruction if available |
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854 if (supports_bmi1()) { |
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855 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
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856 UseCountTrailingZerosInstruction = UseBMI1Instructions; |
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857 } |
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858 } else if (UseCountTrailingZerosInstruction) { |
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859 warning("tzcnt instruction is not available on this CPU"); |
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860 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
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861 } |
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862 |
643
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863 // Use population count instruction if available. |
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864 if (supports_popcnt()) { |
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865 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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866 UsePopCountInstruction = true; |
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867 } |
4759 | 868 } else if (UsePopCountInstruction) { |
869 warning("POPCNT instruction is not available on this CPU"); | |
870 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
643
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871 } |
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872 |
7474
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873 // Use fast-string operations if available. |
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874 if (supports_erms()) { |
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875 if (FLAG_IS_DEFAULT(UseFastStosb)) { |
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876 UseFastStosb = true; |
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877 } |
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878 } else if (UseFastStosb) { |
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879 warning("fast-string operations are not available on this CPU"); |
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880 FLAG_SET_DEFAULT(UseFastStosb, false); |
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881 } |
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882 |
6794 | 883 #ifdef COMPILER2 |
884 if (FLAG_IS_DEFAULT(AlignVector)) { | |
885 // Modern processors allow misaligned memory operations for vectors. | |
886 AlignVector = !UseUnalignedLoadStores; | |
887 } | |
888 #endif // COMPILER2 | |
889 | |
585 | 890 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
891 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
892 | |
893 // set valid Prefetch instruction | |
894 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
895 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
2479 | 896 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
897 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; | |
585 | 898 |
899 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
900 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
2479 | 901 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
902 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; | |
585 | 903 |
904 // Allocation prefetch settings | |
3854 | 905 intx cache_line_size = prefetch_data_size(); |
585 | 906 if( cache_line_size > AllocatePrefetchStepSize ) |
907 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 908 |
585 | 909 assert(AllocatePrefetchLines > 0, "invalid value"); |
3854 | 910 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
911 AllocatePrefetchLines = 3; | |
912 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
913 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
914 AllocateInstancePrefetchLines = 1; | |
585 | 915 |
916 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
917 AllocatePrefetchStyle = allocate_prefetch_style(); | |
918 | |
20311
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919 if (is_intel() && cpu_family() == 6 && supports_sse3()) { |
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920 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core |
585 | 921 #ifdef _LP64 |
1622 | 922 AllocatePrefetchDistance = 384; |
585 | 923 #else |
1622 | 924 AllocatePrefetchDistance = 320; |
585 | 925 #endif |
1622 | 926 } |
20311
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927 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
1622 | 928 AllocatePrefetchDistance = 192; |
929 AllocatePrefetchLines = 4; | |
20311
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930 } |
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931 #ifdef COMPILER2 |
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932 if (supports_sse4_2()) { |
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933 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
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934 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
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935 } |
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936 } |
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937 #endif |
585 | 938 } |
939 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
940 | |
941 #ifdef _LP64 | |
942 // Prefetch settings | |
943 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
944 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
945 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
946 #endif | |
947 | |
7587 | 948 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
949 (cache_line_size > ContendedPaddingWidth)) | |
950 ContendedPaddingWidth = cache_line_size; | |
951 | |
585 | 952 #ifndef PRODUCT |
953 if (PrintMiscellaneous && Verbose) { | |
954 tty->print_cr("Logical CPUs per core: %u", | |
955 logical_processors_per_package()); | |
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956 tty->print("UseSSE=%d", (int) UseSSE); |
4759 | 957 if (UseAVX > 0) { |
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958 tty->print(" UseAVX=%d", (int) UseAVX); |
4759 | 959 } |
6894 | 960 if (UseAES) { |
961 tty->print(" UseAES=1"); | |
962 } | |
17739
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963 #ifdef COMPILER2 |
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964 if (MaxVectorSize > 0) { |
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965 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize); |
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966 } |
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967 #endif |
4759 | 968 tty->cr(); |
3854 | 969 tty->print("Allocation"); |
2479 | 970 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
3854 | 971 tty->print_cr(": no prefetching"); |
585 | 972 } else { |
3854 | 973 tty->print(" prefetching: "); |
2479 | 974 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
585 | 975 tty->print("PREFETCHW"); |
976 } else if (UseSSE >= 1) { | |
977 if (AllocatePrefetchInstr == 0) { | |
978 tty->print("PREFETCHNTA"); | |
979 } else if (AllocatePrefetchInstr == 1) { | |
980 tty->print("PREFETCHT0"); | |
981 } else if (AllocatePrefetchInstr == 2) { | |
982 tty->print("PREFETCHT2"); | |
983 } else if (AllocatePrefetchInstr == 3) { | |
984 tty->print("PREFETCHW"); | |
985 } | |
986 } | |
987 if (AllocatePrefetchLines > 1) { | |
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988 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
585 | 989 } else { |
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990 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
585 | 991 } |
992 } | |
993 | |
994 if (PrefetchCopyIntervalInBytes > 0) { | |
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995 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
585 | 996 } |
997 if (PrefetchScanIntervalInBytes > 0) { | |
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998 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
585 | 999 } |
1000 if (PrefetchFieldsAhead > 0) { | |
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1001 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
585 | 1002 } |
7587 | 1003 if (ContendedPaddingWidth > 0) { |
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1004 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
7587 | 1005 } |
585 | 1006 } |
1007 #endif // !PRODUCT | |
1008 } | |
1009 | |
17780 | 1010 bool VM_Version::use_biased_locking() { |
1011 #if INCLUDE_RTM_OPT | |
1012 // RTM locking is most useful when there is high lock contention and | |
1013 // low data contention. With high lock contention the lock is usually | |
1014 // inflated and biased locking is not suitable for that case. | |
1015 // RTM locking code requires that biased locking is off. | |
1016 // Note: we can't switch off UseBiasedLocking in get_processor_features() | |
1017 // because it is used by Thread::allocate() which is called before | |
1018 // VM_Version::initialize(). | |
1019 if (UseRTMLocking && UseBiasedLocking) { | |
1020 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { | |
1021 FLAG_SET_DEFAULT(UseBiasedLocking, false); | |
1022 } else { | |
1023 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); | |
1024 UseBiasedLocking = false; | |
1025 } | |
1026 } | |
1027 #endif | |
1028 return UseBiasedLocking; | |
1029 } | |
1030 | |
585 | 1031 void VM_Version::initialize() { |
1032 ResourceMark rm; | |
1033 // Making this stub must be FIRST use of assembler | |
1034 | |
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1035 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); |
585 | 1036 if (stub_blob == NULL) { |
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1037 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); |
585 | 1038 } |
1748 | 1039 CodeBuffer c(stub_blob); |
585 | 1040 VM_Version_StubGenerator g(&c); |
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1041 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, |
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1042 g.generate_get_cpu_info()); |
585 | 1043 |
1044 get_processor_features(); | |
1045 } |