Mercurial > hg > graal-compiler
diff src/cpu/x86/vm/vm_version_x86.cpp @ 20313:b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
Summary: Add C2 SHA intrinsics on SPARC
Reviewed-by: kvn, roland
Contributed-by: james.cheng@oracle.com
author | kvn |
---|---|
date | Wed, 11 Jun 2014 11:05:10 -0700 |
parents | b1bc1af04c6e |
children | 999824269b71 |
line wrap: on
line diff
--- a/src/cpu/x86/vm/vm_version_x86.cpp Tue Jun 10 12:28:06 2014 -0700 +++ b/src/cpu/x86/vm/vm_version_x86.cpp Wed Jun 11 11:05:10 2014 -0700 @@ -590,6 +590,17 @@ FLAG_SET_DEFAULT(UseAESIntrinsics, false); } + if (UseSHA) { + warning("SHA instructions are not available on this CPU"); + FLAG_SET_DEFAULT(UseSHA, false); + } + if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { + warning("SHA intrinsics are not available on this CPU"); + FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); + FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); + FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); + } + // Adjust RTM (Restricted Transactional Memory) flags if (!supports_rtm() && UseRTMLocking) { // Can't continue because UseRTMLocking affects UseBiasedLocking flag