Mercurial > hg > graal-jvmci-8
annotate src/cpu/x86/vm/x86_32.ad @ 24206:37ba410ffd43 jdk8u141-b08
8173770: Image conversion improvements
Reviewed-by: kvn, vlivanov, dlong, rhalade, mschoene, iignatyev
| author | thartmann |
|---|---|
| date | Thu, 30 Mar 2017 15:28:33 +0200 |
| parents | c3d0bd36ab28 |
| children | 719853999215 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
126 // Class for no registers (empty set). |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
127 reg_class no_reg(); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
128 |
| 0 | 129 // Class for all registers |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
130 reg_class any_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
131 // Class for all registers (excluding EBP) |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
132 reg_class any_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX, ESP); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
133 // Dynamic register class that selects at runtime between register classes |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
134 // any_reg and any_no_ebp_reg (depending on the value of the flag PreserveFramePointer). |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
135 // Equivalent to: return PreserveFramePointer ? any_no_ebp_reg : any_reg; |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
136 reg_class_dynamic any_reg(any_reg_no_ebp, any_reg_with_ebp, %{ PreserveFramePointer %}); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
137 |
| 0 | 138 // Class for general registers |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
139 reg_class int_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
140 // Class for general registers (excluding EBP). |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
141 // This register class can be used for implicit null checks on win95. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
142 // It is also safe for use by tailjumps (we don't want to allocate in ebp). |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
143 // Used also if the PreserveFramePointer flag is true. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
144 reg_class int_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
145 // Dynamic register class that selects between int_reg and int_reg_no_ebp. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
146 reg_class_dynamic int_reg(int_reg_no_ebp, int_reg_with_ebp, %{ PreserveFramePointer %}); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
147 |
| 0 | 148 // Class of "X" registers |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
149 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
150 |
| 0 | 151 // Class of registers that can appear in an address with no offset. |
| 152 // EBP and ESP require an extra instruction byte for zero offset. | |
| 153 // Used in fast-unlock | |
| 154 reg_class p_reg(EDX, EDI, ESI, EBX); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
155 |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
156 // Class for general registers excluding ECX |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
157 reg_class ncx_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, EBX); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
158 // Class for general registers excluding ECX (and EBP) |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
159 reg_class ncx_reg_no_ebp(EAX, EDX, EDI, ESI, EBX); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
160 // Dynamic register class that selects between ncx_reg and ncx_reg_no_ebp. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
161 reg_class_dynamic ncx_reg(ncx_reg_no_ebp, ncx_reg_with_ebp, %{ PreserveFramePointer %}); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
162 |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
163 // Class for general registers excluding EAX |
| 0 | 164 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
165 |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
166 // Class for general registers excluding EAX and EBX. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
167 reg_class nabx_reg_with_ebp(EDX, EDI, ESI, ECX, EBP); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
168 // Class for general registers excluding EAX and EBX (and EBP) |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
169 reg_class nabx_reg_no_ebp(EDX, EDI, ESI, ECX); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
170 // Dynamic register class that selects between nabx_reg and nabx_reg_no_ebp. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
171 reg_class_dynamic nabx_reg(nabx_reg_no_ebp, nabx_reg_with_ebp, %{ PreserveFramePointer %}); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
172 |
| 0 | 173 // Class of EAX (for multiply and divide operations) |
| 174 reg_class eax_reg(EAX); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
175 |
| 0 | 176 // Class of EBX (for atomic add) |
| 177 reg_class ebx_reg(EBX); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
178 |
| 0 | 179 // Class of ECX (for shift and JCXZ operations and cmpLTMask) |
| 180 reg_class ecx_reg(ECX); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
181 |
| 0 | 182 // Class of EDX (for multiply and divide operations) |
| 183 reg_class edx_reg(EDX); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
184 |
| 0 | 185 // Class of EDI (for synchronization) |
| 186 reg_class edi_reg(EDI); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
187 |
| 0 | 188 // Class of ESI (for synchronization) |
| 189 reg_class esi_reg(ESI); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
190 |
| 0 | 191 // Singleton class for stack pointer |
| 192 reg_class sp_reg(ESP); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
193 |
| 0 | 194 // Singleton class for instruction pointer |
| 195 // reg_class ip_reg(EIP); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
196 |
| 0 | 197 // Class of integer register pairs |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
198 reg_class long_reg_with_ebp( EAX,EDX, ECX,EBX, EBP,EDI ); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
199 // Class of integer register pairs (excluding EBP and EDI); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
200 reg_class long_reg_no_ebp( EAX,EDX, ECX,EBX ); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
201 // Dynamic register class that selects between long_reg and long_reg_no_ebp. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
202 reg_class_dynamic long_reg(long_reg_no_ebp, long_reg_with_ebp, %{ PreserveFramePointer %}); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
203 |
| 0 | 204 // Class of integer register pairs that aligns with calling convention |
| 205 reg_class eadx_reg( EAX,EDX ); | |
| 206 reg_class ebcx_reg( ECX,EBX ); | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
207 |
| 0 | 208 // Not AX or DX, used in divides |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
209 reg_class nadx_reg_with_ebp(EBX, ECX, ESI, EDI, EBP); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
210 // Not AX or DX (and neither EBP), used in divides |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
211 reg_class nadx_reg_no_ebp(EBX, ECX, ESI, EDI); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp. |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %}); |
| 0 | 214 |
| 215 // Floating point registers. Notice FPR0 is not a choice. | |
| 216 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 217 // a 2-address instructions out of Intels FP stack. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
219 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
221 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
222 FPR7L,FPR7H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
223 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
224 reg_class fp_flt_reg0( FPR1L ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
225 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
226 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
228 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
229 |
| 0 | 230 %} |
| 231 | |
| 232 | |
| 233 //----------SOURCE BLOCK------------------------------------------------------- | |
| 234 // This is a block of C++ code which provides values, functions, and | |
| 235 // definitions necessary in the rest of the architecture description | |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
236 source_hpp %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
237 // Must be visible to the DFA in dfa_x86_32.cpp |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
238 extern bool is_operand_hi32_zero(Node* n); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
239 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
240 |
| 0 | 241 source %{ |
| 304 | 242 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 243 #define RELOC_DISP32 Assembler::disp32_operand |
| 244 | |
| 245 #define __ _masm. | |
| 246 | |
| 247 // How to find the high register of a Long pair, given the low register | |
| 248 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 249 | |
| 250 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 251 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 252 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 253 | |
| 254 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 255 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 256 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 257 // of 128-bits operands for SSE instructions. | |
| 258 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 259 // Store the value to a 128-bits operand. | |
| 260 operand[0] = lo; | |
| 261 operand[1] = hi; | |
| 262 return operand; | |
| 263 } | |
| 264 | |
| 265 // Buffer for 128-bits masks used by SSE instructions. | |
| 266 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 267 | |
| 268 // Static initialization during VM startup. | |
| 269 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 270 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 271 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 272 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 273 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
274 // Offset hacking within calls. |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
275 static int pre_call_resets_size() { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
276 int size = 0; |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
277 Compile* C = Compile::current(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
278 if (C->in_24_bit_fp_mode()) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
279 size += 6; // fldcw |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
280 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
281 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
282 size += 3; // vzeroupper |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
283 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
284 return size; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
285 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
291 return 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
| 0 | 292 } |
| 293 | |
| 294 int MachCallDynamicJavaNode::ret_addr_offset() { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
295 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 296 } |
| 297 | |
| 298 static int sizeof_FFree_Float_Stack_All = -1; | |
| 299 | |
| 300 int MachCallRuntimeNode::ret_addr_offset() { | |
| 301 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
302 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 303 } |
| 304 | |
| 305 // Indicate if the safepoint node needs the polling page as an input. | |
| 306 // Since x86 does have absolute addressing, it doesn't. | |
| 307 bool SafePointNode::needs_polling_address_input() { | |
| 308 return false; | |
| 309 } | |
| 310 | |
| 311 // | |
| 312 // Compute padding required for nodes which need alignment | |
| 313 // | |
| 314 | |
| 315 // The address of the call instruction needs to be 4-byte aligned to | |
| 316 // ensure that it does not span a cache line so that it can be patched. | |
| 317 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
318 current_offset += pre_call_resets_size(); // skip fldcw, if any |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
319 current_offset += 1; // skip call opcode byte |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
320 return round_to(current_offset, alignment_required()) - current_offset; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
321 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
322 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
323 // The address of the call instruction needs to be 4-byte aligned to |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
324 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 325 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
326 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 327 current_offset += 5; // skip MOV instruction |
| 328 current_offset += 1; // skip call opcode byte | |
| 329 return round_to(current_offset, alignment_required()) - current_offset; | |
| 330 } | |
| 331 | |
| 332 // EMIT_RM() | |
| 333 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 334 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 335 cbuf.insts()->emit_int8(c); |
| 0 | 336 } |
| 337 | |
| 338 // EMIT_CC() | |
| 339 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 340 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 341 cbuf.insts()->emit_int8(c); |
| 0 | 342 } |
| 343 | |
| 344 // EMIT_OPCODE() | |
| 345 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 346 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 347 } |
| 348 | |
| 349 // EMIT_OPCODE() w/ relocation information | |
| 350 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 351 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 352 emit_opcode(cbuf, code); |
| 353 } | |
| 354 | |
| 355 // EMIT_D8() | |
| 356 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 357 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 358 } |
| 359 | |
| 360 // EMIT_D16() | |
| 361 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 362 cbuf.insts()->emit_int16(d16); |
| 0 | 363 } |
| 364 | |
| 365 // EMIT_D32() | |
| 366 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 367 cbuf.insts()->emit_int32(d32); |
| 0 | 368 } |
| 369 | |
| 370 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 371 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 372 int format) { | |
| 1748 | 373 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 374 cbuf.insts()->emit_int32(d32); | |
| 0 | 375 } |
| 376 | |
| 377 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 379 int format) { | |
| 380 #ifdef ASSERT | |
| 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
|
12316
190899198332
7195622: CheckUnhandledOops has limited usefulness now
hseigel
parents:
10169
diff
changeset
|
382 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 383 } |
| 384 #endif | |
| 1748 | 385 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 386 cbuf.insts()->emit_int32(d32); | |
| 0 | 387 } |
| 388 | |
| 389 // Access stack slot for load or store | |
| 390 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 391 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 392 if( -128 <= disp && disp <= 127 ) { | |
| 393 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 394 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 395 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 396 } else { | |
| 397 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 398 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 399 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 400 } | |
| 401 } | |
| 402 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
403 // rRegI ereg, memory mem) %{ // emit_reg_mem |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
404 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 405 // There is no index & no scale, use form without SIB byte |
| 406 if ((index == 0x4) && | |
| 407 (scale == 0) && (base != ESP_enc)) { | |
| 408 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 409 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 410 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 411 } | |
| 412 else { // If 8-bit displacement, mode 0x1 | |
| 413 if ((displace >= -128) && (displace <= 127) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
414 && (disp_reloc == relocInfo::none) ) { |
| 0 | 415 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 416 emit_d8(cbuf, displace); | |
| 417 } | |
| 418 else { // If 32-bit displacement | |
| 419 if (base == -1) { // Special flag for absolute address | |
| 420 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 421 // (manual lies; no SIB needed here) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
422 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
423 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 424 } else { |
| 425 emit_d32 (cbuf, displace); | |
| 426 } | |
| 427 } | |
| 428 else { // Normal base + offset | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, base); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
430 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
431 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 432 } else { |
| 433 emit_d32 (cbuf, displace); | |
| 434 } | |
| 435 } | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 else { // Else, encode with the SIB byte | |
| 440 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 441 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 442 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 443 emit_rm(cbuf, scale, index, base); | |
| 444 } | |
| 445 else { // If 8-bit displacement, mode 0x1 | |
| 446 if ((displace >= -128) && (displace <= 127) | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
447 && (disp_reloc == relocInfo::none) ) { |
| 0 | 448 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 449 emit_rm(cbuf, scale, index, base); | |
| 450 emit_d8(cbuf, displace); | |
| 451 } | |
| 452 else { // If 32-bit displacement | |
| 453 if (base == 0x04 ) { | |
| 454 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 455 emit_rm(cbuf, scale, index, 0x04); | |
| 456 } else { | |
| 457 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 458 emit_rm(cbuf, scale, index, base); | |
| 459 } | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
460 if ( disp_reloc != relocInfo::none ) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
461 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 462 } else { |
| 463 emit_d32 (cbuf, displace); | |
| 464 } | |
| 465 } | |
| 466 } | |
| 467 } | |
| 468 } | |
| 469 | |
| 470 | |
| 471 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 472 if( dst_encoding == src_encoding ) { | |
| 473 // reg-reg copy, use an empty encoding | |
| 474 } else { | |
| 475 emit_opcode( cbuf, 0x8B ); | |
| 476 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 477 } | |
| 478 } | |
| 479 | |
| 4759 | 480 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 481 Label exit; | |
| 482 __ jccb(Assembler::noParity, exit); | |
| 483 __ pushf(); | |
| 484 // | |
| 485 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 486 // zero OF,AF,SF for NaN values. | |
| 487 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 488 // values returns 'less than' result (CF is set). | |
| 489 // Leave the rest of flags unchanged. | |
| 490 // | |
| 491 // 7 6 5 4 3 2 1 0 | |
| 492 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 493 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 494 // | |
| 495 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 496 __ popf(); | |
| 497 __ bind(exit); | |
| 498 } | |
| 499 | |
| 500 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 501 Label done; | |
| 502 __ movl(dst, -1); | |
| 503 __ jcc(Assembler::parity, done); | |
| 504 __ jcc(Assembler::below, done); | |
| 505 __ setb(Assembler::notEqual, dst); | |
| 506 __ movzbl(dst, dst); | |
| 507 __ bind(done); | |
| 0 | 508 } |
| 509 | |
| 510 | |
| 511 //============================================================================= | |
| 2008 | 512 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 513 | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
514 int Compile::ConstantTable::calculate_table_base_offset() const { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
515 return 0; // absolute addressing, no offset |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
516 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
517 |
|
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
518 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
519 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
520 ShouldNotReachHere(); |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
521 } |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
522 |
| 2008 | 523 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 524 // Empty encoding | |
| 525 } | |
| 526 | |
| 527 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 528 return 0; | |
| 529 } | |
| 530 | |
| 531 #ifndef PRODUCT | |
| 532 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 533 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 534 } | |
| 535 #endif | |
| 536 | |
| 537 | |
| 538 //============================================================================= | |
| 0 | 539 #ifndef PRODUCT |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
540 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 541 Compile* C = ra_->C; |
| 542 | |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
543 int framesize = C->frame_size_in_bytes(); |
|
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
544 int bangsize = C->bang_size_in_bytes(); |
| 0 | 545 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
546 // Remove wordSize for return addr which is already pushed. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
547 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
548 |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
549 if (C->need_stack_bang(bangsize)) { |
| 0 | 550 framesize -= wordSize; |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
551 st->print("# stack bang (%d bytes)", bangsize); |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
552 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
553 st->print("PUSH EBP\t# Save EBP"); |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
554 if (PreserveFramePointer) { |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
555 st->print("\n\t"); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
556 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP"); |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
557 } |
| 0 | 558 if (framesize) { |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
559 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
560 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 561 } |
| 562 } else { | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
563 st->print("SUB ESP, #%d\t# Create frame",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
564 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
565 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
566 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
567 if (PreserveFramePointer) { |
|
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
568 st->print("\n\t"); |
|
23451
faef2a237329
8080650: Enable stubs to use frame pointers correctly
zmajo
parents:
23050
diff
changeset
|
569 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP"); |
|
faef2a237329
8080650: Enable stubs to use frame pointers correctly
zmajo
parents:
23050
diff
changeset
|
570 if (framesize > 0) { |
|
faef2a237329
8080650: Enable stubs to use frame pointers correctly
zmajo
parents:
23050
diff
changeset
|
571 st->print("\n\t"); |
|
faef2a237329
8080650: Enable stubs to use frame pointers correctly
zmajo
parents:
23050
diff
changeset
|
572 st->print("ADD EBP, #%d", framesize); |
|
faef2a237329
8080650: Enable stubs to use frame pointers correctly
zmajo
parents:
23050
diff
changeset
|
573 } |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
574 } |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
575 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
576 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
577 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
578 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
579 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
580 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 581 } |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
582 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
583 if( C->in_24_bit_fp_mode() ) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
584 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
585 st->print("FLDCW \t# load 24 bit fpu control word"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
586 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
587 if (UseSSE >= 2 && VerifyFPU) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
588 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
589 st->print("# verify FPU stack (must be clean on entry)"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
590 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
591 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
592 #ifdef ASSERT |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
593 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
594 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
595 st->print("# stack alignment check"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
596 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
597 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
598 st->cr(); |
| 0 | 599 } |
| 600 #endif | |
| 601 | |
| 602 | |
| 603 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 604 Compile* C = ra_->C; | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
605 MacroAssembler _masm(&cbuf); |
| 0 | 606 |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
607 int framesize = C->frame_size_in_bytes(); |
|
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
608 int bangsize = C->bang_size_in_bytes(); |
|
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
609 |
|
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
610 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode()); |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
611 |
| 1748 | 612 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 613 |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
614 if (C->has_mach_constant_base_node()) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
615 // NOTE: We set the table base offset here because users might be |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
616 // emitted before MachConstantBaseNode. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
617 Compile::ConstantTable& constant_table = C->constant_table(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
618 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
619 } |
| 0 | 620 } |
| 621 | |
| 622 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 623 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 624 } | |
| 625 | |
| 626 int MachPrologNode::reloc() const { | |
| 627 return 0; // a large enough number | |
| 628 } | |
| 629 | |
| 630 //============================================================================= | |
| 631 #ifndef PRODUCT | |
| 632 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 633 Compile *C = ra_->C; | |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
634 int framesize = C->frame_size_in_bytes(); |
| 0 | 635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 636 // Remove two words for return addr and rbp, | |
| 637 framesize -= 2*wordSize; | |
| 638 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
639 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
640 st->print("VZEROUPPER"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
641 st->cr(); st->print("\t"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
642 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
643 if (C->in_24_bit_fp_mode()) { |
| 0 | 644 st->print("FLDCW standard control word"); |
| 645 st->cr(); st->print("\t"); | |
| 646 } | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
647 if (framesize) { |
| 0 | 648 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 649 st->cr(); st->print("\t"); | |
| 650 } | |
| 651 st->print_cr("POPL EBP"); st->print("\t"); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
652 if (do_polling() && C->is_method_compilation()) { |
| 0 | 653 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 654 st->cr(); st->print("\t"); | |
| 655 } | |
| 656 } | |
| 657 #endif | |
| 658 | |
| 659 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 660 Compile *C = ra_->C; | |
| 661 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
662 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
663 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
664 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
665 MacroAssembler masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
666 masm.vzeroupper(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
667 } |
| 0 | 668 // If method set FPU control word, restore to standard control word |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
669 if (C->in_24_bit_fp_mode()) { |
| 0 | 670 MacroAssembler masm(&cbuf); |
| 671 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 672 } | |
| 673 | |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
674 int framesize = C->frame_size_in_bytes(); |
| 0 | 675 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 676 // Remove two words for return addr and rbp, | |
| 677 framesize -= 2*wordSize; | |
| 678 | |
| 679 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 680 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
681 if (framesize >= 128) { |
| 0 | 682 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 683 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 684 emit_d32(cbuf, framesize); | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
685 } else if (framesize) { |
| 0 | 686 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 687 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 688 emit_d8(cbuf, framesize); | |
| 689 } | |
| 690 | |
| 691 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 692 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
693 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 694 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 695 emit_opcode(cbuf,0x85); |
| 696 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 697 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 698 } | |
| 699 } | |
| 700 | |
| 701 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 702 Compile *C = ra_->C; | |
| 703 // If method set FPU control word, restore to standard control word | |
| 704 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
705 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
706 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 707 |
|
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
roland
parents:
17810
diff
changeset
|
708 int framesize = C->frame_size_in_bytes(); |
| 0 | 709 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 710 // Remove two words for return addr and rbp, | |
| 711 framesize -= 2*wordSize; | |
| 712 | |
| 713 size++; // popl rbp, | |
| 714 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
715 if (framesize >= 128) { |
| 0 | 716 size += 6; |
| 717 } else { | |
| 718 size += framesize ? 3 : 0; | |
| 719 } | |
| 720 return size; | |
| 721 } | |
| 722 | |
| 723 int MachEpilogNode::reloc() const { | |
| 724 return 0; // a large enough number | |
| 725 } | |
| 726 | |
| 727 const Pipeline * MachEpilogNode::pipeline() const { | |
| 728 return MachNode::pipeline_class(); | |
| 729 } | |
| 730 | |
| 731 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 732 | |
| 733 //============================================================================= | |
| 734 | |
| 735 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 736 static enum RC rc_class( OptoReg::Name reg ) { | |
| 737 | |
| 738 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 739 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 740 | |
| 741 VMReg r = OptoReg::as_VMReg(reg); | |
| 742 if (r->is_Register()) return rc_int; | |
| 743 if (r->is_FloatRegister()) { | |
| 744 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 745 return rc_float; | |
| 746 } | |
| 747 assert(r->is_XMMRegister(), "must be"); | |
| 748 return rc_xmm; | |
| 749 } | |
| 750 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
751 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
752 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 753 if( cbuf ) { |
| 754 emit_opcode (*cbuf, opcode ); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
755 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 756 #ifndef PRODUCT |
| 757 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
758 if( size != 0 ) st->print("\n\t"); |
| 0 | 759 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
760 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
761 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 762 } else { // FLD, FST, PUSH, POP |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
763 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 764 } |
| 765 #endif | |
| 766 } | |
| 767 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 768 return size+3+offset_size; | |
| 769 } | |
| 770 | |
| 771 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 772 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
773 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 774 if (cbuf) { |
| 775 MacroAssembler _masm(cbuf); | |
| 776 if (reg_lo+1 == reg_hi) { // double move? | |
| 777 if (is_load) { | |
| 778 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 779 } else { | |
| 780 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 781 } | |
| 0 | 782 } else { |
| 4759 | 783 if (is_load) { |
| 784 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 785 } else { | |
| 786 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 787 } | |
| 0 | 788 } |
| 789 #ifndef PRODUCT | |
| 4759 | 790 } else if (!do_size) { |
| 791 if (size != 0) st->print("\n\t"); | |
| 792 if (reg_lo+1 == reg_hi) { // double move? | |
| 793 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 794 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 795 Matcher::regName[reg_lo], offset); | |
| 796 else st->print("MOVSD [ESP + #%d],%s", | |
| 797 offset, Matcher::regName[reg_lo]); | |
| 0 | 798 } else { |
| 4759 | 799 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 800 Matcher::regName[reg_lo], offset); | |
| 801 else st->print("MOVSS [ESP + #%d],%s", | |
| 802 offset, Matcher::regName[reg_lo]); | |
| 0 | 803 } |
| 804 #endif | |
| 805 } | |
| 806 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
807 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 808 return size+5+offset_size; |
| 809 } | |
| 810 | |
| 811 | |
| 812 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
813 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 814 if (cbuf) { |
| 815 MacroAssembler _masm(cbuf); | |
| 816 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 817 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 818 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 819 } else { | |
| 820 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 821 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 822 } | |
| 0 | 823 #ifndef PRODUCT |
| 4759 | 824 } else if (!do_size) { |
| 825 if (size != 0) st->print("\n\t"); | |
| 826 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 827 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 829 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 831 } |
| 4759 | 832 } else { |
| 0 | 833 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
834 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 835 } else { |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
836 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 837 } |
| 4759 | 838 } |
| 0 | 839 #endif |
| 840 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
841 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 842 // Only MOVAPS SSE prefix uses 1 byte. |
| 843 int sz = 4; | |
| 844 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 845 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 846 return size + sz; | |
| 0 | 847 } |
| 848 | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
849 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
850 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
851 // 32-bit |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
852 if (cbuf) { |
| 4759 | 853 MacroAssembler _masm(cbuf); |
| 854 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 855 as_Register(Matcher::_regEncode[src_lo])); | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
856 #ifndef PRODUCT |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
857 } else if (!do_size) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
858 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
859 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
860 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
861 return 4; |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
862 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
863 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
864 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
865 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
866 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
867 // 32-bit |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
868 if (cbuf) { |
| 4759 | 869 MacroAssembler _masm(cbuf); |
| 870 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 871 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
872 #ifndef PRODUCT |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
873 } else if (!do_size) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
875 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
876 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
877 return 4; |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
878 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
879 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
880 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 881 if( cbuf ) { |
| 882 emit_opcode(*cbuf, 0x8B ); | |
| 883 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 884 #ifndef PRODUCT | |
| 885 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
886 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
887 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 888 #endif |
| 889 } | |
| 890 return size+2; | |
| 891 } | |
| 892 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
893 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
894 int offset, int size, outputStream* st ) { |
| 0 | 895 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 896 if( cbuf ) { | |
| 897 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 898 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 899 #ifndef PRODUCT | |
| 900 } else if( !do_size ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
901 if( size != 0 ) st->print("\n\t"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
902 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 903 #endif |
| 904 } | |
| 905 size += 2; | |
| 906 } | |
| 907 | |
| 908 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 909 const char *op_str; | |
| 910 int op; | |
| 911 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 912 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 913 op = 0xDD; | |
| 914 } else { // 32-bit store | |
| 915 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 916 op = 0xD9; | |
| 917 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 918 } | |
| 919 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
920 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 921 } |
| 922 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
923 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
924 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
925 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
926 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
927 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
928 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
929 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
930 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
931 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
932 int calc_size = 0; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
933 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
934 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
935 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
936 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
937 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
938 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
939 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
940 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
941 src_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
942 dst_offset += 4; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
943 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
944 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
945 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
946 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
947 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
948 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
949 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
950 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
951 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
952 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
955 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
956 if (cbuf) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
957 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
958 int offset = __ offset(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
959 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
960 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
961 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
962 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
963 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
964 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
965 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
966 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
967 __ pushl(Address(rsp, src_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
968 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
969 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
970 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
971 __ movdqu(Address(rsp, -16), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
972 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
973 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
974 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
975 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
976 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
977 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
978 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
979 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
980 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
981 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
982 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
983 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
984 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
985 int size = __ offset() - offset; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
986 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
987 return size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
988 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
989 } else if (!do_size) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
990 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
991 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
992 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
993 "popl [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
994 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
995 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
996 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
997 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
998 "popq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
999 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1000 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1001 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1002 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1003 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1004 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1005 "movdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1006 "movdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1007 "movdqu xmm0, [rsp - #16]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1008 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1009 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1010 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1011 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1012 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1013 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1014 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1015 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1016 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1017 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1018 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1019 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1020 #endif |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1021 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1022 return calc_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1023 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1024 |
| 0 | 1025 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 1026 // Get registers to move | |
| 1027 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1028 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1029 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1030 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1031 | |
| 1032 enum RC src_second_rc = rc_class(src_second); | |
| 1033 enum RC src_first_rc = rc_class(src_first); | |
| 1034 enum RC dst_second_rc = rc_class(dst_second); | |
| 1035 enum RC dst_first_rc = rc_class(dst_first); | |
| 1036 | |
| 1037 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1038 | |
| 1039 // Generate spill code! | |
| 1040 int size = 0; | |
| 1041 | |
| 1042 if( src_first == dst_first && src_second == dst_second ) | |
| 1043 return size; // Self copy, no move | |
| 1044 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1045 if (bottom_type()->isa_vect() != NULL) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1046 uint ireg = ideal_reg(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1047 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1048 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1049 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1050 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1051 // mem -> mem |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1052 int src_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1053 int dst_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1054 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1055 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1056 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1057 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1058 int stack_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1059 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1060 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1061 int stack_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1062 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1063 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1064 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1065 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1066 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1067 |
| 0 | 1068 // -------------------------------------- |
| 1069 // Check for mem-mem move. push/pop to move. | |
| 1070 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1071 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1072 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1073 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1074 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1075 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1076 } | |
| 1077 // move low bits | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1078 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1079 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1080 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1081 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1082 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1083 } |
| 1084 return size; | |
| 1085 } | |
| 1086 | |
| 1087 // -------------------------------------- | |
| 1088 // Check for integer reg-reg copy | |
| 1089 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1090 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1091 |
| 1092 // Check for integer store | |
| 1093 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1094 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1095 |
| 1096 // Check for integer load | |
| 1097 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1098 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1099 |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1100 // Check for integer reg-xmm reg copy |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1101 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1102 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1103 "no 64 bit integer-float reg moves" ); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1104 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1105 } |
| 0 | 1106 // -------------------------------------- |
| 1107 // Check for float reg-reg copy | |
| 1108 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1109 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1110 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1111 if( cbuf ) { | |
| 1112 | |
| 1113 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1114 // indexing issue mentioned in a comment in the reg_def sections | |
| 1115 // for FPR registers many lines above here. | |
| 1116 | |
| 1117 if( src_first != FPR1L_num ) { | |
| 1118 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1119 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1120 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1121 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1122 } else { | |
| 1123 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1124 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1125 } | |
| 1126 #ifndef PRODUCT | |
| 1127 } else if( !do_size ) { | |
| 1128 if( size != 0 ) st->print("\n\t"); | |
| 1129 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1130 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1131 #endif | |
| 1132 } | |
| 1133 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1134 } | |
| 1135 | |
| 1136 // Check for float store | |
| 1137 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1138 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1139 } |
| 1140 | |
| 1141 // Check for float load | |
| 1142 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1143 int offset = ra_->reg2offset(src_first); | |
| 1144 const char *op_str; | |
| 1145 int op; | |
| 1146 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1147 op_str = "FLD_D"; | |
| 1148 op = 0xDD; | |
| 1149 } else { // 32-bit load | |
| 1150 op_str = "FLD_S"; | |
| 1151 op = 0xD9; | |
| 1152 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1153 } | |
| 1154 if( cbuf ) { | |
| 1155 emit_opcode (*cbuf, op ); | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1156 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1157 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1158 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1159 #ifndef PRODUCT | |
| 1160 } else if( !do_size ) { | |
| 1161 if( size != 0 ) st->print("\n\t"); | |
| 1162 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1163 #endif | |
| 1164 } | |
| 1165 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1166 return size + 3+offset_size+2; | |
| 1167 } | |
| 1168 | |
| 1169 // Check for xmm reg-reg copy | |
| 1170 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1171 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1172 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1173 "no non-adjacent float-moves" ); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1174 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1175 } |
| 1176 | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1177 // Check for xmm reg-integer reg copy |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1178 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1179 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1180 "no 64 bit float-integer reg moves" ); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1181 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1182 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
1183 |
| 0 | 1184 // Check for xmm store |
| 1185 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1186 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1187 } |
| 1188 | |
| 1189 // Check for float xmm load | |
| 1190 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1191 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1192 } |
| 1193 | |
| 1194 // Copy from float reg to xmm reg | |
| 1195 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1196 // copy to the top of stack from floating point reg | |
| 1197 // and use LEA to preserve flags | |
| 1198 if( cbuf ) { | |
| 1199 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1200 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1201 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1202 emit_d8(*cbuf,0xF8); | |
| 1203 #ifndef PRODUCT | |
| 1204 } else if( !do_size ) { | |
| 1205 if( size != 0 ) st->print("\n\t"); | |
| 1206 st->print("LEA ESP,[ESP-8]"); | |
| 1207 #endif | |
| 1208 } | |
| 1209 size += 4; | |
| 1210 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1211 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1212 |
| 1213 // Copy from the temp memory to the xmm reg. | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1214 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1215 |
| 1216 if( cbuf ) { | |
| 1217 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1218 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1219 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1220 emit_d8(*cbuf,0x08); | |
| 1221 #ifndef PRODUCT | |
| 1222 } else if( !do_size ) { | |
| 1223 if( size != 0 ) st->print("\n\t"); | |
| 1224 st->print("LEA ESP,[ESP+8]"); | |
| 1225 #endif | |
| 1226 } | |
| 1227 size += 4; | |
| 1228 return size; | |
| 1229 } | |
| 1230 | |
| 1231 assert( size > 0, "missed a case" ); | |
| 1232 | |
| 1233 // -------------------------------------------------------------------- | |
| 1234 // Check for second bits still needing moving. | |
| 1235 if( src_second == dst_second ) | |
| 1236 return size; // Self copy; no move | |
| 1237 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1238 | |
| 1239 // Check for second word int-int move | |
| 1240 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1241 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1242 |
| 1243 // Check for second word integer store | |
| 1244 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1245 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1246 |
| 1247 // Check for second word integer load | |
| 1248 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1249 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1250 |
| 1251 | |
| 1252 Unimplemented(); | |
| 1253 } | |
| 1254 | |
| 1255 #ifndef PRODUCT | |
| 4950 | 1256 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1257 implementation( NULL, ra_, false, st ); |
| 1258 } | |
| 1259 #endif | |
| 1260 | |
| 1261 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1262 implementation( &cbuf, ra_, false, NULL ); | |
| 1263 } | |
| 1264 | |
| 1265 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1266 return implementation( NULL, ra_, true, NULL ); | |
| 1267 } | |
| 1268 | |
| 1269 | |
| 1270 //============================================================================= | |
| 1271 #ifndef PRODUCT | |
| 1272 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1273 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1274 int reg = ra_->get_reg_first(this); | |
| 1275 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1276 } | |
| 1277 #endif | |
| 1278 | |
| 1279 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1280 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1281 int reg = ra_->get_encode(this); | |
| 1282 if( offset >= 128 ) { | |
| 1283 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1284 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1285 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1286 emit_d32(cbuf, offset); | |
| 1287 } | |
| 1288 else { | |
| 1289 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1290 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1291 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1292 emit_d8(cbuf, offset); | |
| 1293 } | |
| 1294 } | |
| 1295 | |
| 1296 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1297 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1298 if( offset >= 128 ) { | |
| 1299 return 7; | |
| 1300 } | |
| 1301 else { | |
| 1302 return 4; | |
| 1303 } | |
| 1304 } | |
| 1305 | |
| 1306 //============================================================================= | |
| 1307 #ifndef PRODUCT | |
| 1308 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1309 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1310 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1311 st->print_cr("\tNOP"); | |
| 1312 st->print_cr("\tNOP"); | |
| 1313 if( !OptoBreakpoint ) | |
| 1314 st->print_cr("\tNOP"); | |
| 1315 } | |
| 1316 #endif | |
| 1317 | |
| 1318 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1319 MacroAssembler masm(&cbuf); | |
| 1320 #ifdef ASSERT | |
| 1748 | 1321 uint insts_size = cbuf.insts_size(); |
| 0 | 1322 #endif |
| 304 | 1323 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1324 masm.jump_cc(Assembler::notEqual, |
| 1325 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1326 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1327 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1328 int nops_cnt = 2; | |
| 1329 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1330 nops_cnt += 1; | |
| 1331 masm.nop(nops_cnt); | |
| 1332 | |
| 1748 | 1333 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1334 } |
| 1335 | |
| 1336 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1337 return OptoBreakpoint ? 11 : 12; | |
| 1338 } | |
| 1339 | |
| 1340 | |
| 1341 //============================================================================= | |
| 1342 | |
| 1343 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1344 return regnum - 32; // The FP registers are in the second chunk | |
| 1345 } | |
| 1346 | |
| 1347 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1348 const bool Matcher::convL2FSupported(void) { | |
| 1349 return true; | |
| 1350 } | |
| 1351 | |
| 1352 // Is this branch offset short enough that a short branch can be used? | |
| 1353 // | |
| 1354 // NOTE: If the platform does not provide any short branch variants, then | |
| 1355 // this method should return false for offset 0. | |
| 3851 | 1356 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1357 // The passed offset is relative to address of the branch. | |
| 1358 // On 86 a branch displacement is calculated relative to address | |
| 1359 // of a next instruction. | |
| 1360 offset -= br_size; | |
| 1361 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1362 // the short version of jmpConUCF2 contains multiple branches, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1363 // making the reach slightly less |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1364 if (rule == jmpConUCF2_rule) |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1365 return (-126 <= offset && offset <= 125); |
| 0 | 1366 return (-128 <= offset && offset <= 127); |
| 1367 } | |
| 1368 | |
| 1369 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1370 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1371 return false; | |
| 1372 } | |
| 1373 | |
| 1374 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1375 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1376 | |
| 1377 // Threshold size for cleararray. | |
| 1378 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1379 | |
| 4047 | 1380 // Needs 2 CMOV's for longs. |
| 1381 const int Matcher::long_cmove_cost() { return 1; } | |
| 1382 | |
| 1383 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1384 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1385 | |
|
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1386 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1387 const bool Matcher::require_postalloc_expand = false; |
|
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
14422
diff
changeset
|
1388 |
| 0 | 1389 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1390 // be subsumed into complex addressing expressions or compute them into | |
| 1391 // registers? True for Intel but false for most RISCs | |
| 1392 const bool Matcher::clone_shift_expressions = true; | |
| 1393 | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1394 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1395 // the cpu only look at the lower 5/6 bits anyway? |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1396 const bool Matcher::need_masked_shift_count = false; |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1397 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1398 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1399 ShouldNotCallThis(); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1400 return true; |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1401 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1402 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1403 bool Matcher::narrow_klass_use_complex_address() { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1404 ShouldNotCallThis(); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1405 return true; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1406 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1407 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1567
diff
changeset
|
1408 |
| 0 | 1409 // Is it better to copy float constants, or load them directly from memory? |
| 1410 // Intel can load a float constant from a direct address, requiring no | |
| 1411 // extra registers. Most RISCs will have to materialize an address into a | |
| 1412 // register first, so they would do better to copy the constant from stack. | |
| 1413 const bool Matcher::rematerialize_float_constants = true; | |
| 1414 | |
| 1415 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1416 // needed. Else we split the double into 2 integer pieces and move it | |
| 1417 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1418 // Java calling convention forces doubles to be aligned. | |
| 1419 const bool Matcher::misaligned_doubles_ok = true; | |
| 1420 | |
| 1421 | |
| 1422 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1423 // Get the memory operand from the node | |
| 1424 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1425 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1426 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1427 uint opcnt = 1; // First operand | |
| 1428 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1429 while( idx >= skipped+num_edges ) { | |
| 1430 skipped += num_edges; | |
| 1431 opcnt++; // Bump operand count | |
| 1432 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1433 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1434 } | |
| 1435 | |
| 1436 MachOper *memory = node->_opnds[opcnt]; | |
| 1437 MachOper *new_memory = NULL; | |
| 1438 switch (memory->opcode()) { | |
| 1439 case DIRECT: | |
| 1440 case INDOFFSET32X: | |
| 1441 // No transformation necessary. | |
| 1442 return; | |
| 1443 case INDIRECT: | |
| 1444 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1445 break; | |
| 1446 case INDOFFSET8: | |
| 1447 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1448 break; | |
| 1449 case INDOFFSET32: | |
| 1450 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1451 break; | |
| 1452 case INDINDEXOFFSET: | |
| 1453 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1454 break; | |
| 1455 case INDINDEXSCALE: | |
| 1456 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1457 break; | |
| 1458 case INDINDEXSCALEOFFSET: | |
| 1459 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1460 break; | |
| 1461 case LOAD_LONG_INDIRECT: | |
| 1462 case LOAD_LONG_INDOFFSET32: | |
| 1463 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1464 return; | |
| 1465 default: | |
| 1466 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1467 return; | |
| 1468 } | |
| 1469 node->_opnds[opcnt] = new_memory; | |
| 1470 } | |
| 1471 | |
| 1472 // Advertise here if the CPU requires explicit rounding operations | |
| 1473 // to implement the UseStrictFP mode. | |
| 1474 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1475 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1476 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1477 // On x32 it is stored with convertion only when FPU is used for floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1478 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1479 |
| 0 | 1480 // Do ints take an entire long register or just half? |
| 1481 const bool Matcher::int_in_long = false; | |
| 1482 | |
| 1483 // Return whether or not this register is ever used as an argument. This | |
| 1484 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1485 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1486 // arguments in those registers not be available to the callee. | |
| 1487 bool Matcher::can_be_java_arg( int reg ) { | |
| 1488 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1489 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1490 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1491 return false; | |
| 1492 } | |
| 1493 | |
| 1494 bool Matcher::is_spillable_arg( int reg ) { | |
| 1495 return can_be_java_arg(reg); | |
| 1496 } | |
| 1497 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1498 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1499 // Use hardware integer DIV instruction when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1500 // it is faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1501 // Only when constant divisor fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1502 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1503 // positive 32 bit values from negative). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1504 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1505 (divisor == (int)divisor && divisor != min_jint); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1506 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1507 |
| 0 | 1508 // Register for DIVI projection of divmodI |
| 1509 RegMask Matcher::divI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1510 return EAX_REG_mask(); |
| 0 | 1511 } |
| 1512 | |
| 1513 // Register for MODI projection of divmodI | |
| 1514 RegMask Matcher::modI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1515 return EDX_REG_mask(); |
| 0 | 1516 } |
| 1517 | |
| 1518 // Register for DIVL projection of divmodL | |
| 1519 RegMask Matcher::divL_proj_mask() { | |
| 1520 ShouldNotReachHere(); | |
| 1521 return RegMask(); | |
| 1522 } | |
| 1523 | |
| 1524 // Register for MODL projection of divmodL | |
| 1525 RegMask Matcher::modL_proj_mask() { | |
| 1526 ShouldNotReachHere(); | |
| 1527 return RegMask(); | |
| 1528 } | |
| 1529 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1530 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
1531 return NO_REG_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1532 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1533 |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1534 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1535 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1536 int opc = n->Opcode(); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1537 if (opc == Op_AndL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1538 Node* o2 = n->in(2); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1539 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1540 return true; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1541 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1542 } |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1543 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1544 return true; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1545 } |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1546 return false; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1547 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1548 |
| 0 | 1549 %} |
| 1550 | |
| 1551 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1552 // This block specifies the encoding classes used by the compiler to output | |
| 1553 // byte streams. Encoding classes generate functions which are called by | |
| 1554 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1555 // instruction. Operands specify their base encoding interface with the | |
| 1556 // interface keyword. There are currently supported four interfaces, | |
| 1557 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1558 // operand to generate a function which returns its register number when | |
| 1559 // queried. CONST_INTER causes an operand to generate a function which | |
| 1560 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1561 // operand to generate four functions which return the Base Register, the | |
| 1562 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1563 // queried. COND_INTER causes an operand to generate six functions which | |
| 1564 // return the encoding code (ie - encoding bits for the instruction) | |
| 1565 // associated with each basic boolean condition for a conditional instruction. | |
| 1566 // Instructions specify two basic values for encoding. They use the | |
| 1567 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1568 // the class names specified in the encoding block), and they use the | |
| 1569 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1570 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1571 // needs for encoding need to be specified. | |
| 1572 encode %{ | |
| 1573 // Build emit functions for each basic byte or larger field in the intel | |
| 1574 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1575 // code in the enc_class source block. Emit functions will live in the | |
| 1576 // main source block for now. In future, we can generalize this by | |
| 1577 // adding a syntax that specifies the sizes of fields in an order, | |
| 1578 // so that the adlc can build the emit functions automagically | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1579 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1580 // Emit primary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1581 enc_class OpcP %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1582 emit_opcode(cbuf, $primary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1583 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1584 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1585 // Emit secondary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1586 enc_class OpcS %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1587 emit_opcode(cbuf, $secondary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1588 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1589 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1590 // Emit opcode directly |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1591 enc_class Opcode(immI d8) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1592 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1593 %} |
| 1594 | |
| 1595 enc_class SizePrefix %{ | |
| 1596 emit_opcode(cbuf,0x66); | |
| 1597 %} | |
| 1598 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1599 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1600 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1601 %} | |
| 1602 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1603 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1604 emit_opcode(cbuf,$opcode$$constant); |
| 1605 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1606 %} | |
| 1607 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1608 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1609 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1610 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1611 %} | |
| 1612 | |
| 1613 enc_class cdq_enc %{ | |
| 1614 // Full implementation of Java idiv and irem; checks for | |
| 1615 // special case as described in JVM spec., p.243 & p.271. | |
| 1616 // | |
| 1617 // normal case special case | |
| 1618 // | |
| 1619 // input : rax,: dividend min_int | |
| 1620 // reg: divisor -1 | |
| 1621 // | |
| 1622 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1623 // rdx: remainder (= rax, irem reg) 0 | |
| 1624 // | |
| 1625 // Code sequnce: | |
| 1626 // | |
| 1627 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1628 // 0F 85 0B 00 00 00 jne normal_case | |
| 1629 // 33 D2 xor rdx,edx | |
| 1630 // 83 F9 FF cmp rcx,0FFh | |
| 1631 // 0F 84 03 00 00 00 je done | |
| 1632 // normal_case: | |
| 1633 // 99 cdq | |
| 1634 // F7 F9 idiv rax,ecx | |
| 1635 // done: | |
| 1636 // | |
| 1637 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1639 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1640 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1641 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1643 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1644 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1645 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1646 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1647 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1648 // normal_case: | |
| 1649 emit_opcode(cbuf,0x99); // cdq | |
| 1650 // idiv (note: must be emitted by the user of this rule) | |
| 1651 // normal: | |
| 1652 %} | |
| 1653 | |
| 1654 // Dense encoding for older common ops | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1655 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1656 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1657 %} | |
| 1658 | |
| 1659 | |
| 1660 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1661 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1662 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1663 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1664 emit_opcode(cbuf, $primary | 0x02); | |
| 1665 } | |
| 1666 else { // If 32-bit immediate | |
| 1667 emit_opcode(cbuf, $primary); | |
| 1668 } | |
| 1669 %} | |
| 1670 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1671 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1672 // Emit primary opcode and set sign-extend bit |
| 1673 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1675 emit_opcode(cbuf, $primary | 0x02); } | |
| 1676 else { // If 32-bit immediate | |
| 1677 emit_opcode(cbuf, $primary); | |
| 1678 } | |
| 1679 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1680 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1681 %} | |
| 1682 | |
| 1683 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1684 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1686 $$$emit8$imm$$constant; | |
| 1687 } | |
| 1688 else { // If 32-bit immediate | |
| 1689 // Output immediate | |
| 1690 $$$emit32$imm$$constant; | |
| 1691 } | |
| 1692 %} | |
| 1693 | |
| 1694 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1695 // Emit primary opcode and set sign-extend bit | |
| 1696 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1697 int con = (int)$imm$$constant; // Throw away top bits | |
| 1698 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1699 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1700 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1701 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1702 else emit_d32(cbuf,con); | |
| 1703 %} | |
| 1704 | |
| 1705 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1706 // Emit primary opcode and set sign-extend bit | |
| 1707 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1708 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1710 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1711 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1713 else emit_d32(cbuf,con); | |
| 1714 %} | |
| 1715 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1716 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1717 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1718 %} | |
| 1719 | |
| 1720 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1721 int destlo = $dst$$reg; | |
| 1722 int desthi = HIGH_FROM_LOW(destlo); | |
| 1723 // bswap lo | |
| 1724 emit_opcode(cbuf, 0x0F); | |
| 1725 emit_cc(cbuf, 0xC8, destlo); | |
| 1726 // bswap hi | |
| 1727 emit_opcode(cbuf, 0x0F); | |
| 1728 emit_cc(cbuf, 0xC8, desthi); | |
| 1729 // xchg lo and hi | |
| 1730 emit_opcode(cbuf, 0x87); | |
| 1731 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1732 %} | |
| 1733 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1734 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1735 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1736 %} | |
| 1737 | |
| 1738 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1739 $$$emit8$primary; | |
| 1740 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1741 %} | |
| 1742 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
1743 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1744 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1745 emit_d8(cbuf, op >> 8 ); | |
| 1746 emit_d8(cbuf, op & 255); | |
| 1747 %} | |
| 1748 | |
| 1749 // emulate a CMOV with a conditional branch around a MOV | |
| 1750 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1751 // Invert sense of branch from sense of CMOV | |
| 1752 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1753 emit_d8( cbuf, $brOffs$$constant ); | |
| 1754 %} | |
| 1755 | |
| 1756 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1757 Register Redi = as_Register(EDI_enc); // result register | |
| 1758 Register Reax = as_Register(EAX_enc); // super class | |
| 1759 Register Recx = as_Register(ECX_enc); // killed | |
| 1760 Register Resi = as_Register(ESI_enc); // sub class | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1761 Label miss; |
| 0 | 1762 |
| 1763 MacroAssembler _masm(&cbuf); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1764 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1765 NULL, &miss, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1766 /*set_cond_codes:*/ true); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1767 if ($primary) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1768 __ xorptr(Redi, Redi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1769 } |
| 0 | 1770 __ bind(miss); |
| 1771 %} | |
| 1772 | |
| 1773 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1774 MacroAssembler masm(&cbuf); | |
| 1775 int start = masm.offset(); | |
| 1776 if (UseSSE >= 2) { | |
| 1777 if (VerifyFPU) { | |
| 1778 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1779 } | |
| 1780 } else { | |
| 1781 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1782 // Compiled code leaves it dirty. Do cleanup now. | |
| 1783 masm.empty_FPU_stack(); | |
| 1784 } | |
| 1785 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1786 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1787 } else { | |
| 1788 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1789 } | |
| 1790 %} | |
| 1791 | |
| 1792 enc_class Verify_FPU_For_Leaf %{ | |
| 1793 if( VerifyFPU ) { | |
| 1794 MacroAssembler masm(&cbuf); | |
| 1795 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1796 } | |
| 1797 %} | |
| 1798 | |
| 1799 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1800 // This is the instruction starting address for relocation info. | |
| 1748 | 1801 cbuf.set_insts_mark(); |
| 0 | 1802 $$$emit8$primary; |
| 1803 // CALL directly to the runtime | |
| 1748 | 1804 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1805 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1806 | |
| 1807 if (UseSSE >= 2) { | |
| 1808 MacroAssembler _masm(&cbuf); | |
| 1809 BasicType rt = tf()->return_type(); | |
| 1810 | |
| 1811 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1812 // A C runtime call where the return value is unused. In SSE2+ | |
| 1813 // mode the result needs to be removed from the FPU stack. It's | |
| 1814 // likely that this function call could be removed by the | |
| 1815 // optimizer if the C function is a pure function. | |
| 1816 __ ffree(0); | |
| 1817 } else if (rt == T_FLOAT) { | |
| 304 | 1818 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1819 __ fstp_s(Address(rsp, 0)); |
| 1820 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1821 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1822 } else if (rt == T_DOUBLE) { |
| 304 | 1823 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1824 __ fstp_d(Address(rsp, 0)); |
| 1825 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1826 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1827 } |
| 1828 } | |
| 1829 %} | |
| 1830 | |
| 1831 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1832 enc_class pre_call_resets %{ |
| 0 | 1833 // If method sets FPU control word restore it here |
| 1748 | 1834 debug_only(int off0 = cbuf.insts_size()); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1835 if (ra_->C->in_24_bit_fp_mode()) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1836 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1837 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1838 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1839 if (ra_->C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1840 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1841 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1842 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1843 __ vzeroupper(); |
| 0 | 1844 } |
| 1748 | 1845 debug_only(int off1 = cbuf.insts_size()); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1846 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1847 %} |
| 1848 | |
| 1849 enc_class post_call_FPU %{ | |
| 1850 // If method sets FPU control word do it here also | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1851 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1852 MacroAssembler masm(&cbuf); |
| 1853 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1854 } | |
| 1855 %} | |
| 1856 | |
| 1857 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1858 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1859 // who we intended to call. | |
| 1748 | 1860 cbuf.set_insts_mark(); |
| 0 | 1861 $$$emit8$primary; |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1862 if (!_method) { |
| 1748 | 1863 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1864 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1865 } else if (_optimized_virtual) { |
| 1748 | 1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1867 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1868 } else { | |
| 1748 | 1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1870 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1871 } | |
|
10168
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
8873
diff
changeset
|
1872 if (_method) { // Emit stub for static call. |
|
24000
c3d0bd36ab28
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
vkempik
parents:
23451
diff
changeset
|
1873 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
c3d0bd36ab28
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
vkempik
parents:
23451
diff
changeset
|
1874 if (stub == NULL) { |
|
c3d0bd36ab28
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
vkempik
parents:
23451
diff
changeset
|
1875 ciEnv::current()->record_failure("CodeCache is full"); |
|
c3d0bd36ab28
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
vkempik
parents:
23451
diff
changeset
|
1876 return; |
|
c3d0bd36ab28
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space
vkempik
parents:
23451
diff
changeset
|
1877 } |
| 0 | 1878 } |
| 1879 %} | |
| 1880 | |
| 1881 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1882 MacroAssembler _masm(&cbuf); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1883 __ ic_call((address)$meth$$method); |
| 0 | 1884 %} |
| 1885 | |
| 1886 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1887 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1888 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1889 | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
1890 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1891 cbuf.set_insts_mark(); |
| 0 | 1892 $$$emit8$primary; |
| 1893 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1894 emit_d8(cbuf, disp); // Displacement | |
| 1895 | |
| 1896 %} | |
| 1897 | |
| 1898 // Following encoding is no longer used, but may be restored if calling | |
| 1899 // convention changes significantly. | |
| 1900 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1901 // | |
| 1902 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1903 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1904 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1905 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1906 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1907 // | |
| 1908 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1909 // // // so we load it immediately before the call | |
| 1910 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1911 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1912 // | |
| 1913 // // xor rbp,ebp | |
| 1914 // emit_opcode(cbuf, 0x33); | |
| 1915 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1916 // | |
| 1917 // // CALL to interpreter. | |
| 1748 | 1918 // cbuf.set_insts_mark(); |
| 0 | 1919 // $$$emit8$primary; |
| 1748 | 1920 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1921 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1922 // %} | |
| 1923 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1924 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1925 $$$emit8$primary; |
| 1926 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1927 $$$emit8$shift$$constant; | |
| 1928 %} | |
| 1929 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1930 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1931 // Load immediate does not have a zero or sign extended version |
| 1932 // for 8-bit immediates | |
| 1933 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1934 $$$emit32$src$$constant; | |
| 1935 %} | |
| 1936 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1937 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1938 // Load immediate does not have a zero or sign extended version |
| 1939 // for 8-bit immediates | |
| 1940 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1941 $$$emit32$src$$constant; | |
| 1942 %} | |
| 1943 | |
| 1944 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1945 // Load immediate does not have a zero or sign extended version | |
| 1946 // for 8-bit immediates | |
| 1947 int dst_enc = $dst$$reg; | |
| 1948 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1949 if (src_con == 0) { | |
| 1950 // xor dst, dst | |
| 1951 emit_opcode(cbuf, 0x33); | |
| 1952 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1953 } else { | |
| 1954 emit_opcode(cbuf, $primary + dst_enc); | |
| 1955 emit_d32(cbuf, src_con); | |
| 1956 } | |
| 1957 %} | |
| 1958 | |
| 1959 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1960 // Load immediate does not have a zero or sign extended version | |
| 1961 // for 8-bit immediates | |
| 1962 int dst_enc = $dst$$reg + 2; | |
| 1963 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1964 if (src_con == 0) { | |
| 1965 // xor dst, dst | |
| 1966 emit_opcode(cbuf, 0x33); | |
| 1967 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1968 } else { | |
| 1969 emit_opcode(cbuf, $primary + dst_enc); | |
| 1970 emit_d32(cbuf, src_con); | |
| 1971 } | |
| 1972 %} | |
| 1973 | |
| 1974 | |
| 1975 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1976 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1977 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1978 %} | |
| 1979 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1980 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1981 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1982 %} | |
| 1983 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1984 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1985 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1986 %} | |
| 1987 | |
| 1988 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1989 $$$emit8$primary; | |
| 1990 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1991 %} | |
| 1992 | |
| 1993 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1994 $$$emit8$secondary; | |
| 1995 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1996 %} | |
| 1997 | |
| 1998 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2000 %} | |
| 2001 | |
| 2002 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2003 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2004 %} | |
| 2005 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2006 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 2007 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2008 %} | |
| 2009 | |
| 2010 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2011 // Output immediate | |
| 2012 $$$emit32$src$$constant; | |
| 2013 %} | |
| 2014 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2015 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2016 // Output Float immediate bits |
| 2017 jfloat jf = $src$$constant; | |
| 2018 int jf_as_bits = jint_cast( jf ); | |
| 2019 emit_d32(cbuf, jf_as_bits); | |
| 2020 %} | |
| 2021 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2022 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2023 // Output Float immediate bits |
| 2024 jfloat jf = $src$$constant; | |
| 2025 int jf_as_bits = jint_cast( jf ); | |
| 2026 emit_d32(cbuf, jf_as_bits); | |
| 2027 %} | |
| 2028 | |
| 2029 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2030 // Output immediate | |
| 2031 $$$emit16$src$$constant; | |
| 2032 %} | |
| 2033 | |
| 2034 enc_class Con_d32(immI src) %{ | |
| 2035 emit_d32(cbuf,$src$$constant); | |
| 2036 %} | |
| 2037 | |
| 2038 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2039 // Output immediate memory reference | |
| 2040 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2041 emit_d32(cbuf, 0x00); | |
| 2042 %} | |
| 2043 | |
| 2044 enc_class lock_prefix( ) %{ | |
| 2045 if( os::is_MP() ) | |
| 2046 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2047 %} | |
| 2048 | |
| 2049 // Cmp-xchg long value. | |
| 2050 // Note: we need to swap rbx, and rcx before and after the | |
| 2051 // cmpxchg8 instruction because the instruction uses | |
| 2052 // rcx as the high order word of the new value to store but | |
| 2053 // our register encoding uses rbx,. | |
| 2054 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2055 | |
| 2056 // XCHG rbx,ecx | |
| 2057 emit_opcode(cbuf,0x87); | |
| 2058 emit_opcode(cbuf,0xD9); | |
| 2059 // [Lock] | |
| 2060 if( os::is_MP() ) | |
| 2061 emit_opcode(cbuf,0xF0); | |
| 2062 // CMPXCHG8 [Eptr] | |
| 2063 emit_opcode(cbuf,0x0F); | |
| 2064 emit_opcode(cbuf,0xC7); | |
| 2065 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2066 // XCHG rbx,ecx | |
| 2067 emit_opcode(cbuf,0x87); | |
| 2068 emit_opcode(cbuf,0xD9); | |
| 2069 %} | |
| 2070 | |
| 2071 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2072 // [Lock] | |
| 2073 if( os::is_MP() ) | |
| 2074 emit_opcode(cbuf,0xF0); | |
| 2075 | |
| 2076 // CMPXCHG [Eptr] | |
| 2077 emit_opcode(cbuf,0x0F); | |
| 2078 emit_opcode(cbuf,0xB1); | |
| 2079 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2080 %} | |
| 2081 | |
| 2082 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2083 int res_encoding = $res$$reg; | |
| 2084 | |
| 2085 // MOV res,0 | |
| 2086 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2087 emit_d32( cbuf, 0 ); | |
| 2088 // JNE,s fail | |
| 2089 emit_opcode(cbuf,0x75); | |
| 2090 emit_d8(cbuf, 5 ); | |
| 2091 // MOV res,1 | |
| 2092 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2093 emit_d32( cbuf, 1 ); | |
| 2094 // fail: | |
| 2095 %} | |
| 2096 | |
| 2097 enc_class set_instruction_start( ) %{ | |
| 1748 | 2098 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2099 %} |
| 2100 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2101 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2102 int reg_encoding = $ereg$$reg; |
| 2103 int base = $mem$$base; | |
| 2104 int index = $mem$$index; | |
| 2105 int scale = $mem$$scale; | |
| 2106 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2107 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2108 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2109 %} |
| 2110 | |
| 2111 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2112 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2113 int base = $mem$$base; | |
| 2114 int index = $mem$$index; | |
| 2115 int scale = $mem$$scale; | |
| 2116 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2117 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2118 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2119 %} |
| 2120 | |
| 2121 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2122 int r1, r2; | |
| 2123 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2124 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2125 emit_opcode(cbuf,0x0F); | |
| 2126 emit_opcode(cbuf,$tertiary); | |
| 2127 emit_rm(cbuf, 0x3, r1, r2); | |
| 2128 emit_d8(cbuf,$cnt$$constant); | |
| 2129 emit_d8(cbuf,$primary); | |
| 2130 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2131 emit_d8(cbuf,$cnt$$constant); | |
| 2132 %} | |
| 2133 | |
| 2134 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2135 emit_opcode( cbuf, 0x8B ); // Move | |
| 2136 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2137 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2138 emit_d8(cbuf,$primary); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2139 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2140 emit_d8(cbuf,$cnt$$constant-32); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
2141 } |
| 0 | 2142 emit_d8(cbuf,$primary); |
| 2143 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2144 emit_d8(cbuf,31); | |
| 2145 %} | |
| 2146 | |
| 2147 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2148 int r1, r2; | |
| 2149 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2150 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2151 | |
| 2152 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2153 emit_rm(cbuf, 0x3, r1, r2); | |
| 2154 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2155 emit_opcode(cbuf,$primary); | |
| 2156 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2157 emit_d8(cbuf,$cnt$$constant-32); | |
| 2158 } | |
| 2159 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2160 emit_rm(cbuf, 0x3, r2, r2); | |
| 2161 %} | |
| 2162 | |
| 2163 // Clone of RegMem but accepts an extra parameter to access each | |
| 2164 // half of a double in memory; it never needs relocation info. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2165 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2166 emit_opcode(cbuf,$opcode$$constant); |
| 2167 int reg_encoding = $rm_reg$$reg; | |
| 2168 int base = $mem$$base; | |
| 2169 int index = $mem$$index; | |
| 2170 int scale = $mem$$scale; | |
| 2171 int displace = $mem$$disp + $disp_for_half$$constant; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2172 relocInfo::relocType disp_reloc = relocInfo::none; |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2173 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2174 %} |
| 2175 | |
| 2176 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2177 // | |
| 2178 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2179 // and it never needs relocation information. | |
| 2180 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2181 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2182 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2183 int base = $mem$$base; | |
| 2184 int index = $mem$$index; | |
| 2185 int scale = $mem$$scale; | |
| 2186 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2187 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2188 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2189 %} |
| 2190 | |
| 2191 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2192 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2193 int base = $mem$$base; | |
| 2194 int index = $mem$$index; | |
| 2195 int scale = $mem$$scale; | |
| 2196 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2197 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2198 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2199 %} |
| 2200 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2201 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2202 int reg_encoding = $dst$$reg; |
| 2203 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2204 int index = 0x04; // 0x04 indicates no index | |
| 2205 int scale = 0x00; // 0x00 indicates no scale | |
| 2206 int displace = $src1$$constant; // 0x00 indicates no displacement | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2207 relocInfo::relocType disp_reloc = relocInfo::none; |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2208 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2209 %} |
| 2210 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2211 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2212 // Compare dst,src |
| 2213 emit_opcode(cbuf,0x3B); | |
| 2214 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2215 // jmp dst < src around move | |
| 2216 emit_opcode(cbuf,0x7C); | |
| 2217 emit_d8(cbuf,2); | |
| 2218 // move dst,src | |
| 2219 emit_opcode(cbuf,0x8B); | |
| 2220 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2221 %} | |
| 2222 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2223 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2224 // Compare dst,src |
| 2225 emit_opcode(cbuf,0x3B); | |
| 2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2227 // jmp dst > src around move | |
| 2228 emit_opcode(cbuf,0x7F); | |
| 2229 emit_d8(cbuf,2); | |
| 2230 // move dst,src | |
| 2231 emit_opcode(cbuf,0x8B); | |
| 2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2233 %} | |
| 2234 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2235 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2236 // If src is FPR1, we can just FST to store it. |
| 2237 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2238 int reg_encoding = 0x2; // Just store | |
| 2239 int base = $mem$$base; | |
| 2240 int index = $mem$$index; | |
| 2241 int scale = $mem$$scale; | |
| 2242 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2243 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2244 if( $src$$reg != FPR1L_enc ) { |
| 2245 reg_encoding = 0x3; // Store & pop | |
| 2246 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2247 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2248 } | |
| 1748 | 2249 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2250 emit_opcode(cbuf,$primary); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2251 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2252 %} |
| 2253 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2254 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2255 // NEG $dst |
| 2256 emit_opcode(cbuf,0xF7); | |
| 2257 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2258 %} | |
| 2259 | |
| 2260 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2261 // SETLT $dst | |
| 2262 emit_opcode(cbuf,0x0F); | |
| 2263 emit_opcode(cbuf,0x9C); | |
| 2264 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2265 %} | |
| 2266 | |
| 2267 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2268 int tmpReg = $tmp$$reg; | |
| 2269 | |
| 2270 // SUB $p,$q | |
| 2271 emit_opcode(cbuf,0x2B); | |
| 2272 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2273 // SBB $tmp,$tmp | |
| 2274 emit_opcode(cbuf,0x1B); | |
| 2275 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2276 // AND $tmp,$y | |
| 2277 emit_opcode(cbuf,0x23); | |
| 2278 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2279 // ADD $p,$tmp | |
| 2280 emit_opcode(cbuf,0x03); | |
| 2281 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2282 %} | |
| 2283 | |
| 2284 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2285 // TEST shift,32 | |
| 2286 emit_opcode(cbuf,0xF7); | |
| 2287 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2288 emit_d32(cbuf,0x20); | |
| 2289 // JEQ,s small | |
| 2290 emit_opcode(cbuf, 0x74); | |
| 2291 emit_d8(cbuf, 0x04); | |
| 2292 // MOV $dst.hi,$dst.lo | |
| 2293 emit_opcode( cbuf, 0x8B ); | |
| 2294 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2295 // CLR $dst.lo | |
| 2296 emit_opcode(cbuf, 0x33); | |
| 2297 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2298 // small: | |
| 2299 // SHLD $dst.hi,$dst.lo,$shift | |
| 2300 emit_opcode(cbuf,0x0F); | |
| 2301 emit_opcode(cbuf,0xA5); | |
| 2302 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2303 // SHL $dst.lo,$shift" | |
| 2304 emit_opcode(cbuf,0xD3); | |
| 2305 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2306 %} | |
| 2307 | |
| 2308 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2309 // TEST shift,32 | |
| 2310 emit_opcode(cbuf,0xF7); | |
| 2311 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2312 emit_d32(cbuf,0x20); | |
| 2313 // JEQ,s small | |
| 2314 emit_opcode(cbuf, 0x74); | |
| 2315 emit_d8(cbuf, 0x04); | |
| 2316 // MOV $dst.lo,$dst.hi | |
| 2317 emit_opcode( cbuf, 0x8B ); | |
| 2318 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2319 // CLR $dst.hi | |
| 2320 emit_opcode(cbuf, 0x33); | |
| 2321 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2322 // small: | |
| 2323 // SHRD $dst.lo,$dst.hi,$shift | |
| 2324 emit_opcode(cbuf,0x0F); | |
| 2325 emit_opcode(cbuf,0xAD); | |
| 2326 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2327 // SHR $dst.hi,$shift" | |
| 2328 emit_opcode(cbuf,0xD3); | |
| 2329 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2330 %} | |
| 2331 | |
| 2332 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2333 // TEST shift,32 | |
| 2334 emit_opcode(cbuf,0xF7); | |
| 2335 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2336 emit_d32(cbuf,0x20); | |
| 2337 // JEQ,s small | |
| 2338 emit_opcode(cbuf, 0x74); | |
| 2339 emit_d8(cbuf, 0x05); | |
| 2340 // MOV $dst.lo,$dst.hi | |
| 2341 emit_opcode( cbuf, 0x8B ); | |
| 2342 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2343 // SAR $dst.hi,31 | |
| 2344 emit_opcode(cbuf, 0xC1); | |
| 2345 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2346 emit_d8(cbuf, 0x1F ); | |
| 2347 // small: | |
| 2348 // SHRD $dst.lo,$dst.hi,$shift | |
| 2349 emit_opcode(cbuf,0x0F); | |
| 2350 emit_opcode(cbuf,0xAD); | |
| 2351 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2352 // SAR $dst.hi,$shift" | |
| 2353 emit_opcode(cbuf,0xD3); | |
| 2354 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2355 %} | |
| 2356 | |
| 2357 | |
| 2358 // ----------------- Encodings for floating point unit ----------------- | |
| 2359 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2360 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2361 $$$emit8$primary; |
| 2362 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2363 %} | |
| 2364 | |
| 2365 // Pop argument in FPR0 with FSTP ST(0) | |
| 2366 enc_class PopFPU() %{ | |
| 2367 emit_opcode( cbuf, 0xDD ); | |
| 2368 emit_d8( cbuf, 0xD8 ); | |
| 2369 %} | |
| 2370 | |
| 2371 // !!!!! equivalent to Pop_Reg_F | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2372 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2373 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2374 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2375 %} | |
| 2376 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2377 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2378 emit_opcode( cbuf, 0xD9 ); |
| 2379 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2380 %} | |
| 2381 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2382 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2383 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2384 emit_opcode( cbuf, 0x2D ); | |
| 2385 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2386 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2387 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2388 %} | |
| 2389 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2390 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2391 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2392 emit_opcode( cbuf, 0x2D ); | |
| 2393 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2394 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2395 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2396 %} | |
| 2397 | |
| 2398 // Special case for moving an integer register to a stack slot. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2399 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2400 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2401 %} | |
| 2402 | |
| 2403 // Special case for moving a register to a stack slot. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2404 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2405 // Opcode already emitted |
| 2406 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2407 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2408 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2409 %} | |
| 2410 | |
| 2411 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2412 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2413 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2414 %} | |
| 2415 | |
| 2416 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2417 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2418 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2419 %} | |
| 2420 | |
| 2421 // Same as Pop_Mem_F except for opcode | |
| 2422 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2423 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2424 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2425 %} | |
| 2426 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2427 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2428 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2429 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2430 %} | |
| 2431 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2432 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2433 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2434 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2435 %} | |
| 2436 | |
| 2437 // Push FPU's float to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2438 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2439 int pop = 0x02; |
| 2440 if ($src$$reg != FPR1L_enc) { | |
| 2441 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2442 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2443 pop = 0x03; | |
| 2444 } | |
| 2445 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2446 %} | |
| 2447 | |
| 2448 // Push FPU's double to a stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2449 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2450 int pop = 0x02; |
| 2451 if ($src$$reg != FPR1L_enc) { | |
| 2452 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2453 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2454 pop = 0x03; | |
| 2455 } | |
| 2456 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2457 %} | |
| 2458 | |
| 2459 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2460 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2461 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2462 if ($src$$reg != FPR1L_enc) { | |
| 2463 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2464 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2465 pop = 0xD8; | |
| 2466 } | |
| 2467 emit_opcode( cbuf, 0xDD ); | |
| 2468 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2469 %} | |
| 2470 | |
| 2471 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2472 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2473 // load dst in FPR0 |
| 2474 emit_opcode( cbuf, 0xD9 ); | |
| 2475 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2476 if ($src$$reg != FPR1L_enc) { | |
| 2477 // fincstp | |
| 2478 emit_opcode (cbuf, 0xD9); | |
| 2479 emit_opcode (cbuf, 0xF7); | |
| 2480 // swap src with FPR1: | |
| 2481 // FXCH FPR1 with src | |
| 2482 emit_opcode(cbuf, 0xD9); | |
| 2483 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2484 // fdecstp | |
| 2485 emit_opcode (cbuf, 0xD9); | |
| 2486 emit_opcode (cbuf, 0xF6); | |
| 2487 } | |
| 2488 %} | |
| 2489 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2490 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2491 MacroAssembler _masm(&cbuf); |
| 2492 __ subptr(rsp, 8); | |
| 2493 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2494 __ fld_d(Address(rsp, 0)); | |
| 2495 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2496 __ fld_d(Address(rsp, 0)); | |
| 2497 %} | |
| 2498 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2499 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2500 MacroAssembler _masm(&cbuf); |
| 2501 __ subptr(rsp, 4); | |
| 2502 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2503 __ fld_s(Address(rsp, 0)); | |
| 2504 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2505 __ fld_s(Address(rsp, 0)); | |
| 0 | 2506 %} |
| 2507 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2508 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2509 MacroAssembler _masm(&cbuf); |
| 2510 __ fstp_d(Address(rsp, 0)); | |
| 2511 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2512 __ addptr(rsp, 8); | |
| 0 | 2513 %} |
| 2514 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2515 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2516 MacroAssembler _masm(&cbuf); |
| 2517 __ fstp_s(Address(rsp, 0)); | |
| 2518 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2519 __ addptr(rsp, $d8$$constant); | |
| 0 | 2520 %} |
| 2521 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2522 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2523 MacroAssembler _masm(&cbuf); |
| 2524 __ subptr(rsp, 8); | |
| 2525 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2526 __ fld_d(Address(rsp, 0)); | |
| 0 | 2527 %} |
| 2528 | |
| 2529 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2530 MacroAssembler _masm(&cbuf); |
| 2531 __ subptr(rsp, 8); | |
| 0 | 2532 %} |
| 2533 | |
| 2534 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2535 MacroAssembler _masm(&cbuf); |
| 2536 __ addptr(rsp, 8); | |
| 2537 %} | |
| 2538 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2539 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2540 MacroAssembler _masm(&cbuf); |
| 2541 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2542 __ fld_d(Address(rsp, 0)); | |
| 0 | 2543 %} |
| 2544 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2545 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2546 if ($src$$reg != FPR1L_enc) { |
| 2547 // fincstp | |
| 2548 emit_opcode (cbuf, 0xD9); | |
| 2549 emit_opcode (cbuf, 0xF7); | |
| 2550 // FXCH FPR1 with src | |
| 2551 emit_opcode(cbuf, 0xD9); | |
| 2552 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2553 // fdecstp | |
| 2554 emit_opcode (cbuf, 0xD9); | |
| 2555 emit_opcode (cbuf, 0xF6); | |
| 2556 } | |
| 2557 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2558 // // FSTP FPR$dst$$reg | |
| 2559 // emit_opcode( cbuf, 0xDD ); | |
| 2560 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2561 %} | |
| 2562 | |
| 2563 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2564 // fnstsw ax | |
| 2565 emit_opcode( cbuf, 0xDF ); | |
| 2566 emit_opcode( cbuf, 0xE0 ); | |
| 2567 // sahf | |
| 2568 emit_opcode( cbuf, 0x9E ); | |
| 2569 // jnp ::skip | |
| 2570 emit_opcode( cbuf, 0x7B ); | |
| 2571 emit_opcode( cbuf, 0x05 ); | |
| 2572 %} | |
| 2573 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2574 enc_class emitModDPR() %{ |
| 0 | 2575 // fprem must be iterative |
| 2576 // :: loop | |
| 2577 // fprem | |
| 2578 emit_opcode( cbuf, 0xD9 ); | |
| 2579 emit_opcode( cbuf, 0xF8 ); | |
| 2580 // wait | |
| 2581 emit_opcode( cbuf, 0x9b ); | |
| 2582 // fnstsw ax | |
| 2583 emit_opcode( cbuf, 0xDF ); | |
| 2584 emit_opcode( cbuf, 0xE0 ); | |
| 2585 // sahf | |
| 2586 emit_opcode( cbuf, 0x9E ); | |
| 2587 // jp ::loop | |
| 2588 emit_opcode( cbuf, 0x0F ); | |
| 2589 emit_opcode( cbuf, 0x8A ); | |
| 2590 emit_opcode( cbuf, 0xF4 ); | |
| 2591 emit_opcode( cbuf, 0xFF ); | |
| 2592 emit_opcode( cbuf, 0xFF ); | |
| 2593 emit_opcode( cbuf, 0xFF ); | |
| 2594 %} | |
| 2595 | |
| 2596 enc_class fpu_flags() %{ | |
| 2597 // fnstsw_ax | |
| 2598 emit_opcode( cbuf, 0xDF); | |
| 2599 emit_opcode( cbuf, 0xE0); | |
| 2600 // test ax,0x0400 | |
| 2601 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2602 emit_opcode( cbuf, 0xA9 ); | |
| 2603 emit_d16 ( cbuf, 0x0400 ); | |
| 2604 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2605 // // test rax,0x0400 | |
| 2606 // emit_opcode( cbuf, 0xA9 ); | |
| 2607 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2608 // | |
| 2609 // jz exit (no unordered comparison) | |
| 2610 emit_opcode( cbuf, 0x74 ); | |
| 2611 emit_d8 ( cbuf, 0x02 ); | |
| 2612 // mov ah,1 - treat as LT case (set carry flag) | |
| 2613 emit_opcode( cbuf, 0xB4 ); | |
| 2614 emit_d8 ( cbuf, 0x01 ); | |
| 2615 // sahf | |
| 2616 emit_opcode( cbuf, 0x9E); | |
| 2617 %} | |
| 2618 | |
| 2619 enc_class cmpF_P6_fixup() %{ | |
| 2620 // Fixup the integer flags in case comparison involved a NaN | |
| 2621 // | |
| 2622 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2623 emit_opcode( cbuf, 0x7B ); | |
| 2624 emit_d8 ( cbuf, 0x03 ); | |
| 2625 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2626 emit_opcode( cbuf, 0xB4 ); | |
| 2627 emit_d8 ( cbuf, 0x01 ); | |
| 2628 // SAHF | |
| 2629 emit_opcode( cbuf, 0x9E); | |
| 2630 // NOP // target for branch to avoid branch to branch | |
| 2631 emit_opcode( cbuf, 0x90); | |
| 2632 %} | |
| 2633 | |
| 2634 // fnstsw_ax(); | |
| 2635 // sahf(); | |
| 2636 // movl(dst, nan_result); | |
| 2637 // jcc(Assembler::parity, exit); | |
| 2638 // movl(dst, less_result); | |
| 2639 // jcc(Assembler::below, exit); | |
| 2640 // movl(dst, equal_result); | |
| 2641 // jcc(Assembler::equal, exit); | |
| 2642 // movl(dst, greater_result); | |
| 2643 | |
| 2644 // less_result = 1; | |
| 2645 // greater_result = -1; | |
| 2646 // equal_result = 0; | |
| 2647 // nan_result = -1; | |
| 2648 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2649 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2650 // fnstsw_ax(); |
| 2651 emit_opcode( cbuf, 0xDF); | |
| 2652 emit_opcode( cbuf, 0xE0); | |
| 2653 // sahf | |
| 2654 emit_opcode( cbuf, 0x9E); | |
| 2655 // movl(dst, nan_result); | |
| 2656 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2657 emit_d32( cbuf, -1 ); | |
| 2658 // jcc(Assembler::parity, exit); | |
| 2659 emit_opcode( cbuf, 0x7A ); | |
| 2660 emit_d8 ( cbuf, 0x13 ); | |
| 2661 // movl(dst, less_result); | |
| 2662 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2663 emit_d32( cbuf, -1 ); | |
| 2664 // jcc(Assembler::below, exit); | |
| 2665 emit_opcode( cbuf, 0x72 ); | |
| 2666 emit_d8 ( cbuf, 0x0C ); | |
| 2667 // movl(dst, equal_result); | |
| 2668 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2669 emit_d32( cbuf, 0 ); | |
| 2670 // jcc(Assembler::equal, exit); | |
| 2671 emit_opcode( cbuf, 0x74 ); | |
| 2672 emit_d8 ( cbuf, 0x05 ); | |
| 2673 // movl(dst, greater_result); | |
| 2674 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2675 emit_d32( cbuf, 1 ); | |
| 2676 %} | |
| 2677 | |
| 2678 | |
| 2679 // Compare the longs and set flags | |
| 2680 // BROKEN! Do Not use as-is | |
| 2681 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2682 // CMP $src1.hi,$src2.hi | |
| 2683 emit_opcode( cbuf, 0x3B ); | |
| 2684 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2685 // JNE,s done | |
| 2686 emit_opcode(cbuf,0x75); | |
| 2687 emit_d8(cbuf, 2 ); | |
| 2688 // CMP $src1.lo,$src2.lo | |
| 2689 emit_opcode( cbuf, 0x3B ); | |
| 2690 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2691 // done: | |
| 2692 %} | |
| 2693 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2694 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2695 // mov $dst.lo,$src |
| 2696 int dst_encoding = $dst$$reg; | |
| 2697 int src_encoding = $src$$reg; | |
| 2698 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2699 // mov $dst.hi,$src | |
| 2700 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2701 // sar $dst.hi,31 | |
| 2702 emit_opcode( cbuf, 0xC1 ); | |
| 2703 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2704 emit_d8(cbuf, 0x1F ); | |
| 2705 %} | |
| 2706 | |
| 2707 enc_class convert_long_double( eRegL src ) %{ | |
| 2708 // push $src.hi | |
| 2709 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2710 // push $src.lo | |
| 2711 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2712 // fild 64-bits at [SP] | |
| 2713 emit_opcode(cbuf,0xdf); | |
| 2714 emit_d8(cbuf, 0x6C); | |
| 2715 emit_d8(cbuf, 0x24); | |
| 2716 emit_d8(cbuf, 0x00); | |
| 2717 // pop stack | |
| 2718 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2719 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2720 emit_d8(cbuf, 0x8); | |
| 2721 %} | |
| 2722 | |
| 2723 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2724 // IMUL EDX:EAX,$src1 | |
| 2725 emit_opcode( cbuf, 0xF7 ); | |
| 2726 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2727 // SAR EDX,$cnt-32 | |
| 2728 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2729 if (shift_count > 0) { | |
| 2730 emit_opcode(cbuf, 0xC1); | |
| 2731 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2732 emit_d8(cbuf, shift_count); | |
| 2733 } | |
| 2734 %} | |
| 2735 | |
| 2736 // this version doesn't have add sp, 8 | |
| 2737 enc_class convert_long_double2( eRegL src ) %{ | |
| 2738 // push $src.hi | |
| 2739 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2740 // push $src.lo | |
| 2741 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2742 // fild 64-bits at [SP] | |
| 2743 emit_opcode(cbuf,0xdf); | |
| 2744 emit_d8(cbuf, 0x6C); | |
| 2745 emit_d8(cbuf, 0x24); | |
| 2746 emit_d8(cbuf, 0x00); | |
| 2747 %} | |
| 2748 | |
| 2749 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2750 // Basic idea: long = (long)int * (long)int | |
| 2751 // IMUL EDX:EAX, src | |
| 2752 emit_opcode( cbuf, 0xF7 ); | |
| 2753 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2754 %} | |
| 2755 | |
| 2756 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2757 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2758 // MUL EDX:EAX, src | |
| 2759 emit_opcode( cbuf, 0xF7 ); | |
| 2760 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2761 %} | |
| 2762 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2763 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2764 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2765 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2766 // MOV $tmp,$src.lo | |
| 2767 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2768 // IMUL $tmp,EDX | |
| 2769 emit_opcode( cbuf, 0x0F ); | |
| 2770 emit_opcode( cbuf, 0xAF ); | |
| 2771 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2772 // MOV EDX,$src.hi | |
| 2773 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2774 // IMUL EDX,EAX | |
| 2775 emit_opcode( cbuf, 0x0F ); | |
| 2776 emit_opcode( cbuf, 0xAF ); | |
| 2777 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2778 // ADD $tmp,EDX | |
| 2779 emit_opcode( cbuf, 0x03 ); | |
| 2780 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2781 // MUL EDX:EAX,$src.lo | |
| 2782 emit_opcode( cbuf, 0xF7 ); | |
| 2783 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2784 // ADD EDX,ESI | |
| 2785 emit_opcode( cbuf, 0x03 ); | |
| 2786 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2787 %} | |
| 2788 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2789 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2790 // Basic idea: lo(result) = lo(src * y_lo) |
| 2791 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2792 // IMUL $tmp,EDX,$src | |
| 2793 emit_opcode( cbuf, 0x6B ); | |
| 2794 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2795 emit_d8( cbuf, (int)$src$$constant ); | |
| 2796 // MOV EDX,$src | |
| 2797 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2798 emit_d32( cbuf, (int)$src$$constant ); | |
| 2799 // MUL EDX:EAX,EDX | |
| 2800 emit_opcode( cbuf, 0xF7 ); | |
| 2801 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2802 // ADD EDX,ESI | |
| 2803 emit_opcode( cbuf, 0x03 ); | |
| 2804 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2805 %} | |
| 2806 | |
| 2807 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2808 // PUSH src1.hi | |
| 2809 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2810 // PUSH src1.lo | |
| 2811 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2812 // PUSH src2.hi | |
| 2813 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2814 // PUSH src2.lo | |
| 2815 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2816 // CALL directly to the runtime | |
| 1748 | 2817 cbuf.set_insts_mark(); |
| 0 | 2818 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2819 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2820 // Restore stack |
| 2821 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2822 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2823 emit_d8(cbuf, 4*4); | |
| 2824 %} | |
| 2825 | |
| 2826 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2827 // PUSH src1.hi | |
| 2828 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2829 // PUSH src1.lo | |
| 2830 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2831 // PUSH src2.hi | |
| 2832 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2833 // PUSH src2.lo | |
| 2834 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2835 // CALL directly to the runtime | |
| 1748 | 2836 cbuf.set_insts_mark(); |
| 0 | 2837 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2838 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2839 // Restore stack |
| 2840 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2841 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2842 emit_d8(cbuf, 4*4); | |
| 2843 %} | |
| 2844 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2845 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2846 // MOV $tmp,$src.lo |
| 2847 emit_opcode(cbuf, 0x8B); | |
| 2848 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2849 // OR $tmp,$src.hi | |
| 2850 emit_opcode(cbuf, 0x0B); | |
| 2851 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2852 %} | |
| 2853 | |
| 2854 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2855 // CMP $src1.lo,$src2.lo | |
| 2856 emit_opcode( cbuf, 0x3B ); | |
| 2857 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2858 // JNE,s skip | |
| 2859 emit_cc(cbuf, 0x70, 0x5); | |
| 2860 emit_d8(cbuf,2); | |
| 2861 // CMP $src1.hi,$src2.hi | |
| 2862 emit_opcode( cbuf, 0x3B ); | |
| 2863 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2864 %} | |
| 2865 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2866 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2867 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2868 emit_opcode( cbuf, 0x3B ); | |
| 2869 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2870 // MOV $tmp,$src1.hi | |
| 2871 emit_opcode( cbuf, 0x8B ); | |
| 2872 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2873 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2874 emit_opcode( cbuf, 0x1B ); | |
| 2875 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2876 %} | |
| 2877 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2878 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2879 // XOR $tmp,$tmp |
| 2880 emit_opcode(cbuf,0x33); // XOR | |
| 2881 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2882 // CMP $tmp,$src.lo | |
| 2883 emit_opcode( cbuf, 0x3B ); | |
| 2884 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2885 // SBB $tmp,$src.hi | |
| 2886 emit_opcode( cbuf, 0x1B ); | |
| 2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2888 %} | |
| 2889 | |
| 2890 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2891 enc_class neg_long( eRegL dst ) %{ | |
| 2892 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2893 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2894 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2895 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2896 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2897 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2898 emit_d8 (cbuf,0 ); | |
| 2899 %} | |
| 2900 | |
| 2901 enc_class enc_pop_rdx() %{ | |
| 2902 emit_opcode(cbuf,0x5A); | |
| 2903 %} | |
| 2904 | |
| 2905 enc_class enc_rethrow() %{ | |
| 1748 | 2906 cbuf.set_insts_mark(); |
| 0 | 2907 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 2908 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 2909 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 2910 %} | |
| 2911 | |
| 2912 | |
| 2913 // Convert a double to an int. Java semantics require we do complex | |
| 2914 // manglelations in the corner cases. So we set the rounding mode to | |
| 2915 // 'zero', store the darned double down as an int, and reset the | |
| 2916 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 2917 // patches up the correct value directly to the stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2918 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 2919 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 2920 // exceptions here, so that a NAN or other corner-case value will | |
| 2921 // thrown an exception (but normal values get converted at full speed). | |
| 2922 // However, I2C adapters and other float-stack manglers leave pending | |
| 2923 // invalid-op exceptions hanging. We would have to clear them before | |
| 2924 // enabling them and that is more expensive than just testing for the | |
| 2925 // invalid value Intel stores down in the corner cases. | |
| 2926 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 2927 emit_opcode(cbuf,0x2D); | |
| 2928 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2929 // Allocate a word | |
| 2930 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2931 emit_opcode(cbuf,0xEC); | |
| 2932 emit_d8(cbuf,0x04); | |
| 2933 // Encoding assumes a double has been pushed into FPR0. | |
| 2934 // Store down the double as an int, popping the FPU stack | |
| 2935 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 2936 emit_opcode(cbuf,0x1C); | |
| 2937 emit_d8(cbuf,0x24); | |
| 2938 // Restore the rounding mode; mask the exception | |
| 2939 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2940 emit_opcode(cbuf,0x2D); | |
| 2941 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2942 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2943 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2944 | |
| 2945 // Load the converted int; adjust CPU stack | |
| 2946 emit_opcode(cbuf,0x58); // POP EAX | |
| 2947 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 2948 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2949 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2950 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2951 // Push src onto stack slow-path | |
| 2952 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2953 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2954 // CALL directly to the runtime | |
| 1748 | 2955 cbuf.set_insts_mark(); |
| 0 | 2956 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2957 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2958 // Carry on here... |
| 2959 %} | |
| 2960 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2961 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 2962 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 2963 emit_opcode(cbuf,0x2D); | |
| 2964 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2965 // Allocate a word | |
| 2966 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2967 emit_opcode(cbuf,0xEC); | |
| 2968 emit_d8(cbuf,0x08); | |
| 2969 // Encoding assumes a double has been pushed into FPR0. | |
| 2970 // Store down the double as a long, popping the FPU stack | |
| 2971 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 2972 emit_opcode(cbuf,0x3C); | |
| 2973 emit_d8(cbuf,0x24); | |
| 2974 // Restore the rounding mode; mask the exception | |
| 2975 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2976 emit_opcode(cbuf,0x2D); | |
| 2977 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2978 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2979 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2980 | |
| 2981 // Load the converted int; adjust CPU stack | |
| 2982 emit_opcode(cbuf,0x58); // POP EAX | |
| 2983 emit_opcode(cbuf,0x5A); // POP EDX | |
| 2984 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 2985 emit_d8 (cbuf,0xFA); // rdx | |
| 2986 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2987 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2988 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 2989 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 2990 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 2991 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2992 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2993 // Push src onto stack slow-path | |
| 2994 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2995 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2996 // CALL directly to the runtime | |
| 1748 | 2997 cbuf.set_insts_mark(); |
| 0 | 2998 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2999 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3000 // Carry on here... |
| 3001 %} | |
| 3002 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3003 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3004 // Operand was loaded from memory into fp ST (stack top) |
| 3005 // FMUL ST,$src /* D8 C8+i */ | |
| 3006 emit_opcode(cbuf, 0xD8); | |
| 3007 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3008 %} | |
| 3009 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3010 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3011 // FADDP ST,src2 /* D8 C0+i */ |
| 3012 emit_opcode(cbuf, 0xD8); | |
| 3013 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3014 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3015 %} | |
| 3016 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3017 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3018 // FADDP src2,ST /* DE C0+i */ |
| 3019 emit_opcode(cbuf, 0xDE); | |
| 3020 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3021 %} | |
| 3022 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3023 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3024 // Operand has been loaded into fp ST (stack top) |
| 3025 // FSUB ST,$src1 | |
| 3026 emit_opcode(cbuf, 0xD8); | |
| 3027 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3028 | |
| 3029 // FDIV | |
| 3030 emit_opcode(cbuf, 0xD8); | |
| 3031 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3032 %} | |
| 3033 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3034 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3035 // Operand was loaded from memory into fp ST (stack top) |
| 3036 // FADD ST,$src /* D8 C0+i */ | |
| 3037 emit_opcode(cbuf, 0xD8); | |
| 3038 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3039 | |
| 3040 // FMUL ST,src2 /* D8 C*+i */ | |
| 3041 emit_opcode(cbuf, 0xD8); | |
| 3042 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3043 %} | |
| 3044 | |
| 3045 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3046 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3047 // Operand was loaded from memory into fp ST (stack top) |
| 3048 // FADD ST,$src /* D8 C0+i */ | |
| 3049 emit_opcode(cbuf, 0xD8); | |
| 3050 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3051 | |
| 3052 // FMULP src2,ST /* DE C8+i */ | |
| 3053 emit_opcode(cbuf, 0xDE); | |
| 3054 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3055 %} | |
| 3056 | |
| 3057 // Atomically load the volatile long | |
| 3058 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3059 emit_opcode(cbuf,0xDF); | |
| 3060 int rm_byte_opcode = 0x05; | |
| 3061 int base = $mem$$base; | |
| 3062 int index = $mem$$index; | |
| 3063 int scale = $mem$$scale; | |
| 3064 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3065 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3066 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3067 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3068 %} | |
| 3069 | |
| 3070 // Volatile Store Long. Must be atomic, so move it into | |
| 3071 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3072 // target address before the store (for null-ptr checks) | |
| 3073 // so the memory operand is used twice in the encoding. | |
| 3074 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3075 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3076 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3077 emit_opcode(cbuf,0xDF); |
| 3078 int rm_byte_opcode = 0x07; | |
| 3079 int base = $mem$$base; | |
| 3080 int index = $mem$$index; | |
| 3081 int scale = $mem$$scale; | |
| 3082 int displace = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3083 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
3084 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3085 %} |
| 3086 | |
| 3087 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3088 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3089 // in the process | |
| 3090 // We current use TESTL [spp],EDI | |
| 3091 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3092 | |
| 3093 enc_class Safepoint_Poll() %{ | |
| 1748 | 3094 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3095 emit_opcode(cbuf,0x85); |
| 3096 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3097 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3098 %} | |
| 3099 %} | |
| 3100 | |
| 3101 | |
| 3102 //----------FRAME-------------------------------------------------------------- | |
| 3103 // Definition of frame structure and management information. | |
| 3104 // | |
| 3105 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3106 // | (to get allocators register number | |
| 3107 // G Owned by | | v add OptoReg::stack0()) | |
| 3108 // r CALLER | | | |
| 3109 // o | +--------+ pad to even-align allocators stack-slot | |
| 3110 // w V | pad0 | numbers; owned by CALLER | |
| 3111 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3112 // h ^ | in | 5 | |
| 3113 // | | args | 4 Holes in incoming args owned by SELF | |
| 3114 // | | | | 3 | |
| 3115 // | | +--------+ | |
| 3116 // V | | old out| Empty on Intel, window on Sparc | |
| 3117 // | old |preserve| Must be even aligned. | |
| 3118 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3119 // | | in | 3 area for Intel ret address | |
| 3120 // Owned by |preserve| Empty on Sparc. | |
| 3121 // SELF +--------+ | |
| 3122 // | | pad2 | 2 pad to align old SP | |
| 3123 // | +--------+ 1 | |
| 3124 // | | locks | 0 | |
| 3125 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3126 // | | pad1 | 11 pad to align new SP | |
| 3127 // | +--------+ | |
| 3128 // | | | 10 | |
| 3129 // | | spills | 9 spills | |
| 3130 // V | | 8 (pad0 slot for callee) | |
| 3131 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3132 // ^ | out | 7 | |
| 3133 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3134 // Owned by +--------+ | |
| 3135 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3136 // | new |preserve| Must be even-aligned. | |
| 3137 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3138 // | | | | |
| 3139 // | |
| 3140 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3141 // known from SELF's arguments and the Java calling convention. | |
| 3142 // Region 6-7 is determined per call site. | |
| 3143 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3144 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3145 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3146 // incoming area, as the Java calling convention is completely under | |
| 3147 // the control of the AD file. Doubles can be sorted and packed to | |
| 3148 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3149 // varargs C calling conventions. | |
| 3150 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3151 // even aligned with pad0 as needed. | |
| 3152 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3153 // region 6-11 is even aligned; it may be padded out more so that | |
| 3154 // the region from SP to FP meets the minimum stack alignment. | |
| 3155 | |
| 3156 frame %{ | |
| 3157 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3158 stack_direction(TOWARDS_LOW); | |
| 3159 | |
| 3160 // These three registers define part of the calling convention | |
| 3161 // between compiled code and the interpreter. | |
| 3162 inline_cache_reg(EAX); // Inline Cache Register | |
| 3163 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3164 | |
| 3165 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3166 cisc_spilling_operand_name(indOffset32); | |
| 3167 | |
| 3168 // Number of stack slots consumed by locking an object | |
| 3169 sync_stack_slots(1); | |
| 3170 | |
| 3171 // Compiled code's Frame Pointer | |
| 3172 frame_pointer(ESP); | |
| 3173 // Interpreter stores its frame pointer in a register which is | |
| 3174 // stored to the stack by I2CAdaptors. | |
| 3175 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3176 interpreter_frame_pointer(EBP); | |
| 3177 | |
| 3178 // Stack alignment requirement | |
| 3179 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3180 stack_alignment(StackAlignmentInBytes); | |
| 3181 | |
| 3182 // Number of stack slots between incoming argument block and the start of | |
| 3183 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3184 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3185 // return address and one for rbp, (must save rbp) | |
| 3186 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3187 | |
| 3188 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3189 // for calls to C. Supports the var-args backing area for register parms. | |
| 3190 varargs_C_out_slots_killed(0); | |
| 3191 | |
| 3192 // The after-PROLOG location of the return address. Location of | |
| 3193 // return address specifies a type (REG or STACK) and a number | |
| 3194 // representing the register number (i.e. - use a register name) or | |
| 3195 // stack slot. | |
| 3196 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3197 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3198 return_addr(STACK - 1 + | |
| 4950 | 3199 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3200 Compile::current()->fixed_slots()), | |
| 3201 stack_alignment_in_slots())); | |
| 0 | 3202 |
| 3203 // Body of function which returns an integer array locating | |
| 3204 // arguments either in registers or in stack slots. Passed an array | |
| 3205 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3206 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3207 // arguments for a CALLEE. Incoming stack arguments are | |
| 3208 // automatically biased by the preserve_stack_slots field above. | |
| 3209 calling_convention %{ | |
| 3210 // No difference between ingoing/outgoing just pass false | |
| 3211 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3212 %} | |
| 3213 | |
| 3214 | |
| 3215 // Body of function which returns an integer array locating | |
| 3216 // arguments either in registers or in stack slots. Passed an array | |
| 3217 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3218 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3219 // arguments for a CALLEE. Incoming stack arguments are | |
| 3220 // automatically biased by the preserve_stack_slots field above. | |
| 3221 c_calling_convention %{ | |
| 3222 // This is obviously always outgoing | |
|
14416
6a936747b569
8024344: PPC64 (part 112): C argument in register AND stack slot.
goetz
parents:
10169
diff
changeset
|
3223 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3224 %} |
| 3225 | |
| 3226 // Location of C & interpreter return values | |
| 3227 c_return_value %{ | |
| 3228 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3229 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3230 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3231 |
| 3232 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3233 // that C functions return float and double results in XMM0. | |
| 3234 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3235 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3236 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3237 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3238 |
| 3239 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3240 %} | |
| 3241 | |
| 3242 // Location of return values | |
| 3243 return_value %{ | |
| 3244 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3245 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3246 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3247 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3248 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3249 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3250 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3251 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3252 %} | |
| 3253 | |
| 3254 %} | |
| 3255 | |
| 3256 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3257 //----------Operand Attributes------------------------------------------------- | |
| 3258 op_attrib op_cost(0); // Required cost attribute | |
| 3259 | |
| 3260 //----------Instruction Attributes--------------------------------------------- | |
| 3261 ins_attrib ins_cost(100); // Required cost attribute | |
| 3262 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3263 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3264 // non-matching short branch variant of some | |
| 3265 // long branch? | |
| 3266 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3267 // specifies the alignment that some part of the instruction (not | |
| 3268 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3269 // function must be provided for the instruction | |
| 3270 | |
| 3271 //----------OPERANDS----------------------------------------------------------- | |
| 3272 // Operand definitions must precede instruction definitions for correct parsing | |
| 3273 // in the ADLC because operands constitute user defined types which are used in | |
| 3274 // instruction definitions. | |
| 3275 | |
| 3276 //----------Simple Operands---------------------------------------------------- | |
| 3277 // Immediate Operands | |
| 3278 // Integer Immediate | |
| 3279 operand immI() %{ | |
| 3280 match(ConI); | |
| 3281 | |
| 3282 op_cost(10); | |
| 3283 format %{ %} | |
| 3284 interface(CONST_INTER); | |
| 3285 %} | |
| 3286 | |
| 3287 // Constant for test vs zero | |
| 3288 operand immI0() %{ | |
| 3289 predicate(n->get_int() == 0); | |
| 3290 match(ConI); | |
| 3291 | |
| 3292 op_cost(0); | |
| 3293 format %{ %} | |
| 3294 interface(CONST_INTER); | |
| 3295 %} | |
| 3296 | |
| 3297 // Constant for increment | |
| 3298 operand immI1() %{ | |
| 3299 predicate(n->get_int() == 1); | |
| 3300 match(ConI); | |
| 3301 | |
| 3302 op_cost(0); | |
| 3303 format %{ %} | |
| 3304 interface(CONST_INTER); | |
| 3305 %} | |
| 3306 | |
| 3307 // Constant for decrement | |
| 3308 operand immI_M1() %{ | |
| 3309 predicate(n->get_int() == -1); | |
| 3310 match(ConI); | |
| 3311 | |
| 3312 op_cost(0); | |
| 3313 format %{ %} | |
| 3314 interface(CONST_INTER); | |
| 3315 %} | |
| 3316 | |
| 3317 // Valid scale values for addressing modes | |
| 3318 operand immI2() %{ | |
| 3319 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3320 match(ConI); | |
| 3321 | |
| 3322 format %{ %} | |
| 3323 interface(CONST_INTER); | |
| 3324 %} | |
| 3325 | |
| 3326 operand immI8() %{ | |
| 3327 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3328 match(ConI); | |
| 3329 | |
| 3330 op_cost(5); | |
| 3331 format %{ %} | |
| 3332 interface(CONST_INTER); | |
| 3333 %} | |
| 3334 | |
| 3335 operand immI16() %{ | |
| 3336 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3337 match(ConI); | |
| 3338 | |
| 3339 op_cost(10); | |
| 3340 format %{ %} | |
| 3341 interface(CONST_INTER); | |
| 3342 %} | |
| 3343 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3344 // Int Immediate non-negative |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3345 operand immU31() |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3346 %{ |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3347 predicate(n->get_int() >= 0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3348 match(ConI); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3349 |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3350 op_cost(0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3351 format %{ %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3352 interface(CONST_INTER); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3353 %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
3354 |
| 0 | 3355 // Constant for long shifts |
| 3356 operand immI_32() %{ | |
| 3357 predicate( n->get_int() == 32 ); | |
| 3358 match(ConI); | |
| 3359 | |
| 3360 op_cost(0); | |
| 3361 format %{ %} | |
| 3362 interface(CONST_INTER); | |
| 3363 %} | |
| 3364 | |
| 3365 operand immI_1_31() %{ | |
| 3366 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3367 match(ConI); | |
| 3368 | |
| 3369 op_cost(0); | |
| 3370 format %{ %} | |
| 3371 interface(CONST_INTER); | |
| 3372 %} | |
| 3373 | |
| 3374 operand immI_32_63() %{ | |
| 3375 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3376 match(ConI); | |
| 3377 op_cost(0); | |
| 3378 | |
| 3379 format %{ %} | |
| 3380 interface(CONST_INTER); | |
| 3381 %} | |
| 3382 | |
| 219 | 3383 operand immI_1() %{ |
| 3384 predicate( n->get_int() == 1 ); | |
| 3385 match(ConI); | |
| 3386 | |
| 3387 op_cost(0); | |
| 3388 format %{ %} | |
| 3389 interface(CONST_INTER); | |
| 3390 %} | |
| 3391 | |
| 3392 operand immI_2() %{ | |
| 3393 predicate( n->get_int() == 2 ); | |
| 3394 match(ConI); | |
| 3395 | |
| 3396 op_cost(0); | |
| 3397 format %{ %} | |
| 3398 interface(CONST_INTER); | |
| 3399 %} | |
| 3400 | |
| 3401 operand immI_3() %{ | |
| 3402 predicate( n->get_int() == 3 ); | |
| 3403 match(ConI); | |
| 3404 | |
| 3405 op_cost(0); | |
| 3406 format %{ %} | |
| 3407 interface(CONST_INTER); | |
| 3408 %} | |
| 3409 | |
| 0 | 3410 // Pointer Immediate |
| 3411 operand immP() %{ | |
| 3412 match(ConP); | |
| 3413 | |
| 3414 op_cost(10); | |
| 3415 format %{ %} | |
| 3416 interface(CONST_INTER); | |
| 3417 %} | |
| 3418 | |
| 3419 // NULL Pointer Immediate | |
| 3420 operand immP0() %{ | |
| 3421 predicate( n->get_ptr() == 0 ); | |
| 3422 match(ConP); | |
| 3423 op_cost(0); | |
| 3424 | |
| 3425 format %{ %} | |
| 3426 interface(CONST_INTER); | |
| 3427 %} | |
| 3428 | |
| 3429 // Long Immediate | |
| 3430 operand immL() %{ | |
| 3431 match(ConL); | |
| 3432 | |
| 3433 op_cost(20); | |
| 3434 format %{ %} | |
| 3435 interface(CONST_INTER); | |
| 3436 %} | |
| 3437 | |
| 3438 // Long Immediate zero | |
| 3439 operand immL0() %{ | |
| 3440 predicate( n->get_long() == 0L ); | |
| 3441 match(ConL); | |
| 3442 op_cost(0); | |
| 3443 | |
| 3444 format %{ %} | |
| 3445 interface(CONST_INTER); | |
| 3446 %} | |
| 3447 | |
| 403 | 3448 // Long Immediate zero |
| 3449 operand immL_M1() %{ | |
| 3450 predicate( n->get_long() == -1L ); | |
| 3451 match(ConL); | |
| 3452 op_cost(0); | |
| 3453 | |
| 3454 format %{ %} | |
| 3455 interface(CONST_INTER); | |
| 3456 %} | |
| 3457 | |
| 0 | 3458 // Long immediate from 0 to 127. |
| 3459 // Used for a shorter form of long mul by 10. | |
| 3460 operand immL_127() %{ | |
| 3461 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3462 match(ConL); | |
| 3463 op_cost(0); | |
| 3464 | |
| 3465 format %{ %} | |
| 3466 interface(CONST_INTER); | |
| 3467 %} | |
| 3468 | |
| 3469 // Long Immediate: low 32-bit mask | |
| 3470 operand immL_32bits() %{ | |
| 3471 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3472 match(ConL); | |
| 3473 op_cost(0); | |
| 3474 | |
| 3475 format %{ %} | |
| 3476 interface(CONST_INTER); | |
| 3477 %} | |
| 3478 | |
| 3479 // Long Immediate: low 32-bit mask | |
| 3480 operand immL32() %{ | |
| 3481 predicate(n->get_long() == (int)(n->get_long())); | |
| 3482 match(ConL); | |
| 3483 op_cost(20); | |
| 3484 | |
| 3485 format %{ %} | |
| 3486 interface(CONST_INTER); | |
| 3487 %} | |
| 3488 | |
| 3489 //Double Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3490 operand immDPR0() %{ |
| 0 | 3491 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3492 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3493 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3494 match(ConD); | |
| 3495 | |
| 3496 op_cost(5); | |
| 3497 format %{ %} | |
| 3498 interface(CONST_INTER); | |
| 3499 %} | |
| 3500 | |
| 2008 | 3501 // Double Immediate one |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3502 operand immDPR1() %{ |
| 0 | 3503 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 3504 match(ConD); | |
| 3505 | |
| 3506 op_cost(5); | |
| 3507 format %{ %} | |
| 3508 interface(CONST_INTER); | |
| 3509 %} | |
| 3510 | |
| 3511 // Double Immediate | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3512 operand immDPR() %{ |
| 0 | 3513 predicate(UseSSE<=1); |
| 3514 match(ConD); | |
| 3515 | |
| 3516 op_cost(5); | |
| 3517 format %{ %} | |
| 3518 interface(CONST_INTER); | |
| 3519 %} | |
| 3520 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3521 operand immD() %{ |
| 0 | 3522 predicate(UseSSE>=2); |
| 3523 match(ConD); | |
| 3524 | |
| 3525 op_cost(5); | |
| 3526 format %{ %} | |
| 3527 interface(CONST_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 // Double Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3531 operand immD0() %{ |
| 0 | 3532 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3533 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 3534 // compare equal to -0.0. | |
| 3535 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 3536 match(ConD); | |
| 3537 | |
| 3538 format %{ %} | |
| 3539 interface(CONST_INTER); | |
| 3540 %} | |
| 3541 | |
| 3542 // Float Immediate zero | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3543 operand immFPR0() %{ |
| 2008 | 3544 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 3545 match(ConF); | |
| 3546 | |
| 3547 op_cost(5); | |
| 3548 format %{ %} | |
| 3549 interface(CONST_INTER); | |
| 3550 %} | |
| 3551 | |
| 3552 // Float Immediate one | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3553 operand immFPR1() %{ |
| 2008 | 3554 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 3555 match(ConF); |
| 3556 | |
| 3557 op_cost(5); | |
| 3558 format %{ %} | |
| 3559 interface(CONST_INTER); | |
| 3560 %} | |
| 3561 | |
| 3562 // Float Immediate | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3563 operand immFPR() %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3564 predicate( UseSSE == 0 ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3565 match(ConF); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3566 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3567 op_cost(5); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3568 format %{ %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3569 interface(CONST_INTER); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3570 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3571 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3572 // Float Immediate |
| 0 | 3573 operand immF() %{ |
| 3574 predicate(UseSSE >= 1); | |
| 3575 match(ConF); | |
| 3576 | |
| 3577 op_cost(5); | |
| 3578 format %{ %} | |
| 3579 interface(CONST_INTER); | |
| 3580 %} | |
| 3581 | |
| 3582 // Float Immediate zero. Zero and not -0.0 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3583 operand immF0() %{ |
| 0 | 3584 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 3585 match(ConF); | |
| 3586 | |
| 3587 op_cost(5); | |
| 3588 format %{ %} | |
| 3589 interface(CONST_INTER); | |
| 3590 %} | |
| 3591 | |
| 3592 // Immediates for special shifts (sign extend) | |
| 3593 | |
| 3594 // Constants for increment | |
| 3595 operand immI_16() %{ | |
| 3596 predicate( n->get_int() == 16 ); | |
| 3597 match(ConI); | |
| 3598 | |
| 3599 format %{ %} | |
| 3600 interface(CONST_INTER); | |
| 3601 %} | |
| 3602 | |
| 3603 operand immI_24() %{ | |
| 3604 predicate( n->get_int() == 24 ); | |
| 3605 match(ConI); | |
| 3606 | |
| 3607 format %{ %} | |
| 3608 interface(CONST_INTER); | |
| 3609 %} | |
| 3610 | |
| 3611 // Constant for byte-wide masking | |
| 3612 operand immI_255() %{ | |
| 3613 predicate( n->get_int() == 255 ); | |
| 3614 match(ConI); | |
| 3615 | |
| 3616 format %{ %} | |
| 3617 interface(CONST_INTER); | |
| 3618 %} | |
| 3619 | |
| 785 | 3620 // Constant for short-wide masking |
| 3621 operand immI_65535() %{ | |
| 3622 predicate(n->get_int() == 65535); | |
| 3623 match(ConI); | |
| 3624 | |
| 3625 format %{ %} | |
| 3626 interface(CONST_INTER); | |
| 3627 %} | |
| 3628 | |
| 0 | 3629 // Register Operands |
| 3630 // Integer Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3631 operand rRegI() %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3632 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3633 match(RegI); |
| 3634 match(xRegI); | |
| 3635 match(eAXRegI); | |
| 3636 match(eBXRegI); | |
| 3637 match(eCXRegI); | |
| 3638 match(eDXRegI); | |
| 3639 match(eDIRegI); | |
| 3640 match(eSIRegI); | |
| 3641 | |
| 3642 format %{ %} | |
| 3643 interface(REG_INTER); | |
| 3644 %} | |
| 3645 | |
| 3646 // Subset of Integer Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3647 operand xRegI(rRegI reg) %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3648 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 3649 match(reg); |
| 3650 match(eAXRegI); | |
| 3651 match(eBXRegI); | |
| 3652 match(eCXRegI); | |
| 3653 match(eDXRegI); | |
| 3654 | |
| 3655 format %{ %} | |
| 3656 interface(REG_INTER); | |
| 3657 %} | |
| 3658 | |
| 3659 // Special Registers | |
| 3660 operand eAXRegI(xRegI reg) %{ | |
| 3661 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3662 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3663 match(rRegI); |
| 0 | 3664 |
| 3665 format %{ "EAX" %} | |
| 3666 interface(REG_INTER); | |
| 3667 %} | |
| 3668 | |
| 3669 // Special Registers | |
| 3670 operand eBXRegI(xRegI reg) %{ | |
| 3671 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3672 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3673 match(rRegI); |
| 0 | 3674 |
| 3675 format %{ "EBX" %} | |
| 3676 interface(REG_INTER); | |
| 3677 %} | |
| 3678 | |
| 3679 operand eCXRegI(xRegI reg) %{ | |
| 3680 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3681 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3682 match(rRegI); |
| 0 | 3683 |
| 3684 format %{ "ECX" %} | |
| 3685 interface(REG_INTER); | |
| 3686 %} | |
| 3687 | |
| 3688 operand eDXRegI(xRegI reg) %{ | |
| 3689 constraint(ALLOC_IN_RC(edx_reg)); | |
| 3690 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3691 match(rRegI); |
| 0 | 3692 |
| 3693 format %{ "EDX" %} | |
| 3694 interface(REG_INTER); | |
| 3695 %} | |
| 3696 | |
| 3697 operand eDIRegI(xRegI reg) %{ | |
| 3698 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3699 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3700 match(rRegI); |
| 0 | 3701 |
| 3702 format %{ "EDI" %} | |
| 3703 interface(REG_INTER); | |
| 3704 %} | |
| 3705 | |
| 3706 operand naxRegI() %{ | |
| 3707 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3708 match(RegI); | |
| 3709 match(eCXRegI); | |
| 3710 match(eDXRegI); | |
| 3711 match(eSIRegI); | |
| 3712 match(eDIRegI); | |
| 3713 | |
| 3714 format %{ %} | |
| 3715 interface(REG_INTER); | |
| 3716 %} | |
| 3717 | |
| 3718 operand nadxRegI() %{ | |
| 3719 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 3720 match(RegI); | |
| 3721 match(eBXRegI); | |
| 3722 match(eCXRegI); | |
| 3723 match(eSIRegI); | |
| 3724 match(eDIRegI); | |
| 3725 | |
| 3726 format %{ %} | |
| 3727 interface(REG_INTER); | |
| 3728 %} | |
| 3729 | |
| 3730 operand ncxRegI() %{ | |
| 3731 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 3732 match(RegI); | |
| 3733 match(eAXRegI); | |
| 3734 match(eDXRegI); | |
| 3735 match(eSIRegI); | |
| 3736 match(eDIRegI); | |
| 3737 | |
| 3738 format %{ %} | |
| 3739 interface(REG_INTER); | |
| 3740 %} | |
| 3741 | |
| 3742 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 3743 // // | |
| 3744 operand eSIRegI(xRegI reg) %{ | |
| 3745 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3746 match(reg); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3747 match(rRegI); |
| 0 | 3748 |
| 3749 format %{ "ESI" %} | |
| 3750 interface(REG_INTER); | |
| 3751 %} | |
| 3752 | |
| 3753 // Pointer Register | |
| 3754 operand anyRegP() %{ | |
| 3755 constraint(ALLOC_IN_RC(any_reg)); | |
| 3756 match(RegP); | |
| 3757 match(eAXRegP); | |
| 3758 match(eBXRegP); | |
| 3759 match(eCXRegP); | |
| 3760 match(eDIRegP); | |
| 3761 match(eRegP); | |
| 3762 | |
| 3763 format %{ %} | |
| 3764 interface(REG_INTER); | |
| 3765 %} | |
| 3766 | |
| 3767 operand eRegP() %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3768 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3769 match(RegP); |
| 3770 match(eAXRegP); | |
| 3771 match(eBXRegP); | |
| 3772 match(eCXRegP); | |
| 3773 match(eDIRegP); | |
| 3774 | |
| 3775 format %{ %} | |
| 3776 interface(REG_INTER); | |
| 3777 %} | |
| 3778 | |
| 3779 // On windows95, EBP is not safe to use for implicit null tests. | |
| 3780 operand eRegP_no_EBP() %{ | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
17980
diff
changeset
|
3781 constraint(ALLOC_IN_RC(int_reg_no_ebp)); |
| 0 | 3782 match(RegP); |
| 3783 match(eAXRegP); | |
| 3784 match(eBXRegP); | |
| 3785 match(eCXRegP); | |
| 3786 match(eDIRegP); | |
| 3787 | |
| 3788 op_cost(100); | |
| 3789 format %{ %} | |
| 3790 interface(REG_INTER); | |
| 3791 %} | |
| 3792 | |
| 3793 operand naxRegP() %{ | |
| 3794 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3795 match(RegP); | |
| 3796 match(eBXRegP); | |
| 3797 match(eDXRegP); | |
| 3798 match(eCXRegP); | |
| 3799 match(eSIRegP); | |
| 3800 match(eDIRegP); | |
| 3801 | |
| 3802 format %{ %} | |
| 3803 interface(REG_INTER); | |
| 3804 %} | |
| 3805 | |
| 3806 operand nabxRegP() %{ | |
| 3807 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 3808 match(RegP); | |
| 3809 match(eCXRegP); | |
| 3810 match(eDXRegP); | |
| 3811 match(eSIRegP); | |
| 3812 match(eDIRegP); | |
| 3813 | |
| 3814 format %{ %} | |
| 3815 interface(REG_INTER); | |
| 3816 %} | |
| 3817 | |
| 3818 operand pRegP() %{ | |
| 3819 constraint(ALLOC_IN_RC(p_reg)); | |
| 3820 match(RegP); | |
| 3821 match(eBXRegP); | |
| 3822 match(eDXRegP); | |
| 3823 match(eSIRegP); | |
| 3824 match(eDIRegP); | |
| 3825 | |
| 3826 format %{ %} | |
| 3827 interface(REG_INTER); | |
| 3828 %} | |
| 3829 | |
| 3830 // Special Registers | |
| 3831 // Return a pointer value | |
| 3832 operand eAXRegP(eRegP reg) %{ | |
| 3833 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3834 match(reg); | |
| 3835 format %{ "EAX" %} | |
| 3836 interface(REG_INTER); | |
| 3837 %} | |
| 3838 | |
| 3839 // Used in AtomicAdd | |
| 3840 operand eBXRegP(eRegP reg) %{ | |
| 3841 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3842 match(reg); | |
| 3843 format %{ "EBX" %} | |
| 3844 interface(REG_INTER); | |
| 3845 %} | |
| 3846 | |
| 3847 // Tail-call (interprocedural jump) to interpreter | |
| 3848 operand eCXRegP(eRegP reg) %{ | |
| 3849 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3850 match(reg); | |
| 3851 format %{ "ECX" %} | |
| 3852 interface(REG_INTER); | |
| 3853 %} | |
| 3854 | |
| 3855 operand eSIRegP(eRegP reg) %{ | |
| 3856 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3857 match(reg); | |
| 3858 format %{ "ESI" %} | |
| 3859 interface(REG_INTER); | |
| 3860 %} | |
| 3861 | |
| 3862 // Used in rep stosw | |
| 3863 operand eDIRegP(eRegP reg) %{ | |
| 3864 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3865 match(reg); | |
| 3866 format %{ "EDI" %} | |
| 3867 interface(REG_INTER); | |
| 3868 %} | |
| 3869 | |
| 3870 operand eRegL() %{ | |
| 3871 constraint(ALLOC_IN_RC(long_reg)); | |
| 3872 match(RegL); | |
| 3873 match(eADXRegL); | |
| 3874 | |
| 3875 format %{ %} | |
| 3876 interface(REG_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 operand eADXRegL( eRegL reg ) %{ | |
| 3880 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3881 match(reg); | |
| 3882 | |
| 3883 format %{ "EDX:EAX" %} | |
| 3884 interface(REG_INTER); | |
| 3885 %} | |
| 3886 | |
| 3887 operand eBCXRegL( eRegL reg ) %{ | |
| 3888 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 3889 match(reg); | |
| 3890 | |
| 3891 format %{ "EBX:ECX" %} | |
| 3892 interface(REG_INTER); | |
| 3893 %} | |
| 3894 | |
| 3895 // Special case for integer high multiply | |
| 3896 operand eADXRegL_low_only() %{ | |
| 3897 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3898 match(RegL); | |
| 3899 | |
| 3900 format %{ "EAX" %} | |
| 3901 interface(REG_INTER); | |
| 3902 %} | |
| 3903 | |
| 3904 // Flags register, used as output of compare instructions | |
| 3905 operand eFlagsReg() %{ | |
| 3906 constraint(ALLOC_IN_RC(int_flags)); | |
| 3907 match(RegFlags); | |
| 3908 | |
| 3909 format %{ "EFLAGS" %} | |
| 3910 interface(REG_INTER); | |
| 3911 %} | |
| 3912 | |
| 3913 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3914 operand eFlagsRegU() %{ | |
| 3915 constraint(ALLOC_IN_RC(int_flags)); | |
| 3916 match(RegFlags); | |
| 3917 | |
| 3918 format %{ "EFLAGS_U" %} | |
| 3919 interface(REG_INTER); | |
| 3920 %} | |
| 3921 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3922 operand eFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3923 constraint(ALLOC_IN_RC(int_flags)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3924 match(RegFlags); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3925 predicate(false); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3926 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3927 format %{ "EFLAGS_U_CF" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3928 interface(REG_INTER); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3929 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3930 |
| 0 | 3931 // Condition Code Register used by long compare |
| 3932 operand flagsReg_long_LTGE() %{ | |
| 3933 constraint(ALLOC_IN_RC(int_flags)); | |
| 3934 match(RegFlags); | |
| 3935 format %{ "FLAGS_LTGE" %} | |
| 3936 interface(REG_INTER); | |
| 3937 %} | |
| 3938 operand flagsReg_long_EQNE() %{ | |
| 3939 constraint(ALLOC_IN_RC(int_flags)); | |
| 3940 match(RegFlags); | |
| 3941 format %{ "FLAGS_EQNE" %} | |
| 3942 interface(REG_INTER); | |
| 3943 %} | |
| 3944 operand flagsReg_long_LEGT() %{ | |
| 3945 constraint(ALLOC_IN_RC(int_flags)); | |
| 3946 match(RegFlags); | |
| 3947 format %{ "FLAGS_LEGT" %} | |
| 3948 interface(REG_INTER); | |
| 3949 %} | |
| 3950 | |
| 24206 | 3951 // Condition Code Register used by unsigned long compare |
| 3952 operand flagsReg_ulong_LTGE() %{ | |
| 3953 constraint(ALLOC_IN_RC(int_flags)); | |
| 3954 match(RegFlags); | |
| 3955 format %{ "FLAGS_U_LTGE" %} | |
| 3956 interface(REG_INTER); | |
| 3957 %} | |
| 3958 operand flagsReg_ulong_EQNE() %{ | |
| 3959 constraint(ALLOC_IN_RC(int_flags)); | |
| 3960 match(RegFlags); | |
| 3961 format %{ "FLAGS_U_EQNE" %} | |
| 3962 interface(REG_INTER); | |
| 3963 %} | |
| 3964 operand flagsReg_ulong_LEGT() %{ | |
| 3965 constraint(ALLOC_IN_RC(int_flags)); | |
| 3966 match(RegFlags); | |
| 3967 format %{ "FLAGS_U_LEGT" %} | |
| 3968 interface(REG_INTER); | |
| 3969 %} | |
| 3970 | |
| 0 | 3971 // Float register operands |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3972 operand regDPR() %{ |
| 0 | 3973 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3974 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 3975 match(RegD); |
| 3976 match(regDPR1); | |
| 3977 match(regDPR2); | |
| 3978 format %{ %} | |
| 3979 interface(REG_INTER); | |
| 3980 %} | |
| 3981 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3982 operand regDPR1(regDPR reg) %{ |
| 0 | 3983 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3984 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 3985 match(reg); |
| 3986 format %{ "FPR1" %} | |
| 3987 interface(REG_INTER); | |
| 3988 %} | |
| 3989 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3990 operand regDPR2(regDPR reg) %{ |
| 0 | 3991 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
3992 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 3993 match(reg); |
| 3994 format %{ "FPR2" %} | |
| 3995 interface(REG_INTER); | |
| 3996 %} | |
| 3997 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3998 operand regnotDPR1(regDPR reg) %{ |
| 0 | 3999 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4000 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 4001 match(reg); |
| 4002 format %{ %} | |
| 4003 interface(REG_INTER); | |
| 4004 %} | |
| 4005 | |
| 4006 // Float register operands | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4007 operand regFPR() %{ |
| 0 | 4008 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4009 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 4010 match(RegF); |
| 4011 match(regFPR1); | |
| 4012 format %{ %} | |
| 4013 interface(REG_INTER); | |
| 4014 %} | |
| 4015 | |
| 4016 // Float register operands | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4017 operand regFPR1(regFPR reg) %{ |
| 0 | 4018 predicate( UseSSE < 2 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4019 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 4020 match(reg); |
| 4021 format %{ "FPR1" %} | |
| 4022 interface(REG_INTER); | |
| 4023 %} | |
| 4024 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4025 // XMM Float register operands |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4026 operand regF() %{ |
| 0 | 4027 predicate( UseSSE>=1 ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4028 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4029 match(RegF); |
| 4030 format %{ %} | |
| 4031 interface(REG_INTER); | |
| 4032 %} | |
| 4033 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4034 // XMM Double register operands |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4035 operand regD() %{ |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4036 predicate( UseSSE>=2 ); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4037 constraint(ALLOC_IN_RC(double_reg)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4038 match(RegD); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4039 format %{ %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4040 interface(REG_INTER); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4041 %} |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4042 |
| 0 | 4043 |
| 4044 //----------Memory Operands---------------------------------------------------- | |
| 4045 // Direct Memory Operand | |
| 4046 operand direct(immP addr) %{ | |
| 4047 match(addr); | |
| 4048 | |
| 4049 format %{ "[$addr]" %} | |
| 4050 interface(MEMORY_INTER) %{ | |
| 4051 base(0xFFFFFFFF); | |
| 4052 index(0x4); | |
| 4053 scale(0x0); | |
| 4054 disp($addr); | |
| 4055 %} | |
| 4056 %} | |
| 4057 | |
| 4058 // Indirect Memory Operand | |
| 4059 operand indirect(eRegP reg) %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4060 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4061 match(reg); |
| 4062 | |
| 4063 format %{ "[$reg]" %} | |
| 4064 interface(MEMORY_INTER) %{ | |
| 4065 base($reg); | |
| 4066 index(0x4); | |
| 4067 scale(0x0); | |
| 4068 disp(0x0); | |
| 4069 %} | |
| 4070 %} | |
| 4071 | |
| 4072 // Indirect Memory Plus Short Offset Operand | |
| 4073 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4074 match(AddP reg off); | |
| 4075 | |
| 4076 format %{ "[$reg + $off]" %} | |
| 4077 interface(MEMORY_INTER) %{ | |
| 4078 base($reg); | |
| 4079 index(0x4); | |
| 4080 scale(0x0); | |
| 4081 disp($off); | |
| 4082 %} | |
| 4083 %} | |
| 4084 | |
| 4085 // Indirect Memory Plus Long Offset Operand | |
| 4086 operand indOffset32(eRegP reg, immI off) %{ | |
| 4087 match(AddP reg off); | |
| 4088 | |
| 4089 format %{ "[$reg + $off]" %} | |
| 4090 interface(MEMORY_INTER) %{ | |
| 4091 base($reg); | |
| 4092 index(0x4); | |
| 4093 scale(0x0); | |
| 4094 disp($off); | |
| 4095 %} | |
| 4096 %} | |
| 4097 | |
| 4098 // Indirect Memory Plus Long Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4099 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4100 match(AddP off reg); |
| 4101 | |
| 4102 format %{ "[$reg + $off]" %} | |
| 4103 interface(MEMORY_INTER) %{ | |
| 4104 base($reg); | |
| 4105 index(0x4); | |
| 4106 scale(0x0); | |
| 4107 disp($off); | |
| 4108 %} | |
| 4109 %} | |
| 4110 | |
| 4111 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4112 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4113 match(AddP (AddP reg ireg) off); |
| 4114 | |
| 4115 op_cost(10); | |
| 4116 format %{"[$reg + $off + $ireg]" %} | |
| 4117 interface(MEMORY_INTER) %{ | |
| 4118 base($reg); | |
| 4119 index($ireg); | |
| 4120 scale(0x0); | |
| 4121 disp($off); | |
| 4122 %} | |
| 4123 %} | |
| 4124 | |
| 4125 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4126 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4127 match(AddP reg ireg); |
| 4128 | |
| 4129 op_cost(10); | |
| 4130 format %{"[$reg + $ireg]" %} | |
| 4131 interface(MEMORY_INTER) %{ | |
| 4132 base($reg); | |
| 4133 index($ireg); | |
| 4134 scale(0x0); | |
| 4135 disp(0x0); | |
| 4136 %} | |
| 4137 %} | |
| 4138 | |
| 4139 // // ------------------------------------------------------------------------- | |
| 4140 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4141 // // ------------------------------------------------------------------------- | |
| 4142 // // Scaled Memory Operands | |
| 4143 // // Indirect Memory Times Scale Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4144 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4145 // match(AddP off (LShiftI ireg scale)); |
| 4146 // | |
| 4147 // op_cost(10); | |
| 4148 // format %{"[$off + $ireg << $scale]" %} | |
| 4149 // interface(MEMORY_INTER) %{ | |
| 4150 // base(0x4); | |
| 4151 // index($ireg); | |
| 4152 // scale($scale); | |
| 4153 // disp($off); | |
| 4154 // %} | |
| 4155 // %} | |
| 4156 | |
| 4157 // Indirect Memory Times Scale Plus Index Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4158 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4159 match(AddP reg (LShiftI ireg scale)); |
| 4160 | |
| 4161 op_cost(10); | |
| 4162 format %{"[$reg + $ireg << $scale]" %} | |
| 4163 interface(MEMORY_INTER) %{ | |
| 4164 base($reg); | |
| 4165 index($ireg); | |
| 4166 scale($scale); | |
| 4167 disp(0x0); | |
| 4168 %} | |
| 4169 %} | |
| 4170 | |
| 4171 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4172 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4173 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4174 | |
| 4175 op_cost(10); | |
| 4176 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4177 interface(MEMORY_INTER) %{ | |
| 4178 base($reg); | |
| 4179 index($ireg); | |
| 4180 scale($scale); | |
| 4181 disp($off); | |
| 4182 %} | |
| 4183 %} | |
| 4184 | |
| 4185 //----------Load Long Memory Operands------------------------------------------ | |
| 4186 // The load-long idiom will use it's address expression again after loading | |
| 4187 // the first word of the long. If the load-long destination overlaps with | |
| 4188 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4189 // from a clobbered address. Fix this by requiring that load-long use | |
| 4190 // address registers that do not overlap with the load-long target. | |
| 4191 | |
| 4192 // load-long support | |
| 4193 operand load_long_RegP() %{ | |
| 4194 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4195 match(RegP); | |
| 4196 match(eSIRegP); | |
| 4197 op_cost(100); | |
| 4198 format %{ %} | |
| 4199 interface(REG_INTER); | |
| 4200 %} | |
| 4201 | |
| 4202 // Indirect Memory Operand Long | |
| 4203 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4204 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4205 match(reg); | |
| 4206 | |
| 4207 format %{ "[$reg]" %} | |
| 4208 interface(MEMORY_INTER) %{ | |
| 4209 base($reg); | |
| 4210 index(0x4); | |
| 4211 scale(0x0); | |
| 4212 disp(0x0); | |
| 4213 %} | |
| 4214 %} | |
| 4215 | |
| 4216 // Indirect Memory Plus Long Offset Operand | |
| 4217 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4218 match(AddP reg off); | |
| 4219 | |
| 4220 format %{ "[$reg + $off]" %} | |
| 4221 interface(MEMORY_INTER) %{ | |
| 4222 base($reg); | |
| 4223 index(0x4); | |
| 4224 scale(0x0); | |
| 4225 disp($off); | |
| 4226 %} | |
| 4227 %} | |
| 4228 | |
| 4229 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4230 | |
| 4231 | |
| 4232 //----------Special Memory Operands-------------------------------------------- | |
| 4233 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4234 // values on the stack where a match requires a value to | |
| 4235 // flow through memory. | |
| 4236 operand stackSlotP(sRegP reg) %{ | |
| 4237 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4238 // No match rule because this operand is only generated in matching | |
| 4239 format %{ "[$reg]" %} | |
| 4240 interface(MEMORY_INTER) %{ | |
| 4241 base(0x4); // ESP | |
| 4242 index(0x4); // No Index | |
| 4243 scale(0x0); // No Scale | |
| 4244 disp($reg); // Stack Offset | |
| 4245 %} | |
| 4246 %} | |
| 4247 | |
| 4248 operand stackSlotI(sRegI reg) %{ | |
| 4249 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4250 // No match rule because this operand is only generated in matching | |
| 4251 format %{ "[$reg]" %} | |
| 4252 interface(MEMORY_INTER) %{ | |
| 4253 base(0x4); // ESP | |
| 4254 index(0x4); // No Index | |
| 4255 scale(0x0); // No Scale | |
| 4256 disp($reg); // Stack Offset | |
| 4257 %} | |
| 4258 %} | |
| 4259 | |
| 4260 operand stackSlotF(sRegF reg) %{ | |
| 4261 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4262 // No match rule because this operand is only generated in matching | |
| 4263 format %{ "[$reg]" %} | |
| 4264 interface(MEMORY_INTER) %{ | |
| 4265 base(0x4); // ESP | |
| 4266 index(0x4); // No Index | |
| 4267 scale(0x0); // No Scale | |
| 4268 disp($reg); // Stack Offset | |
| 4269 %} | |
| 4270 %} | |
| 4271 | |
| 4272 operand stackSlotD(sRegD reg) %{ | |
| 4273 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4274 // No match rule because this operand is only generated in matching | |
| 4275 format %{ "[$reg]" %} | |
| 4276 interface(MEMORY_INTER) %{ | |
| 4277 base(0x4); // ESP | |
| 4278 index(0x4); // No Index | |
| 4279 scale(0x0); // No Scale | |
| 4280 disp($reg); // Stack Offset | |
| 4281 %} | |
| 4282 %} | |
| 4283 | |
| 4284 operand stackSlotL(sRegL reg) %{ | |
| 4285 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4286 // No match rule because this operand is only generated in matching | |
| 4287 format %{ "[$reg]" %} | |
| 4288 interface(MEMORY_INTER) %{ | |
| 4289 base(0x4); // ESP | |
| 4290 index(0x4); // No Index | |
| 4291 scale(0x0); // No Scale | |
| 4292 disp($reg); // Stack Offset | |
| 4293 %} | |
| 4294 %} | |
| 4295 | |
| 4296 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4297 // Indirect Memory Operand | |
| 4298 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4299 %{ | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4300 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4301 match(reg); |
| 4302 | |
| 4303 op_cost(100); | |
| 4304 format %{ "[$reg]" %} | |
| 4305 interface(MEMORY_INTER) %{ | |
| 4306 base($reg); | |
| 4307 index(0x4); | |
| 4308 scale(0x0); | |
| 4309 disp(0x0); | |
| 4310 %} | |
| 4311 %} | |
| 4312 | |
| 4313 // Indirect Memory Plus Short Offset Operand | |
| 4314 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4315 %{ | |
| 4316 match(AddP reg off); | |
| 4317 | |
| 4318 op_cost(100); | |
| 4319 format %{ "[$reg + $off]" %} | |
| 4320 interface(MEMORY_INTER) %{ | |
| 4321 base($reg); | |
| 4322 index(0x4); | |
| 4323 scale(0x0); | |
| 4324 disp($off); | |
| 4325 %} | |
| 4326 %} | |
| 4327 | |
| 4328 // Indirect Memory Plus Long Offset Operand | |
| 4329 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4330 %{ | |
| 4331 match(AddP reg off); | |
| 4332 | |
| 4333 op_cost(100); | |
| 4334 format %{ "[$reg + $off]" %} | |
| 4335 interface(MEMORY_INTER) %{ | |
| 4336 base($reg); | |
| 4337 index(0x4); | |
| 4338 scale(0x0); | |
| 4339 disp($off); | |
| 4340 %} | |
| 4341 %} | |
| 4342 | |
| 4343 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4344 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4345 %{ |
| 4346 match(AddP (AddP reg ireg) off); | |
| 4347 | |
| 4348 op_cost(100); | |
| 4349 format %{"[$reg + $off + $ireg]" %} | |
| 4350 interface(MEMORY_INTER) %{ | |
| 4351 base($reg); | |
| 4352 index($ireg); | |
| 4353 scale(0x0); | |
| 4354 disp($off); | |
| 4355 %} | |
| 4356 %} | |
| 4357 | |
| 4358 // Indirect Memory Times Scale Plus Index Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4359 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4360 %{ |
| 4361 match(AddP reg (LShiftI ireg scale)); | |
| 4362 | |
| 4363 op_cost(100); | |
| 4364 format %{"[$reg + $ireg << $scale]" %} | |
| 4365 interface(MEMORY_INTER) %{ | |
| 4366 base($reg); | |
| 4367 index($ireg); | |
| 4368 scale($scale); | |
| 4369 disp(0x0); | |
| 4370 %} | |
| 4371 %} | |
| 4372 | |
| 4373 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4374 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4375 %{ |
| 4376 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4377 | |
| 4378 op_cost(100); | |
| 4379 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4380 interface(MEMORY_INTER) %{ | |
| 4381 base($reg); | |
| 4382 index($ireg); | |
| 4383 scale($scale); | |
| 4384 disp($off); | |
| 4385 %} | |
| 4386 %} | |
| 4387 | |
| 4388 //----------Conditional Branch Operands---------------------------------------- | |
| 4389 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4390 // the following set of codes: | |
| 4391 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4392 // | |
| 4393 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4394 // by the comparison instruction that sets a condition code flags register. | |
| 4395 // That result is represented by a flags operand whose subtype is appropriate | |
| 4396 // to the unsignedness (etc.) of the comparison. | |
| 4397 // | |
| 4398 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4399 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4400 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4401 | |
| 4402 // Comparision Code | |
| 4403 operand cmpOp() %{ | |
| 4404 match(Bool); | |
| 4405 | |
| 4406 format %{ "" %} | |
| 4407 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4408 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4409 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4410 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4411 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4412 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4413 greater(0xF, "g"); |
| 12323 | 4414 overflow(0x0, "o"); |
| 4415 no_overflow(0x1, "no"); | |
| 0 | 4416 %} |
| 4417 %} | |
| 4418 | |
| 4419 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4420 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4421 // C0 and C3 are turned into Carry & Zero flags. | |
| 4422 operand cmpOpU() %{ | |
| 4423 match(Bool); | |
| 4424 | |
| 4425 format %{ "" %} | |
| 4426 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4427 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4428 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4429 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4430 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4431 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4432 greater(0x7, "nbe"); |
| 12323 | 4433 overflow(0x0, "o"); |
| 4434 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4435 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4436 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4437 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4438 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4439 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4440 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4441 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4442 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4443 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4444 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4445 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4446 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4447 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4448 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4449 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4450 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4451 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4452 greater(0x7, "nbe"); |
| 12323 | 4453 overflow(0x0, "o"); |
| 4454 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4455 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4456 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4457 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4458 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4459 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4460 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4461 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4462 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4463 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4464 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4465 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4466 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4467 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4468 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4469 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4470 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4471 greater(0x7, "nbe"); |
| 12323 | 4472 overflow(0x0, "o"); |
| 4473 no_overflow(0x1, "no"); | |
| 0 | 4474 %} |
| 4475 %} | |
| 4476 | |
| 4477 // Comparison Code for FP conditional move | |
| 4478 operand cmpOp_fcmov() %{ | |
| 4479 match(Bool); | |
| 4480 | |
| 12323 | 4481 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4482 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4483 format %{ "" %} |
| 4484 interface(COND_INTER) %{ | |
| 4485 equal (0x0C8); | |
| 4486 not_equal (0x1C8); | |
| 4487 less (0x0C0); | |
| 4488 greater_equal(0x1C0); | |
| 4489 less_equal (0x0D0); | |
| 4490 greater (0x1D0); | |
| 12323 | 4491 overflow(0x0, "o"); // not really supported by the instruction |
| 4492 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4493 %} |
| 4494 %} | |
| 4495 | |
| 24206 | 4496 // Comparison Code used in long compares |
| 0 | 4497 operand cmpOp_commute() %{ |
| 4498 match(Bool); | |
| 4499 | |
| 4500 format %{ "" %} | |
| 4501 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4502 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4503 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4504 less(0xF, "g"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4505 greater_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4506 less_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4507 greater(0xC, "l"); |
| 12323 | 4508 overflow(0x0, "o"); |
| 4509 no_overflow(0x1, "no"); | |
| 0 | 4510 %} |
| 4511 %} | |
| 4512 | |
| 24206 | 4513 // Comparison Code used in unsigned long compares |
| 4514 operand cmpOpU_commute() %{ | |
| 4515 match(Bool); | |
| 4516 | |
| 4517 format %{ "" %} | |
| 4518 interface(COND_INTER) %{ | |
| 4519 equal(0x4, "e"); | |
| 4520 not_equal(0x5, "ne"); | |
| 4521 less(0x7, "nbe"); | |
| 4522 greater_equal(0x6, "be"); | |
| 4523 less_equal(0x3, "nb"); | |
| 4524 greater(0x2, "b"); | |
| 4525 overflow(0x0, "o"); | |
| 4526 no_overflow(0x1, "no"); | |
| 4527 %} | |
| 4528 %} | |
| 4529 | |
| 0 | 4530 //----------OPERAND CLASSES---------------------------------------------------- |
| 4531 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4532 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4533 // instructions for every form of operand when the instruction accepts |
| 4534 // multiple operand types with the same basic encoding and format. The classic | |
| 4535 // case of this is memory operands. | |
| 4536 | |
| 4537 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 4538 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4539 | |
| 4540 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 4541 // This means some kind of offset is always required and you cannot use | |
| 4542 // an oop as the offset (done when working on static globals). | |
| 4543 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 4544 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4545 | |
| 4546 | |
| 4547 //----------PIPELINE----------------------------------------------------------- | |
| 4548 // Rules which define the behavior of the target architectures pipeline. | |
| 4549 pipeline %{ | |
| 4550 | |
| 4551 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4552 attributes %{ | |
| 4553 variable_size_instructions; // Fixed size instructions | |
| 4554 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4555 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4556 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4557 instruction_fetch_units = 1; // of 16 bytes | |
| 4558 | |
| 4559 // List of nop instructions | |
| 4560 nops( MachNop ); | |
| 4561 %} | |
| 4562 | |
| 4563 //----------RESOURCES---------------------------------------------------------- | |
| 4564 // Resources are the functional units available to the machine | |
| 4565 | |
| 4566 // Generic P2/P3 pipeline | |
| 4567 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4568 // 3 instructions decoded per cycle. | |
| 4569 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4570 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 4571 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4572 MS0, MS1, MEM = MS0 | MS1, | |
| 4573 BR, FPU, | |
| 4574 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 4575 | |
| 4576 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4577 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4578 | |
| 4579 // Generic P2/P3 pipeline | |
| 4580 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4581 | |
| 4582 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4583 // Pipeline Classes describe the stages in which input and output are | |
| 4584 // referenced by the hardware pipeline. | |
| 4585 | |
| 4586 // Naming convention: ialu or fpu | |
| 4587 // Then: _reg | |
| 4588 // Then: _reg if there is a 2nd register | |
| 4589 // Then: _long if it's a pair of instructions implementing a long | |
| 4590 // Then: _fat if it requires the big decoder | |
| 4591 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4592 | |
| 4593 // Integer ALU reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4594 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 4595 single_instruction; |
| 4596 dst : S4(write); | |
| 4597 dst : S3(read); | |
| 4598 DECODE : S0; // any decoder | |
| 4599 ALU : S3; // any alu | |
| 4600 %} | |
| 4601 | |
| 4602 // Long ALU reg operation | |
| 4603 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 4604 instruction_count(2); | |
| 4605 dst : S4(write); | |
| 4606 dst : S3(read); | |
| 4607 DECODE : S0(2); // any 2 decoders | |
| 4608 ALU : S3(2); // both alus | |
| 4609 %} | |
| 4610 | |
| 4611 // Integer ALU reg operation using big decoder | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4612 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 4613 single_instruction; |
| 4614 dst : S4(write); | |
| 4615 dst : S3(read); | |
| 4616 D0 : S0; // big decoder only | |
| 4617 ALU : S3; // any alu | |
| 4618 %} | |
| 4619 | |
| 4620 // Long ALU reg operation using big decoder | |
| 4621 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 4622 instruction_count(2); | |
| 4623 dst : S4(write); | |
| 4624 dst : S3(read); | |
| 4625 D0 : S0(2); // big decoder only; twice | |
| 4626 ALU : S3(2); // any 2 alus | |
| 4627 %} | |
| 4628 | |
| 4629 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4630 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 4631 single_instruction; |
| 4632 dst : S4(write); | |
| 4633 src : S3(read); | |
| 4634 DECODE : S0; // any decoder | |
| 4635 ALU : S3; // any alu | |
| 4636 %} | |
| 4637 | |
| 4638 // Long ALU reg-reg operation | |
| 4639 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 4640 instruction_count(2); | |
| 4641 dst : S4(write); | |
| 4642 src : S3(read); | |
| 4643 DECODE : S0(2); // any 2 decoders | |
| 4644 ALU : S3(2); // both alus | |
| 4645 %} | |
| 4646 | |
| 4647 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4648 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 4649 single_instruction; |
| 4650 dst : S4(write); | |
| 4651 src : S3(read); | |
| 4652 D0 : S0; // big decoder only | |
| 4653 ALU : S3; // any alu | |
| 4654 %} | |
| 4655 | |
| 4656 // Long ALU reg-reg operation | |
| 4657 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 4658 instruction_count(2); | |
| 4659 dst : S4(write); | |
| 4660 src : S3(read); | |
| 4661 D0 : S0(2); // big decoder only; twice | |
| 4662 ALU : S3(2); // both alus | |
| 4663 %} | |
| 4664 | |
| 4665 // Integer ALU reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4666 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 4667 single_instruction; |
| 4668 dst : S5(write); | |
| 4669 mem : S3(read); | |
| 4670 D0 : S0; // big decoder only | |
| 4671 ALU : S4; // any alu | |
| 4672 MEM : S3; // any mem | |
| 4673 %} | |
| 4674 | |
| 4675 // Long ALU reg-mem operation | |
| 4676 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 4677 instruction_count(2); | |
| 4678 dst : S5(write); | |
| 4679 mem : S3(read); | |
| 4680 D0 : S0(2); // big decoder only; twice | |
| 4681 ALU : S4(2); // any 2 alus | |
| 4682 MEM : S3(2); // both mems | |
| 4683 %} | |
| 4684 | |
| 4685 // Integer mem operation (prefetch) | |
| 4686 pipe_class ialu_mem(memory mem) | |
| 4687 %{ | |
| 4688 single_instruction; | |
| 4689 mem : S3(read); | |
| 4690 D0 : S0; // big decoder only | |
| 4691 MEM : S3; // any mem | |
| 4692 %} | |
| 4693 | |
| 4694 // Integer Store to Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4695 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 4696 single_instruction; |
| 4697 mem : S3(read); | |
| 4698 src : S5(read); | |
| 4699 D0 : S0; // big decoder only | |
| 4700 ALU : S4; // any alu | |
| 4701 MEM : S3; | |
| 4702 %} | |
| 4703 | |
| 4704 // Long Store to Memory | |
| 4705 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 4706 instruction_count(2); | |
| 4707 mem : S3(read); | |
| 4708 src : S5(read); | |
| 4709 D0 : S0(2); // big decoder only; twice | |
| 4710 ALU : S4(2); // any 2 alus | |
| 4711 MEM : S3(2); // Both mems | |
| 4712 %} | |
| 4713 | |
| 4714 // Integer Store to Memory | |
| 4715 pipe_class ialu_mem_imm(memory mem) %{ | |
| 4716 single_instruction; | |
| 4717 mem : S3(read); | |
| 4718 D0 : S0; // big decoder only | |
| 4719 ALU : S4; // any alu | |
| 4720 MEM : S3; | |
| 4721 %} | |
| 4722 | |
| 4723 // Integer ALU0 reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4724 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 4725 single_instruction; |
| 4726 dst : S4(write); | |
| 4727 src : S3(read); | |
| 4728 D0 : S0; // Big decoder only | |
| 4729 ALU0 : S3; // only alu0 | |
| 4730 %} | |
| 4731 | |
| 4732 // Integer ALU0 reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4733 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 4734 single_instruction; |
| 4735 dst : S5(write); | |
| 4736 mem : S3(read); | |
| 4737 D0 : S0; // big decoder only | |
| 4738 ALU0 : S4; // ALU0 only | |
| 4739 MEM : S3; // any mem | |
| 4740 %} | |
| 4741 | |
| 4742 // Integer ALU reg-reg operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4743 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 4744 single_instruction; |
| 4745 cr : S4(write); | |
| 4746 src1 : S3(read); | |
| 4747 src2 : S3(read); | |
| 4748 DECODE : S0; // any decoder | |
| 4749 ALU : S3; // any alu | |
| 4750 %} | |
| 4751 | |
| 4752 // Integer ALU reg-imm operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4753 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 4754 single_instruction; |
| 4755 cr : S4(write); | |
| 4756 src1 : S3(read); | |
| 4757 DECODE : S0; // any decoder | |
| 4758 ALU : S3; // any alu | |
| 4759 %} | |
| 4760 | |
| 4761 // Integer ALU reg-mem operation | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4762 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 4763 single_instruction; |
| 4764 cr : S4(write); | |
| 4765 src1 : S3(read); | |
| 4766 src2 : S3(read); | |
| 4767 D0 : S0; // big decoder only | |
| 4768 ALU : S4; // any alu | |
| 4769 MEM : S3; | |
| 4770 %} | |
| 4771 | |
| 4772 // Conditional move reg-reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4773 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 4774 instruction_count(4); |
| 4775 y : S4(read); | |
| 4776 q : S3(read); | |
| 4777 p : S3(read); | |
| 4778 DECODE : S0(4); // any decoder | |
| 4779 %} | |
| 4780 | |
| 4781 // Conditional move reg-reg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4782 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 4783 single_instruction; |
| 4784 dst : S4(write); | |
| 4785 src : S3(read); | |
| 4786 cr : S3(read); | |
| 4787 DECODE : S0; // any decoder | |
| 4788 %} | |
| 4789 | |
| 4790 // Conditional move reg-mem | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
4791 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 4792 single_instruction; |
| 4793 dst : S4(write); | |
| 4794 src : S3(read); | |
| 4795 cr : S3(read); | |
| 4796 DECODE : S0; // any decoder | |
| 4797 MEM : S3; | |
| 4798 %} | |
| 4799 | |
| 4800 // Conditional move reg-reg long | |
| 4801 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 4802 single_instruction; | |
| 4803 dst : S4(write); | |
| 4804 src : S3(read); | |
| 4805 cr : S3(read); | |
| 4806 DECODE : S0(2); // any 2 decoders | |
| 4807 %} | |
| 4808 | |
| 4809 // Conditional move double reg-reg | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4810 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 4811 single_instruction; |
| 4812 dst : S4(write); | |
| 4813 src : S3(read); | |
| 4814 cr : S3(read); | |
| 4815 DECODE : S0; // any decoder | |
| 4816 %} | |
| 4817 | |
| 4818 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4819 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 4820 instruction_count(2); |
| 4821 dst : S3(read); | |
| 4822 DECODE : S0(2); // any 2 decoders | |
| 4823 FPU : S3; | |
| 4824 %} | |
| 4825 | |
| 4826 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4827 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 4828 instruction_count(2); |
| 4829 dst : S4(write); | |
| 4830 src : S3(read); | |
| 4831 DECODE : S0(2); // any 2 decoders | |
| 4832 FPU : S3; | |
| 4833 %} | |
| 4834 | |
| 4835 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4836 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 4837 instruction_count(3); |
| 4838 dst : S4(write); | |
| 4839 src1 : S3(read); | |
| 4840 src2 : S3(read); | |
| 4841 DECODE : S0(3); // any 3 decoders | |
| 4842 FPU : S3(2); | |
| 4843 %} | |
| 4844 | |
| 4845 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4846 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 4847 instruction_count(4); |
| 4848 dst : S4(write); | |
| 4849 src1 : S3(read); | |
| 4850 src2 : S3(read); | |
| 4851 src3 : S3(read); | |
| 4852 DECODE : S0(4); // any 3 decoders | |
| 4853 FPU : S3(2); | |
| 4854 %} | |
| 4855 | |
| 4856 // Float reg-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4857 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 4858 instruction_count(4); |
| 4859 dst : S4(write); | |
| 4860 src1 : S3(read); | |
| 4861 src2 : S3(read); | |
| 4862 src3 : S3(read); | |
| 4863 DECODE : S1(3); // any 3 decoders | |
| 4864 D0 : S0; // Big decoder only | |
| 4865 FPU : S3(2); | |
| 4866 MEM : S3; | |
| 4867 %} | |
| 4868 | |
| 4869 // Float reg-mem operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4870 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 4871 instruction_count(2); |
| 4872 dst : S5(write); | |
| 4873 mem : S3(read); | |
| 4874 D0 : S0; // big decoder only | |
| 4875 DECODE : S1; // any decoder for FPU POP | |
| 4876 FPU : S4; | |
| 4877 MEM : S3; // any mem | |
| 4878 %} | |
| 4879 | |
| 4880 // Float reg-mem operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4881 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 4882 instruction_count(3); |
| 4883 dst : S5(write); | |
| 4884 src1 : S3(read); | |
| 4885 mem : S3(read); | |
| 4886 D0 : S0; // big decoder only | |
| 4887 DECODE : S1(2); // any decoder for FPU POP | |
| 4888 FPU : S4; | |
| 4889 MEM : S3; // any mem | |
| 4890 %} | |
| 4891 | |
| 4892 // Float mem-reg operation | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4893 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 4894 instruction_count(2); |
| 4895 src : S5(read); | |
| 4896 mem : S3(read); | |
| 4897 DECODE : S0; // any decoder for FPU PUSH | |
| 4898 D0 : S1; // big decoder only | |
| 4899 FPU : S4; | |
| 4900 MEM : S3; // any mem | |
| 4901 %} | |
| 4902 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4903 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 4904 instruction_count(3); |
| 4905 src1 : S3(read); | |
| 4906 src2 : S3(read); | |
| 4907 mem : S3(read); | |
| 4908 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4909 D0 : S1; // big decoder only | |
| 4910 FPU : S4; | |
| 4911 MEM : S3; // any mem | |
| 4912 %} | |
| 4913 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4914 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 4915 instruction_count(3); |
| 4916 src1 : S3(read); | |
| 4917 src2 : S3(read); | |
| 4918 mem : S4(read); | |
| 4919 DECODE : S0; // any decoder for FPU PUSH | |
| 4920 D0 : S0(2); // big decoder only | |
| 4921 FPU : S4; | |
| 4922 MEM : S3(2); // any mem | |
| 4923 %} | |
| 4924 | |
| 4925 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 4926 instruction_count(2); | |
| 4927 src1 : S3(read); | |
| 4928 dst : S4(read); | |
| 4929 D0 : S0(2); // big decoder only | |
| 4930 MEM : S3(2); // any mem | |
| 4931 %} | |
| 4932 | |
| 4933 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 4934 instruction_count(3); | |
| 4935 src1 : S3(read); | |
| 4936 src2 : S3(read); | |
| 4937 dst : S4(read); | |
| 4938 D0 : S0(3); // big decoder only | |
| 4939 FPU : S4; | |
| 4940 MEM : S3(3); // any mem | |
| 4941 %} | |
| 4942 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4943 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 4944 instruction_count(3); |
| 4945 src1 : S4(read); | |
| 4946 mem : S4(read); | |
| 4947 DECODE : S0; // any decoder for FPU PUSH | |
| 4948 D0 : S0(2); // big decoder only | |
| 4949 FPU : S4; | |
| 4950 MEM : S3(2); // any mem | |
| 4951 %} | |
| 4952 | |
| 4953 // Float load constant | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4954 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 4955 instruction_count(2); |
| 4956 dst : S5(write); | |
| 4957 D0 : S0; // big decoder only for the load | |
| 4958 DECODE : S1; // any decoder for FPU POP | |
| 4959 FPU : S4; | |
| 4960 MEM : S3; // any mem | |
| 4961 %} | |
| 4962 | |
| 4963 // Float load constant | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
4964 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 4965 instruction_count(3); |
| 4966 dst : S5(write); | |
| 4967 src : S3(read); | |
| 4968 D0 : S0; // big decoder only for the load | |
| 4969 DECODE : S1(2); // any decoder for FPU POP | |
| 4970 FPU : S4; | |
| 4971 MEM : S3; // any mem | |
| 4972 %} | |
| 4973 | |
| 4974 // UnConditional branch | |
| 4975 pipe_class pipe_jmp( label labl ) %{ | |
| 4976 single_instruction; | |
| 4977 BR : S3; | |
| 4978 %} | |
| 4979 | |
| 4980 // Conditional branch | |
| 4981 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 4982 single_instruction; | |
| 4983 cr : S1(read); | |
| 4984 BR : S3; | |
| 4985 %} | |
| 4986 | |
| 4987 // Allocation idiom | |
| 4988 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 4989 instruction_count(1); force_serialization; | |
| 4990 fixed_latency(6); | |
| 4991 heap_ptr : S3(read); | |
| 4992 DECODE : S0(3); | |
| 4993 D0 : S2; | |
| 4994 MEM : S3; | |
| 4995 ALU : S3(2); | |
| 4996 dst : S5(write); | |
| 4997 BR : S5; | |
| 4998 %} | |
| 4999 | |
| 5000 // Generic big/slow expanded idiom | |
| 5001 pipe_class pipe_slow( ) %{ | |
| 5002 instruction_count(10); multiple_bundles; force_serialization; | |
| 5003 fixed_latency(100); | |
| 5004 D0 : S0(2); | |
| 5005 MEM : S3(2); | |
| 5006 %} | |
| 5007 | |
| 5008 // The real do-nothing guy | |
| 5009 pipe_class empty( ) %{ | |
| 5010 instruction_count(0); | |
| 5011 %} | |
| 5012 | |
| 5013 // Define the class for the Nop node | |
| 5014 define %{ | |
| 5015 MachNop = empty; | |
| 5016 %} | |
| 5017 | |
| 5018 %} | |
| 5019 | |
| 5020 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5021 // | |
| 5022 // match -- States which machine-independent subtree may be replaced | |
| 5023 // by this instruction. | |
| 5024 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5025 // selection to identify a minimum cost tree of machine | |
| 5026 // instructions that matches a tree of machine-independent | |
| 5027 // instructions. | |
| 5028 // format -- A string providing the disassembly for this instruction. | |
| 5029 // The value of an instruction's operand may be inserted | |
| 5030 // by referring to it with a '$' prefix. | |
| 5031 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5032 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5033 // respectively. The primary opcode is commonly used to | |
| 5034 // indicate the type of machine instruction, while secondary | |
| 5035 // and tertiary are often used for prefix options or addressing | |
| 5036 // modes. | |
| 5037 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5038 // name must have been defined in an 'enc_class' specification | |
| 5039 // in the encode section of the architecture description. | |
| 5040 | |
| 5041 //----------BSWAP-Instruction-------------------------------------------------- | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5042 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5043 match(Set dst (ReverseBytesI dst)); |
| 5044 | |
| 5045 format %{ "BSWAP $dst" %} | |
| 5046 opcode(0x0F, 0xC8); | |
| 5047 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5048 ins_pipe( ialu_reg ); | |
| 5049 %} | |
| 5050 | |
| 5051 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5052 match(Set dst (ReverseBytesL dst)); | |
| 5053 | |
| 5054 format %{ "BSWAP $dst.lo\n\t" | |
| 5055 "BSWAP $dst.hi\n\t" | |
| 5056 "XCHG $dst.lo $dst.hi" %} | |
| 5057 | |
| 5058 ins_cost(125); | |
| 5059 ins_encode( bswap_long_bytes(dst) ); | |
| 5060 ins_pipe( ialu_reg_reg); | |
| 5061 %} | |
| 5062 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5063 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5064 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5065 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5066 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5067 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5068 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5069 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5070 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5071 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5072 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5073 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5074 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5075 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5076 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5077 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5078 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5079 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5080 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5081 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5082 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5083 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5084 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5085 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5086 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5087 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5088 |
| 0 | 5089 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5090 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5091 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5092 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5093 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5094 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5095 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5096 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5097 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5098 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5099 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5100 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5101 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5102 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5103 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5104 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5105 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5106 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5107 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5108 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5109 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5110 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5111 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5112 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5113 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5114 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5115 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5116 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5117 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5118 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5119 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5120 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5121 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5122 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5123 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5124 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5125 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5126 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5127 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5128 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5129 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5130 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5131 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5132 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5133 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5134 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5135 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5136 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5137 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5138 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5139 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5140 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5141 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5142 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5143 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5144 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5145 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5146 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5147 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5148 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5149 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5150 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5151 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5152 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5153 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5154 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5155 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5156 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5157 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5158 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5159 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5160 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5161 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5162 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5163 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5164 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5165 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5166 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5167 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5168 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5169 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5170 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5171 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5172 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5173 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5174 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5175 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5176 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5177 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5178 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5179 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5180 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5181 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5182 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5183 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5184 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5185 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5186 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5187 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5188 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5189 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5190 match(Set dst (CountTrailingZerosI src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5191 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5192 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5193 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5194 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5195 __ tzcntl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5196 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5197 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5198 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5199 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5200 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5201 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5202 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5203 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5204 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5205 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5206 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5207 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5208 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5209 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5210 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5211 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5212 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5213 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5214 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5215 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5216 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5217 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5218 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5219 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5220 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5221 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5222 match(Set dst (CountTrailingZerosL src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5223 effect(TEMP dst, KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5224 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5225 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5226 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5227 "TZCNT $dst, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5228 "ADD $dst, 32\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5229 "done:" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5230 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5231 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5232 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5233 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5234 __ tzcntl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5235 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5236 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5237 __ addl(Rdst, BitsPerInt); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5238 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5239 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5240 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5241 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5242 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5243 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5244 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5245 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5246 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5247 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5248 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5249 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5250 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5251 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5252 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5253 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5254 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5255 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5256 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5257 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5258 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5259 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5260 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5261 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5262 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5263 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5264 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5265 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5266 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5267 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5268 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5269 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5270 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5271 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5272 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5273 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5274 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5275 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5276 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5277 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5278 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5279 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5280 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5281 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5282 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5283 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5284 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5285 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5286 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5287 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5288 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5289 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5290 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5291 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5292 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5293 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5294 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5295 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5296 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5297 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5298 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5299 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5300 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5301 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5302 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5303 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5304 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5305 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5306 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5307 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5308 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5309 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5310 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5311 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5312 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5313 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5314 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5315 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5316 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5317 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5318 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5319 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5320 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5321 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5322 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5323 format %{ "POPCNT $dst, $mem\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5324 "POPCNT $tmp, $mem+4\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5325 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5326 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5327 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5328 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5329 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5330 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5331 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5332 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5333 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5334 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5335 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5336 |
| 0 | 5337 //----------Load/Store/Move Instructions--------------------------------------- |
| 5338 //----------Load Instructions-------------------------------------------------- | |
| 5339 // Load Byte (8bit signed) | |
| 5340 instruct loadB(xRegI dst, memory mem) %{ | |
| 5341 match(Set dst (LoadB mem)); | |
| 5342 | |
| 5343 ins_cost(125); | |
| 624 | 5344 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5345 | |
| 5346 ins_encode %{ | |
| 5347 __ movsbl($dst$$Register, $mem$$Address); | |
| 5348 %} | |
| 5349 | |
| 5350 ins_pipe(ialu_reg_mem); | |
| 5351 %} | |
| 5352 | |
| 5353 // Load Byte (8bit signed) into Long Register | |
| 824 | 5354 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5355 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5356 effect(KILL cr); |
| 624 | 5357 |
| 5358 ins_cost(375); | |
| 5359 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5360 "MOV $dst.hi,$dst.lo\n\t" | |
| 5361 "SAR $dst.hi,7" %} | |
| 5362 | |
| 5363 ins_encode %{ | |
| 5364 __ movsbl($dst$$Register, $mem$$Address); | |
| 5365 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5366 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5367 %} | |
| 5368 | |
| 5369 ins_pipe(ialu_reg_mem); | |
| 5370 %} | |
| 5371 | |
| 5372 // Load Unsigned Byte (8bit UNsigned) | |
| 5373 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5374 match(Set dst (LoadUB mem)); | |
| 0 | 5375 |
| 5376 ins_cost(125); | |
| 624 | 5377 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5378 | |
| 5379 ins_encode %{ | |
| 5380 __ movzbl($dst$$Register, $mem$$Address); | |
| 5381 %} | |
| 5382 | |
| 5383 ins_pipe(ialu_reg_mem); | |
| 5384 %} | |
| 5385 | |
| 5386 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5387 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5388 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5389 effect(KILL cr); |
| 624 | 5390 |
| 5391 ins_cost(250); | |
| 5392 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5393 "XOR $dst.hi,$dst.hi" %} | |
| 5394 | |
| 5395 ins_encode %{ | |
| 824 | 5396 Register Rdst = $dst$$Register; |
| 5397 __ movzbl(Rdst, $mem$$Address); | |
| 5398 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5399 %} | |
| 5400 | |
| 5401 ins_pipe(ialu_reg_mem); | |
| 5402 %} | |
| 5403 | |
| 5404 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5405 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5406 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5407 effect(KILL cr); | |
| 5408 | |
| 5409 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5410 "XOR $dst.hi,$dst.hi\n\t" | |
| 5411 "AND $dst.lo,$mask" %} | |
| 5412 ins_encode %{ | |
| 5413 Register Rdst = $dst$$Register; | |
| 5414 __ movzbl(Rdst, $mem$$Address); | |
| 5415 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5416 __ andl(Rdst, $mask$$constant); | |
| 5417 %} | |
| 624 | 5418 ins_pipe(ialu_reg_mem); |
| 5419 %} | |
| 5420 | |
| 5421 // Load Short (16bit signed) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5422 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5423 match(Set dst (LoadS mem)); |
| 5424 | |
| 5425 ins_cost(125); | |
| 5426 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5427 | |
| 5428 ins_encode %{ | |
| 5429 __ movswl($dst$$Register, $mem$$Address); | |
| 5430 %} | |
| 5431 | |
| 5432 ins_pipe(ialu_reg_mem); | |
| 5433 %} | |
| 5434 | |
| 785 | 5435 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5436 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5437 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5438 | |
| 5439 ins_cost(125); | |
| 5440 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5441 ins_encode %{ | |
| 5442 __ movsbl($dst$$Register, $mem$$Address); | |
| 5443 %} | |
| 5444 ins_pipe(ialu_reg_mem); | |
| 5445 %} | |
| 5446 | |
| 624 | 5447 // Load Short (16bit signed) into Long Register |
| 824 | 5448 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5449 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5450 effect(KILL cr); |
| 624 | 5451 |
| 5452 ins_cost(375); | |
| 5453 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5454 "MOV $dst.hi,$dst.lo\n\t" | |
| 5455 "SAR $dst.hi,15" %} | |
| 5456 | |
| 5457 ins_encode %{ | |
| 5458 __ movswl($dst$$Register, $mem$$Address); | |
| 5459 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5460 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5461 %} | |
| 5462 | |
| 5463 ins_pipe(ialu_reg_mem); | |
| 0 | 5464 %} |
| 5465 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5466 // Load Unsigned Short/Char (16bit unsigned) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5467 instruct loadUS(rRegI dst, memory mem) %{ |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5468 match(Set dst (LoadUS mem)); |
| 0 | 5469 |
| 5470 ins_cost(125); | |
| 624 | 5471 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5472 | |
| 5473 ins_encode %{ | |
| 5474 __ movzwl($dst$$Register, $mem$$Address); | |
| 5475 %} | |
| 5476 | |
| 5477 ins_pipe(ialu_reg_mem); | |
| 5478 %} | |
| 5479 | |
| 785 | 5480 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5481 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5482 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5483 | |
| 5484 ins_cost(125); | |
| 5485 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5486 ins_encode %{ | |
| 5487 __ movsbl($dst$$Register, $mem$$Address); | |
| 5488 %} | |
| 5489 ins_pipe(ialu_reg_mem); | |
| 5490 %} | |
| 5491 | |
| 624 | 5492 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5493 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5494 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5495 effect(KILL cr); |
| 624 | 5496 |
| 5497 ins_cost(250); | |
| 5498 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5499 "XOR $dst.hi,$dst.hi" %} | |
| 5500 | |
| 5501 ins_encode %{ | |
| 5502 __ movzwl($dst$$Register, $mem$$Address); | |
| 5503 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5504 %} | |
| 5505 | |
| 5506 ins_pipe(ialu_reg_mem); | |
| 0 | 5507 %} |
| 5508 | |
| 824 | 5509 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5510 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5511 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5512 effect(KILL cr); | |
| 5513 | |
| 5514 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5515 "XOR $dst.hi,$dst.hi" %} | |
| 5516 ins_encode %{ | |
| 5517 Register Rdst = $dst$$Register; | |
| 5518 __ movzbl(Rdst, $mem$$Address); | |
| 5519 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5520 %} | |
| 5521 ins_pipe(ialu_reg_mem); | |
| 5522 %} | |
| 5523 | |
| 5524 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5525 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5526 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5527 effect(KILL cr); | |
| 5528 | |
| 5529 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5530 "XOR $dst.hi,$dst.hi\n\t" | |
| 5531 "AND $dst.lo,$mask" %} | |
| 5532 ins_encode %{ | |
| 5533 Register Rdst = $dst$$Register; | |
| 5534 __ movzwl(Rdst, $mem$$Address); | |
| 5535 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5536 __ andl(Rdst, $mask$$constant); | |
| 5537 %} | |
| 5538 ins_pipe(ialu_reg_mem); | |
| 5539 %} | |
| 5540 | |
| 0 | 5541 // Load Integer |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5542 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5543 match(Set dst (LoadI mem)); |
| 5544 | |
| 5545 ins_cost(125); | |
| 624 | 5546 format %{ "MOV $dst,$mem\t# int" %} |
| 5547 | |
| 5548 ins_encode %{ | |
| 5549 __ movl($dst$$Register, $mem$$Address); | |
| 5550 %} | |
| 5551 | |
| 5552 ins_pipe(ialu_reg_mem); | |
| 5553 %} | |
| 5554 | |
| 785 | 5555 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5556 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5557 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5558 | |
| 5559 ins_cost(125); | |
| 5560 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5561 ins_encode %{ | |
| 5562 __ movsbl($dst$$Register, $mem$$Address); | |
| 5563 %} | |
| 5564 ins_pipe(ialu_reg_mem); | |
| 5565 %} | |
| 5566 | |
| 5567 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5568 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 5569 match(Set dst (AndI (LoadI mem) mask)); |
| 5570 | |
| 5571 ins_cost(125); | |
| 5572 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 5573 ins_encode %{ | |
| 5574 __ movzbl($dst$$Register, $mem$$Address); | |
| 5575 %} | |
| 5576 ins_pipe(ialu_reg_mem); | |
| 5577 %} | |
| 5578 | |
| 5579 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5580 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 5581 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 5582 | |
| 5583 ins_cost(125); | |
| 5584 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 5585 ins_encode %{ | |
| 5586 __ movswl($dst$$Register, $mem$$Address); | |
| 5587 %} | |
| 5588 ins_pipe(ialu_reg_mem); | |
| 5589 %} | |
| 5590 | |
| 5591 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5592 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 5593 match(Set dst (AndI (LoadI mem) mask)); |
| 5594 | |
| 5595 ins_cost(125); | |
| 5596 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 5597 ins_encode %{ | |
| 5598 __ movzwl($dst$$Register, $mem$$Address); | |
| 5599 %} | |
| 5600 ins_pipe(ialu_reg_mem); | |
| 5601 %} | |
| 5602 | |
| 624 | 5603 // Load Integer into Long Register |
| 824 | 5604 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5605 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 5606 effect(KILL cr); |
| 624 | 5607 |
| 5608 ins_cost(375); | |
| 5609 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 5610 "MOV $dst.hi,$dst.lo\n\t" | |
| 5611 "SAR $dst.hi,31" %} | |
| 5612 | |
| 5613 ins_encode %{ | |
| 5614 __ movl($dst$$Register, $mem$$Address); | |
| 5615 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5616 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 5617 %} | |
| 5618 | |
| 5619 ins_pipe(ialu_reg_mem); | |
| 5620 %} | |
| 5621 | |
| 824 | 5622 // Load Integer with mask 0xFF into Long Register |
| 5623 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5624 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5625 effect(KILL cr); | |
| 5626 | |
| 5627 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 5628 "XOR $dst.hi,$dst.hi" %} | |
| 5629 ins_encode %{ | |
| 5630 Register Rdst = $dst$$Register; | |
| 5631 __ movzbl(Rdst, $mem$$Address); | |
| 5632 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5633 %} | |
| 5634 ins_pipe(ialu_reg_mem); | |
| 5635 %} | |
| 5636 | |
| 5637 // Load Integer with mask 0xFFFF into Long Register | |
| 5638 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 5639 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5640 effect(KILL cr); | |
| 5641 | |
| 5642 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 5643 "XOR $dst.hi,$dst.hi" %} | |
| 5644 ins_encode %{ | |
| 5645 Register Rdst = $dst$$Register; | |
| 5646 __ movzwl(Rdst, $mem$$Address); | |
| 5647 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5648 %} | |
| 5649 ins_pipe(ialu_reg_mem); | |
| 5650 %} | |
| 5651 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
5652 // Load Integer with 31-bit mask into Long Register |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
5653 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 5654 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5655 effect(KILL cr); | |
| 5656 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
5657 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5658 "XOR $dst.hi,$dst.hi\n\t" |
| 5659 "AND $dst.lo,$mask" %} | |
| 5660 ins_encode %{ | |
| 5661 Register Rdst = $dst$$Register; | |
| 5662 __ movl(Rdst, $mem$$Address); | |
| 5663 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5664 __ andl(Rdst, $mask$$constant); | |
| 5665 %} | |
| 5666 ins_pipe(ialu_reg_mem); | |
| 5667 %} | |
| 5668 | |
| 624 | 5669 // Load Unsigned Integer into Long Register |
| 6849 | 5670 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 5671 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 5672 effect(KILL cr); |
| 624 | 5673 |
| 5674 ins_cost(250); | |
| 5675 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 5676 "XOR $dst.hi,$dst.hi" %} | |
| 5677 | |
| 5678 ins_encode %{ | |
| 5679 __ movl($dst$$Register, $mem$$Address); | |
| 5680 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5681 %} | |
| 5682 | |
| 5683 ins_pipe(ialu_reg_mem); | |
| 0 | 5684 %} |
| 5685 | |
| 5686 // Load Long. Cannot clobber address while loading, so restrict address | |
| 5687 // register to ESI | |
| 5688 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 5689 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 5690 match(Set dst (LoadL mem)); | |
| 5691 | |
| 5692 ins_cost(250); | |
| 624 | 5693 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 5694 "MOV $dst.hi,$mem+4" %} |
| 624 | 5695 |
| 5696 ins_encode %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5697 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5698 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 5699 __ movl($dst$$Register, Amemlo); |
| 5700 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 5701 %} | |
| 5702 | |
| 5703 ins_pipe(ialu_reg_long_mem); | |
| 0 | 5704 %} |
| 5705 | |
| 5706 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 5707 // then store it down to the stack and reload on the int | |
| 5708 // side. | |
| 5709 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 5710 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 5711 match(Set dst (LoadL mem)); | |
| 5712 | |
| 5713 ins_cost(200); | |
| 5714 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 5715 "FISTp $dst" %} | |
| 5716 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 5717 ins_pipe( fpu_reg_mem ); | |
| 5718 %} | |
| 5719 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5720 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 5721 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5722 match(Set dst (LoadL mem)); | |
| 5723 effect(TEMP tmp); | |
| 5724 ins_cost(180); | |
| 5725 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5726 "MOVSD $dst,$tmp" %} | |
| 4759 | 5727 ins_encode %{ |
| 5728 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5729 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 5730 %} | |
| 0 | 5731 ins_pipe( pipe_slow ); |
| 5732 %} | |
| 5733 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5734 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 5735 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5736 match(Set dst (LoadL mem)); | |
| 5737 effect(TEMP tmp); | |
| 5738 ins_cost(160); | |
| 5739 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5740 "MOVD $dst.lo,$tmp\n\t" | |
| 5741 "PSRLQ $tmp,32\n\t" | |
| 5742 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 5743 ins_encode %{ |
| 5744 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5745 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 5746 __ psrlq($tmp$$XMMRegister, 32); | |
| 5747 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 5748 %} | |
| 0 | 5749 ins_pipe( pipe_slow ); |
| 5750 %} | |
| 5751 | |
| 5752 // Load Range | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5753 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 5754 match(Set dst (LoadRange mem)); |
| 5755 | |
| 5756 ins_cost(125); | |
| 5757 format %{ "MOV $dst,$mem" %} | |
| 5758 opcode(0x8B); | |
| 5759 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5760 ins_pipe( ialu_reg_mem ); | |
| 5761 %} | |
| 5762 | |
| 5763 | |
| 5764 // Load Pointer | |
| 5765 instruct loadP(eRegP dst, memory mem) %{ | |
| 5766 match(Set dst (LoadP mem)); | |
| 5767 | |
| 5768 ins_cost(125); | |
| 5769 format %{ "MOV $dst,$mem" %} | |
| 5770 opcode(0x8B); | |
| 5771 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5772 ins_pipe( ialu_reg_mem ); | |
| 5773 %} | |
| 5774 | |
| 5775 // Load Klass Pointer | |
| 5776 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 5777 match(Set dst (LoadKlass mem)); | |
| 5778 | |
| 5779 ins_cost(125); | |
| 5780 format %{ "MOV $dst,$mem" %} | |
| 5781 opcode(0x8B); | |
| 5782 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5783 ins_pipe( ialu_reg_mem ); | |
| 5784 %} | |
| 5785 | |
| 5786 // Load Double | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5787 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 5788 predicate(UseSSE<=1); |
| 5789 match(Set dst (LoadD mem)); | |
| 5790 | |
| 5791 ins_cost(150); | |
| 5792 format %{ "FLD_D ST,$mem\n\t" | |
| 5793 "FSTP $dst" %} | |
| 5794 opcode(0xDD); /* DD /0 */ | |
| 5795 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5796 Pop_Reg_DPR(dst) ); |
| 0 | 5797 ins_pipe( fpu_reg_mem ); |
| 5798 %} | |
| 5799 | |
| 5800 // Load Double to XMM | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5801 instruct loadD(regD dst, memory mem) %{ |
| 0 | 5802 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 5803 match(Set dst (LoadD mem)); | |
| 5804 ins_cost(145); | |
| 5805 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 5806 ins_encode %{ |
| 5807 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5808 %} | |
| 0 | 5809 ins_pipe( pipe_slow ); |
| 5810 %} | |
| 5811 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5812 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 5813 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 5814 match(Set dst (LoadD mem)); | |
| 5815 ins_cost(145); | |
| 5816 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 5817 ins_encode %{ |
| 5818 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5819 %} | |
| 0 | 5820 ins_pipe( pipe_slow ); |
| 5821 %} | |
| 5822 | |
| 5823 // Load to XMM register (single-precision floating point) | |
| 5824 // MOVSS instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5825 instruct loadF(regF dst, memory mem) %{ |
| 0 | 5826 predicate(UseSSE>=1); |
| 5827 match(Set dst (LoadF mem)); | |
| 5828 ins_cost(145); | |
| 5829 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 5830 ins_encode %{ |
| 5831 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 5832 %} | |
| 0 | 5833 ins_pipe( pipe_slow ); |
| 5834 %} | |
| 5835 | |
| 5836 // Load Float | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5837 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 5838 predicate(UseSSE==0); |
| 5839 match(Set dst (LoadF mem)); | |
| 5840 | |
| 5841 ins_cost(150); | |
| 5842 format %{ "FLD_S ST,$mem\n\t" | |
| 5843 "FSTP $dst" %} | |
| 5844 opcode(0xD9); /* D9 /0 */ | |
| 5845 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5846 Pop_Reg_FPR(dst) ); |
| 0 | 5847 ins_pipe( fpu_reg_mem ); |
| 5848 %} | |
| 5849 | |
| 5850 // Load Effective Address | |
| 5851 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 5852 match(Set dst mem); | |
| 5853 | |
| 5854 ins_cost(110); | |
| 5855 format %{ "LEA $dst,$mem" %} | |
| 5856 opcode(0x8D); | |
| 5857 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5858 ins_pipe( ialu_reg_reg_fat ); | |
| 5859 %} | |
| 5860 | |
| 5861 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 5862 match(Set dst mem); | |
| 5863 | |
| 5864 ins_cost(110); | |
| 5865 format %{ "LEA $dst,$mem" %} | |
| 5866 opcode(0x8D); | |
| 5867 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5868 ins_pipe( ialu_reg_reg_fat ); | |
| 5869 %} | |
| 5870 | |
| 5871 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 5872 match(Set dst mem); | |
| 5873 | |
| 5874 ins_cost(110); | |
| 5875 format %{ "LEA $dst,$mem" %} | |
| 5876 opcode(0x8D); | |
| 5877 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5878 ins_pipe( ialu_reg_reg_fat ); | |
| 5879 %} | |
| 5880 | |
| 5881 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 5882 match(Set dst mem); | |
| 5883 | |
| 5884 ins_cost(110); | |
| 5885 format %{ "LEA $dst,$mem" %} | |
| 5886 opcode(0x8D); | |
| 5887 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5888 ins_pipe( ialu_reg_reg_fat ); | |
| 5889 %} | |
| 5890 | |
| 5891 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 5892 match(Set dst mem); | |
| 5893 | |
| 5894 ins_cost(110); | |
| 5895 format %{ "LEA $dst,$mem" %} | |
| 5896 opcode(0x8D); | |
| 5897 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5898 ins_pipe( ialu_reg_reg_fat ); | |
| 5899 %} | |
| 5900 | |
| 5901 // Load Constant | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5902 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 5903 match(Set dst src); |
| 5904 | |
| 5905 format %{ "MOV $dst,$src" %} | |
| 5906 ins_encode( LdImmI(dst, src) ); | |
| 5907 ins_pipe( ialu_reg_fat ); | |
| 5908 %} | |
| 5909 | |
| 5910 // Load Constant zero | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5911 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 5912 match(Set dst src); |
| 5913 effect(KILL cr); | |
| 5914 | |
| 5915 ins_cost(50); | |
| 5916 format %{ "XOR $dst,$dst" %} | |
| 5917 opcode(0x33); /* + rd */ | |
| 5918 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 5919 ins_pipe( ialu_reg ); | |
| 5920 %} | |
| 5921 | |
| 5922 instruct loadConP(eRegP dst, immP src) %{ | |
| 5923 match(Set dst src); | |
| 5924 | |
| 5925 format %{ "MOV $dst,$src" %} | |
| 5926 opcode(0xB8); /* + rd */ | |
| 5927 ins_encode( LdImmP(dst, src) ); | |
| 5928 ins_pipe( ialu_reg_fat ); | |
| 5929 %} | |
| 5930 | |
| 5931 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 5932 match(Set dst src); | |
| 5933 effect(KILL cr); | |
| 5934 ins_cost(200); | |
| 5935 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 5936 "MOV $dst.hi,$src.hi" %} | |
| 5937 opcode(0xB8); | |
| 5938 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 5939 ins_pipe( ialu_reg_long_fat ); | |
| 5940 %} | |
| 5941 | |
| 5942 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 5943 match(Set dst src); | |
| 5944 effect(KILL cr); | |
| 5945 ins_cost(150); | |
| 5946 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 5947 "XOR $dst.hi,$dst.hi" %} | |
| 5948 opcode(0x33,0x33); | |
| 5949 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 5950 ins_pipe( ialu_reg_long ); | |
| 5951 %} | |
| 5952 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5953 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5954 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 5955 match(Set dst con); |
| 5956 ins_cost(125); | |
| 5957 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 5958 "FSTP $dst" %} | |
| 5959 ins_encode %{ | |
| 5960 __ fld_s($constantaddress($con)); | |
| 5961 __ fstp_d($dst$$reg); | |
| 5962 %} | |
| 5963 ins_pipe(fpu_reg_con); | |
| 5964 %} | |
| 5965 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5966 // The instruction usage is guarded by predicate in operand immFPR0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5967 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 5968 match(Set dst con); |
| 0 | 5969 ins_cost(125); |
| 2008 | 5970 format %{ "FLDZ ST\n\t" |
| 0 | 5971 "FSTP $dst" %} |
| 2008 | 5972 ins_encode %{ |
| 5973 __ fldz(); | |
| 5974 __ fstp_d($dst$$reg); | |
| 5975 %} | |
| 5976 ins_pipe(fpu_reg_con); | |
| 5977 %} | |
| 5978 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5979 // The instruction usage is guarded by predicate in operand immFPR1(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5980 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 5981 match(Set dst con); |
| 5982 ins_cost(125); | |
| 5983 format %{ "FLD1 ST\n\t" | |
| 5984 "FSTP $dst" %} | |
| 5985 ins_encode %{ | |
| 5986 __ fld1(); | |
| 5987 __ fstp_d($dst$$reg); | |
| 5988 %} | |
| 5989 ins_pipe(fpu_reg_con); | |
| 0 | 5990 %} |
| 5991 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5992 // The instruction usage is guarded by predicate in operand immF(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
5993 instruct loadConF(regF dst, immF con) %{ |
| 0 | 5994 match(Set dst con); |
| 5995 ins_cost(125); | |
| 2008 | 5996 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 5997 ins_encode %{ | |
| 5998 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5999 %} | |
| 6000 ins_pipe(pipe_slow); | |
| 0 | 6001 %} |
| 6002 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6003 // The instruction usage is guarded by predicate in operand immF0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6004 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 6005 match(Set dst src); |
| 6006 ins_cost(100); | |
| 6007 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 6008 ins_encode %{ |
| 6009 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6010 %} | |
| 6011 ins_pipe(pipe_slow); | |
| 0 | 6012 %} |
| 6013 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6014 // The instruction usage is guarded by predicate in operand immDPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6015 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 6016 match(Set dst con); |
| 6017 ins_cost(125); | |
| 6018 | |
| 6019 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 6020 "FSTP $dst" %} | |
| 6021 ins_encode %{ | |
| 6022 __ fld_d($constantaddress($con)); | |
| 6023 __ fstp_d($dst$$reg); | |
| 6024 %} | |
| 6025 ins_pipe(fpu_reg_con); | |
| 6026 %} | |
| 6027 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6028 // The instruction usage is guarded by predicate in operand immDPR0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6029 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 6030 match(Set dst con); |
| 0 | 6031 ins_cost(125); |
| 6032 | |
| 2008 | 6033 format %{ "FLDZ ST\n\t" |
| 0 | 6034 "FSTP $dst" %} |
| 2008 | 6035 ins_encode %{ |
| 6036 __ fldz(); | |
| 6037 __ fstp_d($dst$$reg); | |
| 6038 %} | |
| 6039 ins_pipe(fpu_reg_con); | |
| 6040 %} | |
| 6041 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6042 // The instruction usage is guarded by predicate in operand immDPR1(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6043 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6044 match(Set dst con); |
| 6045 ins_cost(125); | |
| 6046 | |
| 6047 format %{ "FLD1 ST\n\t" | |
| 6048 "FSTP $dst" %} | |
| 6049 ins_encode %{ | |
| 6050 __ fld1(); | |
| 6051 __ fstp_d($dst$$reg); | |
| 6052 %} | |
| 6053 ins_pipe(fpu_reg_con); | |
| 0 | 6054 %} |
| 6055 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6056 // The instruction usage is guarded by predicate in operand immD(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6057 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6058 match(Set dst con); |
| 6059 ins_cost(125); | |
| 2008 | 6060 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6061 ins_encode %{ | |
| 6062 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6063 %} | |
| 6064 ins_pipe(pipe_slow); | |
| 0 | 6065 %} |
| 6066 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6067 // The instruction usage is guarded by predicate in operand immD0(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6068 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6069 match(Set dst src); |
| 6070 ins_cost(100); | |
| 6071 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6072 ins_encode %{ |
| 6073 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6074 %} | |
| 0 | 6075 ins_pipe( pipe_slow ); |
| 6076 %} | |
| 6077 | |
| 6078 // Load Stack Slot | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6079 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6080 match(Set dst src); |
| 6081 ins_cost(125); | |
| 6082 | |
| 6083 format %{ "MOV $dst,$src" %} | |
| 6084 opcode(0x8B); | |
| 6085 ins_encode( OpcP, RegMem(dst,src)); | |
| 6086 ins_pipe( ialu_reg_mem ); | |
| 6087 %} | |
| 6088 | |
| 6089 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6090 match(Set dst src); | |
| 6091 | |
| 6092 ins_cost(200); | |
| 6093 format %{ "MOV $dst,$src.lo\n\t" | |
| 6094 "MOV $dst+4,$src.hi" %} | |
| 6095 opcode(0x8B, 0x8B); | |
| 6096 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6097 ins_pipe( ialu_mem_long_reg ); | |
| 6098 %} | |
| 6099 | |
| 6100 // Load Stack Slot | |
| 6101 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6102 match(Set dst src); | |
| 6103 ins_cost(125); | |
| 6104 | |
| 6105 format %{ "MOV $dst,$src" %} | |
| 6106 opcode(0x8B); | |
| 6107 ins_encode( OpcP, RegMem(dst,src)); | |
| 6108 ins_pipe( ialu_reg_mem ); | |
| 6109 %} | |
| 6110 | |
| 6111 // Load Stack Slot | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6112 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6113 match(Set dst src); |
| 6114 ins_cost(125); | |
| 6115 | |
| 6116 format %{ "FLD_S $src\n\t" | |
| 6117 "FSTP $dst" %} | |
| 6118 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6119 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6120 Pop_Reg_FPR(dst) ); |
| 0 | 6121 ins_pipe( fpu_reg_mem ); |
| 6122 %} | |
| 6123 | |
| 6124 // Load Stack Slot | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6125 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6126 match(Set dst src); |
| 6127 ins_cost(125); | |
| 6128 | |
| 6129 format %{ "FLD_D $src\n\t" | |
| 6130 "FSTP $dst" %} | |
| 6131 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6132 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6133 Pop_Reg_DPR(dst) ); |
| 0 | 6134 ins_pipe( fpu_reg_mem ); |
| 6135 %} | |
| 6136 | |
| 6137 // Prefetch instructions. | |
| 6138 // Must be safe to execute with invalid address (cannot fault). | |
| 6139 | |
| 6140 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6141 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6142 match(PrefetchRead mem); |
| 6143 ins_cost(0); | |
| 6144 size(0); | |
| 6145 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6146 ins_encode(); | |
| 6147 ins_pipe(empty); | |
| 6148 %} | |
| 6149 | |
| 6150 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6151 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6152 match(PrefetchRead mem); |
| 6153 ins_cost(100); | |
| 6154 | |
| 6155 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6156 ins_encode %{ |
| 6157 __ prefetchr($mem$$Address); | |
| 6158 %} | |
| 0 | 6159 ins_pipe(ialu_mem); |
| 6160 %} | |
| 6161 | |
| 6162 instruct prefetchrNTA( memory mem ) %{ | |
| 6163 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6164 match(PrefetchRead mem); | |
| 6165 ins_cost(100); | |
| 6166 | |
| 6167 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6168 ins_encode %{ |
| 6169 __ prefetchnta($mem$$Address); | |
| 6170 %} | |
| 0 | 6171 ins_pipe(ialu_mem); |
| 6172 %} | |
| 6173 | |
| 6174 instruct prefetchrT0( memory mem ) %{ | |
| 6175 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6176 match(PrefetchRead mem); | |
| 6177 ins_cost(100); | |
| 6178 | |
| 6179 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6180 ins_encode %{ |
| 6181 __ prefetcht0($mem$$Address); | |
| 6182 %} | |
| 0 | 6183 ins_pipe(ialu_mem); |
| 6184 %} | |
| 6185 | |
| 6186 instruct prefetchrT2( memory mem ) %{ | |
| 6187 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6188 match(PrefetchRead mem); | |
| 6189 ins_cost(100); | |
| 6190 | |
| 6191 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6192 ins_encode %{ |
| 6193 __ prefetcht2($mem$$Address); | |
| 6194 %} | |
| 0 | 6195 ins_pipe(ialu_mem); |
| 6196 %} | |
| 6197 | |
| 6198 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6199 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6200 match(PrefetchWrite mem); |
| 6201 ins_cost(0); | |
| 6202 size(0); | |
| 6203 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6204 ins_encode(); | |
| 6205 ins_pipe(empty); | |
| 6206 %} | |
| 6207 | |
| 6208 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6209 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6210 match( PrefetchWrite mem ); |
| 6211 ins_cost(100); | |
| 6212 | |
| 6213 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6214 ins_encode %{ |
| 6215 __ prefetchw($mem$$Address); | |
| 6216 %} | |
| 0 | 6217 ins_pipe(ialu_mem); |
| 6218 %} | |
| 6219 | |
| 6220 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6221 predicate(UseSSE>=1); |
| 0 | 6222 match(PrefetchWrite mem); |
| 6223 ins_cost(100); | |
| 6224 | |
| 6225 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6226 ins_encode %{ |
| 6227 __ prefetchnta($mem$$Address); | |
| 6228 %} | |
| 0 | 6229 ins_pipe(ialu_mem); |
| 6230 %} | |
| 6231 | |
| 3854 | 6232 // Prefetch instructions for allocation. |
| 6233 | |
| 6234 instruct prefetchAlloc0( memory mem ) %{ | |
| 6235 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6236 match(PrefetchAllocation mem); | |
| 6237 ins_cost(0); | |
| 6238 size(0); | |
| 6239 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6240 ins_encode(); | |
| 6241 ins_pipe(empty); | |
| 6242 %} | |
| 6243 | |
| 6244 instruct prefetchAlloc( memory mem ) %{ | |
| 6245 predicate(AllocatePrefetchInstr==3); | |
| 6246 match( PrefetchAllocation mem ); | |
| 0 | 6247 ins_cost(100); |
| 6248 | |
| 3854 | 6249 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6250 ins_encode %{ | |
| 6251 __ prefetchw($mem$$Address); | |
| 6252 %} | |
| 6253 ins_pipe(ialu_mem); | |
| 6254 %} | |
| 6255 | |
| 6256 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6257 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6258 match(PrefetchAllocation mem); | |
| 6259 ins_cost(100); | |
| 6260 | |
| 6261 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6262 ins_encode %{ | |
| 6263 __ prefetchnta($mem$$Address); | |
| 6264 %} | |
| 0 | 6265 ins_pipe(ialu_mem); |
| 6266 %} | |
| 6267 | |
| 3854 | 6268 instruct prefetchAllocT0( memory mem ) %{ |
| 6269 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6270 match(PrefetchAllocation mem); | |
| 0 | 6271 ins_cost(100); |
| 6272 | |
| 3854 | 6273 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6274 ins_encode %{ | |
| 6275 __ prefetcht0($mem$$Address); | |
| 6276 %} | |
| 6277 ins_pipe(ialu_mem); | |
| 6278 %} | |
| 6279 | |
| 6280 instruct prefetchAllocT2( memory mem ) %{ | |
| 6281 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6282 match(PrefetchAllocation mem); | |
| 6283 ins_cost(100); | |
| 6284 | |
| 6285 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6286 ins_encode %{ | |
| 6287 __ prefetcht2($mem$$Address); | |
| 6288 %} | |
| 0 | 6289 ins_pipe(ialu_mem); |
| 6290 %} | |
| 6291 | |
| 6292 //----------Store Instructions------------------------------------------------- | |
| 6293 | |
| 6294 // Store Byte | |
| 6295 instruct storeB(memory mem, xRegI src) %{ | |
| 6296 match(Set mem (StoreB mem src)); | |
| 6297 | |
| 6298 ins_cost(125); | |
| 6299 format %{ "MOV8 $mem,$src" %} | |
| 6300 opcode(0x88); | |
| 6301 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6302 ins_pipe( ialu_mem_reg ); | |
| 6303 %} | |
| 6304 | |
| 6305 // Store Char/Short | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6306 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6307 match(Set mem (StoreC mem src)); |
| 6308 | |
| 6309 ins_cost(125); | |
| 6310 format %{ "MOV16 $mem,$src" %} | |
| 6311 opcode(0x89, 0x66); | |
| 6312 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6313 ins_pipe( ialu_mem_reg ); | |
| 6314 %} | |
| 6315 | |
| 6316 // Store Integer | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6317 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6318 match(Set mem (StoreI mem src)); |
| 6319 | |
| 6320 ins_cost(125); | |
| 6321 format %{ "MOV $mem,$src" %} | |
| 6322 opcode(0x89); | |
| 6323 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6324 ins_pipe( ialu_mem_reg ); | |
| 6325 %} | |
| 6326 | |
| 6327 // Store Long | |
| 6328 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6329 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6330 match(Set mem (StoreL mem src)); | |
| 6331 | |
| 6332 ins_cost(200); | |
| 6333 format %{ "MOV $mem,$src.lo\n\t" | |
| 6334 "MOV $mem+4,$src.hi" %} | |
| 6335 opcode(0x89, 0x89); | |
| 6336 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6337 ins_pipe( ialu_mem_long_reg ); | |
| 6338 %} | |
| 6339 | |
| 824 | 6340 // Store Long to Integer |
| 6341 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6342 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6343 | |
| 6344 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6345 ins_encode %{ | |
| 6346 __ movl($mem$$Address, $src$$Register); | |
| 6347 %} | |
| 6348 ins_pipe(ialu_mem_reg); | |
| 6349 %} | |
| 6350 | |
| 0 | 6351 // Volatile Store Long. Must be atomic, so move it into |
| 6352 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6353 // target address before the store (for null-ptr checks) | |
| 6354 // so the memory operand is used twice in the encoding. | |
| 6355 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6356 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6357 match(Set mem (StoreL mem src)); | |
| 6358 effect( KILL cr ); | |
| 6359 ins_cost(400); | |
| 6360 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6361 "FILD $src\n\t" | |
| 6362 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6363 opcode(0x3B); | |
| 6364 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6365 ins_pipe( fpu_reg_mem ); | |
| 6366 %} | |
| 6367 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6368 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6369 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6370 match(Set mem (StoreL mem src)); | |
| 6371 effect( TEMP tmp, KILL cr ); | |
| 6372 ins_cost(380); | |
| 6373 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6374 "MOVSD $tmp,$src\n\t" | |
| 6375 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6376 ins_encode %{ |
| 6377 __ cmpl(rax, $mem$$Address); | |
| 6378 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6379 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6380 %} | |
| 0 | 6381 ins_pipe( pipe_slow ); |
| 6382 %} | |
| 6383 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6384 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6385 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6386 match(Set mem (StoreL mem src)); | |
| 6387 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6388 ins_cost(360); | |
| 6389 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6390 "MOVD $tmp,$src.lo\n\t" | |
| 6391 "MOVD $tmp2,$src.hi\n\t" | |
| 6392 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6393 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6394 ins_encode %{ |
| 6395 __ cmpl(rax, $mem$$Address); | |
| 6396 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6397 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6398 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6399 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6400 %} | |
| 0 | 6401 ins_pipe( pipe_slow ); |
| 6402 %} | |
| 6403 | |
| 6404 // Store Pointer; for storing unknown oops and raw pointers | |
| 6405 instruct storeP(memory mem, anyRegP src) %{ | |
| 6406 match(Set mem (StoreP mem src)); | |
| 6407 | |
| 6408 ins_cost(125); | |
| 6409 format %{ "MOV $mem,$src" %} | |
| 6410 opcode(0x89); | |
| 6411 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6412 ins_pipe( ialu_mem_reg ); | |
| 6413 %} | |
| 6414 | |
| 6415 // Store Integer Immediate | |
| 6416 instruct storeImmI(memory mem, immI src) %{ | |
| 6417 match(Set mem (StoreI mem src)); | |
| 6418 | |
| 6419 ins_cost(150); | |
| 6420 format %{ "MOV $mem,$src" %} | |
| 6421 opcode(0xC7); /* C7 /0 */ | |
| 6422 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6423 ins_pipe( ialu_mem_imm ); | |
| 6424 %} | |
| 6425 | |
| 6426 // Store Short/Char Immediate | |
| 6427 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6428 predicate(UseStoreImmI16); | |
| 6429 match(Set mem (StoreC mem src)); | |
| 6430 | |
| 6431 ins_cost(150); | |
| 6432 format %{ "MOV16 $mem,$src" %} | |
| 6433 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6434 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6435 ins_pipe( ialu_mem_imm ); | |
| 6436 %} | |
| 6437 | |
| 6438 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6439 // need card-mark barriers. | |
| 6440 instruct storeImmP(memory mem, immP src) %{ | |
| 6441 match(Set mem (StoreP mem src)); | |
| 6442 | |
| 6443 ins_cost(150); | |
| 6444 format %{ "MOV $mem,$src" %} | |
| 6445 opcode(0xC7); /* C7 /0 */ | |
| 6446 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6447 ins_pipe( ialu_mem_imm ); | |
| 6448 %} | |
| 6449 | |
| 6450 // Store Byte Immediate | |
| 6451 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6452 match(Set mem (StoreB mem src)); | |
| 6453 | |
| 6454 ins_cost(150); | |
| 6455 format %{ "MOV8 $mem,$src" %} | |
| 6456 opcode(0xC6); /* C6 /0 */ | |
| 6457 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6458 ins_pipe( ialu_mem_imm ); | |
| 6459 %} | |
| 6460 | |
| 6461 // Store CMS card-mark Immediate | |
| 6462 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6463 match(Set mem (StoreCM mem src)); | |
| 6464 | |
| 6465 ins_cost(150); | |
| 6466 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6467 opcode(0xC6); /* C6 /0 */ | |
| 6468 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6469 ins_pipe( ialu_mem_imm ); | |
| 6470 %} | |
| 6471 | |
| 6472 // Store Double | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6473 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6474 predicate(UseSSE<=1); |
| 6475 match(Set mem (StoreD mem src)); | |
| 6476 | |
| 6477 ins_cost(100); | |
| 6478 format %{ "FST_D $mem,$src" %} | |
| 6479 opcode(0xDD); /* DD /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6480 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6481 ins_pipe( fpu_mem_reg ); |
| 6482 %} | |
| 6483 | |
| 6484 // Store double does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6485 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6486 predicate(UseSSE<=1); |
| 6487 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6488 | |
| 6489 ins_cost(100); | |
| 6490 format %{ "FST_D $mem,$src\t# round" %} | |
| 6491 opcode(0xDD); /* DD /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6492 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6493 ins_pipe( fpu_mem_reg ); |
| 6494 %} | |
| 6495 | |
| 6496 // Store XMM register to memory (double-precision floating points) | |
| 6497 // MOVSD instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6498 instruct storeD(memory mem, regD src) %{ |
| 0 | 6499 predicate(UseSSE>=2); |
| 6500 match(Set mem (StoreD mem src)); | |
| 6501 ins_cost(95); | |
| 6502 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6503 ins_encode %{ |
| 6504 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6505 %} | |
| 0 | 6506 ins_pipe( pipe_slow ); |
| 6507 %} | |
| 6508 | |
| 6509 // Store XMM register to memory (single-precision floating point) | |
| 6510 // MOVSS instruction | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6511 instruct storeF(memory mem, regF src) %{ |
| 0 | 6512 predicate(UseSSE>=1); |
| 6513 match(Set mem (StoreF mem src)); | |
| 6514 ins_cost(95); | |
| 6515 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6516 ins_encode %{ |
| 6517 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6518 %} | |
| 0 | 6519 ins_pipe( pipe_slow ); |
| 6520 %} | |
| 6521 | |
| 6522 // Store Float | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6523 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6524 predicate(UseSSE==0); |
| 6525 match(Set mem (StoreF mem src)); | |
| 6526 | |
| 6527 ins_cost(100); | |
| 6528 format %{ "FST_S $mem,$src" %} | |
| 6529 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6530 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6531 ins_pipe( fpu_mem_reg ); |
| 6532 %} | |
| 6533 | |
| 6534 // Store Float does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6535 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6536 predicate(UseSSE==0); |
| 6537 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6538 | |
| 6539 ins_cost(100); | |
| 6540 format %{ "FST_S $mem,$src\t# round" %} | |
| 6541 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6542 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6543 ins_pipe( fpu_mem_reg ); |
| 6544 %} | |
| 6545 | |
| 6546 // Store Float does rounding on x86 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6547 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6548 predicate(UseSSE<=1); |
| 6549 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6550 | |
| 6551 ins_cost(100); | |
| 6552 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6553 opcode(0xD9); /* D9 /2 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6554 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6555 ins_pipe( fpu_mem_reg ); |
| 6556 %} | |
| 6557 | |
| 6558 // Store immediate Float value (it is faster than store from FPU register) | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6559 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6560 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6561 match(Set mem (StoreF mem src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6562 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6563 ins_cost(50); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6564 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6565 opcode(0xC7); /* C7 /0 */ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6566 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6567 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6568 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6569 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6570 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 6571 // The instruction usage is guarded by predicate in operand immF(). |
| 6572 instruct storeF_imm( memory mem, immF src) %{ | |
| 6573 match(Set mem (StoreF mem src)); | |
| 6574 | |
| 6575 ins_cost(50); | |
| 6576 format %{ "MOV $mem,$src\t# store float" %} | |
| 6577 opcode(0xC7); /* C7 /0 */ | |
| 6578 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 6579 ins_pipe( ialu_mem_imm ); | |
| 6580 %} | |
| 6581 | |
| 6582 // Store Integer to stack slot | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6583 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 6584 match(Set dst src); |
| 6585 | |
| 6586 ins_cost(100); | |
| 6587 format %{ "MOV $dst,$src" %} | |
| 6588 opcode(0x89); | |
| 6589 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6590 ins_pipe( ialu_mem_reg ); | |
| 6591 %} | |
| 6592 | |
| 6593 // Store Integer to stack slot | |
| 6594 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 6595 match(Set dst src); | |
| 6596 | |
| 6597 ins_cost(100); | |
| 6598 format %{ "MOV $dst,$src" %} | |
| 6599 opcode(0x89); | |
| 6600 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6601 ins_pipe( ialu_mem_reg ); | |
| 6602 %} | |
| 6603 | |
| 6604 // Store Long to stack slot | |
| 6605 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 6606 match(Set dst src); | |
| 6607 | |
| 6608 ins_cost(200); | |
| 6609 format %{ "MOV $dst,$src.lo\n\t" | |
| 6610 "MOV $dst+4,$src.hi" %} | |
| 6611 opcode(0x89, 0x89); | |
| 6612 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 6613 ins_pipe( ialu_mem_long_reg ); | |
| 6614 %} | |
| 6615 | |
| 6616 //----------MemBar Instructions----------------------------------------------- | |
| 6617 // Memory barrier flavors | |
| 6618 | |
| 6619 instruct membar_acquire() %{ | |
| 6620 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6621 match(LoadFence); |
| 0 | 6622 ins_cost(400); |
| 6623 | |
| 6624 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6625 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6626 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6627 ins_pipe(empty); |
| 0 | 6628 %} |
| 6629 | |
| 6630 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6631 match(MemBarAcquireLock); |
| 0 | 6632 ins_cost(0); |
| 6633 | |
| 6634 size(0); | |
| 6635 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6636 ins_encode( ); | |
| 6637 ins_pipe(empty); | |
| 6638 %} | |
| 6639 | |
| 6640 instruct membar_release() %{ | |
| 6641 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6642 match(StoreFence); |
| 0 | 6643 ins_cost(400); |
| 6644 | |
| 6645 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6646 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6647 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6648 ins_pipe(empty); |
| 0 | 6649 %} |
| 6650 | |
| 6651 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6652 match(MemBarReleaseLock); |
| 0 | 6653 ins_cost(0); |
| 6654 | |
| 6655 size(0); | |
| 6656 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6657 ins_encode( ); | |
| 6658 ins_pipe(empty); | |
| 6659 %} | |
| 6660 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6661 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 6662 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6663 effect(KILL cr); |
| 0 | 6664 ins_cost(400); |
| 6665 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6666 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6667 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6668 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6669 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6670 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6671 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6672 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6673 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6674 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6675 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6676 %} |
| 0 | 6677 ins_pipe(pipe_slow); |
| 6678 %} | |
| 6679 | |
| 6680 instruct unnecessary_membar_volatile() %{ | |
| 6681 match(MemBarVolatile); | |
| 6682 predicate(Matcher::post_store_load_barrier(n)); | |
| 6683 ins_cost(0); | |
| 6684 | |
| 6685 size(0); | |
| 6686 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6687 ins_encode( ); | |
| 6688 ins_pipe(empty); | |
| 6689 %} | |
| 6690 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6691 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6692 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6693 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6694 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6695 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6696 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6697 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6698 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6699 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6700 |
| 0 | 6701 //----------Move Instructions-------------------------------------------------- |
| 6702 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 6703 match(Set dst (CastX2P src)); | |
| 6704 format %{ "# X2P $dst, $src" %} | |
| 6705 ins_encode( /*empty encoding*/ ); | |
| 6706 ins_cost(0); | |
| 6707 ins_pipe(empty); | |
| 6708 %} | |
| 6709 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6710 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 6711 match(Set dst (CastP2X src)); |
| 6712 ins_cost(50); | |
| 6713 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 6714 ins_encode( enc_Copy( dst, src) ); | |
| 6715 ins_pipe( ialu_reg_reg ); | |
| 6716 %} | |
| 6717 | |
| 6718 //----------Conditional Move--------------------------------------------------- | |
| 6719 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6720 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 6721 predicate(!VM_Version::supports_cmov() ); |
| 6722 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6723 ins_cost(200); | |
| 6724 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 6725 "MOV $dst,$src\n" | |
| 6726 "skip:" %} | |
| 6727 ins_encode %{ | |
| 6728 Label Lskip; | |
| 6729 // Invert sense of branch from sense of CMOV | |
| 6730 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6731 __ movl($dst$$Register, $src$$Register); | |
| 6732 __ bind(Lskip); | |
| 6733 %} | |
| 6734 ins_pipe( pipe_cmov_reg ); | |
| 6735 %} | |
| 6736 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6737 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 6738 predicate(!VM_Version::supports_cmov() ); |
| 6739 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6740 ins_cost(200); | |
| 6741 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 6742 "MOV $dst,$src\n" | |
| 6743 "skip:" %} | |
| 6744 ins_encode %{ | |
| 6745 Label Lskip; | |
| 6746 // Invert sense of branch from sense of CMOV | |
| 6747 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6748 __ movl($dst$$Register, $src$$Register); | |
| 6749 __ bind(Lskip); | |
| 6750 %} | |
| 6751 ins_pipe( pipe_cmov_reg ); | |
| 6752 %} | |
| 6753 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6754 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 6755 predicate(VM_Version::supports_cmov() ); |
| 6756 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6757 ins_cost(200); | |
| 6758 format %{ "CMOV$cop $dst,$src" %} | |
| 6759 opcode(0x0F,0x40); | |
| 6760 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6761 ins_pipe( pipe_cmov_reg ); | |
| 6762 %} | |
| 6763 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6764 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 6765 predicate(VM_Version::supports_cmov() ); |
| 6766 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6767 ins_cost(200); | |
| 6768 format %{ "CMOV$cop $dst,$src" %} | |
| 6769 opcode(0x0F,0x40); | |
| 6770 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6771 ins_pipe( pipe_cmov_reg ); | |
| 6772 %} | |
| 6773 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6774 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6775 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6776 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6777 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6778 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6779 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6780 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6781 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6782 |
| 0 | 6783 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6784 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6785 predicate(VM_Version::supports_cmov() ); |
| 6786 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6787 ins_cost(250); | |
| 6788 format %{ "CMOV$cop $dst,$src" %} | |
| 6789 opcode(0x0F,0x40); | |
| 6790 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6791 ins_pipe( pipe_cmov_mem ); | |
| 6792 %} | |
| 6793 | |
| 6794 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6795 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 6796 predicate(VM_Version::supports_cmov() ); |
| 6797 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6798 ins_cost(250); | |
| 6799 format %{ "CMOV$cop $dst,$src" %} | |
| 6800 opcode(0x0F,0x40); | |
| 6801 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6802 ins_pipe( pipe_cmov_mem ); | |
| 6803 %} | |
| 6804 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6805 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6806 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6807 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6808 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6809 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6810 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6811 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6812 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6813 |
| 0 | 6814 // Conditional move |
| 6815 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6816 predicate(VM_Version::supports_cmov() ); | |
| 6817 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6818 ins_cost(200); | |
| 6819 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6820 opcode(0x0F,0x40); | |
| 6821 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6822 ins_pipe( pipe_cmov_reg ); | |
| 6823 %} | |
| 6824 | |
| 6825 // Conditional move (non-P6 version) | |
| 6826 // Note: a CMoveP is generated for stubs and native wrappers | |
| 6827 // regardless of whether we are on a P6, so we | |
| 6828 // emulate a cmov here | |
| 6829 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6830 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6831 ins_cost(300); | |
| 6832 format %{ "Jn$cop skip\n\t" | |
| 6833 "MOV $dst,$src\t# pointer\n" | |
| 6834 "skip:" %} | |
| 6835 opcode(0x8b); | |
| 6836 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 6837 ins_pipe( pipe_cmov_reg ); | |
| 6838 %} | |
| 6839 | |
| 6840 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6841 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 6842 predicate(VM_Version::supports_cmov() ); |
| 6843 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6844 ins_cost(200); | |
| 6845 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6846 opcode(0x0F,0x40); | |
| 6847 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6848 ins_pipe( pipe_cmov_reg ); | |
| 6849 %} | |
| 6850 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6851 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6852 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6853 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6854 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6855 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6856 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6857 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6858 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6859 |
| 0 | 6860 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6861 // correctly meets the two pointer arguments; one is an incoming | |
| 6862 // register but the other is a memory operand. ALSO appears to | |
| 6863 // be buggy with implicit null checks. | |
| 6864 // | |
| 6865 //// Conditional move | |
| 6866 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 6867 // predicate(VM_Version::supports_cmov() ); | |
| 6868 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6869 // ins_cost(250); | |
| 6870 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6871 // opcode(0x0F,0x40); | |
| 6872 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6873 // ins_pipe( pipe_cmov_mem ); | |
| 6874 //%} | |
| 6875 // | |
| 6876 //// Conditional move | |
| 6877 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 6878 // predicate(VM_Version::supports_cmov() ); | |
| 6879 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6880 // ins_cost(250); | |
| 6881 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6882 // opcode(0x0F,0x40); | |
| 6883 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6884 // ins_pipe( pipe_cmov_mem ); | |
| 6885 //%} | |
| 6886 | |
| 6887 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6888 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 6889 predicate(UseSSE<=1); |
| 6890 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6891 ins_cost(200); | |
| 6892 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 6893 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6894 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6895 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6896 %} |
| 6897 | |
| 6898 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6899 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 6900 predicate(UseSSE==0); |
| 6901 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6902 ins_cost(200); | |
| 6903 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 6904 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6905 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6906 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6907 %} |
| 6908 | |
| 6909 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6910 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 6911 predicate(UseSSE<=1); |
| 6912 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6913 ins_cost(200); | |
| 6914 format %{ "Jn$cop skip\n\t" | |
| 6915 "MOV $dst,$src\t# double\n" | |
| 6916 "skip:" %} | |
| 6917 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6918 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6919 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6920 %} |
| 6921 | |
| 6922 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6923 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 6924 predicate(UseSSE==0); |
| 6925 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6926 ins_cost(200); | |
| 6927 format %{ "Jn$cop skip\n\t" | |
| 6928 "MOV $dst,$src\t# float\n" | |
| 6929 "skip:" %} | |
| 6930 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6931 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6932 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6933 %} |
| 6934 | |
| 6935 // No CMOVE with SSE/SSE2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6936 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 6937 predicate (UseSSE>=1); |
| 6938 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6939 ins_cost(200); | |
| 6940 format %{ "Jn$cop skip\n\t" | |
| 6941 "MOVSS $dst,$src\t# float\n" | |
| 6942 "skip:" %} | |
| 6943 ins_encode %{ | |
| 6944 Label skip; | |
| 6945 // Invert sense of branch from sense of CMOV | |
| 6946 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6947 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6948 __ bind(skip); | |
| 6949 %} | |
| 6950 ins_pipe( pipe_slow ); | |
| 6951 %} | |
| 6952 | |
| 6953 // No CMOVE with SSE/SSE2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6954 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 6955 predicate (UseSSE>=2); |
| 6956 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6957 ins_cost(200); | |
| 6958 format %{ "Jn$cop skip\n\t" | |
| 6959 "MOVSD $dst,$src\t# float\n" | |
| 6960 "skip:" %} | |
| 6961 ins_encode %{ | |
| 6962 Label skip; | |
| 6963 // Invert sense of branch from sense of CMOV | |
| 6964 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6965 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6966 __ bind(skip); | |
| 6967 %} | |
| 6968 ins_pipe( pipe_slow ); | |
| 6969 %} | |
| 6970 | |
| 6971 // unsigned version | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6972 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 6973 predicate (UseSSE>=1); |
| 6974 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6975 ins_cost(200); | |
| 6976 format %{ "Jn$cop skip\n\t" | |
| 6977 "MOVSS $dst,$src\t# float\n" | |
| 6978 "skip:" %} | |
| 6979 ins_encode %{ | |
| 6980 Label skip; | |
| 6981 // Invert sense of branch from sense of CMOV | |
| 6982 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6983 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6984 __ bind(skip); | |
| 6985 %} | |
| 6986 ins_pipe( pipe_slow ); | |
| 6987 %} | |
| 6988 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6989 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6990 predicate (UseSSE>=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6991 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6992 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6993 expand %{ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6994 fcmovF_regU(cop, cr, dst, src); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6995 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6996 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6997 |
| 0 | 6998 // unsigned version |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6999 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 7000 predicate (UseSSE>=2); |
| 7001 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7002 ins_cost(200); | |
| 7003 format %{ "Jn$cop skip\n\t" | |
| 7004 "MOVSD $dst,$src\t# float\n" | |
| 7005 "skip:" %} | |
| 7006 ins_encode %{ | |
| 7007 Label skip; | |
| 7008 // Invert sense of branch from sense of CMOV | |
| 7009 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7010 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7011 __ bind(skip); | |
| 7012 %} | |
| 7013 ins_pipe( pipe_slow ); | |
| 7014 %} | |
| 7015 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7016 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7017 predicate (UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7018 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7019 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7020 expand %{ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7021 fcmovD_regU(cop, cr, dst, src); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7022 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7023 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7024 |
| 0 | 7025 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7026 predicate(VM_Version::supports_cmov() ); | |
| 7027 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7028 ins_cost(200); | |
| 7029 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7030 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7031 opcode(0x0F,0x40); | |
| 7032 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7033 ins_pipe( pipe_cmov_reg_long ); | |
| 7034 %} | |
| 7035 | |
| 7036 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7037 predicate(VM_Version::supports_cmov() ); | |
| 7038 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7039 ins_cost(200); | |
| 7040 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7041 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7042 opcode(0x0F,0x40); | |
| 7043 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7044 ins_pipe( pipe_cmov_reg_long ); | |
| 7045 %} | |
| 7046 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7047 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7048 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7049 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7050 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7051 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7052 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7053 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7054 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7055 |
| 0 | 7056 //----------Arithmetic Instructions-------------------------------------------- |
| 7057 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 7058 |
| 0 | 7059 // Integer Addition Instructions |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7060 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7061 match(Set dst (AddI dst src)); |
| 7062 effect(KILL cr); | |
| 7063 | |
| 7064 size(2); | |
| 7065 format %{ "ADD $dst,$src" %} | |
| 7066 opcode(0x03); | |
| 7067 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7068 ins_pipe( ialu_reg_reg ); | |
| 7069 %} | |
| 7070 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7071 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7072 match(Set dst (AddI dst src)); |
| 7073 effect(KILL cr); | |
| 7074 | |
| 7075 format %{ "ADD $dst,$src" %} | |
| 7076 opcode(0x81, 0x00); /* /0 id */ | |
| 7077 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7078 ins_pipe( ialu_reg ); | |
| 7079 %} | |
| 7080 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7081 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7082 predicate(UseIncDec); |
| 7083 match(Set dst (AddI dst src)); | |
| 7084 effect(KILL cr); | |
| 7085 | |
| 7086 size(1); | |
| 7087 format %{ "INC $dst" %} | |
| 7088 opcode(0x40); /* */ | |
| 7089 ins_encode( Opc_plus( primary, dst ) ); | |
| 7090 ins_pipe( ialu_reg ); | |
| 7091 %} | |
| 7092 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7093 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7094 match(Set dst (AddI src0 src1)); |
| 7095 ins_cost(110); | |
| 7096 | |
| 7097 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7098 opcode(0x8D); /* 0x8D /r */ | |
| 7099 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7100 ins_pipe( ialu_reg_reg ); | |
| 7101 %} | |
| 7102 | |
| 7103 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7104 match(Set dst (AddP src0 src1)); | |
| 7105 ins_cost(110); | |
| 7106 | |
| 7107 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7108 opcode(0x8D); /* 0x8D /r */ | |
| 7109 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7110 ins_pipe( ialu_reg_reg ); | |
| 7111 %} | |
| 7112 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7113 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7114 predicate(UseIncDec); |
| 7115 match(Set dst (AddI dst src)); | |
| 7116 effect(KILL cr); | |
| 7117 | |
| 7118 size(1); | |
| 7119 format %{ "DEC $dst" %} | |
| 7120 opcode(0x48); /* */ | |
| 7121 ins_encode( Opc_plus( primary, dst ) ); | |
| 7122 ins_pipe( ialu_reg ); | |
| 7123 %} | |
| 7124 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7125 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7126 match(Set dst (AddP dst src)); |
| 7127 effect(KILL cr); | |
| 7128 | |
| 7129 size(2); | |
| 7130 format %{ "ADD $dst,$src" %} | |
| 7131 opcode(0x03); | |
| 7132 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7133 ins_pipe( ialu_reg_reg ); | |
| 7134 %} | |
| 7135 | |
| 7136 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7137 match(Set dst (AddP dst src)); | |
| 7138 effect(KILL cr); | |
| 7139 | |
| 7140 format %{ "ADD $dst,$src" %} | |
| 7141 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7142 // ins_encode( RegImm( dst, src) ); | |
| 7143 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7144 ins_pipe( ialu_reg ); | |
| 7145 %} | |
| 7146 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7147 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7148 match(Set dst (AddI dst (LoadI src))); |
| 7149 effect(KILL cr); | |
| 7150 | |
| 7151 ins_cost(125); | |
| 7152 format %{ "ADD $dst,$src" %} | |
| 7153 opcode(0x03); | |
| 7154 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7155 ins_pipe( ialu_reg_mem ); | |
| 7156 %} | |
| 7157 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7158 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7159 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7160 effect(KILL cr); | |
| 7161 | |
| 7162 ins_cost(150); | |
| 7163 format %{ "ADD $dst,$src" %} | |
| 7164 opcode(0x01); /* Opcode 01 /r */ | |
| 7165 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7166 ins_pipe( ialu_mem_reg ); | |
| 7167 %} | |
| 7168 | |
| 7169 // Add Memory with Immediate | |
| 7170 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7171 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7172 effect(KILL cr); | |
| 7173 | |
| 7174 ins_cost(125); | |
| 7175 format %{ "ADD $dst,$src" %} | |
| 7176 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7177 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7178 ins_pipe( ialu_mem_imm ); | |
| 7179 %} | |
| 7180 | |
| 7181 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7182 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7183 effect(KILL cr); | |
| 7184 | |
| 7185 ins_cost(125); | |
| 7186 format %{ "INC $dst" %} | |
| 7187 opcode(0xFF); /* Opcode FF /0 */ | |
| 7188 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7189 ins_pipe( ialu_mem_imm ); | |
| 7190 %} | |
| 7191 | |
| 7192 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7193 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7194 effect(KILL cr); | |
| 7195 | |
| 7196 ins_cost(125); | |
| 7197 format %{ "DEC $dst" %} | |
| 7198 opcode(0xFF); /* Opcode FF /1 */ | |
| 7199 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7200 ins_pipe( ialu_mem_imm ); | |
| 7201 %} | |
| 7202 | |
| 7203 | |
| 7204 instruct checkCastPP( eRegP dst ) %{ | |
| 7205 match(Set dst (CheckCastPP dst)); | |
| 7206 | |
| 7207 size(0); | |
| 7208 format %{ "#checkcastPP of $dst" %} | |
| 7209 ins_encode( /*empty encoding*/ ); | |
| 7210 ins_pipe( empty ); | |
| 7211 %} | |
| 7212 | |
| 7213 instruct castPP( eRegP dst ) %{ | |
| 7214 match(Set dst (CastPP dst)); | |
| 7215 format %{ "#castPP of $dst" %} | |
| 7216 ins_encode( /*empty encoding*/ ); | |
| 7217 ins_pipe( empty ); | |
| 7218 %} | |
| 7219 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7220 instruct castII( rRegI dst ) %{ |
| 0 | 7221 match(Set dst (CastII dst)); |
| 7222 format %{ "#castII of $dst" %} | |
| 7223 ins_encode( /*empty encoding*/ ); | |
| 7224 ins_cost(0); | |
| 7225 ins_pipe( empty ); | |
| 7226 %} | |
| 7227 | |
| 7228 | |
| 7229 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7230 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7231 match(Set dst (LoadPLocked mem)); | |
| 7232 | |
| 7233 ins_cost(125); | |
| 7234 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7235 opcode(0x8B); | |
| 7236 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7237 ins_pipe( ialu_reg_mem ); | |
| 7238 %} | |
| 7239 | |
| 7240 // Conditional-store of the updated heap-top. | |
| 7241 // Used during allocation of the shared heap. | |
| 7242 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7243 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7244 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7245 // EAX is killed if there is contention, but then it's also unused. | |
| 7246 // In the common case of no contention, EAX holds the new oop address. | |
| 7247 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7248 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7249 ins_pipe( pipe_cmpxchg ); | |
| 7250 %} | |
| 7251 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7252 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7253 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7254 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7255 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7256 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7257 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7258 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7259 ins_pipe( pipe_cmpxchg ); |
| 7260 %} | |
| 7261 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7262 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7263 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7264 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7265 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7266 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7267 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7268 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7269 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7270 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7271 ins_encode %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7272 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7273 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7274 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7275 // our register encoding uses rbx. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7276 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7277 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7278 __ lock(); |
| 624 | 7279 __ cmpxchg8($mem$$Address); |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7280 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7281 %} |
| 0 | 7282 ins_pipe( pipe_cmpxchg ); |
| 7283 %} | |
| 7284 | |
| 7285 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7286 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7287 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7288 predicate(VM_Version::supports_cx8()); |
| 0 | 7289 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7290 effect(KILL cr, KILL oldval); | |
| 7291 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7292 "MOV $res,0\n\t" | |
| 7293 "JNE,s fail\n\t" | |
| 7294 "MOV $res,1\n" | |
| 7295 "fail:" %} | |
| 7296 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7297 enc_flags_ne_to_boolean(res) ); | |
| 7298 ins_pipe( pipe_cmpxchg ); | |
| 7299 %} | |
| 7300 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7301 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7302 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7303 effect(KILL cr, KILL oldval); | |
| 7304 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7305 "MOV $res,0\n\t" | |
| 7306 "JNE,s fail\n\t" | |
| 7307 "MOV $res,1\n" | |
| 7308 "fail:" %} | |
| 7309 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7310 ins_pipe( pipe_cmpxchg ); | |
| 7311 %} | |
| 7312 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7313 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7314 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7315 effect(KILL cr, KILL oldval); | |
| 7316 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7317 "MOV $res,0\n\t" | |
| 7318 "JNE,s fail\n\t" | |
| 7319 "MOV $res,1\n" | |
| 7320 "fail:" %} | |
| 7321 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7322 ins_pipe( pipe_cmpxchg ); | |
| 7323 %} | |
| 7324 | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7325 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7326 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7327 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7328 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7329 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7330 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7331 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7332 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7333 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7334 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7335 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7336 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7337 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7338 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7339 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7340 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7341 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7342 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7343 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7344 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7345 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7346 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7347 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7348 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7349 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7350 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7351 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7352 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7353 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7354 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7355 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7356 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7357 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7358 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7359 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7360 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7361 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7362 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7363 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7364 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7365 |
| 0 | 7366 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7367 |
| 0 | 7368 // Integer Subtraction Instructions |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7369 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7370 match(Set dst (SubI dst src)); |
| 7371 effect(KILL cr); | |
| 7372 | |
| 7373 size(2); | |
| 7374 format %{ "SUB $dst,$src" %} | |
| 7375 opcode(0x2B); | |
| 7376 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7377 ins_pipe( ialu_reg_reg ); | |
| 7378 %} | |
| 7379 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7380 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7381 match(Set dst (SubI dst src)); |
| 7382 effect(KILL cr); | |
| 7383 | |
| 7384 format %{ "SUB $dst,$src" %} | |
| 7385 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7386 // ins_encode( RegImm( dst, src) ); | |
| 7387 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7388 ins_pipe( ialu_reg ); | |
| 7389 %} | |
| 7390 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7391 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7392 match(Set dst (SubI dst (LoadI src))); |
| 7393 effect(KILL cr); | |
| 7394 | |
| 7395 ins_cost(125); | |
| 7396 format %{ "SUB $dst,$src" %} | |
| 7397 opcode(0x2B); | |
| 7398 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7399 ins_pipe( ialu_reg_mem ); | |
| 7400 %} | |
| 7401 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7402 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7403 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7404 effect(KILL cr); | |
| 7405 | |
| 7406 ins_cost(150); | |
| 7407 format %{ "SUB $dst,$src" %} | |
| 7408 opcode(0x29); /* Opcode 29 /r */ | |
| 7409 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7410 ins_pipe( ialu_mem_reg ); | |
| 7411 %} | |
| 7412 | |
| 7413 // Subtract from a pointer | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7414 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7415 match(Set dst (AddP dst (SubI zero src))); |
| 7416 effect(KILL cr); | |
| 7417 | |
| 7418 size(2); | |
| 7419 format %{ "SUB $dst,$src" %} | |
| 7420 opcode(0x2B); | |
| 7421 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7422 ins_pipe( ialu_reg_reg ); | |
| 7423 %} | |
| 7424 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7425 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7426 match(Set dst (SubI zero dst)); |
| 7427 effect(KILL cr); | |
| 7428 | |
| 7429 size(2); | |
| 7430 format %{ "NEG $dst" %} | |
| 7431 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7432 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7433 ins_pipe( ialu_reg ); | |
| 7434 %} | |
| 7435 | |
| 7436 //----------Multiplication/Division Instructions------------------------------- | |
| 7437 // Integer Multiplication Instructions | |
| 7438 // Multiply Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7439 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7440 match(Set dst (MulI dst src)); |
| 7441 effect(KILL cr); | |
| 7442 | |
| 7443 size(3); | |
| 7444 ins_cost(300); | |
| 7445 format %{ "IMUL $dst,$src" %} | |
| 7446 opcode(0xAF, 0x0F); | |
| 7447 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7448 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7449 %} | |
| 7450 | |
| 7451 // Multiply 32-bit Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7452 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7453 match(Set dst (MulI src imm)); |
| 7454 effect(KILL cr); | |
| 7455 | |
| 7456 ins_cost(300); | |
| 7457 format %{ "IMUL $dst,$src,$imm" %} | |
| 7458 opcode(0x69); /* 69 /r id */ | |
| 7459 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7460 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7461 %} | |
| 7462 | |
| 7463 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7464 match(Set dst src); | |
| 7465 effect(KILL cr); | |
| 7466 | |
| 7467 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7468 ins_cost(250); | |
| 7469 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7470 opcode(0xB8); | |
| 7471 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7472 ins_pipe( ialu_reg_fat ); | |
| 7473 %} | |
| 7474 | |
| 7475 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7476 // (special case for shift by 32) | |
| 7477 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7478 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7479 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7480 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7481 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7482 effect(USE src1, KILL cr); | |
| 7483 | |
| 7484 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7485 ins_cost(0*100 + 1*400 - 150); | |
| 7486 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7487 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7488 ins_pipe( pipe_slow ); | |
| 7489 %} | |
| 7490 | |
| 7491 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7492 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7493 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7494 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7495 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7496 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7497 effect(USE src1, KILL cr); | |
| 7498 | |
| 7499 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7500 ins_cost(1*100 + 1*400 - 150); | |
| 7501 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7502 "SAR EDX,$cnt-32" %} | |
| 7503 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7504 ins_pipe( pipe_slow ); | |
| 7505 %} | |
| 7506 | |
| 7507 // Multiply Memory 32-bit Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7508 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7509 match(Set dst (MulI (LoadI src) imm)); |
| 7510 effect(KILL cr); | |
| 7511 | |
| 7512 ins_cost(300); | |
| 7513 format %{ "IMUL $dst,$src,$imm" %} | |
| 7514 opcode(0x69); /* 69 /r id */ | |
| 7515 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7516 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7517 %} | |
| 7518 | |
| 7519 // Multiply Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7520 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7521 match(Set dst (MulI dst (LoadI src))); |
| 7522 effect(KILL cr); | |
| 7523 | |
| 7524 ins_cost(350); | |
| 7525 format %{ "IMUL $dst,$src" %} | |
| 7526 opcode(0xAF, 0x0F); | |
| 7527 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7528 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7529 %} | |
| 7530 | |
| 7531 // Multiply Register Int to Long | |
| 7532 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7533 // Basic Idea: long = (long)int * (long)int | |
| 7534 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7535 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7536 | |
| 7537 ins_cost(300); | |
| 7538 format %{ "IMUL $dst,$src1" %} | |
| 7539 | |
| 7540 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7541 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7542 %} | |
| 7543 | |
| 7544 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7545 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7546 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7547 effect(KILL flags); | |
| 7548 | |
| 7549 ins_cost(300); | |
| 7550 format %{ "MUL $dst,$src1" %} | |
| 7551 | |
| 7552 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7553 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7554 %} | |
| 7555 | |
| 7556 // Multiply Register Long | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7557 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7558 match(Set dst (MulL dst src)); |
| 7559 effect(KILL cr, TEMP tmp); | |
| 7560 ins_cost(4*100+3*400); | |
| 7561 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7562 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7563 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7564 "IMUL $tmp,EDX\n\t" | |
| 7565 "MOV EDX,$src.hi\n\t" | |
| 7566 "IMUL EDX,EAX\n\t" | |
| 7567 "ADD $tmp,EDX\n\t" | |
| 7568 "MUL EDX:EAX,$src.lo\n\t" | |
| 7569 "ADD EDX,$tmp" %} | |
| 7570 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 7571 ins_pipe( pipe_slow ); | |
| 7572 %} | |
| 7573 | |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7574 // Multiply Register Long where the left operand's high 32 bits are zero |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7575 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7576 predicate(is_operand_hi32_zero(n->in(1))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7577 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7578 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7579 ins_cost(2*100+2*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7580 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7581 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7582 format %{ "MOV $tmp,$src.hi\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7583 "IMUL $tmp,EAX\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7584 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7585 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7586 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7587 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7588 __ imull($tmp$$Register, rax); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7589 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7590 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7591 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7592 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7593 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7594 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7595 // Multiply Register Long where the right operand's high 32 bits are zero |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7596 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7597 predicate(is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7598 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7599 effect(KILL cr, TEMP tmp); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7600 ins_cost(2*100+2*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7601 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7602 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7603 format %{ "MOV $tmp,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7604 "IMUL $tmp,EDX\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7605 "MUL EDX:EAX,$src.lo\n\t" |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7606 "ADD EDX,$tmp" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7607 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7608 __ movl($tmp$$Register, $src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7609 __ imull($tmp$$Register, rdx); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7610 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7611 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7612 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7613 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7614 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7615 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7616 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7617 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7618 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7619 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7620 effect(KILL cr); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7621 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7622 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7623 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7624 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7625 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7626 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7627 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7628 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7629 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
7630 |
| 0 | 7631 // Multiply Register Long by small constant |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7632 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7633 match(Set dst (MulL dst src)); |
| 7634 effect(KILL cr, TEMP tmp); | |
| 7635 ins_cost(2*100+2*400); | |
| 7636 size(12); | |
| 7637 // Basic idea: lo(result) = lo(src * EAX) | |
| 7638 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 7639 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 7640 "MOV EDX,$src\n\t" | |
| 7641 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 7642 "ADD EDX,$tmp" %} | |
| 7643 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 7644 ins_pipe( pipe_slow ); | |
| 7645 %} | |
| 7646 | |
| 7647 // Integer DIV with Register | |
| 7648 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7649 match(Set rax (DivI rax div)); | |
| 7650 effect(KILL rdx, KILL cr); | |
| 7651 size(26); | |
| 7652 ins_cost(30*100+10*100); | |
| 7653 format %{ "CMP EAX,0x80000000\n\t" | |
| 7654 "JNE,s normal\n\t" | |
| 7655 "XOR EDX,EDX\n\t" | |
| 7656 "CMP ECX,-1\n\t" | |
| 7657 "JE,s done\n" | |
| 7658 "normal: CDQ\n\t" | |
| 7659 "IDIV $div\n\t" | |
| 7660 "done:" %} | |
| 7661 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7662 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7663 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7664 %} | |
| 7665 | |
| 7666 // Divide Register Long | |
| 7667 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7668 match(Set dst (DivL src1 src2)); | |
| 7669 effect( KILL cr, KILL cx, KILL bx ); | |
| 7670 ins_cost(10000); | |
| 7671 format %{ "PUSH $src1.hi\n\t" | |
| 7672 "PUSH $src1.lo\n\t" | |
| 7673 "PUSH $src2.hi\n\t" | |
| 7674 "PUSH $src2.lo\n\t" | |
| 7675 "CALL SharedRuntime::ldiv\n\t" | |
| 7676 "ADD ESP,16" %} | |
| 7677 ins_encode( long_div(src1,src2) ); | |
| 7678 ins_pipe( pipe_slow ); | |
| 7679 %} | |
| 7680 | |
| 7681 // Integer DIVMOD with Register, both quotient and mod results | |
| 7682 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7683 match(DivModI rax div); | |
| 7684 effect(KILL cr); | |
| 7685 size(26); | |
| 7686 ins_cost(30*100+10*100); | |
| 7687 format %{ "CMP EAX,0x80000000\n\t" | |
| 7688 "JNE,s normal\n\t" | |
| 7689 "XOR EDX,EDX\n\t" | |
| 7690 "CMP ECX,-1\n\t" | |
| 7691 "JE,s done\n" | |
| 7692 "normal: CDQ\n\t" | |
| 7693 "IDIV $div\n\t" | |
| 7694 "done:" %} | |
| 7695 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7696 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7697 ins_pipe( pipe_slow ); | |
| 7698 %} | |
| 7699 | |
| 7700 // Integer MOD with Register | |
| 7701 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 7702 match(Set rdx (ModI rax div)); | |
| 7703 effect(KILL rax, KILL cr); | |
| 7704 | |
| 7705 size(26); | |
| 7706 ins_cost(300); | |
| 7707 format %{ "CDQ\n\t" | |
| 7708 "IDIV $div" %} | |
| 7709 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7710 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7711 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7712 %} | |
| 7713 | |
| 7714 // Remainder Register Long | |
| 7715 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7716 match(Set dst (ModL src1 src2)); | |
| 7717 effect( KILL cr, KILL cx, KILL bx ); | |
| 7718 ins_cost(10000); | |
| 7719 format %{ "PUSH $src1.hi\n\t" | |
| 7720 "PUSH $src1.lo\n\t" | |
| 7721 "PUSH $src2.hi\n\t" | |
| 7722 "PUSH $src2.lo\n\t" | |
| 7723 "CALL SharedRuntime::lrem\n\t" | |
| 7724 "ADD ESP,16" %} | |
| 7725 ins_encode( long_mod(src1,src2) ); | |
| 7726 ins_pipe( pipe_slow ); | |
| 7727 %} | |
| 7728 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7729 // Divide Register Long (no special case since divisor != -1) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7730 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7731 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7732 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7733 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7734 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 7735 "XOR $tmp2,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7736 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7737 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7738 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7739 "MOV EAX,EDX\n\t" |
| 1920 | 7740 "MOV EDX,0\n\t" |
| 7741 "JLE,s pos\n\t" | |
| 7742 "LNEG EAX : $tmp2\n\t" | |
| 7743 "DIV $tmp # unsigned division\n\t" | |
| 7744 "XCHG EAX,$tmp2\n\t" | |
| 7745 "DIV $tmp\n\t" | |
| 7746 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7747 "JMP,s done\n" |
| 1920 | 7748 "pos:\n\t" |
| 7749 "DIV $tmp\n\t" | |
| 7750 "XCHG EAX,$tmp2\n" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7751 "fast:\n\t" |
| 1920 | 7752 "DIV $tmp\n" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7753 "done:\n\t" |
| 1920 | 7754 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7755 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7756 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7757 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7758 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7759 int pcon = (con > 0) ? con : -con; |
| 1920 | 7760 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7761 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7762 __ movl($tmp$$Register, pcon); |
| 1920 | 7763 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7764 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7765 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7766 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7767 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7768 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7769 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7770 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7771 | |
| 7772 // Negative dividend. | |
| 7773 // convert value to positive to use unsigned division | |
| 7774 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7775 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7776 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 7777 __ divl($tmp$$Register); |
| 7778 // revert result back to negative | |
| 7779 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7780 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7781 |
| 1920 | 7782 __ bind(Lpos); |
| 7783 __ divl($tmp$$Register); // Use unsigned division | |
| 7784 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 7785 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 7786 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7787 __ bind(Lfast); |
| 1920 | 7788 // fast path: src is positive |
| 7789 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7790 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7791 __ bind(Ldone); |
| 1920 | 7792 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7793 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7794 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7795 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7796 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7797 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7798 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7799 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7800 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7801 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7802 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7803 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7804 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7805 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7806 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7807 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7808 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7809 "MOV EAX,EDX\n\t" |
| 1920 | 7810 "MOV EDX,0\n\t" |
| 7811 "JLE,s pos\n\t" | |
| 7812 "LNEG EAX : $tmp2\n\t" | |
| 7813 "DIV $tmp # unsigned division\n\t" | |
| 7814 "MOV EAX,$tmp2\n\t" | |
| 7815 "DIV $tmp\n\t" | |
| 7816 "NEG EDX\n\t" | |
| 7817 "JMP,s done\n" | |
| 7818 "pos:\n\t" | |
| 7819 "DIV $tmp\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7820 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7821 "fast:\n\t" |
| 1920 | 7822 "DIV $tmp\n" |
| 7823 "done:\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7824 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7825 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7826 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7827 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7828 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7829 int pcon = (con > 0) ? con : -con; |
| 1920 | 7830 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7831 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7832 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7833 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7834 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7835 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7836 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7837 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7838 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7839 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7840 | |
| 7841 // Negative dividend. | |
| 7842 // convert value to positive to use unsigned division | |
| 7843 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7844 __ divl($tmp$$Register); | |
| 7845 __ movl($dst$$Register, $tmp2$$Register); | |
| 7846 __ divl($tmp$$Register); | |
| 7847 // revert remainder back to negative | |
| 7848 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 7849 __ jmpb(Ldone); | |
| 7850 | |
| 7851 __ bind(Lpos); | |
| 7852 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7853 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7854 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7855 __ bind(Lfast); |
| 1920 | 7856 // fast path: src is positive |
| 7857 __ divl($tmp$$Register); | |
| 7858 | |
| 7859 __ bind(Ldone); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7860 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7861 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7862 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7863 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7864 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7865 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7866 |
| 0 | 7867 // Integer Shift Instructions |
| 7868 // Shift Left by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7869 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7870 match(Set dst (LShiftI dst shift)); |
| 7871 effect(KILL cr); | |
| 7872 | |
| 7873 size(2); | |
| 7874 format %{ "SHL $dst,$shift" %} | |
| 7875 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7876 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7877 ins_pipe( ialu_reg ); | |
| 7878 %} | |
| 7879 | |
| 7880 // Shift Left by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7881 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7882 match(Set dst (LShiftI dst shift)); |
| 7883 effect(KILL cr); | |
| 7884 | |
| 7885 size(3); | |
| 7886 format %{ "SHL $dst,$shift" %} | |
| 7887 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7888 ins_encode( RegOpcImm( dst, shift) ); | |
| 7889 ins_pipe( ialu_reg ); | |
| 7890 %} | |
| 7891 | |
| 7892 // Shift Left by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7893 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7894 match(Set dst (LShiftI dst shift)); |
| 7895 effect(KILL cr); | |
| 7896 | |
| 7897 size(2); | |
| 7898 format %{ "SHL $dst,$shift" %} | |
| 7899 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7900 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7901 ins_pipe( ialu_reg_reg ); | |
| 7902 %} | |
| 7903 | |
| 7904 // Arithmetic shift right by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7905 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7906 match(Set dst (RShiftI dst shift)); |
| 7907 effect(KILL cr); | |
| 7908 | |
| 7909 size(2); | |
| 7910 format %{ "SAR $dst,$shift" %} | |
| 7911 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7912 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7913 ins_pipe( ialu_reg ); | |
| 7914 %} | |
| 7915 | |
| 7916 // Arithmetic shift right by one | |
| 7917 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 7918 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7919 effect(KILL cr); | |
| 7920 format %{ "SAR $dst,$shift" %} | |
| 7921 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7922 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 7923 ins_pipe( ialu_mem_imm ); | |
| 7924 %} | |
| 7925 | |
| 7926 // Arithmetic Shift Right by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7927 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7928 match(Set dst (RShiftI dst shift)); |
| 7929 effect(KILL cr); | |
| 7930 | |
| 7931 size(3); | |
| 7932 format %{ "SAR $dst,$shift" %} | |
| 7933 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7934 ins_encode( RegOpcImm( dst, shift ) ); | |
| 7935 ins_pipe( ialu_mem_imm ); | |
| 7936 %} | |
| 7937 | |
| 7938 // Arithmetic Shift Right by 8-bit immediate | |
| 7939 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 7940 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7941 effect(KILL cr); | |
| 7942 | |
| 7943 format %{ "SAR $dst,$shift" %} | |
| 7944 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7945 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 7946 ins_pipe( ialu_mem_imm ); | |
| 7947 %} | |
| 7948 | |
| 7949 // Arithmetic Shift Right by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7950 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7951 match(Set dst (RShiftI dst shift)); |
| 7952 effect(KILL cr); | |
| 7953 | |
| 7954 size(2); | |
| 7955 format %{ "SAR $dst,$shift" %} | |
| 7956 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7957 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7958 ins_pipe( ialu_reg_reg ); | |
| 7959 %} | |
| 7960 | |
| 7961 // Logical shift right by one | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7962 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7963 match(Set dst (URShiftI dst shift)); |
| 7964 effect(KILL cr); | |
| 7965 | |
| 7966 size(2); | |
| 7967 format %{ "SHR $dst,$shift" %} | |
| 7968 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7969 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7970 ins_pipe( ialu_reg ); | |
| 7971 %} | |
| 7972 | |
| 7973 // Logical Shift Right by 8-bit immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7974 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7975 match(Set dst (URShiftI dst shift)); |
| 7976 effect(KILL cr); | |
| 7977 | |
| 7978 size(3); | |
| 7979 format %{ "SHR $dst,$shift" %} | |
| 7980 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7981 ins_encode( RegOpcImm( dst, shift) ); | |
| 7982 ins_pipe( ialu_reg ); | |
| 7983 %} | |
| 7984 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7985 |
| 0 | 7986 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 7987 // This idiom is used by the compiler for the i2b bytecode. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7988 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 7989 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 7990 | |
| 7991 size(3); | |
| 7992 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 7993 ins_encode %{ |
| 7994 __ movsbl($dst$$Register, $src$$Register); | |
| 7995 %} | |
| 7996 ins_pipe(ialu_reg_reg); | |
| 0 | 7997 %} |
| 7998 | |
| 7999 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8000 // This idiom is used by the compiler the i2s bytecode. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8001 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8002 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8003 | |
| 8004 size(3); | |
| 8005 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8006 ins_encode %{ |
| 8007 __ movswl($dst$$Register, $src$$Register); | |
| 8008 %} | |
| 8009 ins_pipe(ialu_reg_reg); | |
| 0 | 8010 %} |
| 8011 | |
| 8012 | |
| 8013 // Logical Shift Right by variable | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8014 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8015 match(Set dst (URShiftI dst shift)); |
| 8016 effect(KILL cr); | |
| 8017 | |
| 8018 size(2); | |
| 8019 format %{ "SHR $dst,$shift" %} | |
| 8020 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8021 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8022 ins_pipe( ialu_reg_reg ); | |
| 8023 %} | |
| 8024 | |
| 8025 | |
| 8026 //----------Logical Instructions----------------------------------------------- | |
| 8027 //----------Integer Logical Instructions--------------------------------------- | |
| 8028 // And Instructions | |
| 8029 // And Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8030 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8031 match(Set dst (AndI dst src)); |
| 8032 effect(KILL cr); | |
| 8033 | |
| 8034 size(2); | |
| 8035 format %{ "AND $dst,$src" %} | |
| 8036 opcode(0x23); | |
| 8037 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8038 ins_pipe( ialu_reg_reg ); | |
| 8039 %} | |
| 8040 | |
| 8041 // And Register with Immediate | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8042 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8043 match(Set dst (AndI dst src)); |
| 8044 effect(KILL cr); | |
| 8045 | |
| 8046 format %{ "AND $dst,$src" %} | |
| 8047 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8048 // ins_encode( RegImm( dst, src) ); | |
| 8049 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8050 ins_pipe( ialu_reg ); | |
| 8051 %} | |
| 8052 | |
| 8053 // And Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8054 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8055 match(Set dst (AndI dst (LoadI src))); |
| 8056 effect(KILL cr); | |
| 8057 | |
| 8058 ins_cost(125); | |
| 8059 format %{ "AND $dst,$src" %} | |
| 8060 opcode(0x23); | |
| 8061 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8062 ins_pipe( ialu_reg_mem ); | |
| 8063 %} | |
| 8064 | |
| 8065 // And Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8066 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8067 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8068 effect(KILL cr); | |
| 8069 | |
| 8070 ins_cost(150); | |
| 8071 format %{ "AND $dst,$src" %} | |
| 8072 opcode(0x21); /* Opcode 21 /r */ | |
| 8073 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8074 ins_pipe( ialu_mem_reg ); | |
| 8075 %} | |
| 8076 | |
| 8077 // And Memory with Immediate | |
| 8078 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8079 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8080 effect(KILL cr); | |
| 8081 | |
| 8082 ins_cost(125); | |
| 8083 format %{ "AND $dst,$src" %} | |
| 8084 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8085 // ins_encode( MemImm( dst, src) ); | |
| 8086 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8087 ins_pipe( ialu_mem_imm ); | |
| 8088 %} | |
| 8089 | |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8090 // BMI1 instructions |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8091 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8092 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8093 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8094 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8095 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8096 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8097 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8098 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8099 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8100 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8101 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8102 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8103 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8104 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8105 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8106 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8107 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8108 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8109 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8110 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8111 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8112 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8113 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8114 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8115 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8116 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8117 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8118 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8119 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8120 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8121 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8122 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8123 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8124 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8125 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8126 __ blsil($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8127 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8128 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8129 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8130 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8131 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8132 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8133 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8134 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8135 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8136 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8137 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8138 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8139 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8140 __ blsil($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8141 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8142 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8143 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8144 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8145 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8146 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8147 match(Set dst (XorI (AddI src minus_1) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8148 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8149 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8150 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8151 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8152 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8153 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8154 __ blsmskl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8155 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8156 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8157 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8158 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8159 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8160 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8161 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8162 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8163 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8164 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8165 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8166 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8167 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8168 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8169 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8170 __ blsmskl($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8171 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8172 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8173 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8174 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8175 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8176 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8177 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8178 match(Set dst (AndI (AddI src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8179 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8180 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8181 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8182 format %{ "BLSRL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8183 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8184 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8185 __ blsrl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8186 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8187 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8188 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8189 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8190 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8191 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8192 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8193 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8194 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8195 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8196 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8197 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8198 format %{ "BLSRL $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8199 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8200 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8201 __ blsrl($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8202 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8203 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8204 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8205 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8206 |
| 0 | 8207 // Or Instructions |
| 8208 // Or Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8209 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8210 match(Set dst (OrI dst src)); |
| 8211 effect(KILL cr); | |
| 8212 | |
| 8213 size(2); | |
| 8214 format %{ "OR $dst,$src" %} | |
| 8215 opcode(0x0B); | |
| 8216 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8217 ins_pipe( ialu_reg_reg ); | |
| 8218 %} | |
| 8219 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8220 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8221 match(Set dst (OrI dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8222 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8223 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8224 size(2); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8225 format %{ "OR $dst,$src" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8226 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8227 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8228 ins_pipe( ialu_reg_reg ); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8229 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8230 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8231 |
| 0 | 8232 // Or Register with Immediate |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8233 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8234 match(Set dst (OrI dst src)); |
| 8235 effect(KILL cr); | |
| 8236 | |
| 8237 format %{ "OR $dst,$src" %} | |
| 8238 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8239 // ins_encode( RegImm( dst, src) ); | |
| 8240 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8241 ins_pipe( ialu_reg ); | |
| 8242 %} | |
| 8243 | |
| 8244 // Or Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8245 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8246 match(Set dst (OrI dst (LoadI src))); |
| 8247 effect(KILL cr); | |
| 8248 | |
| 8249 ins_cost(125); | |
| 8250 format %{ "OR $dst,$src" %} | |
| 8251 opcode(0x0B); | |
| 8252 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8253 ins_pipe( ialu_reg_mem ); | |
| 8254 %} | |
| 8255 | |
| 8256 // Or Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8257 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8258 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8259 effect(KILL cr); | |
| 8260 | |
| 8261 ins_cost(150); | |
| 8262 format %{ "OR $dst,$src" %} | |
| 8263 opcode(0x09); /* Opcode 09 /r */ | |
| 8264 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8265 ins_pipe( ialu_mem_reg ); | |
| 8266 %} | |
| 8267 | |
| 8268 // Or Memory with Immediate | |
| 8269 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8270 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8271 effect(KILL cr); | |
| 8272 | |
| 8273 ins_cost(125); | |
| 8274 format %{ "OR $dst,$src" %} | |
| 8275 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8276 // ins_encode( MemImm( dst, src) ); | |
| 8277 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8278 ins_pipe( ialu_mem_imm ); | |
| 8279 %} | |
| 8280 | |
| 8281 // ROL/ROR | |
| 8282 // ROL expand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8283 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8284 effect(USE_DEF dst, USE shift, KILL cr); |
| 8285 | |
| 8286 format %{ "ROL $dst, $shift" %} | |
| 8287 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8288 ins_encode( OpcP, RegOpc( dst )); | |
| 8289 ins_pipe( ialu_reg ); | |
| 8290 %} | |
| 8291 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8292 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8293 effect(USE_DEF dst, USE shift, KILL cr); |
| 8294 | |
| 8295 format %{ "ROL $dst, $shift" %} | |
| 8296 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8297 ins_encode( RegOpcImm(dst, shift) ); | |
| 8298 ins_pipe(ialu_reg); | |
| 8299 %} | |
| 8300 | |
| 8301 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8302 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8303 | |
| 8304 format %{ "ROL $dst, $shift" %} | |
| 8305 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8306 ins_encode(OpcP, RegOpc(dst)); | |
| 8307 ins_pipe( ialu_reg_reg ); | |
| 8308 %} | |
| 8309 // end of ROL expand | |
| 8310 | |
| 8311 // ROL 32bit by one once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8312 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8313 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8314 | |
| 8315 expand %{ | |
| 8316 rolI_eReg_imm1(dst, lshift, cr); | |
| 8317 %} | |
| 8318 %} | |
| 8319 | |
| 8320 // ROL 32bit var by imm8 once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8321 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8322 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8323 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8324 | |
| 8325 expand %{ | |
| 8326 rolI_eReg_imm8(dst, lshift, cr); | |
| 8327 %} | |
| 8328 %} | |
| 8329 | |
| 8330 // ROL 32bit var by var once | |
| 8331 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8332 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8333 | |
| 8334 expand %{ | |
| 8335 rolI_eReg_CL(dst, shift, cr); | |
| 8336 %} | |
| 8337 %} | |
| 8338 | |
| 8339 // ROL 32bit var by var once | |
| 8340 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8341 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8342 | |
| 8343 expand %{ | |
| 8344 rolI_eReg_CL(dst, shift, cr); | |
| 8345 %} | |
| 8346 %} | |
| 8347 | |
| 8348 // ROR expand | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8349 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8350 effect(USE_DEF dst, USE shift, KILL cr); |
| 8351 | |
| 8352 format %{ "ROR $dst, $shift" %} | |
| 8353 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8354 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8355 ins_pipe( ialu_reg ); | |
| 8356 %} | |
| 8357 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8358 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8359 effect (USE_DEF dst, USE shift, KILL cr); |
| 8360 | |
| 8361 format %{ "ROR $dst, $shift" %} | |
| 8362 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8363 ins_encode( RegOpcImm(dst, shift) ); | |
| 8364 ins_pipe( ialu_reg ); | |
| 8365 %} | |
| 8366 | |
| 8367 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8368 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8369 | |
| 8370 format %{ "ROR $dst, $shift" %} | |
| 8371 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8372 ins_encode(OpcP, RegOpc(dst)); | |
| 8373 ins_pipe( ialu_reg_reg ); | |
| 8374 %} | |
| 8375 // end of ROR expand | |
| 8376 | |
| 8377 // ROR right once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8378 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8379 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8380 | |
| 8381 expand %{ | |
| 8382 rorI_eReg_imm1(dst, rshift, cr); | |
| 8383 %} | |
| 8384 %} | |
| 8385 | |
| 8386 // ROR 32bit by immI8 once | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8387 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8388 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8389 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8390 | |
| 8391 expand %{ | |
| 8392 rorI_eReg_imm8(dst, rshift, cr); | |
| 8393 %} | |
| 8394 %} | |
| 8395 | |
| 8396 // ROR 32bit var by var once | |
| 8397 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8398 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8399 | |
| 8400 expand %{ | |
| 8401 rorI_eReg_CL(dst, shift, cr); | |
| 8402 %} | |
| 8403 %} | |
| 8404 | |
| 8405 // ROR 32bit var by var once | |
| 8406 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8407 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8408 | |
| 8409 expand %{ | |
| 8410 rorI_eReg_CL(dst, shift, cr); | |
| 8411 %} | |
| 8412 %} | |
| 8413 | |
| 8414 // Xor Instructions | |
| 8415 // Xor Register with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8416 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8417 match(Set dst (XorI dst src)); |
| 8418 effect(KILL cr); | |
| 8419 | |
| 8420 size(2); | |
| 8421 format %{ "XOR $dst,$src" %} | |
| 8422 opcode(0x33); | |
| 8423 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8424 ins_pipe( ialu_reg_reg ); | |
| 8425 %} | |
| 8426 | |
| 403 | 8427 // Xor Register with Immediate -1 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8428 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8429 match(Set dst (XorI dst imm)); |
| 8430 | |
| 8431 size(2); | |
| 8432 format %{ "NOT $dst" %} | |
| 8433 ins_encode %{ | |
| 8434 __ notl($dst$$Register); | |
| 8435 %} | |
| 8436 ins_pipe( ialu_reg ); | |
| 8437 %} | |
| 8438 | |
| 0 | 8439 // Xor Register with Immediate |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8440 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8441 match(Set dst (XorI dst src)); |
| 8442 effect(KILL cr); | |
| 8443 | |
| 8444 format %{ "XOR $dst,$src" %} | |
| 8445 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8446 // ins_encode( RegImm( dst, src) ); | |
| 8447 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8448 ins_pipe( ialu_reg ); | |
| 8449 %} | |
| 8450 | |
| 8451 // Xor Register with Memory | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8452 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8453 match(Set dst (XorI dst (LoadI src))); |
| 8454 effect(KILL cr); | |
| 8455 | |
| 8456 ins_cost(125); | |
| 8457 format %{ "XOR $dst,$src" %} | |
| 8458 opcode(0x33); | |
| 8459 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8460 ins_pipe( ialu_reg_mem ); | |
| 8461 %} | |
| 8462 | |
| 8463 // Xor Memory with Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8464 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8465 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8466 effect(KILL cr); | |
| 8467 | |
| 8468 ins_cost(150); | |
| 8469 format %{ "XOR $dst,$src" %} | |
| 8470 opcode(0x31); /* Opcode 31 /r */ | |
| 8471 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8472 ins_pipe( ialu_mem_reg ); | |
| 8473 %} | |
| 8474 | |
| 8475 // Xor Memory with Immediate | |
| 8476 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8477 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8478 effect(KILL cr); | |
| 8479 | |
| 8480 ins_cost(125); | |
| 8481 format %{ "XOR $dst,$src" %} | |
| 8482 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8483 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8484 ins_pipe( ialu_mem_imm ); | |
| 8485 %} | |
| 8486 | |
| 8487 //----------Convert Int to Boolean--------------------------------------------- | |
| 8488 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8489 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8490 effect( DEF dst, USE src ); |
| 8491 format %{ "MOV $dst,$src" %} | |
| 8492 ins_encode( enc_Copy( dst, src) ); | |
| 8493 ins_pipe( ialu_reg_reg ); | |
| 8494 %} | |
| 8495 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8496 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8497 effect( USE_DEF dst, USE src, KILL cr ); |
| 8498 | |
| 8499 size(4); | |
| 8500 format %{ "NEG $dst\n\t" | |
| 8501 "ADC $dst,$src" %} | |
| 8502 ins_encode( neg_reg(dst), | |
| 8503 OpcRegReg(0x13,dst,src) ); | |
| 8504 ins_pipe( ialu_reg_reg_long ); | |
| 8505 %} | |
| 8506 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8507 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8508 match(Set dst (Conv2B src)); |
| 8509 | |
| 8510 expand %{ | |
| 8511 movI_nocopy(dst,src); | |
| 8512 ci2b(dst,src,cr); | |
| 8513 %} | |
| 8514 %} | |
| 8515 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8516 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8517 effect( DEF dst, USE src ); |
| 8518 format %{ "MOV $dst,$src" %} | |
| 8519 ins_encode( enc_Copy( dst, src) ); | |
| 8520 ins_pipe( ialu_reg_reg ); | |
| 8521 %} | |
| 8522 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8523 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8524 effect( USE_DEF dst, USE src, KILL cr ); |
| 8525 format %{ "NEG $dst\n\t" | |
| 8526 "ADC $dst,$src" %} | |
| 8527 ins_encode( neg_reg(dst), | |
| 8528 OpcRegReg(0x13,dst,src) ); | |
| 8529 ins_pipe( ialu_reg_reg_long ); | |
| 8530 %} | |
| 8531 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
8532 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8533 match(Set dst (Conv2B src)); |
| 8534 | |
| 8535 expand %{ | |
| 8536 movP_nocopy(dst,src); | |
| 8537 cp2b(dst,src,cr); | |
| 8538 %} | |
| 8539 %} | |
| 8540 | |
| 9154 | 8541 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8542 match(Set dst (CmpLTMask p q)); |
| 9154 | 8543 effect(KILL cr); |
| 0 | 8544 ins_cost(400); |
| 8545 | |
| 8546 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8547 format %{ "XOR $dst,$dst\n\t" | |
| 8548 "CMP $p,$q\n\t" | |
| 8549 "SETlt $dst\n\t" | |
| 8550 "NEG $dst" %} | |
| 9154 | 8551 ins_encode %{ |
| 8552 Register Rp = $p$$Register; | |
| 8553 Register Rq = $q$$Register; | |
| 8554 Register Rd = $dst$$Register; | |
| 8555 Label done; | |
| 8556 __ xorl(Rd, Rd); | |
| 8557 __ cmpl(Rp, Rq); | |
| 8558 __ setb(Assembler::less, Rd); | |
| 8559 __ negl(Rd); | |
| 8560 %} | |
| 8561 | |
| 8562 ins_pipe(pipe_slow); | |
| 8563 %} | |
| 8564 | |
| 8565 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 8566 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 8567 effect(DEF dst, KILL cr); |
| 0 | 8568 ins_cost(100); |
| 8569 | |
| 9154 | 8570 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 8571 ins_encode %{ | |
| 8572 __ sarl($dst$$Register, 31); | |
| 8573 %} | |
| 8574 ins_pipe(ialu_reg); | |
| 8575 %} | |
| 8576 | |
| 8577 /* better to save a register than avoid a branch */ | |
| 8578 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 8579 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 8580 effect(KILL cr); |
| 0 | 8581 ins_cost(400); |
| 9154 | 8582 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 8583 "JGE done\n\t" | |
| 8584 "ADD $p,$y\n" | |
| 8585 "done: " %} | |
| 8586 ins_encode %{ | |
| 8587 Register Rp = $p$$Register; | |
| 8588 Register Rq = $q$$Register; | |
| 8589 Register Ry = $y$$Register; | |
| 8590 Label done; | |
| 8591 __ subl(Rp, Rq); | |
| 8592 __ jccb(Assembler::greaterEqual, done); | |
| 8593 __ addl(Rp, Ry); | |
| 8594 __ bind(done); | |
| 8595 %} | |
| 8596 | |
| 8597 ins_pipe(pipe_cmplt); | |
| 8598 %} | |
| 8599 | |
| 8600 /* better to save a register than avoid a branch */ | |
| 8601 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 8602 match(Set y (AndI (CmpLTMask p q) y)); | |
| 8603 effect(KILL cr); | |
| 8604 | |
| 8605 ins_cost(300); | |
| 8606 | |
| 8607 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 8608 "JLT done\n\t" | |
| 8609 "XORL $y, $y\n" | |
| 8610 "done: " %} | |
| 8611 ins_encode %{ | |
| 8612 Register Rp = $p$$Register; | |
| 8613 Register Rq = $q$$Register; | |
| 8614 Register Ry = $y$$Register; | |
| 8615 Label done; | |
| 8616 __ cmpl(Rp, Rq); | |
| 8617 __ jccb(Assembler::less, done); | |
| 8618 __ xorl(Ry, Ry); | |
| 8619 __ bind(done); | |
| 8620 %} | |
| 8621 | |
| 8622 ins_pipe(pipe_cmplt); | |
| 0 | 8623 %} |
| 8624 | |
| 8625 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 8626 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 8627 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 8628 */ | |
|
17726
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8629 //----------Overflow Math Instructions----------------------------------------- |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8630 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8631 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8632 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8633 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8634 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8635 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8636 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8637 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8638 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8639 __ addl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8640 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8641 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8642 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8643 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8644 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8645 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8646 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8647 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8648 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8649 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8650 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8651 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8652 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8653 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8654 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8655 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8656 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8657 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8658 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8659 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8660 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8661 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8662 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8663 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8664 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8665 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8666 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8667 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8668 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8669 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8670 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8671 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8672 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8673 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8674 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8675 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8676 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8677 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8678 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8679 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8680 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8681 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8682 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8683 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8684 format %{ "NEG $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8685 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8686 __ negl($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8687 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8688 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8689 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8690 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8691 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8692 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8693 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8694 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8695 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8696 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8697 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8698 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8699 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8700 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8701 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8702 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8703 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8704 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8705 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8706 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8707 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8708 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8709 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8710 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8711 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8712 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
8713 %} |
| 0 | 8714 |
| 8715 //----------Long Instructions------------------------------------------------ | |
| 8716 // Add Long Register with Register | |
| 8717 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8718 match(Set dst (AddL dst src)); | |
| 8719 effect(KILL cr); | |
| 8720 ins_cost(200); | |
| 8721 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8722 "ADC $dst.hi,$src.hi" %} | |
| 8723 opcode(0x03, 0x13); | |
| 8724 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8725 ins_pipe( ialu_reg_reg_long ); | |
| 8726 %} | |
| 8727 | |
| 8728 // Add Long Register with Immediate | |
| 8729 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8730 match(Set dst (AddL dst src)); | |
| 8731 effect(KILL cr); | |
| 8732 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8733 "ADC $dst.hi,$src.hi" %} | |
| 8734 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8735 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8736 ins_pipe( ialu_reg_long ); | |
| 8737 %} | |
| 8738 | |
| 8739 // Add Long Register with Memory | |
| 8740 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8741 match(Set dst (AddL dst (LoadL mem))); | |
| 8742 effect(KILL cr); | |
| 8743 ins_cost(125); | |
| 8744 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8745 "ADC $dst.hi,$mem+4" %} | |
| 8746 opcode(0x03, 0x13); | |
| 8747 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8748 ins_pipe( ialu_reg_long_mem ); | |
| 8749 %} | |
| 8750 | |
| 8751 // Subtract Long Register with Register. | |
| 8752 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8753 match(Set dst (SubL dst src)); | |
| 8754 effect(KILL cr); | |
| 8755 ins_cost(200); | |
| 8756 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8757 "SBB $dst.hi,$src.hi" %} | |
| 8758 opcode(0x2B, 0x1B); | |
| 8759 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8760 ins_pipe( ialu_reg_reg_long ); | |
| 8761 %} | |
| 8762 | |
| 8763 // Subtract Long Register with Immediate | |
| 8764 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8765 match(Set dst (SubL dst src)); | |
| 8766 effect(KILL cr); | |
| 8767 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8768 "SBB $dst.hi,$src.hi" %} | |
| 8769 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8770 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8771 ins_pipe( ialu_reg_long ); | |
| 8772 %} | |
| 8773 | |
| 8774 // Subtract Long Register with Memory | |
| 8775 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8776 match(Set dst (SubL dst (LoadL mem))); | |
| 8777 effect(KILL cr); | |
| 8778 ins_cost(125); | |
| 8779 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8780 "SBB $dst.hi,$mem+4" %} | |
| 8781 opcode(0x2B, 0x1B); | |
| 8782 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8783 ins_pipe( ialu_reg_long_mem ); | |
| 8784 %} | |
| 8785 | |
| 8786 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8787 match(Set dst (SubL zero dst)); | |
| 8788 effect(KILL cr); | |
| 8789 ins_cost(300); | |
| 8790 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8791 ins_encode( neg_long(dst) ); | |
| 8792 ins_pipe( ialu_reg_reg_long ); | |
| 8793 %} | |
| 8794 | |
| 8795 // And Long Register with Register | |
| 8796 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8797 match(Set dst (AndL dst src)); | |
| 8798 effect(KILL cr); | |
| 8799 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8800 "AND $dst.hi,$src.hi" %} | |
| 8801 opcode(0x23,0x23); | |
| 8802 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8803 ins_pipe( ialu_reg_reg_long ); | |
| 8804 %} | |
| 8805 | |
| 8806 // And Long Register with Immediate | |
| 8807 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8808 match(Set dst (AndL dst src)); | |
| 8809 effect(KILL cr); | |
| 8810 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8811 "AND $dst.hi,$src.hi" %} | |
| 8812 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 8813 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8814 ins_pipe( ialu_reg_long ); | |
| 8815 %} | |
| 8816 | |
| 8817 // And Long Register with Memory | |
| 8818 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8819 match(Set dst (AndL dst (LoadL mem))); | |
| 8820 effect(KILL cr); | |
| 8821 ins_cost(125); | |
| 8822 format %{ "AND $dst.lo,$mem\n\t" | |
| 8823 "AND $dst.hi,$mem+4" %} | |
| 8824 opcode(0x23, 0x23); | |
| 8825 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8826 ins_pipe( ialu_reg_long_mem ); | |
| 8827 %} | |
| 8828 | |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8829 // BMI1 instructions |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8830 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8831 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8832 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8833 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8834 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8835 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8836 "ANDNL $dst.hi, $src1.hi, $src2.hi" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8837 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8838 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8839 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8840 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8841 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8842 Register Rsrc2 = $src2$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8843 __ andnl(Rdst, Rsrc1, Rsrc2); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8844 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8845 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8846 ins_pipe(ialu_reg_reg_long); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8847 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8848 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8849 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8850 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8851 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8852 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8853 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8854 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8855 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8856 "ANDNL $dst.hi, $src1.hi, $src2+4" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8857 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8858 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8859 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8860 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8861 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8862 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8863 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8864 __ andnl(Rdst, Rsrc1, $src2$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8865 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8866 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8867 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8868 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8869 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8870 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8871 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8872 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8873 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8874 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8875 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8876 "BLSIL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8877 "JNZ done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8878 "BLSIL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8879 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8880 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8881 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8882 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8883 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8884 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8885 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8886 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8887 __ blsil(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8888 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8889 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8890 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8891 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8892 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8893 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8894 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8895 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8896 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8897 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8898 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8899 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8900 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8901 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8902 "BLSIL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8903 "JNZ done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8904 "BLSIL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8905 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8906 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8907 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8908 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8909 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8910 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8911 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8912 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8913 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8914 __ blsil(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8915 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8916 __ blsil(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8917 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8918 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8919 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8920 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8921 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8922 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8923 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8924 match(Set dst (XorL (AddL src minus_1) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8925 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8926 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8927 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8928 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8929 "BLSMSKL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8930 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8931 "BLSMSKL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8932 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8933 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8934 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8935 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8936 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8937 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8938 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8939 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8940 __ blsmskl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8941 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8942 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8943 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8944 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8945 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8946 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8947 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8948 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8949 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8950 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8951 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8952 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8953 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8954 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8955 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8956 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8957 "BLSMSKL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8958 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8959 "BLSMSKL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8960 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8961 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8962 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8963 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8964 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8965 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8966 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8967 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8968 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8969 __ blsmskl(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8970 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8971 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8972 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8973 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8974 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8975 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8976 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8977 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8978 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8979 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8980 match(Set dst (AndL (AddL src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8981 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8982 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8983 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8984 format %{ "MOVL $dst.hi, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8985 "BLSRL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8986 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8987 "BLSRL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8988 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8989 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8990 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8991 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8992 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8993 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8994 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8995 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8996 __ blsrl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8997 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8998 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8999 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9000 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9001 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9002 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9003 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9004 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9005 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9006 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9007 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9008 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9009 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9010 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9011 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9012 format %{ "MOVL $dst.hi, $src+4\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9013 "BLSRL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9014 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9015 "BLSRL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9016 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9017 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9018 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9019 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9020 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9021 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9022 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9023 __ movl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9024 __ blsrl(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9025 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9026 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9027 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9028 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9029 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9030 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9031 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9032 |
| 0 | 9033 // Or Long Register with Register |
| 9034 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9035 match(Set dst (OrL dst src)); | |
| 9036 effect(KILL cr); | |
| 9037 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9038 "OR $dst.hi,$src.hi" %} | |
| 9039 opcode(0x0B,0x0B); | |
| 9040 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9041 ins_pipe( ialu_reg_reg_long ); | |
| 9042 %} | |
| 9043 | |
| 9044 // Or Long Register with Immediate | |
| 9045 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9046 match(Set dst (OrL dst src)); | |
| 9047 effect(KILL cr); | |
| 9048 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9049 "OR $dst.hi,$src.hi" %} | |
| 9050 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9051 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9052 ins_pipe( ialu_reg_long ); | |
| 9053 %} | |
| 9054 | |
| 9055 // Or Long Register with Memory | |
| 9056 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9057 match(Set dst (OrL dst (LoadL mem))); | |
| 9058 effect(KILL cr); | |
| 9059 ins_cost(125); | |
| 9060 format %{ "OR $dst.lo,$mem\n\t" | |
| 9061 "OR $dst.hi,$mem+4" %} | |
| 9062 opcode(0x0B,0x0B); | |
| 9063 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9064 ins_pipe( ialu_reg_long_mem ); | |
| 9065 %} | |
| 9066 | |
| 9067 // Xor Long Register with Register | |
| 9068 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9069 match(Set dst (XorL dst src)); | |
| 9070 effect(KILL cr); | |
| 9071 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9072 "XOR $dst.hi,$src.hi" %} | |
| 9073 opcode(0x33,0x33); | |
| 9074 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9075 ins_pipe( ialu_reg_reg_long ); | |
| 9076 %} | |
| 9077 | |
| 403 | 9078 // Xor Long Register with Immediate -1 |
| 9079 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9080 match(Set dst (XorL dst imm)); | |
| 9081 format %{ "NOT $dst.lo\n\t" | |
| 9082 "NOT $dst.hi" %} | |
| 9083 ins_encode %{ | |
| 9084 __ notl($dst$$Register); | |
| 9085 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9086 %} | |
| 9087 ins_pipe( ialu_reg_long ); | |
| 9088 %} | |
| 9089 | |
| 0 | 9090 // Xor Long Register with Immediate |
| 9091 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9092 match(Set dst (XorL dst src)); | |
| 9093 effect(KILL cr); | |
| 9094 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9095 "XOR $dst.hi,$src.hi" %} | |
| 9096 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9097 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9098 ins_pipe( ialu_reg_long ); | |
| 9099 %} | |
| 9100 | |
| 9101 // Xor Long Register with Memory | |
| 9102 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9103 match(Set dst (XorL dst (LoadL mem))); | |
| 9104 effect(KILL cr); | |
| 9105 ins_cost(125); | |
| 9106 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9107 "XOR $dst.hi,$mem+4" %} | |
| 9108 opcode(0x33,0x33); | |
| 9109 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9110 ins_pipe( ialu_reg_long_mem ); | |
| 9111 %} | |
| 9112 | |
| 219 | 9113 // Shift Left Long by 1 |
| 9114 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9115 predicate(UseNewLongLShift); | |
| 9116 match(Set dst (LShiftL dst cnt)); | |
| 9117 effect(KILL cr); | |
| 9118 ins_cost(100); | |
| 9119 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9120 "ADC $dst.hi,$dst.hi" %} | |
| 9121 ins_encode %{ | |
| 9122 __ addl($dst$$Register,$dst$$Register); | |
| 9123 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9124 %} | |
| 9125 ins_pipe( ialu_reg_long ); | |
| 9126 %} | |
| 9127 | |
| 9128 // Shift Left Long by 2 | |
| 9129 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9130 predicate(UseNewLongLShift); | |
| 9131 match(Set dst (LShiftL dst cnt)); | |
| 9132 effect(KILL cr); | |
| 9133 ins_cost(100); | |
| 9134 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9135 "ADC $dst.hi,$dst.hi\n\t" | |
| 9136 "ADD $dst.lo,$dst.lo\n\t" | |
| 9137 "ADC $dst.hi,$dst.hi" %} | |
| 9138 ins_encode %{ | |
| 9139 __ addl($dst$$Register,$dst$$Register); | |
| 9140 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9141 __ addl($dst$$Register,$dst$$Register); | |
| 9142 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9143 %} | |
| 9144 ins_pipe( ialu_reg_long ); | |
| 9145 %} | |
| 9146 | |
| 9147 // Shift Left Long by 3 | |
| 9148 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9149 predicate(UseNewLongLShift); | |
| 9150 match(Set dst (LShiftL dst cnt)); | |
| 9151 effect(KILL cr); | |
| 9152 ins_cost(100); | |
| 9153 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9154 "ADC $dst.hi,$dst.hi\n\t" | |
| 9155 "ADD $dst.lo,$dst.lo\n\t" | |
| 9156 "ADC $dst.hi,$dst.hi\n\t" | |
| 9157 "ADD $dst.lo,$dst.lo\n\t" | |
| 9158 "ADC $dst.hi,$dst.hi" %} | |
| 9159 ins_encode %{ | |
| 9160 __ addl($dst$$Register,$dst$$Register); | |
| 9161 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9162 __ addl($dst$$Register,$dst$$Register); | |
| 9163 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9164 __ addl($dst$$Register,$dst$$Register); | |
| 9165 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9166 %} | |
| 9167 ins_pipe( ialu_reg_long ); | |
| 9168 %} | |
| 9169 | |
| 0 | 9170 // Shift Left Long by 1-31 |
| 9171 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9172 match(Set dst (LShiftL dst cnt)); | |
| 9173 effect(KILL cr); | |
| 9174 ins_cost(200); | |
| 9175 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9176 "SHL $dst.lo,$cnt" %} | |
| 9177 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9178 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9179 ins_pipe( ialu_reg_long ); | |
| 9180 %} | |
| 9181 | |
| 9182 // Shift Left Long by 32-63 | |
| 9183 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9184 match(Set dst (LShiftL dst cnt)); | |
| 9185 effect(KILL cr); | |
| 9186 ins_cost(300); | |
| 9187 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9188 "\tSHL $dst.hi,$cnt-32\n" | |
| 9189 "\tXOR $dst.lo,$dst.lo" %} | |
| 9190 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9191 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9192 ins_pipe( ialu_reg_long ); | |
| 9193 %} | |
| 9194 | |
| 9195 // Shift Left Long by variable | |
| 9196 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9197 match(Set dst (LShiftL dst shift)); | |
| 9198 effect(KILL cr); | |
| 9199 ins_cost(500+200); | |
| 9200 size(17); | |
| 9201 format %{ "TEST $shift,32\n\t" | |
| 9202 "JEQ,s small\n\t" | |
| 9203 "MOV $dst.hi,$dst.lo\n\t" | |
| 9204 "XOR $dst.lo,$dst.lo\n" | |
| 9205 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9206 "SHL $dst.lo,$shift" %} | |
| 9207 ins_encode( shift_left_long( dst, shift ) ); | |
| 9208 ins_pipe( pipe_slow ); | |
| 9209 %} | |
| 9210 | |
| 9211 // Shift Right Long by 1-31 | |
| 9212 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9213 match(Set dst (URShiftL dst cnt)); | |
| 9214 effect(KILL cr); | |
| 9215 ins_cost(200); | |
| 9216 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9217 "SHR $dst.hi,$cnt" %} | |
| 9218 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9219 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9220 ins_pipe( ialu_reg_long ); | |
| 9221 %} | |
| 9222 | |
| 9223 // Shift Right Long by 32-63 | |
| 9224 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9225 match(Set dst (URShiftL dst cnt)); | |
| 9226 effect(KILL cr); | |
| 9227 ins_cost(300); | |
| 9228 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9229 "\tSHR $dst.lo,$cnt-32\n" | |
| 9230 "\tXOR $dst.hi,$dst.hi" %} | |
| 9231 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9232 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9233 ins_pipe( ialu_reg_long ); | |
| 9234 %} | |
| 9235 | |
| 9236 // Shift Right Long by variable | |
| 9237 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9238 match(Set dst (URShiftL dst shift)); | |
| 9239 effect(KILL cr); | |
| 9240 ins_cost(600); | |
| 9241 size(17); | |
| 9242 format %{ "TEST $shift,32\n\t" | |
| 9243 "JEQ,s small\n\t" | |
| 9244 "MOV $dst.lo,$dst.hi\n\t" | |
| 9245 "XOR $dst.hi,$dst.hi\n" | |
| 9246 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9247 "SHR $dst.hi,$shift" %} | |
| 9248 ins_encode( shift_right_long( dst, shift ) ); | |
| 9249 ins_pipe( pipe_slow ); | |
| 9250 %} | |
| 9251 | |
| 9252 // Shift Right Long by 1-31 | |
| 9253 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9254 match(Set dst (RShiftL dst cnt)); | |
| 9255 effect(KILL cr); | |
| 9256 ins_cost(200); | |
| 9257 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9258 "SAR $dst.hi,$cnt" %} | |
| 9259 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9260 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9261 ins_pipe( ialu_reg_long ); | |
| 9262 %} | |
| 9263 | |
| 9264 // Shift Right Long by 32-63 | |
| 9265 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9266 match(Set dst (RShiftL dst cnt)); | |
| 9267 effect(KILL cr); | |
| 9268 ins_cost(300); | |
| 9269 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9270 "\tSAR $dst.lo,$cnt-32\n" | |
| 9271 "\tSAR $dst.hi,31" %} | |
| 9272 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9273 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9274 ins_pipe( ialu_reg_long ); | |
| 9275 %} | |
| 9276 | |
| 9277 // Shift Right arithmetic Long by variable | |
| 9278 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9279 match(Set dst (RShiftL dst shift)); | |
| 9280 effect(KILL cr); | |
| 9281 ins_cost(600); | |
| 9282 size(18); | |
| 9283 format %{ "TEST $shift,32\n\t" | |
| 9284 "JEQ,s small\n\t" | |
| 9285 "MOV $dst.lo,$dst.hi\n\t" | |
| 9286 "SAR $dst.hi,31\n" | |
| 9287 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9288 "SAR $dst.hi,$shift" %} | |
| 9289 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9290 ins_pipe( pipe_slow ); | |
| 9291 %} | |
| 9292 | |
| 9293 | |
| 9294 //----------Double Instructions------------------------------------------------ | |
| 9295 // Double Math | |
| 9296 | |
| 9297 // Compare & branch | |
| 9298 | |
| 9299 // P6 version of float compare, sets condition codes in EFLAGS | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9300 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9301 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9302 match(Set cr (CmpD src1 src2)); | |
| 9303 effect(KILL rax); | |
| 9304 ins_cost(150); | |
| 9305 format %{ "FLD $src1\n\t" | |
| 9306 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9307 "JNP exit\n\t" | |
| 9308 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9309 "SAHF\n" | |
| 9310 "exit:\tNOP // avoid branch to branch" %} | |
| 9311 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9312 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9313 OpcP, RegOpc(src2), |
| 9314 cmpF_P6_fixup ); | |
| 9315 ins_pipe( pipe_slow ); | |
| 9316 %} | |
| 9317 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9318 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9319 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9320 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9321 ins_cost(150); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9322 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9323 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9324 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9325 ins_encode( Push_Reg_DPR(src1), |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9326 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9327 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9328 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9329 |
| 0 | 9330 // Compare & branch |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9331 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9332 predicate(UseSSE<=1); |
| 9333 match(Set cr (CmpD src1 src2)); | |
| 9334 effect(KILL rax); | |
| 9335 ins_cost(200); | |
| 9336 format %{ "FLD $src1\n\t" | |
| 9337 "FCOMp $src2\n\t" | |
| 9338 "FNSTSW AX\n\t" | |
| 9339 "TEST AX,0x400\n\t" | |
| 9340 "JZ,s flags\n\t" | |
| 9341 "MOV AH,1\t# unordered treat as LT\n" | |
| 9342 "flags:\tSAHF" %} | |
| 9343 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9344 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9345 OpcP, RegOpc(src2), |
| 9346 fpu_flags); | |
| 9347 ins_pipe( pipe_slow ); | |
| 9348 %} | |
| 9349 | |
| 9350 // Compare vs zero into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
9351 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9352 predicate(UseSSE<=1); |
| 9353 match(Set dst (CmpD3 src1 zero)); | |
| 9354 effect(KILL cr, KILL rax); | |
| 9355 ins_cost(280); | |
| 9356 format %{ "FTSTD $dst,$src1" %} | |
| 9357 opcode(0xE4, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9358 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9359 OpcS, OpcP, PopFPU, |
| 9360 CmpF_Result(dst)); | |
| 9361 ins_pipe( pipe_slow ); | |
| 9362 %} | |
| 9363 | |
| 9364 // Compare into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
9365 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9366 predicate(UseSSE<=1); |
| 9367 match(Set dst (CmpD3 src1 src2)); | |
| 9368 effect(KILL cr, KILL rax); | |
| 9369 ins_cost(300); | |
| 9370 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9371 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9372 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9373 OpcP, RegOpc(src2), |
| 9374 CmpF_Result(dst)); | |
| 9375 ins_pipe( pipe_slow ); | |
| 9376 %} | |
| 9377 | |
| 9378 // float compare and set condition codes in EFLAGS by XMM regs | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9379 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9380 predicate(UseSSE>=2); |
| 4759 | 9381 match(Set cr (CmpD src1 src2)); |
| 9382 ins_cost(145); | |
| 9383 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9384 "JNP,s exit\n\t" | |
| 9385 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9386 "AND [rsp], #0xffffff2b\n\t" | |
| 9387 "POPF\n" | |
| 9388 "exit:" %} | |
| 9389 ins_encode %{ | |
| 9390 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9391 emit_cmpfp_fixup(_masm); | |
| 9392 %} | |
| 9393 ins_pipe( pipe_slow ); | |
| 9394 %} | |
| 9395 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9396 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9397 predicate(UseSSE>=2); |
| 4759 | 9398 match(Set cr (CmpD src1 src2)); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9399 ins_cost(100); |
| 4759 | 9400 format %{ "UCOMISD $src1,$src2" %} |
| 9401 ins_encode %{ | |
| 9402 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9403 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9404 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9405 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9406 |
| 0 | 9407 // float compare and set condition codes in EFLAGS by XMM regs |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9408 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9409 predicate(UseSSE>=2); |
| 4759 | 9410 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9411 ins_cost(145); |
| 4759 | 9412 format %{ "UCOMISD $src1,$src2\n\t" |
| 9413 "JNP,s exit\n\t" | |
| 9414 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9415 "AND [rsp], #0xffffff2b\n\t" | |
| 9416 "POPF\n" | |
| 9417 "exit:" %} | |
| 9418 ins_encode %{ | |
| 9419 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9420 emit_cmpfp_fixup(_masm); | |
| 9421 %} | |
| 9422 ins_pipe( pipe_slow ); | |
| 9423 %} | |
| 9424 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9425 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9426 predicate(UseSSE>=2); |
| 4759 | 9427 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9428 ins_cost(100); |
| 4759 | 9429 format %{ "UCOMISD $src1,$src2" %} |
| 9430 ins_encode %{ | |
| 9431 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9432 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9433 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9434 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9435 |
| 0 | 9436 // Compare into -1,0,1 in XMM |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9437 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9438 predicate(UseSSE>=2); |
| 9439 match(Set dst (CmpD3 src1 src2)); | |
| 9440 effect(KILL cr); | |
| 9441 ins_cost(255); | |
| 4759 | 9442 format %{ "UCOMISD $src1, $src2\n\t" |
| 9443 "MOV $dst, #-1\n\t" | |
| 9444 "JP,s done\n\t" | |
| 9445 "JB,s done\n\t" | |
| 9446 "SETNE $dst\n\t" | |
| 9447 "MOVZB $dst, $dst\n" | |
| 9448 "done:" %} | |
| 9449 ins_encode %{ | |
| 9450 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9451 emit_cmpfp3(_masm, $dst$$Register); | |
| 9452 %} | |
| 0 | 9453 ins_pipe( pipe_slow ); |
| 9454 %} | |
| 9455 | |
| 9456 // Compare into -1,0,1 in XMM and memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9457 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9458 predicate(UseSSE>=2); |
| 4759 | 9459 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9460 effect(KILL cr); |
| 9461 ins_cost(275); | |
| 4759 | 9462 format %{ "UCOMISD $src1, $src2\n\t" |
| 9463 "MOV $dst, #-1\n\t" | |
| 9464 "JP,s done\n\t" | |
| 9465 "JB,s done\n\t" | |
| 9466 "SETNE $dst\n\t" | |
| 9467 "MOVZB $dst, $dst\n" | |
| 9468 "done:" %} | |
| 9469 ins_encode %{ | |
| 9470 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9471 emit_cmpfp3(_masm, $dst$$Register); | |
| 9472 %} | |
| 0 | 9473 ins_pipe( pipe_slow ); |
| 9474 %} | |
| 9475 | |
| 9476 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9477 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9478 predicate (UseSSE <=1); |
| 9479 match(Set dst (SubD dst src)); | |
| 9480 | |
| 9481 format %{ "FLD $src\n\t" | |
| 9482 "DSUBp $dst,ST" %} | |
| 9483 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9484 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9485 ins_encode( Push_Reg_DPR(src), |
| 0 | 9486 OpcP, RegOpc(dst) ); |
| 9487 ins_pipe( fpu_reg_reg ); | |
| 9488 %} | |
| 9489 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9490 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9491 predicate (UseSSE <=1); |
| 9492 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9493 ins_cost(250); | |
| 9494 | |
| 9495 format %{ "FLD $src2\n\t" | |
| 9496 "DSUB ST,$src1\n\t" | |
| 9497 "FSTP_D $dst\t# D-round" %} | |
| 9498 opcode(0xD8, 0x5); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9499 ins_encode( Push_Reg_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9500 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9501 ins_pipe( fpu_mem_reg_reg ); |
| 9502 %} | |
| 9503 | |
| 9504 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9505 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9506 predicate (UseSSE <=1); |
| 9507 match(Set dst (SubD dst (LoadD src))); | |
| 9508 ins_cost(150); | |
| 9509 | |
| 9510 format %{ "FLD $src\n\t" | |
| 9511 "DSUBp $dst,ST" %} | |
| 9512 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9513 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9514 OpcP, RegOpc(dst) ); | |
| 9515 ins_pipe( fpu_reg_mem ); | |
| 9516 %} | |
| 9517 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9518 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9519 predicate (UseSSE<=1); |
| 9520 match(Set dst (AbsD src)); | |
| 9521 ins_cost(100); | |
| 9522 format %{ "FABS" %} | |
| 9523 opcode(0xE1, 0xD9); | |
| 9524 ins_encode( OpcS, OpcP ); | |
| 9525 ins_pipe( fpu_reg_reg ); | |
| 9526 %} | |
| 9527 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9528 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9529 predicate(UseSSE<=1); |
| 9530 match(Set dst (NegD src)); | |
| 9531 ins_cost(100); | |
| 9532 format %{ "FCHS" %} | |
| 9533 opcode(0xE0, 0xD9); | |
| 9534 ins_encode( OpcS, OpcP ); | |
| 9535 ins_pipe( fpu_reg_reg ); | |
| 9536 %} | |
| 9537 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9538 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9539 predicate(UseSSE<=1); |
| 9540 match(Set dst (AddD dst src)); | |
| 9541 format %{ "FLD $src\n\t" | |
| 9542 "DADD $dst,ST" %} | |
| 9543 size(4); | |
| 9544 ins_cost(150); | |
| 9545 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9546 ins_encode( Push_Reg_DPR(src), |
| 0 | 9547 OpcP, RegOpc(dst) ); |
| 9548 ins_pipe( fpu_reg_reg ); | |
| 9549 %} | |
| 9550 | |
| 9551 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9552 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9553 predicate(UseSSE<=1); |
| 9554 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9555 ins_cost(250); | |
| 9556 | |
| 9557 format %{ "FLD $src2\n\t" | |
| 9558 "DADD ST,$src1\n\t" | |
| 9559 "FSTP_D $dst\t# D-round" %} | |
| 9560 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9561 ins_encode( Push_Reg_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9562 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9563 ins_pipe( fpu_mem_reg_reg ); |
| 9564 %} | |
| 9565 | |
| 9566 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9567 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9568 predicate(UseSSE<=1); |
| 9569 match(Set dst (AddD dst (LoadD src))); | |
| 9570 ins_cost(150); | |
| 9571 | |
| 9572 format %{ "FLD $src\n\t" | |
| 9573 "DADDp $dst,ST" %} | |
| 9574 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9575 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9576 OpcP, RegOpc(dst) ); | |
| 9577 ins_pipe( fpu_reg_mem ); | |
| 9578 %} | |
| 9579 | |
| 9580 // add-to-memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9581 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9582 predicate(UseSSE<=1); |
| 9583 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9584 ins_cost(150); | |
| 9585 | |
| 9586 format %{ "FLD_D $dst\n\t" | |
| 9587 "DADD ST,$src\n\t" | |
| 9588 "FST_D $dst" %} | |
| 9589 opcode(0xDD, 0x0); | |
| 9590 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9591 Opcode(0xD8), RegOpc(src), | |
| 9592 set_instruction_start, | |
| 9593 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9594 ins_pipe( fpu_reg_mem ); | |
| 9595 %} | |
| 9596 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9597 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9598 predicate(UseSSE<=1); |
| 2008 | 9599 match(Set dst (AddD dst con)); |
| 0 | 9600 ins_cost(125); |
| 9601 format %{ "FLD1\n\t" | |
| 9602 "DADDp $dst,ST" %} | |
| 2008 | 9603 ins_encode %{ |
| 9604 __ fld1(); | |
| 9605 __ faddp($dst$$reg); | |
| 9606 %} | |
| 9607 ins_pipe(fpu_reg); | |
| 9608 %} | |
| 9609 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9610 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9611 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9612 match(Set dst (AddD dst con)); |
| 0 | 9613 ins_cost(200); |
| 2008 | 9614 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9615 "DADDp $dst,ST" %} |
| 2008 | 9616 ins_encode %{ |
| 9617 __ fld_d($constantaddress($con)); | |
| 9618 __ faddp($dst$$reg); | |
| 9619 %} | |
| 9620 ins_pipe(fpu_reg_mem); | |
| 0 | 9621 %} |
| 9622 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9623 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9624 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9625 match(Set dst (RoundDouble (AddD src con))); | |
| 9626 ins_cost(200); | |
| 2008 | 9627 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9628 "DADD ST,$src\n\t" |
| 9629 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9630 ins_encode %{ |
| 9631 __ fld_d($constantaddress($con)); | |
| 9632 __ fadd($src$$reg); | |
| 9633 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9634 %} | |
| 9635 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9636 %} |
| 9637 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9638 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9639 predicate(UseSSE<=1); |
| 9640 match(Set dst (MulD dst src)); | |
| 9641 format %{ "FLD $src\n\t" | |
| 9642 "DMULp $dst,ST" %} | |
| 9643 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9644 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9645 ins_encode( Push_Reg_DPR(src), |
| 0 | 9646 OpcP, RegOpc(dst) ); |
| 9647 ins_pipe( fpu_reg_reg ); | |
| 9648 %} | |
| 9649 | |
| 9650 // Strict FP instruction biases argument before multiply then | |
| 9651 // biases result to avoid double rounding of subnormals. | |
| 9652 // | |
| 9653 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9654 // load arg2 | |
| 9655 // multiply scaled arg1 by arg2 | |
| 9656 // rescale product by 2^(15360) | |
| 9657 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9658 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9659 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9660 match(Set dst (MulD dst src)); | |
| 9661 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9662 | |
| 9663 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9664 "DMULp $dst,ST\n\t" | |
| 9665 "FLD $src\n\t" | |
| 9666 "DMULp $dst,ST\n\t" | |
| 9667 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9668 "DMULp $dst,ST\n\t" %} | |
| 9669 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9670 ins_encode( strictfp_bias1(dst), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9671 Push_Reg_DPR(src), |
| 0 | 9672 OpcP, RegOpc(dst), |
| 9673 strictfp_bias2(dst) ); | |
| 9674 ins_pipe( fpu_reg_reg ); | |
| 9675 %} | |
| 9676 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9677 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9678 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9679 match(Set dst (MulD dst con)); |
| 0 | 9680 ins_cost(200); |
| 2008 | 9681 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9682 "DMULp $dst,ST" %} |
| 2008 | 9683 ins_encode %{ |
| 9684 __ fld_d($constantaddress($con)); | |
| 9685 __ fmulp($dst$$reg); | |
| 9686 %} | |
| 9687 ins_pipe(fpu_reg_mem); | |
| 0 | 9688 %} |
| 9689 | |
| 9690 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9691 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9692 predicate( UseSSE<=1 ); |
| 9693 match(Set dst (MulD dst (LoadD src))); | |
| 9694 ins_cost(200); | |
| 9695 format %{ "FLD_D $src\n\t" | |
| 9696 "DMULp $dst,ST" %} | |
| 9697 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9698 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9699 OpcP, RegOpc(dst) ); | |
| 9700 ins_pipe( fpu_reg_mem ); | |
| 9701 %} | |
| 9702 | |
| 9703 // | |
| 9704 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9705 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9706 predicate( UseSSE<=1 ); |
| 9707 match(Set dst (MulD src (LoadD mem))); | |
| 9708 ins_cost(250); | |
| 9709 format %{ "FLD_D $mem\n\t" | |
| 9710 "DMUL ST,$src\n\t" | |
| 9711 "FSTP_D $dst" %} | |
| 9712 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9713 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9714 OpcReg_FPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9715 Pop_Reg_DPR(dst) ); |
| 0 | 9716 ins_pipe( fpu_reg_reg_mem ); |
| 9717 %} | |
| 9718 | |
| 9719 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9720 // MACRO3 -- addDPR a mulDPR |
| 0 | 9721 // This instruction is a '2-address' instruction in that the result goes |
| 9722 // back to src2. This eliminates a move from the macro; possibly the | |
| 9723 // register allocator will have to add it back (and maybe not). | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9724 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9725 predicate( UseSSE<=1 ); |
| 9726 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9727 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9728 "DMUL ST,$src1\n\t" | |
| 9729 "DADDp $src2,ST" %} | |
| 9730 ins_cost(250); | |
| 9731 opcode(0xDD); /* LoadD DD /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9732 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9733 FMul_ST_reg(src1), |
| 9734 FAddP_reg_ST(src2) ); | |
| 9735 ins_pipe( fpu_reg_reg_reg ); | |
| 9736 %} | |
| 9737 | |
| 9738 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9739 // MACRO3 -- subDPR a mulDPR |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9740 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9741 predicate( UseSSE<=1 ); |
| 9742 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9743 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9744 "DMUL ST,$src1\n\t" | |
| 9745 "DSUBRp $src2,ST" %} | |
| 9746 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9747 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9748 FMul_ST_reg(src1), |
| 9749 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9750 ins_pipe( fpu_reg_reg_reg ); | |
| 9751 %} | |
| 9752 | |
| 9753 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9754 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9755 predicate( UseSSE<=1 ); |
| 9756 match(Set dst (DivD dst src)); | |
| 9757 | |
| 9758 format %{ "FLD $src\n\t" | |
| 9759 "FDIVp $dst,ST" %} | |
| 9760 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9761 ins_cost(150); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9762 ins_encode( Push_Reg_DPR(src), |
| 0 | 9763 OpcP, RegOpc(dst) ); |
| 9764 ins_pipe( fpu_reg_reg ); | |
| 9765 %} | |
| 9766 | |
| 9767 // Strict FP instruction biases argument before division then | |
| 9768 // biases result, to avoid double rounding of subnormals. | |
| 9769 // | |
| 9770 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9771 // load divisor | |
| 9772 // divide scaled dividend by divisor | |
| 9773 // rescale quotient by 2^(15360) | |
| 9774 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9775 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9776 predicate (UseSSE<=1); |
| 9777 match(Set dst (DivD dst src)); | |
| 9778 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9779 ins_cost(01); | |
| 9780 | |
| 9781 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9782 "DMULp $dst,ST\n\t" | |
| 9783 "FLD $src\n\t" | |
| 9784 "FDIVp $dst,ST\n\t" | |
| 9785 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9786 "DMULp $dst,ST\n\t" %} | |
| 9787 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9788 ins_encode( strictfp_bias1(dst), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9789 Push_Reg_DPR(src), |
| 0 | 9790 OpcP, RegOpc(dst), |
| 9791 strictfp_bias2(dst) ); | |
| 9792 ins_pipe( fpu_reg_reg ); | |
| 9793 %} | |
| 9794 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9795 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9796 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9797 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9798 | |
| 9799 format %{ "FLD $src1\n\t" | |
| 9800 "FDIV ST,$src2\n\t" | |
| 9801 "FSTP_D $dst\t# D-round" %} | |
| 9802 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9803 ins_encode( Push_Reg_DPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9804 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9805 ins_pipe( fpu_mem_reg_reg ); |
| 9806 %} | |
| 9807 | |
| 9808 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9809 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9810 predicate(UseSSE<=1); |
| 9811 match(Set dst (ModD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9812 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9813 |
| 9814 format %{ "DMOD $dst,$src" %} | |
| 9815 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9816 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9817 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9818 Push_Result_Mod_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9819 Pop_Reg_DPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9820 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9821 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9822 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9823 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9824 predicate(UseSSE>=2); |
| 9825 match(Set dst (ModD src0 src1)); | |
| 9826 effect(KILL rax, KILL cr); | |
| 9827 | |
| 9828 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9829 "\tMOVSD [ESP+0],$src1\n" | |
| 9830 "\tFLD_D [ESP+0]\n" | |
| 9831 "\tMOVSD [ESP+0],$src0\n" | |
| 9832 "\tFLD_D [ESP+0]\n" | |
| 9833 "loop:\tFPREM\n" | |
| 9834 "\tFWAIT\n" | |
| 9835 "\tFNSTSW AX\n" | |
| 9836 "\tSAHF\n" | |
| 9837 "\tJP loop\n" | |
| 9838 "\tFSTP_D [ESP+0]\n" | |
| 9839 "\tMOVSD $dst,[ESP+0]\n" | |
| 9840 "\tADD ESP,8\n" | |
| 9841 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9842 %} | |
| 9843 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9844 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9845 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9846 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9847 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9848 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9849 predicate (UseSSE<=1); |
| 9850 match(Set dst (SinD src)); | |
| 9851 ins_cost(1800); | |
| 9852 format %{ "DSIN $dst" %} | |
| 9853 opcode(0xD9, 0xFE); | |
| 9854 ins_encode( OpcP, OpcS ); | |
| 9855 ins_pipe( pipe_slow ); | |
| 9856 %} | |
| 9857 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9858 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9859 predicate (UseSSE>=2); |
| 9860 match(Set dst (SinD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9861 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9862 ins_cost(1800); |
| 9863 format %{ "DSIN $dst" %} | |
| 9864 opcode(0xD9, 0xFE); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9865 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9866 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9867 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9868 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9869 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9870 predicate (UseSSE<=1); |
| 9871 match(Set dst (CosD src)); | |
| 9872 ins_cost(1800); | |
| 9873 format %{ "DCOS $dst" %} | |
| 9874 opcode(0xD9, 0xFF); | |
| 9875 ins_encode( OpcP, OpcS ); | |
| 9876 ins_pipe( pipe_slow ); | |
| 9877 %} | |
| 9878 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9879 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9880 predicate (UseSSE>=2); |
| 9881 match(Set dst (CosD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9882 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9883 ins_cost(1800); |
| 9884 format %{ "DCOS $dst" %} | |
| 9885 opcode(0xD9, 0xFF); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9886 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9887 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9888 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9889 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9890 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9891 predicate (UseSSE<=1); |
| 9892 match(Set dst(TanD src)); | |
| 9893 format %{ "DTAN $dst" %} | |
| 9894 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9895 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9896 ins_pipe( pipe_slow ); | |
| 9897 %} | |
| 9898 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9899 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9900 predicate (UseSSE>=2); |
| 9901 match(Set dst(TanD dst)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9902 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9903 format %{ "DTAN $dst" %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9904 ins_encode( Push_SrcD(dst), |
| 0 | 9905 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9906 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9907 Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9908 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9909 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9910 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9911 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9912 predicate (UseSSE<=1); |
| 9913 match(Set dst(AtanD dst src)); | |
| 9914 format %{ "DATA $dst,$src" %} | |
| 9915 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9916 ins_encode( Push_Reg_DPR(src), |
| 0 | 9917 OpcP, OpcS, RegOpc(dst) ); |
| 9918 ins_pipe( pipe_slow ); | |
| 9919 %} | |
| 9920 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9921 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9922 predicate (UseSSE>=2); |
| 9923 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9924 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9925 format %{ "DATA $dst,$src" %} |
| 9926 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9927 ins_encode( Push_SrcD(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9928 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9929 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9930 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9931 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9932 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9933 predicate (UseSSE<=1); |
| 9934 match(Set dst (SqrtD src)); | |
| 9935 format %{ "DSQRT $dst,$src" %} | |
| 9936 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9937 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9938 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9939 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9940 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9941 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9942 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9943 predicate (UseSSE<=1); |
| 9944 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9945 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9946 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9947 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9948 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9949 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9950 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9951 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9952 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9953 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9954 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9955 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9956 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9957 predicate (UseSSE>=2); |
| 9958 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9959 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9960 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9961 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9962 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9963 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9964 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9965 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9966 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9967 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9968 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9969 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9970 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9971 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9972 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9973 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9974 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9975 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9976 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9977 predicate (UseSSE<=1); |
| 9978 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9979 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9980 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9981 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9982 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9983 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9984 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9985 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9986 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9987 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9988 predicate (UseSSE>=2); |
| 9989 match(Set dst (ExpD src)); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9990 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9991 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9992 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9993 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9994 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9995 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9996 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9997 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9998 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9999 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10000 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10001 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
10002 %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10003 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10004 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10005 predicate (UseSSE<=1); |
| 10006 // The source Double operand on FPU stack | |
| 10007 match(Set dst (Log10D src)); | |
| 10008 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10009 // fxch ; swap ST(0) with ST(1) | |
| 10010 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10011 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10012 "FXCH \n\t" | |
| 10013 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10014 %} | |
| 10015 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10016 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10017 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10018 | |
| 10019 ins_pipe( pipe_slow ); | |
| 10020 %} | |
| 10021 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10022 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10023 predicate (UseSSE>=2); |
| 10024 effect(KILL cr); | |
| 10025 match(Set dst (Log10D src)); | |
| 10026 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10027 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10028 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10029 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10030 %} | |
| 10031 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10032 Push_SrcD(src), |
| 0 | 10033 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10034 Push_ResultD(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10035 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10036 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10037 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10038 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10039 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10040 predicate (UseSSE<=1); |
| 10041 // The source Double operand on FPU stack | |
| 10042 match(Set dst (LogD src)); | |
| 10043 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10044 // fxch ; swap ST(0) with ST(1) | |
| 10045 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10046 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10047 "FXCH \n\t" | |
| 10048 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10049 %} | |
| 10050 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10051 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10052 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10053 | |
| 10054 ins_pipe( pipe_slow ); | |
| 10055 %} | |
| 10056 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10057 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10058 predicate (UseSSE>=2); |
| 10059 effect(KILL cr); | |
| 10060 // The source and result Double operands in XMM registers | |
| 10061 match(Set dst (LogD src)); | |
| 10062 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10063 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10064 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10065 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10066 %} | |
| 10067 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10068 Push_SrcD(src), |
| 0 | 10069 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10070 Push_ResultD(dst)); |
| 0 | 10071 ins_pipe( pipe_slow ); |
| 10072 %} | |
| 10073 | |
| 10074 //-------------Float Instructions------------------------------- | |
| 10075 // Float Math | |
| 10076 | |
| 10077 // Code for float compare: | |
| 10078 // fcompp(); | |
| 10079 // fwait(); fnstsw_ax(); | |
| 10080 // sahf(); | |
| 10081 // movl(dst, unordered_result); | |
| 10082 // jcc(Assembler::parity, exit); | |
| 10083 // movl(dst, less_result); | |
| 10084 // jcc(Assembler::below, exit); | |
| 10085 // movl(dst, equal_result); | |
| 10086 // jcc(Assembler::equal, exit); | |
| 10087 // movl(dst, greater_result); | |
| 10088 // exit: | |
| 10089 | |
| 10090 // P6 version of float compare, sets condition codes in EFLAGS | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10091 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10092 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10093 match(Set cr (CmpF src1 src2)); | |
| 10094 effect(KILL rax); | |
| 10095 ins_cost(150); | |
| 10096 format %{ "FLD $src1\n\t" | |
| 10097 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10098 "JNP exit\n\t" | |
| 10099 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10100 "SAHF\n" | |
| 10101 "exit:\tNOP // avoid branch to branch" %} | |
| 10102 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10103 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10104 OpcP, RegOpc(src2), |
| 10105 cmpF_P6_fixup ); | |
| 10106 ins_pipe( pipe_slow ); | |
| 10107 %} | |
| 10108 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10109 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10110 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10111 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10112 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10113 format %{ "FLD $src1\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10114 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10115 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10116 ins_encode( Push_Reg_DPR(src1), |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10117 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10118 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10119 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10120 |
| 0 | 10121 |
| 10122 // Compare & branch | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10123 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10124 predicate(UseSSE == 0); |
| 10125 match(Set cr (CmpF src1 src2)); | |
| 10126 effect(KILL rax); | |
| 10127 ins_cost(200); | |
| 10128 format %{ "FLD $src1\n\t" | |
| 10129 "FCOMp $src2\n\t" | |
| 10130 "FNSTSW AX\n\t" | |
| 10131 "TEST AX,0x400\n\t" | |
| 10132 "JZ,s flags\n\t" | |
| 10133 "MOV AH,1\t# unordered treat as LT\n" | |
| 10134 "flags:\tSAHF" %} | |
| 10135 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10136 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10137 OpcP, RegOpc(src2), |
| 10138 fpu_flags); | |
| 10139 ins_pipe( pipe_slow ); | |
| 10140 %} | |
| 10141 | |
| 10142 // Compare vs zero into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10143 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10144 predicate(UseSSE == 0); |
| 10145 match(Set dst (CmpF3 src1 zero)); | |
| 10146 effect(KILL cr, KILL rax); | |
| 10147 ins_cost(280); | |
| 10148 format %{ "FTSTF $dst,$src1" %} | |
| 10149 opcode(0xE4, 0xD9); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10150 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10151 OpcS, OpcP, PopFPU, |
| 10152 CmpF_Result(dst)); | |
| 10153 ins_pipe( pipe_slow ); | |
| 10154 %} | |
| 10155 | |
| 10156 // Compare into -1,0,1 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
10157 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10158 predicate(UseSSE == 0); |
| 10159 match(Set dst (CmpF3 src1 src2)); | |
| 10160 effect(KILL cr, KILL rax); | |
| 10161 ins_cost(300); | |
| 10162 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10163 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10164 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10165 OpcP, RegOpc(src2), |
| 10166 CmpF_Result(dst)); | |
| 10167 ins_pipe( pipe_slow ); | |
| 10168 %} | |
| 10169 | |
| 10170 // float compare and set condition codes in EFLAGS by XMM regs | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10171 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10172 predicate(UseSSE>=1); |
| 4759 | 10173 match(Set cr (CmpF src1 src2)); |
| 0 | 10174 ins_cost(145); |
| 4759 | 10175 format %{ "UCOMISS $src1,$src2\n\t" |
| 10176 "JNP,s exit\n\t" | |
| 10177 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10178 "AND [rsp], #0xffffff2b\n\t" | |
| 10179 "POPF\n" | |
| 10180 "exit:" %} | |
| 10181 ins_encode %{ | |
| 10182 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10183 emit_cmpfp_fixup(_masm); | |
| 10184 %} | |
| 10185 ins_pipe( pipe_slow ); | |
| 10186 %} | |
| 10187 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10188 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10189 predicate(UseSSE>=1); |
| 4759 | 10190 match(Set cr (CmpF src1 src2)); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10191 ins_cost(100); |
| 4759 | 10192 format %{ "UCOMISS $src1,$src2" %} |
| 10193 ins_encode %{ | |
| 10194 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10195 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10196 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10197 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10198 |
| 0 | 10199 // float compare and set condition codes in EFLAGS by XMM regs |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10200 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10201 predicate(UseSSE>=1); |
| 4759 | 10202 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10203 ins_cost(165); |
| 4759 | 10204 format %{ "UCOMISS $src1,$src2\n\t" |
| 10205 "JNP,s exit\n\t" | |
| 10206 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10207 "AND [rsp], #0xffffff2b\n\t" | |
| 10208 "POPF\n" | |
| 10209 "exit:" %} | |
| 10210 ins_encode %{ | |
| 10211 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10212 emit_cmpfp_fixup(_masm); | |
| 10213 %} | |
| 10214 ins_pipe( pipe_slow ); | |
| 10215 %} | |
| 10216 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10217 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10218 predicate(UseSSE>=1); |
| 4759 | 10219 match(Set cr (CmpF src1 (LoadF src2))); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10220 ins_cost(100); |
| 4759 | 10221 format %{ "UCOMISS $src1,$src2" %} |
| 10222 ins_encode %{ | |
| 10223 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10224 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10225 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10226 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10227 |
| 0 | 10228 // Compare into -1,0,1 in XMM |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10229 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10230 predicate(UseSSE>=1); |
| 10231 match(Set dst (CmpF3 src1 src2)); | |
| 10232 effect(KILL cr); | |
| 10233 ins_cost(255); | |
| 4759 | 10234 format %{ "UCOMISS $src1, $src2\n\t" |
| 10235 "MOV $dst, #-1\n\t" | |
| 10236 "JP,s done\n\t" | |
| 10237 "JB,s done\n\t" | |
| 10238 "SETNE $dst\n\t" | |
| 10239 "MOVZB $dst, $dst\n" | |
| 10240 "done:" %} | |
| 10241 ins_encode %{ | |
| 10242 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10243 emit_cmpfp3(_masm, $dst$$Register); | |
| 10244 %} | |
| 0 | 10245 ins_pipe( pipe_slow ); |
| 10246 %} | |
| 10247 | |
| 10248 // Compare into -1,0,1 in XMM and memory | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10249 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10250 predicate(UseSSE>=1); |
| 4759 | 10251 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10252 effect(KILL cr); |
| 10253 ins_cost(275); | |
| 4759 | 10254 format %{ "UCOMISS $src1, $src2\n\t" |
| 10255 "MOV $dst, #-1\n\t" | |
| 10256 "JP,s done\n\t" | |
| 10257 "JB,s done\n\t" | |
| 10258 "SETNE $dst\n\t" | |
| 10259 "MOVZB $dst, $dst\n" | |
| 10260 "done:" %} | |
| 10261 ins_encode %{ | |
| 10262 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10263 emit_cmpfp3(_masm, $dst$$Register); | |
| 10264 %} | |
| 0 | 10265 ins_pipe( pipe_slow ); |
| 10266 %} | |
| 10267 | |
| 10268 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10269 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10270 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10271 match(Set dst (SubF src1 src2)); | |
| 10272 | |
| 10273 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10274 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10275 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10276 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10277 Pop_Mem_FPR(dst) ); |
| 0 | 10278 ins_pipe( fpu_mem_reg_reg ); |
| 10279 %} | |
| 10280 // | |
| 10281 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10282 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10283 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10284 match(Set dst (SubF dst src)); | |
| 10285 | |
| 10286 format %{ "FSUB $dst,$src" %} | |
| 10287 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10288 ins_encode( Push_Reg_FPR(src), |
| 0 | 10289 OpcP, RegOpc(dst) ); |
| 10290 ins_pipe( fpu_reg_reg ); | |
| 10291 %} | |
| 10292 | |
| 10293 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10294 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10295 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10296 match(Set dst (AddF src1 src2)); | |
| 10297 | |
| 10298 format %{ "FADD $dst,$src1,$src2" %} | |
| 10299 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10300 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10301 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10302 Pop_Mem_FPR(dst) ); |
| 0 | 10303 ins_pipe( fpu_mem_reg_reg ); |
| 10304 %} | |
| 10305 // | |
| 10306 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10307 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10308 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10309 match(Set dst (AddF dst src)); | |
| 10310 | |
| 10311 format %{ "FLD $src\n\t" | |
| 10312 "FADDp $dst,ST" %} | |
| 10313 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10314 ins_encode( Push_Reg_FPR(src), |
| 0 | 10315 OpcP, RegOpc(dst) ); |
| 10316 ins_pipe( fpu_reg_reg ); | |
| 10317 %} | |
| 10318 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10319 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10320 predicate(UseSSE==0); |
| 10321 match(Set dst (AbsF src)); | |
| 10322 ins_cost(100); | |
| 10323 format %{ "FABS" %} | |
| 10324 opcode(0xE1, 0xD9); | |
| 10325 ins_encode( OpcS, OpcP ); | |
| 10326 ins_pipe( fpu_reg_reg ); | |
| 10327 %} | |
| 10328 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10329 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10330 predicate(UseSSE==0); |
| 10331 match(Set dst (NegF src)); | |
| 10332 ins_cost(100); | |
| 10333 format %{ "FCHS" %} | |
| 10334 opcode(0xE0, 0xD9); | |
| 10335 ins_encode( OpcS, OpcP ); | |
| 10336 ins_pipe( fpu_reg_reg ); | |
| 10337 %} | |
| 10338 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10339 // Cisc-alternate to addFPR_reg |
| 0 | 10340 // Spill to obtain 24-bit precision |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10341 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10342 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10343 match(Set dst (AddF src1 (LoadF src2))); | |
| 10344 | |
| 10345 format %{ "FLD $src2\n\t" | |
| 10346 "FADD ST,$src1\n\t" | |
| 10347 "FSTP_S $dst" %} | |
| 10348 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10349 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10350 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10351 Pop_Mem_FPR(dst) ); |
| 0 | 10352 ins_pipe( fpu_mem_reg_mem ); |
| 10353 %} | |
| 10354 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10355 // Cisc-alternate to addFPR_reg |
| 0 | 10356 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10357 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10358 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10359 match(Set dst (AddF dst (LoadF src))); | |
| 10360 | |
| 10361 format %{ "FADD $dst,$src" %} | |
| 10362 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10363 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10364 OpcP, RegOpc(dst) ); | |
| 10365 ins_pipe( fpu_reg_mem ); | |
| 10366 %} | |
| 10367 | |
| 10368 // // Following two instructions for _222_mpegaudio | |
| 10369 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10370 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10371 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10372 match(Set dst (AddF src1 src2)); | |
| 10373 | |
| 10374 format %{ "FADD $dst,$src1,$src2" %} | |
| 10375 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10376 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10377 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10378 Pop_Mem_FPR(dst) ); |
| 0 | 10379 ins_pipe( fpu_mem_reg_mem ); |
| 10380 %} | |
| 10381 | |
| 10382 // Cisc-spill variant | |
| 10383 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10384 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10385 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10386 match(Set dst (AddF src1 (LoadF src2))); | |
| 10387 | |
| 10388 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10389 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10390 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10391 set_instruction_start, | |
| 10392 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10393 Pop_Mem_FPR(dst) ); |
| 0 | 10394 ins_pipe( fpu_mem_mem_mem ); |
| 10395 %} | |
| 10396 | |
| 10397 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10398 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10399 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10400 match(Set dst (AddF src1 src2)); | |
| 10401 | |
| 10402 format %{ "FADD $dst,$src1,$src2" %} | |
| 10403 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10404 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10405 set_instruction_start, | |
| 10406 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10407 Pop_Mem_FPR(dst) ); |
| 0 | 10408 ins_pipe( fpu_mem_mem_mem ); |
| 10409 %} | |
| 10410 | |
| 10411 | |
| 10412 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10413 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10414 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10415 match(Set dst (AddF src con)); |
| 10416 format %{ "FLD $src\n\t" | |
| 10417 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10418 "FSTP_S $dst" %} |
| 2008 | 10419 ins_encode %{ |
| 10420 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10421 __ fadd_s($constantaddress($con)); | |
| 10422 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10423 %} | |
| 10424 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10425 %} |
| 10426 // | |
| 10427 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10428 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10429 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10430 match(Set dst (AddF src con)); |
| 10431 format %{ "FLD $src\n\t" | |
| 10432 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10433 "FSTP $dst" %} | |
| 10434 ins_encode %{ | |
| 10435 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10436 __ fadd_s($constantaddress($con)); | |
| 10437 __ fstp_d($dst$$reg); | |
| 10438 %} | |
| 10439 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10440 %} |
| 10441 | |
| 10442 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10443 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10444 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10445 match(Set dst (MulF src1 src2)); | |
| 10446 | |
| 10447 format %{ "FLD $src1\n\t" | |
| 10448 "FMUL $src2\n\t" | |
| 10449 "FSTP_S $dst" %} | |
| 10450 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10451 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10452 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10453 Pop_Mem_FPR(dst) ); |
| 0 | 10454 ins_pipe( fpu_mem_reg_reg ); |
| 10455 %} | |
| 10456 // | |
| 10457 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10458 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10459 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10460 match(Set dst (MulF src1 src2)); | |
| 10461 | |
| 10462 format %{ "FLD $src1\n\t" | |
| 10463 "FMUL $src2\n\t" | |
| 10464 "FSTP_S $dst" %} | |
| 10465 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10466 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10467 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10468 Pop_Reg_FPR(dst) ); |
| 0 | 10469 ins_pipe( fpu_reg_reg_reg ); |
| 10470 %} | |
| 10471 | |
| 10472 | |
| 10473 // Spill to obtain 24-bit precision | |
| 10474 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10475 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10476 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10477 match(Set dst (MulF src1 (LoadF src2))); | |
| 10478 | |
| 10479 format %{ "FLD_S $src2\n\t" | |
| 10480 "FMUL $src1\n\t" | |
| 10481 "FSTP_S $dst" %} | |
| 10482 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10483 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10484 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10485 Pop_Mem_FPR(dst) ); |
| 0 | 10486 ins_pipe( fpu_mem_reg_mem ); |
| 10487 %} | |
| 10488 // | |
| 10489 // This instruction does not round to 24-bits | |
| 10490 // Cisc-alternate to reg-reg multiply | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10491 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10492 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10493 match(Set dst (MulF src1 (LoadF src2))); | |
| 10494 | |
| 10495 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10496 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10497 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10498 OpcReg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10499 Pop_Reg_FPR(dst) ); |
| 0 | 10500 ins_pipe( fpu_reg_reg_mem ); |
| 10501 %} | |
| 10502 | |
| 10503 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10504 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10505 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10506 match(Set dst (MulF src1 src2)); | |
| 10507 | |
| 10508 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10509 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10510 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10511 set_instruction_start, | |
| 10512 OpcP, RMopc_Mem(secondary,src1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10513 Pop_Mem_FPR(dst) ); |
| 0 | 10514 ins_pipe( fpu_mem_mem_mem ); |
| 10515 %} | |
| 10516 | |
| 10517 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10518 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10519 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10520 match(Set dst (MulF src con)); |
| 10521 | |
| 10522 format %{ "FLD $src\n\t" | |
| 10523 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10524 "FSTP_S $dst" %} | |
| 10525 ins_encode %{ | |
| 10526 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10527 __ fmul_s($constantaddress($con)); | |
| 10528 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10529 %} | |
| 10530 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10531 %} |
| 10532 // | |
| 10533 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10534 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10535 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10536 match(Set dst (MulF src con)); |
| 10537 | |
| 10538 format %{ "FLD $src\n\t" | |
| 10539 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10540 "FSTP $dst" %} | |
| 10541 ins_encode %{ | |
| 10542 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10543 __ fmul_s($constantaddress($con)); | |
| 10544 __ fstp_d($dst$$reg); | |
| 10545 %} | |
| 10546 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10547 %} |
| 10548 | |
| 10549 | |
| 10550 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10551 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10552 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10553 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10554 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10555 match(Set dst (MulF (LoadF mem1) src)); | |
| 10556 | |
| 10557 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10558 "FMUL ST,$src\n\t" | |
| 10559 "FSTP $dst" %} | |
| 10560 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10561 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10562 OpcReg_FPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10563 Pop_Reg_FPR(dst) ); |
| 0 | 10564 ins_pipe( fpu_reg_reg_mem ); |
| 10565 %} | |
| 10566 // | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10567 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10568 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10569 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10570 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10571 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10572 ins_cost(95); | |
| 10573 | |
| 10574 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10575 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10576 "FADD ST,$src2\n\t" |
| 10577 "FSTP $dst" %} | |
| 10578 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10579 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10580 FMul_ST_reg(src1), | |
| 10581 FAdd_ST_reg(src2), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10582 Pop_Reg_FPR(dst) ); |
| 0 | 10583 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10584 %} | |
| 10585 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10586 // MACRO3 -- addFPR a mulFPR |
| 0 | 10587 // This instruction does not round to 24-bits. It is a '2-address' |
| 10588 // instruction in that the result goes back to src2. This eliminates | |
| 10589 // a move from the macro; possibly the register allocator will have | |
| 10590 // to add it back (and maybe not). | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10591 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10592 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10593 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10594 | |
| 10595 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10596 "FMUL ST,$src1\n\t" | |
| 10597 "FADDP $src2,ST" %} | |
| 10598 opcode(0xD9); /* LoadF D9 /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10599 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10600 FMul_ST_reg(src1), |
| 10601 FAddP_reg_ST(src2) ); | |
| 10602 ins_pipe( fpu_reg_reg_reg ); | |
| 10603 %} | |
| 10604 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10605 // MACRO4 -- divFPR subFPR |
| 0 | 10606 // This instruction does not round to 24-bits |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10607 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10608 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10609 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10610 | |
| 10611 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10612 "FSUB ST,$src1\n\t" | |
| 10613 "FDIV ST,$src3\n\t" | |
| 10614 "FSTP $dst" %} | |
| 10615 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10616 ins_encode( Push_Reg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10617 subFPR_divFPR_encode(src1,src3), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10618 Pop_Reg_FPR(dst) ); |
| 0 | 10619 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10620 %} | |
| 10621 | |
| 10622 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10623 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10624 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10625 match(Set dst (DivF src1 src2)); | |
| 10626 | |
| 10627 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10628 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10629 ins_encode( Push_Reg_FPR(src1), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10630 OpcReg_FPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10631 Pop_Mem_FPR(dst) ); |
| 0 | 10632 ins_pipe( fpu_mem_reg_reg ); |
| 10633 %} | |
| 10634 // | |
| 10635 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10636 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10637 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10638 match(Set dst (DivF dst src)); | |
| 10639 | |
| 10640 format %{ "FDIV $dst,$src" %} | |
| 10641 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10642 ins_encode( Push_Reg_FPR(src), |
| 0 | 10643 OpcP, RegOpc(dst) ); |
| 10644 ins_pipe( fpu_reg_reg ); | |
| 10645 %} | |
| 10646 | |
| 10647 | |
| 10648 // Spill to obtain 24-bit precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10649 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10650 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10651 match(Set dst (ModF src1 src2)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10652 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10653 |
| 10654 format %{ "FMOD $dst,$src1,$src2" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10655 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10656 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10657 Push_Result_Mod_DPR(src2), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10658 Pop_Mem_FPR(dst)); |
| 0 | 10659 ins_pipe( pipe_slow ); |
| 10660 %} | |
| 10661 // | |
| 10662 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10663 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10664 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10665 match(Set dst (ModF dst src)); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10666 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10667 |
| 10668 format %{ "FMOD $dst,$src" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10669 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10670 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10671 Push_Result_Mod_DPR(src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10672 Pop_Reg_FPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10673 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10674 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10675 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10676 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10677 predicate(UseSSE>=1); |
| 10678 match(Set dst (ModF src0 src1)); | |
| 10679 effect(KILL rax, KILL cr); | |
| 10680 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10681 "\tMOVSS [ESP+0],$src1\n" | |
| 10682 "\tFLD_S [ESP+0]\n" | |
| 10683 "\tMOVSS [ESP+0],$src0\n" | |
| 10684 "\tFLD_S [ESP+0]\n" | |
| 10685 "loop:\tFPREM\n" | |
| 10686 "\tFWAIT\n" | |
| 10687 "\tFNSTSW AX\n" | |
| 10688 "\tSAHF\n" | |
| 10689 "\tJP loop\n" | |
| 10690 "\tFSTP_S [ESP+0]\n" | |
| 10691 "\tMOVSS $dst,[ESP+0]\n" | |
| 10692 "\tADD ESP,4\n" | |
| 10693 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10694 %} | |
| 10695 ins_cost(250); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10696 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10697 ins_pipe( pipe_slow ); |
| 10698 %} | |
| 10699 | |
| 10700 | |
| 10701 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10702 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10703 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10704 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10705 predicate(UseSSE==0); |
| 10706 match(Set dst (RoundFloat src)); | |
| 10707 ins_cost(125); | |
| 10708 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10709 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10710 ins_pipe( fpu_mem_reg ); |
| 10711 %} | |
| 10712 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10713 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10714 predicate(UseSSE<=1); |
| 10715 match(Set dst (RoundDouble src)); | |
| 10716 ins_cost(125); | |
| 10717 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10718 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10719 ins_pipe( fpu_mem_reg ); |
| 10720 %} | |
| 10721 | |
| 10722 // Force rounding to 24-bit precision and 6-bit exponent | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10723 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10724 predicate(UseSSE==0); |
| 10725 match(Set dst (ConvD2F src)); | |
| 10726 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10727 expand %{ | |
| 10728 roundFloat_mem_reg(dst,src); | |
| 10729 %} | |
| 10730 %} | |
| 10731 | |
| 10732 // Force rounding to 24-bit precision and 6-bit exponent | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10733 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10734 predicate(UseSSE==1); |
| 10735 match(Set dst (ConvD2F src)); | |
| 10736 effect( KILL cr ); | |
| 10737 format %{ "SUB ESP,4\n\t" | |
| 10738 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10739 "MOVSS $dst,[ESP]\n\t" | |
| 10740 "ADD ESP,4" %} | |
| 4759 | 10741 ins_encode %{ |
| 10742 __ subptr(rsp, 4); | |
| 10743 if ($src$$reg != FPR1L_enc) { | |
| 10744 __ fld_s($src$$reg-1); | |
| 10745 __ fstp_s(Address(rsp, 0)); | |
| 10746 } else { | |
| 10747 __ fst_s(Address(rsp, 0)); | |
| 10748 } | |
| 10749 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10750 __ addptr(rsp, 4); | |
| 10751 %} | |
| 0 | 10752 ins_pipe( pipe_slow ); |
| 10753 %} | |
| 10754 | |
| 10755 // Force rounding double precision to single precision | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10756 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10757 predicate(UseSSE>=2); |
| 10758 match(Set dst (ConvD2F src)); | |
| 10759 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10760 ins_encode %{ |
| 10761 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10762 %} | |
| 0 | 10763 ins_pipe( pipe_slow ); |
| 10764 %} | |
| 10765 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10766 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10767 predicate(UseSSE==0); |
| 10768 match(Set dst (ConvF2D src)); | |
| 10769 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10770 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10771 ins_pipe( fpu_reg_reg ); |
| 10772 %} | |
| 10773 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10774 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10775 predicate(UseSSE==1); |
| 10776 match(Set dst (ConvF2D src)); | |
| 10777 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10778 expand %{ | |
| 10779 roundDouble_mem_reg(dst,src); | |
| 10780 %} | |
| 10781 %} | |
| 10782 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10783 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10784 predicate(UseSSE==1); |
| 10785 match(Set dst (ConvF2D src)); | |
| 10786 effect( KILL cr ); | |
| 10787 format %{ "SUB ESP,4\n\t" | |
| 10788 "MOVSS [ESP] $src\n\t" | |
| 10789 "FLD_S [ESP]\n\t" | |
| 10790 "ADD ESP,4\n\t" | |
| 10791 "FSTP $dst\t# D-round" %} | |
| 4759 | 10792 ins_encode %{ |
| 10793 __ subptr(rsp, 4); | |
| 10794 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10795 __ fld_s(Address(rsp, 0)); | |
| 10796 __ addptr(rsp, 4); | |
| 10797 __ fstp_d($dst$$reg); | |
| 10798 %} | |
| 0 | 10799 ins_pipe( pipe_slow ); |
| 10800 %} | |
| 10801 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10802 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10803 predicate(UseSSE>=2); |
| 10804 match(Set dst (ConvF2D src)); | |
| 10805 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10806 ins_encode %{ |
| 10807 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10808 %} | |
| 0 | 10809 ins_pipe( pipe_slow ); |
| 10810 %} | |
| 10811 | |
| 10812 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10813 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10814 predicate(UseSSE<=1); |
| 10815 match(Set dst (ConvD2I src)); | |
| 10816 effect( KILL tmp, KILL cr ); | |
| 10817 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10818 "FLDCW trunc mode\n\t" | |
| 10819 "SUB ESP,4\n\t" | |
| 10820 "FISTp [ESP + #0]\n\t" | |
| 10821 "FLDCW std/24-bit mode\n\t" | |
| 10822 "POP EAX\n\t" | |
| 10823 "CMP EAX,0x80000000\n\t" | |
| 10824 "JNE,s fast\n\t" | |
| 10825 "FLD_D $src\n\t" | |
| 10826 "CALL d2i_wrapper\n" | |
| 10827 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10828 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10829 ins_pipe( pipe_slow ); |
| 10830 %} | |
| 10831 | |
| 10832 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10833 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10834 predicate(UseSSE>=2); |
| 10835 match(Set dst (ConvD2I src)); | |
| 10836 effect( KILL tmp, KILL cr ); | |
| 10837 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10838 "CMP $dst,0x80000000\n\t" | |
| 10839 "JNE,s fast\n\t" | |
| 10840 "SUB ESP, 8\n\t" | |
| 10841 "MOVSD [ESP], $src\n\t" | |
| 10842 "FLD_D [ESP]\n\t" | |
| 10843 "ADD ESP, 8\n\t" | |
| 10844 "CALL d2i_wrapper\n" | |
| 10845 "fast:" %} | |
| 4759 | 10846 ins_encode %{ |
| 10847 Label fast; | |
| 10848 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10849 __ cmpl($dst$$Register, 0x80000000); | |
| 10850 __ jccb(Assembler::notEqual, fast); | |
| 10851 __ subptr(rsp, 8); | |
| 10852 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10853 __ fld_d(Address(rsp, 0)); | |
| 10854 __ addptr(rsp, 8); | |
| 10855 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10856 __ bind(fast); | |
| 10857 %} | |
| 0 | 10858 ins_pipe( pipe_slow ); |
| 10859 %} | |
| 10860 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10861 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10862 predicate(UseSSE<=1); |
| 10863 match(Set dst (ConvD2L src)); | |
| 10864 effect( KILL cr ); | |
| 10865 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10866 "FLDCW trunc mode\n\t" | |
| 10867 "SUB ESP,8\n\t" | |
| 10868 "FISTp [ESP + #0]\n\t" | |
| 10869 "FLDCW std/24-bit mode\n\t" | |
| 10870 "POP EAX\n\t" | |
| 10871 "POP EDX\n\t" | |
| 10872 "CMP EDX,0x80000000\n\t" | |
| 10873 "JNE,s fast\n\t" | |
| 10874 "TEST EAX,EAX\n\t" | |
| 10875 "JNE,s fast\n\t" | |
| 10876 "FLD $src\n\t" | |
| 10877 "CALL d2l_wrapper\n" | |
| 10878 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10879 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10880 ins_pipe( pipe_slow ); |
| 10881 %} | |
| 10882 | |
| 10883 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10884 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10885 predicate (UseSSE>=2); |
| 10886 match(Set dst (ConvD2L src)); | |
| 10887 effect( KILL cr ); | |
| 10888 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10889 "MOVSD [ESP],$src\n\t" | |
| 10890 "FLD_D [ESP]\n\t" | |
| 10891 "FLDCW trunc mode\n\t" | |
| 10892 "FISTp [ESP + #0]\n\t" | |
| 10893 "FLDCW std/24-bit mode\n\t" | |
| 10894 "POP EAX\n\t" | |
| 10895 "POP EDX\n\t" | |
| 10896 "CMP EDX,0x80000000\n\t" | |
| 10897 "JNE,s fast\n\t" | |
| 10898 "TEST EAX,EAX\n\t" | |
| 10899 "JNE,s fast\n\t" | |
| 10900 "SUB ESP,8\n\t" | |
| 10901 "MOVSD [ESP],$src\n\t" | |
| 10902 "FLD_D [ESP]\n\t" | |
| 4759 | 10903 "ADD ESP,8\n\t" |
| 0 | 10904 "CALL d2l_wrapper\n" |
| 10905 "fast:" %} | |
| 4759 | 10906 ins_encode %{ |
| 10907 Label fast; | |
| 10908 __ subptr(rsp, 8); | |
| 10909 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10910 __ fld_d(Address(rsp, 0)); | |
| 10911 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10912 __ fistp_d(Address(rsp, 0)); | |
| 10913 // Restore the rounding mode, mask the exception | |
| 10914 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10915 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10916 } else { | |
| 10917 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10918 } | |
| 10919 // Load the converted long, adjust CPU stack | |
| 10920 __ pop(rax); | |
| 10921 __ pop(rdx); | |
| 10922 __ cmpl(rdx, 0x80000000); | |
| 10923 __ jccb(Assembler::notEqual, fast); | |
| 10924 __ testl(rax, rax); | |
| 10925 __ jccb(Assembler::notEqual, fast); | |
| 10926 __ subptr(rsp, 8); | |
| 10927 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10928 __ fld_d(Address(rsp, 0)); | |
| 10929 __ addptr(rsp, 8); | |
| 10930 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10931 __ bind(fast); | |
| 10932 %} | |
| 0 | 10933 ins_pipe( pipe_slow ); |
| 10934 %} | |
| 10935 | |
| 10936 // Convert a double to an int. Java semantics require we do complex | |
| 10937 // manglations in the corner cases. So we set the rounding mode to | |
| 10938 // 'zero', store the darned double down as an int, and reset the | |
| 10939 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10940 // if we would overflow or converted a NAN; we check for this and | |
| 10941 // and go the slow path if needed. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10942 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10943 predicate(UseSSE==0); |
| 10944 match(Set dst (ConvF2I src)); | |
| 10945 effect( KILL tmp, KILL cr ); | |
| 10946 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10947 "FLDCW trunc mode\n\t" | |
| 10948 "SUB ESP,4\n\t" | |
| 10949 "FISTp [ESP + #0]\n\t" | |
| 10950 "FLDCW std/24-bit mode\n\t" | |
| 10951 "POP EAX\n\t" | |
| 10952 "CMP EAX,0x80000000\n\t" | |
| 10953 "JNE,s fast\n\t" | |
| 10954 "FLD $src\n\t" | |
| 10955 "CALL d2i_wrapper\n" | |
| 10956 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10957 // DPR2I_encoding works for FPR2I |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10958 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10959 ins_pipe( pipe_slow ); |
| 10960 %} | |
| 10961 | |
| 10962 // Convert a float in xmm to an int reg. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10963 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10964 predicate(UseSSE>=1); |
| 10965 match(Set dst (ConvF2I src)); | |
| 10966 effect( KILL tmp, KILL cr ); | |
| 10967 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10968 "CMP $dst,0x80000000\n\t" | |
| 10969 "JNE,s fast\n\t" | |
| 10970 "SUB ESP, 4\n\t" | |
| 10971 "MOVSS [ESP], $src\n\t" | |
| 10972 "FLD [ESP]\n\t" | |
| 10973 "ADD ESP, 4\n\t" | |
| 10974 "CALL d2i_wrapper\n" | |
| 10975 "fast:" %} | |
| 4759 | 10976 ins_encode %{ |
| 10977 Label fast; | |
| 10978 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10979 __ cmpl($dst$$Register, 0x80000000); | |
| 10980 __ jccb(Assembler::notEqual, fast); | |
| 10981 __ subptr(rsp, 4); | |
| 10982 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10983 __ fld_s(Address(rsp, 0)); | |
| 10984 __ addptr(rsp, 4); | |
| 10985 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10986 __ bind(fast); | |
| 10987 %} | |
| 0 | 10988 ins_pipe( pipe_slow ); |
| 10989 %} | |
| 10990 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10991 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10992 predicate(UseSSE==0); |
| 10993 match(Set dst (ConvF2L src)); | |
| 10994 effect( KILL cr ); | |
| 10995 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10996 "FLDCW trunc mode\n\t" | |
| 10997 "SUB ESP,8\n\t" | |
| 10998 "FISTp [ESP + #0]\n\t" | |
| 10999 "FLDCW std/24-bit mode\n\t" | |
| 11000 "POP EAX\n\t" | |
| 11001 "POP EDX\n\t" | |
| 11002 "CMP EDX,0x80000000\n\t" | |
| 11003 "JNE,s fast\n\t" | |
| 11004 "TEST EAX,EAX\n\t" | |
| 11005 "JNE,s fast\n\t" | |
| 11006 "FLD $src\n\t" | |
| 11007 "CALL d2l_wrapper\n" | |
| 11008 "fast:" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11009 // DPR2L_encoding works for FPR2L |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11010 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 11011 ins_pipe( pipe_slow ); |
| 11012 %} | |
| 11013 | |
| 11014 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11015 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 11016 predicate (UseSSE>=1); |
| 11017 match(Set dst (ConvF2L src)); | |
| 11018 effect( KILL cr ); | |
| 11019 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11020 "MOVSS [ESP],$src\n\t" | |
| 11021 "FLD_S [ESP]\n\t" | |
| 11022 "FLDCW trunc mode\n\t" | |
| 11023 "FISTp [ESP + #0]\n\t" | |
| 11024 "FLDCW std/24-bit mode\n\t" | |
| 11025 "POP EAX\n\t" | |
| 11026 "POP EDX\n\t" | |
| 11027 "CMP EDX,0x80000000\n\t" | |
| 11028 "JNE,s fast\n\t" | |
| 11029 "TEST EAX,EAX\n\t" | |
| 11030 "JNE,s fast\n\t" | |
| 11031 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11032 "MOVSS [ESP],$src\n\t" | |
| 11033 "FLD_S [ESP]\n\t" | |
| 11034 "ADD ESP,4\n\t" | |
| 11035 "CALL d2l_wrapper\n" | |
| 11036 "fast:" %} | |
| 4759 | 11037 ins_encode %{ |
| 11038 Label fast; | |
| 11039 __ subptr(rsp, 8); | |
| 11040 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11041 __ fld_s(Address(rsp, 0)); | |
| 11042 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11043 __ fistp_d(Address(rsp, 0)); | |
| 11044 // Restore the rounding mode, mask the exception | |
| 11045 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11046 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11047 } else { | |
| 11048 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11049 } | |
| 11050 // Load the converted long, adjust CPU stack | |
| 11051 __ pop(rax); | |
| 11052 __ pop(rdx); | |
| 11053 __ cmpl(rdx, 0x80000000); | |
| 11054 __ jccb(Assembler::notEqual, fast); | |
| 11055 __ testl(rax, rax); | |
| 11056 __ jccb(Assembler::notEqual, fast); | |
| 11057 __ subptr(rsp, 4); | |
| 11058 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11059 __ fld_s(Address(rsp, 0)); | |
| 11060 __ addptr(rsp, 4); | |
| 11061 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11062 __ bind(fast); | |
| 11063 %} | |
| 0 | 11064 ins_pipe( pipe_slow ); |
| 11065 %} | |
| 11066 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11067 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11068 predicate( UseSSE<=1 ); |
| 11069 match(Set dst (ConvI2D src)); | |
| 11070 format %{ "FILD $src\n\t" | |
| 11071 "FSTP $dst" %} | |
| 11072 opcode(0xDB, 0x0); /* DB /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11073 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11074 ins_pipe( fpu_reg_mem ); |
| 11075 %} | |
| 11076 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11077 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11078 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11079 match(Set dst (ConvI2D src)); |
| 11080 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11081 ins_encode %{ |
| 11082 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11083 %} | |
| 0 | 11084 ins_pipe( pipe_slow ); |
| 11085 %} | |
| 11086 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11087 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11088 predicate( UseSSE>=2 ); |
| 11089 match(Set dst (ConvI2D (LoadI mem))); | |
| 11090 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11091 ins_encode %{ |
| 11092 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11093 %} | |
| 0 | 11094 ins_pipe( pipe_slow ); |
| 11095 %} | |
| 11096 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11097 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11098 %{ |
| 11099 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11100 match(Set dst (ConvI2D src)); | |
| 11101 | |
| 11102 format %{ "MOVD $dst,$src\n\t" | |
| 11103 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11104 ins_encode %{ | |
| 304 | 11105 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11106 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11107 %} | |
| 11108 ins_pipe(pipe_slow); // XXX | |
| 11109 %} | |
| 11110 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11111 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11112 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11113 match(Set dst (ConvI2D (LoadI mem))); | |
| 11114 format %{ "FILD $mem\n\t" | |
| 11115 "FSTP $dst" %} | |
| 11116 opcode(0xDB); /* DB /0 */ | |
| 11117 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11118 Pop_Reg_DPR(dst)); |
| 0 | 11119 ins_pipe( fpu_reg_mem ); |
| 11120 %} | |
| 11121 | |
| 11122 // Convert a byte to a float; no rounding step needed. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11123 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11124 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11125 match(Set dst (ConvI2F src)); | |
| 11126 format %{ "FILD $src\n\t" | |
| 11127 "FSTP $dst" %} | |
| 11128 | |
| 11129 opcode(0xDB, 0x0); /* DB /0 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11130 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11131 ins_pipe( fpu_reg_mem ); |
| 11132 %} | |
| 11133 | |
| 11134 // In 24-bit mode, force exponent rounding by storing back out | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11135 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11136 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11137 match(Set dst (ConvI2F src)); | |
| 11138 ins_cost(200); | |
| 11139 format %{ "FILD $src\n\t" | |
| 11140 "FSTP_S $dst" %} | |
| 11141 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11142 ins_encode( Push_Mem_I(src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11143 Pop_Mem_FPR(dst)); |
| 0 | 11144 ins_pipe( fpu_mem_mem ); |
| 11145 %} | |
| 11146 | |
| 11147 // In 24-bit mode, force exponent rounding by storing back out | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11148 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11149 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11150 match(Set dst (ConvI2F (LoadI mem))); | |
| 11151 ins_cost(200); | |
| 11152 format %{ "FILD $mem\n\t" | |
| 11153 "FSTP_S $dst" %} | |
| 11154 opcode(0xDB); /* DB /0 */ | |
| 11155 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11156 Pop_Mem_FPR(dst)); |
| 0 | 11157 ins_pipe( fpu_mem_mem ); |
| 11158 %} | |
| 11159 | |
| 11160 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11161 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11162 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11163 match(Set dst (ConvI2F src)); | |
| 11164 format %{ "FILD $src\n\t" | |
| 11165 "FSTP $dst" %} | |
| 11166 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11167 ins_encode( Push_Mem_I(src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11168 Pop_Reg_FPR(dst)); |
| 0 | 11169 ins_pipe( fpu_reg_mem ); |
| 11170 %} | |
| 11171 | |
| 11172 // This instruction does not round to 24-bits | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11173 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11174 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11175 match(Set dst (ConvI2F (LoadI mem))); | |
| 11176 format %{ "FILD $mem\n\t" | |
| 11177 "FSTP $dst" %} | |
| 11178 opcode(0xDB); /* DB /0 */ | |
| 11179 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11180 Pop_Reg_FPR(dst)); |
| 0 | 11181 ins_pipe( fpu_reg_mem ); |
| 11182 %} | |
| 11183 | |
| 11184 // Convert an int to a float in xmm; no rounding step needed. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11185 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11186 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11187 match(Set dst (ConvI2F src)); |
| 11188 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11189 ins_encode %{ |
| 11190 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11191 %} | |
| 0 | 11192 ins_pipe( pipe_slow ); |
| 11193 %} | |
| 11194 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11195 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11196 %{ |
| 11197 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11198 match(Set dst (ConvI2F src)); | |
| 11199 | |
| 11200 format %{ "MOVD $dst,$src\n\t" | |
| 11201 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11202 ins_encode %{ | |
| 304 | 11203 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11204 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11205 %} | |
| 11206 ins_pipe(pipe_slow); // XXX | |
| 11207 %} | |
| 11208 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11209 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11210 match(Set dst (ConvI2L src)); |
| 11211 effect(KILL cr); | |
| 624 | 11212 ins_cost(375); |
| 0 | 11213 format %{ "MOV $dst.lo,$src\n\t" |
| 11214 "MOV $dst.hi,$src\n\t" | |
| 11215 "SAR $dst.hi,31" %} | |
| 11216 ins_encode(convert_int_long(dst,src)); | |
| 11217 ins_pipe( ialu_reg_reg_long ); | |
| 11218 %} | |
| 11219 | |
| 11220 // Zero-extend convert int to long | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11221 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11222 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11223 effect( KILL flags ); | |
| 624 | 11224 ins_cost(250); |
| 0 | 11225 format %{ "MOV $dst.lo,$src\n\t" |
| 11226 "XOR $dst.hi,$dst.hi" %} | |
| 11227 opcode(0x33); // XOR | |
| 11228 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11229 ins_pipe( ialu_reg_reg_long ); | |
| 11230 %} | |
| 11231 | |
| 11232 // Zero-extend long | |
| 11233 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11234 match(Set dst (AndL src mask) ); | |
| 11235 effect( KILL flags ); | |
| 624 | 11236 ins_cost(250); |
| 0 | 11237 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11238 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11239 opcode(0x33); // XOR | |
| 11240 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11241 ins_pipe( ialu_reg_reg_long ); | |
| 11242 %} | |
| 11243 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11244 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11245 predicate (UseSSE<=1); |
| 11246 match(Set dst (ConvL2D src)); | |
| 11247 effect( KILL cr ); | |
| 11248 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11249 "PUSH $src.lo\n\t" | |
| 11250 "FILD ST,[ESP + #0]\n\t" | |
| 11251 "ADD ESP,8\n\t" | |
| 11252 "FSTP_D $dst\t# D-round" %} | |
| 11253 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11254 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11255 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11256 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11257 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11258 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11259 predicate (UseSSE>=2); |
| 11260 match(Set dst (ConvL2D src)); | |
| 11261 effect( KILL cr ); | |
| 11262 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11263 "PUSH $src.lo\n\t" | |
| 11264 "FILD_D [ESP]\n\t" | |
| 11265 "FSTP_D [ESP]\n\t" | |
| 11266 "MOVSD $dst,[ESP]\n\t" | |
| 11267 "ADD ESP,8" %} | |
| 11268 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11269 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11270 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11271 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11272 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11273 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11274 predicate (UseSSE>=1); |
| 11275 match(Set dst (ConvL2F src)); | |
| 11276 effect( KILL cr ); | |
| 11277 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11278 "PUSH $src.lo\n\t" | |
| 11279 "FILD_D [ESP]\n\t" | |
| 11280 "FSTP_S [ESP]\n\t" | |
| 11281 "MOVSS $dst,[ESP]\n\t" | |
| 11282 "ADD ESP,8" %} | |
| 11283 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11284 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11285 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11286 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11287 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11288 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11289 match(Set dst (ConvL2F src)); |
| 11290 effect( KILL cr ); | |
| 11291 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11292 "PUSH $src.lo\n\t" | |
| 11293 "FILD ST,[ESP + #0]\n\t" | |
| 11294 "ADD ESP,8\n\t" | |
| 11295 "FSTP_S $dst\t# F-round" %} | |
| 11296 opcode(0xDF, 0x5); /* DF /5 */ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11297 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11298 ins_pipe( pipe_slow ); |
| 11299 %} | |
| 11300 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11301 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11302 match(Set dst (ConvL2I src)); |
| 11303 effect( DEF dst, USE src ); | |
| 11304 format %{ "MOV $dst,$src.lo" %} | |
| 11305 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11306 ins_pipe( ialu_reg_reg ); | |
| 11307 %} | |
| 11308 | |
| 11309 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11310 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11311 match(Set dst (MoveF2I src)); |
| 11312 effect( DEF dst, USE src ); | |
| 11313 ins_cost(100); | |
| 11314 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11315 ins_encode %{ |
| 11316 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11317 %} | |
| 0 | 11318 ins_pipe( ialu_reg_mem ); |
| 11319 %} | |
| 11320 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11321 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11322 predicate(UseSSE==0); |
| 11323 match(Set dst (MoveF2I src)); | |
| 11324 effect( DEF dst, USE src ); | |
| 11325 | |
| 11326 ins_cost(125); | |
| 11327 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11328 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11329 ins_pipe( fpu_mem_reg ); |
| 11330 %} | |
| 11331 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11332 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11333 predicate(UseSSE>=1); |
| 11334 match(Set dst (MoveF2I src)); | |
| 11335 effect( DEF dst, USE src ); | |
| 11336 | |
| 11337 ins_cost(95); | |
| 11338 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11339 ins_encode %{ |
| 11340 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11341 %} | |
| 0 | 11342 ins_pipe( pipe_slow ); |
| 11343 %} | |
| 11344 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11345 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11346 predicate(UseSSE>=2); |
| 11347 match(Set dst (MoveF2I src)); | |
| 11348 effect( DEF dst, USE src ); | |
| 11349 ins_cost(85); | |
| 11350 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11351 ins_encode %{ |
| 11352 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11353 %} | |
| 0 | 11354 ins_pipe( pipe_slow ); |
| 11355 %} | |
| 11356 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11357 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11358 match(Set dst (MoveI2F src)); |
| 11359 effect( DEF dst, USE src ); | |
| 11360 | |
| 11361 ins_cost(100); | |
| 11362 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11363 ins_encode %{ |
| 11364 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11365 %} | |
| 0 | 11366 ins_pipe( ialu_mem_reg ); |
| 11367 %} | |
| 11368 | |
| 11369 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11370 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11371 predicate(UseSSE==0); |
| 11372 match(Set dst (MoveI2F src)); | |
| 11373 effect(DEF dst, USE src); | |
| 11374 | |
| 11375 ins_cost(125); | |
| 11376 format %{ "FLD_S $src\n\t" | |
| 11377 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11378 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11379 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11380 Pop_Reg_FPR(dst) ); |
| 0 | 11381 ins_pipe( fpu_reg_mem ); |
| 11382 %} | |
| 11383 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11384 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11385 predicate(UseSSE>=1); |
| 11386 match(Set dst (MoveI2F src)); | |
| 11387 effect( DEF dst, USE src ); | |
| 11388 | |
| 11389 ins_cost(95); | |
| 11390 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11391 ins_encode %{ |
| 11392 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11393 %} | |
| 0 | 11394 ins_pipe( pipe_slow ); |
| 11395 %} | |
| 11396 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11397 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11398 predicate(UseSSE>=2); |
| 11399 match(Set dst (MoveI2F src)); | |
| 11400 effect( DEF dst, USE src ); | |
| 11401 | |
| 11402 ins_cost(85); | |
| 11403 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11404 ins_encode %{ |
| 11405 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11406 %} | |
| 0 | 11407 ins_pipe( pipe_slow ); |
| 11408 %} | |
| 11409 | |
| 11410 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11411 match(Set dst (MoveD2L src)); | |
| 11412 effect(DEF dst, USE src); | |
| 11413 | |
| 11414 ins_cost(250); | |
| 11415 format %{ "MOV $dst.lo,$src\n\t" | |
| 11416 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11417 opcode(0x8B, 0x8B); | |
| 11418 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11419 ins_pipe( ialu_mem_long_reg ); | |
| 11420 %} | |
| 11421 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11422 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11423 predicate(UseSSE<=1); |
| 11424 match(Set dst (MoveD2L src)); | |
| 11425 effect(DEF dst, USE src); | |
| 11426 | |
| 11427 ins_cost(125); | |
| 11428 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11429 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11430 ins_pipe( fpu_mem_reg ); |
| 11431 %} | |
| 11432 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11433 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11434 predicate(UseSSE>=2); |
| 11435 match(Set dst (MoveD2L src)); | |
| 11436 effect(DEF dst, USE src); | |
| 11437 ins_cost(95); | |
| 11438 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11439 ins_encode %{ |
| 11440 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11441 %} | |
| 0 | 11442 ins_pipe( pipe_slow ); |
| 11443 %} | |
| 11444 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11445 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11446 predicate(UseSSE>=2); |
| 11447 match(Set dst (MoveD2L src)); | |
| 11448 effect(DEF dst, USE src, TEMP tmp); | |
| 11449 ins_cost(85); | |
| 11450 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11451 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11452 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11453 ins_encode %{ |
| 11454 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11455 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11456 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11457 %} | |
| 0 | 11458 ins_pipe( pipe_slow ); |
| 11459 %} | |
| 11460 | |
| 11461 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11462 match(Set dst (MoveL2D src)); | |
| 11463 effect(DEF dst, USE src); | |
| 11464 | |
| 11465 ins_cost(200); | |
| 11466 format %{ "MOV $dst,$src.lo\n\t" | |
| 11467 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11468 opcode(0x89, 0x89); | |
| 11469 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11470 ins_pipe( ialu_mem_long_reg ); | |
| 11471 %} | |
| 11472 | |
| 11473 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11474 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11475 predicate(UseSSE<=1); |
| 11476 match(Set dst (MoveL2D src)); | |
| 11477 effect(DEF dst, USE src); | |
| 11478 ins_cost(125); | |
| 11479 | |
| 11480 format %{ "FLD_D $src\n\t" | |
| 11481 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11482 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11483 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11484 Pop_Reg_DPR(dst) ); |
| 0 | 11485 ins_pipe( fpu_reg_mem ); |
| 11486 %} | |
| 11487 | |
| 11488 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11489 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11490 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11491 match(Set dst (MoveL2D src)); | |
| 11492 effect(DEF dst, USE src); | |
| 11493 | |
| 11494 ins_cost(95); | |
| 11495 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11496 ins_encode %{ |
| 11497 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11498 %} | |
| 0 | 11499 ins_pipe( pipe_slow ); |
| 11500 %} | |
| 11501 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11502 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11503 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11504 match(Set dst (MoveL2D src)); | |
| 11505 effect(DEF dst, USE src); | |
| 11506 | |
| 11507 ins_cost(95); | |
| 11508 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11509 ins_encode %{ |
| 11510 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11511 %} | |
| 0 | 11512 ins_pipe( pipe_slow ); |
| 11513 %} | |
| 11514 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11515 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11516 predicate(UseSSE>=2); |
| 11517 match(Set dst (MoveL2D src)); | |
| 11518 effect(TEMP dst, USE src, TEMP tmp); | |
| 11519 ins_cost(85); | |
| 11520 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11521 "MOVD $tmp,$src.hi\n\t" | |
| 11522 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11523 ins_encode %{ |
| 11524 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11525 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11526 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11527 %} | |
| 0 | 11528 ins_pipe( pipe_slow ); |
| 11529 %} | |
| 11530 | |
| 11531 | |
| 11532 // ======================================================================= | |
| 11533 // fast clearing of an array | |
| 11534 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11535 predicate(!UseFastStosb); |
| 0 | 11536 match(Set dummy (ClearArray cnt base)); |
| 11537 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11538 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11539 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11540 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11541 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11542 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11543 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11544 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11545 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11546 |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11547 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11548 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11549 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11550 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11551 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11552 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11553 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11554 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11555 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11556 %} |
| 0 | 11557 ins_pipe( pipe_slow ); |
| 11558 %} | |
| 11559 | |
| 2262 | 11560 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11561 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11562 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11563 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11564 | |
| 11565 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11566 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11567 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11568 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11569 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11570 %} |
| 681 | 11571 ins_pipe( pipe_slow ); |
| 11572 %} | |
| 11573 | |
| 11574 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11575 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11576 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11577 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11578 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11579 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11580 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11581 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11582 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11583 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11584 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11585 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11586 ins_pipe( pipe_slow ); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11587 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11588 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11589 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11590 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11591 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11592 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11593 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11594 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11595 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11596 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11597 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11598 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11599 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11600 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11601 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11602 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11603 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11604 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11605 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11606 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11607 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11608 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11609 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11610 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11611 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11612 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11613 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11614 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11615 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11616 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11617 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11618 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11619 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11620 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11621 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11622 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11623 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11624 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11625 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11626 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11627 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11628 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11629 %} |
| 0 | 11630 ins_pipe( pipe_slow ); |
| 11631 %} | |
| 11632 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11633 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11634 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11635 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11636 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11637 match(Set result (AryEq ary1 ary2)); |
| 681 | 11638 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11639 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11640 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11641 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11642 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11643 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11644 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11645 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11646 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11647 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11648 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11649 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11650 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11651 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11652 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11653 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11654 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11655 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11656 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11657 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11658 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11659 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11660 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11661 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11662 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11663 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11664 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11665 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11666 |
| 0 | 11667 //----------Control Flow Instructions------------------------------------------ |
| 11668 // Signed compare Instructions | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11669 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11670 match(Set cr (CmpI op1 op2)); |
| 11671 effect( DEF cr, USE op1, USE op2 ); | |
| 11672 format %{ "CMP $op1,$op2" %} | |
| 11673 opcode(0x3B); /* Opcode 3B /r */ | |
| 11674 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11675 ins_pipe( ialu_cr_reg_reg ); | |
| 11676 %} | |
| 11677 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11678 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11679 match(Set cr (CmpI op1 op2)); |
| 11680 effect( DEF cr, USE op1 ); | |
| 11681 format %{ "CMP $op1,$op2" %} | |
| 11682 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11683 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11684 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11685 ins_pipe( ialu_cr_reg_imm ); | |
| 11686 %} | |
| 11687 | |
| 11688 // Cisc-spilled version of cmpI_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11689 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11690 match(Set cr (CmpI op1 (LoadI op2))); |
| 11691 | |
| 11692 format %{ "CMP $op1,$op2" %} | |
| 11693 ins_cost(500); | |
| 11694 opcode(0x3B); /* Opcode 3B /r */ | |
| 11695 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11696 ins_pipe( ialu_cr_reg_mem ); | |
| 11697 %} | |
| 11698 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11699 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11700 match(Set cr (CmpI src zero)); |
| 11701 effect( DEF cr, USE src ); | |
| 11702 | |
| 11703 format %{ "TEST $src,$src" %} | |
| 11704 opcode(0x85); | |
| 11705 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11706 ins_pipe( ialu_cr_reg_imm ); | |
| 11707 %} | |
| 11708 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11709 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11710 match(Set cr (CmpI (AndI src con) zero)); |
| 11711 | |
| 11712 format %{ "TEST $src,$con" %} | |
| 11713 opcode(0xF7,0x00); | |
| 11714 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11715 ins_pipe( ialu_cr_reg_imm ); | |
| 11716 %} | |
| 11717 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11718 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11719 match(Set cr (CmpI (AndI src mem) zero)); |
| 11720 | |
| 11721 format %{ "TEST $src,$mem" %} | |
| 11722 opcode(0x85); | |
| 11723 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11724 ins_pipe( ialu_cr_reg_mem ); | |
| 11725 %} | |
| 11726 | |
| 11727 // Unsigned compare Instructions; really, same as signed except they | |
| 11728 // produce an eFlagsRegU instead of eFlagsReg. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11729 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11730 match(Set cr (CmpU op1 op2)); |
| 11731 | |
| 11732 format %{ "CMPu $op1,$op2" %} | |
| 11733 opcode(0x3B); /* Opcode 3B /r */ | |
| 11734 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11735 ins_pipe( ialu_cr_reg_reg ); | |
| 11736 %} | |
| 11737 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11738 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11739 match(Set cr (CmpU op1 op2)); |
| 11740 | |
| 11741 format %{ "CMPu $op1,$op2" %} | |
| 11742 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11743 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11744 ins_pipe( ialu_cr_reg_imm ); | |
| 11745 %} | |
| 11746 | |
| 11747 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11748 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11749 match(Set cr (CmpU op1 (LoadI op2))); |
| 11750 | |
| 11751 format %{ "CMPu $op1,$op2" %} | |
| 11752 ins_cost(500); | |
| 11753 opcode(0x3B); /* Opcode 3B /r */ | |
| 11754 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11755 ins_pipe( ialu_cr_reg_mem ); | |
| 11756 %} | |
| 11757 | |
| 11758 // // Cisc-spilled version of cmpU_eReg | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11759 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11760 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11761 // | |
| 11762 // format %{ "CMPu $op1,$op2" %} | |
| 11763 // ins_cost(500); | |
| 11764 // opcode(0x39); /* Opcode 39 /r */ | |
| 11765 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11766 //%} | |
| 11767 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11768 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11769 match(Set cr (CmpU src zero)); |
| 11770 | |
| 11771 format %{ "TESTu $src,$src" %} | |
| 11772 opcode(0x85); | |
| 11773 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11774 ins_pipe( ialu_cr_reg_imm ); | |
| 11775 %} | |
| 11776 | |
| 11777 // Unsigned pointer compare Instructions | |
| 11778 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11779 match(Set cr (CmpP op1 op2)); | |
| 11780 | |
| 11781 format %{ "CMPu $op1,$op2" %} | |
| 11782 opcode(0x3B); /* Opcode 3B /r */ | |
| 11783 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11784 ins_pipe( ialu_cr_reg_reg ); | |
| 11785 %} | |
| 11786 | |
| 11787 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11788 match(Set cr (CmpP op1 op2)); | |
| 11789 | |
| 11790 format %{ "CMPu $op1,$op2" %} | |
| 11791 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11792 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11793 ins_pipe( ialu_cr_reg_imm ); | |
| 11794 %} | |
| 11795 | |
| 11796 // // Cisc-spilled version of cmpP_eReg | |
| 11797 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11798 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11799 | |
| 11800 format %{ "CMPu $op1,$op2" %} | |
| 11801 ins_cost(500); | |
| 11802 opcode(0x3B); /* Opcode 3B /r */ | |
| 11803 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11804 ins_pipe( ialu_cr_reg_mem ); | |
| 11805 %} | |
| 11806 | |
| 11807 // // Cisc-spilled version of cmpP_eReg | |
| 11808 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11809 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11810 // | |
| 11811 // format %{ "CMPu $op1,$op2" %} | |
| 11812 // ins_cost(500); | |
| 11813 // opcode(0x39); /* Opcode 39 /r */ | |
| 11814 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11815 //%} | |
| 11816 | |
| 11817 // Compare raw pointer (used in out-of-heap check). | |
| 11818 // Only works because non-oop pointers must be raw pointers | |
| 11819 // and raw pointers have no anti-dependencies. | |
| 11820 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11821 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11822 match(Set cr (CmpP op1 (LoadP op2))); |
| 11823 | |
| 11824 format %{ "CMPu $op1,$op2" %} | |
| 11825 opcode(0x3B); /* Opcode 3B /r */ | |
| 11826 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11827 ins_pipe( ialu_cr_reg_mem ); | |
| 11828 %} | |
| 11829 | |
| 11830 // | |
| 11831 // This will generate a signed flags result. This should be ok | |
| 11832 // since any compare to a zero should be eq/neq. | |
| 11833 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11834 match(Set cr (CmpP src zero)); | |
| 11835 | |
| 11836 format %{ "TEST $src,$src" %} | |
| 11837 opcode(0x85); | |
| 11838 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11839 ins_pipe( ialu_cr_reg_imm ); | |
| 11840 %} | |
| 11841 | |
| 11842 // Cisc-spilled version of testP_reg | |
| 11843 // This will generate a signed flags result. This should be ok | |
| 11844 // since any compare to a zero should be eq/neq. | |
| 11845 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11846 match(Set cr (CmpP (LoadP op) zero)); | |
| 11847 | |
| 11848 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11849 ins_cost(500); | |
| 11850 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11851 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11852 ins_pipe( ialu_cr_reg_imm ); | |
| 11853 %} | |
| 11854 | |
| 11855 // Yanked all unsigned pointer compare operations. | |
| 11856 // Pointer compares are done with CmpP which is already unsigned. | |
| 11857 | |
| 11858 //----------Max and Min-------------------------------------------------------- | |
| 11859 // Min Instructions | |
| 11860 //// | |
| 11861 // *** Min and Max using the conditional move are slower than the | |
| 11862 // *** branch version on a Pentium III. | |
| 11863 // // Conditional move for min | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11864 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11865 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11866 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11867 // opcode(0x4C,0x0F); | |
| 11868 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11869 // ins_pipe( pipe_cmov_reg ); | |
| 11870 //%} | |
| 11871 // | |
| 11872 //// Min Register with Register (P6 version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11873 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11874 // predicate(VM_Version::supports_cmov() ); |
| 11875 // match(Set op2 (MinI op1 op2)); | |
| 11876 // ins_cost(200); | |
| 11877 // expand %{ | |
| 11878 // eFlagsReg cr; | |
| 11879 // compI_eReg(cr,op1,op2); | |
| 11880 // cmovI_reg_lt(op2,op1,cr); | |
| 11881 // %} | |
| 11882 //%} | |
| 11883 | |
| 11884 // Min Register with Register (generic version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11885 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11886 match(Set dst (MinI dst src)); |
| 11887 effect(KILL flags); | |
| 11888 ins_cost(300); | |
| 11889 | |
| 11890 format %{ "MIN $dst,$src" %} | |
| 11891 opcode(0xCC); | |
| 11892 ins_encode( min_enc(dst,src) ); | |
| 11893 ins_pipe( pipe_slow ); | |
| 11894 %} | |
| 11895 | |
| 11896 // Max Register with Register | |
| 11897 // *** Min and Max using the conditional move are slower than the | |
| 11898 // *** branch version on a Pentium III. | |
| 11899 // // Conditional move for max | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11900 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11901 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11902 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11903 // opcode(0x4F,0x0F); | |
| 11904 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11905 // ins_pipe( pipe_cmov_reg ); | |
| 11906 //%} | |
| 11907 // | |
| 11908 // // Max Register with Register (P6 version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11909 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11910 // predicate(VM_Version::supports_cmov() ); |
| 11911 // match(Set op2 (MaxI op1 op2)); | |
| 11912 // ins_cost(200); | |
| 11913 // expand %{ | |
| 11914 // eFlagsReg cr; | |
| 11915 // compI_eReg(cr,op1,op2); | |
| 11916 // cmovI_reg_gt(op2,op1,cr); | |
| 11917 // %} | |
| 11918 //%} | |
| 11919 | |
| 11920 // Max Register with Register (generic version) | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11921 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11922 match(Set dst (MaxI dst src)); |
| 11923 effect(KILL flags); | |
| 11924 ins_cost(300); | |
| 11925 | |
| 11926 format %{ "MAX $dst,$src" %} | |
| 11927 opcode(0xCC); | |
| 11928 ins_encode( max_enc(dst,src) ); | |
| 11929 ins_pipe( pipe_slow ); | |
| 11930 %} | |
| 11931 | |
| 11932 // ============================================================================ | |
| 3345 | 11933 // Counted Loop limit node which represents exact final iterator value. |
| 11934 // Note: the resulting value should fit into integer range since | |
| 11935 // counted loops have limit check on overflow. | |
| 11936 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11937 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11938 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11939 ins_cost(300); | |
| 11940 | |
| 11941 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11942 ins_encode %{ | |
| 11943 int strd = (int)$stride$$constant; | |
| 11944 assert(strd != 1 && strd != -1, "sanity"); | |
| 11945 int m1 = (strd > 0) ? 1 : -1; | |
| 11946 // Convert limit to long (EAX:EDX) | |
| 11947 __ cdql(); | |
| 11948 // Convert init to long (init:tmp) | |
| 11949 __ movl($tmp$$Register, $init$$Register); | |
| 11950 __ sarl($tmp$$Register, 31); | |
| 11951 // $limit - $init | |
| 11952 __ subl($limit$$Register, $init$$Register); | |
| 11953 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11954 // + ($stride - 1) | |
| 11955 if (strd > 0) { | |
| 11956 __ addl($limit$$Register, (strd - 1)); | |
| 11957 __ adcl($limit_hi$$Register, 0); | |
| 11958 __ movl($tmp$$Register, strd); | |
| 11959 } else { | |
| 11960 __ addl($limit$$Register, (strd + 1)); | |
| 11961 __ adcl($limit_hi$$Register, -1); | |
| 11962 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11963 __ movl($tmp$$Register, -strd); | |
| 11964 } | |
| 11965 // signed devision: (EAX:EDX) / pos_stride | |
| 11966 __ idivl($tmp$$Register); | |
| 11967 if (strd < 0) { | |
| 11968 // restore sign | |
| 11969 __ negl($tmp$$Register); | |
| 11970 } | |
| 11971 // (EAX) * stride | |
| 11972 __ mull($tmp$$Register); | |
| 11973 // + init (ignore upper bits) | |
| 11974 __ addl($limit$$Register, $init$$Register); | |
| 11975 %} | |
| 11976 ins_pipe( pipe_slow ); | |
| 11977 %} | |
| 11978 | |
| 11979 // ============================================================================ | |
| 0 | 11980 // Branch Instructions |
| 11981 // Jump Table | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
11982 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11983 match(Jump switch_val); |
| 11984 ins_cost(350); | |
| 2008 | 11985 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11986 ins_encode %{ | |
| 0 | 11987 // Jump to Address(table_base + switch_reg) |
| 11988 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11989 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11990 %} |
| 11991 ins_pipe(pipe_jmp); | |
| 11992 %} | |
| 11993 | |
| 11994 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11995 instruct jmpDir(label labl) %{ | |
| 11996 match(Goto); | |
| 11997 effect(USE labl); | |
| 11998 | |
| 11999 ins_cost(300); | |
| 12000 format %{ "JMP $labl" %} | |
| 12001 size(5); | |
| 3851 | 12002 ins_encode %{ |
| 12003 Label* L = $labl$$label; | |
| 12004 __ jmp(*L, false); // Always long jump | |
| 12005 %} | |
| 0 | 12006 ins_pipe( pipe_jmp ); |
| 12007 %} | |
| 12008 | |
| 12009 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12010 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12011 match(If cop cr); | |
| 12012 effect(USE labl); | |
| 12013 | |
| 12014 ins_cost(300); | |
| 12015 format %{ "J$cop $labl" %} | |
| 12016 size(6); | |
| 3851 | 12017 ins_encode %{ |
| 12018 Label* L = $labl$$label; | |
| 12019 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12020 %} | |
| 0 | 12021 ins_pipe( pipe_jcc ); |
| 12022 %} | |
| 12023 | |
| 12024 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12025 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12026 match(CountedLoopEnd cop cr); | |
| 12027 effect(USE labl); | |
| 12028 | |
| 12029 ins_cost(300); | |
| 12030 format %{ "J$cop $labl\t# Loop end" %} | |
| 12031 size(6); | |
| 3851 | 12032 ins_encode %{ |
| 12033 Label* L = $labl$$label; | |
| 12034 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12035 %} | |
| 0 | 12036 ins_pipe( pipe_jcc ); |
| 12037 %} | |
| 12038 | |
| 12039 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12040 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12041 match(CountedLoopEnd cop cmp); | |
| 12042 effect(USE labl); | |
| 12043 | |
| 12044 ins_cost(300); | |
| 12045 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12046 size(6); | |
| 3851 | 12047 ins_encode %{ |
| 12048 Label* L = $labl$$label; | |
| 12049 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12050 %} | |
| 0 | 12051 ins_pipe( pipe_jcc ); |
| 12052 %} | |
| 12053 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12054 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12055 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12056 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12057 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12058 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12059 format %{ "J$cop,u $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12060 size(6); |
| 3851 | 12061 ins_encode %{ |
| 12062 Label* L = $labl$$label; | |
| 12063 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12064 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12065 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12066 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12067 |
| 0 | 12068 // Jump Direct Conditional - using unsigned comparison |
| 12069 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12070 match(If cop cmp); | |
| 12071 effect(USE labl); | |
| 12072 | |
| 12073 ins_cost(300); | |
| 12074 format %{ "J$cop,u $labl" %} | |
| 12075 size(6); | |
| 3851 | 12076 ins_encode %{ |
| 12077 Label* L = $labl$$label; | |
| 12078 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12079 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12080 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12081 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12082 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12083 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12084 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12085 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12086 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12087 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12088 format %{ "J$cop,u $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12089 size(6); |
| 3851 | 12090 ins_encode %{ |
| 12091 Label* L = $labl$$label; | |
| 12092 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12093 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12094 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12095 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12096 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12097 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12098 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12099 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12100 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12101 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12102 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12103 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12104 $$emit$$"JP,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12105 $$emit$$"J$cop,u $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12106 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12107 $$emit$$"JP,u done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12108 $$emit$$"J$cop,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12109 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12110 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12111 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12112 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12113 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12114 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12115 __ jcc(Assembler::parity, *l, false); |
| 12116 __ jcc(Assembler::notEqual, *l, false); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12117 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12118 Label done; |
| 12119 __ jccb(Assembler::parity, done); | |
| 12120 __ jcc(Assembler::equal, *l, false); | |
| 12121 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12122 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12123 ShouldNotReachHere(); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12124 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12125 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12126 ins_pipe(pipe_jcc); |
| 0 | 12127 %} |
| 12128 | |
| 12129 // ============================================================================ | |
| 12130 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12131 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12132 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12133 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12134 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12135 match(Set result (PartialSubtypeCheck sub super)); | |
| 12136 effect( KILL rcx, KILL cr ); | |
| 12137 | |
| 12138 ins_cost(1100); // slightly larger than the next version | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12139 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12140 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12141 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12142 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12143 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12144 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12145 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12146 "miss:\t" %} | |
| 12147 | |
| 12148 opcode(0x1); // Force a XOR of EDI | |
| 12149 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12150 ins_pipe( pipe_slow ); | |
| 12151 %} | |
| 12152 | |
| 12153 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12154 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12155 effect( KILL rcx, KILL result ); | |
| 12156 | |
| 12157 ins_cost(1000); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12158 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12159 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12160 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12161 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12162 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12163 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12164 "miss:\t" %} | |
| 12165 | |
| 12166 opcode(0x0); // No need to XOR EDI | |
| 12167 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12168 ins_pipe( pipe_slow ); | |
| 12169 %} | |
| 12170 | |
| 12171 // ============================================================================ | |
| 12172 // Branch Instructions -- short offset versions | |
| 12173 // | |
| 12174 // These instructions are used to replace jumps of a long offset (the default | |
| 12175 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12176 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12177 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12178 // method in the MachNode which can be used to do in-place replacement of the | |
| 12179 // long variant with the shorter variant. The compiler will determine if a | |
| 12180 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12181 // specific code section of the file. | |
| 12182 | |
| 12183 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12184 instruct jmpDir_short(label labl) %{ | |
| 12185 match(Goto); | |
| 12186 effect(USE labl); | |
| 12187 | |
| 12188 ins_cost(300); | |
| 12189 format %{ "JMP,s $labl" %} | |
| 12190 size(2); | |
| 3851 | 12191 ins_encode %{ |
| 12192 Label* L = $labl$$label; | |
| 12193 __ jmpb(*L); | |
| 12194 %} | |
| 0 | 12195 ins_pipe( pipe_jmp ); |
| 12196 ins_short_branch(1); | |
| 12197 %} | |
| 12198 | |
| 12199 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12200 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12201 match(If cop cr); | |
| 12202 effect(USE labl); | |
| 12203 | |
| 12204 ins_cost(300); | |
| 12205 format %{ "J$cop,s $labl" %} | |
| 12206 size(2); | |
| 3851 | 12207 ins_encode %{ |
| 12208 Label* L = $labl$$label; | |
| 12209 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12210 %} | |
| 0 | 12211 ins_pipe( pipe_jcc ); |
| 12212 ins_short_branch(1); | |
| 12213 %} | |
| 12214 | |
| 12215 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12216 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12217 match(CountedLoopEnd cop cr); | |
| 12218 effect(USE labl); | |
| 12219 | |
| 12220 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12221 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12222 size(2); |
| 3851 | 12223 ins_encode %{ |
| 12224 Label* L = $labl$$label; | |
| 12225 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12226 %} | |
| 0 | 12227 ins_pipe( pipe_jcc ); |
| 12228 ins_short_branch(1); | |
| 12229 %} | |
| 12230 | |
| 12231 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12232 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12233 match(CountedLoopEnd cop cmp); | |
| 12234 effect(USE labl); | |
| 12235 | |
| 12236 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12237 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12238 size(2); |
| 3851 | 12239 ins_encode %{ |
| 12240 Label* L = $labl$$label; | |
| 12241 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12242 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12243 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12244 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12245 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12246 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12247 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12248 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12249 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12250 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12251 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12252 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12253 size(2); |
| 3851 | 12254 ins_encode %{ |
| 12255 Label* L = $labl$$label; | |
| 12256 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12257 %} | |
| 0 | 12258 ins_pipe( pipe_jcc ); |
| 12259 ins_short_branch(1); | |
| 12260 %} | |
| 12261 | |
| 12262 // Jump Direct Conditional - using unsigned comparison | |
| 12263 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12264 match(If cop cmp); | |
| 12265 effect(USE labl); | |
| 12266 | |
| 12267 ins_cost(300); | |
| 12268 format %{ "J$cop,us $labl" %} | |
| 12269 size(2); | |
| 3851 | 12270 ins_encode %{ |
| 12271 Label* L = $labl$$label; | |
| 12272 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12273 %} | |
| 0 | 12274 ins_pipe( pipe_jcc ); |
| 12275 ins_short_branch(1); | |
| 12276 %} | |
| 12277 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12278 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12279 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12280 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12281 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12282 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12283 format %{ "J$cop,us $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12284 size(2); |
| 3851 | 12285 ins_encode %{ |
| 12286 Label* L = $labl$$label; | |
| 12287 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12288 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12289 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12290 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12291 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12292 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12293 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12294 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12295 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12296 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12297 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12298 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12299 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12300 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12301 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12302 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12303 $$emit$$"JP,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12304 $$emit$$"J$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12305 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12306 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12307 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12308 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12309 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12310 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12311 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12312 __ jccb(Assembler::parity, *l); |
| 12313 __ jccb(Assembler::notEqual, *l); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12314 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12315 Label done; |
| 12316 __ jccb(Assembler::parity, done); | |
| 12317 __ jccb(Assembler::equal, *l); | |
| 12318 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12319 } else { |
| 3851 | 12320 ShouldNotReachHere(); |
| 12321 } | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12322 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12323 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12324 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12325 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12326 |
| 0 | 12327 // ============================================================================ |
| 12328 // Long Compare | |
| 12329 // | |
| 12330 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12331 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12332 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12333 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12334 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12335 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12336 // NE test is negated from that. | |
| 12337 | |
| 12338 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12339 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12340 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12341 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12342 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12343 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12344 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12345 // both forms beat the trinary form of long-compare and both are very useful | |
| 12346 // on Intel which has so few registers. | |
| 12347 | |
| 12348 // Manifest a CmpL result in an integer register. Very painful. | |
| 12349 // This is the test to avoid. | |
| 12350 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12351 match(Set dst (CmpL3 src1 src2)); | |
| 12352 effect( KILL flags ); | |
| 12353 ins_cost(1000); | |
| 12354 format %{ "XOR $dst,$dst\n\t" | |
| 12355 "CMP $src1.hi,$src2.hi\n\t" | |
| 12356 "JLT,s m_one\n\t" | |
| 12357 "JGT,s p_one\n\t" | |
| 12358 "CMP $src1.lo,$src2.lo\n\t" | |
| 12359 "JB,s m_one\n\t" | |
| 12360 "JEQ,s done\n" | |
| 12361 "p_one:\tINC $dst\n\t" | |
| 12362 "JMP,s done\n" | |
| 12363 "m_one:\tDEC $dst\n" | |
| 12364 "done:" %} | |
| 12365 ins_encode %{ | |
| 12366 Label p_one, m_one, done; | |
| 304 | 12367 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12368 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12369 __ jccb(Assembler::less, m_one); | |
| 12370 __ jccb(Assembler::greater, p_one); | |
| 12371 __ cmpl($src1$$Register, $src2$$Register); | |
| 12372 __ jccb(Assembler::below, m_one); | |
| 12373 __ jccb(Assembler::equal, done); | |
| 12374 __ bind(p_one); | |
| 304 | 12375 __ incrementl($dst$$Register); |
| 0 | 12376 __ jmpb(done); |
| 12377 __ bind(m_one); | |
| 304 | 12378 __ decrementl($dst$$Register); |
| 0 | 12379 __ bind(done); |
| 12380 %} | |
| 12381 ins_pipe( pipe_slow ); | |
| 12382 %} | |
| 12383 | |
| 12384 //====== | |
| 12385 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12386 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12387 // NOT GOOD FOR EQ/NE tests. | |
| 12388 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12389 match( Set flags (CmpL src zero )); | |
| 12390 ins_cost(100); | |
| 12391 format %{ "TEST $src.hi,$src.hi" %} | |
| 12392 opcode(0x85); | |
| 12393 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12394 ins_pipe( ialu_cr_reg_reg ); | |
| 12395 %} | |
| 12396 | |
| 12397 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12398 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12399 // NOT GOOD FOR EQ/NE tests. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12400 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12401 match( Set flags (CmpL src1 src2 )); |
| 12402 effect( TEMP tmp ); | |
| 12403 ins_cost(300); | |
| 12404 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12405 "MOV $tmp,$src1.hi\n\t" | |
| 12406 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12407 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12408 ins_pipe( ialu_cr_reg_reg ); | |
| 12409 %} | |
| 12410 | |
| 12411 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12412 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12413 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12414 match(If cmp flags); | |
| 12415 effect(USE labl); | |
| 12416 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12417 expand %{ | |
| 12418 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12419 %} | |
| 12420 %} | |
| 12421 | |
| 24206 | 12422 //====== |
| 12423 // Manifest a CmpUL result in the normal flags. Only good for LT or GE | |
| 12424 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12425 // NOT GOOD FOR EQ/NE tests. | |
| 12426 instruct cmpUL_zero_flags_LTGE(flagsReg_ulong_LTGE flags, eRegL src, immL0 zero) %{ | |
| 12427 match(Set flags (CmpUL src zero)); | |
| 12428 ins_cost(100); | |
| 12429 format %{ "TEST $src.hi,$src.hi" %} | |
| 12430 opcode(0x85); | |
| 12431 ins_encode(OpcP, RegReg_Hi2(src, src)); | |
| 12432 ins_pipe(ialu_cr_reg_reg); | |
| 12433 %} | |
| 12434 | |
| 12435 // Manifest a CmpUL result in the normal flags. Only good for LT or GE | |
| 12436 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12437 // NOT GOOD FOR EQ/NE tests. | |
| 12438 instruct cmpUL_reg_flags_LTGE(flagsReg_ulong_LTGE flags, eRegL src1, eRegL src2, rRegI tmp) %{ | |
| 12439 match(Set flags (CmpUL src1 src2)); | |
| 12440 effect(TEMP tmp); | |
| 12441 ins_cost(300); | |
| 12442 format %{ "CMP $src1.lo,$src2.lo\t! Unsigned long compare; set flags for low bits\n\t" | |
| 12443 "MOV $tmp,$src1.hi\n\t" | |
| 12444 "SBB $tmp,$src2.hi\t! Compute flags for unsigned long compare" %} | |
| 12445 ins_encode(long_cmp_flags2(src1, src2, tmp)); | |
| 12446 ins_pipe(ialu_cr_reg_reg); | |
| 12447 %} | |
| 12448 | |
| 12449 // Unsigned long compares reg < zero/req OR reg >= zero/req. | |
| 12450 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12451 instruct cmpUL_LTGE(cmpOpU cmp, flagsReg_ulong_LTGE flags, label labl) %{ | |
| 12452 match(If cmp flags); | |
| 12453 effect(USE labl); | |
| 12454 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge); | |
| 12455 expand %{ | |
| 12456 jmpCon(cmp, flags, labl); // JLT or JGE... | |
| 12457 %} | |
| 12458 %} | |
| 12459 | |
| 0 | 12460 // Compare 2 longs and CMOVE longs. |
| 12461 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12462 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12463 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12464 ins_cost(400); | |
| 12465 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12466 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12467 opcode(0x0F,0x40); | |
| 12468 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12469 ins_pipe( pipe_cmov_reg_long ); | |
| 12470 %} | |
| 12471 | |
| 12472 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12473 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12474 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12475 ins_cost(500); | |
| 12476 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12477 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12478 opcode(0x0F,0x40); | |
| 12479 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12480 ins_pipe( pipe_cmov_reg_long ); | |
| 12481 %} | |
| 12482 | |
| 12483 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12484 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12485 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12486 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12487 ins_cost(200); | |
| 12488 format %{ "CMOV$cmp $dst,$src" %} | |
| 12489 opcode(0x0F,0x40); | |
| 12490 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12491 ins_pipe( pipe_cmov_reg ); | |
| 12492 %} | |
| 12493 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12494 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12495 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12496 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12497 ins_cost(250); | |
| 12498 format %{ "CMOV$cmp $dst,$src" %} | |
| 12499 opcode(0x0F,0x40); | |
| 12500 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12501 ins_pipe( pipe_cmov_mem ); | |
| 12502 %} | |
| 12503 | |
| 12504 // Compare 2 longs and CMOVE ints. | |
| 12505 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12506 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12507 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12508 ins_cost(200); | |
| 12509 format %{ "CMOV$cmp $dst,$src" %} | |
| 12510 opcode(0x0F,0x40); | |
| 12511 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12512 ins_pipe( pipe_cmov_reg ); | |
| 12513 %} | |
| 12514 | |
| 12515 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12516 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12517 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12518 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12519 ins_cost(200); | |
| 12520 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12521 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12522 %} |
| 12523 %} | |
| 12524 | |
| 12525 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12526 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12527 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12528 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12529 ins_cost(200); | |
| 12530 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12531 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12532 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12533 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12534 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12535 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12536 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12537 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12538 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12539 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12540 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12541 %} |
| 12542 %} | |
| 12543 | |
| 12544 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12545 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12546 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12547 ins_cost(200); | |
| 12548 expand %{ | |
| 12549 fcmovF_regS(cmp,flags,dst,src); | |
| 12550 %} | |
| 12551 %} | |
| 12552 | |
| 12553 //====== | |
| 12554 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12555 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12556 match( Set flags (CmpL src zero )); |
| 12557 effect(TEMP tmp); | |
| 12558 ins_cost(200); | |
| 12559 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12560 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12561 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12562 ins_pipe( ialu_reg_reg_long ); | |
| 12563 %} | |
| 12564 | |
| 12565 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12566 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12567 match( Set flags (CmpL src1 src2 )); | |
| 12568 ins_cost(200+300); | |
| 12569 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12570 "JNE,s skip\n\t" | |
| 12571 "CMP $src1.hi,$src2.hi\n\t" | |
| 12572 "skip:\t" %} | |
| 12573 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12574 ins_pipe( ialu_cr_reg_reg ); | |
| 12575 %} | |
| 12576 | |
| 12577 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12578 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12579 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12580 match(If cmp flags); | |
| 12581 effect(USE labl); | |
| 12582 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12583 expand %{ | |
| 12584 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12585 %} | |
| 12586 %} | |
| 12587 | |
| 24206 | 12588 //====== |
| 12589 // Manifest a CmpUL result in the normal flags. Only good for EQ/NE compares. | |
| 12590 instruct cmpUL_zero_flags_EQNE(flagsReg_ulong_EQNE flags, eRegL src, immL0 zero, rRegI tmp) %{ | |
| 12591 match(Set flags (CmpUL src zero)); | |
| 12592 effect(TEMP tmp); | |
| 12593 ins_cost(200); | |
| 12594 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12595 "OR $tmp,$src.hi\t! Unsigned long is EQ/NE 0?" %} | |
| 12596 ins_encode(long_cmp_flags0(src, tmp)); | |
| 12597 ins_pipe(ialu_reg_reg_long); | |
| 12598 %} | |
| 12599 | |
| 12600 // Manifest a CmpUL result in the normal flags. Only good for EQ/NE compares. | |
| 12601 instruct cmpUL_reg_flags_EQNE(flagsReg_ulong_EQNE flags, eRegL src1, eRegL src2) %{ | |
| 12602 match(Set flags (CmpUL src1 src2)); | |
| 12603 ins_cost(200+300); | |
| 12604 format %{ "CMP $src1.lo,$src2.lo\t! Unsigned long compare; set flags for low bits\n\t" | |
| 12605 "JNE,s skip\n\t" | |
| 12606 "CMP $src1.hi,$src2.hi\n\t" | |
| 12607 "skip:\t" %} | |
| 12608 ins_encode(long_cmp_flags1(src1, src2)); | |
| 12609 ins_pipe(ialu_cr_reg_reg); | |
| 12610 %} | |
| 12611 | |
| 12612 // Unsigned long compare reg == zero/reg OR reg != zero/reg | |
| 12613 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12614 instruct cmpUL_EQNE(cmpOpU cmp, flagsReg_ulong_EQNE flags, label labl) %{ | |
| 12615 match(If cmp flags); | |
| 12616 effect(USE labl); | |
| 12617 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne); | |
| 12618 expand %{ | |
| 12619 jmpCon(cmp, flags, labl); // JEQ or JNE... | |
| 12620 %} | |
| 12621 %} | |
| 12622 | |
| 0 | 12623 // Compare 2 longs and CMOVE longs. |
| 12624 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12625 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12626 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12627 ins_cost(400); | |
| 12628 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12629 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12630 opcode(0x0F,0x40); | |
| 12631 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12632 ins_pipe( pipe_cmov_reg_long ); | |
| 12633 %} | |
| 12634 | |
| 12635 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12636 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12637 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12638 ins_cost(500); | |
| 12639 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12640 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12641 opcode(0x0F,0x40); | |
| 12642 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12643 ins_pipe( pipe_cmov_reg_long ); | |
| 12644 %} | |
| 12645 | |
| 12646 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12647 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12648 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12649 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12650 ins_cost(200); | |
| 12651 format %{ "CMOV$cmp $dst,$src" %} | |
| 12652 opcode(0x0F,0x40); | |
| 12653 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12654 ins_pipe( pipe_cmov_reg ); | |
| 12655 %} | |
| 12656 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12657 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12658 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12659 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12660 ins_cost(250); | |
| 12661 format %{ "CMOV$cmp $dst,$src" %} | |
| 12662 opcode(0x0F,0x40); | |
| 12663 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12664 ins_pipe( pipe_cmov_mem ); | |
| 12665 %} | |
| 12666 | |
| 12667 // Compare 2 longs and CMOVE ints. | |
| 12668 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12669 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12670 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12671 ins_cost(200); | |
| 12672 format %{ "CMOV$cmp $dst,$src" %} | |
| 12673 opcode(0x0F,0x40); | |
| 12674 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12675 ins_pipe( pipe_cmov_reg ); | |
| 12676 %} | |
| 12677 | |
| 12678 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12679 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12680 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12681 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12682 ins_cost(200); | |
| 12683 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12684 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12685 %} |
| 12686 %} | |
| 12687 | |
| 12688 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12689 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12690 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12691 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12692 ins_cost(200); | |
| 12693 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12694 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12695 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12696 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12697 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12698 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12699 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12700 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12701 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12702 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12703 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12704 %} |
| 12705 %} | |
| 12706 | |
| 12707 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12708 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12709 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12710 ins_cost(200); | |
| 12711 expand %{ | |
| 12712 fcmovF_regS(cmp,flags,dst,src); | |
| 12713 %} | |
| 12714 %} | |
| 12715 | |
| 12716 //====== | |
| 12717 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12718 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12719 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12720 match( Set flags (CmpL src zero )); |
| 12721 effect( TEMP tmp ); | |
| 12722 ins_cost(300); | |
| 12723 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12724 "CMP $tmp,$src.lo\n\t" | |
| 12725 "SBB $tmp,$src.hi\n\t" %} | |
| 12726 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12727 ins_pipe( ialu_reg_reg_long ); | |
| 12728 %} | |
| 12729 | |
| 12730 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12731 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12732 // requires a commuted test to get the same result. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12733 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12734 match( Set flags (CmpL src1 src2 )); |
| 12735 effect( TEMP tmp ); | |
| 12736 ins_cost(300); | |
| 12737 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12738 "MOV $tmp,$src2.hi\n\t" | |
| 12739 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12740 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12741 ins_pipe( ialu_cr_reg_reg ); | |
| 12742 %} | |
| 12743 | |
| 12744 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12745 // Just a wrapper for a normal branch, plus the predicate test | |
| 12746 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12747 match(If cmp flags); | |
| 12748 effect(USE labl); | |
| 12749 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12750 ins_cost(300); | |
| 12751 expand %{ | |
| 12752 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12753 %} | |
| 12754 %} | |
| 12755 | |
| 24206 | 12756 //====== |
| 12757 // Manifest a CmpUL result in the normal flags. Only good for LE or GT compares. | |
| 12758 // Same as cmpUL_reg_flags_LEGT except must negate src | |
| 12759 instruct cmpUL_zero_flags_LEGT(flagsReg_ulong_LEGT flags, eRegL src, immL0 zero, rRegI tmp) %{ | |
| 12760 match(Set flags (CmpUL src zero)); | |
| 12761 effect(TEMP tmp); | |
| 12762 ins_cost(300); | |
| 12763 format %{ "XOR $tmp,$tmp\t# Unsigned long compare for -$src < 0, use commuted test\n\t" | |
| 12764 "CMP $tmp,$src.lo\n\t" | |
| 12765 "SBB $tmp,$src.hi\n\t" %} | |
| 12766 ins_encode(long_cmp_flags3(src, tmp)); | |
| 12767 ins_pipe(ialu_reg_reg_long); | |
| 12768 %} | |
| 12769 | |
| 12770 // Manifest a CmpUL result in the normal flags. Only good for LE or GT compares. | |
| 12771 // Same as cmpUL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12772 // requires a commuted test to get the same result. | |
| 12773 instruct cmpUL_reg_flags_LEGT(flagsReg_ulong_LEGT flags, eRegL src1, eRegL src2, rRegI tmp) %{ | |
| 12774 match(Set flags (CmpUL src1 src2)); | |
| 12775 effect(TEMP tmp); | |
| 12776 ins_cost(300); | |
| 12777 format %{ "CMP $src2.lo,$src1.lo\t! Unsigned long compare, swapped operands, use with commuted test\n\t" | |
| 12778 "MOV $tmp,$src2.hi\n\t" | |
| 12779 "SBB $tmp,$src1.hi\t! Compute flags for unsigned long compare" %} | |
| 12780 ins_encode(long_cmp_flags2( src2, src1, tmp)); | |
| 12781 ins_pipe(ialu_cr_reg_reg); | |
| 12782 %} | |
| 12783 | |
| 12784 // Unsigned long compares reg < zero/req OR reg >= zero/req. | |
| 12785 // Just a wrapper for a normal branch, plus the predicate test | |
| 12786 instruct cmpUL_LEGT(cmpOpU_commute cmp, flagsReg_ulong_LEGT flags, label labl) %{ | |
| 12787 match(If cmp flags); | |
| 12788 effect(USE labl); | |
| 12789 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le); | |
| 12790 ins_cost(300); | |
| 12791 expand %{ | |
| 12792 jmpCon(cmp, flags, labl); // JGT or JLE... | |
| 12793 %} | |
| 12794 %} | |
| 12795 | |
| 0 | 12796 // Compare 2 longs and CMOVE longs. |
| 12797 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12798 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12799 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12800 ins_cost(400); | |
| 12801 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12802 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12803 opcode(0x0F,0x40); | |
| 12804 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12805 ins_pipe( pipe_cmov_reg_long ); | |
| 12806 %} | |
| 12807 | |
| 12808 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12809 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12810 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12811 ins_cost(500); | |
| 12812 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12813 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12814 opcode(0x0F,0x40); | |
| 12815 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12816 ins_pipe( pipe_cmov_reg_long ); | |
| 12817 %} | |
| 12818 | |
| 12819 // Compare 2 longs and CMOVE ints. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12820 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12821 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12822 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12823 ins_cost(200); | |
| 12824 format %{ "CMOV$cmp $dst,$src" %} | |
| 12825 opcode(0x0F,0x40); | |
| 12826 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12827 ins_pipe( pipe_cmov_reg ); | |
| 12828 %} | |
| 12829 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
12830 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12831 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12832 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12833 ins_cost(250); | |
| 12834 format %{ "CMOV$cmp $dst,$src" %} | |
| 12835 opcode(0x0F,0x40); | |
| 12836 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12837 ins_pipe( pipe_cmov_mem ); | |
| 12838 %} | |
| 12839 | |
| 12840 // Compare 2 longs and CMOVE ptrs. | |
| 12841 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12842 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12843 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12844 ins_cost(200); | |
| 12845 format %{ "CMOV$cmp $dst,$src" %} | |
| 12846 opcode(0x0F,0x40); | |
| 12847 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12848 ins_pipe( pipe_cmov_reg ); | |
| 12849 %} | |
| 12850 | |
| 12851 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12852 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12853 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12854 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12855 ins_cost(200); | |
| 12856 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12857 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12858 %} |
| 12859 %} | |
| 12860 | |
| 12861 // Compare 2 longs and CMOVE doubles | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12862 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12863 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12864 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12865 ins_cost(200); | |
| 12866 expand %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12867 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12868 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12869 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12870 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12871 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12872 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12873 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12874 ins_cost(200); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12875 expand %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12876 fcmovFPR_regS(cmp,flags,dst,src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12877 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12878 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12879 |
| 0 | 12880 |
| 12881 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
12882 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12883 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12884 ins_cost(200); | |
| 12885 expand %{ | |
| 12886 fcmovF_regS(cmp,flags,dst,src); | |
| 12887 %} | |
| 12888 %} | |
| 12889 | |
| 12890 | |
| 12891 // ============================================================================ | |
| 12892 // Procedure Call/Return Instructions | |
| 12893 // Call Java Static Instruction | |
| 12894 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12895 // compute_padding() functions will have to be adjusted. | |
| 12896 instruct CallStaticJavaDirect(method meth) %{ | |
| 12897 match(CallStaticJava); | |
| 12898 effect(USE meth); | |
| 12899 | |
| 12900 ins_cost(300); | |
| 12901 format %{ "CALL,static " %} | |
| 12902 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12903 ins_encode( pre_call_resets, |
| 0 | 12904 Java_Static_Call( meth ), |
| 12905 call_epilog, | |
| 12906 post_call_FPU ); | |
| 12907 ins_pipe( pipe_slow ); | |
| 12908 ins_alignment(4); | |
| 12909 %} | |
| 12910 | |
| 12911 // Call Java Dynamic Instruction | |
| 12912 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12913 // compute_padding() functions will have to be adjusted. | |
| 12914 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12915 match(CallDynamicJava); | |
| 12916 effect(USE meth); | |
| 12917 | |
| 12918 ins_cost(300); | |
| 12919 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12920 "CALL,dynamic" %} | |
| 12921 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12922 ins_encode( pre_call_resets, |
| 0 | 12923 Java_Dynamic_Call( meth ), |
| 12924 call_epilog, | |
| 12925 post_call_FPU ); | |
| 12926 ins_pipe( pipe_slow ); | |
| 12927 ins_alignment(4); | |
| 12928 %} | |
| 12929 | |
| 12930 // Call Runtime Instruction | |
| 12931 instruct CallRuntimeDirect(method meth) %{ | |
| 12932 match(CallRuntime ); | |
| 12933 effect(USE meth); | |
| 12934 | |
| 12935 ins_cost(300); | |
| 12936 format %{ "CALL,runtime " %} | |
| 12937 opcode(0xE8); /* E8 cd */ | |
| 12938 // Use FFREEs to clear entries in float stack | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12939 ins_encode( pre_call_resets, |
| 0 | 12940 FFree_Float_Stack_All, |
| 12941 Java_To_Runtime( meth ), | |
| 12942 post_call_FPU ); | |
| 12943 ins_pipe( pipe_slow ); | |
| 12944 %} | |
| 12945 | |
| 12946 // Call runtime without safepoint | |
| 12947 instruct CallLeafDirect(method meth) %{ | |
| 12948 match(CallLeaf); | |
| 12949 effect(USE meth); | |
| 12950 | |
| 12951 ins_cost(300); | |
| 12952 format %{ "CALL_LEAF,runtime " %} | |
| 12953 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
12954 ins_encode( pre_call_resets, |
| 0 | 12955 FFree_Float_Stack_All, |
| 12956 Java_To_Runtime( meth ), | |
| 12957 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12958 ins_pipe( pipe_slow ); | |
| 12959 %} | |
| 12960 | |
| 12961 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12962 match(CallLeafNoFP); | |
| 12963 effect(USE meth); | |
| 12964 | |
| 12965 ins_cost(300); | |
| 12966 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12967 opcode(0xE8); /* E8 cd */ | |
| 12968 ins_encode(Java_To_Runtime(meth)); | |
| 12969 ins_pipe( pipe_slow ); | |
| 12970 %} | |
| 12971 | |
| 12972 | |
| 12973 // Return Instruction | |
| 12974 // Remove the return address & jump to it. | |
| 12975 instruct Ret() %{ | |
| 12976 match(Return); | |
| 12977 format %{ "RET" %} | |
| 12978 opcode(0xC3); | |
| 12979 ins_encode(OpcP); | |
| 12980 ins_pipe( pipe_jmp ); | |
| 12981 %} | |
| 12982 | |
| 12983 // Tail Call; Jump from runtime stub to Java code. | |
| 12984 // Also known as an 'interprocedural jump'. | |
| 12985 // Target of jump will eventually return to caller. | |
| 12986 // TailJump below removes the return address. | |
| 12987 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12988 match(TailCall jump_target method_oop ); | |
| 12989 ins_cost(300); | |
| 12990 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12991 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12992 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12993 ins_pipe( pipe_jmp ); | |
| 12994 %} | |
| 12995 | |
| 12996 | |
| 12997 // Tail Jump; remove the return address; jump to target. | |
| 12998 // TailCall above leaves the return address around. | |
| 12999 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13000 match( TailJump jump_target ex_oop ); | |
| 13001 ins_cost(300); | |
| 13002 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13003 "JMP $jump_target " %} | |
| 13004 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13005 ins_encode( enc_pop_rdx, | |
| 13006 OpcP, RegOpc(jump_target) ); | |
| 13007 ins_pipe( pipe_jmp ); | |
| 13008 %} | |
| 13009 | |
| 13010 // Create exception oop: created by stack-crawling runtime code. | |
| 13011 // Created exception is now available to this handler, and is setup | |
| 13012 // just prior to jumping to this handler. No code emitted. | |
| 13013 instruct CreateException( eAXRegP ex_oop ) | |
| 13014 %{ | |
| 13015 match(Set ex_oop (CreateEx)); | |
| 13016 | |
| 13017 size(0); | |
| 13018 // use the following format syntax | |
| 13019 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13020 ins_encode(); | |
| 13021 ins_pipe( empty ); | |
| 13022 %} | |
| 13023 | |
| 13024 | |
| 13025 // Rethrow exception: | |
| 13026 // The exception oop will come in the first argument position. | |
| 13027 // Then JUMP (not call) to the rethrow stub code. | |
| 13028 instruct RethrowException() | |
| 13029 %{ | |
| 13030 match(Rethrow); | |
| 13031 | |
| 13032 // use the following format syntax | |
| 13033 format %{ "JMP rethrow_stub" %} | |
| 13034 ins_encode(enc_rethrow); | |
| 13035 ins_pipe( pipe_jmp ); | |
| 13036 %} | |
| 13037 | |
| 13038 // inlined locking and unlocking | |
| 13039 | |
| 17780 | 13040 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{ |
| 13041 predicate(Compile::current()->use_rtm()); | |
| 13042 match(Set cr (FastLock object box)); | |
| 13043 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); | |
| 13044 ins_cost(300); | |
| 13045 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} | |
| 13046 ins_encode %{ | |
| 13047 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, | |
| 13048 $scr$$Register, $cx1$$Register, $cx2$$Register, | |
| 13049 _counters, _rtm_counters, _stack_rtm_counters, | |
| 13050 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), | |
| 13051 true, ra_->C->profile_rtm()); | |
| 13052 %} | |
| 13053 ins_pipe(pipe_slow); | |
| 13054 %} | |
| 13055 | |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13056 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 17780 | 13057 predicate(!Compile::current()->use_rtm()); |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13058 match(Set cr (FastLock object box)); |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13059 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 13060 ins_cost(300); |
| 4777 | 13061 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13062 ins_encode %{ |
| 17780 | 13063 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
| 13064 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); | |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13065 %} |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13066 ins_pipe(pipe_slow); |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13067 %} |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13068 |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13069 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13070 match(Set cr (FastUnlock object box)); |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13071 effect(TEMP tmp, USE_KILL box); |
| 0 | 13072 ins_cost(300); |
| 4777 | 13073 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13074 ins_encode %{ |
| 17780 | 13075 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13076 %} |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
13077 ins_pipe(pipe_slow); |
| 0 | 13078 %} |
| 13079 | |
| 13080 | |
| 13081 | |
| 13082 // ============================================================================ | |
| 13083 // Safepoint Instruction | |
| 13084 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13085 match(SafePoint); | |
| 13086 effect(KILL cr); | |
| 13087 | |
| 13088 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13089 // On SPARC that might be acceptable as we can generate the address with | |
| 13090 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13091 // putting additional pressure on the index-0 in the D$. Because of | |
| 13092 // alignment (just like the situation at hand) the lower indices tend | |
| 13093 // to see more traffic. It'd be better to change the polling address | |
| 13094 // to offset 0 of the last $line in the polling page. | |
| 13095 | |
| 13096 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13097 ins_cost(125); | |
| 13098 size(6) ; | |
| 13099 ins_encode( Safepoint_Poll() ); | |
| 13100 ins_pipe( ialu_reg_mem ); | |
| 13101 %} | |
| 13102 | |
| 4950 | 13103 |
| 13104 // ============================================================================ | |
| 13105 // This name is KNOWN by the ADLC and cannot be changed. | |
| 13106 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 13107 // for this guy. | |
| 13108 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 13109 match(Set dst (ThreadLocal)); | |
| 13110 effect(DEF dst, KILL cr); | |
| 13111 | |
| 13112 format %{ "MOV $dst, Thread::current()" %} | |
| 13113 ins_encode %{ | |
| 13114 Register dstReg = as_Register($dst$$reg); | |
| 13115 __ get_thread(dstReg); | |
| 13116 %} | |
| 13117 ins_pipe( ialu_reg_fat ); | |
| 13118 %} | |
| 13119 | |
| 13120 | |
| 13121 | |
| 0 | 13122 //----------PEEPHOLE RULES----------------------------------------------------- |
| 13123 // These must follow all instruction definitions as they use the names | |
| 13124 // defined in the instructions definitions. | |
| 13125 // | |
| 605 | 13126 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13127 // |
| 13128 // peepconstraint %{ | |
| 13129 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13130 // [, ...] ); | |
| 13131 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13132 // | |
| 13133 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13134 // // provide an instruction_number.operand_name for each operand that appears | |
| 13135 // // in the replacement instruction's match rule | |
| 13136 // | |
| 13137 // ---------VM FLAGS--------------------------------------------------------- | |
| 13138 // | |
| 13139 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13140 // | |
| 13141 // Each peephole rule is given an identifying number starting with zero and | |
| 13142 // increasing by one in the order seen by the parser. An individual peephole | |
| 13143 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13144 // on the command-line. | |
| 13145 // | |
| 13146 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13147 // | |
| 13148 // Only match adjacent instructions in same basic block | |
| 13149 // Only equality constraints | |
| 13150 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13151 // Only one replacement instruction | |
| 13152 // | |
| 13153 // ---------EXAMPLE---------------------------------------------------------- | |
| 13154 // | |
| 13155 // // pertinent parts of existing instructions in architecture description | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13156 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 13157 // match(Set dst (CopyI src)); |
| 13158 // %} | |
| 13159 // | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13160 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13161 // match(Set dst (AddI dst src)); |
| 13162 // effect(KILL cr); | |
| 13163 // %} | |
| 13164 // | |
| 13165 // // Change (inc mov) to lea | |
| 13166 // peephole %{ | |
| 13167 // // increment preceeded by register-register move | |
| 13168 // peepmatch ( incI_eReg movI ); | |
| 13169 // // require that the destination register of the increment | |
| 13170 // // match the destination register of the move | |
| 13171 // peepconstraint ( 0.dst == 1.dst ); | |
| 13172 // // construct a replacement instruction that sets | |
| 13173 // // the destination to ( move's source register + one ) | |
| 13174 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13175 // %} | |
| 13176 // | |
| 13177 // Implementation no longer uses movX instructions since | |
| 13178 // machine-independent system no longer uses CopyX nodes. | |
| 13179 // | |
| 13180 // peephole %{ | |
| 13181 // peepmatch ( incI_eReg movI ); | |
| 13182 // peepconstraint ( 0.dst == 1.dst ); | |
| 13183 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13184 // %} | |
| 13185 // | |
| 13186 // peephole %{ | |
| 13187 // peepmatch ( decI_eReg movI ); | |
| 13188 // peepconstraint ( 0.dst == 1.dst ); | |
| 13189 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13190 // %} | |
| 13191 // | |
| 13192 // peephole %{ | |
| 13193 // peepmatch ( addI_eReg_imm movI ); | |
| 13194 // peepconstraint ( 0.dst == 1.dst ); | |
| 13195 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13196 // %} | |
| 13197 // | |
| 13198 // peephole %{ | |
| 13199 // peepmatch ( addP_eReg_imm movP ); | |
| 13200 // peepconstraint ( 0.dst == 1.dst ); | |
| 13201 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13202 // %} | |
| 13203 | |
| 13204 // // Change load of spilled value to only a spill | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13205 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13206 // match(Set mem (StoreI mem src)); |
| 13207 // %} | |
| 13208 // | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
13209 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13210 // match(Set dst (LoadI mem)); |
| 13211 // %} | |
| 13212 // | |
| 13213 peephole %{ | |
| 13214 peepmatch ( loadI storeI ); | |
| 13215 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13216 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13217 %} | |
| 13218 | |
| 13219 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13220 // These must follow all instruction definitions as they use the names | |
| 13221 // defined in the instructions definitions. |