Mercurial > hg > graal-jvmci-8

annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 24234:ea6f94ab283b default tip

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Added tag jvmci-0.36 for changeset 8128b98d4736
author Gilles Duboscq <gilles.m.duboscq@oracle.com>
date Mon, 18 Sep 2017 18:49:45 +0200
parents f13e777eb255
children
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1 /*
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "asm/macroAssembler.inline.hpp"
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27 #include "memory/resourceArea.hpp"
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28 #include "runtime/java.hpp"
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29 #include "runtime/stubCodeGenerator.hpp"
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30 #include "vm_version_sparc.hpp"
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31 #ifdef TARGET_OS_FAMILY_linux
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32 # include "os_linux.inline.hpp"
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33 #endif
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34 #ifdef TARGET_OS_FAMILY_solaris
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35 # include "os_solaris.inline.hpp"
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36 #endif
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37
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38 int VM_Version::_features = VM_Version::unknown_m;
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39 const char* VM_Version::_features_str = "";
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40 unsigned int VM_Version::_L2_data_cache_line_size = 0;
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41
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42 void VM_Version::initialize() {
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43
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44 assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete.");
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45 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
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46
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47 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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48 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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49 PrefetchFieldsAhead = prefetch_fields_ahead();
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50
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51 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
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52 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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53 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
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54
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55 // Allocation prefetch settings
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56 intx cache_line_size = prefetch_data_size();
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57 if( cache_line_size > AllocatePrefetchStepSize )
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58 AllocatePrefetchStepSize = cache_line_size;
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59
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60 assert(AllocatePrefetchLines > 0, "invalid value");
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61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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62 AllocatePrefetchLines = 3;
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63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
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64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
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65 AllocateInstancePrefetchLines = 1;
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67 AllocatePrefetchDistance = allocate_prefetch_distance();
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68 AllocatePrefetchStyle = allocate_prefetch_style();
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69
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70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
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71 (AllocatePrefetchDistance > 0), "invalid value");
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72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
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73 (AllocatePrefetchDistance <= 0)) {
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74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
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75 }
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76
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77 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
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78 warning("BIS instructions are not available on this CPU");
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79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
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80 }
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81
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82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
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83 if (ArraycopySrcPrefetchDistance >= 4096)
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84 ArraycopySrcPrefetchDistance = 4064;
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85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
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86 if (ArraycopyDstPrefetchDistance >= 4096)
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87 ArraycopyDstPrefetchDistance = 4064;
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88
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89 UseSSE = 0; // Only on x86 and x64
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90
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91 _supports_cx8 = has_v9();
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92 _supports_atomic_getset4 = true; // swap instruction
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93
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94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
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95 // we have to take this check out of the 'is_niagara()' block below.
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96 if (has_blk_init()) {
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97 // When using CMS or G1, we cannot use memset() in BOT updates
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98 // because the sun4v/CMT version in libc_psr uses BIS which
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99 // exposes "phantom zeros" to concurrent readers. See 6948537.
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100 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
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101 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
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102 }
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103 // Issue a stern warning if the user has explicitly set
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104 // UseMemSetInBOT (it is known to cause issues), but allow
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105 // use for experimentation and debugging.
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106 if (UseConcMarkSweepGC || UseG1GC) {
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107 if (UseMemSetInBOT) {
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108 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
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109 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
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110 " on sun4v; please understand that you are using at your own risk!");
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111 }
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112 }
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113 }
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114
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115 if (is_niagara()) {
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116 // Indirect branch is the same cost as direct
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117 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
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118 FLAG_SET_DEFAULT(UseInlineCaches, false);
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119 }
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120 // Align loops on a single instruction boundary.
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121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
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122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
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123 }
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124 #ifdef _LP64
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125 // 32-bit oops don't make sense for the 64-bit VM on sparc
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126 // since the 32-bit VM has the same registers and smaller objects.
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127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
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128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
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129 #endif // _LP64
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130 #ifdef COMPILER2
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131 // Indirect branch is the same cost as direct
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132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
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133 FLAG_SET_DEFAULT(UseJumpTables, true);
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134 }
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135 // Single-issue, so entry and loop tops are
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136 // aligned on a single instruction boundary
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137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
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138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
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139 }
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140 if (is_niagara_plus()) {
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141 if (has_blk_init() && UseTLAB &&
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142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
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143 // Use BIS instruction for TLAB allocation prefetch.
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144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
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145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
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146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
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147 }
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148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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149 // Use smaller prefetch distance with BIS
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150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
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151 }
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152 }
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153 if (is_T4()) {
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154 // Double number of prefetched cache lines on T4
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155 // since L2 cache line size is smaller (32 bytes).
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156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
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157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
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158 }
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159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
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160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
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161 }
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162 }
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diff changeset
163 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
9e321dcfa5b7 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 1365
diff changeset
164 // Use different prefetch distance without BIS
9e321dcfa5b7 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 1365
diff changeset
165 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
9e321dcfa5b7 6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents: 1365
diff changeset
166 }
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
167 if (AllocatePrefetchInstr == 1) {
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
168 // Need a space at the end of TLAB for BIS since it
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
169 // will fault when accessing memory outside of heap.
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
170
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
171 // +1 for rounding up to next cache line, +1 to be safe
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
172 int lines = AllocatePrefetchLines + 2;
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
173 int step_size = AllocatePrefetchStepSize;
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
174 int distance = AllocatePrefetchDistance;
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
175 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
176 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
177 }
a61af66fc99e Initial load
duke
parents:
diff changeset
178 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
179 }
a61af66fc99e Initial load
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parents:
diff changeset
180
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
181 // Use hardware population count instruction if available.
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
182 if (has_hardware_popc()) {
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
183 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
675
f6da6f0174ac 6821700: tune VM flags for peak performance
kvn
parents: 643
diff changeset
184 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
185 }
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
186 } else if (UsePopCountInstruction) {
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
187 warning("POPC instruction is not available on this CPU");
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
188 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
189 }
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
190
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
191 // T4 and newer Sparc cpus have new compare and branch instruction.
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
192 if (has_cbcond()) {
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
193 if (FLAG_IS_DEFAULT(UseCBCond)) {
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
194 FLAG_SET_DEFAULT(UseCBCond, true);
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
195 }
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
196 } else if (UseCBCond) {
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
197 warning("CBCOND instruction is not available on this CPU");
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
198 FLAG_SET_DEFAULT(UseCBCond, false);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
199 }
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
200
3892
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
201 assert(BlockZeroingLowLimit > 0, "invalid value");
20421
d635fd1ac81c 8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents: 20313
diff changeset
202 if (has_block_zeroing() && cache_line_size > 0) {
3892
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
203 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
204 FLAG_SET_DEFAULT(UseBlockZeroing, true);
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
205 }
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
206 } else if (UseBlockZeroing) {
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
207 warning("BIS zeroing instructions are not available on this CPU");
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
208 FLAG_SET_DEFAULT(UseBlockZeroing, false);
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
209 }
baf763f388e6 7059037: Use BIS for zeroing on T4
kvn
parents: 3854
diff changeset
210
3903
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
211 assert(BlockCopyLowLimit > 0, "invalid value");
20421
d635fd1ac81c 8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents: 20313
diff changeset
212 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
3903
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
213 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
214 FLAG_SET_DEFAULT(UseBlockCopy, true);
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
215 }
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
216 } else if (UseBlockCopy) {
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
217 warning("BIS instructions are not available or expensive on this CPU");
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
218 FLAG_SET_DEFAULT(UseBlockCopy, false);
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
219 }
2f9b79ddb05c 7039731: arraycopy could use prefetch on SPARC
kvn
parents: 3892
diff changeset
220
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
221 #ifdef COMPILER2
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
222 // T4 and newer Sparc cpus have fast RDPC.
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
223 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
4053
e3b0dcc327b9 7104561: UseRDPCForConstantTableBase doesn't work after shorten branches changes
twisti
parents: 3903
diff changeset
224 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
225 }
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
226
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
227 // Currently not supported anywhere.
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
228 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3839
diff changeset
229
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4053
diff changeset
230 MaxVectorSize = 8;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4053
diff changeset
231
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3839
diff changeset
232 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
233 #endif
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1579
diff changeset
234
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3839
diff changeset
235 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3839
diff changeset
236 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3839
diff changeset
237
0
a61af66fc99e Initial load
duke
parents:
diff changeset
238 char buf[512];
20313
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
239 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
240 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
241 (has_hardware_popc() ? ", popc" : ""),
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
242 (has_vis1() ? ", vis1" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
243 (has_vis2() ? ", vis2" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
244 (has_vis3() ? ", vis3" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
245 (has_blk_init() ? ", blk_init" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
246 (has_cbcond() ? ", cbcond" : ""),
14261
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
247 (has_aes() ? ", aes" : ""),
20313
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
248 (has_sha1() ? ", sha1" : ""),
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
249 (has_sha256() ? ", sha256" : ""),
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
250 (has_sha512() ? ", sha512" : ""),
3839
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
251 (is_ultra3() ? ", ultra3" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
252 (is_sun4v() ? ", sun4v" : ""),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
253 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
3d42f82cd811 7063628: Use cbcond on T4
kvn
parents: 3804
diff changeset
254 (is_sparc64() ? ", sparc64" : ""),
641
6af0a709d52b 6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents: 196
diff changeset
255 (!has_hardware_mul32() ? ", no-mul32" : ""),
6af0a709d52b 6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents: 196
diff changeset
256 (!has_hardware_div32() ? ", no-div32" : ""),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
257 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
a61af66fc99e Initial load
duke
parents:
diff changeset
258
a61af66fc99e Initial load
duke
parents:
diff changeset
259 // buf is started with ", " or is empty
a61af66fc99e Initial load
duke
parents:
diff changeset
260 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
a61af66fc99e Initial load
duke
parents:
diff changeset
261
3804
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
262 // UseVIS is set to the smallest of what hardware supports and what
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
263 // the command line requires. I.e., you cannot set UseVIS to 3 on
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
264 // older UltraSparc which do not support it.
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
265 if (UseVIS > 3) UseVIS=3;
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
266 if (UseVIS < 0) UseVIS=0;
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
267 if (!has_vis3()) // Drop to 2 if no VIS3 support
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
268 UseVIS = MIN2((intx)2,UseVIS);
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
269 if (!has_vis2()) // Drop to 1 if no VIS2 support
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
270 UseVIS = MIN2((intx)1,UseVIS);
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
271 if (!has_vis1()) // Drop to 0 if no VIS1 support
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
272 UseVIS = 0;
faa472957b38 7059034: Use movxtod/movdtox on T4
kvn
parents: 2080
diff changeset
273
17910
03214612e77e 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 14261
diff changeset
274 // SPARC T4 and above should have support for AES instructions
14261
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
275 if (has_aes()) {
17910
03214612e77e 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 14261
diff changeset
276 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
14261
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
277 if (FLAG_IS_DEFAULT(UseAES)) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
278 FLAG_SET_DEFAULT(UseAES, true);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
279 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
280 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
281 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
282 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
283 // we disable both the AES flags if either of them is disabled on the command line
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
284 if (!UseAES || !UseAESIntrinsics) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
285 FLAG_SET_DEFAULT(UseAES, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
286 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
287 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
288 } else {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
289 if (UseAES || UseAESIntrinsics) {
17910
03214612e77e 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents: 14261
diff changeset
290 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
14261
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
291 if (UseAES) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
292 FLAG_SET_DEFAULT(UseAES, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
293 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
294 if (UseAESIntrinsics) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
295 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
296 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
297 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
298 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
299 } else if (UseAES || UseAESIntrinsics) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
300 warning("AES instructions are not available on this CPU");
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
301 if (UseAES) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
302 FLAG_SET_DEFAULT(UseAES, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
303 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
304 if (UseAESIntrinsics) {
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
305 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
306 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
307 }
00f5eff62d18 8002074: Support for AES on SPARC
kvn
parents: 14223
diff changeset
308
20313
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
309 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
310 if (has_sha1() || has_sha256() || has_sha512()) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
311 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
312 if (FLAG_IS_DEFAULT(UseSHA)) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
313 FLAG_SET_DEFAULT(UseSHA, true);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
314 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
315 } else {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
316 if (UseSHA) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
317 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
318 FLAG_SET_DEFAULT(UseSHA, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
319 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
320 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
321 } else if (UseSHA) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
322 warning("SHA instructions are not available on this CPU");
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
323 FLAG_SET_DEFAULT(UseSHA, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
324 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
325
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
326 if (!UseSHA) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
327 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
328 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
329 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
330 } else {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
331 if (has_sha1()) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
332 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
333 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
334 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
335 } else if (UseSHA1Intrinsics) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
336 warning("SHA1 instruction is not available on this CPU.");
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
337 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
338 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
339 if (has_sha256()) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
340 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
341 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
342 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
343 } else if (UseSHA256Intrinsics) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
344 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
345 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
346 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
347
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
348 if (has_sha512()) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
349 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
350 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
351 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
352 } else if (UseSHA512Intrinsics) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
353 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
354 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
355 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
356 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
357 FLAG_SET_DEFAULT(UseSHA, false);
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
358 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
359 }
b20a35eae442 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 17937
diff changeset
360
7587
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
361 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
362 (cache_line_size > ContendedPaddingWidth))
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
363 ContendedPaddingWidth = cache_line_size;
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
364
0
a61af66fc99e Initial load
duke
parents:
diff changeset
365 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
366 if (PrintMiscellaneous && Verbose) {
22963
f79d8e8caecb 8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect
iveresov
parents: 20421
diff changeset
367 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
368 tty->print("Allocation");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
369 if (AllocatePrefetchStyle <= 0) {
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
370 tty->print_cr(": no prefetching");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
371 } else {
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
372 tty->print(" prefetching: ");
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
373 if (AllocatePrefetchInstr == 0) {
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
374 tty->print("PREFETCH");
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
375 } else if (AllocatePrefetchInstr == 1) {
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
376 tty->print("BIS");
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
377 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
378 if (AllocatePrefetchLines > 1) {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
379 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
380 } else {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
381 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
382 }
a61af66fc99e Initial load
duke
parents:
diff changeset
383 }
a61af66fc99e Initial load
duke
parents:
diff changeset
384 if (PrefetchCopyIntervalInBytes > 0) {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
385 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
386 }
a61af66fc99e Initial load
duke
parents:
diff changeset
387 if (PrefetchScanIntervalInBytes > 0) {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
388 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
389 }
a61af66fc99e Initial load
duke
parents:
diff changeset
390 if (PrefetchFieldsAhead > 0) {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
391 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
392 }
7587
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
393 if (ContendedPaddingWidth > 0) {
17937
78bbf4d43a14 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 17910
diff changeset
394 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
7587
4a916f2ce331 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 7204
diff changeset
395 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
396 }
a61af66fc99e Initial load
duke
parents:
diff changeset
397 #endif // PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
398 }
a61af66fc99e Initial load
duke
parents:
diff changeset
399
a61af66fc99e Initial load
duke
parents:
diff changeset
400 void VM_Version::print_features() {
a61af66fc99e Initial load
duke
parents:
diff changeset
401 tty->print_cr("Version:%s", cpu_features());
a61af66fc99e Initial load
duke
parents:
diff changeset
402 }
a61af66fc99e Initial load
duke
parents:
diff changeset
403
a61af66fc99e Initial load
duke
parents:
diff changeset
404 int VM_Version::determine_features() {
a61af66fc99e Initial load
duke
parents:
diff changeset
405 if (UseV8InstrsOnly) {
a61af66fc99e Initial load
duke
parents:
diff changeset
406 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
a61af66fc99e Initial load
duke
parents:
diff changeset
407 return generic_v8_m;
a61af66fc99e Initial load
duke
parents:
diff changeset
408 }
a61af66fc99e Initial load
duke
parents:
diff changeset
409
a61af66fc99e Initial load
duke
parents:
diff changeset
410 int features = platform_features(unknown_m); // platform_features() is os_arch specific
a61af66fc99e Initial load
duke
parents:
diff changeset
411
a61af66fc99e Initial load
duke
parents:
diff changeset
412 if (features == unknown_m) {
a61af66fc99e Initial load
duke
parents:
diff changeset
413 features = generic_v9_m;
a61af66fc99e Initial load
duke
parents:
diff changeset
414 warning("Cannot recognize SPARC version. Default to V9");
a61af66fc99e Initial load
duke
parents:
diff changeset
415 }
a61af66fc99e Initial load
duke
parents:
diff changeset
416
2080
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
417 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
418 if (UseNiagaraInstrs) { // Force code generation for Niagara
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
419 if (is_T_family(features)) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
420 // Happy to accomodate...
a61af66fc99e Initial load
duke
parents:
diff changeset
421 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
422 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
2080
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
423 features |= T_family_m;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
424 }
a61af66fc99e Initial load
duke
parents:
diff changeset
425 } else {
2080
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
426 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
427 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
2080
c04052fd6ae1 7006505: Use kstat info to identify SPARC processor
kvn
parents: 1972
diff changeset
428 features &= ~(T_family_m | T1_model_m);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
429 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
430 // Happy to accomodate...
a61af66fc99e Initial load
duke
parents:
diff changeset
431 }
a61af66fc99e Initial load
duke
parents:
diff changeset
432 }
a61af66fc99e Initial load
duke
parents:
diff changeset
433
a61af66fc99e Initial load
duke
parents:
diff changeset
434 return features;
a61af66fc99e Initial load
duke
parents:
diff changeset
435 }
a61af66fc99e Initial load
duke
parents:
diff changeset
436
a61af66fc99e Initial load
duke
parents:
diff changeset
437 static int saved_features = 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
438
a61af66fc99e Initial load
duke
parents:
diff changeset
439 void VM_Version::allow_all() {
a61af66fc99e Initial load
duke
parents:
diff changeset
440 saved_features = _features;
a61af66fc99e Initial load
duke
parents:
diff changeset
441 _features = all_features_m;
a61af66fc99e Initial load
duke
parents:
diff changeset
442 }
a61af66fc99e Initial load
duke
parents:
diff changeset
443
a61af66fc99e Initial load
duke
parents:
diff changeset
444 void VM_Version::revert() {
a61af66fc99e Initial load
duke
parents:
diff changeset
445 _features = saved_features;
a61af66fc99e Initial load
duke
parents:
diff changeset
446 }
10
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
447
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
448 unsigned int VM_Version::calc_parallel_worker_threads() {
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
449 unsigned int result;
6797
3a327d0b8586 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents: 6795
diff changeset
450 if (is_M_series()) {
3a327d0b8586 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents: 6795
diff changeset
451 // for now, use same gc thread calculation for M-series as for niagara-plus
3a327d0b8586 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents: 6795
diff changeset
452 // in future, we may want to tweak parameters for nof_parallel_worker_thread
3a327d0b8586 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents: 6795
diff changeset
453 result = nof_parallel_worker_threads(5, 16, 8);
3a327d0b8586 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents: 6795
diff changeset
454 } else if (is_niagara_plus()) {
10
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
455 result = nof_parallel_worker_threads(5, 16, 8);
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
456 } else {
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
457 result = nof_parallel_worker_threads(5, 8, 8);
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
458 }
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
459 return result;
28372612af5e 6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents: 0
diff changeset
460 }