Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 4759:127b3692c168
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Wed, 14 Dec 2011 14:54:38 -0800 |
| parents | 6729bbc1fcd6 |
| children | 65149e74c706 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
| 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
| 27 | |
| 0 | 28 class BiasedLockingCounters; |
| 29 | |
| 30 // Contains all the definitions needed for x86 assembly code generation. | |
| 31 | |
| 32 // Calling convention | |
| 33 class Argument VALUE_OBJ_CLASS_SPEC { | |
| 34 public: | |
| 35 enum { | |
| 36 #ifdef _LP64 | |
| 37 #ifdef _WIN64 | |
| 38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
| 40 #else | |
| 41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
| 43 #endif // _WIN64 | |
| 44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
| 45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
| 46 #else | |
| 47 n_register_parameters = 0 // 0 registers used to pass arguments | |
| 48 #endif // _LP64 | |
| 49 }; | |
| 50 }; | |
| 51 | |
| 52 | |
| 53 #ifdef _LP64 | |
| 54 // Symbolically name the register arguments used by the c calling convention. | |
| 55 // Windows is different from linux/solaris. So much for standards... | |
| 56 | |
| 57 #ifdef _WIN64 | |
| 58 | |
| 59 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
| 60 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
| 61 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
| 62 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
| 63 | |
| 304 | 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 0 | 68 |
| 69 #else | |
| 70 | |
| 71 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
| 72 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
| 73 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
| 74 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
| 75 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
| 76 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
| 77 | |
| 304 | 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
| 79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
| 83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
| 84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
| 85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
| 0 | 86 |
| 87 #endif // _WIN64 | |
| 88 | |
| 89 // Symbolically name the register arguments used by the Java calling convention. | |
| 90 // We have control over the convention for java so we can do what we please. | |
| 91 // What pleases us is to offset the java calling convention so that when | |
| 92 // we call a suitable jni method the arguments are lined up and we don't | |
| 93 // have to do little shuffling. A suitable jni method is non-static and a | |
| 94 // small number of arguments (two fewer args on windows) | |
| 95 // | |
| 96 // |-------------------------------------------------------| | |
| 97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
| 98 // |-------------------------------------------------------| | |
| 99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
| 100 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
| 101 // |-------------------------------------------------------| | |
| 102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
| 103 // |-------------------------------------------------------| | |
| 104 | |
| 105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
| 106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
| 107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
| 108 // Windows runs out of register args here | |
| 109 #ifdef _WIN64 | |
| 110 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
| 111 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
| 112 #else | |
| 113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
| 114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
| 115 #endif /* _WIN64 */ | |
| 116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
| 117 | |
| 304 | 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
| 119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
| 120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
| 121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
| 122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
| 123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
| 124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
| 125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
| 0 | 126 |
| 127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
| 128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
| 129 | |
| 304 | 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
| 0 | 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
| 132 | |
| 304 | 133 #else |
| 134 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
| 135 // Using noreg ensures if the dead code is incorrectly live and executed it | |
| 136 // will cause an assertion failure | |
| 137 #define rscratch1 noreg | |
| 2002 | 138 #define rscratch2 noreg |
| 304 | 139 |
| 0 | 140 #endif // _LP64 |
| 141 | |
| 1564 | 142 // JSR 292 fixed register usages: |
| 143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
| 144 | |
| 0 | 145 // Address is an abstraction used to represent a memory location |
| 146 // using any of the amd64 addressing modes with one object. | |
| 147 // | |
| 148 // Note: A register location is represented via a Register, not | |
| 149 // via an address for efficiency & simplicity reasons. | |
| 150 | |
| 151 class ArrayAddress; | |
| 152 | |
| 153 class Address VALUE_OBJ_CLASS_SPEC { | |
| 154 public: | |
| 155 enum ScaleFactor { | |
| 156 no_scale = -1, | |
| 157 times_1 = 0, | |
| 158 times_2 = 1, | |
| 159 times_4 = 2, | |
| 304 | 160 times_8 = 3, |
| 161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
| 0 | 162 }; |
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163 static ScaleFactor times(int size) { |
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164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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165 if (size == 8) return times_8; |
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166 if (size == 4) return times_4; |
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167 if (size == 2) return times_2; |
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168 return times_1; |
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169 } |
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170 static int scale_size(ScaleFactor scale) { |
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171 assert(scale != no_scale, ""); |
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172 assert(((1 << (int)times_1) == 1 && |
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173 (1 << (int)times_2) == 2 && |
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174 (1 << (int)times_4) == 4 && |
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175 (1 << (int)times_8) == 8), ""); |
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176 return (1 << (int)scale); |
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177 } |
| 0 | 178 |
| 179 private: | |
| 180 Register _base; | |
| 181 Register _index; | |
| 182 ScaleFactor _scale; | |
| 183 int _disp; | |
| 184 RelocationHolder _rspec; | |
| 185 | |
| 304 | 186 // Easily misused constructors make them private |
| 187 // %%% can we make these go away? | |
| 188 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
| 189 Address(int disp, address loc, relocInfo::relocType rtype); | |
| 190 Address(int disp, address loc, RelocationHolder spec); | |
| 0 | 191 |
| 192 public: | |
| 304 | 193 |
| 194 int disp() { return _disp; } | |
| 0 | 195 // creation |
| 196 Address() | |
| 197 : _base(noreg), | |
| 198 _index(noreg), | |
| 199 _scale(no_scale), | |
| 200 _disp(0) { | |
| 201 } | |
| 202 | |
| 203 // No default displacement otherwise Register can be implicitly | |
| 204 // converted to 0(Register) which is quite a different animal. | |
| 205 | |
| 206 Address(Register base, int disp) | |
| 207 : _base(base), | |
| 208 _index(noreg), | |
| 209 _scale(no_scale), | |
| 210 _disp(disp) { | |
| 211 } | |
| 212 | |
| 213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
| 214 : _base (base), | |
| 215 _index(index), | |
| 216 _scale(scale), | |
| 217 _disp (disp) { | |
| 218 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 219 "inconsistent address"); | |
| 220 } | |
| 221 | |
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222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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223 : _base (base), |
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224 _index(index.register_or_noreg()), |
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225 _scale(scale), |
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226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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227 if (!index.is_register()) scale = Address::no_scale; |
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228 assert(!_index->is_valid() == (scale == Address::no_scale), |
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229 "inconsistent address"); |
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230 } |
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231 |
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232 Address plus_disp(int disp) const { |
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233 Address a = (*this); |
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234 a._disp += disp; |
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235 return a; |
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236 } |
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237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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238 Address a = (*this); |
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239 a._disp += disp.constant_or_zero() * scale_size(scale); |
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240 if (disp.is_register()) { |
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241 assert(!a.index()->is_valid(), "competing indexes"); |
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242 a._index = disp.as_register(); |
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243 a._scale = scale; |
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244 } |
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245 return a; |
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246 } |
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247 bool is_same_address(Address a) const { |
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248 // disregard _rspec |
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249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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250 } |
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251 |
| 0 | 252 // The following two overloads are used in connection with the |
| 253 // ByteSize type (see sizes.hpp). They simplify the use of | |
| 254 // ByteSize'd arguments in assembly code. Note that their equivalent | |
| 255 // for the optimized build are the member functions with int disp | |
| 256 // argument since ByteSize is mapped to an int type in that case. | |
| 257 // | |
| 258 // Note: DO NOT introduce similar overloaded functions for WordSize | |
| 259 // arguments as in the optimized mode, both ByteSize and WordSize | |
| 260 // are mapped to the same type and thus the compiler cannot make a | |
| 261 // distinction anymore (=> compiler errors). | |
| 262 | |
| 263 #ifdef ASSERT | |
| 264 Address(Register base, ByteSize disp) | |
| 265 : _base(base), | |
| 266 _index(noreg), | |
| 267 _scale(no_scale), | |
| 268 _disp(in_bytes(disp)) { | |
| 269 } | |
| 270 | |
| 271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
| 272 : _base(base), | |
| 273 _index(index), | |
| 274 _scale(scale), | |
| 275 _disp(in_bytes(disp)) { | |
| 276 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 277 "inconsistent address"); | |
| 278 } | |
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279 |
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280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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281 : _base (base), |
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282 _index(index.register_or_noreg()), |
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283 _scale(scale), |
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284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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285 if (!index.is_register()) scale = Address::no_scale; |
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286 assert(!_index->is_valid() == (scale == Address::no_scale), |
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287 "inconsistent address"); |
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288 } |
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289 |
| 0 | 290 #endif // ASSERT |
| 291 | |
| 292 // accessors | |
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293 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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294 Register base() const { return _base; } |
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295 Register index() const { return _index; } |
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296 ScaleFactor scale() const { return _scale; } |
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297 int disp() const { return _disp; } |
| 0 | 298 |
| 299 // Convert the raw encoding form into the form expected by the constructor for | |
| 300 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 301 // that to noreg for the Address constructor. | |
| 624 | 302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
| 0 | 303 |
| 304 static Address make_array(ArrayAddress); | |
| 305 | |
| 306 private: | |
| 307 bool base_needs_rex() const { | |
| 308 return _base != noreg && _base->encoding() >= 8; | |
| 309 } | |
| 310 | |
| 311 bool index_needs_rex() const { | |
| 312 return _index != noreg &&_index->encoding() >= 8; | |
| 313 } | |
| 314 | |
| 315 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 316 | |
| 317 friend class Assembler; | |
| 318 friend class MacroAssembler; | |
| 319 friend class LIR_Assembler; // base/index/scale/disp | |
| 320 }; | |
| 321 | |
| 322 // | |
| 323 // AddressLiteral has been split out from Address because operands of this type | |
| 324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
| 325 // the few instructions that need to deal with address literals are unique and the | |
| 326 // MacroAssembler does not have to implement every instruction in the Assembler | |
| 327 // in order to search for address literals that may need special handling depending | |
| 328 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
| 329 // directories. | |
| 330 // | |
| 331 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
| 332 friend class ArrayAddress; | |
| 333 RelocationHolder _rspec; | |
| 334 // Typically we use AddressLiterals we want to use their rval | |
| 335 // However in some situations we want the lval (effect address) of the item. | |
| 336 // We provide a special factory for making those lvals. | |
| 337 bool _is_lval; | |
| 338 | |
| 339 // If the target is far we'll need to load the ea of this to | |
| 340 // a register to reach it. Otherwise if near we can do rip | |
| 341 // relative addressing. | |
| 342 | |
| 343 address _target; | |
| 344 | |
| 345 protected: | |
| 346 // creation | |
| 347 AddressLiteral() | |
| 348 : _is_lval(false), | |
| 349 _target(NULL) | |
| 350 {} | |
| 351 | |
| 352 public: | |
| 353 | |
| 354 | |
| 355 AddressLiteral(address target, relocInfo::relocType rtype); | |
| 356 | |
| 357 AddressLiteral(address target, RelocationHolder const& rspec) | |
| 358 : _rspec(rspec), | |
| 359 _is_lval(false), | |
| 360 _target(target) | |
| 361 {} | |
| 362 | |
| 363 AddressLiteral addr() { | |
| 364 AddressLiteral ret = *this; | |
| 365 ret._is_lval = true; | |
| 366 return ret; | |
| 367 } | |
| 368 | |
| 369 | |
| 370 private: | |
| 371 | |
| 372 address target() { return _target; } | |
| 373 bool is_lval() { return _is_lval; } | |
| 374 | |
| 375 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 376 const RelocationHolder& rspec() const { return _rspec; } | |
| 377 | |
| 378 friend class Assembler; | |
| 379 friend class MacroAssembler; | |
| 380 friend class Address; | |
| 381 friend class LIR_Assembler; | |
| 382 }; | |
| 383 | |
| 384 // Convience classes | |
| 385 class RuntimeAddress: public AddressLiteral { | |
| 386 | |
| 387 public: | |
| 388 | |
| 389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
| 390 | |
| 391 }; | |
| 392 | |
| 393 class OopAddress: public AddressLiteral { | |
| 394 | |
| 395 public: | |
| 396 | |
| 397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
| 398 | |
| 399 }; | |
| 400 | |
| 401 class ExternalAddress: public AddressLiteral { | |
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402 private: |
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403 static relocInfo::relocType reloc_for_target(address target) { |
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404 // Sometimes ExternalAddress is used for values which aren't |
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405 // exactly addresses, like the card table base. |
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406 // external_word_type can't be used for values in the first page |
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407 // so just skip the reloc in that case. |
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408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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409 } |
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410 |
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411 public: |
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412 |
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413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
| 0 | 414 |
| 415 }; | |
| 416 | |
| 417 class InternalAddress: public AddressLiteral { | |
| 418 | |
| 419 public: | |
| 420 | |
| 421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
| 422 | |
| 423 }; | |
| 424 | |
| 425 // x86 can do array addressing as a single operation since disp can be an absolute | |
| 426 // address amd64 can't. We create a class that expresses the concept but does extra | |
| 427 // magic on amd64 to get the final result | |
| 428 | |
| 429 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
| 430 private: | |
| 431 | |
| 432 AddressLiteral _base; | |
| 433 Address _index; | |
| 434 | |
| 435 public: | |
| 436 | |
| 437 ArrayAddress() {}; | |
| 438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
| 439 AddressLiteral base() { return _base; } | |
| 440 Address index() { return _index; } | |
| 441 | |
| 442 }; | |
| 443 | |
| 304 | 444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
| 0 | 445 |
| 446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
| 447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
| 448 // is what you get. The Assembler is generating code into a CodeBuffer. | |
| 449 | |
| 450 class Assembler : public AbstractAssembler { | |
| 451 friend class AbstractAssembler; // for the non-virtual hack | |
| 452 friend class LIR_Assembler; // as_Address() | |
| 304 | 453 friend class StubGenerator; |
| 0 | 454 |
| 455 public: | |
| 456 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
| 457 zero = 0x4, | |
| 458 notZero = 0x5, | |
| 459 equal = 0x4, | |
| 460 notEqual = 0x5, | |
| 461 less = 0xc, | |
| 462 lessEqual = 0xe, | |
| 463 greater = 0xf, | |
| 464 greaterEqual = 0xd, | |
| 465 below = 0x2, | |
| 466 belowEqual = 0x6, | |
| 467 above = 0x7, | |
| 468 aboveEqual = 0x3, | |
| 469 overflow = 0x0, | |
| 470 noOverflow = 0x1, | |
| 471 carrySet = 0x2, | |
| 472 carryClear = 0x3, | |
| 473 negative = 0x8, | |
| 474 positive = 0x9, | |
| 475 parity = 0xa, | |
| 476 noParity = 0xb | |
| 477 }; | |
| 478 | |
| 479 enum Prefix { | |
| 480 // segment overrides | |
| 481 CS_segment = 0x2e, | |
| 482 SS_segment = 0x36, | |
| 483 DS_segment = 0x3e, | |
| 484 ES_segment = 0x26, | |
| 485 FS_segment = 0x64, | |
| 486 GS_segment = 0x65, | |
| 487 | |
| 488 REX = 0x40, | |
| 489 | |
| 490 REX_B = 0x41, | |
| 491 REX_X = 0x42, | |
| 492 REX_XB = 0x43, | |
| 493 REX_R = 0x44, | |
| 494 REX_RB = 0x45, | |
| 495 REX_RX = 0x46, | |
| 496 REX_RXB = 0x47, | |
| 497 | |
| 498 REX_W = 0x48, | |
| 499 | |
| 500 REX_WB = 0x49, | |
| 501 REX_WX = 0x4A, | |
| 502 REX_WXB = 0x4B, | |
| 503 REX_WR = 0x4C, | |
| 504 REX_WRB = 0x4D, | |
| 505 REX_WRX = 0x4E, | |
| 4759 | 506 REX_WRXB = 0x4F, |
| 507 | |
| 508 VEX_3bytes = 0xC4, | |
| 509 VEX_2bytes = 0xC5 | |
| 510 }; | |
| 511 | |
| 512 enum VexPrefix { | |
| 513 VEX_B = 0x20, | |
| 514 VEX_X = 0x40, | |
| 515 VEX_R = 0x80, | |
| 516 VEX_W = 0x80 | |
| 517 }; | |
| 518 | |
| 519 enum VexSimdPrefix { | |
| 520 VEX_SIMD_NONE = 0x0, | |
| 521 VEX_SIMD_66 = 0x1, | |
| 522 VEX_SIMD_F3 = 0x2, | |
| 523 VEX_SIMD_F2 = 0x3 | |
| 524 }; | |
| 525 | |
| 526 enum VexOpcode { | |
| 527 VEX_OPCODE_NONE = 0x0, | |
| 528 VEX_OPCODE_0F = 0x1, | |
| 529 VEX_OPCODE_0F_38 = 0x2, | |
| 530 VEX_OPCODE_0F_3A = 0x3 | |
| 0 | 531 }; |
| 532 | |
| 533 enum WhichOperand { | |
| 534 // input to locate_operand, and format code for relocations | |
| 304 | 535 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
| 0 | 536 disp32_operand = 1, // embedded 32-bit displacement or address |
| 537 call32_operand = 2, // embedded 32-bit self-relative displacement | |
| 304 | 538 #ifndef _LP64 |
| 0 | 539 _WhichOperand_limit = 3 |
| 304 | 540 #else |
| 541 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
| 542 _WhichOperand_limit = 4 | |
| 543 #endif | |
| 0 | 544 }; |
| 545 | |
| 304 | 546 |
| 547 | |
| 548 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
| 549 // of instructions are freely declared without the need for wrapping them an ifdef. | |
| 550 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
| 551 // In the .cpp file the implementations are wrapped so that they are dropped out | |
| 552 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
| 553 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
| 554 // | |
| 555 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
| 556 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
| 557 | |
| 558 private: | |
| 559 | |
| 560 | |
| 561 // 64bit prefixes | |
| 562 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
| 563 int prefixq_and_encode(int reg_enc); | |
| 564 | |
| 565 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
| 566 int prefixq_and_encode(int dst_enc, int src_enc); | |
| 567 | |
| 568 void prefix(Register reg); | |
| 569 void prefix(Address adr); | |
| 570 void prefixq(Address adr); | |
| 571 | |
| 572 void prefix(Address adr, Register reg, bool byteinst = false); | |
| 4759 | 573 void prefix(Address adr, XMMRegister reg); |
| 304 | 574 void prefixq(Address adr, Register reg); |
| 4759 | 575 void prefixq(Address adr, XMMRegister reg); |
| 304 | 576 |
| 577 void prefetch_prefix(Address src); | |
| 578 | |
| 4759 | 579 void rex_prefix(Address adr, XMMRegister xreg, |
| 580 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 581 int rex_prefix_and_encode(int dst_enc, int src_enc, | |
| 582 VexSimdPrefix pre, VexOpcode opc, bool rex_w); | |
| 583 | |
| 584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, | |
| 585 int nds_enc, VexSimdPrefix pre, VexOpcode opc, | |
| 586 bool vector256); | |
| 587 | |
| 588 void vex_prefix(Address adr, int nds_enc, int xreg_enc, | |
| 589 VexSimdPrefix pre, VexOpcode opc, | |
| 590 bool vex_w, bool vector256); | |
| 591 | |
| 592 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, | |
| 593 VexSimdPrefix pre, VexOpcode opc, | |
| 594 bool vex_w, bool vector256); | |
| 595 | |
| 596 | |
| 597 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, | |
| 598 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 599 bool rex_w = false, bool vector256 = false); | |
| 600 | |
| 601 void simd_prefix(XMMRegister dst, Address src, | |
| 602 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 603 simd_prefix(dst, xnoreg, src, pre, opc); | |
| 604 } | |
| 605 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { | |
| 606 simd_prefix(src, dst, pre); | |
| 607 } | |
| 608 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, | |
| 609 VexSimdPrefix pre) { | |
| 610 bool rex_w = true; | |
| 611 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); | |
| 612 } | |
| 613 | |
| 614 | |
| 615 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, | |
| 616 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, | |
| 617 bool rex_w = false, bool vector256 = false); | |
| 618 | |
| 619 int simd_prefix_and_encode(XMMRegister dst, XMMRegister src, | |
| 620 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 621 return simd_prefix_and_encode(dst, xnoreg, src, pre, opc); | |
| 622 } | |
| 623 | |
| 624 // Move/convert 32-bit integer value. | |
| 625 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, | |
| 626 VexSimdPrefix pre) { | |
| 627 // It is OK to cast from Register to XMMRegister to pass argument here | |
| 628 // since only encoding is used in simd_prefix_and_encode() and number of | |
| 629 // Gen and Xmm registers are the same. | |
| 630 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); | |
| 631 } | |
| 632 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 633 return simd_prefix_and_encode(dst, xnoreg, src, pre); | |
| 634 } | |
| 635 int simd_prefix_and_encode(Register dst, XMMRegister src, | |
| 636 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 637 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); | |
| 638 } | |
| 639 | |
| 640 // Move/convert 64-bit integer value. | |
| 641 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, | |
| 642 VexSimdPrefix pre) { | |
| 643 bool rex_w = true; | |
| 644 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); | |
| 645 } | |
| 646 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { | |
| 647 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); | |
| 648 } | |
| 649 int simd_prefix_and_encode_q(Register dst, XMMRegister src, | |
| 650 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { | |
| 651 bool rex_w = true; | |
| 652 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); | |
| 653 } | |
| 654 | |
| 304 | 655 // Helper functions for groups of instructions |
| 656 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
| 657 | |
| 658 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
| 659 // only 32bit?? | |
| 660 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
| 661 void emit_arith(int op1, int op2, Register dst, Register src); | |
| 662 | |
| 663 void emit_operand(Register reg, | |
| 664 Register base, Register index, Address::ScaleFactor scale, | |
| 665 int disp, | |
| 666 RelocationHolder const& rspec, | |
| 667 int rip_relative_correction = 0); | |
| 668 | |
| 669 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
| 670 | |
| 671 // operands that only take the original 32bit registers | |
| 672 void emit_operand32(Register reg, Address adr); | |
| 673 | |
| 674 void emit_operand(XMMRegister reg, | |
| 675 Register base, Register index, Address::ScaleFactor scale, | |
| 676 int disp, | |
| 677 RelocationHolder const& rspec); | |
| 678 | |
| 679 void emit_operand(XMMRegister reg, Address adr); | |
| 680 | |
| 681 void emit_operand(MMXRegister reg, Address adr); | |
| 682 | |
| 683 // workaround gcc (3.2.1-7) bug | |
| 684 void emit_operand(Address adr, MMXRegister reg); | |
| 685 | |
| 686 | |
| 687 // Immediate-to-memory forms | |
| 688 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
| 689 | |
| 690 void emit_farith(int b1, int b2, int i); | |
| 691 | |
| 692 | |
| 693 protected: | |
| 694 #ifdef ASSERT | |
| 695 void check_relocation(RelocationHolder const& rspec, int format); | |
| 696 #endif | |
| 697 | |
| 698 inline void emit_long64(jlong x); | |
| 699 | |
| 700 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
| 701 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
| 702 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
| 703 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
| 704 | |
| 705 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
| 706 | |
| 707 // These are all easily abused and hence protected | |
| 708 | |
| 709 // 32BIT ONLY SECTION | |
| 710 #ifndef _LP64 | |
| 711 // Make these disappear in 64bit mode since they would never be correct | |
| 712 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 713 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 714 | |
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715 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 304 | 716 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
| 717 | |
| 718 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
| 719 #else | |
| 720 // 64BIT ONLY SECTION | |
| 721 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
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722 |
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723 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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724 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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725 |
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726 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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727 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
| 304 | 728 #endif // _LP64 |
| 729 | |
| 730 // These are unique in that we are ensured by the caller that the 32bit | |
| 731 // relative in these instructions will always be able to reach the potentially | |
| 732 // 64bit address described by entry. Since they can take a 64bit address they | |
| 733 // don't have the 32 suffix like the other instructions in this class. | |
| 734 | |
| 735 void call_literal(address entry, RelocationHolder const& rspec); | |
| 736 void jmp_literal(address entry, RelocationHolder const& rspec); | |
| 737 | |
| 738 // Avoid using directly section | |
| 739 // Instructions in this section are actually usable by anyone without danger | |
| 740 // of failure but have performance issues that are addressed my enhanced | |
| 741 // instructions which will do the proper thing base on the particular cpu. | |
| 742 // We protect them because we don't trust you... | |
| 743 | |
| 744 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
| 745 // could cause a partial flag stall since they don't set CF flag. | |
| 746 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
| 747 // which call inc() & dec() or add() & sub() in accordance with | |
| 748 // the product flag UseIncDec value. | |
| 749 | |
| 750 void decl(Register dst); | |
| 751 void decl(Address dst); | |
| 752 void decq(Register dst); | |
| 753 void decq(Address dst); | |
| 754 | |
| 755 void incl(Register dst); | |
| 756 void incl(Address dst); | |
| 757 void incq(Register dst); | |
| 758 void incq(Address dst); | |
| 759 | |
| 760 // New cpus require use of movsd and movss to avoid partial register stall | |
| 761 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 762 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 763 | |
| 764 // Move Scalar Single-Precision Floating-Point Values | |
| 765 void movss(XMMRegister dst, Address src); | |
| 766 void movss(XMMRegister dst, XMMRegister src); | |
| 767 void movss(Address dst, XMMRegister src); | |
| 768 | |
| 769 // Move Scalar Double-Precision Floating-Point Values | |
| 770 void movsd(XMMRegister dst, Address src); | |
| 771 void movsd(XMMRegister dst, XMMRegister src); | |
| 772 void movsd(Address dst, XMMRegister src); | |
| 773 void movlpd(XMMRegister dst, Address src); | |
| 774 | |
| 775 // New cpus require use of movaps and movapd to avoid partial register stall | |
| 776 // when moving between registers. | |
| 777 void movaps(XMMRegister dst, XMMRegister src); | |
| 778 void movapd(XMMRegister dst, XMMRegister src); | |
| 779 | |
| 780 // End avoid using directly | |
| 781 | |
| 782 | |
| 783 // Instruction prefixes | |
| 784 void prefix(Prefix p); | |
| 785 | |
| 0 | 786 public: |
| 787 | |
| 788 // Creation | |
| 789 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
| 790 | |
| 791 // Decoding | |
| 792 static address locate_operand(address inst, WhichOperand which); | |
| 793 static address locate_next_instruction(address inst); | |
| 794 | |
| 304 | 795 // Utilities |
|
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796 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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797 |
| 304 | 798 // Generic instructions |
| 799 // Does 32bit or 64bit as needed for the platform. In some sense these | |
| 800 // belong in macro assembler but there is no need for both varieties to exist | |
| 801 | |
| 802 void lea(Register dst, Address src); | |
| 803 | |
| 804 void mov(Register dst, Register src); | |
| 805 | |
| 806 void pusha(); | |
| 807 void popa(); | |
| 808 | |
| 809 void pushf(); | |
| 810 void popf(); | |
| 811 | |
| 812 void push(int32_t imm32); | |
| 813 | |
| 814 void push(Register src); | |
| 815 | |
| 816 void pop(Register dst); | |
| 817 | |
| 818 // These are dummies to prevent surprise implicit conversions to Register | |
| 819 void push(void* v); | |
| 820 void pop(void* v); | |
| 821 | |
| 822 // These do register sized moves/scans | |
| 823 void rep_mov(); | |
| 824 void rep_set(); | |
| 825 void repne_scan(); | |
| 826 #ifdef _LP64 | |
| 827 void repne_scanl(); | |
| 828 #endif | |
| 829 | |
| 830 // Vanilla instructions in lexical order | |
| 831 | |
|
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832 void adcl(Address dst, int32_t imm32); |
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833 void adcl(Address dst, Register src); |
| 304 | 834 void adcl(Register dst, int32_t imm32); |
| 0 | 835 void adcl(Register dst, Address src); |
| 836 void adcl(Register dst, Register src); | |
| 837 | |
| 304 | 838 void adcq(Register dst, int32_t imm32); |
| 839 void adcq(Register dst, Address src); | |
| 840 void adcq(Register dst, Register src); | |
| 841 | |
| 842 void addl(Address dst, int32_t imm32); | |
| 0 | 843 void addl(Address dst, Register src); |
| 304 | 844 void addl(Register dst, int32_t imm32); |
| 0 | 845 void addl(Register dst, Address src); |
| 846 void addl(Register dst, Register src); | |
| 847 | |
| 304 | 848 void addq(Address dst, int32_t imm32); |
| 849 void addq(Address dst, Register src); | |
| 850 void addq(Register dst, int32_t imm32); | |
| 851 void addq(Register dst, Address src); | |
| 852 void addq(Register dst, Register src); | |
| 853 | |
| 0 | 854 void addr_nop_4(); |
| 855 void addr_nop_5(); | |
| 856 void addr_nop_7(); | |
| 857 void addr_nop_8(); | |
| 858 | |
| 304 | 859 // Add Scalar Double-Precision Floating-Point Values |
| 860 void addsd(XMMRegister dst, Address src); | |
| 861 void addsd(XMMRegister dst, XMMRegister src); | |
| 862 | |
| 863 // Add Scalar Single-Precision Floating-Point Values | |
| 864 void addss(XMMRegister dst, Address src); | |
| 865 void addss(XMMRegister dst, XMMRegister src); | |
| 866 | |
| 4759 | 867 void andl(Address dst, int32_t imm32); |
| 304 | 868 void andl(Register dst, int32_t imm32); |
| 869 void andl(Register dst, Address src); | |
| 870 void andl(Register dst, Register src); | |
| 871 | |
| 3783 | 872 void andq(Address dst, int32_t imm32); |
| 304 | 873 void andq(Register dst, int32_t imm32); |
| 874 void andq(Register dst, Address src); | |
| 875 void andq(Register dst, Register src); | |
| 876 | |
| 877 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values | |
| 878 void andpd(XMMRegister dst, XMMRegister src); | |
| 879 | |
| 4759 | 880 // Bitwise Logical AND of Packed Single-Precision Floating-Point Values |
| 881 void andps(XMMRegister dst, XMMRegister src); | |
| 882 | |
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883 void bsfl(Register dst, Register src); |
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884 void bsrl(Register dst, Register src); |
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885 |
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886 #ifdef _LP64 |
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887 void bsfq(Register dst, Register src); |
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888 void bsrq(Register dst, Register src); |
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889 #endif |
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|
890 |
| 304 | 891 void bswapl(Register reg); |
| 892 | |
| 893 void bswapq(Register reg); | |
| 894 | |
| 0 | 895 void call(Label& L, relocInfo::relocType rtype); |
| 896 void call(Register reg); // push pc; pc <- reg | |
| 897 void call(Address adr); // push pc; pc <- adr | |
| 898 | |
| 304 | 899 void cdql(); |
| 900 | |
| 901 void cdqq(); | |
| 902 | |
| 903 void cld() { emit_byte(0xfc); } | |
| 904 | |
| 905 void clflush(Address adr); | |
| 906 | |
| 907 void cmovl(Condition cc, Register dst, Register src); | |
| 908 void cmovl(Condition cc, Register dst, Address src); | |
| 909 | |
| 910 void cmovq(Condition cc, Register dst, Register src); | |
| 911 void cmovq(Condition cc, Register dst, Address src); | |
| 912 | |
| 913 | |
| 914 void cmpb(Address dst, int imm8); | |
| 915 | |
| 916 void cmpl(Address dst, int32_t imm32); | |
| 917 | |
| 918 void cmpl(Register dst, int32_t imm32); | |
| 919 void cmpl(Register dst, Register src); | |
| 920 void cmpl(Register dst, Address src); | |
| 921 | |
| 922 void cmpq(Address dst, int32_t imm32); | |
| 923 void cmpq(Address dst, Register src); | |
| 924 | |
| 925 void cmpq(Register dst, int32_t imm32); | |
| 926 void cmpq(Register dst, Register src); | |
| 927 void cmpq(Register dst, Address src); | |
| 928 | |
| 929 // these are dummies used to catch attempting to convert NULL to Register | |
| 930 void cmpl(Register dst, void* junk); // dummy | |
| 931 void cmpq(Register dst, void* junk); // dummy | |
| 932 | |
| 933 void cmpw(Address dst, int imm16); | |
| 934 | |
| 935 void cmpxchg8 (Address adr); | |
| 936 | |
| 937 void cmpxchgl(Register reg, Address adr); | |
| 938 | |
| 939 void cmpxchgq(Register reg, Address adr); | |
| 940 | |
| 941 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 942 void comisd(XMMRegister dst, Address src); | |
| 4759 | 943 void comisd(XMMRegister dst, XMMRegister src); |
| 304 | 944 |
| 945 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
| 946 void comiss(XMMRegister dst, Address src); | |
| 4759 | 947 void comiss(XMMRegister dst, XMMRegister src); |
| 304 | 948 |
| 949 // Identify processor type and features | |
| 950 void cpuid() { | |
| 951 emit_byte(0x0F); | |
| 952 emit_byte(0xA2); | |
| 953 } | |
| 954 | |
| 955 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
| 956 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
| 4759 | 957 void cvtsd2ss(XMMRegister dst, Address src); |
| 304 | 958 |
| 959 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
| 960 void cvtsi2sdl(XMMRegister dst, Register src); | |
| 4759 | 961 void cvtsi2sdl(XMMRegister dst, Address src); |
| 304 | 962 void cvtsi2sdq(XMMRegister dst, Register src); |
| 4759 | 963 void cvtsi2sdq(XMMRegister dst, Address src); |
| 304 | 964 |
| 965 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
| 966 void cvtsi2ssl(XMMRegister dst, Register src); | |
| 4759 | 967 void cvtsi2ssl(XMMRegister dst, Address src); |
| 304 | 968 void cvtsi2ssq(XMMRegister dst, Register src); |
| 4759 | 969 void cvtsi2ssq(XMMRegister dst, Address src); |
| 304 | 970 |
| 971 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
| 972 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
| 973 | |
| 974 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
| 975 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
| 976 | |
| 977 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
| 978 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
| 4759 | 979 void cvtss2sd(XMMRegister dst, Address src); |
| 304 | 980 |
| 981 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
| 982 void cvttsd2sil(Register dst, Address src); | |
| 983 void cvttsd2sil(Register dst, XMMRegister src); | |
| 984 void cvttsd2siq(Register dst, XMMRegister src); | |
| 985 | |
| 986 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
| 987 void cvttss2sil(Register dst, XMMRegister src); | |
| 988 void cvttss2siq(Register dst, XMMRegister src); | |
| 989 | |
| 990 // Divide Scalar Double-Precision Floating-Point Values | |
| 991 void divsd(XMMRegister dst, Address src); | |
| 992 void divsd(XMMRegister dst, XMMRegister src); | |
| 993 | |
| 994 // Divide Scalar Single-Precision Floating-Point Values | |
| 995 void divss(XMMRegister dst, Address src); | |
| 996 void divss(XMMRegister dst, XMMRegister src); | |
| 997 | |
| 998 void emms(); | |
| 999 | |
| 1000 void fabs(); | |
| 1001 | |
| 1002 void fadd(int i); | |
| 1003 | |
| 1004 void fadd_d(Address src); | |
| 1005 void fadd_s(Address src); | |
| 1006 | |
| 1007 // "Alternate" versions of x87 instructions place result down in FPU | |
| 1008 // stack instead of on TOS | |
| 1009 | |
| 1010 void fadda(int i); // "alternate" fadd | |
| 1011 void faddp(int i = 1); | |
| 1012 | |
| 1013 void fchs(); | |
| 1014 | |
| 1015 void fcom(int i); | |
| 1016 | |
| 1017 void fcomp(int i = 1); | |
| 1018 void fcomp_d(Address src); | |
| 1019 void fcomp_s(Address src); | |
| 1020 | |
| 1021 void fcompp(); | |
| 1022 | |
| 1023 void fcos(); | |
| 1024 | |
| 1025 void fdecstp(); | |
| 1026 | |
| 1027 void fdiv(int i); | |
| 1028 void fdiv_d(Address src); | |
| 1029 void fdivr_s(Address src); | |
| 1030 void fdiva(int i); // "alternate" fdiv | |
| 1031 void fdivp(int i = 1); | |
| 1032 | |
| 1033 void fdivr(int i); | |
| 1034 void fdivr_d(Address src); | |
| 1035 void fdiv_s(Address src); | |
| 1036 | |
| 1037 void fdivra(int i); // "alternate" reversed fdiv | |
| 1038 | |
| 1039 void fdivrp(int i = 1); | |
| 1040 | |
| 1041 void ffree(int i = 0); | |
| 1042 | |
| 1043 void fild_d(Address adr); | |
| 1044 void fild_s(Address adr); | |
| 1045 | |
| 1046 void fincstp(); | |
| 1047 | |
| 1048 void finit(); | |
| 1049 | |
| 1050 void fist_s (Address adr); | |
| 1051 void fistp_d(Address adr); | |
| 1052 void fistp_s(Address adr); | |
| 1053 | |
| 1054 void fld1(); | |
| 1055 | |
| 1056 void fld_d(Address adr); | |
| 1057 void fld_s(Address adr); | |
| 1058 void fld_s(int index); | |
| 1059 void fld_x(Address adr); // extended-precision (80-bit) format | |
| 1060 | |
| 1061 void fldcw(Address src); | |
| 1062 | |
| 1063 void fldenv(Address src); | |
| 1064 | |
| 1065 void fldlg2(); | |
| 1066 | |
| 1067 void fldln2(); | |
| 1068 | |
| 1069 void fldz(); | |
| 1070 | |
| 1071 void flog(); | |
| 1072 void flog10(); | |
| 1073 | |
| 1074 void fmul(int i); | |
| 1075 | |
| 1076 void fmul_d(Address src); | |
| 1077 void fmul_s(Address src); | |
| 1078 | |
| 1079 void fmula(int i); // "alternate" fmul | |
| 1080 | |
| 1081 void fmulp(int i = 1); | |
| 1082 | |
| 1083 void fnsave(Address dst); | |
| 1084 | |
| 1085 void fnstcw(Address src); | |
| 1086 | |
| 1087 void fnstsw_ax(); | |
| 1088 | |
| 1089 void fprem(); | |
| 1090 void fprem1(); | |
| 1091 | |
| 1092 void frstor(Address src); | |
| 1093 | |
| 1094 void fsin(); | |
| 1095 | |
| 1096 void fsqrt(); | |
| 1097 | |
| 1098 void fst_d(Address adr); | |
| 1099 void fst_s(Address adr); | |
| 1100 | |
| 1101 void fstp_d(Address adr); | |
| 1102 void fstp_d(int index); | |
| 1103 void fstp_s(Address adr); | |
| 1104 void fstp_x(Address adr); // extended-precision (80-bit) format | |
| 1105 | |
| 1106 void fsub(int i); | |
| 1107 void fsub_d(Address src); | |
| 1108 void fsub_s(Address src); | |
| 1109 | |
| 1110 void fsuba(int i); // "alternate" fsub | |
| 1111 | |
| 1112 void fsubp(int i = 1); | |
| 1113 | |
| 1114 void fsubr(int i); | |
| 1115 void fsubr_d(Address src); | |
| 1116 void fsubr_s(Address src); | |
| 1117 | |
| 1118 void fsubra(int i); // "alternate" reversed fsub | |
| 1119 | |
| 1120 void fsubrp(int i = 1); | |
| 1121 | |
| 1122 void ftan(); | |
| 1123 | |
| 1124 void ftst(); | |
| 1125 | |
| 1126 void fucomi(int i = 1); | |
| 1127 void fucomip(int i = 1); | |
| 1128 | |
| 1129 void fwait(); | |
| 1130 | |
| 1131 void fxch(int i = 1); | |
| 1132 | |
| 1133 void fxrstor(Address src); | |
| 1134 | |
| 1135 void fxsave(Address dst); | |
| 1136 | |
| 1137 void fyl2x(); | |
| 1138 | |
| 1139 void hlt(); | |
| 1140 | |
| 1141 void idivl(Register src); | |
| 1920 | 1142 void divl(Register src); // Unsigned division |
| 304 | 1143 |
| 1144 void idivq(Register src); | |
| 1145 | |
| 1146 void imull(Register dst, Register src); | |
| 1147 void imull(Register dst, Register src, int value); | |
| 1148 | |
| 1149 void imulq(Register dst, Register src); | |
| 1150 void imulq(Register dst, Register src, int value); | |
| 1151 | |
| 0 | 1152 |
| 1153 // jcc is the generic conditional branch generator to run- | |
| 1154 // time routines, jcc is used for branches to labels. jcc | |
| 1155 // takes a branch opcode (cc) and a label (L) and generates | |
| 1156 // either a backward branch or a forward branch and links it | |
| 1157 // to the label fixup chain. Usage: | |
| 1158 // | |
| 1159 // Label L; // unbound label | |
| 1160 // jcc(cc, L); // forward branch to unbound label | |
| 1161 // bind(L); // bind label to the current pc | |
| 1162 // jcc(cc, L); // backward branch to bound label | |
| 1163 // bind(L); // illegal: a label may be bound only once | |
| 1164 // | |
| 1165 // Note: The same Label can be used for forward and backward branches | |
| 1166 // but it may be bound only once. | |
| 1167 | |
| 3851 | 1168 void jcc(Condition cc, Label& L, bool maybe_short = true); |
| 0 | 1169 |
| 1170 // Conditional jump to a 8-bit offset to L. | |
| 1171 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1172 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1173 // will occur. | |
| 1174 void jccb(Condition cc, Label& L); | |
| 1175 | |
| 304 | 1176 void jmp(Address entry); // pc <- entry |
| 1177 | |
| 1178 // Label operations & relative jumps (PPUM Appendix D) | |
| 3851 | 1179 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
| 304 | 1180 |
| 1181 void jmp(Register entry); // pc <- entry | |
| 1182 | |
| 1183 // Unconditional 8-bit offset jump to L. | |
| 1184 // WARNING: be very careful using this for forward jumps. If the label is | |
| 1185 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 1186 // will occur. | |
| 1187 void jmpb(Label& L); | |
| 1188 | |
| 1189 void ldmxcsr( Address src ); | |
| 1190 | |
| 1191 void leal(Register dst, Address src); | |
| 1192 | |
| 1193 void leaq(Register dst, Address src); | |
| 1194 | |
| 1195 void lfence() { | |
| 1196 emit_byte(0x0F); | |
| 1197 emit_byte(0xAE); | |
| 1198 emit_byte(0xE8); | |
| 1199 } | |
| 1200 | |
| 1201 void lock(); | |
| 1202 | |
|
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1203 void lzcntl(Register dst, Register src); |
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1204 |
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1205 #ifdef _LP64 |
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1206 void lzcntq(Register dst, Register src); |
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1207 #endif |
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1208 |
| 304 | 1209 enum Membar_mask_bits { |
| 1210 StoreStore = 1 << 3, | |
| 1211 LoadStore = 1 << 2, | |
| 1212 StoreLoad = 1 << 1, | |
| 1213 LoadLoad = 1 << 0 | |
| 1214 }; | |
| 1215 | |
|
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1216 // Serializes memory and blows flags |
| 304 | 1217 void membar(Membar_mask_bits order_constraint) { |
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1218 if (os::is_MP()) { |
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1219 // We only have to handle StoreLoad |
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1220 if (order_constraint & StoreLoad) { |
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1221 // All usable chips support "locked" instructions which suffice |
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1222 // as barriers, and are much faster than the alternative of |
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1223 // using cpuid instruction. We use here a locked add [esp],0. |
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1224 // This is conveniently otherwise a no-op except for blowing |
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1225 // flags. |
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1226 // Any change to this code may need to revisit other places in |
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1227 // the code where this idiom is used, in particular the |
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1228 // orderAccess code. |
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1229 lock(); |
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1230 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1231 } |
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1232 } |
| 304 | 1233 } |
| 1234 | |
| 1235 void mfence(); | |
| 1236 | |
| 1237 // Moves | |
| 1238 | |
| 1239 void mov64(Register dst, int64_t imm64); | |
| 1240 | |
| 1241 void movb(Address dst, Register src); | |
| 1242 void movb(Address dst, int imm8); | |
| 1243 void movb(Register dst, Address src); | |
| 1244 | |
| 1245 void movdl(XMMRegister dst, Register src); | |
| 1246 void movdl(Register dst, XMMRegister src); | |
|
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1247 void movdl(XMMRegister dst, Address src); |
| 304 | 1248 |
| 1249 // Move Double Quadword | |
| 1250 void movdq(XMMRegister dst, Register src); | |
| 1251 void movdq(Register dst, XMMRegister src); | |
| 1252 | |
| 1253 // Move Aligned Double Quadword | |
| 1254 void movdqa(XMMRegister dst, XMMRegister src); | |
| 1255 | |
| 405 | 1256 // Move Unaligned Double Quadword |
| 1257 void movdqu(Address dst, XMMRegister src); | |
| 1258 void movdqu(XMMRegister dst, Address src); | |
| 1259 void movdqu(XMMRegister dst, XMMRegister src); | |
| 1260 | |
| 304 | 1261 void movl(Register dst, int32_t imm32); |
| 1262 void movl(Address dst, int32_t imm32); | |
| 1263 void movl(Register dst, Register src); | |
| 1264 void movl(Register dst, Address src); | |
| 1265 void movl(Address dst, Register src); | |
| 1266 | |
| 1267 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
| 1268 // by giving the compiler two choices it can't resolve | |
| 1269 | |
| 1270 void movl(Address dst, void* junk); | |
| 1271 void movl(Register dst, void* junk); | |
| 1272 | |
| 1273 #ifdef _LP64 | |
| 1274 void movq(Register dst, Register src); | |
| 1275 void movq(Register dst, Address src); | |
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1276 void movq(Address dst, Register src); |
| 304 | 1277 #endif |
| 1278 | |
| 1279 void movq(Address dst, MMXRegister src ); | |
| 1280 void movq(MMXRegister dst, Address src ); | |
| 1281 | |
| 1282 #ifdef _LP64 | |
| 1283 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
| 1284 // by giving the compiler two choices it can't resolve | |
| 1285 | |
| 1286 void movq(Address dst, void* dummy); | |
| 1287 void movq(Register dst, void* dummy); | |
| 1288 #endif | |
| 1289 | |
| 1290 // Move Quadword | |
| 1291 void movq(Address dst, XMMRegister src); | |
| 1292 void movq(XMMRegister dst, Address src); | |
| 1293 | |
| 1294 void movsbl(Register dst, Address src); | |
| 1295 void movsbl(Register dst, Register src); | |
| 1296 | |
| 1297 #ifdef _LP64 | |
| 624 | 1298 void movsbq(Register dst, Address src); |
| 1299 void movsbq(Register dst, Register src); | |
| 1300 | |
| 304 | 1301 // Move signed 32bit immediate to 64bit extending sign |
|
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1302 void movslq(Address dst, int32_t imm64); |
| 304 | 1303 void movslq(Register dst, int32_t imm64); |
| 1304 | |
| 1305 void movslq(Register dst, Address src); | |
| 1306 void movslq(Register dst, Register src); | |
| 1307 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
| 1308 #endif | |
| 1309 | |
| 1310 void movswl(Register dst, Address src); | |
| 1311 void movswl(Register dst, Register src); | |
| 1312 | |
| 624 | 1313 #ifdef _LP64 |
| 1314 void movswq(Register dst, Address src); | |
| 1315 void movswq(Register dst, Register src); | |
| 1316 #endif | |
| 1317 | |
| 304 | 1318 void movw(Address dst, int imm16); |
| 1319 void movw(Register dst, Address src); | |
| 1320 void movw(Address dst, Register src); | |
| 1321 | |
| 1322 void movzbl(Register dst, Address src); | |
| 1323 void movzbl(Register dst, Register src); | |
| 1324 | |
| 624 | 1325 #ifdef _LP64 |
| 1326 void movzbq(Register dst, Address src); | |
| 1327 void movzbq(Register dst, Register src); | |
| 1328 #endif | |
| 1329 | |
| 304 | 1330 void movzwl(Register dst, Address src); |
| 1331 void movzwl(Register dst, Register src); | |
| 1332 | |
| 624 | 1333 #ifdef _LP64 |
| 1334 void movzwq(Register dst, Address src); | |
| 1335 void movzwq(Register dst, Register src); | |
| 1336 #endif | |
| 1337 | |
| 304 | 1338 void mull(Address src); |
| 1339 void mull(Register src); | |
| 1340 | |
| 1341 // Multiply Scalar Double-Precision Floating-Point Values | |
| 1342 void mulsd(XMMRegister dst, Address src); | |
| 1343 void mulsd(XMMRegister dst, XMMRegister src); | |
| 1344 | |
| 1345 // Multiply Scalar Single-Precision Floating-Point Values | |
| 1346 void mulss(XMMRegister dst, Address src); | |
| 1347 void mulss(XMMRegister dst, XMMRegister src); | |
| 1348 | |
| 1349 void negl(Register dst); | |
| 1350 | |
| 1351 #ifdef _LP64 | |
| 1352 void negq(Register dst); | |
| 1353 #endif | |
| 1354 | |
| 1355 void nop(int i = 1); | |
| 1356 | |
| 1357 void notl(Register dst); | |
| 1358 | |
| 1359 #ifdef _LP64 | |
| 1360 void notq(Register dst); | |
| 1361 #endif | |
| 1362 | |
| 1363 void orl(Address dst, int32_t imm32); | |
| 1364 void orl(Register dst, int32_t imm32); | |
| 1365 void orl(Register dst, Address src); | |
| 1366 void orl(Register dst, Register src); | |
| 1367 | |
| 1368 void orq(Address dst, int32_t imm32); | |
| 1369 void orq(Register dst, int32_t imm32); | |
| 1370 void orq(Register dst, Address src); | |
| 1371 void orq(Register dst, Register src); | |
| 1372 | |
| 4759 | 1373 // Pack with unsigned saturation |
| 1374 void packuswb(XMMRegister dst, XMMRegister src); | |
| 1375 void packuswb(XMMRegister dst, Address src); | |
| 1376 | |
| 681 | 1377 // SSE4.2 string instructions |
| 1378 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
| 1379 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
| 1380 | |
| 4759 | 1381 // SSE4.1 packed move |
| 1382 void pmovzxbw(XMMRegister dst, XMMRegister src); | |
| 1383 void pmovzxbw(XMMRegister dst, Address src); | |
| 1384 | |
| 1060 | 1385 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1386 void popl(Address dst); |
| 1060 | 1387 #endif |
| 304 | 1388 |
| 1389 #ifdef _LP64 | |
| 1390 void popq(Address dst); | |
| 1391 #endif | |
| 1392 | |
|
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1393 void popcntl(Register dst, Address src); |
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1394 void popcntl(Register dst, Register src); |
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1395 |
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1396 #ifdef _LP64 |
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1397 void popcntq(Register dst, Address src); |
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1398 void popcntq(Register dst, Register src); |
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1399 #endif |
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1400 |
| 304 | 1401 // Prefetches (SSE, SSE2, 3DNOW only) |
| 1402 | |
| 1403 void prefetchnta(Address src); | |
| 1404 void prefetchr(Address src); | |
| 1405 void prefetcht0(Address src); | |
| 1406 void prefetcht1(Address src); | |
| 1407 void prefetcht2(Address src); | |
| 1408 void prefetchw(Address src); | |
| 1409 | |
| 2262 | 1410 // POR - Bitwise logical OR |
| 1411 void por(XMMRegister dst, XMMRegister src); | |
| 4759 | 1412 void por(XMMRegister dst, Address src); |
| 2262 | 1413 |
| 304 | 1414 // Shuffle Packed Doublewords |
| 1415 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
| 1416 void pshufd(XMMRegister dst, Address src, int mode); | |
| 1417 | |
| 1418 // Shuffle Packed Low Words | |
| 1419 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
| 1420 void pshuflw(XMMRegister dst, Address src, int mode); | |
| 1421 | |
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1422 // Shift Right by bits Logical Quadword Immediate |
| 304 | 1423 void psrlq(XMMRegister dst, int shift); |
| 1424 | |
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1425 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1426 void psrldq(XMMRegister dst, int shift); |
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1427 |
| 681 | 1428 // Logical Compare Double Quadword |
| 1429 void ptest(XMMRegister dst, XMMRegister src); | |
| 1430 void ptest(XMMRegister dst, Address src); | |
| 1431 | |
| 304 | 1432 // Interleave Low Bytes |
| 1433 void punpcklbw(XMMRegister dst, XMMRegister src); | |
| 4759 | 1434 void punpcklbw(XMMRegister dst, Address src); |
| 1435 | |
| 1436 // Interleave Low Doublewords | |
| 1437 void punpckldq(XMMRegister dst, XMMRegister src); | |
| 1438 void punpckldq(XMMRegister dst, Address src); | |
| 304 | 1439 |
| 1060 | 1440 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 1441 void pushl(Address src); |
| 1060 | 1442 #endif |
| 304 | 1443 |
| 1444 void pushq(Address src); | |
| 1445 | |
| 1446 // Xor Packed Byte Integer Values | |
| 1447 void pxor(XMMRegister dst, Address src); | |
| 1448 void pxor(XMMRegister dst, XMMRegister src); | |
| 1449 | |
| 1450 void rcll(Register dst, int imm8); | |
| 1451 | |
| 1452 void rclq(Register dst, int imm8); | |
| 1453 | |
| 1454 void ret(int imm16); | |
| 0 | 1455 |
| 1456 void sahf(); | |
| 1457 | |
| 304 | 1458 void sarl(Register dst, int imm8); |
| 1459 void sarl(Register dst); | |
| 1460 | |
| 1461 void sarq(Register dst, int imm8); | |
| 1462 void sarq(Register dst); | |
| 1463 | |
| 1464 void sbbl(Address dst, int32_t imm32); | |
| 1465 void sbbl(Register dst, int32_t imm32); | |
| 1466 void sbbl(Register dst, Address src); | |
| 1467 void sbbl(Register dst, Register src); | |
| 1468 | |
| 1469 void sbbq(Address dst, int32_t imm32); | |
| 1470 void sbbq(Register dst, int32_t imm32); | |
| 1471 void sbbq(Register dst, Address src); | |
| 1472 void sbbq(Register dst, Register src); | |
| 1473 | |
| 1474 void setb(Condition cc, Register dst); | |
| 1475 | |
| 1476 void shldl(Register dst, Register src); | |
| 1477 | |
| 1478 void shll(Register dst, int imm8); | |
| 1479 void shll(Register dst); | |
| 1480 | |
| 1481 void shlq(Register dst, int imm8); | |
| 1482 void shlq(Register dst); | |
| 1483 | |
| 1484 void shrdl(Register dst, Register src); | |
| 1485 | |
| 1486 void shrl(Register dst, int imm8); | |
| 1487 void shrl(Register dst); | |
| 1488 | |
| 1489 void shrq(Register dst, int imm8); | |
| 1490 void shrq(Register dst); | |
| 1491 | |
| 1492 void smovl(); // QQQ generic? | |
| 1493 | |
| 1494 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
| 1495 void sqrtsd(XMMRegister dst, Address src); | |
| 1496 void sqrtsd(XMMRegister dst, XMMRegister src); | |
| 1497 | |
| 2008 | 1498 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
| 1499 void sqrtss(XMMRegister dst, Address src); | |
| 1500 void sqrtss(XMMRegister dst, XMMRegister src); | |
| 1501 | |
| 304 | 1502 void std() { emit_byte(0xfd); } |
| 1503 | |
| 1504 void stmxcsr( Address dst ); | |
| 1505 | |
| 1506 void subl(Address dst, int32_t imm32); | |
| 1507 void subl(Address dst, Register src); | |
| 1508 void subl(Register dst, int32_t imm32); | |
| 1509 void subl(Register dst, Address src); | |
| 1510 void subl(Register dst, Register src); | |
| 1511 | |
| 1512 void subq(Address dst, int32_t imm32); | |
| 1513 void subq(Address dst, Register src); | |
| 1514 void subq(Register dst, int32_t imm32); | |
| 1515 void subq(Register dst, Address src); | |
| 1516 void subq(Register dst, Register src); | |
| 1517 | |
| 1518 | |
| 1519 // Subtract Scalar Double-Precision Floating-Point Values | |
| 1520 void subsd(XMMRegister dst, Address src); | |
| 0 | 1521 void subsd(XMMRegister dst, XMMRegister src); |
| 1522 | |
| 304 | 1523 // Subtract Scalar Single-Precision Floating-Point Values |
| 1524 void subss(XMMRegister dst, Address src); | |
| 1525 void subss(XMMRegister dst, XMMRegister src); | |
| 1526 | |
| 1527 void testb(Register dst, int imm8); | |
| 1528 | |
| 1529 void testl(Register dst, int32_t imm32); | |
| 1530 void testl(Register dst, Register src); | |
| 1531 void testl(Register dst, Address src); | |
| 1532 | |
| 1533 void testq(Register dst, int32_t imm32); | |
| 1534 void testq(Register dst, Register src); | |
| 1535 | |
| 1536 | |
| 1537 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
| 1538 void ucomisd(XMMRegister dst, Address src); | |
| 0 | 1539 void ucomisd(XMMRegister dst, XMMRegister src); |
| 1540 | |
| 304 | 1541 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
| 1542 void ucomiss(XMMRegister dst, Address src); | |
| 1543 void ucomiss(XMMRegister dst, XMMRegister src); | |
| 1544 | |
| 1545 void xaddl(Address dst, Register src); | |
| 1546 | |
| 1547 void xaddq(Address dst, Register src); | |
| 1548 | |
| 1549 void xchgl(Register reg, Address adr); | |
| 1550 void xchgl(Register dst, Register src); | |
| 1551 | |
| 1552 void xchgq(Register reg, Address adr); | |
| 1553 void xchgq(Register dst, Register src); | |
| 1554 | |
| 4759 | 1555 // Get Value of Extended Control Register |
| 1556 void xgetbv() { | |
| 1557 emit_byte(0x0F); | |
| 1558 emit_byte(0x01); | |
| 1559 emit_byte(0xD0); | |
| 1560 } | |
| 1561 | |
| 304 | 1562 void xorl(Register dst, int32_t imm32); |
| 1563 void xorl(Register dst, Address src); | |
| 1564 void xorl(Register dst, Register src); | |
| 1565 | |
| 1566 void xorq(Register dst, Address src); | |
| 1567 void xorq(Register dst, Register src); | |
| 1568 | |
| 1569 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
| 1570 void xorpd(XMMRegister dst, XMMRegister src); | |
| 1571 | |
| 1572 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
| 0 | 1573 void xorps(XMMRegister dst, XMMRegister src); |
| 304 | 1574 |
| 1575 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
| 4759 | 1576 |
| 1577 protected: | |
| 1578 // Next instructions require address alignment 16 bytes SSE mode. | |
| 1579 // They should be called only from corresponding MacroAssembler instructions. | |
| 1580 void andpd(XMMRegister dst, Address src); | |
| 1581 void andps(XMMRegister dst, Address src); | |
| 1582 void xorpd(XMMRegister dst, Address src); | |
| 1583 void xorps(XMMRegister dst, Address src); | |
| 1584 | |
| 0 | 1585 }; |
| 1586 | |
| 1587 | |
| 1588 // MacroAssembler extends Assembler by frequently used macros. | |
| 1589 // | |
| 1590 // Instructions for which a 'better' code sequence exists depending | |
| 1591 // on arguments should also go in here. | |
| 1592 | |
| 1593 class MacroAssembler: public Assembler { | |
|
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1594 friend class LIR_Assembler; |
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1595 friend class Runtime1; // as_Address() |
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1596 |
| 0 | 1597 protected: |
| 1598 | |
| 1599 Address as_Address(AddressLiteral adr); | |
| 1600 Address as_Address(ArrayAddress adr); | |
| 1601 | |
| 1602 // Support for VM calls | |
| 1603 // | |
| 1604 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
| 1605 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
| 1606 // additional registers when doing a VM call). | |
| 1607 #ifdef CC_INTERP | |
| 1608 // c++ interpreter never wants to use interp_masm version of call_VM | |
| 1609 #define VIRTUAL | |
| 1610 #else | |
| 1611 #define VIRTUAL virtual | |
| 1612 #endif | |
| 1613 | |
| 1614 VIRTUAL void call_VM_leaf_base( | |
| 1615 address entry_point, // the entry point | |
| 1616 int number_of_arguments // the number of arguments to pop after the call | |
| 1617 ); | |
| 1618 | |
| 1619 // This is the base routine called by the different versions of call_VM. The interpreter | |
| 1620 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
| 1621 // additional registers when doing a VM call). | |
| 1622 // | |
| 1623 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
| 1624 // returns the register which contains the thread upon return. If a thread register has been | |
| 1625 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
| 1626 // (noreg) than rsp will be used instead. | |
| 1627 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
| 1628 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
| 1629 Register java_thread, // the thread if computed before ; use noreg otherwise | |
| 1630 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
| 1631 address entry_point, // the entry point | |
| 1632 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
| 1633 bool check_exceptions // whether to check for pending exceptions after return | |
| 1634 ); | |
| 1635 | |
| 1636 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
| 1637 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
| 1638 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
| 1639 virtual void check_and_handle_popframe(Register java_thread); | |
| 1640 virtual void check_and_handle_earlyret(Register java_thread); | |
| 1641 | |
| 1642 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
| 1643 | |
| 1644 // helpers for FPU flag access | |
| 1645 // tmp is a temporary register, if none is available use noreg | |
| 1646 void save_rax (Register tmp); | |
| 1647 void restore_rax(Register tmp); | |
| 1648 | |
| 1649 public: | |
| 1650 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
| 1651 | |
| 1652 // Support for NULL-checks | |
| 1653 // | |
| 1654 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
| 1655 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
| 1656 // offset. No explicit code generation is needed if the offset is within a certain | |
| 1657 // range (0 <= offset <= page_size). | |
| 1658 | |
| 1659 void null_check(Register reg, int offset = -1); | |
|
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1660 static bool needs_explicit_null_check(intptr_t offset); |
| 0 | 1661 |
| 1662 // Required platform-specific helpers for Label::patch_instructions. | |
| 1663 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
| 1664 void pd_patch_instruction(address branch, address target); | |
| 1665 #ifndef PRODUCT | |
| 1666 static void pd_print_patched_instruction(address branch); | |
| 1667 #endif | |
| 1668 | |
| 1669 // The following 4 methods return the offset of the appropriate move instruction | |
| 1670 | |
|
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1671 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
| 0 | 1672 int load_unsigned_byte(Register dst, Address src); |
|
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1673 int load_unsigned_short(Register dst, Address src); |
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1674 |
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1675 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
| 0 | 1676 int load_signed_byte(Register dst, Address src); |
|
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1677 int load_signed_short(Register dst, Address src); |
| 0 | 1678 |
| 1679 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
| 1680 void extend_sign(Register hi, Register lo); | |
| 1681 | |
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1682 // Load and store values by size and signed-ness |
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1683 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
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1684 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
|
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1685 |
| 0 | 1686 // Support for inc/dec with optimal instruction selection depending on value |
| 304 | 1687 |
| 1688 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
| 1689 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
| 1690 | |
| 1691 void decrementl(Address dst, int value = 1); | |
| 1692 void decrementl(Register reg, int value = 1); | |
| 1693 | |
| 1694 void decrementq(Register reg, int value = 1); | |
| 1695 void decrementq(Address dst, int value = 1); | |
| 1696 | |
| 1697 void incrementl(Address dst, int value = 1); | |
| 1698 void incrementl(Register reg, int value = 1); | |
| 1699 | |
| 1700 void incrementq(Register reg, int value = 1); | |
| 1701 void incrementq(Address dst, int value = 1); | |
| 1702 | |
| 0 | 1703 |
| 1704 // Support optimal SSE move instructions. | |
| 1705 void movflt(XMMRegister dst, XMMRegister src) { | |
| 1706 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
| 1707 else { movss (dst, src); return; } | |
| 1708 } | |
| 1709 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
| 1710 void movflt(XMMRegister dst, AddressLiteral src); | |
| 1711 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
| 1712 | |
| 1713 void movdbl(XMMRegister dst, XMMRegister src) { | |
| 1714 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
| 1715 else { movsd (dst, src); return; } | |
| 1716 } | |
| 1717 | |
| 1718 void movdbl(XMMRegister dst, AddressLiteral src); | |
| 1719 | |
| 1720 void movdbl(XMMRegister dst, Address src) { | |
| 1721 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
| 1722 else { movlpd(dst, src); return; } | |
| 1723 } | |
| 1724 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
| 1725 | |
| 304 | 1726 void incrementl(AddressLiteral dst); |
| 1727 void incrementl(ArrayAddress dst); | |
| 0 | 1728 |
| 1729 // Alignment | |
| 1730 void align(int modulus); | |
| 1731 | |
| 1732 // Misc | |
| 1733 void fat_nop(); // 5 byte nop | |
| 1734 | |
| 1735 // Stack frame creation/removal | |
| 1736 void enter(); | |
| 1737 void leave(); | |
| 1738 | |
| 1739 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
| 1740 // The pointer will be loaded into the thread register. | |
| 1741 void get_thread(Register thread); | |
| 1742 | |
| 362 | 1743 |
| 0 | 1744 // Support for VM calls |
| 1745 // | |
| 1746 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
| 1747 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
| 1748 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
| 1749 | |
| 304 | 1750 |
| 1751 void call_VM(Register oop_result, | |
| 1752 address entry_point, | |
| 1753 bool check_exceptions = true); | |
| 1754 void call_VM(Register oop_result, | |
| 1755 address entry_point, | |
| 1756 Register arg_1, | |
| 1757 bool check_exceptions = true); | |
| 1758 void call_VM(Register oop_result, | |
| 1759 address entry_point, | |
| 1760 Register arg_1, Register arg_2, | |
| 1761 bool check_exceptions = true); | |
| 1762 void call_VM(Register oop_result, | |
| 1763 address entry_point, | |
| 1764 Register arg_1, Register arg_2, Register arg_3, | |
| 1765 bool check_exceptions = true); | |
| 1766 | |
| 1767 // Overloadings with last_Java_sp | |
| 1768 void call_VM(Register oop_result, | |
| 1769 Register last_java_sp, | |
| 1770 address entry_point, | |
| 1771 int number_of_arguments = 0, | |
| 1772 bool check_exceptions = true); | |
| 1773 void call_VM(Register oop_result, | |
| 1774 Register last_java_sp, | |
| 1775 address entry_point, | |
| 1776 Register arg_1, bool | |
| 1777 check_exceptions = true); | |
| 1778 void call_VM(Register oop_result, | |
| 1779 Register last_java_sp, | |
| 1780 address entry_point, | |
| 1781 Register arg_1, Register arg_2, | |
| 1782 bool check_exceptions = true); | |
| 1783 void call_VM(Register oop_result, | |
| 1784 Register last_java_sp, | |
| 1785 address entry_point, | |
| 1786 Register arg_1, Register arg_2, Register arg_3, | |
| 1787 bool check_exceptions = true); | |
| 1788 | |
|
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1789 // These always tightly bind to MacroAssembler::call_VM_base |
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1790 // bypassing the virtual implementation |
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1791 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
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1792 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
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1793 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
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1794 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
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1795 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
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1796 |
| 304 | 1797 void call_VM_leaf(address entry_point, |
| 1798 int number_of_arguments = 0); | |
| 1799 void call_VM_leaf(address entry_point, | |
| 1800 Register arg_1); | |
| 1801 void call_VM_leaf(address entry_point, | |
| 1802 Register arg_1, Register arg_2); | |
| 1803 void call_VM_leaf(address entry_point, | |
| 1804 Register arg_1, Register arg_2, Register arg_3); | |
| 0 | 1805 |
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1806 // These always tightly bind to MacroAssembler::call_VM_leaf_base |
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1807 // bypassing the virtual implementation |
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1808 void super_call_VM_leaf(address entry_point); |
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1809 void super_call_VM_leaf(address entry_point, Register arg_1); |
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1810 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
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1811 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
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1812 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
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1813 |
| 0 | 1814 // last Java Frame (fills frame anchor) |
| 304 | 1815 void set_last_Java_frame(Register thread, |
| 1816 Register last_java_sp, | |
| 1817 Register last_java_fp, | |
| 1818 address last_java_pc); | |
| 1819 | |
| 1820 // thread in the default location (r15_thread on 64bit) | |
| 1821 void set_last_Java_frame(Register last_java_sp, | |
| 1822 Register last_java_fp, | |
| 1823 address last_java_pc); | |
| 1824 | |
| 0 | 1825 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
| 1826 | |
| 304 | 1827 // thread in the default location (r15_thread on 64bit) |
| 1828 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
| 1829 | |
| 0 | 1830 // Stores |
| 1831 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
| 1832 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
| 1833 | |
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1834 #ifndef SERIALGC |
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1835 |
| 362 | 1836 void g1_write_barrier_pre(Register obj, |
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1837 Register pre_val, |
| 362 | 1838 Register thread, |
| 1839 Register tmp, | |
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1840 bool tosca_live, |
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1841 bool expand_call); |
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1842 |
| 362 | 1843 void g1_write_barrier_post(Register store_addr, |
| 1844 Register new_val, | |
| 1845 Register thread, | |
| 1846 Register tmp, | |
| 1847 Register tmp2); | |
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1848 |
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1849 #endif // SERIALGC |
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1850 |
| 0 | 1851 // split store_check(Register obj) to enhance instruction interleaving |
| 1852 void store_check_part_1(Register obj); | |
| 1853 void store_check_part_2(Register obj); | |
| 1854 | |
| 1855 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
| 1856 void c2bool(Register x); | |
| 1857 | |
| 1858 // C++ bool manipulation | |
| 1859 | |
| 1860 void movbool(Register dst, Address src); | |
| 1861 void movbool(Address dst, bool boolconst); | |
| 1862 void movbool(Address dst, Register src); | |
| 1863 void testbool(Register dst); | |
| 1864 | |
| 304 | 1865 // oop manipulations |
| 1866 void load_klass(Register dst, Register src); | |
| 1867 void store_klass(Register dst, Register src); | |
| 1868 | |
| 1846 | 1869 void load_heap_oop(Register dst, Address src); |
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1870 void load_heap_oop_not_null(Register dst, Address src); |
| 1846 | 1871 void store_heap_oop(Address dst, Register src); |
| 1872 | |
| 1873 // Used for storing NULL. All other oop constants should be | |
| 1874 // stored using routines that take a jobject. | |
| 1875 void store_heap_oop_null(Address dst); | |
| 1876 | |
| 304 | 1877 void load_prototype_header(Register dst, Register src); |
| 1878 | |
| 1879 #ifdef _LP64 | |
| 1880 void store_klass_gap(Register dst, Register src); | |
| 1881 | |
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1882 // This dummy is to prevent a call to store_heap_oop from |
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1883 // converting a zero (like NULL) into a Register by giving |
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1884 // the compiler two choices it can't resolve |
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1885 |
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1886 void store_heap_oop(Address dst, void* dummy); |
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1887 |
| 304 | 1888 void encode_heap_oop(Register r); |
| 1889 void decode_heap_oop(Register r); | |
| 1890 void encode_heap_oop_not_null(Register r); | |
| 1891 void decode_heap_oop_not_null(Register r); | |
| 1892 void encode_heap_oop_not_null(Register dst, Register src); | |
| 1893 void decode_heap_oop_not_null(Register dst, Register src); | |
| 1894 | |
| 1895 void set_narrow_oop(Register dst, jobject obj); | |
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1896 void set_narrow_oop(Address dst, jobject obj); |
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1897 void cmp_narrow_oop(Register dst, jobject obj); |
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1898 void cmp_narrow_oop(Address dst, jobject obj); |
| 304 | 1899 |
| 1900 // if heap base register is used - reinit it with the correct value | |
| 1901 void reinit_heapbase(); | |
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1902 |
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1903 DEBUG_ONLY(void verify_heapbase(const char* msg);) |
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1904 |
| 304 | 1905 #endif // _LP64 |
| 1906 | |
| 1907 // Int division/remainder for Java | |
| 0 | 1908 // (as idivl, but checks for special case as described in JVM spec.) |
| 1909 // returns idivl instruction offset for implicit exception handling | |
| 1910 int corrected_idivl(Register reg); | |
| 1911 | |
| 304 | 1912 // Long division/remainder for Java |
| 1913 // (as idivq, but checks for special case as described in JVM spec.) | |
| 1914 // returns idivq instruction offset for implicit exception handling | |
| 1915 int corrected_idivq(Register reg); | |
| 1916 | |
| 0 | 1917 void int3(); |
| 1918 | |
| 304 | 1919 // Long operation macros for a 32bit cpu |
| 0 | 1920 // Long negation for Java |
| 1921 void lneg(Register hi, Register lo); | |
| 1922 | |
| 1923 // Long multiplication for Java | |
| 304 | 1924 // (destroys contents of eax, ebx, ecx and edx) |
| 0 | 1925 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
| 1926 | |
| 1927 // Long shifts for Java | |
| 1928 // (semantics as described in JVM spec.) | |
| 1929 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
| 1930 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
| 1931 | |
| 1932 // Long compare for Java | |
| 1933 // (semantics as described in JVM spec.) | |
| 1934 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
| 1935 | |
| 304 | 1936 |
| 1937 // misc | |
| 1938 | |
| 1939 // Sign extension | |
| 1940 void sign_extend_short(Register reg); | |
| 1941 void sign_extend_byte(Register reg); | |
| 1942 | |
| 1943 // Division by power of 2, rounding towards 0 | |
| 1944 void division_with_shift(Register reg, int shift_value); | |
| 1945 | |
| 0 | 1946 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
| 1947 // | |
| 1948 // CF (corresponds to C0) if x < y | |
| 1949 // PF (corresponds to C2) if unordered | |
| 1950 // ZF (corresponds to C3) if x = y | |
| 1951 // | |
| 1952 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
| 1953 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
| 1954 void fcmp(Register tmp); | |
| 1955 // Variant of the above which allows y to be further down the stack | |
| 1956 // and which only pops x and y if specified. If pop_right is | |
| 1957 // specified then pop_left must also be specified. | |
| 1958 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
| 1959 | |
| 1960 // Floating-point comparison for Java | |
| 1961 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
| 1962 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
| 1963 // (semantics as described in JVM spec.) | |
| 1964 void fcmp2int(Register dst, bool unordered_is_less); | |
| 1965 // Variant of the above which allows y to be further down the stack | |
| 1966 // and which only pops x and y if specified. If pop_right is | |
| 1967 // specified then pop_left must also be specified. | |
| 1968 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
| 1969 | |
| 1970 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
| 1971 // tmp is a temporary register, if none is available use noreg | |
| 1972 void fremr(Register tmp); | |
| 1973 | |
| 1974 | |
| 1975 // same as fcmp2int, but using SSE2 | |
| 1976 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
| 1977 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
| 1978 | |
| 1979 // Inlined sin/cos generator for Java; must not use CPU instruction | |
| 1980 // directly on Intel as it does not have high enough precision | |
| 1981 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
| 1982 // number of FPU stack slots in use; all but the topmost will | |
| 1983 // require saving if a slow case is necessary. Assumes argument is | |
| 1984 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
| 1985 // this code. | |
| 1986 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
| 1987 | |
| 1988 // branch to L if FPU flag C2 is set/not set | |
| 1989 // tmp is a temporary register, if none is available use noreg | |
| 1990 void jC2 (Register tmp, Label& L); | |
| 1991 void jnC2(Register tmp, Label& L); | |
| 1992 | |
| 1993 // Pop ST (ffree & fincstp combined) | |
| 1994 void fpop(); | |
| 1995 | |
| 1996 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
| 1997 void push_fTOS(); | |
| 1998 | |
| 1999 // pops double TOS element from CPU stack and pushes on FPU stack | |
| 2000 void pop_fTOS(); | |
| 2001 | |
| 2002 void empty_FPU_stack(); | |
| 2003 | |
| 2004 void push_IU_state(); | |
| 2005 void pop_IU_state(); | |
| 2006 | |
| 2007 void push_FPU_state(); | |
| 2008 void pop_FPU_state(); | |
| 2009 | |
| 2010 void push_CPU_state(); | |
| 2011 void pop_CPU_state(); | |
| 2012 | |
| 2013 // Round up to a power of two | |
| 2014 void round_to(Register reg, int modulus); | |
| 2015 | |
| 2016 // Callee saved registers handling | |
| 2017 void push_callee_saved_registers(); | |
| 2018 void pop_callee_saved_registers(); | |
| 2019 | |
| 2020 // allocation | |
| 2021 void eden_allocate( | |
| 2022 Register obj, // result: pointer to object after successful allocation | |
| 2023 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
| 2024 int con_size_in_bytes, // object size in bytes if known at compile time | |
| 2025 Register t1, // temp register | |
| 2026 Label& slow_case // continuation point if fast allocation fails | |
| 2027 ); | |
| 2028 void tlab_allocate( | |
| 2029 Register obj, // result: pointer to object after successful allocation | |
| 2030 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
| 2031 int con_size_in_bytes, // object size in bytes if known at compile time | |
| 2032 Register t1, // temp register | |
| 2033 Register t2, // temp register | |
| 2034 Label& slow_case // continuation point if fast allocation fails | |
| 2035 ); | |
|
2100
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2036 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
|
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|
2037 void incr_allocated_bytes(Register thread, |
|
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2038 Register var_size_in_bytes, int con_size_in_bytes, |
|
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|
2039 Register t1 = noreg); |
| 0 | 2040 |
|
623
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2041 // interface method calling |
|
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2042 void lookup_interface_method(Register recv_klass, |
|
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2043 Register intf_klass, |
|
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2044 RegisterOrConstant itable_index, |
|
623
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2045 Register method_result, |
|
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2046 Register scan_temp, |
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2047 Label& no_such_interface); |
|
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2048 |
|
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2049 // Test sub_klass against super_klass, with fast and slow paths. |
|
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2050 |
|
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2051 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
|
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2052 // One of the three labels can be NULL, meaning take the fall-through. |
|
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2053 // If super_check_offset is -1, the value is loaded up from super_klass. |
|
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2054 // No registers are killed, except temp_reg. |
|
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2055 void check_klass_subtype_fast_path(Register sub_klass, |
|
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|
2056 Register super_klass, |
|
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|
2057 Register temp_reg, |
|
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|
2058 Label* L_success, |
|
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|
2059 Label* L_failure, |
|
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|
2060 Label* L_slow_path, |
|
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2061 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
|
644
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|
2062 |
|
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2063 // The rest of the type check; must be wired to a corresponding fast path. |
|
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2064 // It does not repeat the fast path logic, so don't use it standalone. |
|
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2065 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
|
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2066 // Updates the sub's secondary super cache as necessary. |
|
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2067 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
|
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2068 void check_klass_subtype_slow_path(Register sub_klass, |
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2069 Register super_klass, |
|
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|
2070 Register temp_reg, |
|
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|
2071 Register temp2_reg, |
|
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|
2072 Label* L_success, |
|
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2073 Label* L_failure, |
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|
2074 bool set_cond_codes = false); |
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|
2075 |
|
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2076 // Simplified, combined version, good for typical uses. |
|
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2077 // Falls through on failure. |
|
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|
2078 void check_klass_subtype(Register sub_klass, |
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|
2079 Register super_klass, |
|
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|
2080 Register temp_reg, |
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|
2081 Label& L_success); |
|
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|
2082 |
| 710 | 2083 // method handles (JSR 292) |
| 2084 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 2085 Register temp_reg, | |
| 2086 Label& wrong_method_type); | |
| 2087 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 2088 Register temp_reg); | |
| 2089 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
| 2090 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
| 2091 | |
| 2092 | |
| 0 | 2093 //---- |
| 2094 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
| 2095 | |
| 2096 // Debugging | |
| 304 | 2097 |
| 2098 // only if +VerifyOops | |
| 2099 void verify_oop(Register reg, const char* s = "broken oop"); | |
| 0 | 2100 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
| 2101 | |
| 304 | 2102 // only if +VerifyFPU |
| 2103 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
| 2104 | |
| 2105 // prints msg, dumps registers and stops execution | |
| 2106 void stop(const char* msg); | |
| 2107 | |
| 2108 // prints msg and continues | |
| 2109 void warn(const char* msg); | |
| 2110 | |
| 2111 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); | |
| 2112 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
| 2113 | |
| 0 | 2114 void os_breakpoint(); |
| 304 | 2115 |
| 0 | 2116 void untested() { stop("untested"); } |
| 304 | 2117 |
| 1846 | 2118 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
| 304 | 2119 |
| 0 | 2120 void should_not_reach_here() { stop("should not reach here"); } |
| 304 | 2121 |
| 0 | 2122 void print_CPU_state(); |
| 2123 | |
| 2124 // Stack overflow checking | |
| 2125 void bang_stack_with_offset(int offset) { | |
| 2126 // stack grows down, caller passes positive offset | |
| 2127 assert(offset > 0, "must bang with negative offset"); | |
| 2128 movl(Address(rsp, (-offset)), rax); | |
| 2129 } | |
| 2130 | |
| 2131 // Writes to stack successive pages until offset reached to check for | |
| 2132 // stack overflow + shadow pages. Also, clobbers tmp | |
| 2133 void bang_stack_size(Register size, Register tmp); | |
| 2134 | |
|
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2135 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
|
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2136 Register tmp, |
|
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2137 int offset); |
|
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2138 |
| 0 | 2139 // Support for serializing memory accesses between threads |
| 2140 void serialize_memory(Register thread, Register tmp); | |
| 2141 | |
| 2142 void verify_tlab(); | |
| 2143 | |
| 2144 // Biased locking support | |
| 2145 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
| 2146 // swap_reg must be rax, and is killed. | |
| 2147 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
| 2148 // be killed; if not supplied, push/pop will be used internally to | |
| 2149 // allocate a temporary (inefficient, avoid if possible). | |
| 2150 // Optional slow case is for implementations (interpreter and C1) which branch to | |
| 2151 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
| 2152 // Returns offset of first potentially-faulting instruction for null | |
| 2153 // check info (currently consumed only by C1). If | |
| 2154 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
| 2155 // the calling code has already passed any potential faults. | |
|
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|
2156 int biased_locking_enter(Register lock_reg, Register obj_reg, |
|
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|
2157 Register swap_reg, Register tmp_reg, |
| 0 | 2158 bool swap_reg_contains_mark, |
| 2159 Label& done, Label* slow_case = NULL, | |
| 2160 BiasedLockingCounters* counters = NULL); | |
| 2161 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
| 2162 | |
| 2163 | |
| 2164 Condition negate_condition(Condition cond); | |
| 2165 | |
| 2166 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
| 2167 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
| 2168 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
| 2169 // here in MacroAssembler. The major exception to this rule is call | |
| 2170 | |
| 2171 // Arithmetics | |
| 2172 | |
| 304 | 2173 |
| 2174 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
| 2175 void addptr(Address dst, Register src); | |
| 2176 | |
| 2177 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
| 2178 void addptr(Register dst, int32_t src); | |
| 2179 void addptr(Register dst, Register src); | |
|
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2180 void addptr(Register dst, RegisterOrConstant src) { |
|
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2181 if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
|
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2182 else addptr(dst, src.as_register()); |
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2183 } |
| 304 | 2184 |
| 2185 void andptr(Register dst, int32_t src); | |
| 2186 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
| 2187 | |
| 2188 void cmp8(AddressLiteral src1, int imm); | |
| 2189 | |
| 2190 // renamed to drag out the casting of address to int32_t/intptr_t | |
| 0 | 2191 void cmp32(Register src1, int32_t imm); |
| 2192 | |
| 2193 void cmp32(AddressLiteral src1, int32_t imm); | |
| 2194 // compare reg - mem, or reg - &mem | |
| 2195 void cmp32(Register src1, AddressLiteral src2); | |
| 2196 | |
| 2197 void cmp32(Register src1, Address src2); | |
| 2198 | |
| 304 | 2199 #ifndef _LP64 |
| 2200 void cmpoop(Address dst, jobject obj); | |
| 2201 void cmpoop(Register dst, jobject obj); | |
| 2202 #endif // _LP64 | |
| 2203 | |
| 0 | 2204 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
| 2205 void cmpptr(Address src1, AddressLiteral src2); | |
| 2206 | |
| 2207 void cmpptr(Register src1, AddressLiteral src2); | |
| 2208 | |
| 304 | 2209 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
| 2210 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2211 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2212 | |
| 2213 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2214 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
| 2215 | |
| 2216 // cmp64 to avoild hiding cmpq | |
| 2217 void cmp64(Register src1, AddressLiteral src); | |
| 2218 | |
| 2219 void cmpxchgptr(Register reg, Address adr); | |
| 2220 | |
| 2221 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
| 2222 | |
| 2223 | |
| 2224 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
| 2225 | |
| 2226 | |
| 2227 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
| 2228 | |
| 2229 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
| 2230 | |
| 2231 void shlptr(Register dst, int32_t shift); | |
| 2232 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
| 2233 | |
| 2234 void shrptr(Register dst, int32_t shift); | |
| 2235 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
| 2236 | |
| 2237 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
| 2238 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
| 2239 | |
| 2240 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
| 2241 | |
| 2242 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
| 2243 void subptr(Register dst, int32_t src); | |
| 2244 void subptr(Register dst, Register src); | |
|
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2245 void subptr(Register dst, RegisterOrConstant src) { |
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2246 if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
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2247 else subptr(dst, src.as_register()); |
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2248 } |
| 304 | 2249 |
| 2250 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
| 2251 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
| 2252 | |
| 2253 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
| 2254 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
| 2255 | |
| 2256 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
| 2257 | |
| 2258 | |
| 0 | 2259 |
| 2260 // Helper functions for statistics gathering. | |
| 2261 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
| 2262 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
| 2263 // Unconditional atomic increment. | |
| 2264 void atomic_incl(AddressLiteral counter_addr); | |
| 2265 | |
| 2266 void lea(Register dst, AddressLiteral adr); | |
| 2267 void lea(Address dst, AddressLiteral adr); | |
| 304 | 2268 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
| 2269 | |
| 2270 void leal32(Register dst, Address src) { leal(dst, src); } | |
| 2271 | |
|
2404
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2272 // Import other testl() methods from the parent class or else |
|
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2273 // they will be hidden by the following overriding declaration. |
|
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2274 using Assembler::testl; |
|
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2275 void testl(Register dst, AddressLiteral src); |
| 304 | 2276 |
| 2277 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2278 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2279 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
| 2280 | |
| 2281 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
| 2282 void testptr(Register src1, Register src2); | |
| 2283 | |
| 2284 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
| 2285 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
| 0 | 2286 |
| 2287 // Calls | |
| 2288 | |
| 2289 void call(Label& L, relocInfo::relocType rtype); | |
| 2290 void call(Register entry); | |
| 2291 | |
| 2292 // NOTE: this call tranfers to the effective address of entry NOT | |
| 2293 // the address contained by entry. This is because this is more natural | |
| 2294 // for jumps/calls. | |
| 2295 void call(AddressLiteral entry); | |
| 2296 | |
| 2297 // Jumps | |
| 2298 | |
| 2299 // NOTE: these jumps tranfer to the effective address of dst NOT | |
| 2300 // the address contained by dst. This is because this is more natural | |
| 2301 // for jumps/calls. | |
| 2302 void jump(AddressLiteral dst); | |
| 2303 void jump_cc(Condition cc, AddressLiteral dst); | |
| 2304 | |
| 2305 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 2306 // to be installed in the Address class. This jump will tranfers to the address | |
| 2307 // contained in the location described by entry (not the address of entry) | |
| 2308 void jump(ArrayAddress entry); | |
| 2309 | |
| 2310 // Floating | |
| 2311 | |
| 2312 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
| 2313 void andpd(XMMRegister dst, AddressLiteral src); | |
| 2314 | |
| 4759 | 2315 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } |
| 2316 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } | |
| 2317 void andps(XMMRegister dst, AddressLiteral src); | |
| 2318 | |
| 2319 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } | |
| 0 | 2320 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
| 2321 void comiss(XMMRegister dst, AddressLiteral src); | |
| 2322 | |
| 4759 | 2323 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } |
| 0 | 2324 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
| 2325 void comisd(XMMRegister dst, AddressLiteral src); | |
| 2326 | |
| 2008 | 2327 void fadd_s(Address src) { Assembler::fadd_s(src); } |
| 2328 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } | |
| 2329 | |
| 0 | 2330 void fldcw(Address src) { Assembler::fldcw(src); } |
| 2331 void fldcw(AddressLiteral src); | |
| 2332 | |
| 2333 void fld_s(int index) { Assembler::fld_s(index); } | |
| 2334 void fld_s(Address src) { Assembler::fld_s(src); } | |
| 2335 void fld_s(AddressLiteral src); | |
| 2336 | |
| 2337 void fld_d(Address src) { Assembler::fld_d(src); } | |
| 2338 void fld_d(AddressLiteral src); | |
| 2339 | |
| 2340 void fld_x(Address src) { Assembler::fld_x(src); } | |
| 2341 void fld_x(AddressLiteral src); | |
| 2342 | |
| 2008 | 2343 void fmul_s(Address src) { Assembler::fmul_s(src); } |
| 2344 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } | |
| 2345 | |
| 0 | 2346 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
| 2347 void ldmxcsr(AddressLiteral src); | |
| 2348 | |
| 304 | 2349 private: |
| 2350 // these are private because users should be doing movflt/movdbl | |
| 2351 | |
| 0 | 2352 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
| 2353 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
| 2354 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
| 2355 void movss(XMMRegister dst, AddressLiteral src); | |
| 2356 | |
| 4759 | 2357 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
| 304 | 2358 void movlpd(XMMRegister dst, AddressLiteral src); |
| 2359 | |
| 2360 public: | |
| 2361 | |
| 2008 | 2362 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
| 2363 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } | |
| 4759 | 2364 void addsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2365 |
| 2366 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } | |
| 2367 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } | |
| 4759 | 2368 void addss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2369 |
| 2370 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } | |
| 2371 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } | |
| 4759 | 2372 void divsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2373 |
| 2374 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } | |
| 2375 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } | |
| 4759 | 2376 void divss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2377 |
|
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2378 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
|
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2379 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
|
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|
2380 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
| 4759 | 2381 void movsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2382 |
| 2383 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } | |
| 2384 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } | |
| 4759 | 2385 void mulsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2386 |
| 2387 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } | |
| 2388 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } | |
| 4759 | 2389 void mulss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2390 |
| 2391 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } | |
| 2392 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } | |
| 4759 | 2393 void sqrtsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2394 |
| 2395 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } | |
| 2396 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } | |
| 4759 | 2397 void sqrtss(XMMRegister dst, AddressLiteral src); |
| 2008 | 2398 |
| 2399 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } | |
| 2400 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } | |
| 4759 | 2401 void subsd(XMMRegister dst, AddressLiteral src); |
| 2008 | 2402 |
| 2403 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } | |
| 2404 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } | |
| 4759 | 2405 void subss(XMMRegister dst, AddressLiteral src); |
| 0 | 2406 |
| 2407 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
| 4759 | 2408 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
| 0 | 2409 void ucomiss(XMMRegister dst, AddressLiteral src); |
| 2410 | |
| 2411 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
| 4759 | 2412 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
| 0 | 2413 void ucomisd(XMMRegister dst, AddressLiteral src); |
| 2414 | |
| 2415 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
| 2416 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
| 2417 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
| 2418 void xorpd(XMMRegister dst, AddressLiteral src); | |
| 2419 | |
| 2420 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
| 2421 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
| 2422 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
| 2423 void xorps(XMMRegister dst, AddressLiteral src); | |
| 2424 | |
| 2425 // Data | |
| 2426 | |
|
2415
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2427 void cmov32( Condition cc, Register dst, Address src); |
|
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|
2428 void cmov32( Condition cc, Register dst, Register src); |
|
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2429 |
|
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|
2430 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
|
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2431 |
|
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|
2432 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
|
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|
2433 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
| 304 | 2434 |
| 0 | 2435 void movoop(Register dst, jobject obj); |
| 2436 void movoop(Address dst, jobject obj); | |
| 2437 | |
| 2438 void movptr(ArrayAddress dst, Register src); | |
| 2439 // can this do an lea? | |
| 2440 void movptr(Register dst, ArrayAddress src); | |
| 2441 | |
| 304 | 2442 void movptr(Register dst, Address src); |
| 2443 | |
| 0 | 2444 void movptr(Register dst, AddressLiteral src); |
| 2445 | |
| 304 | 2446 void movptr(Register dst, intptr_t src); |
| 2447 void movptr(Register dst, Register src); | |
| 2448 void movptr(Address dst, intptr_t src); | |
| 2449 | |
| 2450 void movptr(Address dst, Register src); | |
| 2451 | |
|
3363
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|
2452 void movptr(Register dst, RegisterOrConstant src) { |
|
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|
2453 if (src.is_constant()) movptr(dst, src.as_constant()); |
|
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|
2454 else movptr(dst, src.as_register()); |
|
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|
2455 } |
|
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|
2456 |
| 304 | 2457 #ifdef _LP64 |
| 2458 // Generally the next two are only used for moving NULL | |
| 2459 // Although there are situations in initializing the mark word where | |
| 2460 // they could be used. They are dangerous. | |
| 2461 | |
| 2462 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
| 2463 // and we have ambiguous declarations. | |
| 2464 | |
| 2465 void movptr(Address dst, int32_t imm32); | |
| 2466 void movptr(Register dst, int32_t imm32); | |
| 2467 #endif // _LP64 | |
| 2468 | |
| 0 | 2469 // to avoid hiding movl |
| 2470 void mov32(AddressLiteral dst, Register src); | |
| 2471 void mov32(Register dst, AddressLiteral src); | |
| 304 | 2472 |
| 0 | 2473 // to avoid hiding movb |
| 2474 void movbyte(ArrayAddress dst, int src); | |
| 2475 | |
| 2476 // Can push value or effective address | |
| 2477 void pushptr(AddressLiteral src); | |
| 2478 | |
| 304 | 2479 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
| 2480 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
| 2481 | |
| 2482 void pushoop(jobject obj); | |
| 2483 | |
| 2484 // sign extend as need a l to ptr sized element | |
| 2485 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
| 2486 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
| 2487 | |
|
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2488 // IndexOf strings. |
|
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2489 // Small strings are loaded through stack if they cross page boundary. |
|
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2490 void string_indexof(Register str1, Register str2, |
|
2320
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2491 Register cnt1, Register cnt2, |
|
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|
2492 int int_cnt2, Register result, |
|
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|
2493 XMMRegister vec, Register tmp); |
|
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|
2494 |
|
2320
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|
2495 // IndexOf for constant substrings with size >= 8 elements |
|
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2496 // which don't need to be loaded through stack. |
|
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|
2497 void string_indexofC8(Register str1, Register str2, |
|
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|
2498 Register cnt1, Register cnt2, |
|
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2499 int int_cnt2, Register result, |
|
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2500 XMMRegister vec, Register tmp); |
|
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|
2501 |
|
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2502 // Smallest code: we don't need to load through stack, |
|
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|
2503 // check string tail. |
|
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|
2504 |
|
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2505 // Compare strings. |
|
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|
2506 void string_compare(Register str1, Register str2, |
|
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|
2507 Register cnt1, Register cnt2, Register result, |
| 2262 | 2508 XMMRegister vec1); |
|
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|
2509 |
|
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|
2510 // Compare char[] arrays. |
|
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|
2511 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
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|
2512 Register limit, Register result, Register chr, |
|
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|
2513 XMMRegister vec1, XMMRegister vec2); |
| 304 | 2514 |
| 1763 | 2515 // Fill primitive arrays |
| 2516 void generate_fill(BasicType t, bool aligned, | |
| 2517 Register to, Register value, Register count, | |
| 2518 Register rtmp, XMMRegister xtmp); | |
| 2519 | |
| 0 | 2520 #undef VIRTUAL |
| 2521 | |
| 2522 }; | |
| 2523 | |
| 2524 /** | |
| 2525 * class SkipIfEqual: | |
| 2526 * | |
| 2527 * Instantiating this class will result in assembly code being output that will | |
| 2528 * jump around any code emitted between the creation of the instance and it's | |
| 2529 * automatic destruction at the end of a scope block, depending on the value of | |
| 2530 * the flag passed to the constructor, which will be checked at run-time. | |
| 2531 */ | |
| 2532 class SkipIfEqual { | |
| 2533 private: | |
| 2534 MacroAssembler* _masm; | |
| 2535 Label _label; | |
| 2536 | |
| 2537 public: | |
| 2538 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
| 2539 ~SkipIfEqual(); | |
| 2540 }; | |
| 2541 | |
| 2542 #ifdef ASSERT | |
| 2543 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
| 2544 #endif | |
| 1972 | 2545 |
| 2546 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |