truffle: src/cpu/sparc/vm/assembler

annotate src/cpu/sparc/vm/assembler_sparc.hpp @ 17877:17b2fbdb6637

8038297: Avoid placing CTI immediately following cbcond instruction on T4 Summary: Insert a nop between cbcond and CTI Reviewed-by: kvn, twisti

author	iveresov
date	Thu, 10 Apr 2014 23:15:13 -0700
parents	04d32e7fad07
children	03214612e77e

rev	line source
0 a61af66fc99e Initial load duke parents: diff changeset	1 /*
17467 55fb97c4c58d 8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013 mikael parents: 10997 diff changeset	2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
0 a61af66fc99e Initial load duke parents: diff changeset	3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
a61af66fc99e Initial load duke parents: diff changeset	4 *
a61af66fc99e Initial load duke parents: diff changeset	5 * This code is free software; you can redistribute it and/or modify it
a61af66fc99e Initial load duke parents: diff changeset	6 * under the terms of the GNU General Public License version 2 only, as
a61af66fc99e Initial load duke parents: diff changeset	7 * published by the Free Software Foundation.
a61af66fc99e Initial load duke parents: diff changeset	8 *
a61af66fc99e Initial load duke parents: diff changeset	9 * This code is distributed in the hope that it will be useful, but WITHOUT
a61af66fc99e Initial load duke parents: diff changeset	10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
a61af66fc99e Initial load duke parents: diff changeset	11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
a61af66fc99e Initial load duke parents: diff changeset	12 * version 2 for more details (a copy is included in the LICENSE file that
a61af66fc99e Initial load duke parents: diff changeset	13 * accompanied this code).
a61af66fc99e Initial load duke parents: diff changeset	14 *
a61af66fc99e Initial load duke parents: diff changeset	15 * You should have received a copy of the GNU General Public License version
a61af66fc99e Initial load duke parents: diff changeset	16 * 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load duke parents: diff changeset	17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
a61af66fc99e Initial load duke parents: diff changeset	18 *
1552 c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1547 diff changeset	19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1547 diff changeset	20 * or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1547 diff changeset	21 * questions.
0 a61af66fc99e Initial load duke parents: diff changeset	22 *
a61af66fc99e Initial load duke parents: diff changeset	23 */
a61af66fc99e Initial load duke parents: diff changeset	24
1972 f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1911 diff changeset	25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1911 diff changeset	26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1911 diff changeset	27
7204 f0c2369fda5a 8003250: SPARC: move MacroAssembler into separate file twisti parents: 6848 diff changeset	28 #include "asm/register.hpp"
0 a61af66fc99e Initial load duke parents: diff changeset	29
a61af66fc99e Initial load duke parents: diff changeset	30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
a61af66fc99e Initial load duke parents: diff changeset	31 // level; i.e., what you write
a61af66fc99e Initial load duke parents: diff changeset	32 // is what you get. The Assembler is generating code into a CodeBuffer.
a61af66fc99e Initial load duke parents: diff changeset	33
a61af66fc99e Initial load duke parents: diff changeset	34 class Assembler : public AbstractAssembler {
a61af66fc99e Initial load duke parents: diff changeset	35 friend class AbstractAssembler;
727 6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC twisti parents: 710 diff changeset	36 friend class AddressLiteral;
0 a61af66fc99e Initial load duke parents: diff changeset	37
a61af66fc99e Initial load duke parents: diff changeset	38 // code patchers need various routines like inv_wdisp()
a61af66fc99e Initial load duke parents: diff changeset	39 friend class NativeInstruction;
a61af66fc99e Initial load duke parents: diff changeset	40 friend class NativeGeneralJump;
a61af66fc99e Initial load duke parents: diff changeset	41 friend class Relocation;
a61af66fc99e Initial load duke parents: diff changeset	42 friend class Label;
a61af66fc99e Initial load duke parents: diff changeset	43
a61af66fc99e Initial load duke parents: diff changeset	44 public:
a61af66fc99e Initial load duke parents: diff changeset	45 // op carries format info; see page 62 & 267
a61af66fc99e Initial load duke parents: diff changeset	46
a61af66fc99e Initial load duke parents: diff changeset	47 enum ops {
a61af66fc99e Initial load duke parents: diff changeset	48 call_op = 1, // fmt 1
a61af66fc99e Initial load duke parents: diff changeset	49 branch_op = 0, // also sethi (fmt2)
a61af66fc99e Initial load duke parents: diff changeset	50 arith_op = 2, // fmt 3, arith & misc
a61af66fc99e Initial load duke parents: diff changeset	51 ldst_op = 3 // fmt 3, load/store
a61af66fc99e Initial load duke parents: diff changeset	52 };
a61af66fc99e Initial load duke parents: diff changeset	53
a61af66fc99e Initial load duke parents: diff changeset	54 enum op2s {
a61af66fc99e Initial load duke parents: diff changeset	55 bpr_op2 = 3,
a61af66fc99e Initial load duke parents: diff changeset	56 fb_op2 = 6,
a61af66fc99e Initial load duke parents: diff changeset	57 fbp_op2 = 5,
a61af66fc99e Initial load duke parents: diff changeset	58 br_op2 = 2,
a61af66fc99e Initial load duke parents: diff changeset	59 bp_op2 = 1,
a61af66fc99e Initial load duke parents: diff changeset	60 sethi_op2 = 4
a61af66fc99e Initial load duke parents: diff changeset	61 };
a61af66fc99e Initial load duke parents: diff changeset	62
a61af66fc99e Initial load duke parents: diff changeset	63 enum op3s {
a61af66fc99e Initial load duke parents: diff changeset	64 // selected op3s
a61af66fc99e Initial load duke parents: diff changeset	65 add_op3 = 0x00,
a61af66fc99e Initial load duke parents: diff changeset	66 and_op3 = 0x01,
a61af66fc99e Initial load duke parents: diff changeset	67 or_op3 = 0x02,
a61af66fc99e Initial load duke parents: diff changeset	68 xor_op3 = 0x03,
a61af66fc99e Initial load duke parents: diff changeset	69 sub_op3 = 0x04,
a61af66fc99e Initial load duke parents: diff changeset	70 andn_op3 = 0x05,
a61af66fc99e Initial load duke parents: diff changeset	71 orn_op3 = 0x06,
a61af66fc99e Initial load duke parents: diff changeset	72 xnor_op3 = 0x07,
a61af66fc99e Initial load duke parents: diff changeset	73 addc_op3 = 0x08,
a61af66fc99e Initial load duke parents: diff changeset	74 mulx_op3 = 0x09,
a61af66fc99e Initial load duke parents: diff changeset	75 umul_op3 = 0x0a,
a61af66fc99e Initial load duke parents: diff changeset	76 smul_op3 = 0x0b,
a61af66fc99e Initial load duke parents: diff changeset	77 subc_op3 = 0x0c,
a61af66fc99e Initial load duke parents: diff changeset	78 udivx_op3 = 0x0d,
a61af66fc99e Initial load duke parents: diff changeset	79 udiv_op3 = 0x0e,
a61af66fc99e Initial load duke parents: diff changeset	80 sdiv_op3 = 0x0f,
a61af66fc99e Initial load duke parents: diff changeset	81
a61af66fc99e Initial load duke parents: diff changeset	82 addcc_op3 = 0x10,
a61af66fc99e Initial load duke parents: diff changeset	83 andcc_op3 = 0x11,
a61af66fc99e Initial load duke parents: diff changeset	84 orcc_op3 = 0x12,
a61af66fc99e Initial load duke parents: diff changeset	85 xorcc_op3 = 0x13,
a61af66fc99e Initial load duke parents: diff changeset	86 subcc_op3 = 0x14,
a61af66fc99e Initial load duke parents: diff changeset	87 andncc_op3 = 0x15,
a61af66fc99e Initial load duke parents: diff changeset	88 orncc_op3 = 0x16,
a61af66fc99e Initial load duke parents: diff changeset	89 xnorcc_op3 = 0x17,
a61af66fc99e Initial load duke parents: diff changeset	90 addccc_op3 = 0x18,
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	91 aes4_op3 = 0x19,
0 a61af66fc99e Initial load duke parents: diff changeset	92 umulcc_op3 = 0x1a,
a61af66fc99e Initial load duke parents: diff changeset	93 smulcc_op3 = 0x1b,
a61af66fc99e Initial load duke parents: diff changeset	94 subccc_op3 = 0x1c,
a61af66fc99e Initial load duke parents: diff changeset	95 udivcc_op3 = 0x1e,
a61af66fc99e Initial load duke parents: diff changeset	96 sdivcc_op3 = 0x1f,
a61af66fc99e Initial load duke parents: diff changeset	97
a61af66fc99e Initial load duke parents: diff changeset	98 taddcc_op3 = 0x20,
a61af66fc99e Initial load duke parents: diff changeset	99 tsubcc_op3 = 0x21,
a61af66fc99e Initial load duke parents: diff changeset	100 taddcctv_op3 = 0x22,
a61af66fc99e Initial load duke parents: diff changeset	101 tsubcctv_op3 = 0x23,
a61af66fc99e Initial load duke parents: diff changeset	102 mulscc_op3 = 0x24,
a61af66fc99e Initial load duke parents: diff changeset	103 sll_op3 = 0x25,
a61af66fc99e Initial load duke parents: diff changeset	104 sllx_op3 = 0x25,
a61af66fc99e Initial load duke parents: diff changeset	105 srl_op3 = 0x26,
a61af66fc99e Initial load duke parents: diff changeset	106 srlx_op3 = 0x26,
a61af66fc99e Initial load duke parents: diff changeset	107 sra_op3 = 0x27,
a61af66fc99e Initial load duke parents: diff changeset	108 srax_op3 = 0x27,
a61af66fc99e Initial load duke parents: diff changeset	109 rdreg_op3 = 0x28,
a61af66fc99e Initial load duke parents: diff changeset	110 membar_op3 = 0x28,
a61af66fc99e Initial load duke parents: diff changeset	111
a61af66fc99e Initial load duke parents: diff changeset	112 flushw_op3 = 0x2b,
a61af66fc99e Initial load duke parents: diff changeset	113 movcc_op3 = 0x2c,
a61af66fc99e Initial load duke parents: diff changeset	114 sdivx_op3 = 0x2d,
a61af66fc99e Initial load duke parents: diff changeset	115 popc_op3 = 0x2e,
a61af66fc99e Initial load duke parents: diff changeset	116 movr_op3 = 0x2f,
a61af66fc99e Initial load duke parents: diff changeset	117
a61af66fc99e Initial load duke parents: diff changeset	118 sir_op3 = 0x30,
a61af66fc99e Initial load duke parents: diff changeset	119 wrreg_op3 = 0x30,
a61af66fc99e Initial load duke parents: diff changeset	120 saved_op3 = 0x31,
a61af66fc99e Initial load duke parents: diff changeset	121
a61af66fc99e Initial load duke parents: diff changeset	122 fpop1_op3 = 0x34,
a61af66fc99e Initial load duke parents: diff changeset	123 fpop2_op3 = 0x35,
a61af66fc99e Initial load duke parents: diff changeset	124 impdep1_op3 = 0x36,
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	125 aes3_op3 = 0x36,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	126 flog3_op3 = 0x36,
0 a61af66fc99e Initial load duke parents: diff changeset	127 impdep2_op3 = 0x37,
a61af66fc99e Initial load duke parents: diff changeset	128 jmpl_op3 = 0x38,
a61af66fc99e Initial load duke parents: diff changeset	129 rett_op3 = 0x39,
a61af66fc99e Initial load duke parents: diff changeset	130 trap_op3 = 0x3a,
a61af66fc99e Initial load duke parents: diff changeset	131 flush_op3 = 0x3b,
a61af66fc99e Initial load duke parents: diff changeset	132 save_op3 = 0x3c,
a61af66fc99e Initial load duke parents: diff changeset	133 restore_op3 = 0x3d,
a61af66fc99e Initial load duke parents: diff changeset	134 done_op3 = 0x3e,
a61af66fc99e Initial load duke parents: diff changeset	135 retry_op3 = 0x3e,
a61af66fc99e Initial load duke parents: diff changeset	136
a61af66fc99e Initial load duke parents: diff changeset	137 lduw_op3 = 0x00,
a61af66fc99e Initial load duke parents: diff changeset	138 ldub_op3 = 0x01,
a61af66fc99e Initial load duke parents: diff changeset	139 lduh_op3 = 0x02,
a61af66fc99e Initial load duke parents: diff changeset	140 ldd_op3 = 0x03,
a61af66fc99e Initial load duke parents: diff changeset	141 stw_op3 = 0x04,
a61af66fc99e Initial load duke parents: diff changeset	142 stb_op3 = 0x05,
a61af66fc99e Initial load duke parents: diff changeset	143 sth_op3 = 0x06,
a61af66fc99e Initial load duke parents: diff changeset	144 std_op3 = 0x07,
a61af66fc99e Initial load duke parents: diff changeset	145 ldsw_op3 = 0x08,
a61af66fc99e Initial load duke parents: diff changeset	146 ldsb_op3 = 0x09,
a61af66fc99e Initial load duke parents: diff changeset	147 ldsh_op3 = 0x0a,
a61af66fc99e Initial load duke parents: diff changeset	148 ldx_op3 = 0x0b,
a61af66fc99e Initial load duke parents: diff changeset	149
a61af66fc99e Initial load duke parents: diff changeset	150 stx_op3 = 0x0e,
a61af66fc99e Initial load duke parents: diff changeset	151 swap_op3 = 0x0f,
a61af66fc99e Initial load duke parents: diff changeset	152
a61af66fc99e Initial load duke parents: diff changeset	153 stwa_op3 = 0x14,
a61af66fc99e Initial load duke parents: diff changeset	154 stxa_op3 = 0x1e,
a61af66fc99e Initial load duke parents: diff changeset	155
a61af66fc99e Initial load duke parents: diff changeset	156 ldf_op3 = 0x20,
a61af66fc99e Initial load duke parents: diff changeset	157 ldfsr_op3 = 0x21,
a61af66fc99e Initial load duke parents: diff changeset	158 ldqf_op3 = 0x22,
a61af66fc99e Initial load duke parents: diff changeset	159 lddf_op3 = 0x23,
a61af66fc99e Initial load duke parents: diff changeset	160 stf_op3 = 0x24,
a61af66fc99e Initial load duke parents: diff changeset	161 stfsr_op3 = 0x25,
a61af66fc99e Initial load duke parents: diff changeset	162 stqf_op3 = 0x26,
a61af66fc99e Initial load duke parents: diff changeset	163 stdf_op3 = 0x27,
a61af66fc99e Initial load duke parents: diff changeset	164
a61af66fc99e Initial load duke parents: diff changeset	165 prefetch_op3 = 0x2d,
a61af66fc99e Initial load duke parents: diff changeset	166
a61af66fc99e Initial load duke parents: diff changeset	167 casa_op3 = 0x3c,
a61af66fc99e Initial load duke parents: diff changeset	168 casxa_op3 = 0x3e,
a61af66fc99e Initial load duke parents: diff changeset	169
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	170 mftoi_op3 = 0x36,
faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	171
0 a61af66fc99e Initial load duke parents: diff changeset	172 alt_bit_op3 = 0x10,
a61af66fc99e Initial load duke parents: diff changeset	173 cc_bit_op3 = 0x10
a61af66fc99e Initial load duke parents: diff changeset	174 };
a61af66fc99e Initial load duke parents: diff changeset	175
a61af66fc99e Initial load duke parents: diff changeset	176 enum opfs {
a61af66fc99e Initial load duke parents: diff changeset	177 // selected opfs
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	178 fmovs_opf = 0x01,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	179 fmovd_opf = 0x02,
0 a61af66fc99e Initial load duke parents: diff changeset	180
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	181 fnegs_opf = 0x05,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	182 fnegd_opf = 0x06,
0 a61af66fc99e Initial load duke parents: diff changeset	183
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	184 fadds_opf = 0x41,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	185 faddd_opf = 0x42,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	186 fsubs_opf = 0x45,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	187 fsubd_opf = 0x46,
0 a61af66fc99e Initial load duke parents: diff changeset	188
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	189 fmuls_opf = 0x49,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	190 fmuld_opf = 0x4a,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	191 fdivs_opf = 0x4d,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	192 fdivd_opf = 0x4e,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	193
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	194 fcmps_opf = 0x51,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	195 fcmpd_opf = 0x52,
0 a61af66fc99e Initial load duke parents: diff changeset	196
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	197 fstox_opf = 0x81,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	198 fdtox_opf = 0x82,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	199 fxtos_opf = 0x84,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	200 fxtod_opf = 0x88,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	201 fitos_opf = 0xc4,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	202 fdtos_opf = 0xc6,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	203 fitod_opf = 0xc8,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	204 fstod_opf = 0xc9,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	205 fstoi_opf = 0xd1,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	206 fdtoi_opf = 0xd2,
0 a61af66fc99e Initial load duke parents: diff changeset	207
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	208 mdtox_opf = 0x110,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	209 mstouw_opf = 0x111,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	210 mstosw_opf = 0x113,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	211 mxtod_opf = 0x118,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	212 mwtos_opf = 0x119,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	213
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	214 aes_kexpand0_opf = 0x130,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	215 aes_kexpand2_opf = 0x131
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	216 };
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	217
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	218 enum op5s {
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	219 aes_eround01_op5 = 0x00,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	220 aes_eround23_op5 = 0x01,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	221 aes_dround01_op5 = 0x02,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	222 aes_dround23_op5 = 0x03,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	223 aes_eround01_l_op5 = 0x04,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	224 aes_eround23_l_op5 = 0x05,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	225 aes_dround01_l_op5 = 0x06,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	226 aes_dround23_l_op5 = 0x07,
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	227 aes_kexpand1_op5 = 0x08
0 a61af66fc99e Initial load duke parents: diff changeset	228 };
a61af66fc99e Initial load duke parents: diff changeset	229
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	230 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
0 a61af66fc99e Initial load duke parents: diff changeset	231
a61af66fc99e Initial load duke parents: diff changeset	232 enum Condition {
a61af66fc99e Initial load duke parents: diff changeset	233 // for FBfcc & FBPfcc instruction
a61af66fc99e Initial load duke parents: diff changeset	234 f_never = 0,
a61af66fc99e Initial load duke parents: diff changeset	235 f_notEqual = 1,
a61af66fc99e Initial load duke parents: diff changeset	236 f_notZero = 1,
a61af66fc99e Initial load duke parents: diff changeset	237 f_lessOrGreater = 2,
a61af66fc99e Initial load duke parents: diff changeset	238 f_unorderedOrLess = 3,
a61af66fc99e Initial load duke parents: diff changeset	239 f_less = 4,
a61af66fc99e Initial load duke parents: diff changeset	240 f_unorderedOrGreater = 5,
a61af66fc99e Initial load duke parents: diff changeset	241 f_greater = 6,
a61af66fc99e Initial load duke parents: diff changeset	242 f_unordered = 7,
a61af66fc99e Initial load duke parents: diff changeset	243 f_always = 8,
a61af66fc99e Initial load duke parents: diff changeset	244 f_equal = 9,
a61af66fc99e Initial load duke parents: diff changeset	245 f_zero = 9,
a61af66fc99e Initial load duke parents: diff changeset	246 f_unorderedOrEqual = 10,
a61af66fc99e Initial load duke parents: diff changeset	247 f_greaterOrEqual = 11,
a61af66fc99e Initial load duke parents: diff changeset	248 f_unorderedOrGreaterOrEqual = 12,
a61af66fc99e Initial load duke parents: diff changeset	249 f_lessOrEqual = 13,
a61af66fc99e Initial load duke parents: diff changeset	250 f_unorderedOrLessOrEqual = 14,
a61af66fc99e Initial load duke parents: diff changeset	251 f_ordered = 15,
a61af66fc99e Initial load duke parents: diff changeset	252
a61af66fc99e Initial load duke parents: diff changeset	253 // V8 coproc, pp 123 v8 manual
a61af66fc99e Initial load duke parents: diff changeset	254
a61af66fc99e Initial load duke parents: diff changeset	255 cp_always = 8,
a61af66fc99e Initial load duke parents: diff changeset	256 cp_never = 0,
a61af66fc99e Initial load duke parents: diff changeset	257 cp_3 = 7,
a61af66fc99e Initial load duke parents: diff changeset	258 cp_2 = 6,
a61af66fc99e Initial load duke parents: diff changeset	259 cp_2or3 = 5,
a61af66fc99e Initial load duke parents: diff changeset	260 cp_1 = 4,
a61af66fc99e Initial load duke parents: diff changeset	261 cp_1or3 = 3,
a61af66fc99e Initial load duke parents: diff changeset	262 cp_1or2 = 2,
a61af66fc99e Initial load duke parents: diff changeset	263 cp_1or2or3 = 1,
a61af66fc99e Initial load duke parents: diff changeset	264 cp_0 = 9,
a61af66fc99e Initial load duke parents: diff changeset	265 cp_0or3 = 10,
a61af66fc99e Initial load duke parents: diff changeset	266 cp_0or2 = 11,
a61af66fc99e Initial load duke parents: diff changeset	267 cp_0or2or3 = 12,
a61af66fc99e Initial load duke parents: diff changeset	268 cp_0or1 = 13,
a61af66fc99e Initial load duke parents: diff changeset	269 cp_0or1or3 = 14,
a61af66fc99e Initial load duke parents: diff changeset	270 cp_0or1or2 = 15,
a61af66fc99e Initial load duke parents: diff changeset	271
a61af66fc99e Initial load duke parents: diff changeset	272
a61af66fc99e Initial load duke parents: diff changeset	273 // for integers
a61af66fc99e Initial load duke parents: diff changeset	274
a61af66fc99e Initial load duke parents: diff changeset	275 never = 0,
a61af66fc99e Initial load duke parents: diff changeset	276 equal = 1,
a61af66fc99e Initial load duke parents: diff changeset	277 zero = 1,
a61af66fc99e Initial load duke parents: diff changeset	278 lessEqual = 2,
a61af66fc99e Initial load duke parents: diff changeset	279 less = 3,
a61af66fc99e Initial load duke parents: diff changeset	280 lessEqualUnsigned = 4,
a61af66fc99e Initial load duke parents: diff changeset	281 lessUnsigned = 5,
a61af66fc99e Initial load duke parents: diff changeset	282 carrySet = 5,
a61af66fc99e Initial load duke parents: diff changeset	283 negative = 6,
a61af66fc99e Initial load duke parents: diff changeset	284 overflowSet = 7,
a61af66fc99e Initial load duke parents: diff changeset	285 always = 8,
a61af66fc99e Initial load duke parents: diff changeset	286 notEqual = 9,
a61af66fc99e Initial load duke parents: diff changeset	287 notZero = 9,
a61af66fc99e Initial load duke parents: diff changeset	288 greater = 10,
a61af66fc99e Initial load duke parents: diff changeset	289 greaterEqual = 11,
a61af66fc99e Initial load duke parents: diff changeset	290 greaterUnsigned = 12,
a61af66fc99e Initial load duke parents: diff changeset	291 greaterEqualUnsigned = 13,
a61af66fc99e Initial load duke parents: diff changeset	292 carryClear = 13,
a61af66fc99e Initial load duke parents: diff changeset	293 positive = 14,
a61af66fc99e Initial load duke parents: diff changeset	294 overflowClear = 15
a61af66fc99e Initial load duke parents: diff changeset	295 };
a61af66fc99e Initial load duke parents: diff changeset	296
a61af66fc99e Initial load duke parents: diff changeset	297 enum CC {
a61af66fc99e Initial load duke parents: diff changeset	298 icc = 0, xcc = 2,
a61af66fc99e Initial load duke parents: diff changeset	299 // ptr_cc is the correct condition code for a pointer or intptr_t:
a61af66fc99e Initial load duke parents: diff changeset	300 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
a61af66fc99e Initial load duke parents: diff changeset	301 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
a61af66fc99e Initial load duke parents: diff changeset	302 };
a61af66fc99e Initial load duke parents: diff changeset	303
a61af66fc99e Initial load duke parents: diff changeset	304 enum PrefetchFcn {
a61af66fc99e Initial load duke parents: diff changeset	305 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
a61af66fc99e Initial load duke parents: diff changeset	306 };
a61af66fc99e Initial load duke parents: diff changeset	307
a61af66fc99e Initial load duke parents: diff changeset	308 public:
a61af66fc99e Initial load duke parents: diff changeset	309 // Helper functions for groups of instructions
a61af66fc99e Initial load duke parents: diff changeset	310
a61af66fc99e Initial load duke parents: diff changeset	311 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
a61af66fc99e Initial load duke parents: diff changeset	312
a61af66fc99e Initial load duke parents: diff changeset	313 enum Membar_mask_bits { // page 184, v9
a61af66fc99e Initial load duke parents: diff changeset	314 StoreStore = 1 << 3,
a61af66fc99e Initial load duke parents: diff changeset	315 LoadStore = 1 << 2,
a61af66fc99e Initial load duke parents: diff changeset	316 StoreLoad = 1 << 1,
a61af66fc99e Initial load duke parents: diff changeset	317 LoadLoad = 1 << 0,
a61af66fc99e Initial load duke parents: diff changeset	318
a61af66fc99e Initial load duke parents: diff changeset	319 Sync = 1 << 6,
a61af66fc99e Initial load duke parents: diff changeset	320 MemIssue = 1 << 5,
a61af66fc99e Initial load duke parents: diff changeset	321 Lookaside = 1 << 4
a61af66fc99e Initial load duke parents: diff changeset	322 };
a61af66fc99e Initial load duke parents: diff changeset	323
2121 c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	324 static bool is_in_wdisp_range(address a, address b, int nbits) {
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	325 intptr_t d = intptr_t(b) - intptr_t(a);
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	326 return is_simm(d, nbits + 2);
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	327 }
0 a61af66fc99e Initial load duke parents: diff changeset	328
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	329 address target_distance(Label& L) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	330 // Assembler::target(L) should be called only when
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	331 // a branch instruction is emitted since non-bound
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	332 // labels record current pc() as a branch address.
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	333 if (L.is_bound()) return target(L);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	334 // Return current address for non-bound labels.
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	335 return pc();
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	336 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	337
1848 c393f046f4c5 6991512: G1 barriers fail with 64bit C1 iveresov parents: 1846 diff changeset	338 // test if label is in simm16 range in words (wdisp16).
c393f046f4c5 6991512: G1 barriers fail with 64bit C1 iveresov parents: 1846 diff changeset	339 bool is_in_wdisp16_range(Label& L) {
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	340 return is_in_wdisp_range(target_distance(L), pc(), 16);
2121 c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	341 }
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	342 // test if the distance between two addresses fits in simm30 range in words
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	343 static bool is_in_wdisp30_range(address a, address b) {
c17b998c5926 7011627: C1: call_RT must support targets that don't fit in wdisp30 iveresov parents: 2076 diff changeset	344 return is_in_wdisp_range(a, b, 30);
1848 c393f046f4c5 6991512: G1 barriers fail with 64bit C1 iveresov parents: 1846 diff changeset	345 }
c393f046f4c5 6991512: G1 barriers fail with 64bit C1 iveresov parents: 1846 diff changeset	346
0 a61af66fc99e Initial load duke parents: diff changeset	347 enum ASIs { // page 72, v9
3892 baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	348 ASI_PRIMARY = 0x80,
baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	349 ASI_PRIMARY_NOFAULT = 0x82,
baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	350 ASI_PRIMARY_LITTLE = 0x88,
3854 1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	351 // Block initializing store
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	352 ASI_ST_BLKINIT_PRIMARY = 0xE2,
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	353 // Most-Recently-Used (MRU) BIS variant
1af104d6cf99 7079329: Adjust allocation prefetching for T4 kvn parents: 3851 diff changeset	354 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
0 a61af66fc99e Initial load duke parents: diff changeset	355 // add more from book as needed
a61af66fc99e Initial load duke parents: diff changeset	356 };
a61af66fc99e Initial load duke parents: diff changeset	357
a61af66fc99e Initial load duke parents: diff changeset	358 protected:
a61af66fc99e Initial load duke parents: diff changeset	359 // helpers
a61af66fc99e Initial load duke parents: diff changeset	360
a61af66fc99e Initial load duke parents: diff changeset	361 // x is supposed to fit in a field "nbits" wide
a61af66fc99e Initial load duke parents: diff changeset	362 // and be sign-extended. Check the range.
a61af66fc99e Initial load duke parents: diff changeset	363
a61af66fc99e Initial load duke parents: diff changeset	364 static void assert_signed_range(intptr_t x, int nbits) {
3753 cba7b5c2d53f 7045514: SPARC assembly code for JSR 292 ricochet frames never parents: 3249 diff changeset	365 assert(nbits == 32 \|\| (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
cba7b5c2d53f 7045514: SPARC assembly code for JSR 292 ricochet frames never parents: 3249 diff changeset	366 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
0 a61af66fc99e Initial load duke parents: diff changeset	367 }
a61af66fc99e Initial load duke parents: diff changeset	368
a61af66fc99e Initial load duke parents: diff changeset	369 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
a61af66fc99e Initial load duke parents: diff changeset	370 assert( (x & 3) == 0, "not word aligned");
a61af66fc99e Initial load duke parents: diff changeset	371 assert_signed_range(x, nbits + 2);
a61af66fc99e Initial load duke parents: diff changeset	372 }
a61af66fc99e Initial load duke parents: diff changeset	373
a61af66fc99e Initial load duke parents: diff changeset	374 static void assert_unsigned_const(int x, int nbits) {
a61af66fc99e Initial load duke parents: diff changeset	375 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
a61af66fc99e Initial load duke parents: diff changeset	376 }
a61af66fc99e Initial load duke parents: diff changeset	377
a61af66fc99e Initial load duke parents: diff changeset	378 // fields: note bits numbered from LSB = 0,
a61af66fc99e Initial load duke parents: diff changeset	379 // fields known by inclusive bit range
a61af66fc99e Initial load duke parents: diff changeset	380
a61af66fc99e Initial load duke parents: diff changeset	381 static int fmask(juint hi_bit, juint lo_bit) {
a61af66fc99e Initial load duke parents: diff changeset	382 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
a61af66fc99e Initial load duke parents: diff changeset	383 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
a61af66fc99e Initial load duke parents: diff changeset	384 }
a61af66fc99e Initial load duke parents: diff changeset	385
a61af66fc99e Initial load duke parents: diff changeset	386 // inverse of u_field
a61af66fc99e Initial load duke parents: diff changeset	387
a61af66fc99e Initial load duke parents: diff changeset	388 static int inv_u_field(int x, int hi_bit, int lo_bit) {
a61af66fc99e Initial load duke parents: diff changeset	389 juint r = juint(x) >> lo_bit;
a61af66fc99e Initial load duke parents: diff changeset	390 r &= fmask( hi_bit, lo_bit);
a61af66fc99e Initial load duke parents: diff changeset	391 return int(r);
a61af66fc99e Initial load duke parents: diff changeset	392 }
a61af66fc99e Initial load duke parents: diff changeset	393
a61af66fc99e Initial load duke parents: diff changeset	394
a61af66fc99e Initial load duke parents: diff changeset	395 // signed version: extract from field and sign-extend
a61af66fc99e Initial load duke parents: diff changeset	396
a61af66fc99e Initial load duke parents: diff changeset	397 static int inv_s_field(int x, int hi_bit, int lo_bit) {
a61af66fc99e Initial load duke parents: diff changeset	398 int sign_shift = 31 - hi_bit;
a61af66fc99e Initial load duke parents: diff changeset	399 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
a61af66fc99e Initial load duke parents: diff changeset	400 }
a61af66fc99e Initial load duke parents: diff changeset	401
a61af66fc99e Initial load duke parents: diff changeset	402 // given a field that ranges from hi_bit to lo_bit (inclusive,
a61af66fc99e Initial load duke parents: diff changeset	403 // LSB = 0), and an unsigned value for the field,
a61af66fc99e Initial load duke parents: diff changeset	404 // shift it into the field
a61af66fc99e Initial load duke parents: diff changeset	405
a61af66fc99e Initial load duke parents: diff changeset	406 #ifdef ASSERT
a61af66fc99e Initial load duke parents: diff changeset	407 static int u_field(int x, int hi_bit, int lo_bit) {
a61af66fc99e Initial load duke parents: diff changeset	408 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
a61af66fc99e Initial load duke parents: diff changeset	409 "value out of range");
a61af66fc99e Initial load duke parents: diff changeset	410 int r = x << lo_bit;
a61af66fc99e Initial load duke parents: diff changeset	411 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
a61af66fc99e Initial load duke parents: diff changeset	412 return r;
a61af66fc99e Initial load duke parents: diff changeset	413 }
a61af66fc99e Initial load duke parents: diff changeset	414 #else
a61af66fc99e Initial load duke parents: diff changeset	415 // make sure this is inlined as it will reduce code size significantly
a61af66fc99e Initial load duke parents: diff changeset	416 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
a61af66fc99e Initial load duke parents: diff changeset	417 #endif
a61af66fc99e Initial load duke parents: diff changeset	418
a61af66fc99e Initial load duke parents: diff changeset	419 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
a61af66fc99e Initial load duke parents: diff changeset	420 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
a61af66fc99e Initial load duke parents: diff changeset	421 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
a61af66fc99e Initial load duke parents: diff changeset	422 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
a61af66fc99e Initial load duke parents: diff changeset	423
a61af66fc99e Initial load duke parents: diff changeset	424 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
a61af66fc99e Initial load duke parents: diff changeset	425
a61af66fc99e Initial load duke parents: diff changeset	426 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
a61af66fc99e Initial load duke parents: diff changeset	427 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
a61af66fc99e Initial load duke parents: diff changeset	428 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
a61af66fc99e Initial load duke parents: diff changeset	429
a61af66fc99e Initial load duke parents: diff changeset	430 static int op( int x) { return u_field(x, 31, 30); }
a61af66fc99e Initial load duke parents: diff changeset	431 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
a61af66fc99e Initial load duke parents: diff changeset	432 static int fcn( int x) { return u_field(x, 29, 25); }
a61af66fc99e Initial load duke parents: diff changeset	433 static int op3( int x) { return u_field(x, 24, 19); }
a61af66fc99e Initial load duke parents: diff changeset	434 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
a61af66fc99e Initial load duke parents: diff changeset	435 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
a61af66fc99e Initial load duke parents: diff changeset	436 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
a61af66fc99e Initial load duke parents: diff changeset	437 static int cond( int x) { return u_field(x, 28, 25); }
a61af66fc99e Initial load duke parents: diff changeset	438 static int cond_mov( int x) { return u_field(x, 17, 14); }
a61af66fc99e Initial load duke parents: diff changeset	439 static int rcond( RCondition x) { return u_field(x, 12, 10); }
a61af66fc99e Initial load duke parents: diff changeset	440 static int op2( int x) { return u_field(x, 24, 22); }
a61af66fc99e Initial load duke parents: diff changeset	441 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
a61af66fc99e Initial load duke parents: diff changeset	442 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
a61af66fc99e Initial load duke parents: diff changeset	443 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
a61af66fc99e Initial load duke parents: diff changeset	444 static int imm_asi( int x) { return u_field(x, 12, 5); }
a61af66fc99e Initial load duke parents: diff changeset	445 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
a61af66fc99e Initial load duke parents: diff changeset	446 static int opf_low6( int w) { return u_field(w, 10, 5); }
a61af66fc99e Initial load duke parents: diff changeset	447 static int opf_low5( int w) { return u_field(w, 9, 5); }
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	448 static int op5( int x) { return u_field(x, 8, 5); }
0 a61af66fc99e Initial load duke parents: diff changeset	449 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
a61af66fc99e Initial load duke parents: diff changeset	450 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
a61af66fc99e Initial load duke parents: diff changeset	451 static int opf( int x) { return u_field(x, 13, 5); }
a61af66fc99e Initial load duke parents: diff changeset	452
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	453 static bool is_cbcond( int x ) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	454 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	455 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	456 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	457 static bool is_cxb( int x ) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	458 assert(is_cbcond(x), "wrong instruction");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	459 return (x & (1<<21)) != 0;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	460 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	461 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	462 static int inv_cond_cbcond(int x) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	463 assert(is_cbcond(x), "wrong instruction");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	464 return inv_u_field(x, 27, 25) \| (inv_u_field(x, 29, 29)<<3);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	465 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	466
0 a61af66fc99e Initial load duke parents: diff changeset	467 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
a61af66fc99e Initial load duke parents: diff changeset	468 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) \| u_field(c, 12, 11); }
a61af66fc99e Initial load duke parents: diff changeset	469
a61af66fc99e Initial load duke parents: diff changeset	470 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
a61af66fc99e Initial load duke parents: diff changeset	471 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
a61af66fc99e Initial load duke parents: diff changeset	472 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	473 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
0 a61af66fc99e Initial load duke parents: diff changeset	474
a61af66fc99e Initial load duke parents: diff changeset	475 // some float instructions use this encoding on the op3 field
a61af66fc99e Initial load duke parents: diff changeset	476 static int alt_op3(int op, FloatRegisterImpl::Width w) {
a61af66fc99e Initial load duke parents: diff changeset	477 int r;
a61af66fc99e Initial load duke parents: diff changeset	478 switch(w) {
a61af66fc99e Initial load duke parents: diff changeset	479 case FloatRegisterImpl::S: r = op + 0; break;
a61af66fc99e Initial load duke parents: diff changeset	480 case FloatRegisterImpl::D: r = op + 3; break;
a61af66fc99e Initial load duke parents: diff changeset	481 case FloatRegisterImpl::Q: r = op + 2; break;
a61af66fc99e Initial load duke parents: diff changeset	482 default: ShouldNotReachHere(); break;
a61af66fc99e Initial load duke parents: diff changeset	483 }
a61af66fc99e Initial load duke parents: diff changeset	484 return op3(r);
a61af66fc99e Initial load duke parents: diff changeset	485 }
a61af66fc99e Initial load duke parents: diff changeset	486
a61af66fc99e Initial load duke parents: diff changeset	487
a61af66fc99e Initial load duke parents: diff changeset	488 // compute inverse of simm
a61af66fc99e Initial load duke parents: diff changeset	489 static int inv_simm(int x, int nbits) {
a61af66fc99e Initial load duke parents: diff changeset	490 return (int)(x << (32 - nbits)) >> (32 - nbits);
a61af66fc99e Initial load duke parents: diff changeset	491 }
a61af66fc99e Initial load duke parents: diff changeset	492
a61af66fc99e Initial load duke parents: diff changeset	493 static int inv_simm13( int x ) { return inv_simm(x, 13); }
a61af66fc99e Initial load duke parents: diff changeset	494
a61af66fc99e Initial load duke parents: diff changeset	495 // signed immediate, in low bits, nbits long
a61af66fc99e Initial load duke parents: diff changeset	496 static int simm(int x, int nbits) {
a61af66fc99e Initial load duke parents: diff changeset	497 assert_signed_range(x, nbits);
a61af66fc99e Initial load duke parents: diff changeset	498 return x & (( 1 << nbits ) - 1);
a61af66fc99e Initial load duke parents: diff changeset	499 }
a61af66fc99e Initial load duke parents: diff changeset	500
a61af66fc99e Initial load duke parents: diff changeset	501 // compute inverse of wdisp16
a61af66fc99e Initial load duke parents: diff changeset	502 static intptr_t inv_wdisp16(int x, intptr_t pos) {
a61af66fc99e Initial load duke parents: diff changeset	503 int lo = x & (( 1 << 14 ) - 1);
a61af66fc99e Initial load duke parents: diff changeset	504 int hi = (x >> 20) & 3;
a61af66fc99e Initial load duke parents: diff changeset	505 if (hi >= 2) hi \|= ~1;
a61af66fc99e Initial load duke parents: diff changeset	506 return (((hi << 14) \| lo) << 2) + pos;
a61af66fc99e Initial load duke parents: diff changeset	507 }
a61af66fc99e Initial load duke parents: diff changeset	508
a61af66fc99e Initial load duke parents: diff changeset	509 // word offset, 14 bits at LSend, 2 bits at B21, B20
a61af66fc99e Initial load duke parents: diff changeset	510 static int wdisp16(intptr_t x, intptr_t off) {
a61af66fc99e Initial load duke parents: diff changeset	511 intptr_t xx = x - off;
a61af66fc99e Initial load duke parents: diff changeset	512 assert_signed_word_disp_range(xx, 16);
a61af66fc99e Initial load duke parents: diff changeset	513 int r = (xx >> 2) & ((1 << 14) - 1)
a61af66fc99e Initial load duke parents: diff changeset	514 \| ( ( (xx>>(2+14)) & 3 ) << 20 );
a61af66fc99e Initial load duke parents: diff changeset	515 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
a61af66fc99e Initial load duke parents: diff changeset	516 return r;
a61af66fc99e Initial load duke parents: diff changeset	517 }
a61af66fc99e Initial load duke parents: diff changeset	518
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	519 // compute inverse of wdisp10
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	520 static intptr_t inv_wdisp10(int x, intptr_t pos) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	521 assert(is_cbcond(x), "wrong instruction");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	522 int lo = inv_u_field(x, 12, 5);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	523 int hi = (x >> 19) & 3;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	524 if (hi >= 2) hi \|= ~1;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	525 return (((hi << 8) \| lo) << 2) + pos;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	526 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	527
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	528 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	529 static int wdisp10(intptr_t x, intptr_t off) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	530 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	531 intptr_t xx = x - off;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	532 assert_signed_word_disp_range(xx, 10);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	533 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	534 \| ( ( (xx >> (2+8)) & 3 ) << 19 );
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	535 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	536 assert(inv_wdisp10((r \| op(branch_op) \| cond_cbcond(rc_last+1) \| op2(bpr_op2)), off) == x, "inverse is not inverse");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	537 return r;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	538 }
0 a61af66fc99e Initial load duke parents: diff changeset	539
a61af66fc99e Initial load duke parents: diff changeset	540 // word displacement in low-order nbits bits
a61af66fc99e Initial load duke parents: diff changeset	541
a61af66fc99e Initial load duke parents: diff changeset	542 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
a61af66fc99e Initial load duke parents: diff changeset	543 int pre_sign_extend = x & (( 1 << nbits ) - 1);
a61af66fc99e Initial load duke parents: diff changeset	544 int r = pre_sign_extend >= ( 1 << (nbits-1) )
a61af66fc99e Initial load duke parents: diff changeset	545 ? pre_sign_extend \| ~(( 1 << nbits ) - 1)
a61af66fc99e Initial load duke parents: diff changeset	546 : pre_sign_extend;
a61af66fc99e Initial load duke parents: diff changeset	547 return (r << 2) + pos;
a61af66fc99e Initial load duke parents: diff changeset	548 }
a61af66fc99e Initial load duke parents: diff changeset	549
a61af66fc99e Initial load duke parents: diff changeset	550 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
a61af66fc99e Initial load duke parents: diff changeset	551 intptr_t xx = x - off;
a61af66fc99e Initial load duke parents: diff changeset	552 assert_signed_word_disp_range(xx, nbits);
a61af66fc99e Initial load duke parents: diff changeset	553 int r = (xx >> 2) & (( 1 << nbits ) - 1);
a61af66fc99e Initial load duke parents: diff changeset	554 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
a61af66fc99e Initial load duke parents: diff changeset	555 return r;
a61af66fc99e Initial load duke parents: diff changeset	556 }
a61af66fc99e Initial load duke parents: diff changeset	557
a61af66fc99e Initial load duke parents: diff changeset	558
a61af66fc99e Initial load duke parents: diff changeset	559 // Extract the top 32 bits in a 64 bit word
a61af66fc99e Initial load duke parents: diff changeset	560 static int32_t hi32( int64_t x ) {
a61af66fc99e Initial load duke parents: diff changeset	561 int32_t r = int32_t( (uint64_t)x >> 32 );
a61af66fc99e Initial load duke parents: diff changeset	562 return r;
a61af66fc99e Initial load duke parents: diff changeset	563 }
a61af66fc99e Initial load duke parents: diff changeset	564
a61af66fc99e Initial load duke parents: diff changeset	565 // given a sethi instruction, extract the constant, left-justified
a61af66fc99e Initial load duke parents: diff changeset	566 static int inv_hi22( int x ) {
a61af66fc99e Initial load duke parents: diff changeset	567 return x << 10;
a61af66fc99e Initial load duke parents: diff changeset	568 }
a61af66fc99e Initial load duke parents: diff changeset	569
a61af66fc99e Initial load duke parents: diff changeset	570 // create an imm22 field, given a 32-bit left-justified constant
a61af66fc99e Initial load duke parents: diff changeset	571 static int hi22( int x ) {
a61af66fc99e Initial load duke parents: diff changeset	572 int r = int( juint(x) >> 10 );
a61af66fc99e Initial load duke parents: diff changeset	573 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
a61af66fc99e Initial load duke parents: diff changeset	574 return r;
a61af66fc99e Initial load duke parents: diff changeset	575 }
a61af66fc99e Initial load duke parents: diff changeset	576
a61af66fc99e Initial load duke parents: diff changeset	577 // create a low10 __value__ (not a field) for a given a 32-bit constant
a61af66fc99e Initial load duke parents: diff changeset	578 static int low10( int x ) {
a61af66fc99e Initial load duke parents: diff changeset	579 return x & ((1 << 10) - 1);
a61af66fc99e Initial load duke parents: diff changeset	580 }
a61af66fc99e Initial load duke parents: diff changeset	581
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	582 // AES crypto instructions supported only on certain processors
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	583 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	584
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	585 // instruction only in VIS1
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	586 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	587
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	588 // instruction only in VIS3
faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	589 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	590
0 a61af66fc99e Initial load duke parents: diff changeset	591 // instruction only in v9
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	592 static void v9_only() { } // do nothing
0 a61af66fc99e Initial load duke parents: diff changeset	593
a61af66fc99e Initial load duke parents: diff changeset	594 // instruction deprecated in v9
a61af66fc99e Initial load duke parents: diff changeset	595 static void v9_dep() { } // do nothing for now
a61af66fc99e Initial load duke parents: diff changeset	596
a61af66fc99e Initial load duke parents: diff changeset	597 // v8 has no CC field
a61af66fc99e Initial load duke parents: diff changeset	598 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
a61af66fc99e Initial load duke parents: diff changeset	599
a61af66fc99e Initial load duke parents: diff changeset	600 protected:
a61af66fc99e Initial load duke parents: diff changeset	601 // Simple delay-slot scheme:
a61af66fc99e Initial load duke parents: diff changeset	602 // In order to check the programmer, the assembler keeps track of deley slots.
a61af66fc99e Initial load duke parents: diff changeset	603 // It forbids CTIs in delay slots (conservative, but should be OK).
a61af66fc99e Initial load duke parents: diff changeset	604 // Also, when putting an instruction into a delay slot, you must say
a61af66fc99e Initial load duke parents: diff changeset	605 // asm->delayed()->add(...), in order to check that you don't omit
a61af66fc99e Initial load duke parents: diff changeset	606 // delay-slot instructions.
a61af66fc99e Initial load duke parents: diff changeset	607 // To implement this, we use a simple FSA
a61af66fc99e Initial load duke parents: diff changeset	608
a61af66fc99e Initial load duke parents: diff changeset	609 #ifdef ASSERT
a61af66fc99e Initial load duke parents: diff changeset	610 #define CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	611 #endif
a61af66fc99e Initial load duke parents: diff changeset	612 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	613 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
a61af66fc99e Initial load duke parents: diff changeset	614 #endif
a61af66fc99e Initial load duke parents: diff changeset	615
a61af66fc99e Initial load duke parents: diff changeset	616 public:
a61af66fc99e Initial load duke parents: diff changeset	617 // Tells assembler next instruction must NOT be in delay slot.
a61af66fc99e Initial load duke parents: diff changeset	618 // Use at start of multinstruction macros.
a61af66fc99e Initial load duke parents: diff changeset	619 void assert_not_delayed() {
a61af66fc99e Initial load duke parents: diff changeset	620 // This is a separate overloading to avoid creation of string constants
a61af66fc99e Initial load duke parents: diff changeset	621 // in non-asserted code--with some compilers this pollutes the object code.
a61af66fc99e Initial load duke parents: diff changeset	622 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	623 assert_not_delayed("next instruction should not be a delay slot");
a61af66fc99e Initial load duke parents: diff changeset	624 #endif
a61af66fc99e Initial load duke parents: diff changeset	625 }
a61af66fc99e Initial load duke parents: diff changeset	626 void assert_not_delayed(const char* msg) {
a61af66fc99e Initial load duke parents: diff changeset	627 #ifdef CHECK_DELAY
1490 f03d0a26bf83 6888954: argument formatting for assert() and friends jcoomes parents: 1006 diff changeset	628 assert(delay_state == no_delay, msg);
0 a61af66fc99e Initial load duke parents: diff changeset	629 #endif
a61af66fc99e Initial load duke parents: diff changeset	630 }
a61af66fc99e Initial load duke parents: diff changeset	631
a61af66fc99e Initial load duke parents: diff changeset	632 protected:
17877 17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	633 // Insert a nop if the previous is cbcond
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	634 void insert_nop_after_cbcond() {
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	635 if (UseCBCond && cbcond_before()) {
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	636 nop();
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	637 }
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	638 }
0 a61af66fc99e Initial load duke parents: diff changeset	639 // Delay slot helpers
a61af66fc99e Initial load duke parents: diff changeset	640 // cti is called when emitting control-transfer instruction,
a61af66fc99e Initial load duke parents: diff changeset	641 // BEFORE doing the emitting.
a61af66fc99e Initial load duke parents: diff changeset	642 // Only effective when assertion-checking is enabled.
a61af66fc99e Initial load duke parents: diff changeset	643 void cti() {
17877 17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	644 // A cbcond instruction immediately followed by a CTI
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	645 // instruction introduces pipeline stalls, we need to avoid that.
17b2fbdb6637 8038297: Avoid placing CTI immediately following cbcond instruction on T4 iveresov parents: 17670 diff changeset	646 no_cbcond_before();
0 a61af66fc99e Initial load duke parents: diff changeset	647 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	648 assert_not_delayed("cti should not be in delay slot");
a61af66fc99e Initial load duke parents: diff changeset	649 #endif
a61af66fc99e Initial load duke parents: diff changeset	650 }
a61af66fc99e Initial load duke parents: diff changeset	651
a61af66fc99e Initial load duke parents: diff changeset	652 // called when emitting cti with a delay slot, AFTER emitting
a61af66fc99e Initial load duke parents: diff changeset	653 void has_delay_slot() {
a61af66fc99e Initial load duke parents: diff changeset	654 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	655 assert_not_delayed("just checking");
a61af66fc99e Initial load duke parents: diff changeset	656 delay_state = at_delay_slot;
a61af66fc99e Initial load duke parents: diff changeset	657 #endif
a61af66fc99e Initial load duke parents: diff changeset	658 }
a61af66fc99e Initial load duke parents: diff changeset	659
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	660 // cbcond instruction should not be generated one after an other
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	661 bool cbcond_before() {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	662 if (offset() == 0) return false; // it is first instruction
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	663 int x = (int)(intptr_t(pc()) - 4); // previous instruction
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	664 return is_cbcond(x);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	665 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	666
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	667 void no_cbcond_before() {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	668 assert(offset() == 0 \|\| !cbcond_before(), "cbcond should not follow an other cbcond");
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	669 }
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	670 public:
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	671
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	672 bool use_cbcond(Label& L) {
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	673 if (!UseCBCond \|\| cbcond_before()) return false;
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	674 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	675 assert( (x & 3) == 0, "not word aligned");
4114 6729bbc1fcd6 7003454: order constants in constant table by number of references in code twisti parents: 3910 diff changeset	676 return is_simm12(x);
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	677 }
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	678
0 a61af66fc99e Initial load duke parents: diff changeset	679 // Tells assembler you know that next instruction is delayed
a61af66fc99e Initial load duke parents: diff changeset	680 Assembler* delayed() {
a61af66fc99e Initial load duke parents: diff changeset	681 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	682 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
a61af66fc99e Initial load duke parents: diff changeset	683 delay_state = filling_delay_slot;
a61af66fc99e Initial load duke parents: diff changeset	684 #endif
a61af66fc99e Initial load duke parents: diff changeset	685 return this;
a61af66fc99e Initial load duke parents: diff changeset	686 }
a61af66fc99e Initial load duke parents: diff changeset	687
a61af66fc99e Initial load duke parents: diff changeset	688 void flush() {
a61af66fc99e Initial load duke parents: diff changeset	689 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	690 assert ( delay_state == no_delay, "ending code with a delay slot");
a61af66fc99e Initial load duke parents: diff changeset	691 #endif
a61af66fc99e Initial load duke parents: diff changeset	692 AbstractAssembler::flush();
a61af66fc99e Initial load duke parents: diff changeset	693 }
a61af66fc99e Initial load duke parents: diff changeset	694
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	695 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	696 inline void emit_data(int x) { emit_int32(x); }
0 a61af66fc99e Initial load duke parents: diff changeset	697 inline void emit_data(int, RelocationHolder const&);
a61af66fc99e Initial load duke parents: diff changeset	698 inline void emit_data(int, relocInfo::relocType rtype);
a61af66fc99e Initial load duke parents: diff changeset	699 // helper for above fcns
a61af66fc99e Initial load duke parents: diff changeset	700 inline void check_delay();
a61af66fc99e Initial load duke parents: diff changeset	701
a61af66fc99e Initial load duke parents: diff changeset	702
a61af66fc99e Initial load duke parents: diff changeset	703 public:
a61af66fc99e Initial load duke parents: diff changeset	704 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
a61af66fc99e Initial load duke parents: diff changeset	705
a61af66fc99e Initial load duke parents: diff changeset	706 // pp 135 (addc was addx in v8)
a61af66fc99e Initial load duke parents: diff changeset	707
727 6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC twisti parents: 710 diff changeset	708 inline void add(Register s1, Register s2, Register d );
7204 f0c2369fda5a 8003250: SPARC: move MacroAssembler into separate file twisti parents: 6848 diff changeset	709 inline void add(Register s1, int simm13a, Register d );
0 a61af66fc99e Initial load duke parents: diff changeset	710
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	711 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(add_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	712 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(add_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	713 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(addc_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	714 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(addc_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	715 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(addc_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	716 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(addc_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	717
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	718
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	719 // 4-operand AES instructions
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	720
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	721 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_eround01_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	722 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_eround23_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	723 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_dround01_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	724 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_dround23_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	725 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_eround01_l_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	726 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_eround23_l_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	727 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_dround01_l_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	728 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| fs3(s3, FloatRegisterImpl::D) \| op5(aes_dround23_l_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	729 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes4_op3) \| fs1(s1, FloatRegisterImpl::D) \| u_field(imm5a, 13, 9) \| op5(aes_kexpand1_op5) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	730
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	731
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	732 // 3-operand AES instructions
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	733
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	734 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes3_op3) \| fs1(s1, FloatRegisterImpl::D) \| opf(aes_kexpand0_opf) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	735 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(aes3_op3) \| fs1(s1, FloatRegisterImpl::D) \| opf(aes_kexpand2_opf) \| fs2(s2, FloatRegisterImpl::D) ); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	736
0 a61af66fc99e Initial load duke parents: diff changeset	737 // pp 136
a61af66fc99e Initial load duke parents: diff changeset	738
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	739 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	740 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
0 a61af66fc99e Initial load duke parents: diff changeset	741
3851 95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	742 // compare and branch
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	743 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	744 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
95134e034042 7063629: use cbcond in C2 generated code on T4 kvn parents: 3839 diff changeset	745
0 a61af66fc99e Initial load duke parents: diff changeset	746 protected: // use MacroAssembler::br instead
a61af66fc99e Initial load duke parents: diff changeset	747
a61af66fc99e Initial load duke parents: diff changeset	748 // pp 138
a61af66fc99e Initial load duke parents: diff changeset	749
a61af66fc99e Initial load duke parents: diff changeset	750 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
a61af66fc99e Initial load duke parents: diff changeset	751 inline void fb( Condition c, bool a, Label& L );
a61af66fc99e Initial load duke parents: diff changeset	752
a61af66fc99e Initial load duke parents: diff changeset	753 // pp 141
a61af66fc99e Initial load duke parents: diff changeset	754
a61af66fc99e Initial load duke parents: diff changeset	755 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
a61af66fc99e Initial load duke parents: diff changeset	756 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
a61af66fc99e Initial load duke parents: diff changeset	757
a61af66fc99e Initial load duke parents: diff changeset	758 // pp 144
a61af66fc99e Initial load duke parents: diff changeset	759
a61af66fc99e Initial load duke parents: diff changeset	760 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
a61af66fc99e Initial load duke parents: diff changeset	761 inline void br( Condition c, bool a, Label& L );
a61af66fc99e Initial load duke parents: diff changeset	762
a61af66fc99e Initial load duke parents: diff changeset	763 // pp 146
a61af66fc99e Initial load duke parents: diff changeset	764
a61af66fc99e Initial load duke parents: diff changeset	765 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
a61af66fc99e Initial load duke parents: diff changeset	766 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
a61af66fc99e Initial load duke parents: diff changeset	767
a61af66fc99e Initial load duke parents: diff changeset	768 // pp 149
a61af66fc99e Initial load duke parents: diff changeset	769
a61af66fc99e Initial load duke parents: diff changeset	770 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
a61af66fc99e Initial load duke parents: diff changeset	771 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
a61af66fc99e Initial load duke parents: diff changeset	772
3839 3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	773 public:
3d42f82cd811 7063628: Use cbcond on T4 kvn parents: 3804 diff changeset	774
0 a61af66fc99e Initial load duke parents: diff changeset	775 // pp 150
a61af66fc99e Initial load duke parents: diff changeset	776
a61af66fc99e Initial load duke parents: diff changeset	777 // These instructions compare the contents of s2 with the contents of
a61af66fc99e Initial load duke parents: diff changeset	778 // memory at address in s1. If the values are equal, the contents of memory
a61af66fc99e Initial load duke parents: diff changeset	779 // at address s1 is swapped with the data in d. If the values are not equal,
a61af66fc99e Initial load duke parents: diff changeset	780 // the the contents of memory at s1 is loaded into d, without the swap.
a61af66fc99e Initial load duke parents: diff changeset	781
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	782 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(casa_op3 ) \| rs1(s1) \| (ia == -1 ? immed(true) : imm_asi(ia)) \| rs2(s2)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	783 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(casxa_op3) \| rs1(s1) \| (ia == -1 ? immed(true) : imm_asi(ia)) \| rs2(s2)); }
0 a61af66fc99e Initial load duke parents: diff changeset	784
a61af66fc99e Initial load duke parents: diff changeset	785 // pp 152
a61af66fc99e Initial load duke parents: diff changeset	786
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	787 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(udiv_op3 ) \| rs1(s1) \| rs2(s2)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	788 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(udiv_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	789 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sdiv_op3 ) \| rs1(s1) \| rs2(s2)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	790 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sdiv_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	791 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(udiv_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	792 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(udiv_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	793 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sdiv_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	794 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sdiv_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	795
a61af66fc99e Initial load duke parents: diff changeset	796 // pp 155
a61af66fc99e Initial load duke parents: diff changeset	797
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	798 void done() { v9_only(); cti(); emit_int32( op(arith_op) \| fcn(0) \| op3(done_op3) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	799 void retry() { v9_only(); cti(); emit_int32( op(arith_op) \| fcn(1) \| op3(retry_op3) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	800
a61af66fc99e Initial load duke parents: diff changeset	801 // pp 156
a61af66fc99e Initial load duke parents: diff changeset	802
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	803 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| fs1(s1, w) \| opf(0x40 + w) \| fs2(s2, w)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	804 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| fs1(s1, w) \| opf(0x44 + w) \| fs2(s2, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	805
a61af66fc99e Initial load duke parents: diff changeset	806 // pp 157
a61af66fc99e Initial load duke parents: diff changeset	807
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	808 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) \| cmpcc(cc) \| op3(fpop2_op3) \| fs1(s1, w) \| opf(0x50 + w) \| fs2(s2, w)); }
46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	809 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) \| cmpcc(cc) \| op3(fpop2_op3) \| fs1(s1, w) \| opf(0x54 + w) \| fs2(s2, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	810
a61af66fc99e Initial load duke parents: diff changeset	811 // pp 159
a61af66fc99e Initial load duke parents: diff changeset	812
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	813 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(fpop1_op3) \| opf(0x80 + w) \| fs2(s, w)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	814 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::S) \| op3(fpop1_op3) \| opf(0xd0 + w) \| fs2(s, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	815
a61af66fc99e Initial load duke parents: diff changeset	816 // pp 160
a61af66fc99e Initial load duke parents: diff changeset	817
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	818 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, dw) \| op3(fpop1_op3) \| opf(0xc0 + sw + dw*4) \| fs2(s, sw)); }
0 a61af66fc99e Initial load duke parents: diff changeset	819
a61af66fc99e Initial load duke parents: diff changeset	820 // pp 161
a61af66fc99e Initial load duke parents: diff changeset	821
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	822 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0x80 + w*4) \| fs2(s, FloatRegisterImpl::D)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	823 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0xc0 + w*4) \| fs2(s, FloatRegisterImpl::S)); }
0 a61af66fc99e Initial load duke parents: diff changeset	824
a61af66fc99e Initial load duke parents: diff changeset	825 // pp 162
a61af66fc99e Initial load duke parents: diff changeset	826
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	827 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0x00 + w) \| fs2(s, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	828
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	829 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0x04 + w) \| fs2(s, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	830
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	831 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0x08 + w) \| fs2(s, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	832
a61af66fc99e Initial load duke parents: diff changeset	833 // pp 163
a61af66fc99e Initial load duke parents: diff changeset	834
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	835 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| fs1(s1, w) \| opf(0x48 + w) \| fs2(s2, w)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	836 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, dw) \| op3(fpop1_op3) \| fs1(s1, sw) \| opf(0x60 + sw + dw*4) \| fs2(s2, sw)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	837 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| fs1(s1, w) \| opf(0x4c + w) \| fs2(s2, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	838
17670 04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	839 // FXORs/FXORd instructions
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	840
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	841 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) \| fd(d, w) \| op3(flog3_op3) \| fs1(s1, w) \| opf(0x6E - w) \| fs2(s2, w)); }
04d32e7fad07 8002074: Support for AES on SPARC kvn parents: 17467 diff changeset	842
0 a61af66fc99e Initial load duke parents: diff changeset	843 // pp 164
a61af66fc99e Initial load duke parents: diff changeset	844
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	845 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop1_op3) \| opf(0x28 + w) \| fs2(s, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	846
a61af66fc99e Initial load duke parents: diff changeset	847 // pp 165
a61af66fc99e Initial load duke parents: diff changeset	848
a61af66fc99e Initial load duke parents: diff changeset	849 inline void flush( Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	850 inline void flush( Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	851
a61af66fc99e Initial load duke parents: diff changeset	852 // pp 167
a61af66fc99e Initial load duke parents: diff changeset	853
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	854 void flushw() { v9_only(); emit_int32( op(arith_op) \| op3(flushw_op3) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	855
a61af66fc99e Initial load duke parents: diff changeset	856 // pp 168
a61af66fc99e Initial load duke parents: diff changeset	857
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	858 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) \| u_field(const22a, 21, 0) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	859 // v8 unimp == illtrap(0)
a61af66fc99e Initial load duke parents: diff changeset	860
a61af66fc99e Initial load duke parents: diff changeset	861 // pp 169
a61af66fc99e Initial load duke parents: diff changeset	862
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	863 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) \| fcn(id1) \| op3(impdep1_op3) \| u_field(const19a, 18, 0)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	864 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) \| fcn(id1) \| op3(impdep2_op3) \| u_field(const19a, 18, 0)); }
0 a61af66fc99e Initial load duke parents: diff changeset	865
a61af66fc99e Initial load duke parents: diff changeset	866 // pp 170
a61af66fc99e Initial load duke parents: diff changeset	867
a61af66fc99e Initial load duke parents: diff changeset	868 void jmpl( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	869 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
a61af66fc99e Initial load duke parents: diff changeset	870
a61af66fc99e Initial load duke parents: diff changeset	871 // 171
a61af66fc99e Initial load duke parents: diff changeset	872
727 6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC twisti parents: 710 diff changeset	873 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC twisti parents: 710 diff changeset	874 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
6b2273dd6fa9 6822110: Add AddressLiteral class on SPARC twisti parents: 710 diff changeset	875
0 a61af66fc99e Initial load duke parents: diff changeset	876
a61af66fc99e Initial load duke parents: diff changeset	877 inline void ldfsr( Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	878 inline void ldfsr( Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	879 inline void ldxfsr( Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	880 inline void ldxfsr( Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	881
a61af66fc99e Initial load duke parents: diff changeset	882 // 173
a61af66fc99e Initial load duke parents: diff changeset	883
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	884 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) \| fd(d, w) \| alt_op3(ldf_op3 \| alt_bit_op3, w) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	885 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) \| fd(d, w) \| alt_op3(ldf_op3 \| alt_bit_op3, w) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	886
a61af66fc99e Initial load duke parents: diff changeset	887 // pp 175, lduw is ld on v8
a61af66fc99e Initial load duke parents: diff changeset	888
a61af66fc99e Initial load duke parents: diff changeset	889 inline void ldsb( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	890 inline void ldsb( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	891 inline void ldsh( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	892 inline void ldsh( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	893 inline void ldsw( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	894 inline void ldsw( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	895 inline void ldub( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	896 inline void ldub( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	897 inline void lduh( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	898 inline void lduh( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	899 inline void lduw( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	900 inline void lduw( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	901 inline void ldx( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	902 inline void ldx( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	903 inline void ldd( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	904 inline void ldd( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	905
a61af66fc99e Initial load duke parents: diff changeset	906 // pp 177
a61af66fc99e Initial load duke parents: diff changeset	907
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	908 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldsb_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	909 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldsb_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	910 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldsh_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	911 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldsh_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	912 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(ldsw_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	913 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(ldsw_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	914 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldub_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	915 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(ldub_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	916 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(lduh_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	917 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(lduh_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	918 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(lduw_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	919 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) \| rd(d) \| op3(lduw_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	920 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(ldx_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	921 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(ldx_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	922
a61af66fc99e Initial load duke parents: diff changeset	923 // pp 181
a61af66fc99e Initial load duke parents: diff changeset	924
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	925 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(and_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	926 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(and_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	927 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(and_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	928 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(and_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	929 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(andn_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	930 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(andn_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	931 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(andn_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	932 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(andn_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	933 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(or_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	934 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(or_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	935 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(or_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	936 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(or_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	937 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(orn_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	938 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(orn_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	939 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(orn_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	940 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(orn_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	941 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xor_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	942 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xor_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	943 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xor_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	944 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xor_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	945 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xnor_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	946 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xnor_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	947 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xnor_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	948 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(xnor_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	949
a61af66fc99e Initial load duke parents: diff changeset	950 // pp 183
a61af66fc99e Initial load duke parents: diff changeset	951
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	952 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) \| op3(membar_op3) \| rs1(O7) \| immed(true) \| u_field( int(const7a), 6, 0)); }
0 a61af66fc99e Initial load duke parents: diff changeset	953
a61af66fc99e Initial load duke parents: diff changeset	954 // pp 185
a61af66fc99e Initial load duke parents: diff changeset	955
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	956 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop2_op3) \| cond_mov(c) \| opf_cc(cca, floatCC) \| opf_low6(w) \| fs2(s2, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	957
a61af66fc99e Initial load duke parents: diff changeset	958 // pp 189
a61af66fc99e Initial load duke parents: diff changeset	959
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	960 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) \| fd(d, w) \| op3(fpop2_op3) \| rs1(s1) \| rcond(c) \| opf_low5(4 + w) \| fs2(s2, w)); }
0 a61af66fc99e Initial load duke parents: diff changeset	961
a61af66fc99e Initial load duke parents: diff changeset	962 // pp 191
a61af66fc99e Initial load duke parents: diff changeset	963
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	964 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(movcc_op3) \| mov_cc(cca, floatCC) \| cond_mov(c) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	965 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(movcc_op3) \| mov_cc(cca, floatCC) \| cond_mov(c) \| immed(true) \| simm(simm11a, 11) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	966
a61af66fc99e Initial load duke parents: diff changeset	967 // pp 195
a61af66fc99e Initial load duke parents: diff changeset	968
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	969 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(movr_op3) \| rs1(s1) \| rcond(c) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	970 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(movr_op3) \| rs1(s1) \| rcond(c) \| immed(true) \| simm(simm10a, 10) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	971
a61af66fc99e Initial load duke parents: diff changeset	972 // pp 196
a61af66fc99e Initial load duke parents: diff changeset	973
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	974 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(mulx_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	975 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(mulx_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	976 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sdivx_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	977 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sdivx_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	978 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(udivx_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	979 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(udivx_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	980
a61af66fc99e Initial load duke parents: diff changeset	981 // pp 197
a61af66fc99e Initial load duke parents: diff changeset	982
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	983 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(umul_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	984 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(umul_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	985 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(smul_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	986 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(smul_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	987 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(umul_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	988 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(umul_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	989 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(smul_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	990 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(smul_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	991
a61af66fc99e Initial load duke parents: diff changeset	992 // pp 201
a61af66fc99e Initial load duke parents: diff changeset	993
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	994 void nop() { emit_int32( op(branch_op) \| op2(sethi_op2) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	995
a61af66fc99e Initial load duke parents: diff changeset	996
a61af66fc99e Initial load duke parents: diff changeset	997 // pp 202
a61af66fc99e Initial load duke parents: diff changeset	998
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	999 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(popc_op3) \| rs2(s)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1000 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(popc_op3) \| immed(true) \| simm(simm13a, 13)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1001
a61af66fc99e Initial load duke parents: diff changeset	1002 // pp 203
a61af66fc99e Initial load duke parents: diff changeset	1003
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1004 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) \| fcn(f) \| op3(prefetch_op3) \| rs1(s1) \| rs2(s2) ); }
7204 f0c2369fda5a 8003250: SPARC: move MacroAssembler into separate file twisti parents: 6848 diff changeset	1005 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) \| fcn(f) \| op3(prefetch_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13)); }
f0c2369fda5a 8003250: SPARC: move MacroAssembler into separate file twisti parents: 6848 diff changeset	1006
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1007 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) \| fcn(f) \| op3(prefetch_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1008 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) \| fcn(f) \| op3(prefetch_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1009
a61af66fc99e Initial load duke parents: diff changeset	1010 // pp 208
a61af66fc99e Initial load duke parents: diff changeset	1011
a61af66fc99e Initial load duke parents: diff changeset	1012 // not implementing read privileged register
a61af66fc99e Initial load duke parents: diff changeset	1013
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1014 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(0, 18, 14)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1015 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(2, 18, 14)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1016 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(3, 18, 14)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1017 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(4, 18, 14)); } // Spoon!
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1018 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(5, 18, 14)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1019 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(rdreg_op3) \| u_field(6, 18, 14)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1020
a61af66fc99e Initial load duke parents: diff changeset	1021 // pp 213
a61af66fc99e Initial load duke parents: diff changeset	1022
a61af66fc99e Initial load duke parents: diff changeset	1023 inline void rett( Register s1, Register s2);
a61af66fc99e Initial load duke parents: diff changeset	1024 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
a61af66fc99e Initial load duke parents: diff changeset	1025
a61af66fc99e Initial load duke parents: diff changeset	1026 // pp 214
a61af66fc99e Initial load duke parents: diff changeset	1027
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1028 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(save_op3) \| rs1(s1) \| rs2(s2) ); }
342 37f87013dfd8 6711316: Open source the Garbage-First garbage collector ysr parents: 124 diff changeset	1029 void save( Register s1, int simm13a, Register d ) {
37f87013dfd8 6711316: Open source the Garbage-First garbage collector ysr parents: 124 diff changeset	1030 // make sure frame is at least large enough for the register save area
37f87013dfd8 6711316: Open source the Garbage-First garbage collector ysr parents: 124 diff changeset	1031 assert(-simm13a >= 16 * wordSize, "frame too small");
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1032 emit_int32( op(arith_op) \| rd(d) \| op3(save_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) );
342 37f87013dfd8 6711316: Open source the Garbage-First garbage collector ysr parents: 124 diff changeset	1033 }
0 a61af66fc99e Initial load duke parents: diff changeset	1034
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1035 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) \| rd(d) \| op3(restore_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1036 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(restore_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1037
a61af66fc99e Initial load duke parents: diff changeset	1038 // pp 216
a61af66fc99e Initial load duke parents: diff changeset	1039
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1040 void saved() { v9_only(); emit_int32( op(arith_op) \| fcn(0) \| op3(saved_op3)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1041 void restored() { v9_only(); emit_int32( op(arith_op) \| fcn(1) \| op3(saved_op3)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1042
a61af66fc99e Initial load duke parents: diff changeset	1043 // pp 217
a61af66fc99e Initial load duke parents: diff changeset	1044
a61af66fc99e Initial load duke parents: diff changeset	1045 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
a61af66fc99e Initial load duke parents: diff changeset	1046 // pp 218
a61af66fc99e Initial load duke parents: diff changeset	1047
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1048 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sll_op3) \| rs1(s1) \| sx(0) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1049 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sll_op3) \| rs1(s1) \| sx(0) \| immed(true) \| u_field(imm5a, 4, 0) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1050 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(srl_op3) \| rs1(s1) \| sx(0) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1051 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(srl_op3) \| rs1(s1) \| sx(0) \| immed(true) \| u_field(imm5a, 4, 0) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1052 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sra_op3) \| rs1(s1) \| sx(0) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1053 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sra_op3) \| rs1(s1) \| sx(0) \| immed(true) \| u_field(imm5a, 4, 0) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1054
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1055 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sll_op3) \| rs1(s1) \| sx(1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1056 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sll_op3) \| rs1(s1) \| sx(1) \| immed(true) \| u_field(imm6a, 5, 0) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1057 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(srl_op3) \| rs1(s1) \| sx(1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1058 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(srl_op3) \| rs1(s1) \| sx(1) \| immed(true) \| u_field(imm6a, 5, 0) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1059 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sra_op3) \| rs1(s1) \| sx(1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1060 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) \| rd(d) \| op3(sra_op3) \| rs1(s1) \| sx(1) \| immed(true) \| u_field(imm6a, 5, 0) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1061
a61af66fc99e Initial load duke parents: diff changeset	1062 // pp 220
a61af66fc99e Initial load duke parents: diff changeset	1063
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1064 void sir( int simm13a ) { emit_int32( op(arith_op) \| fcn(15) \| op3(sir_op3) \| immed(true) \| simm(simm13a, 13)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1065
a61af66fc99e Initial load duke parents: diff changeset	1066 // pp 221
a61af66fc99e Initial load duke parents: diff changeset	1067
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1068 void stbar() { emit_int32( op(arith_op) \| op3(membar_op3) \| u_field(15, 18, 14)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1069
a61af66fc99e Initial load duke parents: diff changeset	1070 // pp 222
a61af66fc99e Initial load duke parents: diff changeset	1071
1006 dcf03e02b020 6879902: CTW failure jdk6_18/hotspot/src/cpu/sparc/vm/assembler_sparc.hpp:845 twisti parents: 986 diff changeset	1072 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
0 a61af66fc99e Initial load duke parents: diff changeset	1073 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1074
a61af66fc99e Initial load duke parents: diff changeset	1075 inline void stfsr( Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1076 inline void stfsr( Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1077 inline void stxfsr( Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1078 inline void stxfsr( Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1079
a61af66fc99e Initial load duke parents: diff changeset	1080 // pp 224
a61af66fc99e Initial load duke parents: diff changeset	1081
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1082 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) \| fd(d, w) \| alt_op3(stf_op3 \| alt_bit_op3, w) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1083 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) \| fd(d, w) \| alt_op3(stf_op3 \| alt_bit_op3, w) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1084
a61af66fc99e Initial load duke parents: diff changeset	1085 // p 226
a61af66fc99e Initial load duke parents: diff changeset	1086
a61af66fc99e Initial load duke parents: diff changeset	1087 inline void stb( Register d, Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1088 inline void stb( Register d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1089 inline void sth( Register d, Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1090 inline void sth( Register d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1091 inline void stw( Register d, Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1092 inline void stw( Register d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1093 inline void stx( Register d, Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1094 inline void stx( Register d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1095 inline void std( Register d, Register s1, Register s2 );
a61af66fc99e Initial load duke parents: diff changeset	1096 inline void std( Register d, Register s1, int simm13a);
a61af66fc99e Initial load duke parents: diff changeset	1097
a61af66fc99e Initial load duke parents: diff changeset	1098 // pp 177
a61af66fc99e Initial load duke parents: diff changeset	1099
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1100 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) \| rd(d) \| op3(stb_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1101 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) \| rd(d) \| op3(stb_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1102 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) \| rd(d) \| op3(sth_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1103 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) \| rd(d) \| op3(sth_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1104 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) \| rd(d) \| op3(stw_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1105 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) \| rd(d) \| op3(stw_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1106 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(stx_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1107 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) \| rd(d) \| op3(stx_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1108 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) \| rd(d) \| op3(std_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1109 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) \| rd(d) \| op3(std_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1110
a61af66fc99e Initial load duke parents: diff changeset	1111 // pp 230
a61af66fc99e Initial load duke parents: diff changeset	1112
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1113 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sub_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1114 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sub_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 2002 diff changeset	1115
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1116 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sub_op3 \| cc_bit_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1117 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(sub_op3 \| cc_bit_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1118 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(subc_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1119 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(subc_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1120 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(subc_op3 \| cc_bit_op3) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1121 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(subc_op3 \| cc_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1122
a61af66fc99e Initial load duke parents: diff changeset	1123 // pp 231
a61af66fc99e Initial load duke parents: diff changeset	1124
a61af66fc99e Initial load duke parents: diff changeset	1125 inline void swap( Register s1, Register s2, Register d );
a61af66fc99e Initial load duke parents: diff changeset	1126 inline void swap( Register s1, int simm13a, Register d);
a61af66fc99e Initial load duke parents: diff changeset	1127
a61af66fc99e Initial load duke parents: diff changeset	1128 // pp 232
a61af66fc99e Initial load duke parents: diff changeset	1129
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1130 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) \| rd(d) \| op3(swap_op3 \| alt_bit_op3) \| rs1(s1) \| imm_asi(ia) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1131 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) \| rd(d) \| op3(swap_op3 \| alt_bit_op3) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1132
a61af66fc99e Initial load duke parents: diff changeset	1133 // pp 234, note op in book is wrong, see pp 268
a61af66fc99e Initial load duke parents: diff changeset	1134
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1135 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(taddcc_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1136 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(taddcc_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1137
a61af66fc99e Initial load duke parents: diff changeset	1138 // pp 235
a61af66fc99e Initial load duke parents: diff changeset	1139
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1140 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(tsubcc_op3 ) \| rs1(s1) \| rs2(s2) ); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1141 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) \| rd(d) \| op3(tsubcc_op3 ) \| rs1(s1) \| immed(true) \| simm(simm13a, 13) ); }
0 a61af66fc99e Initial load duke parents: diff changeset	1142
a61af66fc99e Initial load duke parents: diff changeset	1143 // pp 237
a61af66fc99e Initial load duke parents: diff changeset	1144
10997 46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	1145 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) \| cond(c) \| op3(trap_op3) \| rs1(s1) \| trapcc(cc) \| rs2(s2)); }
46c544b8fbfc 8008407: remove SPARC V8 support morris parents: 7476 diff changeset	1146 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) \| cond(c) \| op3(trap_op3) \| rs1(s1) \| trapcc(cc) \| immed(true) \| u_field(trapa, 6, 0)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1147 // simple uncond. trap
a61af66fc99e Initial load duke parents: diff changeset	1148 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
a61af66fc99e Initial load duke parents: diff changeset	1149
a61af66fc99e Initial load duke parents: diff changeset	1150 // pp 239 omit write priv register for now
a61af66fc99e Initial load duke parents: diff changeset	1151
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1152 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) \| rs1(d) \| op3(wrreg_op3) \| u_field(0, 29, 25)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1153 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) \| rs1(s) \| op3(wrreg_op3) \| u_field(2, 29, 25)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1154 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) \|
0 a61af66fc99e Initial load duke parents: diff changeset	1155 rs1(s) \|
a61af66fc99e Initial load duke parents: diff changeset	1156 op3(wrreg_op3) \|
a61af66fc99e Initial load duke parents: diff changeset	1157 u_field(2, 29, 25) \|
3892 baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	1158 immed(true) \|
0 a61af66fc99e Initial load duke parents: diff changeset	1159 simm(simm13a, 13)); }
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1160 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) \| rs1(d) \| op3(wrreg_op3) \| u_field(3, 29, 25)); }
3892 baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	1161 // wrasi(d, imm) stores (d xor imm) to asi
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1162 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) \| rs1(d) \| op3(wrreg_op3) \|
3892 baf763f388e6 7059037: Use BIS for zeroing on T4 kvn parents: 3854 diff changeset	1163 u_field(3, 29, 25) \| immed(true) \| simm(simm13a, 13)); }
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1164 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) \| rs1(d) \| op3(wrreg_op3) \| u_field(6, 29, 25)); }
0 a61af66fc99e Initial load duke parents: diff changeset	1165
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	1166
faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	1167 // VIS3 instructions
faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	1168
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1169 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) \| rd(d) \| op3(mftoi_op3) \| opf(mstosw_opf) \| fs2(s, FloatRegisterImpl::S)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1170 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) \| rd(d) \| op3(mftoi_op3) \| opf(mstouw_opf) \| fs2(s, FloatRegisterImpl::S)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1171 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) \| rd(d) \| op3(mftoi_op3) \| opf(mdtox_opf) \| fs2(s, FloatRegisterImpl::D)); }
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	1172
7476 ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1173 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::S) \| op3(mftoi_op3) \| opf(mwtos_opf) \| rs2(s)); }
ffa87474d7a4 8004537: replace AbstractAssembler emit_long with emit_int32 twisti parents: 7204 diff changeset	1174 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) \| fd(d, FloatRegisterImpl::D) \| op3(mftoi_op3) \| opf(mxtod_opf) \| rs2(s)); }
3804 faa472957b38 7059034: Use movxtod/movdtox on T4 kvn parents: 3753 diff changeset	1175
0 a61af66fc99e Initial load duke parents: diff changeset	1176 // Creation
a61af66fc99e Initial load duke parents: diff changeset	1177 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
a61af66fc99e Initial load duke parents: diff changeset	1178 #ifdef CHECK_DELAY
a61af66fc99e Initial load duke parents: diff changeset	1179 delay_state = no_delay;
a61af66fc99e Initial load duke parents: diff changeset	1180 #endif
a61af66fc99e Initial load duke parents: diff changeset	1181 }
a61af66fc99e Initial load duke parents: diff changeset	1182 };
a61af66fc99e Initial load duke parents: diff changeset	1183
1972 f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1911 diff changeset	1184 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP

Mercurial > hg > truffle

annotate src/cpu/sparc/vm/assembler_sparc.hpp @ 17877:17b2fbdb6637