Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 17877:17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
Summary: Insert a nop between cbcond and CTI
Reviewed-by: kvn, twisti
author | iveresov |
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date | Thu, 10 Apr 2014 23:15:13 -0700 |
parents | 0118c8c7b80f |
children | 1eba0601f0dd |
rev | line source |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.hpp" |
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27 #include "asm/macroAssembler.inline.hpp" |
1972 | 28 #include "memory/resourceArea.hpp" |
29 #include "runtime/java.hpp" | |
30 #include "runtime/stubCodeGenerator.hpp" | |
31 #include "vm_version_x86.hpp" | |
32 #ifdef TARGET_OS_FAMILY_linux | |
33 # include "os_linux.inline.hpp" | |
34 #endif | |
35 #ifdef TARGET_OS_FAMILY_solaris | |
36 # include "os_solaris.inline.hpp" | |
37 #endif | |
38 #ifdef TARGET_OS_FAMILY_windows | |
39 # include "os_windows.inline.hpp" | |
40 #endif | |
3960 | 41 #ifdef TARGET_OS_FAMILY_bsd |
42 # include "os_bsd.inline.hpp" | |
43 #endif | |
585 | 44 |
45 | |
46 int VM_Version::_cpu; | |
47 int VM_Version::_model; | |
48 int VM_Version::_stepping; | |
49 int VM_Version::_cpuFeatures; | |
50 const char* VM_Version::_features_str = ""; | |
51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
52 | |
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53 // Address of instruction which causes SEGV |
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54 address VM_Version::_cpuinfo_segv_addr = 0; |
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55 // Address of instruction after the one which causes SEGV |
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56 address VM_Version::_cpuinfo_cont_addr = 0; |
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57 |
585 | 58 static BufferBlob* stub_blob; |
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59 static const int stub_size = 600; |
585 | 60 |
61 extern "C" { | |
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62 typedef void (*get_cpu_info_stub_t)(void*); |
585 | 63 } |
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64 static get_cpu_info_stub_t get_cpu_info_stub = NULL; |
585 | 65 |
66 | |
67 class VM_Version_StubGenerator: public StubCodeGenerator { | |
68 public: | |
69 | |
70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
71 | |
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72 address generate_get_cpu_info() { |
585 | 73 // Flags to test CPU type. |
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74 const uint32_t HS_EFL_AC = 0x40000; |
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75 const uint32_t HS_EFL_ID = 0x200000; |
585 | 76 // Values for when we don't have a CPUID instruction. |
77 const int CPU_FAMILY_SHIFT = 8; | |
78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
80 | |
1622 | 81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
4771 | 82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
585 | 83 |
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84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); |
585 | 85 # define __ _masm-> |
86 | |
87 address start = __ pc(); | |
88 | |
89 // | |
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90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); |
585 | 91 // |
92 // LP64: rcx and rdx are first and second argument registers on windows | |
93 | |
94 __ push(rbp); | |
95 #ifdef _LP64 | |
96 __ mov(rbp, c_rarg0); // cpuid_info address | |
97 #else | |
98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
99 #endif | |
100 __ push(rbx); | |
101 __ push(rsi); | |
102 __ pushf(); // preserve rbx, and flags | |
103 __ pop(rax); | |
104 __ push(rax); | |
105 __ mov(rcx, rax); | |
106 // | |
107 // if we are unable to change the AC flag, we have a 386 | |
108 // | |
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109 __ xorl(rax, HS_EFL_AC); |
585 | 110 __ push(rax); |
111 __ popf(); | |
112 __ pushf(); | |
113 __ pop(rax); | |
114 __ cmpptr(rax, rcx); | |
115 __ jccb(Assembler::notEqual, detect_486); | |
116 | |
117 __ movl(rax, CPU_FAMILY_386); | |
118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
119 __ jmp(done); | |
120 | |
121 // | |
122 // If we are unable to change the ID flag, we have a 486 which does | |
123 // not support the "cpuid" instruction. | |
124 // | |
125 __ bind(detect_486); | |
126 __ mov(rax, rcx); | |
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127 __ xorl(rax, HS_EFL_ID); |
585 | 128 __ push(rax); |
129 __ popf(); | |
130 __ pushf(); | |
131 __ pop(rax); | |
132 __ cmpptr(rcx, rax); | |
133 __ jccb(Assembler::notEqual, detect_586); | |
134 | |
135 __ bind(cpu486); | |
136 __ movl(rax, CPU_FAMILY_486); | |
137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
138 __ jmp(done); | |
139 | |
140 // | |
141 // At this point, we have a chip which supports the "cpuid" instruction | |
142 // | |
143 __ bind(detect_586); | |
144 __ xorl(rax, rax); | |
145 __ cpuid(); | |
146 __ orl(rax, rax); | |
147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
148 // value of at least 1, we give up and | |
149 // assume a 486 | |
150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
151 __ movl(Address(rsi, 0), rax); | |
152 __ movl(Address(rsi, 4), rbx); | |
153 __ movl(Address(rsi, 8), rcx); | |
154 __ movl(Address(rsi,12), rdx); | |
155 | |
1622 | 156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
157 __ jccb(Assembler::belowEqual, std_cpuid4); | |
158 | |
159 // | |
160 // cpuid(0xB) Processor Topology | |
161 // | |
162 __ movl(rax, 0xb); | |
163 __ xorl(rcx, rcx); // Threads level | |
164 __ cpuid(); | |
165 | |
166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
167 __ movl(Address(rsi, 0), rax); | |
168 __ movl(Address(rsi, 4), rbx); | |
169 __ movl(Address(rsi, 8), rcx); | |
170 __ movl(Address(rsi,12), rdx); | |
171 | |
172 __ movl(rax, 0xb); | |
173 __ movl(rcx, 1); // Cores level | |
174 __ cpuid(); | |
175 __ push(rax); | |
176 __ andl(rax, 0x1f); // Determine if valid topology level | |
177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
178 __ andl(rax, 0xffff); | |
179 __ pop(rax); | |
180 __ jccb(Assembler::equal, std_cpuid4); | |
181 | |
182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
183 __ movl(Address(rsi, 0), rax); | |
184 __ movl(Address(rsi, 4), rbx); | |
185 __ movl(Address(rsi, 8), rcx); | |
186 __ movl(Address(rsi,12), rdx); | |
187 | |
188 __ movl(rax, 0xb); | |
189 __ movl(rcx, 2); // Packages level | |
190 __ cpuid(); | |
191 __ push(rax); | |
192 __ andl(rax, 0x1f); // Determine if valid topology level | |
193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
194 __ andl(rax, 0xffff); | |
195 __ pop(rax); | |
196 __ jccb(Assembler::equal, std_cpuid4); | |
197 | |
198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
199 __ movl(Address(rsi, 0), rax); | |
200 __ movl(Address(rsi, 4), rbx); | |
201 __ movl(Address(rsi, 8), rcx); | |
202 __ movl(Address(rsi,12), rdx); | |
585 | 203 |
204 // | |
205 // cpuid(0x4) Deterministic cache params | |
206 // | |
1622 | 207 __ bind(std_cpuid4); |
585 | 208 __ movl(rax, 4); |
1622 | 209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
210 __ jccb(Assembler::greater, std_cpuid1); | |
211 | |
585 | 212 __ xorl(rcx, rcx); // L1 cache |
213 __ cpuid(); | |
214 __ push(rax); | |
215 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
217 __ pop(rax); | |
218 __ jccb(Assembler::equal, std_cpuid1); | |
219 | |
220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
221 __ movl(Address(rsi, 0), rax); | |
222 __ movl(Address(rsi, 4), rbx); | |
223 __ movl(Address(rsi, 8), rcx); | |
224 __ movl(Address(rsi,12), rdx); | |
225 | |
226 // | |
227 // Standard cpuid(0x1) | |
228 // | |
229 __ bind(std_cpuid1); | |
230 __ movl(rax, 1); | |
231 __ cpuid(); | |
232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
233 __ movl(Address(rsi, 0), rax); | |
234 __ movl(Address(rsi, 4), rbx); | |
235 __ movl(Address(rsi, 8), rcx); | |
236 __ movl(Address(rsi,12), rdx); | |
237 | |
4759 | 238 // |
239 // Check if OS has enabled XGETBV instruction to access XCR0 | |
240 // (OSXSAVE feature flag) and CPU supports AVX | |
241 // | |
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242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
4759 | 243 __ cmpl(rcx, 0x18000000); |
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244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
4759 | 245 |
246 // | |
247 // XCR0, XFEATURE_ENABLED_MASK register | |
248 // | |
249 __ xorl(rcx, rcx); // zero for XCR0 register | |
250 __ xgetbv(); | |
251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); | |
252 __ movl(Address(rsi, 0), rax); | |
253 __ movl(Address(rsi, 4), rdx); | |
254 | |
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255 __ andl(rax, 0x6); // xcr0 bits sse | ymm |
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256 __ cmpl(rax, 0x6); |
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257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
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258 |
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259 // |
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260 // Some OSs have a bug when upper 128bits of YMM |
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261 // registers are not restored after a signal processing. |
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262 // Generate SEGV here (reference through NULL) |
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263 // and check upper YMM bits after it. |
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264 // |
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265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
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266 |
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267 // load value into all 32 bytes of ymm7 register |
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268 __ movl(rcx, VM_Version::ymm_test_value()); |
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269 |
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270 __ movdl(xmm0, rcx); |
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271 __ pshufd(xmm0, xmm0, 0x00); |
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272 __ vinsertf128h(xmm0, xmm0, xmm0); |
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273 __ vmovdqu(xmm7, xmm0); |
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274 #ifdef _LP64 |
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275 __ vmovdqu(xmm8, xmm0); |
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276 __ vmovdqu(xmm15, xmm0); |
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277 #endif |
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278 |
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279 __ xorl(rsi, rsi); |
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280 VM_Version::set_cpuinfo_segv_addr( __ pc() ); |
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281 // Generate SEGV |
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282 __ movl(rax, Address(rsi, 0)); |
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283 |
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284 VM_Version::set_cpuinfo_cont_addr( __ pc() ); |
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285 // Returns here after signal. Save xmm0 to check it later. |
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286 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); |
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287 __ vmovdqu(Address(rsi, 0), xmm0); |
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288 __ vmovdqu(Address(rsi, 32), xmm7); |
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289 #ifdef _LP64 |
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290 __ vmovdqu(Address(rsi, 64), xmm8); |
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291 __ vmovdqu(Address(rsi, 96), xmm15); |
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292 #endif |
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293 |
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294 VM_Version::clean_cpuFeatures(); |
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295 |
4759 | 296 // |
297 // cpuid(0x7) Structured Extended Features | |
298 // | |
299 __ bind(sef_cpuid); | |
300 __ movl(rax, 7); | |
301 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? | |
302 __ jccb(Assembler::greater, ext_cpuid); | |
303 | |
304 __ xorl(rcx, rcx); | |
305 __ cpuid(); | |
306 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); | |
307 __ movl(Address(rsi, 0), rax); | |
308 __ movl(Address(rsi, 4), rbx); | |
309 | |
310 // | |
311 // Extended cpuid(0x80000000) | |
312 // | |
313 __ bind(ext_cpuid); | |
585 | 314 __ movl(rax, 0x80000000); |
315 __ cpuid(); | |
316 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
317 __ jcc(Assembler::belowEqual, done); | |
318 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
319 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
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320 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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321 __ jccb(Assembler::belowEqual, ext_cpuid5); |
585 | 322 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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323 __ jccb(Assembler::belowEqual, ext_cpuid7); |
585 | 324 // |
325 // Extended cpuid(0x80000008) | |
326 // | |
327 __ movl(rax, 0x80000008); | |
328 __ cpuid(); | |
329 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
330 __ movl(Address(rsi, 0), rax); | |
331 __ movl(Address(rsi, 4), rbx); | |
332 __ movl(Address(rsi, 8), rcx); | |
333 __ movl(Address(rsi,12), rdx); | |
334 | |
335 // | |
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336 // Extended cpuid(0x80000007) |
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337 // |
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338 __ bind(ext_cpuid7); |
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339 __ movl(rax, 0x80000007); |
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340 __ cpuid(); |
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341 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
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342 __ movl(Address(rsi, 0), rax); |
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343 __ movl(Address(rsi, 4), rbx); |
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344 __ movl(Address(rsi, 8), rcx); |
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345 __ movl(Address(rsi,12), rdx); |
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346 |
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347 // |
585 | 348 // Extended cpuid(0x80000005) |
349 // | |
350 __ bind(ext_cpuid5); | |
351 __ movl(rax, 0x80000005); | |
352 __ cpuid(); | |
353 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
354 __ movl(Address(rsi, 0), rax); | |
355 __ movl(Address(rsi, 4), rbx); | |
356 __ movl(Address(rsi, 8), rcx); | |
357 __ movl(Address(rsi,12), rdx); | |
358 | |
359 // | |
360 // Extended cpuid(0x80000001) | |
361 // | |
362 __ bind(ext_cpuid1); | |
363 __ movl(rax, 0x80000001); | |
364 __ cpuid(); | |
365 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
366 __ movl(Address(rsi, 0), rax); | |
367 __ movl(Address(rsi, 4), rbx); | |
368 __ movl(Address(rsi, 8), rcx); | |
369 __ movl(Address(rsi,12), rdx); | |
370 | |
371 // | |
372 // return | |
373 // | |
374 __ bind(done); | |
375 __ popf(); | |
376 __ pop(rsi); | |
377 __ pop(rbx); | |
378 __ pop(rbp); | |
379 __ ret(0); | |
380 | |
381 # undef __ | |
382 | |
383 return start; | |
384 }; | |
385 }; | |
386 | |
387 | |
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388 void VM_Version::get_cpu_info_wrapper() { |
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389 get_cpu_info_stub(&_cpuid_info); |
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390 } |
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391 |
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392 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED |
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393 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() |
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394 #endif |
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395 |
585 | 396 void VM_Version::get_processor_features() { |
397 | |
398 _cpu = 4; // 486 by default | |
399 _model = 0; | |
400 _stepping = 0; | |
401 _cpuFeatures = 0; | |
402 _logical_processors_per_package = 1; | |
403 | |
404 if (!Use486InstrsOnly) { | |
405 // Get raw processor info | |
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406 |
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407 // Some platforms (like Win*) need a wrapper around here |
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408 // in order to properly handle SEGV for YMM registers test. |
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409 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper); |
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410 |
585 | 411 assert_is_initialized(); |
412 _cpu = extended_cpu_family(); | |
413 _model = extended_cpu_model(); | |
414 _stepping = cpu_stepping(); | |
415 | |
416 if (cpu_family() > 4) { // it supports CPUID | |
417 _cpuFeatures = feature_flags(); | |
418 // Logical processors are only available on P4s and above, | |
419 // and only if hyperthreading is available. | |
420 _logical_processors_per_package = logical_processor_count(); | |
421 } | |
422 } | |
423 | |
424 _supports_cx8 = supports_cmpxchg8(); | |
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425 // xchg and xadd instructions |
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426 _supports_atomic_getset4 = true; |
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427 _supports_atomic_getadd4 = true; |
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428 LP64_ONLY(_supports_atomic_getset8 = true); |
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429 LP64_ONLY(_supports_atomic_getadd8 = true); |
585 | 430 |
431 #ifdef _LP64 | |
432 // OS should support SSE for x64 and hardware should support at least SSE2. | |
433 if (!VM_Version::supports_sse2()) { | |
434 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
435 } | |
1060 | 436 // in 64 bit the use of SSE2 is the minimum |
437 if (UseSSE < 2) UseSSE = 2; | |
585 | 438 #endif |
439 | |
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440 #ifdef AMD64 |
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441 // flush_icache_stub have to be generated first. |
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442 // That is why Icache line size is hard coded in ICache class, |
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443 // see icache_x86.hpp. It is also the reason why we can't use |
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444 // clflush instruction in 32-bit VM since it could be running |
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445 // on CPU which does not support it. |
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446 // |
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447 // The only thing we can do is to verify that flushed |
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448 // ICache::line_size has correct value. |
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449 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
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450 // clflush_size is size in quadwords (8 bytes). |
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451 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
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452 #endif |
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453 |
585 | 454 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
455 if (!os::supports_sse()) | |
456 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
457 | |
458 if (UseSSE < 4) { | |
459 _cpuFeatures &= ~CPU_SSE4_1; | |
460 _cpuFeatures &= ~CPU_SSE4_2; | |
461 } | |
462 | |
463 if (UseSSE < 3) { | |
464 _cpuFeatures &= ~CPU_SSE3; | |
465 _cpuFeatures &= ~CPU_SSSE3; | |
466 _cpuFeatures &= ~CPU_SSE4A; | |
467 } | |
468 | |
469 if (UseSSE < 2) | |
470 _cpuFeatures &= ~CPU_SSE2; | |
471 | |
472 if (UseSSE < 1) | |
473 _cpuFeatures &= ~CPU_SSE; | |
474 | |
4759 | 475 if (UseAVX < 2) |
476 _cpuFeatures &= ~CPU_AVX2; | |
477 | |
478 if (UseAVX < 1) | |
479 _cpuFeatures &= ~CPU_AVX; | |
480 | |
6894 | 481 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
482 _cpuFeatures &= ~CPU_AES; | |
483 | |
585 | 484 if (logical_processors_per_package() == 1) { |
485 // HT processor could be installed on a system which doesn't support HT. | |
486 _cpuFeatures &= ~CPU_HT; | |
487 } | |
488 | |
489 char buf[256]; | |
17780 | 490 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 491 cores_per_cpu(), threads_per_core(), |
492 cpu_family(), _model, _stepping, | |
493 (supports_cmov() ? ", cmov" : ""), | |
494 (supports_cmpxchg8() ? ", cx8" : ""), | |
495 (supports_fxsr() ? ", fxsr" : ""), | |
496 (supports_mmx() ? ", mmx" : ""), | |
497 (supports_sse() ? ", sse" : ""), | |
498 (supports_sse2() ? ", sse2" : ""), | |
499 (supports_sse3() ? ", sse3" : ""), | |
500 (supports_ssse3()? ", ssse3": ""), | |
501 (supports_sse4_1() ? ", sse4.1" : ""), | |
502 (supports_sse4_2() ? ", sse4.2" : ""), | |
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503 (supports_popcnt() ? ", popcnt" : ""), |
4759 | 504 (supports_avx() ? ", avx" : ""), |
505 (supports_avx2() ? ", avx2" : ""), | |
6894 | 506 (supports_aes() ? ", aes" : ""), |
17780 | 507 (supports_clmul() ? ", clmul" : ""), |
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508 (supports_erms() ? ", erms" : ""), |
17780 | 509 (supports_rtm() ? ", rtm" : ""), |
585 | 510 (supports_mmx_ext() ? ", mmxext" : ""), |
2479 | 511 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
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512 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 513 (supports_sse4a() ? ", sse4a": ""), |
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514 (supports_ht() ? ", ht": ""), |
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515 (supports_tsc() ? ", tsc": ""), |
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516 (supports_tscinv_bit() ? ", tscinvbit": ""), |
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517 (supports_tscinv() ? ", tscinv": ""), |
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518 (supports_bmi1() ? ", bmi1" : ""), |
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519 (supports_bmi2() ? ", bmi2" : "")); |
585 | 520 _features_str = strdup(buf); |
521 | |
522 // UseSSE is set to the smaller of what hardware supports and what | |
523 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
524 // older Pentiums which do not support it. | |
4759 | 525 if (UseSSE > 4) UseSSE=4; |
526 if (UseSSE < 0) UseSSE=0; | |
527 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support | |
585 | 528 UseSSE = MIN2((intx)3,UseSSE); |
4759 | 529 if (!supports_sse3()) // Drop to 2 if no SSE3 support |
585 | 530 UseSSE = MIN2((intx)2,UseSSE); |
4759 | 531 if (!supports_sse2()) // Drop to 1 if no SSE2 support |
585 | 532 UseSSE = MIN2((intx)1,UseSSE); |
4759 | 533 if (!supports_sse ()) // Drop to 0 if no SSE support |
585 | 534 UseSSE = 0; |
535 | |
4759 | 536 if (UseAVX > 2) UseAVX=2; |
537 if (UseAVX < 0) UseAVX=0; | |
538 if (!supports_avx2()) // Drop to 1 if no AVX2 support | |
539 UseAVX = MIN2((intx)1,UseAVX); | |
540 if (!supports_avx ()) // Drop to 0 if no AVX support | |
541 UseAVX = 0; | |
542 | |
6894 | 543 // Use AES instructions if available. |
544 if (supports_aes()) { | |
545 if (FLAG_IS_DEFAULT(UseAES)) { | |
546 UseAES = true; | |
547 } | |
548 } else if (UseAES) { | |
549 if (!FLAG_IS_DEFAULT(UseAES)) | |
17780 | 550 warning("AES instructions are not available on this CPU"); |
6894 | 551 FLAG_SET_DEFAULT(UseAES, false); |
552 } | |
553 | |
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554 // Use CLMUL instructions if available. |
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555 if (supports_clmul()) { |
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556 if (FLAG_IS_DEFAULT(UseCLMUL)) { |
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557 UseCLMUL = true; |
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558 } |
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559 } else if (UseCLMUL) { |
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560 if (!FLAG_IS_DEFAULT(UseCLMUL)) |
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561 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
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562 FLAG_SET_DEFAULT(UseCLMUL, false); |
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563 } |
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564 |
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565 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) { |
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566 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
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567 UseCRC32Intrinsics = true; |
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568 } |
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569 } else if (UseCRC32Intrinsics) { |
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570 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
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571 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)"); |
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572 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
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573 } |
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574 |
6894 | 575 // The AES intrinsic stubs require AES instruction support (of course) |
7427 | 576 // but also require sse3 mode for instructions it use. |
577 if (UseAES && (UseSSE > 2)) { | |
6894 | 578 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
579 UseAESIntrinsics = true; | |
580 } | |
581 } else if (UseAESIntrinsics) { | |
582 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) | |
17780 | 583 warning("AES intrinsics are not available on this CPU"); |
6894 | 584 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
585 } | |
586 | |
17780 | 587 // Adjust RTM (Restricted Transactional Memory) flags |
588 if (!supports_rtm() && UseRTMLocking) { | |
589 // Can't continue because UseRTMLocking affects UseBiasedLocking flag | |
590 // setting during arguments processing. See use_biased_locking(). | |
591 // VM_Version_init() is executed after UseBiasedLocking is used | |
592 // in Thread::allocate(). | |
593 vm_exit_during_initialization("RTM instructions are not available on this CPU"); | |
594 } | |
595 | |
596 #if INCLUDE_RTM_OPT | |
597 if (UseRTMLocking) { | |
598 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { | |
599 // RTM locking should be used only for applications with | |
600 // high lock contention. For now we do not use it by default. | |
601 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); | |
602 } | |
603 if (!is_power_of_2(RTMTotalCountIncrRate)) { | |
604 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); | |
605 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); | |
606 } | |
607 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { | |
608 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); | |
609 FLAG_SET_DEFAULT(RTMAbortRatio, 50); | |
610 } | |
611 } else { // !UseRTMLocking | |
612 if (UseRTMForStackLocks) { | |
613 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { | |
614 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); | |
615 } | |
616 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); | |
617 } | |
618 if (UseRTMDeopt) { | |
619 FLAG_SET_DEFAULT(UseRTMDeopt, false); | |
620 } | |
621 if (PrintPreciseRTMLockingStatistics) { | |
622 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); | |
623 } | |
624 } | |
625 #else | |
626 if (UseRTMLocking) { | |
627 // Only C2 does RTM locking optimization. | |
628 // Can't continue because UseRTMLocking affects UseBiasedLocking flag | |
629 // setting during arguments processing. See use_biased_locking(). | |
630 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); | |
631 } | |
632 #endif | |
633 | |
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634 #ifdef COMPILER2 |
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635 if (UseFPUForSpilling) { |
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636 if (UseSSE < 2) { |
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637 // Only supported with SSE2+ |
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638 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
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639 } |
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640 } |
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641 if (MaxVectorSize > 0) { |
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642 if (!is_power_of_2(MaxVectorSize)) { |
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643 warning("MaxVectorSize must be a power of 2"); |
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644 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
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645 } |
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646 if (MaxVectorSize > 32) { |
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647 FLAG_SET_DEFAULT(MaxVectorSize, 32); |
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648 } |
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649 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { |
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650 // 32 bytes vectors (in YMM) are only supported with AVX+ |
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651 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
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652 } |
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653 if (UseSSE < 2) { |
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654 // Vectors (in XMM) are only supported with SSE2+ |
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655 FLAG_SET_DEFAULT(MaxVectorSize, 0); |
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656 } |
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657 #ifdef ASSERT |
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658 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { |
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659 tty->print_cr("State of YMM registers after signal handle:"); |
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660 int nreg = 2 LP64_ONLY(+2); |
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661 const char* ymm_name[4] = {"0", "7", "8", "15"}; |
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662 for (int i = 0; i < nreg; i++) { |
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663 tty->print("YMM%s:", ymm_name[i]); |
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664 for (int j = 7; j >=0; j--) { |
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665 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); |
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666 } |
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667 tty->cr(); |
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668 } |
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669 } |
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670 #endif |
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671 } |
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672 #endif |
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673 |
585 | 674 // On new cpus instructions which update whole XMM register should be used |
675 // to prevent partial register stall due to dependencies on high half. | |
676 // | |
677 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
678 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
679 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
680 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
681 | |
682 if( is_amd() ) { // AMD cpus specific settings | |
683 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
684 // Use it on new AMD cpus starting from Opteron. | |
685 UseAddressNop = true; | |
686 } | |
687 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
688 // Use it on new AMD cpus starting from Opteron. | |
689 UseNewLongLShift = true; | |
690 } | |
691 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
692 if( supports_sse4a() ) { | |
693 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
694 } else { | |
695 UseXmmLoadAndClearUpper = false; | |
696 } | |
697 } | |
698 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
699 if( supports_sse4a() ) { | |
700 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
701 } else { | |
702 UseXmmRegToRegMoveAll = false; | |
703 } | |
704 } | |
705 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
706 if( supports_sse4a() ) { | |
707 UseXmmI2F = true; | |
708 } else { | |
709 UseXmmI2F = false; | |
710 } | |
711 } | |
712 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
713 if( supports_sse4a() ) { | |
714 UseXmmI2D = true; | |
715 } else { | |
716 UseXmmI2D = false; | |
717 } | |
718 } | |
2406 | 719 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
720 if( supports_sse4_2() && UseSSE >= 4 ) { | |
721 UseSSE42Intrinsics = true; | |
722 } | |
723 } | |
775
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724 |
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725 // some defaults for AMD family 15h |
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726 if ( cpu_family() == 0x15 ) { |
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727 // On family 15h processors default is no sw prefetch |
2358 | 728 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
729 AllocatePrefetchStyle = 0; | |
730 } | |
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731 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
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732 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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733 AllocatePrefetchInstr = 3; |
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734 } |
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735 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
6794 | 736 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
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737 UseXMMForArrayCopy = true; |
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738 } |
6794 | 739 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
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740 UseUnalignedLoadStores = true; |
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741 } |
2358 | 742 } |
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743 |
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744 #ifdef COMPILER2 |
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745 if (MaxVectorSize > 16) { |
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746 // Limit vectors size to 16 bytes on current AMD cpus. |
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747 FLAG_SET_DEFAULT(MaxVectorSize, 16); |
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748 } |
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749 #endif // COMPILER2 |
585 | 750 } |
751 | |
752 if( is_intel() ) { // Intel cpus specific settings | |
753 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
754 UseStoreImmI16 = false; // don't use it on Intel cpus | |
755 } | |
756 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
757 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
758 // Use it on all Intel cpus starting from PentiumPro | |
759 UseAddressNop = true; | |
760 } | |
761 } | |
762 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
763 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
764 } | |
765 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
766 if( supports_sse3() ) { | |
767 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
768 } else { | |
769 UseXmmRegToRegMoveAll = false; | |
770 } | |
771 } | |
772 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
773 #ifdef COMPILER2 | |
774 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
775 // For new Intel cpus do the next optimization: | |
776 // don't align the beginning of a loop if there are enough instructions | |
777 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
778 // in current fetch line (OptoLoopAlignment) or the padding | |
779 // is big (> MaxLoopPad). | |
780 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
781 // generated NOP instructions. 11 is the largest size of one | |
782 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
783 MaxLoopPad = 11; | |
784 } | |
785 #endif // COMPILER2 | |
6794 | 786 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
585 | 787 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
788 } | |
6794 | 789 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
790 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { | |
585 | 791 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
792 } | |
793 } | |
6794 | 794 if (supports_sse4_2() && UseSSE >= 4) { |
795 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
681 | 796 UseSSE42Intrinsics = true; |
797 } | |
798 } | |
585 | 799 } |
800 } | |
801 | |
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802 // Use count leading zeros count instruction if available. |
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803 if (supports_lzcnt()) { |
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804 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
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805 UseCountLeadingZerosInstruction = true; |
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806 } |
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807 } else if (UseCountLeadingZerosInstruction) { |
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808 warning("lzcnt instruction is not available on this CPU"); |
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809 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
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810 } |
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811 |
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812 if (supports_bmi1()) { |
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813 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
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814 UseBMI1Instructions = true; |
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815 } |
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816 } else if (UseBMI1Instructions) { |
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817 warning("BMI1 instructions are not available on this CPU"); |
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818 FLAG_SET_DEFAULT(UseBMI1Instructions, false); |
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819 } |
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820 |
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821 // Use count trailing zeros instruction if available |
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822 if (supports_bmi1()) { |
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823 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
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824 UseCountTrailingZerosInstruction = UseBMI1Instructions; |
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825 } |
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826 } else if (UseCountTrailingZerosInstruction) { |
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827 warning("tzcnt instruction is not available on this CPU"); |
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828 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
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829 } |
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830 |
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831 // Use population count instruction if available. |
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832 if (supports_popcnt()) { |
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833 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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834 UsePopCountInstruction = true; |
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835 } |
4759 | 836 } else if (UsePopCountInstruction) { |
837 warning("POPCNT instruction is not available on this CPU"); | |
838 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
643
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839 } |
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840 |
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841 // Use fast-string operations if available. |
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842 if (supports_erms()) { |
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843 if (FLAG_IS_DEFAULT(UseFastStosb)) { |
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844 UseFastStosb = true; |
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845 } |
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846 } else if (UseFastStosb) { |
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847 warning("fast-string operations are not available on this CPU"); |
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848 FLAG_SET_DEFAULT(UseFastStosb, false); |
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849 } |
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850 |
6794 | 851 #ifdef COMPILER2 |
852 if (FLAG_IS_DEFAULT(AlignVector)) { | |
853 // Modern processors allow misaligned memory operations for vectors. | |
854 AlignVector = !UseUnalignedLoadStores; | |
855 } | |
856 #endif // COMPILER2 | |
857 | |
585 | 858 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
859 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
860 | |
861 // set valid Prefetch instruction | |
862 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
863 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
2479 | 864 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
865 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; | |
585 | 866 |
867 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
868 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
2479 | 869 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
870 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; | |
585 | 871 |
872 // Allocation prefetch settings | |
3854 | 873 intx cache_line_size = prefetch_data_size(); |
585 | 874 if( cache_line_size > AllocatePrefetchStepSize ) |
875 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 876 |
585 | 877 assert(AllocatePrefetchLines > 0, "invalid value"); |
3854 | 878 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
879 AllocatePrefetchLines = 3; | |
880 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
881 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
882 AllocateInstancePrefetchLines = 1; | |
585 | 883 |
884 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
885 AllocatePrefetchStyle = allocate_prefetch_style(); | |
886 | |
1622 | 887 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
888 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | |
585 | 889 #ifdef _LP64 |
1622 | 890 AllocatePrefetchDistance = 384; |
585 | 891 #else |
1622 | 892 AllocatePrefetchDistance = 320; |
585 | 893 #endif |
1622 | 894 } |
895 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | |
896 AllocatePrefetchDistance = 192; | |
897 AllocatePrefetchLines = 4; | |
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898 #ifdef COMPILER2 |
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899 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
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900 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
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901 } |
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902 #endif |
1622 | 903 } |
585 | 904 } |
905 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
906 | |
907 #ifdef _LP64 | |
908 // Prefetch settings | |
909 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
910 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
911 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
912 #endif | |
913 | |
7587 | 914 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
915 (cache_line_size > ContendedPaddingWidth)) | |
916 ContendedPaddingWidth = cache_line_size; | |
917 | |
585 | 918 #ifndef PRODUCT |
919 if (PrintMiscellaneous && Verbose) { | |
920 tty->print_cr("Logical CPUs per core: %u", | |
921 logical_processors_per_package()); | |
4759 | 922 tty->print("UseSSE=%d",UseSSE); |
923 if (UseAVX > 0) { | |
924 tty->print(" UseAVX=%d",UseAVX); | |
925 } | |
6894 | 926 if (UseAES) { |
927 tty->print(" UseAES=1"); | |
928 } | |
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929 #ifdef COMPILER2 |
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930 if (MaxVectorSize > 0) { |
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931 tty->print(" MaxVectorSize=%d", MaxVectorSize); |
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932 } |
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933 #endif |
4759 | 934 tty->cr(); |
3854 | 935 tty->print("Allocation"); |
2479 | 936 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
3854 | 937 tty->print_cr(": no prefetching"); |
585 | 938 } else { |
3854 | 939 tty->print(" prefetching: "); |
2479 | 940 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
585 | 941 tty->print("PREFETCHW"); |
942 } else if (UseSSE >= 1) { | |
943 if (AllocatePrefetchInstr == 0) { | |
944 tty->print("PREFETCHNTA"); | |
945 } else if (AllocatePrefetchInstr == 1) { | |
946 tty->print("PREFETCHT0"); | |
947 } else if (AllocatePrefetchInstr == 2) { | |
948 tty->print("PREFETCHT2"); | |
949 } else if (AllocatePrefetchInstr == 3) { | |
950 tty->print("PREFETCHW"); | |
951 } | |
952 } | |
953 if (AllocatePrefetchLines > 1) { | |
3854 | 954 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
585 | 955 } else { |
3854 | 956 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
585 | 957 } |
958 } | |
959 | |
960 if (PrefetchCopyIntervalInBytes > 0) { | |
961 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
962 } | |
963 if (PrefetchScanIntervalInBytes > 0) { | |
964 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
965 } | |
966 if (PrefetchFieldsAhead > 0) { | |
967 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
968 } | |
7587 | 969 if (ContendedPaddingWidth > 0) { |
970 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth); | |
971 } | |
585 | 972 } |
973 #endif // !PRODUCT | |
974 } | |
975 | |
17780 | 976 bool VM_Version::use_biased_locking() { |
977 #if INCLUDE_RTM_OPT | |
978 // RTM locking is most useful when there is high lock contention and | |
979 // low data contention. With high lock contention the lock is usually | |
980 // inflated and biased locking is not suitable for that case. | |
981 // RTM locking code requires that biased locking is off. | |
982 // Note: we can't switch off UseBiasedLocking in get_processor_features() | |
983 // because it is used by Thread::allocate() which is called before | |
984 // VM_Version::initialize(). | |
985 if (UseRTMLocking && UseBiasedLocking) { | |
986 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { | |
987 FLAG_SET_DEFAULT(UseBiasedLocking, false); | |
988 } else { | |
989 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); | |
990 UseBiasedLocking = false; | |
991 } | |
992 } | |
993 #endif | |
994 return UseBiasedLocking; | |
995 } | |
996 | |
585 | 997 void VM_Version::initialize() { |
998 ResourceMark rm; | |
999 // Making this stub must be FIRST use of assembler | |
1000 | |
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1001 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); |
585 | 1002 if (stub_blob == NULL) { |
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1003 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); |
585 | 1004 } |
1748 | 1005 CodeBuffer c(stub_blob); |
585 | 1006 VM_Version_StubGenerator g(&c); |
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1007 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, |
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1008 g.generate_get_cpu_info()); |
585 | 1009 |
1010 get_processor_features(); | |
1011 } |