Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 7212:291ffc492eb6
Merge with http://hg.openjdk.java.net/hsx/hsx25/hotspot/
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Fri, 14 Dec 2012 14:35:13 +0100 |
| parents | e522a00b91aa |
| children | 989155e2d07a |
| rev | line source |
|---|---|
| 585 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 585 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
| 26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
| 27 | |
| 28 #include "runtime/globals_extension.hpp" | |
| 29 #include "runtime/vm_version.hpp" | |
| 30 | |
| 585 | 31 class VM_Version : public Abstract_VM_Version { |
| 32 public: | |
| 33 // cpuid result register layouts. These are all unions of a uint32_t | |
| 34 // (in case anyone wants access to the register as a whole) and a bitfield. | |
| 35 | |
| 36 union StdCpuid1Eax { | |
| 37 uint32_t value; | |
| 38 struct { | |
| 39 uint32_t stepping : 4, | |
| 40 model : 4, | |
| 41 family : 4, | |
| 42 proc_type : 2, | |
| 43 : 2, | |
| 44 ext_model : 4, | |
| 45 ext_family : 8, | |
| 46 : 4; | |
| 47 } bits; | |
| 48 }; | |
| 49 | |
| 50 union StdCpuid1Ebx { // example, unused | |
| 51 uint32_t value; | |
| 52 struct { | |
| 53 uint32_t brand_id : 8, | |
| 54 clflush_size : 8, | |
| 55 threads_per_cpu : 8, | |
| 56 apic_id : 8; | |
| 57 } bits; | |
| 58 }; | |
| 59 | |
| 60 union StdCpuid1Ecx { | |
| 61 uint32_t value; | |
| 62 struct { | |
| 63 uint32_t sse3 : 1, | |
| 64 : 2, | |
| 65 monitor : 1, | |
| 66 : 1, | |
| 67 vmx : 1, | |
| 68 : 1, | |
| 69 est : 1, | |
| 70 : 1, | |
| 71 ssse3 : 1, | |
| 72 cid : 1, | |
| 73 : 2, | |
| 74 cmpxchg16: 1, | |
| 75 : 4, | |
| 76 dca : 1, | |
| 77 sse4_1 : 1, | |
| 78 sse4_2 : 1, | |
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79 : 2, |
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80 popcnt : 1, |
| 6894 | 81 : 1, |
| 82 aes : 1, | |
| 83 : 1, | |
| 4759 | 84 osxsave : 1, |
| 85 avx : 1, | |
| 86 : 3; | |
| 585 | 87 } bits; |
| 88 }; | |
| 89 | |
| 90 union StdCpuid1Edx { | |
| 91 uint32_t value; | |
| 92 struct { | |
| 93 uint32_t : 4, | |
| 94 tsc : 1, | |
| 95 : 3, | |
| 96 cmpxchg8 : 1, | |
| 97 : 6, | |
| 98 cmov : 1, | |
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99 : 3, |
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100 clflush : 1, |
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101 : 3, |
| 585 | 102 mmx : 1, |
| 103 fxsr : 1, | |
| 104 sse : 1, | |
| 105 sse2 : 1, | |
| 106 : 1, | |
| 107 ht : 1, | |
| 108 : 3; | |
| 109 } bits; | |
| 110 }; | |
| 111 | |
| 112 union DcpCpuid4Eax { | |
| 113 uint32_t value; | |
| 114 struct { | |
| 115 uint32_t cache_type : 5, | |
| 116 : 21, | |
| 117 cores_per_cpu : 6; | |
| 118 } bits; | |
| 119 }; | |
| 120 | |
| 121 union DcpCpuid4Ebx { | |
| 122 uint32_t value; | |
| 123 struct { | |
| 124 uint32_t L1_line_size : 12, | |
| 125 partitions : 10, | |
| 126 associativity : 10; | |
| 127 } bits; | |
| 128 }; | |
| 129 | |
| 1622 | 130 union TplCpuidBEbx { |
| 131 uint32_t value; | |
| 132 struct { | |
| 133 uint32_t logical_cpus : 16, | |
| 134 : 16; | |
| 135 } bits; | |
| 136 }; | |
| 137 | |
| 585 | 138 union ExtCpuid1Ecx { |
| 139 uint32_t value; | |
| 140 struct { | |
| 141 uint32_t LahfSahf : 1, | |
| 142 CmpLegacy : 1, | |
| 143 : 4, | |
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144 lzcnt : 1, |
| 585 | 145 sse4a : 1, |
| 146 misalignsse : 1, | |
| 147 prefetchw : 1, | |
| 148 : 22; | |
| 149 } bits; | |
| 150 }; | |
| 151 | |
| 152 union ExtCpuid1Edx { | |
| 153 uint32_t value; | |
| 154 struct { | |
| 155 uint32_t : 22, | |
| 156 mmx_amd : 1, | |
| 157 mmx : 1, | |
| 158 fxsr : 1, | |
| 159 : 4, | |
| 160 long_mode : 1, | |
| 161 tdnow2 : 1, | |
| 162 tdnow : 1; | |
| 163 } bits; | |
| 164 }; | |
| 165 | |
| 166 union ExtCpuid5Ex { | |
| 167 uint32_t value; | |
| 168 struct { | |
| 169 uint32_t L1_line_size : 8, | |
| 170 L1_tag_lines : 8, | |
| 171 L1_assoc : 8, | |
| 172 L1_size : 8; | |
| 173 } bits; | |
| 174 }; | |
| 175 | |
| 4771 | 176 union ExtCpuid7Edx { |
| 177 uint32_t value; | |
| 178 struct { | |
| 179 uint32_t : 8, | |
| 180 tsc_invariance : 1, | |
| 181 : 23; | |
| 182 } bits; | |
| 183 }; | |
| 184 | |
| 585 | 185 union ExtCpuid8Ecx { |
| 186 uint32_t value; | |
| 187 struct { | |
| 188 uint32_t cores_per_cpu : 8, | |
| 189 : 24; | |
| 190 } bits; | |
| 191 }; | |
| 192 | |
| 4759 | 193 union SefCpuid7Eax { |
| 194 uint32_t value; | |
| 195 }; | |
| 196 | |
| 197 union SefCpuid7Ebx { | |
| 198 uint32_t value; | |
| 199 struct { | |
| 200 uint32_t fsgsbase : 1, | |
| 201 : 2, | |
| 202 bmi1 : 1, | |
| 203 : 1, | |
| 204 avx2 : 1, | |
| 205 : 2, | |
| 206 bmi2 : 1, | |
| 207 : 23; | |
| 208 } bits; | |
| 209 }; | |
| 210 | |
| 211 union XemXcr0Eax { | |
| 212 uint32_t value; | |
| 213 struct { | |
| 214 uint32_t x87 : 1, | |
| 215 sse : 1, | |
| 216 ymm : 1, | |
| 217 : 29; | |
| 218 } bits; | |
| 219 }; | |
| 220 | |
| 585 | 221 protected: |
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222 static int _cpu; |
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223 static int _model; |
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224 static int _stepping; |
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225 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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226 // 0 if this instruction is not available |
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227 static const char* _features_str; |
| 585 | 228 |
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229 enum { |
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230 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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231 CPU_CMOV = (1 << 1), |
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232 CPU_FXSR = (1 << 2), |
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233 CPU_HT = (1 << 3), |
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234 CPU_MMX = (1 << 4), |
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235 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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236 // may not necessarily support other 3dnow instructions |
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237 CPU_SSE = (1 << 6), |
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238 CPU_SSE2 = (1 << 7), |
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239 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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240 CPU_SSSE3 = (1 << 9), |
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241 CPU_SSE4A = (1 << 10), |
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242 CPU_SSE4_1 = (1 << 11), |
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243 CPU_SSE4_2 = (1 << 12), |
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244 CPU_POPCNT = (1 << 13), |
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245 CPU_LZCNT = (1 << 14), |
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246 CPU_TSC = (1 << 15), |
| 4771 | 247 CPU_TSCINV = (1 << 16), |
| 248 CPU_AVX = (1 << 17), | |
| 6894 | 249 CPU_AVX2 = (1 << 18), |
| 250 CPU_AES = (1 << 19) | |
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251 } cpuFeatureFlags; |
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252 |
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253 enum { |
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254 // AMD |
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255 CPU_FAMILY_AMD_11H = 0x11, |
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256 // Intel |
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257 CPU_FAMILY_INTEL_CORE = 6, |
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258 CPU_MODEL_NEHALEM = 0x1e, |
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259 CPU_MODEL_NEHALEM_EP = 0x1a, |
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260 CPU_MODEL_NEHALEM_EX = 0x2e, |
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261 CPU_MODEL_WESTMERE = 0x25, |
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262 CPU_MODEL_WESTMERE_EP = 0x2c, |
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263 CPU_MODEL_WESTMERE_EX = 0x2f, |
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264 CPU_MODEL_SANDYBRIDGE = 0x2a, |
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265 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, |
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266 CPU_MODEL_IVYBRIDGE_EP = 0x3a |
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267 } cpuExtendedFamily; |
| 585 | 268 |
| 269 // cpuid information block. All info derived from executing cpuid with | |
| 270 // various function numbers is stored here. Intel and AMD info is | |
| 271 // merged in this block: accessor methods disentangle it. | |
| 272 // | |
| 273 // The info block is laid out in subblocks of 4 dwords corresponding to | |
| 274 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
| 275 struct CpuidInfo { | |
| 276 // cpuid function 0 | |
| 277 uint32_t std_max_function; | |
| 278 uint32_t std_vendor_name_0; | |
| 279 uint32_t std_vendor_name_1; | |
| 280 uint32_t std_vendor_name_2; | |
| 281 | |
| 282 // cpuid function 1 | |
| 283 StdCpuid1Eax std_cpuid1_eax; | |
| 284 StdCpuid1Ebx std_cpuid1_ebx; | |
| 285 StdCpuid1Ecx std_cpuid1_ecx; | |
| 286 StdCpuid1Edx std_cpuid1_edx; | |
| 287 | |
| 288 // cpuid function 4 (deterministic cache parameters) | |
| 289 DcpCpuid4Eax dcp_cpuid4_eax; | |
| 290 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
| 291 uint32_t dcp_cpuid4_ecx; // unused currently | |
| 292 uint32_t dcp_cpuid4_edx; // unused currently | |
| 293 | |
| 4759 | 294 // cpuid function 7 (structured extended features) |
| 295 SefCpuid7Eax sef_cpuid7_eax; | |
| 296 SefCpuid7Ebx sef_cpuid7_ebx; | |
| 297 uint32_t sef_cpuid7_ecx; // unused currently | |
| 298 uint32_t sef_cpuid7_edx; // unused currently | |
| 299 | |
| 1622 | 300 // cpuid function 0xB (processor topology) |
| 301 // ecx = 0 | |
| 302 uint32_t tpl_cpuidB0_eax; | |
| 303 TplCpuidBEbx tpl_cpuidB0_ebx; | |
| 304 uint32_t tpl_cpuidB0_ecx; // unused currently | |
| 305 uint32_t tpl_cpuidB0_edx; // unused currently | |
| 306 | |
| 307 // ecx = 1 | |
| 308 uint32_t tpl_cpuidB1_eax; | |
| 309 TplCpuidBEbx tpl_cpuidB1_ebx; | |
| 310 uint32_t tpl_cpuidB1_ecx; // unused currently | |
| 311 uint32_t tpl_cpuidB1_edx; // unused currently | |
| 312 | |
| 313 // ecx = 2 | |
| 314 uint32_t tpl_cpuidB2_eax; | |
| 315 TplCpuidBEbx tpl_cpuidB2_ebx; | |
| 316 uint32_t tpl_cpuidB2_ecx; // unused currently | |
| 317 uint32_t tpl_cpuidB2_edx; // unused currently | |
| 318 | |
| 585 | 319 // cpuid function 0x80000000 // example, unused |
| 320 uint32_t ext_max_function; | |
| 321 uint32_t ext_vendor_name_0; | |
| 322 uint32_t ext_vendor_name_1; | |
| 323 uint32_t ext_vendor_name_2; | |
| 324 | |
| 325 // cpuid function 0x80000001 | |
| 326 uint32_t ext_cpuid1_eax; // reserved | |
| 327 uint32_t ext_cpuid1_ebx; // reserved | |
| 328 ExtCpuid1Ecx ext_cpuid1_ecx; | |
| 329 ExtCpuid1Edx ext_cpuid1_edx; | |
| 330 | |
| 331 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
| 332 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
| 333 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
| 334 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
| 335 | |
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336 // cpuid function 0x80000005 // AMD L1, Intel reserved |
| 585 | 337 uint32_t ext_cpuid5_eax; // unused currently |
| 338 uint32_t ext_cpuid5_ebx; // reserved | |
| 339 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
| 340 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
| 341 | |
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342 // cpuid function 0x80000007 |
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343 uint32_t ext_cpuid7_eax; // reserved |
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344 uint32_t ext_cpuid7_ebx; // reserved |
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345 uint32_t ext_cpuid7_ecx; // reserved |
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346 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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347 |
| 585 | 348 // cpuid function 0x80000008 |
| 349 uint32_t ext_cpuid8_eax; // unused currently | |
| 350 uint32_t ext_cpuid8_ebx; // reserved | |
| 351 ExtCpuid8Ecx ext_cpuid8_ecx; | |
| 352 uint32_t ext_cpuid8_edx; // reserved | |
| 4759 | 353 |
| 354 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
| 355 XemXcr0Eax xem_xcr0_eax; | |
| 356 uint32_t xem_xcr0_edx; // reserved | |
| 585 | 357 }; |
| 358 | |
| 359 // The actual cpuid info block | |
| 360 static CpuidInfo _cpuid_info; | |
| 361 | |
| 362 // Extractors and predicates | |
| 363 static uint32_t extended_cpu_family() { | |
| 364 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
| 365 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
| 366 return result; | |
| 367 } | |
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368 |
| 585 | 369 static uint32_t extended_cpu_model() { |
| 370 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
| 371 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
| 372 return result; | |
| 373 } | |
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374 |
| 585 | 375 static uint32_t cpu_stepping() { |
| 376 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
| 377 return result; | |
| 378 } | |
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379 |
| 585 | 380 static uint logical_processor_count() { |
| 381 uint result = threads_per_core(); | |
| 382 return result; | |
| 383 } | |
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384 |
| 585 | 385 static uint32_t feature_flags() { |
| 386 uint32_t result = 0; | |
| 387 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
| 388 result |= CPU_CX8; | |
| 389 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
| 390 result |= CPU_CMOV; | |
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391 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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392 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
| 585 | 393 result |= CPU_FXSR; |
| 394 // HT flag is set for multi-core processors also. | |
| 395 if (threads_per_core() > 1) | |
| 396 result |= CPU_HT; | |
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397 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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398 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
| 585 | 399 result |= CPU_MMX; |
| 400 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
| 401 result |= CPU_SSE; | |
| 402 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
| 403 result |= CPU_SSE2; | |
| 404 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
| 405 result |= CPU_SSE3; | |
| 406 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
| 407 result |= CPU_SSSE3; | |
| 408 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
| 409 result |= CPU_SSE4_1; | |
| 410 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
| 411 result |= CPU_SSE4_2; | |
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412 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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413 result |= CPU_POPCNT; |
| 4759 | 414 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
| 415 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
| 416 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
| 417 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
| 418 result |= CPU_AVX; | |
| 419 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
| 420 result |= CPU_AVX2; | |
| 421 } | |
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422 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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423 result |= CPU_TSC; |
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424 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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425 result |= CPU_TSCINV; |
| 6894 | 426 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) |
| 427 result |= CPU_AES; | |
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428 |
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429 // AMD features. |
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430 if (is_amd()) { |
| 2479 | 431 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
| 432 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
| 433 result |= CPU_3DNOW_PREFETCH; | |
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434 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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435 result |= CPU_LZCNT; |
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436 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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437 result |= CPU_SSE4A; |
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438 } |
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439 |
| 585 | 440 return result; |
| 441 } | |
| 442 | |
| 443 static void get_processor_features(); | |
| 444 | |
| 445 public: | |
| 446 // Offsets for cpuid asm stub | |
| 447 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
| 448 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
| 449 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
| 4759 | 450 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
| 585 | 451 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
| 452 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
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453 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
| 585 | 454 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
| 1622 | 455 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
| 456 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
| 457 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
| 4759 | 458 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
| 585 | 459 |
| 460 // Initialization | |
| 461 static void initialize(); | |
| 462 | |
| 463 // Asserts | |
| 464 static void assert_is_initialized() { | |
| 465 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
| 466 } | |
| 467 | |
| 468 // | |
| 469 // Processor family: | |
| 470 // 3 - 386 | |
| 471 // 4 - 486 | |
| 472 // 5 - Pentium | |
| 473 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
| 474 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
| 475 // family 6 model: 9, 13, 14, 15 | |
| 476 // 0x0f - Pentium 4, Opteron | |
| 477 // | |
| 478 // Note: The cpu family should be used to select between | |
| 479 // instruction sequences which are valid on all Intel | |
| 480 // processors. Use the feature test functions below to | |
| 481 // determine whether a particular instruction is supported. | |
| 482 // | |
| 483 static int cpu_family() { return _cpu;} | |
| 484 static bool is_P6() { return cpu_family() >= 6; } | |
| 485 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
| 486 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
| 487 | |
| 1647 | 488 static bool supports_processor_topology() { |
| 489 return (_cpuid_info.std_max_function >= 0xB) && | |
| 490 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
| 491 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
| 492 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); | |
| 493 } | |
| 494 | |
| 585 | 495 static uint cores_per_cpu() { |
| 496 uint result = 1; | |
| 497 if (is_intel()) { | |
| 1647 | 498 if (supports_processor_topology()) { |
| 1622 | 499 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
| 500 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
| 501 } else { | |
| 502 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
| 503 } | |
| 585 | 504 } else if (is_amd()) { |
| 505 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
| 506 } | |
| 507 return result; | |
| 508 } | |
| 509 | |
| 510 static uint threads_per_core() { | |
| 511 uint result = 1; | |
| 1647 | 512 if (is_intel() && supports_processor_topology()) { |
| 1622 | 513 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
| 514 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
| 585 | 515 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
| 516 cores_per_cpu(); | |
| 517 } | |
| 518 return result; | |
| 519 } | |
| 520 | |
| 3854 | 521 static intx prefetch_data_size() { |
| 585 | 522 intx result = 0; |
| 523 if (is_intel()) { | |
| 524 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
| 525 } else if (is_amd()) { | |
| 526 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
| 527 } | |
| 528 if (result < 32) // not defined ? | |
| 529 result = 32; // 32 bytes by default on x86 and other x64 | |
| 530 return result; | |
| 531 } | |
| 532 | |
| 533 // | |
| 534 // Feature identification | |
| 535 // | |
| 536 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
| 537 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
| 538 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
| 539 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
| 540 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
| 541 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
| 542 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
| 543 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
| 544 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
| 545 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
| 546 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
| 547 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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548 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
| 4759 | 549 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
| 550 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
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551 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
| 6894 | 552 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } |
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553 |
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554 // Intel features |
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555 static bool is_intel_family_core() { return is_intel() && |
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556 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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557 |
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558 static bool is_intel_tsc_synched_at_init() { |
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559 if (is_intel_family_core()) { |
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560 uint32_t ext_model = extended_cpu_model(); |
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561 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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562 ext_model == CPU_MODEL_WESTMERE_EP || |
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563 ext_model == CPU_MODEL_SANDYBRIDGE_EP || |
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564 ext_model == CPU_MODEL_IVYBRIDGE_EP) { |
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565 // <= 2-socket invariant tsc support. EX versions are usually used |
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566 // in > 2-socket systems and likely don't synchronize tscs at |
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567 // initialization. |
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568 // Code that uses tsc values must be prepared for them to arbitrarily |
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569 // jump forward or backward. |
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570 return true; |
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571 } |
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572 } |
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573 return false; |
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574 } |
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575 |
| 585 | 576 // AMD features |
| 2479 | 577 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
| 585 | 578 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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579 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
| 585 | 580 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
| 581 | |
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582 static bool is_amd_Barcelona() { return is_amd() && |
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583 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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584 |
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585 // Intel and AMD newer cores support fast timestamps well |
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586 static bool supports_tscinv_bit() { |
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587 return (_cpuFeatures & CPU_TSCINV) != 0; |
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588 } |
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589 static bool supports_tscinv() { |
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590 return supports_tscinv_bit() && |
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591 ( (is_amd() && !is_amd_Barcelona()) || |
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592 is_intel_tsc_synched_at_init() ); |
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593 } |
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594 |
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595 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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596 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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597 supports_sse3() && _model != 0x1C; } |
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598 |
| 585 | 599 static bool supports_compare_and_exchange() { return true; } |
| 600 | |
| 601 static const char* cpu_features() { return _features_str; } | |
| 602 | |
| 603 static intx allocate_prefetch_distance() { | |
| 604 // This method should be called before allocate_prefetch_style(). | |
| 605 // | |
| 606 // Hardware prefetching (distance/size in bytes): | |
| 607 // Pentium 3 - 64 / 32 | |
| 608 // Pentium 4 - 256 / 128 | |
| 609 // Athlon - 64 / 32 ???? | |
| 610 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
| 611 // Core - 128 / 64 | |
| 612 // | |
| 613 // Software prefetching (distance in bytes / instruction with best score): | |
| 614 // Pentium 3 - 128 / prefetchnta | |
| 615 // Pentium 4 - 512 / prefetchnta | |
| 616 // Athlon - 128 / prefetchnta | |
| 617 // Opteron - 256 / prefetchnta | |
| 618 // Core - 256 / prefetchnta | |
| 619 // It will be used only when AllocatePrefetchStyle > 0 | |
| 620 | |
| 621 intx count = AllocatePrefetchDistance; | |
| 622 if (count < 0) { // default ? | |
| 623 if (is_amd()) { // AMD | |
| 624 if (supports_sse2()) | |
| 625 count = 256; // Opteron | |
| 626 else | |
| 627 count = 128; // Athlon | |
| 628 } else { // Intel | |
| 629 if (supports_sse2()) | |
| 630 if (cpu_family() == 6) { | |
| 631 count = 256; // Pentium M, Core, Core2 | |
| 632 } else { | |
| 633 count = 512; // Pentium 4 | |
| 634 } | |
| 635 else | |
| 636 count = 128; // Pentium 3 (and all other old CPUs) | |
| 637 } | |
| 638 } | |
| 639 return count; | |
| 640 } | |
| 641 static intx allocate_prefetch_style() { | |
| 642 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 643 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 644 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 645 } | |
| 646 | |
| 647 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
| 648 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
| 649 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
| 650 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
| 651 | |
| 652 // gc copy/scan is disabled if prefetchw isn't supported, because | |
| 653 // Prefetch::write emits an inlined prefetchw on Linux. | |
| 654 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
| 655 // The used prefetcht0 instruction works for both amd64 and em64t. | |
| 656 static intx prefetch_copy_interval_in_bytes() { | |
| 657 intx interval = PrefetchCopyIntervalInBytes; | |
| 658 return interval >= 0 ? interval : 576; | |
| 659 } | |
| 660 static intx prefetch_scan_interval_in_bytes() { | |
| 661 intx interval = PrefetchScanIntervalInBytes; | |
| 662 return interval >= 0 ? interval : 576; | |
| 663 } | |
| 664 static intx prefetch_fields_ahead() { | |
| 665 intx count = PrefetchFieldsAhead; | |
| 666 return count >= 0 ? count : 1; | |
| 667 } | |
| 668 }; | |
| 1972 | 669 |
| 670 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |