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annotate src/cpu/x86/vm/vm_version_x86.hpp @ 4749:7ab5f6318694

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7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64 Summary: Add rdtsc detection and inline generation. Reviewed-by: kamg, dholmes Contributed-by: karen.kinnear@oracle.com
author phh
date Sun, 01 Jan 2012 11:17:59 -0500
parents 9f12ede5571a
children 22cee0ee8927
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1 /*
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7ab5f6318694 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
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26 #define CPU_X86_VM_VM_VERSION_X86_HPP
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27
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28 #include "runtime/globals_extension.hpp"
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29 #include "runtime/vm_version.hpp"
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30
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31 class VM_Version : public Abstract_VM_Version {
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32 public:
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33 // cpuid result register layouts. These are all unions of a uint32_t
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34 // (in case anyone wants access to the register as a whole) and a bitfield.
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35
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36 union StdCpuid1Eax {
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37 uint32_t value;
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38 struct {
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39 uint32_t stepping : 4,
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40 model : 4,
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41 family : 4,
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42 proc_type : 2,
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43 : 2,
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44 ext_model : 4,
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45 ext_family : 8,
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46 : 4;
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47 } bits;
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48 };
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49
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50 union StdCpuid1Ebx { // example, unused
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51 uint32_t value;
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52 struct {
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53 uint32_t brand_id : 8,
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54 clflush_size : 8,
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55 threads_per_cpu : 8,
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56 apic_id : 8;
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57 } bits;
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58 };
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59
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60 union StdCpuid1Ecx {
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61 uint32_t value;
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62 struct {
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63 uint32_t sse3 : 1,
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64 : 2,
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65 monitor : 1,
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66 : 1,
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67 vmx : 1,
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68 : 1,
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69 est : 1,
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70 : 1,
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71 ssse3 : 1,
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72 cid : 1,
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73 : 2,
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74 cmpxchg16: 1,
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75 : 4,
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76 dca : 1,
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77 sse4_1 : 1,
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78 sse4_2 : 1,
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79 : 2,
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80 popcnt : 1,
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81 : 8;
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82 } bits;
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83 };
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84
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85 union StdCpuid1Edx {
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86 uint32_t value;
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87 struct {
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88 uint32_t : 4,
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89 tsc : 1,
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90 : 3,
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91 cmpxchg8 : 1,
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92 : 6,
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93 cmov : 1,
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94 : 3,
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95 clflush : 1,
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96 : 3,
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97 mmx : 1,
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98 fxsr : 1,
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99 sse : 1,
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100 sse2 : 1,
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101 : 1,
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102 ht : 1,
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103 : 3;
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104 } bits;
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105 };
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106
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107 union DcpCpuid4Eax {
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108 uint32_t value;
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109 struct {
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110 uint32_t cache_type : 5,
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111 : 21,
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112 cores_per_cpu : 6;
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113 } bits;
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114 };
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115
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116 union DcpCpuid4Ebx {
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117 uint32_t value;
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118 struct {
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119 uint32_t L1_line_size : 12,
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120 partitions : 10,
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121 associativity : 10;
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122 } bits;
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123 };
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124
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125 union TplCpuidBEbx {
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126 uint32_t value;
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127 struct {
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128 uint32_t logical_cpus : 16,
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129 : 16;
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130 } bits;
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131 };
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132
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133 union ExtCpuid1Ecx {
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134 uint32_t value;
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135 struct {
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136 uint32_t LahfSahf : 1,
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137 CmpLegacy : 1,
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138 : 4,
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139 lzcnt : 1,
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140 sse4a : 1,
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141 misalignsse : 1,
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142 prefetchw : 1,
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143 : 22;
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144 } bits;
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145 };
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146
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147 union ExtCpuid1Edx {
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148 uint32_t value;
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149 struct {
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150 uint32_t : 22,
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151 mmx_amd : 1,
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152 mmx : 1,
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153 fxsr : 1,
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154 : 4,
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155 long_mode : 1,
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156 tdnow2 : 1,
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157 tdnow : 1;
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158 } bits;
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159 };
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160
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161 union ExtCpuid5Ex {
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162 uint32_t value;
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163 struct {
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164 uint32_t L1_line_size : 8,
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165 L1_tag_lines : 8,
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166 L1_assoc : 8,
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167 L1_size : 8;
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168 } bits;
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169 };
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170
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171 union ExtCpuid8Ecx {
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172 uint32_t value;
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173 struct {
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174 uint32_t cores_per_cpu : 8,
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175 : 24;
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176 } bits;
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177 };
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178
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179 union ExtCpuid7Edx {
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180 uint32_t value;
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181 struct {
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182 uint32_t : 8,
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183 tsc_invariance : 1,
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184 : 23;
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185 } bits;
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186 };
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187
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188 protected:
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189 static int _cpu;
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190 static int _model;
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191 static int _stepping;
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192 static int _cpuFeatures; // features returned by the "cpuid" instruction
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193 // 0 if this instruction is not available
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194 static const char* _features_str;
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195
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196 enum {
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197 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
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198 CPU_CMOV = (1 << 1),
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199 CPU_FXSR = (1 << 2),
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200 CPU_HT = (1 << 3),
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201 CPU_MMX = (1 << 4),
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202 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
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203 // may not necessarily support other 3dnow instructions
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204 CPU_SSE = (1 << 6),
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205 CPU_SSE2 = (1 << 7),
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206 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
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207 CPU_SSSE3 = (1 << 9),
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208 CPU_SSE4A = (1 << 10),
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209 CPU_SSE4_1 = (1 << 11),
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210 CPU_SSE4_2 = (1 << 12),
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211 CPU_POPCNT = (1 << 13),
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212 CPU_LZCNT = (1 << 14),
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213 CPU_TSC = (1 << 15),
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214 CPU_TSCINV = (1 << 16)
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215 } cpuFeatureFlags;
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216
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217 enum {
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218 // AMD
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219 CPU_FAMILY_AMD_11H = 17,
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220 // Intel
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221 CPU_FAMILY_INTEL_CORE = 6,
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222 CPU_MODEL_NEHALEM_EP = 26,
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223 CPU_MODEL_WESTMERE_EP = 44,
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224 // CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value
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225 CPU_MODEL_SANDYBRIDGE_EP = 45
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226 } cpuExtendedFamily;
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227
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228 // cpuid information block. All info derived from executing cpuid with
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229 // various function numbers is stored here. Intel and AMD info is
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230 // merged in this block: accessor methods disentangle it.
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231 //
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232 // The info block is laid out in subblocks of 4 dwords corresponding to
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233 // eax, ebx, ecx and edx, whether or not they contain anything useful.
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234 struct CpuidInfo {
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235 // cpuid function 0
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236 uint32_t std_max_function;
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237 uint32_t std_vendor_name_0;
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238 uint32_t std_vendor_name_1;
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239 uint32_t std_vendor_name_2;
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240
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241 // cpuid function 1
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242 StdCpuid1Eax std_cpuid1_eax;
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243 StdCpuid1Ebx std_cpuid1_ebx;
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244 StdCpuid1Ecx std_cpuid1_ecx;
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245 StdCpuid1Edx std_cpuid1_edx;
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246
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247 // cpuid function 4 (deterministic cache parameters)
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248 DcpCpuid4Eax dcp_cpuid4_eax;
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249 DcpCpuid4Ebx dcp_cpuid4_ebx;
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250 uint32_t dcp_cpuid4_ecx; // unused currently
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251 uint32_t dcp_cpuid4_edx; // unused currently
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252
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253 // cpuid function 0xB (processor topology)
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254 // ecx = 0
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255 uint32_t tpl_cpuidB0_eax;
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256 TplCpuidBEbx tpl_cpuidB0_ebx;
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257 uint32_t tpl_cpuidB0_ecx; // unused currently
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258 uint32_t tpl_cpuidB0_edx; // unused currently
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259
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260 // ecx = 1
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261 uint32_t tpl_cpuidB1_eax;
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262 TplCpuidBEbx tpl_cpuidB1_ebx;
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263 uint32_t tpl_cpuidB1_ecx; // unused currently
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264 uint32_t tpl_cpuidB1_edx; // unused currently
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265
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266 // ecx = 2
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267 uint32_t tpl_cpuidB2_eax;
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268 TplCpuidBEbx tpl_cpuidB2_ebx;
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269 uint32_t tpl_cpuidB2_ecx; // unused currently
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270 uint32_t tpl_cpuidB2_edx; // unused currently
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271
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272 // cpuid function 0x80000000 // example, unused
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273 uint32_t ext_max_function;
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274 uint32_t ext_vendor_name_0;
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275 uint32_t ext_vendor_name_1;
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276 uint32_t ext_vendor_name_2;
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277
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278 // cpuid function 0x80000001
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279 uint32_t ext_cpuid1_eax; // reserved
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280 uint32_t ext_cpuid1_ebx; // reserved
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281 ExtCpuid1Ecx ext_cpuid1_ecx;
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282 ExtCpuid1Edx ext_cpuid1_edx;
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283
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284 // cpuid functions 0x80000002 thru 0x80000004: example, unused
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285 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
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286 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
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287 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
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288
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289 // cpuid function 0x80000005 //AMD L1, Intel reserved
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290 uint32_t ext_cpuid5_eax; // unused currently
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291 uint32_t ext_cpuid5_ebx; // reserved
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292 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
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293 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
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294
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295 // cpuid function 0x80000007
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296 uint32_t ext_cpuid7_eax; // reserved
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297 uint32_t ext_cpuid7_ebx; // reserved
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298 uint32_t ext_cpuid7_ecx; // reserved
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299 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
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300
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301 // cpuid function 0x80000008
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302 uint32_t ext_cpuid8_eax; // unused currently
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303 uint32_t ext_cpuid8_ebx; // reserved
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304 ExtCpuid8Ecx ext_cpuid8_ecx;
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305 uint32_t ext_cpuid8_edx; // reserved
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306 };
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307
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308 // The actual cpuid info block
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309 static CpuidInfo _cpuid_info;
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310
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311 // Extractors and predicates
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312 static uint32_t extended_cpu_family() {
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313 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
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314 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
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315 return result;
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316 }
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317
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318 static uint32_t extended_cpu_model() {
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319 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
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320 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
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321 return result;
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322 }
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323
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324 static uint32_t cpu_stepping() {
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325 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
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326 return result;
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327 }
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328
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329 static uint logical_processor_count() {
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330 uint result = threads_per_core();
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331 return result;
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332 }
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333
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334 static uint32_t feature_flags() {
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335 uint32_t result = 0;
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336 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
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337 result |= CPU_CX8;
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338 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
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339 result |= CPU_CMOV;
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340 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
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341 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
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342 result |= CPU_FXSR;
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343 // HT flag is set for multi-core processors also.
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344 if (threads_per_core() > 1)
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345 result |= CPU_HT;
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346 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
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347 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
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348 result |= CPU_MMX;
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349 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
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350 result |= CPU_SSE;
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351 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
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352 result |= CPU_SSE2;
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353 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
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354 result |= CPU_SSE3;
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355 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
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356 result |= CPU_SSSE3;
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357 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
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358 result |= CPU_SSE4_1;
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359 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
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360 result |= CPU_SSE4_2;
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361 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
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362 result |= CPU_POPCNT;
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363 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
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364 result |= CPU_TSC;
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365 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
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366 result |= CPU_TSCINV;
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367
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368 // AMD features.
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369 if (is_amd()) {
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370 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
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371 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
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372 result |= CPU_3DNOW_PREFETCH;
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373 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
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374 result |= CPU_LZCNT;
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375 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
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376 result |= CPU_SSE4A;
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377 }
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378
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379 return result;
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380 }
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381
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382 static void get_processor_features();
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383
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384 public:
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385 // Offsets for cpuid asm stub
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386 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
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387 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
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388 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
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389 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
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390 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
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391 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
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392 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
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393 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
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394 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
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395 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
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396
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397 // Initialization
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398 static void initialize();
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399
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400 // Asserts
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401 static void assert_is_initialized() {
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402 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
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403 }
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404
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405 //
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406 // Processor family:
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407 // 3 - 386
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408 // 4 - 486
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409 // 5 - Pentium
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410 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
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411 // Pentium M, Core Solo, Core Duo, Core2 Duo
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412 // family 6 model: 9, 13, 14, 15
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413 // 0x0f - Pentium 4, Opteron
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414 //
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415 // Note: The cpu family should be used to select between
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416 // instruction sequences which are valid on all Intel
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417 // processors. Use the feature test functions below to
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418 // determine whether a particular instruction is supported.
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419 //
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420 static int cpu_family() { return _cpu;}
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421 static bool is_P6() { return cpu_family() >= 6; }
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422 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
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423 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
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424
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425 static bool supports_processor_topology() {
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426 return (_cpuid_info.std_max_function >= 0xB) &&
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427 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
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428 // Some cpus have max cpuid >= 0xB but do not support processor topology.
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429 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
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430 }
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431
585
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432 static uint cores_per_cpu() {
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433 uint result = 1;
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434 if (is_intel()) {
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435 if (supports_processor_topology()) {
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436 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
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437 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
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438 } else {
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439 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
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440 }
585
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441 } else if (is_amd()) {
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442 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
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443 }
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444 return result;
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445 }
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446
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447 static uint threads_per_core() {
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448 uint result = 1;
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449 if (is_intel() && supports_processor_topology()) {
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450 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
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451 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
585
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452 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
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453 cores_per_cpu();
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454 }
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455 return result;
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456 }
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457
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458 static intx prefetch_data_size() {
585
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459 intx result = 0;
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460 if (is_intel()) {
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461 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
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462 } else if (is_amd()) {
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463 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
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464 }
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465 if (result < 32) // not defined ?
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466 result = 32; // 32 bytes by default on x86 and other x64
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467 return result;
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468 }
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469
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470 //
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471 // Feature identification
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472 //
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473 static bool supports_cpuid() { return _cpuFeatures != 0; }
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474 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
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475 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
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476 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
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477 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
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478 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
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479 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
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480 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
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481 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
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482 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
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483 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
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484 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
643
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485 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
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486 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
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487
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488 // Intel features
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489 static bool is_intel_family_core() { return is_intel() &&
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490 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
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491
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492 static bool is_intel_tsc_synched_at_init() {
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493 if (is_intel_family_core()) {
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494 uint32_t ext_model = extended_cpu_model();
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495 if (ext_model == CPU_MODEL_NEHALEM_EP ||
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496 ext_model == CPU_MODEL_WESTMERE_EP ||
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497 // TODO ext_model == CPU_MODEL_IVYBRIDGE_EP ||
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498 ext_model == CPU_MODEL_SANDYBRIDGE_EP) {
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499 // 2-socket invtsc support. EX versions with 4 sockets are not
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500 // guaranteed to synchronize tscs at initialization via a double
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501 // handshake. The tscs can be explicitly set in software. Code
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502 // that uses tsc values must be prepared for them to arbitrarily
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503 // jump backward or forward.
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504 return true;
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505 }
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506 }
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507 return false;
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508 }
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509
585
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510 // AMD features
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511 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
585
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512 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
775
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513 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
585
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514 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
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515
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516 static bool is_amd_Barcelona() { return is_amd() &&
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517 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
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518
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519 // Intel and AMD newer cores support fast timestamps well
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520 static bool supports_tscinv_bit() {
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521 return (_cpuFeatures & CPU_TSCINV) != 0;
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522 }
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523 static bool supports_tscinv() {
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524 return supports_tscinv_bit() &&
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525 ( (is_amd() && !is_amd_Barcelona()) ||
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526 is_intel_tsc_synched_at_init() );
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527 }
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528
1914
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529 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
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530 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
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531 supports_sse3() && _model != 0x1C; }
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532
585
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533 static bool supports_compare_and_exchange() { return true; }
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534
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535 static const char* cpu_features() { return _features_str; }
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536
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537 static intx allocate_prefetch_distance() {
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538 // This method should be called before allocate_prefetch_style().
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539 //
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540 // Hardware prefetching (distance/size in bytes):
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541 // Pentium 3 - 64 / 32
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542 // Pentium 4 - 256 / 128
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543 // Athlon - 64 / 32 ????
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544 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
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545 // Core - 128 / 64
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546 //
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547 // Software prefetching (distance in bytes / instruction with best score):
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548 // Pentium 3 - 128 / prefetchnta
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549 // Pentium 4 - 512 / prefetchnta
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550 // Athlon - 128 / prefetchnta
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551 // Opteron - 256 / prefetchnta
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552 // Core - 256 / prefetchnta
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553 // It will be used only when AllocatePrefetchStyle > 0
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554
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555 intx count = AllocatePrefetchDistance;
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556 if (count < 0) { // default ?
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557 if (is_amd()) { // AMD
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558 if (supports_sse2())
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559 count = 256; // Opteron
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560 else
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561 count = 128; // Athlon
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562 } else { // Intel
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563 if (supports_sse2())
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564 if (cpu_family() == 6) {
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565 count = 256; // Pentium M, Core, Core2
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566 } else {
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567 count = 512; // Pentium 4
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568 }
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569 else
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570 count = 128; // Pentium 3 (and all other old CPUs)
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571 }
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572 }
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573 return count;
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574 }
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575 static intx allocate_prefetch_style() {
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576 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
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577 // Return 0 if AllocatePrefetchDistance was not defined.
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578 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
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579 }
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580
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581 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
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582 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
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583 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
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584 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
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585
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586 // gc copy/scan is disabled if prefetchw isn't supported, because
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587 // Prefetch::write emits an inlined prefetchw on Linux.
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588 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
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589 // The used prefetcht0 instruction works for both amd64 and em64t.
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590 static intx prefetch_copy_interval_in_bytes() {
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591 intx interval = PrefetchCopyIntervalInBytes;
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592 return interval >= 0 ? interval : 576;
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593 }
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594 static intx prefetch_scan_interval_in_bytes() {
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595 intx interval = PrefetchScanIntervalInBytes;
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596 return interval >= 0 ? interval : 576;
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597 }
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598 static intx prefetch_fields_ahead() {
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599 intx count = PrefetchFieldsAhead;
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600 return count >= 0 ? count : 1;
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601 }
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602 };
1972
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603
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604 #endif // CPU_X86_VM_VM_VERSION_X86_HPP