truffle: src/cpu/x86/vm/x86.ad annotate

annotate src/cpu/x86/vm/x86.ad @ 6225:2c368ea3e844

7181494: cleanup avx and vectors code Summary: renamed mach nodes which use scalar AVX instructions, added integer vectors shuffling instructions Reviewed-by: twisti

author	kvn
date	Mon, 16 Jul 2012 17:10:22 -0700
parents	6f8f439e247d
children	006050192a5a

rev	line source
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1 //
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	2 // Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	4 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	5 // This code is free software; you can redistribute it and/or modify it
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	6 // under the terms of the GNU General Public License version 2 only, as
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	7 // published by the Free Software Foundation.
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	8 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	9 // This code is distributed in the hope that it will be useful, but WITHOUT
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	12 // version 2 for more details (a copy is included in the LICENSE file that
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	13 // accompanied this code).
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	14 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	15 // You should have received a copy of the GNU General Public License version
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	16 // 2 along with this work; if not, write to the Free Software Foundation,
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	18 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	20 // or visit www.oracle.com if you need additional information or have any
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	21 // questions.
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	22 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	23 //
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	24
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	25 // X86 Common Architecture Description File
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	26
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	27 //----------REGISTER DEFINITION BLOCK------------------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	28 // This information is used by the matcher and the register allocator to
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	29 // describe individual registers and classes of registers within the target
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	30 // archtecture.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	31
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	32 register %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	33 //----------Architecture Description Register Definitions----------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	34 // General Registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	35 // "reg_def" name ( register save type, C convention save type,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	36 // ideal register type, encoding );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	37 // Register Save Types:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	38 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	39 // NS = No-Save: The register allocator assumes that these registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	40 // can be used without saving upon entry to the method, &
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	41 // that they do not need to be saved at call sites.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	42 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	43 // SOC = Save-On-Call: The register allocator assumes that these registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	44 // can be used without saving upon entry to the method,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	45 // but that they must be saved at call sites.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	46 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	47 // SOE = Save-On-Entry: The register allocator assumes that these registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	48 // must be saved before using them upon entry to the
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	49 // method, but they do not need to be saved at call
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	50 // sites.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	51 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	52 // AS = Always-Save: The register allocator assumes that these registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	53 // must be saved before using them upon entry to the
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	54 // method, & that they must be saved at call sites.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	55 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	56 // Ideal Register Type is used to determine how to save & restore a
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	59 //
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	60 // The encoding number is the actual bit-pattern placed into the opcodes.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	61
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	62 // XMM registers. 256-bit registers or 8 words each, labeled (a)-h.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	63 // Word a in each register holds a Float, words ab hold a Double.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	64 // The whole registers are used in SSE4.2 version intrinsics,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	65 // array copy stubs and superword operations (see UseSSE42Intrinsics,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	66 // UseXMMForArrayCopy and UseSuperword flags).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	67 // XMM8-XMM15 must be encoded with REX (VEX for UseAVX).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	68 // Linux ABI: No register preserved across function calls
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	69 // XMM0-XMM7 might hold parameters
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	70 // Windows ABI: XMM6-XMM15 preserved across function calls
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	71 // XMM0-XMM3 might hold parameters
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	72
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	73 reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	74 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	75 reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	76 reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	77 reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	78 reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	79 reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	80 reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	81
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	82 reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	83 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	84 reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	85 reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	86 reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	87 reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	88 reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	89 reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	90
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	91 reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	92 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	93 reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	94 reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	95 reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	96 reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	97 reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	98 reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	99
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	100 reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	101 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	102 reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	103 reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	104 reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	105 reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	106 reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	107 reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	108
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	109 reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	110 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	111 reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	112 reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	113 reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	114 reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	115 reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	116 reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	117
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	118 reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	119 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	120 reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	121 reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	122 reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	123 reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	124 reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	125 reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	126
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	127 #ifdef _WIN64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	128
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	129 reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	130 reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	131 reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	132 reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	133 reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	134 reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	135 reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	136 reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	137
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	138 reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	139 reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	140 reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	141 reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	142 reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	143 reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	144 reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	145 reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	146
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	147 reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	148 reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	149 reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	150 reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	151 reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	152 reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	153 reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	154 reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	155
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	156 reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	157 reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	158 reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	159 reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	160 reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	161 reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	162 reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	163 reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	164
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	165 reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	166 reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	167 reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	168 reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	169 reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	170 reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	171 reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	172 reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	173
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	174 reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	175 reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	176 reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	177 reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	178 reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	179 reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	180 reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	181 reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	182
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	183 reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	184 reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	185 reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	186 reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	187 reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	188 reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	189 reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	190 reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	191
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	192 reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	193 reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	194 reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	195 reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	196 reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	197 reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	198 reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	199 reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	200
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	201 reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	202 reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	203 reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	204 reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	205 reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	206 reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	207 reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	208 reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	209
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	210 reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	211 reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	212 reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	213 reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	214 reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	215 reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	216 reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	217 reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	218
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	219 #else // _WIN64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	220
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	221 reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	222 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	223 reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	224 reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	225 reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	226 reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	227 reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	228 reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	229
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	230 reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	231 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	232 reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	233 reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	234 reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	235 reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	236 reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	237 reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	238
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	239 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	240
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	241 reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	242 reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	243 reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	244 reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	245 reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	246 reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	247 reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	248 reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	249
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	250 reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	251 reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	252 reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	253 reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	254 reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	255 reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	256 reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	257 reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	258
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	259 reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	260 reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	261 reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	262 reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	263 reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	264 reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	265 reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	266 reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	267
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	268 reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	269 reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	270 reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	271 reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	272 reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	273 reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	274 reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	275 reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	276
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	277 reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	278 reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	279 reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	280 reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	281 reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	282 reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	283 reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	284 reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	285
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	286 reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	287 reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	288 reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	289 reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	290 reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	291 reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	292 reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	293 reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	294
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	295 reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	296 reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	297 reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	298 reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	299 reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	300 reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	301 reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	302 reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	303
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	304 reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	305 reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(1));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	306 reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(2));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	307 reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(3));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	308 reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(4));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	309 reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(5));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	310 reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(6));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	311 reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(7));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	312
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	313 #endif // _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	314
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	315 #endif // _WIN64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	316
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	317 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	318 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	319 #else
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	320 reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	321 #endif // _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	322
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	323 alloc_class chunk1(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	324 XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	325 XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	326 XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	327 XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	328 XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	329 XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	330 XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	331 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	332 ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	333 XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	334 XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	335 XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	336 XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	337 XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	338 XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	339 XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	340 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	341 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	342
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	343 // flags allocation class should be last.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	344 alloc_class chunk2(RFLAGS);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	345
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	346 // Singleton class for condition codes
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	347 reg_class int_flags(RFLAGS);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	348
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	349 // Class for all float registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	350 reg_class float_reg(XMM0,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	351 XMM1,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	352 XMM2,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	353 XMM3,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	354 XMM4,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	355 XMM5,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	356 XMM6,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	357 XMM7
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	358 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	359 ,XMM8,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	360 XMM9,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	361 XMM10,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	362 XMM11,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	363 XMM12,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	364 XMM13,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	365 XMM14,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	366 XMM15
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	367 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	368 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	369
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	370 // Class for all double registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	371 reg_class double_reg(XMM0, XMM0b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	372 XMM1, XMM1b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	373 XMM2, XMM2b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	374 XMM3, XMM3b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	375 XMM4, XMM4b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	376 XMM5, XMM5b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	377 XMM6, XMM6b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	378 XMM7, XMM7b
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	379 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	380 ,XMM8, XMM8b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	381 XMM9, XMM9b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	382 XMM10, XMM10b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	383 XMM11, XMM11b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	384 XMM12, XMM12b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	385 XMM13, XMM13b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	386 XMM14, XMM14b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	387 XMM15, XMM15b
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	388 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	389 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	390
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	391 // Class for all 32bit vector registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	392 reg_class vectors_reg(XMM0,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	393 XMM1,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	394 XMM2,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	395 XMM3,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	396 XMM4,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	397 XMM5,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	398 XMM6,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	399 XMM7
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	400 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	401 ,XMM8,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	402 XMM9,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	403 XMM10,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	404 XMM11,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	405 XMM12,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	406 XMM13,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	407 XMM14,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	408 XMM15
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	409 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	410 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	411
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	412 // Class for all 64bit vector registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	413 reg_class vectord_reg(XMM0, XMM0b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	414 XMM1, XMM1b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	415 XMM2, XMM2b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	416 XMM3, XMM3b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	417 XMM4, XMM4b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	418 XMM5, XMM5b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	419 XMM6, XMM6b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	420 XMM7, XMM7b
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	421 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	422 ,XMM8, XMM8b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	423 XMM9, XMM9b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	424 XMM10, XMM10b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	425 XMM11, XMM11b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	426 XMM12, XMM12b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	427 XMM13, XMM13b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	428 XMM14, XMM14b,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	429 XMM15, XMM15b
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	430 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	431 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	432
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	433 // Class for all 128bit vector registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	434 reg_class vectorx_reg(XMM0, XMM0b, XMM0c, XMM0d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	435 XMM1, XMM1b, XMM1c, XMM1d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	436 XMM2, XMM2b, XMM2c, XMM2d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	437 XMM3, XMM3b, XMM3c, XMM3d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	438 XMM4, XMM4b, XMM4c, XMM4d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	439 XMM5, XMM5b, XMM5c, XMM5d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	440 XMM6, XMM6b, XMM6c, XMM6d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	441 XMM7, XMM7b, XMM7c, XMM7d
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	442 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	443 ,XMM8, XMM8b, XMM8c, XMM8d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	444 XMM9, XMM9b, XMM9c, XMM9d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	445 XMM10, XMM10b, XMM10c, XMM10d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	446 XMM11, XMM11b, XMM11c, XMM11d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	447 XMM12, XMM12b, XMM12c, XMM12d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	448 XMM13, XMM13b, XMM13c, XMM13d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	449 XMM14, XMM14b, XMM14c, XMM14d,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	450 XMM15, XMM15b, XMM15c, XMM15d
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	451 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	452 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	453
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	454 // Class for all 256bit vector registers
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	455 reg_class vectory_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	456 XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	457 XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	458 XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	459 XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	460 XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	461 XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	462 XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	463 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	464 ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	465 XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	466 XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	467 XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	468 XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	469 XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	470 XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	471 XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	472 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	473 );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	474
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	475 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	476
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	477 source %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	478 // Float masks come from different places depending on platform.
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	479 #ifdef _LP64
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	480 static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	481 static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	482 static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	483 static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	484 #else
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	485 static address float_signmask() { return (address)float_signmask_pool; }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	486 static address float_signflip() { return (address)float_signflip_pool; }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	487 static address double_signmask() { return (address)double_signmask_pool; }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	488 static address double_signflip() { return (address)double_signflip_pool; }
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	489 #endif
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	490
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	491 // Map Types to machine register types
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	492 const int Matcher::base2reg[Type::lastype] = {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	493 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	494 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	495 Op_VecS, Op_VecD, Op_VecX, Op_VecY, /* Vectors */
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	496 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	497 0, 0/abio/,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	498 Op_RegP /* Return address /, 0, / the memories */
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	499 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	500 0 /bottom/
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	501 };
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	502
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	503 // Max vector size in bytes. 0 if not supported.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	504 const int Matcher::vector_width_in_bytes(BasicType bt) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	505 assert(is_java_primitive(bt), "only primitive type vectors");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	506 if (UseSSE < 2) return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	507 // SSE2 supports 128bit vectors for all types.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	508 // AVX2 supports 256bit vectors for all types.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	509 int size = (UseAVX > 1) ? 32 : 16;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	510 // AVX1 supports 256bit vectors only for FLOAT and DOUBLE.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	511 if (UseAVX > 0 && (bt == T_FLOAT \|\| bt == T_DOUBLE))
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	512 size = 32;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	513 // Use flag to limit vector size.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	514 size = MIN2(size,(int)MaxVectorSize);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	515 // Minimum 2 values in vector (or 4 for bytes).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	516 switch (bt) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	517 case T_DOUBLE:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	518 case T_LONG:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	519 if (size < 16) return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	520 case T_FLOAT:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	521 case T_INT:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	522 if (size < 8) return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	523 case T_BOOLEAN:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	524 case T_BYTE:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	525 case T_CHAR:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	526 case T_SHORT:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	527 if (size < 4) return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	528 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	529 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	530 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	531 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	532 return size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	533 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	534
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	535 // Limits on vector size (number of elements) loaded into vector.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	536 const int Matcher::max_vector_size(const BasicType bt) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	537 return vector_width_in_bytes(bt)/type2aelembytes(bt);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	538 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	539 const int Matcher::min_vector_size(const BasicType bt) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	540 int max_size = max_vector_size(bt);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	541 // Min size which can be loaded into vector is 4 bytes.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	542 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	543 return MIN2(size,max_size);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	544 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	545
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	546 // Vector ideal reg corresponding to specidied size in bytes
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	547 const int Matcher::vector_ideal_reg(int size) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	548 assert(MaxVectorSize >= size, "");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	549 switch(size) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	550 case 4: return Op_VecS;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	551 case 8: return Op_VecD;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	552 case 16: return Op_VecX;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	553 case 32: return Op_VecY;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	554 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	555 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	556 return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	557 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	558
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	559 // x86 supports misaligned vectors store/load.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	560 const bool Matcher::misaligned_vectors_ok() {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	561 return !AlignVector; // can be changed by flag
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	562 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	563
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	564 // Helper methods for MachSpillCopyNode::implementation().
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	565 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	566 int src_hi, int dst_hi, uint ireg, outputStream* st) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	567 // In 64-bit VM size calculation is very complex. Emitting instructions
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	568 // into scratch buffer is used to get size in 64-bit VM.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	569 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	570 assert(ireg == Op_VecS \|\| // 32bit vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	571 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	572 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	573 "no non-adjacent vector moves" );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	574 if (cbuf) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	575 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	576 int offset = __ offset();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	577 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	578 case Op_VecS: // copy whole register
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	579 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	580 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	581 __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	582 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	583 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	584 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	585 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	586 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	587 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	588 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	589 int size = __ offset() - offset;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	590 #ifdef ASSERT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	591 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	592 assert(!do_size \|\| size == 4, "incorrect size calculattion");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	593 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	594 return size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	595 #ifndef PRODUCT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	596 } else if (!do_size) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	597 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	598 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	599 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	600 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	601 st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	602 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	603 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	604 st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	605 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	606 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	607 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	608 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	609 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	610 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	611 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	612 return 4;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	613 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	614
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	615 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	616 int stack_offset, int reg, uint ireg, outputStream* st) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	617 // In 64-bit VM size calculation is very complex. Emitting instructions
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	618 // into scratch buffer is used to get size in 64-bit VM.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	619 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	620 if (cbuf) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	621 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	622 int offset = __ offset();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	623 if (is_load) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	624 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	625 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	626 __ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	627 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	628 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	629 __ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	630 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	631 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	632 __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	633 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	634 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	635 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	636 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	637 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	638 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	639 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	640 } else { // store
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	641 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	642 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	643 __ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	644 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	645 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	646 __ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	647 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	648 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	649 __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	650 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	651 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	652 __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	653 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	654 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	655 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	656 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	657 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	658 int size = __ offset() - offset;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	659 #ifdef ASSERT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	660 int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	661 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	662 assert(!do_size \|\| size == (5+offset_size), "incorrect size calculattion");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	663 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	664 return size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	665 #ifndef PRODUCT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	666 } else if (!do_size) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	667 if (is_load) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	668 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	669 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	670 st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	671 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	672 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	673 st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	674 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	675 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	676 st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	677 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	678 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	679 st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	680 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	681 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	682 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	683 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	684 } else { // store
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	685 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	686 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	687 st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	688 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	689 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	690 st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	691 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	692 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	693 st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	694 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	695 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	696 st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	697 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	698 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	699 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	700 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	701 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	702 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	703 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	704 int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	705 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	706 return 5+offset_size;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	707 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	708
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	709 static inline jfloat replicate4_imm(int con, int width) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	710 // Load a constant of "width" (in bytes) and replicate it to fill 32bit.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	711 assert(width == 1 \|\| width == 2, "only byte or short types here");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	712 int bit_width = width * 8;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	713 jint val = con;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	714 val &= (1 << bit_width) - 1; // mask off sign bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	715 while(bit_width < 32) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	716 val \|= (val << bit_width);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	717 bit_width <<= 1;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	718 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	719 jfloat fval = ((jfloat) &val); // coerce to float type
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	720 return fval;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	721 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	722
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	723 static inline jdouble replicate8_imm(int con, int width) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	724 // Load a constant of "width" (in bytes) and replicate it to fill 64bit.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	725 assert(width == 1 \|\| width == 2 \|\| width == 4, "only byte, short or int types here");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	726 int bit_width = width * 8;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	727 jlong val = con;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	729 while(bit_width < 64) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	730 val \|= (val << bit_width);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	731 bit_width <<= 1;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	732 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	733 jdouble dval = ((jdouble) &val); // coerce to double type
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	734 return dval;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	735 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	736
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	737 #ifndef PRODUCT
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	738 void MachNopNode::format(PhaseRegAlloc, outputStream st) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	739 st->print("nop \t# %d bytes pad for loops and calls", _count);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	740 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	741 #endif
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	742
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	743 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	744 MacroAssembler _masm(&cbuf);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	745 __ nop(_count);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	746 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	747
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	748 uint MachNopNode::size(PhaseRegAlloc*) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	749 return _count;
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	750 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	751
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	752 #ifndef PRODUCT
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	753 void MachBreakpointNode::format(PhaseRegAlloc, outputStream st) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	754 st->print("# breakpoint");
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	755 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	756 #endif
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	757
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	758 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	759 MacroAssembler _masm(&cbuf);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	760 __ int3();
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	761 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	762
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	763 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	764 return MachNode::size(ra_);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	765 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	766
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	767 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	768
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	769 encode %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	770
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	771 enc_class preserve_SP %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	772 debug_only(int off0 = cbuf.insts_size());
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	773 MacroAssembler _masm(&cbuf);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	774 // RBP is preserved across all calls, even compiled calls.
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	775 // Use it to preserve RSP in places where the callee might change the SP.
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	776 __ movptr(rbp_mh_SP_save, rsp);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	777 debug_only(int off1 = cbuf.insts_size());
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	778 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	779 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	780
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	781 enc_class restore_SP %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	782 MacroAssembler _masm(&cbuf);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	783 __ movptr(rsp, rbp_mh_SP_save);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	784 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	785
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	786 enc_class call_epilog %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	787 if (VerifyStackAtCalls) {
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	788 // Check that stack depth is unchanged: find majik cookie on stack
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	789 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	790 MacroAssembler _masm(&cbuf);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	791 Label L;
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	792 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	793 __ jccb(Assembler::equal, L);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	794 // Die if stack mismatch
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	795 __ int3();
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	796 __ bind(L);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	797 }
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	798 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	799
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	800 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	801
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	802
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	803 //----------OPERANDS-----------------------------------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	804 // Operand definitions must precede instruction definitions for correct parsing
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	805 // in the ADLC because operands constitute user defined types which are used in
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	806 // instruction definitions.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	807
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	808 // Vectors
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	809 operand vecS() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	810 constraint(ALLOC_IN_RC(vectors_reg));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	811 match(VecS);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	812
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	813 format %{ %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	814 interface(REG_INTER);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	815 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	816
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	817 operand vecD() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	818 constraint(ALLOC_IN_RC(vectord_reg));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	819 match(VecD);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	820
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	821 format %{ %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	822 interface(REG_INTER);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	823 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	824
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	825 operand vecX() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	826 constraint(ALLOC_IN_RC(vectorx_reg));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	827 match(VecX);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	828
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	829 format %{ %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	830 interface(REG_INTER);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	831 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	832
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	833 operand vecY() %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	834 constraint(ALLOC_IN_RC(vectory_reg));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	835 match(VecY);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	836
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	837 format %{ %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	838 interface(REG_INTER);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	839 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	840
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	841
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	842 // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	843
4950 9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	844 // ============================================================================
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	845
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	846 instruct ShouldNotReachHere() %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	847 match(Halt);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	848 format %{ "int3\t# ShouldNotReachHere" %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	849 ins_encode %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	850 __ int3();
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	851 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	852 ins_pipe(pipe_slow);
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	853 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	854
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	855 // ============================================================================
9b8ce46870df 7145346: VerifyStackAtCalls is broken kvn parents: 4761 diff changeset	856
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	857 instruct addF_reg(regF dst, regF src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	858 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	859 match(Set dst (AddF dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	860
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	861 format %{ "addss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	862 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	863 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	864 __ addss($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	865 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	866 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	867 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	868
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	869 instruct addF_mem(regF dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	870 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	871 match(Set dst (AddF dst (LoadF src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	872
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	873 format %{ "addss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	874 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	875 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	876 __ addss($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	877 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	878 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	879 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	880
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	881 instruct addF_imm(regF dst, immF con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	882 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	883 match(Set dst (AddF dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	884 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	885 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	886 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	887 __ addss($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	888 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	889 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	890 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	891
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	892 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	893 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	894 match(Set dst (AddF src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	895
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	896 format %{ "vaddss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	897 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	898 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	899 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	900 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	901 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	902 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	903
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	904 instruct addF_reg_mem(regF dst, regF src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	905 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	906 match(Set dst (AddF src1 (LoadF src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	907
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	908 format %{ "vaddss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	909 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	910 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	911 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	912 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	913 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	914 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	915
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	916 instruct addF_reg_imm(regF dst, regF src, immF con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	917 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	918 match(Set dst (AddF src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	919
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	920 format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	921 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	922 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	923 __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	924 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	925 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	926 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	927
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	928 instruct addD_reg(regD dst, regD src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	929 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	930 match(Set dst (AddD dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	931
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	932 format %{ "addsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	933 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	934 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	935 __ addsd($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	936 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	937 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	938 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	939
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	940 instruct addD_mem(regD dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	941 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	942 match(Set dst (AddD dst (LoadD src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	943
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	944 format %{ "addsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	945 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	946 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	947 __ addsd($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	948 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	949 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	950 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	951
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	952 instruct addD_imm(regD dst, immD con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	953 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	954 match(Set dst (AddD dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	955 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	956 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	957 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	958 __ addsd($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	959 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	960 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	961 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	962
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	963 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	964 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	965 match(Set dst (AddD src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	966
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	967 format %{ "vaddsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	968 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	969 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	970 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	971 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	972 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	973 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	974
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	975 instruct addD_reg_mem(regD dst, regD src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	976 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	977 match(Set dst (AddD src1 (LoadD src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	978
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	979 format %{ "vaddsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	980 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	981 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	982 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	983 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	984 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	985 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	986
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	987 instruct addD_reg_imm(regD dst, regD src, immD con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	988 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	989 match(Set dst (AddD src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	990
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	991 format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	992 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	993 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	994 __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	995 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	996 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	997 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	998
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	999 instruct subF_reg(regF dst, regF src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1000 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1001 match(Set dst (SubF dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1002
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1003 format %{ "subss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1004 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1005 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1006 __ subss($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1007 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1008 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1009 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1010
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1011 instruct subF_mem(regF dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1012 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1013 match(Set dst (SubF dst (LoadF src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1014
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1015 format %{ "subss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1016 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1017 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1018 __ subss($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1019 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1020 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1021 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1022
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1023 instruct subF_imm(regF dst, immF con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1024 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1025 match(Set dst (SubF dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1026 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1027 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1028 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1029 __ subss($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1030 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1031 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1032 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1033
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1034 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1035 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1036 match(Set dst (SubF src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1037
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1038 format %{ "vsubss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1039 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1040 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1041 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1042 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1043 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1044 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1045
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1046 instruct subF_reg_mem(regF dst, regF src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1047 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1048 match(Set dst (SubF src1 (LoadF src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1049
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1050 format %{ "vsubss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1051 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1052 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1053 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1054 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1055 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1056 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1057
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1058 instruct subF_reg_imm(regF dst, regF src, immF con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1059 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1060 match(Set dst (SubF src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1061
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1062 format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1063 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1064 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1065 __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1066 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1067 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1068 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1069
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1070 instruct subD_reg(regD dst, regD src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1071 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1072 match(Set dst (SubD dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1073
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1074 format %{ "subsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1075 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1076 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1077 __ subsd($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1078 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1079 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1080 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1081
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1082 instruct subD_mem(regD dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1083 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1084 match(Set dst (SubD dst (LoadD src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1085
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1086 format %{ "subsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1087 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1088 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1089 __ subsd($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1090 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1091 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1092 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1093
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1094 instruct subD_imm(regD dst, immD con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1095 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1096 match(Set dst (SubD dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1097 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1098 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1099 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1100 __ subsd($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1101 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1102 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1103 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1104
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1105 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1106 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1107 match(Set dst (SubD src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1108
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1109 format %{ "vsubsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1110 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1111 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1112 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1113 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1114 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1115 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1116
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1117 instruct subD_reg_mem(regD dst, regD src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1118 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1119 match(Set dst (SubD src1 (LoadD src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1120
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1121 format %{ "vsubsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1122 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1123 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1124 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1125 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1126 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1127 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1128
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1129 instruct subD_reg_imm(regD dst, regD src, immD con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1130 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1131 match(Set dst (SubD src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1132
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1133 format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1134 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1135 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1136 __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1137 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1138 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1139 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1140
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1141 instruct mulF_reg(regF dst, regF src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1142 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1143 match(Set dst (MulF dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1144
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1145 format %{ "mulss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1146 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1147 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1148 __ mulss($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1149 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1150 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1151 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1152
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1153 instruct mulF_mem(regF dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1154 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1155 match(Set dst (MulF dst (LoadF src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1156
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1157 format %{ "mulss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1158 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1159 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1160 __ mulss($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1161 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1162 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1163 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1164
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1165 instruct mulF_imm(regF dst, immF con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1166 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1167 match(Set dst (MulF dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1168 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1169 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1170 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1171 __ mulss($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1172 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1173 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1174 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1175
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1176 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1177 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1178 match(Set dst (MulF src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1179
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1180 format %{ "vmulss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1181 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1182 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1183 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1184 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1185 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1186 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1187
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1188 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1189 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1190 match(Set dst (MulF src1 (LoadF src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1191
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1192 format %{ "vmulss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1193 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1194 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1195 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1196 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1197 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1198 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1199
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1200 instruct mulF_reg_imm(regF dst, regF src, immF con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1201 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1202 match(Set dst (MulF src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1203
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1204 format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1205 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1206 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1207 __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1208 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1209 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1210 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1211
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1212 instruct mulD_reg(regD dst, regD src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1213 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1214 match(Set dst (MulD dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1215
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1216 format %{ "mulsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1217 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1218 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1219 __ mulsd($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1220 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1221 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1222 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1223
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1224 instruct mulD_mem(regD dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1225 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1226 match(Set dst (MulD dst (LoadD src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1227
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1228 format %{ "mulsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1229 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1230 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1231 __ mulsd($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1232 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1233 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1234 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1235
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1236 instruct mulD_imm(regD dst, immD con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1237 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1238 match(Set dst (MulD dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1239 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1240 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1241 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1242 __ mulsd($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1243 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1244 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1245 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1246
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1247 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1248 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1249 match(Set dst (MulD src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1250
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1251 format %{ "vmulsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1252 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1253 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1254 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1255 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1256 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1257 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1258
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1259 instruct mulD_reg_mem(regD dst, regD src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1260 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1261 match(Set dst (MulD src1 (LoadD src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1262
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1263 format %{ "vmulsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1264 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1265 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1266 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1267 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1268 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1269 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1270
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1271 instruct mulD_reg_imm(regD dst, regD src, immD con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1272 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1273 match(Set dst (MulD src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1274
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1275 format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1276 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1277 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1278 __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1279 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1280 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1281 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1282
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1283 instruct divF_reg(regF dst, regF src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1284 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1285 match(Set dst (DivF dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1286
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1287 format %{ "divss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1288 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1289 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1290 __ divss($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1291 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1292 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1293 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1294
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1295 instruct divF_mem(regF dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1296 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1297 match(Set dst (DivF dst (LoadF src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1298
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1299 format %{ "divss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1300 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1301 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1302 __ divss($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1303 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1304 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1305 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1306
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1307 instruct divF_imm(regF dst, immF con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1308 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1309 match(Set dst (DivF dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1310 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1311 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1312 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1313 __ divss($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1314 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1315 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1316 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1317
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1318 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1319 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1320 match(Set dst (DivF src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1321
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1322 format %{ "vdivss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1323 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1324 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1325 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1326 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1327 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1328 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1329
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1330 instruct divF_reg_mem(regF dst, regF src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1331 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1332 match(Set dst (DivF src1 (LoadF src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1333
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1334 format %{ "vdivss $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1335 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1336 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1337 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1338 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1339 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1340 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1341
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1342 instruct divF_reg_imm(regF dst, regF src, immF con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1343 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1344 match(Set dst (DivF src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1345
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1346 format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1347 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1348 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1349 __ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1350 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1351 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1352 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1353
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1354 instruct divD_reg(regD dst, regD src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1355 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1356 match(Set dst (DivD dst src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1357
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1358 format %{ "divsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1359 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1360 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1361 __ divsd($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1362 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1363 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1364 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1365
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1366 instruct divD_mem(regD dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1367 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1368 match(Set dst (DivD dst (LoadD src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1369
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1370 format %{ "divsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1371 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1372 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1373 __ divsd($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1374 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1375 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1376 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1377
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1378 instruct divD_imm(regD dst, immD con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1379 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1380 match(Set dst (DivD dst con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1381 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1382 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1383 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1384 __ divsd($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1385 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1386 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1387 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1388
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1389 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1390 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1391 match(Set dst (DivD src1 src2));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1392
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1393 format %{ "vdivsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1394 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1395 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1396 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1397 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1398 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1399 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1400
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1401 instruct divD_reg_mem(regD dst, regD src1, memory src2) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1402 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1403 match(Set dst (DivD src1 (LoadD src2)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1404
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1405 format %{ "vdivsd $dst, $src1, $src2" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1406 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1407 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1408 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1409 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1410 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1411 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1412
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1413 instruct divD_reg_imm(regD dst, regD src, immD con) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1414 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1415 match(Set dst (DivD src con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1416
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1417 format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1418 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1419 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1420 __ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1421 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1422 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1423 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1424
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1425 instruct absF_reg(regF dst) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1426 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1427 match(Set dst (AbsF dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1428 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1429 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1430 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1431 __ andps($dst$$XMMRegister, ExternalAddress(float_signmask()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1432 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1433 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1434 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1435
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1436 instruct absF_reg_reg(regF dst, regF src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1437 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1438 match(Set dst (AbsF src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1439 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1440 format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1441 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1442 __ vandps($dst$$XMMRegister, $src$$XMMRegister,
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1443 ExternalAddress(float_signmask()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1444 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1445 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1446 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1447
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1448 instruct absD_reg(regD dst) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1449 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1450 match(Set dst (AbsD dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1451 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1452 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1453 "# abs double by sign masking" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1454 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1455 __ andpd($dst$$XMMRegister, ExternalAddress(double_signmask()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1456 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1457 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1458 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1459
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1460 instruct absD_reg_reg(regD dst, regD src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1461 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1462 match(Set dst (AbsD src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1463 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1464 format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t"
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1465 "# abs double by sign masking" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1466 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1467 __ vandpd($dst$$XMMRegister, $src$$XMMRegister,
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1468 ExternalAddress(double_signmask()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1469 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1470 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1471 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1472
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1473 instruct negF_reg(regF dst) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1474 predicate((UseSSE>=1) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1475 match(Set dst (NegF dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1476 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1477 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1478 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1479 __ xorps($dst$$XMMRegister, ExternalAddress(float_signflip()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1480 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1481 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1482 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1483
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1484 instruct negF_reg_reg(regF dst, regF src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1485 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1486 match(Set dst (NegF src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1487 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1488 format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1489 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1490 __ vxorps($dst$$XMMRegister, $src$$XMMRegister,
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1491 ExternalAddress(float_signflip()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1492 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1493 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1494 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1495
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1496 instruct negD_reg(regD dst) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1497 predicate((UseSSE>=2) && (UseAVX == 0));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1498 match(Set dst (NegD dst));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1499 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1500 format %{ "xorpd $dst, [0x8000000000000000]\t"
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1501 "# neg double by sign flipping" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1502 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1503 __ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1504 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1505 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1506 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1507
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1508 instruct negD_reg_reg(regD dst, regD src) %{
4761 65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1509 predicate(UseAVX > 0);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1510 match(Set dst (NegD src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1511 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1512 format %{ "vxorpd $dst, $src, [0x8000000000000000]\t"
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1513 "# neg double by sign flipping" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1514 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1515 __ vxorpd($dst$$XMMRegister, $src$$XMMRegister,
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1516 ExternalAddress(double_signflip()));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1517 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1518 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1519 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1520
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1521 instruct sqrtF_reg(regF dst, regF src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1522 predicate(UseSSE>=1);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1523 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1524
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1525 format %{ "sqrtss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1526 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1527 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1528 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1529 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1530 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1531 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1532
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1533 instruct sqrtF_mem(regF dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1534 predicate(UseSSE>=1);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1535 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1536
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1537 format %{ "sqrtss $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1538 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1539 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1540 __ sqrtss($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1541 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1542 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1543 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1544
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1545 instruct sqrtF_imm(regF dst, immF con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1546 predicate(UseSSE>=1);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1547 match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1548 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1549 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1550 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1551 __ sqrtss($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1552 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1553 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1554 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1555
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1556 instruct sqrtD_reg(regD dst, regD src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1557 predicate(UseSSE>=2);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1558 match(Set dst (SqrtD src));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1559
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1560 format %{ "sqrtsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1561 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1562 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1563 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1564 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1565 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1566 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1567
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1568 instruct sqrtD_mem(regD dst, memory src) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1569 predicate(UseSSE>=2);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1570 match(Set dst (SqrtD (LoadD src)));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1571
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1572 format %{ "sqrtsd $dst, $src" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1573 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1574 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1575 __ sqrtsd($dst$$XMMRegister, $src$$Address);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1576 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1577 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1578 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1579
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1580 instruct sqrtD_imm(regD dst, immD con) %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1581 predicate(UseSSE>=2);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1582 match(Set dst (SqrtD con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1583 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1584 ins_cost(150);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1585 ins_encode %{
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1586 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1587 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1588 ins_pipe(pipe_slow);
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1589 %}
65149e74c706 7121648: Use 3-operands SIMD instructions on x86 with AVX kvn parents: diff changeset	1590
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1591
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1592 // ====================VECTOR INSTRUCTIONS=====================================
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1593
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1594 // Load vectors (4 bytes long)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1595 instruct loadV4(vecS dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1596 predicate(n->as_LoadVector()->memory_size() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1597 match(Set dst (LoadVector mem));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1598 ins_cost(125);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1599 format %{ "movd $dst,$mem\t! load vector (4 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1600 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1601 __ movdl($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1602 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1603 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1604 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1605
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1606 // Load vectors (8 bytes long)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1607 instruct loadV8(vecD dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1608 predicate(n->as_LoadVector()->memory_size() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1609 match(Set dst (LoadVector mem));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1610 ins_cost(125);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1611 format %{ "movq $dst,$mem\t! load vector (8 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1612 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1613 __ movq($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1614 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1615 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1616 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1617
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1618 // Load vectors (16 bytes long)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1619 instruct loadV16(vecX dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1620 predicate(n->as_LoadVector()->memory_size() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1621 match(Set dst (LoadVector mem));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1622 ins_cost(125);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1623 format %{ "movdqu $dst,$mem\t! load vector (16 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1624 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1625 __ movdqu($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1626 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1627 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1628 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1629
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1630 // Load vectors (32 bytes long)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1631 instruct loadV32(vecY dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1632 predicate(n->as_LoadVector()->memory_size() == 32);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1633 match(Set dst (LoadVector mem));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1634 ins_cost(125);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1635 format %{ "vmovdqu $dst,$mem\t! load vector (32 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1636 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1637 __ vmovdqu($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1638 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1639 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1640 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1641
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1642 // Store vectors
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1643 instruct storeV4(memory mem, vecS src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1644 predicate(n->as_StoreVector()->memory_size() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1645 match(Set mem (StoreVector mem src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1646 ins_cost(145);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1647 format %{ "movd $mem,$src\t! store vector (4 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1648 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1649 __ movdl($mem$$Address, $src$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1650 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1651 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1652 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1653
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1654 instruct storeV8(memory mem, vecD src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1655 predicate(n->as_StoreVector()->memory_size() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1656 match(Set mem (StoreVector mem src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1657 ins_cost(145);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1658 format %{ "movq $mem,$src\t! store vector (8 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1659 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1660 __ movq($mem$$Address, $src$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1661 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1662 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1663 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1664
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1665 instruct storeV16(memory mem, vecX src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1666 predicate(n->as_StoreVector()->memory_size() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1667 match(Set mem (StoreVector mem src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1668 ins_cost(145);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1669 format %{ "movdqu $mem,$src\t! store vector (16 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1670 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1671 __ movdqu($mem$$Address, $src$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1672 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1673 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1674 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1675
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1676 instruct storeV32(memory mem, vecY src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1677 predicate(n->as_StoreVector()->memory_size() == 32);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1678 match(Set mem (StoreVector mem src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1679 ins_cost(145);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1680 format %{ "vmovdqu $mem,$src\t! store vector (32 bytes)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1681 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1682 __ vmovdqu($mem$$Address, $src$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1683 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1684 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1685 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1686
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1687 // Replicate byte scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1688 instruct Repl4B(vecS dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1689 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1690 match(Set dst (ReplicateB src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1691 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1692 "punpcklbw $dst,$dst\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1693 "pshuflw $dst,$dst,0x00\t! replicate4B" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1694 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1695 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1696 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1697 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1698 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1699 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1700 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1701
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1702 instruct Repl8B(vecD dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1703 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1704 match(Set dst (ReplicateB src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1705 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1706 "punpcklbw $dst,$dst\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1707 "pshuflw $dst,$dst,0x00\t! replicate8B" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1708 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1709 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1710 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1711 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1712 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1713 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1714 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1715
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1716 instruct Repl16B(vecX dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1717 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1718 match(Set dst (ReplicateB src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1719 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1720 "punpcklbw $dst,$dst\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1721 "pshuflw $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1722 "punpcklqdq $dst,$dst\t! replicate16B" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1723 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1724 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1725 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1726 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1727 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1728 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1729 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1730 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1731
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1732 instruct Repl32B(vecY dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1733 predicate(n->as_Vector()->length() == 32);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1734 match(Set dst (ReplicateB src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1735 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1736 "punpcklbw $dst,$dst\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1737 "pshuflw $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1738 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1739 "vinserti128h $dst,$dst,$dst\t! replicate32B" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1740 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1741 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1742 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1743 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1744 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1745 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1746 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1747 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1748 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1749
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1750 // Replicate byte scalar immediate to be vector by loading from const table.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1751 instruct Repl4B_imm(vecS dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1752 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1753 match(Set dst (ReplicateB con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1754 format %{ "movdl $dst,[$constantaddress]\t! replicate4B($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1755 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1756 __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1757 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1758 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1759 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1760
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1761 instruct Repl8B_imm(vecD dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1762 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1763 match(Set dst (ReplicateB con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1764 format %{ "movq $dst,[$constantaddress]\t! replicate8B($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1765 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1766 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1767 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1768 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1769 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1770
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1771 instruct Repl16B_imm(vecX dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1772 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1773 match(Set dst (ReplicateB con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1774 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1775 "punpcklqdq $dst,$dst\t! replicate16B($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1776 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1777 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1778 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1779 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1780 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1781 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1782
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1783 instruct Repl32B_imm(vecY dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1784 predicate(n->as_Vector()->length() == 32);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1785 match(Set dst (ReplicateB con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1786 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1787 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1788 "vinserti128h $dst,$dst,$dst\t! lreplicate32B($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1789 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1790 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1791 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1792 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1793 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1794 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1795 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1796
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1797 // Replicate byte scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1798 instruct Repl4B_zero(vecS dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1799 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1800 match(Set dst (ReplicateB zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1801 format %{ "pxor $dst,$dst\t! replicate4B zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1802 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1803 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1804 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1805 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1806 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1807
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1808 instruct Repl8B_zero(vecD dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1809 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1810 match(Set dst (ReplicateB zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1811 format %{ "pxor $dst,$dst\t! replicate8B zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1812 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1813 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1814 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1815 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1816 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1817
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1818 instruct Repl16B_zero(vecX dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1819 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1820 match(Set dst (ReplicateB zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1821 format %{ "pxor $dst,$dst\t! replicate16B zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1822 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1823 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1824 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1825 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1826 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1827
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1828 instruct Repl32B_zero(vecY dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1829 predicate(n->as_Vector()->length() == 32);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1830 match(Set dst (ReplicateB zero));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1831 format %{ "vpxor $dst,$dst,$dst\t! replicate32B zero" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1832 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1833 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1834 bool vector256 = true;
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1835 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1836 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1837 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1838 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1839
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1840 // Replicate char/short (2 byte) scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1841 instruct Repl2S(vecS dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1842 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1843 match(Set dst (ReplicateS src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1844 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1845 "pshuflw $dst,$dst,0x00\t! replicate2S" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1846 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1847 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1848 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1849 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1850 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1851 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1852
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1853 instruct Repl4S(vecD dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1854 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1855 match(Set dst (ReplicateS src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1856 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1857 "pshuflw $dst,$dst,0x00\t! replicate4S" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1858 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1859 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1860 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1861 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1862 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1863 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1864
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1865 instruct Repl8S(vecX dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1866 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1867 match(Set dst (ReplicateS src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1868 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1869 "pshuflw $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1870 "punpcklqdq $dst,$dst\t! replicate8S" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1871 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1872 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1873 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1874 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1875 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1876 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1877 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1878
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1879 instruct Repl16S(vecY dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1880 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1881 match(Set dst (ReplicateS src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1882 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1883 "pshuflw $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1884 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1885 "vinserti128h $dst,$dst,$dst\t! replicate16S" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1886 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1887 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1888 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1889 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1890 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1891 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1892 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1893 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1894
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1895 // Replicate char/short (2 byte) scalar immediate to be vector by loading from const table.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1896 instruct Repl2S_imm(vecS dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1897 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1898 match(Set dst (ReplicateS con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1899 format %{ "movdl $dst,[$constantaddress]\t! replicate2S($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1900 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1901 __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1902 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1903 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1904 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1905
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1906 instruct Repl4S_imm(vecD dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1907 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1908 match(Set dst (ReplicateS con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1909 format %{ "movq $dst,[$constantaddress]\t! replicate4S($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1910 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1911 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1912 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1913 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1914 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1915
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1916 instruct Repl8S_imm(vecX dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1917 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1918 match(Set dst (ReplicateS con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1919 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1920 "punpcklqdq $dst,$dst\t! replicate8S($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1921 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1922 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1923 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1924 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1925 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1926 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1927
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1928 instruct Repl16S_imm(vecY dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1929 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1930 match(Set dst (ReplicateS con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1931 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1932 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1933 "vinserti128h $dst,$dst,$dst\t! replicate16S($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1934 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1935 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1936 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1937 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1938 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1939 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1940 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1941
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1942 // Replicate char/short (2 byte) scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1943 instruct Repl2S_zero(vecS dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1944 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1945 match(Set dst (ReplicateS zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1946 format %{ "pxor $dst,$dst\t! replicate2S zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1947 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1948 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1949 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1950 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1951 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1952
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1953 instruct Repl4S_zero(vecD dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1954 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1955 match(Set dst (ReplicateS zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1956 format %{ "pxor $dst,$dst\t! replicate4S zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1957 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1958 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1959 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1960 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1961 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1962
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1963 instruct Repl8S_zero(vecX dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1964 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1965 match(Set dst (ReplicateS zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1966 format %{ "pxor $dst,$dst\t! replicate8S zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1967 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1968 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1969 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1970 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1971 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1972
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1973 instruct Repl16S_zero(vecY dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1974 predicate(n->as_Vector()->length() == 16);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1975 match(Set dst (ReplicateS zero));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1976 format %{ "vpxor $dst,$dst,$dst\t! replicate16S zero" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1977 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1978 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1979 bool vector256 = true;
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	1980 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1981 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1982 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1983 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1984
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1985 // Replicate integer (4 byte) scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1986 instruct Repl2I(vecD dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1987 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1988 match(Set dst (ReplicateI src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1989 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1990 "pshufd $dst,$dst,0x00\t! replicate2I" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1991 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1992 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1993 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1994 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1995 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1996 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1997
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1998 instruct Repl4I(vecX dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	1999 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2000 match(Set dst (ReplicateI src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2001 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2002 "pshufd $dst,$dst,0x00\t! replicate4I" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2003 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2004 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2005 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2006 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2007 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2008 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2009
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2010 instruct Repl8I(vecY dst, rRegI src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2011 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2012 match(Set dst (ReplicateI src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2013 format %{ "movd $dst,$src\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2014 "pshufd $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2015 "vinserti128h $dst,$dst,$dst\t! replicate8I" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2016 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2017 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2018 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2019 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2020 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2021 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2022 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2023
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2024 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2025 instruct Repl2I_imm(vecD dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2026 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2027 match(Set dst (ReplicateI con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2028 format %{ "movq $dst,[$constantaddress]\t! replicate2I($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2029 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2030 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2031 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2032 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2033 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2034
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2035 instruct Repl4I_imm(vecX dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2036 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2037 match(Set dst (ReplicateI con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2038 format %{ "movq $dst,[$constantaddress]\t! replicate4I($con)\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2039 "punpcklqdq $dst,$dst" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2040 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2041 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2042 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2043 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2044 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2045 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2046
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2047 instruct Repl8I_imm(vecY dst, immI con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2048 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2049 match(Set dst (ReplicateI con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2050 format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2051 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2052 "vinserti128h $dst,$dst,$dst" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2053 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2054 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4)));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2055 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2056 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2057 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2058 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2059 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2060
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2061 // Integer could be loaded into xmm register directly from memory.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2062 instruct Repl2I_mem(vecD dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2063 predicate(n->as_Vector()->length() == 2);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2064 match(Set dst (ReplicateI (LoadI mem)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2065 format %{ "movd $dst,$mem\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2066 "pshufd $dst,$dst,0x00\t! replicate2I" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2067 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2068 __ movdl($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2069 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2070 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2071 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2072 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2073
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2074 instruct Repl4I_mem(vecX dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2075 predicate(n->as_Vector()->length() == 4);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2076 match(Set dst (ReplicateI (LoadI mem)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2077 format %{ "movd $dst,$mem\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2078 "pshufd $dst,$dst,0x00\t! replicate4I" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2079 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2080 __ movdl($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2081 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2082 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2083 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2084 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2085
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2086 instruct Repl8I_mem(vecY dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2087 predicate(n->as_Vector()->length() == 8);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2088 match(Set dst (ReplicateI (LoadI mem)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2089 format %{ "movd $dst,$mem\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2090 "pshufd $dst,$dst,0x00\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2091 "vinserti128h $dst,$dst,$dst\t! replicate8I" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2092 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2093 __ movdl($dst$$XMMRegister, $mem$$Address);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2094 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2095 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2096 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2097 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2098 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2099
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2100 // Replicate integer (4 byte) scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2101 instruct Repl2I_zero(vecD dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2102 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2103 match(Set dst (ReplicateI zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2104 format %{ "pxor $dst,$dst\t! replicate2I" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2105 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2106 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2107 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2108 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2109 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2110
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2111 instruct Repl4I_zero(vecX dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2112 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2113 match(Set dst (ReplicateI zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2114 format %{ "pxor $dst,$dst\t! replicate4I zero)" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2115 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2116 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2117 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2118 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2119 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2120
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2121 instruct Repl8I_zero(vecY dst, immI0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2122 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2123 match(Set dst (ReplicateI zero));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2124 format %{ "vpxor $dst,$dst,$dst\t! replicate8I zero" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2125 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2126 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2127 bool vector256 = true;
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2128 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2129 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2130 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2131 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2132
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2133 // Replicate long (8 byte) scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2134 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2135 instruct Repl2L(vecX dst, rRegL src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2136 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2137 match(Set dst (ReplicateL src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2138 format %{ "movdq $dst,$src\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2139 "punpcklqdq $dst,$dst\t! replicate2L" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2140 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2141 __ movdq($dst$$XMMRegister, $src$$Register);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2142 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2143 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2144 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2145 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2146
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2147 instruct Repl4L(vecY dst, rRegL src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2148 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2149 match(Set dst (ReplicateL src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2150 format %{ "movdq $dst,$src\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2151 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2152 "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2153 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2154 __ movdq($dst$$XMMRegister, $src$$Register);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2155 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2156 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2157 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2158 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2159 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2160 #else // _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2161 instruct Repl2L(vecX dst, eRegL src, regD tmp) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2162 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2163 match(Set dst (ReplicateL src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2164 effect(TEMP dst, USE src, TEMP tmp);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2165 format %{ "movdl $dst,$src.lo\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2166 "movdl $tmp,$src.hi\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2167 "punpckldq $dst,$tmp\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2168 "punpcklqdq $dst,$dst\t! replicate2L"%}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2169 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2170 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2171 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2172 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2173 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2174 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2175 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2176 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2177
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2178 instruct Repl4L(vecY dst, eRegL src, regD tmp) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2179 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2180 match(Set dst (ReplicateL src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2181 effect(TEMP dst, USE src, TEMP tmp);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2182 format %{ "movdl $dst,$src.lo\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2183 "movdl $tmp,$src.hi\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2184 "punpckldq $dst,$tmp\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2185 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2186 "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2187 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2188 __ movdl($dst$$XMMRegister, $src$$Register);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2189 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2190 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2191 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2192 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2193 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2194 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2195 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2196 #endif // _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2197
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2198 // Replicate long (8 byte) scalar immediate to be vector by loading from const table.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2199 instruct Repl2L_imm(vecX dst, immL con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2200 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2201 match(Set dst (ReplicateL con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2202 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2203 "punpcklqdq $dst,$dst\t! replicate2L($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2204 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2205 __ movq($dst$$XMMRegister, $constantaddress($con));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2206 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2207 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2208 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2209 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2210
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2211 instruct Repl4L_imm(vecY dst, immL con) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2212 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2213 match(Set dst (ReplicateL con));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2214 format %{ "movq $dst,[$constantaddress]\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2215 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2216 "vinserti128h $dst,$dst,$dst\t! replicate4L($con)" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2217 ins_encode %{
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2218 __ movq($dst$$XMMRegister, $constantaddress($con));
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2219 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2220 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2221 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2222 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2223 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2224
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2225 // Long could be loaded into xmm register directly from memory.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2226 instruct Repl2L_mem(vecX dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2227 predicate(n->as_Vector()->length() == 2);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2228 match(Set dst (ReplicateL (LoadL mem)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2229 format %{ "movq $dst,$mem\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2230 "punpcklqdq $dst,$dst\t! replicate2L" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2231 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2232 __ movq($dst$$XMMRegister, $mem$$Address);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2233 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2234 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2235 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2236 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2237
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2238 instruct Repl4L_mem(vecY dst, memory mem) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2239 predicate(n->as_Vector()->length() == 4);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2240 match(Set dst (ReplicateL (LoadL mem)));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2241 format %{ "movq $dst,$mem\n\t"
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2242 "punpcklqdq $dst,$dst\n\t"
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2243 "vinserti128h $dst,$dst,$dst\t! replicate4L" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2244 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2245 __ movq($dst$$XMMRegister, $mem$$Address);
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2246 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2247 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2248 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2249 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2250 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2251
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2252 // Replicate long (8 byte) scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2253 instruct Repl2L_zero(vecX dst, immL0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2254 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2255 match(Set dst (ReplicateL zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2256 format %{ "pxor $dst,$dst\t! replicate2L zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2257 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2258 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2259 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2260 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2261 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2262
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2263 instruct Repl4L_zero(vecY dst, immL0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2264 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2265 match(Set dst (ReplicateL zero));
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2266 format %{ "vpxor $dst,$dst,$dst\t! replicate4L zero" %}
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2267 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2268 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it).
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2269 bool vector256 = true;
6225 2c368ea3e844 7181494: cleanup avx and vectors code kvn parents: 6183 diff changeset	2270 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2271 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2272 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2273 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2274
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2275 // Replicate float (4 byte) scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2276 instruct Repl2F(vecD dst, regF src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2277 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2278 match(Set dst (ReplicateF src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2279 format %{ "pshufd $dst,$dst,0x00\t! replicate2F" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2280 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2281 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2282 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2283 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2284 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2285
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2286 instruct Repl4F(vecX dst, regF src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2287 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2288 match(Set dst (ReplicateF src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2289 format %{ "pshufd $dst,$dst,0x00\t! replicate4F" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2290 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2291 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2292 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2293 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2294 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2295
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2296 instruct Repl8F(vecY dst, regF src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2297 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2298 match(Set dst (ReplicateF src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2299 format %{ "pshufd $dst,$src,0x00\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2300 "vinsertf128h $dst,$dst,$dst\t! replicate8F" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2301 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2302 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2303 __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2304 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2305 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2306 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2307
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2308 // Replicate float (4 byte) scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2309 instruct Repl2F_zero(vecD dst, immF0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2310 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2311 match(Set dst (ReplicateF zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2312 format %{ "xorps $dst,$dst\t! replicate2F zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2313 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2314 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2315 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2316 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2317 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2318
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2319 instruct Repl4F_zero(vecX dst, immF0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2320 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2321 match(Set dst (ReplicateF zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2322 format %{ "xorps $dst,$dst\t! replicate4F zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2323 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2324 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2325 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2326 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2327 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2328
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2329 instruct Repl8F_zero(vecY dst, immF0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2330 predicate(n->as_Vector()->length() == 8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2331 match(Set dst (ReplicateF zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2332 format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2333 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2334 bool vector256 = true;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2335 __ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2336 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2337 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2338 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2339
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2340 // Replicate double (8 bytes) scalar to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2341 instruct Repl2D(vecX dst, regD src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2342 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2343 match(Set dst (ReplicateD src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2344 format %{ "pshufd $dst,$src,0x44\t! replicate2D" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2345 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2346 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2347 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2348 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2349 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2350
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2351 instruct Repl4D(vecY dst, regD src) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2352 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2353 match(Set dst (ReplicateD src));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2354 format %{ "pshufd $dst,$src,0x44\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2355 "vinsertf128h $dst,$dst,$dst\t! replicate4D" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2356 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2357 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2358 __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2359 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2360 ins_pipe( pipe_slow );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2361 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2362
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2363 // Replicate double (8 byte) scalar zero to be vector
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2364 instruct Repl2D_zero(vecX dst, immD0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2365 predicate(n->as_Vector()->length() == 2);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2366 match(Set dst (ReplicateD zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2367 format %{ "xorpd $dst,$dst\t! replicate2D zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2368 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2369 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2370 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2371 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2372 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2373
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2374 instruct Repl4D_zero(vecY dst, immD0 zero) %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2375 predicate(n->as_Vector()->length() == 4);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2376 match(Set dst (ReplicateD zero));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2377 format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2378 ins_encode %{
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2379 bool vector256 = true;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2380 __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2381 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2382 ins_pipe( fpu_reg_reg );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2383 %}
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4950 diff changeset	2384

Mercurial > hg > truffle

annotate src/cpu/x86/vm/x86.ad @ 6225:2c368ea3e844