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4761
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1 //
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4950
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2 // Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.
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4761
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 // or visit www.oracle.com if you need additional information or have any
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21 // questions.
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22 //
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23 //
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24
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25 // X86 Common Architecture Description File
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26
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27 source %{
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28 // Float masks come from different places depending on platform.
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29 #ifdef _LP64
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30 static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
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31 static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
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32 static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
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33 static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
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34 #else
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35 static address float_signmask() { return (address)float_signmask_pool; }
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36 static address float_signflip() { return (address)float_signflip_pool; }
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37 static address double_signmask() { return (address)double_signmask_pool; }
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38 static address double_signflip() { return (address)double_signflip_pool; }
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39 #endif
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4950
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40
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41 #ifndef PRODUCT
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42 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
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43 st->print("nop \t# %d bytes pad for loops and calls", _count);
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44 }
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45 #endif
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46
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47 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
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48 MacroAssembler _masm(&cbuf);
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49 __ nop(_count);
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50 }
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51
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52 uint MachNopNode::size(PhaseRegAlloc*) const {
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53 return _count;
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54 }
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55
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56 #ifndef PRODUCT
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57 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
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58 st->print("# breakpoint");
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59 }
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60 #endif
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61
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62 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
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63 MacroAssembler _masm(&cbuf);
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64 __ int3();
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65 }
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66
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67 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
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68 return MachNode::size(ra_);
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69 }
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70
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71 %}
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72
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73 encode %{
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74
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75 enc_class preserve_SP %{
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76 debug_only(int off0 = cbuf.insts_size());
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77 MacroAssembler _masm(&cbuf);
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78 // RBP is preserved across all calls, even compiled calls.
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79 // Use it to preserve RSP in places where the callee might change the SP.
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80 __ movptr(rbp_mh_SP_save, rsp);
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81 debug_only(int off1 = cbuf.insts_size());
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82 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
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83 %}
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84
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85 enc_class restore_SP %{
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86 MacroAssembler _masm(&cbuf);
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87 __ movptr(rsp, rbp_mh_SP_save);
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88 %}
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89
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90 enc_class call_epilog %{
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91 if (VerifyStackAtCalls) {
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92 // Check that stack depth is unchanged: find majik cookie on stack
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93 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
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94 MacroAssembler _masm(&cbuf);
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95 Label L;
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96 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
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97 __ jccb(Assembler::equal, L);
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98 // Die if stack mismatch
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99 __ int3();
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100 __ bind(L);
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101 }
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102 %}
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103
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104 %}
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105
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106 // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit)
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107
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4950
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108 // ============================================================================
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109
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110 instruct ShouldNotReachHere() %{
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111 match(Halt);
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112 format %{ "int3\t# ShouldNotReachHere" %}
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113 ins_encode %{
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114 __ int3();
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115 %}
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116 ins_pipe(pipe_slow);
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117 %}
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118
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119 // ============================================================================
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120
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121 instruct addF_reg(regF dst, regF src) %{
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122 predicate((UseSSE>=1) && (UseAVX == 0));
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123 match(Set dst (AddF dst src));
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124
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125 format %{ "addss $dst, $src" %}
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126 ins_cost(150);
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127 ins_encode %{
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128 __ addss($dst$$XMMRegister, $src$$XMMRegister);
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129 %}
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130 ins_pipe(pipe_slow);
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131 %}
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132
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133 instruct addF_mem(regF dst, memory src) %{
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134 predicate((UseSSE>=1) && (UseAVX == 0));
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135 match(Set dst (AddF dst (LoadF src)));
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136
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137 format %{ "addss $dst, $src" %}
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138 ins_cost(150);
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139 ins_encode %{
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140 __ addss($dst$$XMMRegister, $src$$Address);
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141 %}
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142 ins_pipe(pipe_slow);
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143 %}
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144
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145 instruct addF_imm(regF dst, immF con) %{
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146 predicate((UseSSE>=1) && (UseAVX == 0));
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147 match(Set dst (AddF dst con));
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148 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
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149 ins_cost(150);
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150 ins_encode %{
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151 __ addss($dst$$XMMRegister, $constantaddress($con));
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152 %}
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153 ins_pipe(pipe_slow);
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154 %}
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155
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156 instruct vaddF_reg(regF dst, regF src1, regF src2) %{
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157 predicate(UseAVX > 0);
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158 match(Set dst (AddF src1 src2));
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159
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160 format %{ "vaddss $dst, $src1, $src2" %}
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161 ins_cost(150);
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162 ins_encode %{
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163 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
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164 %}
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165 ins_pipe(pipe_slow);
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166 %}
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167
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168 instruct vaddF_mem(regF dst, regF src1, memory src2) %{
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169 predicate(UseAVX > 0);
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170 match(Set dst (AddF src1 (LoadF src2)));
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171
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172 format %{ "vaddss $dst, $src1, $src2" %}
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173 ins_cost(150);
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174 ins_encode %{
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175 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
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176 %}
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177 ins_pipe(pipe_slow);
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178 %}
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179
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180 instruct vaddF_imm(regF dst, regF src, immF con) %{
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181 predicate(UseAVX > 0);
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182 match(Set dst (AddF src con));
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183
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184 format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
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185 ins_cost(150);
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186 ins_encode %{
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187 __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
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188 %}
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189 ins_pipe(pipe_slow);
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190 %}
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191
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192 instruct addD_reg(regD dst, regD src) %{
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193 predicate((UseSSE>=2) && (UseAVX == 0));
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194 match(Set dst (AddD dst src));
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195
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196 format %{ "addsd $dst, $src" %}
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197 ins_cost(150);
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198 ins_encode %{
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199 __ addsd($dst$$XMMRegister, $src$$XMMRegister);
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200 %}
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201 ins_pipe(pipe_slow);
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202 %}
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203
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204 instruct addD_mem(regD dst, memory src) %{
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205 predicate((UseSSE>=2) && (UseAVX == 0));
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206 match(Set dst (AddD dst (LoadD src)));
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207
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208 format %{ "addsd $dst, $src" %}
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209 ins_cost(150);
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210 ins_encode %{
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211 __ addsd($dst$$XMMRegister, $src$$Address);
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212 %}
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213 ins_pipe(pipe_slow);
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214 %}
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215
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216 instruct addD_imm(regD dst, immD con) %{
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217 predicate((UseSSE>=2) && (UseAVX == 0));
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218 match(Set dst (AddD dst con));
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219 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
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220 ins_cost(150);
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221 ins_encode %{
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222 __ addsd($dst$$XMMRegister, $constantaddress($con));
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223 %}
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224 ins_pipe(pipe_slow);
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225 %}
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226
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227 instruct vaddD_reg(regD dst, regD src1, regD src2) %{
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228 predicate(UseAVX > 0);
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229 match(Set dst (AddD src1 src2));
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230
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231 format %{ "vaddsd $dst, $src1, $src2" %}
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232 ins_cost(150);
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233 ins_encode %{
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234 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
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235 %}
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236 ins_pipe(pipe_slow);
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237 %}
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238
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239 instruct vaddD_mem(regD dst, regD src1, memory src2) %{
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240 predicate(UseAVX > 0);
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241 match(Set dst (AddD src1 (LoadD src2)));
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242
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243 format %{ "vaddsd $dst, $src1, $src2" %}
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244 ins_cost(150);
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245 ins_encode %{
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246 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
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247 %}
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248 ins_pipe(pipe_slow);
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249 %}
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250
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251 instruct vaddD_imm(regD dst, regD src, immD con) %{
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252 predicate(UseAVX > 0);
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253 match(Set dst (AddD src con));
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254
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255 format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
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256 ins_cost(150);
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257 ins_encode %{
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258 __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
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259 %}
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260 ins_pipe(pipe_slow);
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261 %}
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262
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263 instruct subF_reg(regF dst, regF src) %{
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264 predicate((UseSSE>=1) && (UseAVX == 0));
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265 match(Set dst (SubF dst src));
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266
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267 format %{ "subss $dst, $src" %}
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268 ins_cost(150);
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269 ins_encode %{
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270 __ subss($dst$$XMMRegister, $src$$XMMRegister);
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271 %}
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272 ins_pipe(pipe_slow);
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273 %}
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274
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275 instruct subF_mem(regF dst, memory src) %{
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276 predicate((UseSSE>=1) && (UseAVX == 0));
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277 match(Set dst (SubF dst (LoadF src)));
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278
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279 format %{ "subss $dst, $src" %}
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280 ins_cost(150);
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281 ins_encode %{
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282 __ subss($dst$$XMMRegister, $src$$Address);
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283 %}
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284 ins_pipe(pipe_slow);
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285 %}
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286
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287 instruct subF_imm(regF dst, immF con) %{
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288 predicate((UseSSE>=1) && (UseAVX == 0));
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289 match(Set dst (SubF dst con));
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290 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
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291 ins_cost(150);
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292 ins_encode %{
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293 __ subss($dst$$XMMRegister, $constantaddress($con));
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294 %}
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295 ins_pipe(pipe_slow);
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296 %}
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297
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298 instruct vsubF_reg(regF dst, regF src1, regF src2) %{
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299 predicate(UseAVX > 0);
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300 match(Set dst (SubF src1 src2));
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301
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302 format %{ "vsubss $dst, $src1, $src2" %}
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303 ins_cost(150);
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304 ins_encode %{
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305 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
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306 %}
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307 ins_pipe(pipe_slow);
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308 %}
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309
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310 instruct vsubF_mem(regF dst, regF src1, memory src2) %{
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311 predicate(UseAVX > 0);
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312 match(Set dst (SubF src1 (LoadF src2)));
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313
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314 format %{ "vsubss $dst, $src1, $src2" %}
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315 ins_cost(150);
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316 ins_encode %{
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317 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
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318 %}
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319 ins_pipe(pipe_slow);
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320 %}
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321
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322 instruct vsubF_imm(regF dst, regF src, immF con) %{
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323 predicate(UseAVX > 0);
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324 match(Set dst (SubF src con));
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325
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326 format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
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327 ins_cost(150);
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328 ins_encode %{
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329 __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
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330 %}
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331 ins_pipe(pipe_slow);
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332 %}
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333
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334 instruct subD_reg(regD dst, regD src) %{
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335 predicate((UseSSE>=2) && (UseAVX == 0));
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336 match(Set dst (SubD dst src));
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337
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338 format %{ "subsd $dst, $src" %}
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339 ins_cost(150);
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340 ins_encode %{
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341 __ subsd($dst$$XMMRegister, $src$$XMMRegister);
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342 %}
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343 ins_pipe(pipe_slow);
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344 %}
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345
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346 instruct subD_mem(regD dst, memory src) %{
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347 predicate((UseSSE>=2) && (UseAVX == 0));
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348 match(Set dst (SubD dst (LoadD src)));
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349
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350 format %{ "subsd $dst, $src" %}
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351 ins_cost(150);
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352 ins_encode %{
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353 __ subsd($dst$$XMMRegister, $src$$Address);
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354 %}
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355 ins_pipe(pipe_slow);
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356 %}
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357
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358 instruct subD_imm(regD dst, immD con) %{
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359 predicate((UseSSE>=2) && (UseAVX == 0));
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360 match(Set dst (SubD dst con));
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361 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
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362 ins_cost(150);
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363 ins_encode %{
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364 __ subsd($dst$$XMMRegister, $constantaddress($con));
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365 %}
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366 ins_pipe(pipe_slow);
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367 %}
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368
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369 instruct vsubD_reg(regD dst, regD src1, regD src2) %{
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370 predicate(UseAVX > 0);
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371 match(Set dst (SubD src1 src2));
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372
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373 format %{ "vsubsd $dst, $src1, $src2" %}
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374 ins_cost(150);
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375 ins_encode %{
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376 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
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377 %}
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378 ins_pipe(pipe_slow);
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379 %}
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380
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381 instruct vsubD_mem(regD dst, regD src1, memory src2) %{
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382 predicate(UseAVX > 0);
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383 match(Set dst (SubD src1 (LoadD src2)));
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384
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385 format %{ "vsubsd $dst, $src1, $src2" %}
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386 ins_cost(150);
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387 ins_encode %{
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388 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
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389 %}
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390 ins_pipe(pipe_slow);
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391 %}
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392
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393 instruct vsubD_imm(regD dst, regD src, immD con) %{
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394 predicate(UseAVX > 0);
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395 match(Set dst (SubD src con));
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396
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397 format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
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|
|
398 ins_cost(150);
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|
|
399 ins_encode %{
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|
|
400 __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
|
|
|
401 %}
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|
|
402 ins_pipe(pipe_slow);
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|
|
403 %}
|
|
|
404
|
|
|
405 instruct mulF_reg(regF dst, regF src) %{
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|
|
406 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
407 match(Set dst (MulF dst src));
|
|
|
408
|
|
|
409 format %{ "mulss $dst, $src" %}
|
|
|
410 ins_cost(150);
|
|
|
411 ins_encode %{
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|
|
412 __ mulss($dst$$XMMRegister, $src$$XMMRegister);
|
|
|
413 %}
|
|
|
414 ins_pipe(pipe_slow);
|
|
|
415 %}
|
|
|
416
|
|
|
417 instruct mulF_mem(regF dst, memory src) %{
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|
|
418 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
419 match(Set dst (MulF dst (LoadF src)));
|
|
|
420
|
|
|
421 format %{ "mulss $dst, $src" %}
|
|
|
422 ins_cost(150);
|
|
|
423 ins_encode %{
|
|
|
424 __ mulss($dst$$XMMRegister, $src$$Address);
|
|
|
425 %}
|
|
|
426 ins_pipe(pipe_slow);
|
|
|
427 %}
|
|
|
428
|
|
|
429 instruct mulF_imm(regF dst, immF con) %{
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|
|
430 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
431 match(Set dst (MulF dst con));
|
|
|
432 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
|
|
|
433 ins_cost(150);
|
|
|
434 ins_encode %{
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|
|
435 __ mulss($dst$$XMMRegister, $constantaddress($con));
|
|
|
436 %}
|
|
|
437 ins_pipe(pipe_slow);
|
|
|
438 %}
|
|
|
439
|
|
|
440 instruct vmulF_reg(regF dst, regF src1, regF src2) %{
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|
|
441 predicate(UseAVX > 0);
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|
|
442 match(Set dst (MulF src1 src2));
|
|
|
443
|
|
|
444 format %{ "vmulss $dst, $src1, $src2" %}
|
|
|
445 ins_cost(150);
|
|
|
446 ins_encode %{
|
|
|
447 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
|
|
|
448 %}
|
|
|
449 ins_pipe(pipe_slow);
|
|
|
450 %}
|
|
|
451
|
|
|
452 instruct vmulF_mem(regF dst, regF src1, memory src2) %{
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|
|
453 predicate(UseAVX > 0);
|
|
|
454 match(Set dst (MulF src1 (LoadF src2)));
|
|
|
455
|
|
|
456 format %{ "vmulss $dst, $src1, $src2" %}
|
|
|
457 ins_cost(150);
|
|
|
458 ins_encode %{
|
|
|
459 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
|
|
|
460 %}
|
|
|
461 ins_pipe(pipe_slow);
|
|
|
462 %}
|
|
|
463
|
|
|
464 instruct vmulF_imm(regF dst, regF src, immF con) %{
|
|
|
465 predicate(UseAVX > 0);
|
|
|
466 match(Set dst (MulF src con));
|
|
|
467
|
|
|
468 format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
|
|
|
469 ins_cost(150);
|
|
|
470 ins_encode %{
|
|
|
471 __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
|
|
|
472 %}
|
|
|
473 ins_pipe(pipe_slow);
|
|
|
474 %}
|
|
|
475
|
|
|
476 instruct mulD_reg(regD dst, regD src) %{
|
|
|
477 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
478 match(Set dst (MulD dst src));
|
|
|
479
|
|
|
480 format %{ "mulsd $dst, $src" %}
|
|
|
481 ins_cost(150);
|
|
|
482 ins_encode %{
|
|
|
483 __ mulsd($dst$$XMMRegister, $src$$XMMRegister);
|
|
|
484 %}
|
|
|
485 ins_pipe(pipe_slow);
|
|
|
486 %}
|
|
|
487
|
|
|
488 instruct mulD_mem(regD dst, memory src) %{
|
|
|
489 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
490 match(Set dst (MulD dst (LoadD src)));
|
|
|
491
|
|
|
492 format %{ "mulsd $dst, $src" %}
|
|
|
493 ins_cost(150);
|
|
|
494 ins_encode %{
|
|
|
495 __ mulsd($dst$$XMMRegister, $src$$Address);
|
|
|
496 %}
|
|
|
497 ins_pipe(pipe_slow);
|
|
|
498 %}
|
|
|
499
|
|
|
500 instruct mulD_imm(regD dst, immD con) %{
|
|
|
501 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
502 match(Set dst (MulD dst con));
|
|
|
503 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
|
|
|
504 ins_cost(150);
|
|
|
505 ins_encode %{
|
|
|
506 __ mulsd($dst$$XMMRegister, $constantaddress($con));
|
|
|
507 %}
|
|
|
508 ins_pipe(pipe_slow);
|
|
|
509 %}
|
|
|
510
|
|
|
511 instruct vmulD_reg(regD dst, regD src1, regD src2) %{
|
|
|
512 predicate(UseAVX > 0);
|
|
|
513 match(Set dst (MulD src1 src2));
|
|
|
514
|
|
|
515 format %{ "vmulsd $dst, $src1, $src2" %}
|
|
|
516 ins_cost(150);
|
|
|
517 ins_encode %{
|
|
|
518 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
|
|
|
519 %}
|
|
|
520 ins_pipe(pipe_slow);
|
|
|
521 %}
|
|
|
522
|
|
|
523 instruct vmulD_mem(regD dst, regD src1, memory src2) %{
|
|
|
524 predicate(UseAVX > 0);
|
|
|
525 match(Set dst (MulD src1 (LoadD src2)));
|
|
|
526
|
|
|
527 format %{ "vmulsd $dst, $src1, $src2" %}
|
|
|
528 ins_cost(150);
|
|
|
529 ins_encode %{
|
|
|
530 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
|
|
|
531 %}
|
|
|
532 ins_pipe(pipe_slow);
|
|
|
533 %}
|
|
|
534
|
|
|
535 instruct vmulD_imm(regD dst, regD src, immD con) %{
|
|
|
536 predicate(UseAVX > 0);
|
|
|
537 match(Set dst (MulD src con));
|
|
|
538
|
|
|
539 format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
|
|
|
540 ins_cost(150);
|
|
|
541 ins_encode %{
|
|
|
542 __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
|
|
|
543 %}
|
|
|
544 ins_pipe(pipe_slow);
|
|
|
545 %}
|
|
|
546
|
|
|
547 instruct divF_reg(regF dst, regF src) %{
|
|
|
548 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
549 match(Set dst (DivF dst src));
|
|
|
550
|
|
|
551 format %{ "divss $dst, $src" %}
|
|
|
552 ins_cost(150);
|
|
|
553 ins_encode %{
|
|
|
554 __ divss($dst$$XMMRegister, $src$$XMMRegister);
|
|
|
555 %}
|
|
|
556 ins_pipe(pipe_slow);
|
|
|
557 %}
|
|
|
558
|
|
|
559 instruct divF_mem(regF dst, memory src) %{
|
|
|
560 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
561 match(Set dst (DivF dst (LoadF src)));
|
|
|
562
|
|
|
563 format %{ "divss $dst, $src" %}
|
|
|
564 ins_cost(150);
|
|
|
565 ins_encode %{
|
|
|
566 __ divss($dst$$XMMRegister, $src$$Address);
|
|
|
567 %}
|
|
|
568 ins_pipe(pipe_slow);
|
|
|
569 %}
|
|
|
570
|
|
|
571 instruct divF_imm(regF dst, immF con) %{
|
|
|
572 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
573 match(Set dst (DivF dst con));
|
|
|
574 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
|
|
|
575 ins_cost(150);
|
|
|
576 ins_encode %{
|
|
|
577 __ divss($dst$$XMMRegister, $constantaddress($con));
|
|
|
578 %}
|
|
|
579 ins_pipe(pipe_slow);
|
|
|
580 %}
|
|
|
581
|
|
|
582 instruct vdivF_reg(regF dst, regF src1, regF src2) %{
|
|
|
583 predicate(UseAVX > 0);
|
|
|
584 match(Set dst (DivF src1 src2));
|
|
|
585
|
|
|
586 format %{ "vdivss $dst, $src1, $src2" %}
|
|
|
587 ins_cost(150);
|
|
|
588 ins_encode %{
|
|
|
589 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
|
|
|
590 %}
|
|
|
591 ins_pipe(pipe_slow);
|
|
|
592 %}
|
|
|
593
|
|
|
594 instruct vdivF_mem(regF dst, regF src1, memory src2) %{
|
|
|
595 predicate(UseAVX > 0);
|
|
|
596 match(Set dst (DivF src1 (LoadF src2)));
|
|
|
597
|
|
|
598 format %{ "vdivss $dst, $src1, $src2" %}
|
|
|
599 ins_cost(150);
|
|
|
600 ins_encode %{
|
|
|
601 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
|
|
|
602 %}
|
|
|
603 ins_pipe(pipe_slow);
|
|
|
604 %}
|
|
|
605
|
|
|
606 instruct vdivF_imm(regF dst, regF src, immF con) %{
|
|
|
607 predicate(UseAVX > 0);
|
|
|
608 match(Set dst (DivF src con));
|
|
|
609
|
|
|
610 format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %}
|
|
|
611 ins_cost(150);
|
|
|
612 ins_encode %{
|
|
|
613 __ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
|
|
|
614 %}
|
|
|
615 ins_pipe(pipe_slow);
|
|
|
616 %}
|
|
|
617
|
|
|
618 instruct divD_reg(regD dst, regD src) %{
|
|
|
619 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
620 match(Set dst (DivD dst src));
|
|
|
621
|
|
|
622 format %{ "divsd $dst, $src" %}
|
|
|
623 ins_cost(150);
|
|
|
624 ins_encode %{
|
|
|
625 __ divsd($dst$$XMMRegister, $src$$XMMRegister);
|
|
|
626 %}
|
|
|
627 ins_pipe(pipe_slow);
|
|
|
628 %}
|
|
|
629
|
|
|
630 instruct divD_mem(regD dst, memory src) %{
|
|
|
631 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
632 match(Set dst (DivD dst (LoadD src)));
|
|
|
633
|
|
|
634 format %{ "divsd $dst, $src" %}
|
|
|
635 ins_cost(150);
|
|
|
636 ins_encode %{
|
|
|
637 __ divsd($dst$$XMMRegister, $src$$Address);
|
|
|
638 %}
|
|
|
639 ins_pipe(pipe_slow);
|
|
|
640 %}
|
|
|
641
|
|
|
642 instruct divD_imm(regD dst, immD con) %{
|
|
|
643 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
644 match(Set dst (DivD dst con));
|
|
|
645 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
|
|
|
646 ins_cost(150);
|
|
|
647 ins_encode %{
|
|
|
648 __ divsd($dst$$XMMRegister, $constantaddress($con));
|
|
|
649 %}
|
|
|
650 ins_pipe(pipe_slow);
|
|
|
651 %}
|
|
|
652
|
|
|
653 instruct vdivD_reg(regD dst, regD src1, regD src2) %{
|
|
|
654 predicate(UseAVX > 0);
|
|
|
655 match(Set dst (DivD src1 src2));
|
|
|
656
|
|
|
657 format %{ "vdivsd $dst, $src1, $src2" %}
|
|
|
658 ins_cost(150);
|
|
|
659 ins_encode %{
|
|
|
660 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister);
|
|
|
661 %}
|
|
|
662 ins_pipe(pipe_slow);
|
|
|
663 %}
|
|
|
664
|
|
|
665 instruct vdivD_mem(regD dst, regD src1, memory src2) %{
|
|
|
666 predicate(UseAVX > 0);
|
|
|
667 match(Set dst (DivD src1 (LoadD src2)));
|
|
|
668
|
|
|
669 format %{ "vdivsd $dst, $src1, $src2" %}
|
|
|
670 ins_cost(150);
|
|
|
671 ins_encode %{
|
|
|
672 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address);
|
|
|
673 %}
|
|
|
674 ins_pipe(pipe_slow);
|
|
|
675 %}
|
|
|
676
|
|
|
677 instruct vdivD_imm(regD dst, regD src, immD con) %{
|
|
|
678 predicate(UseAVX > 0);
|
|
|
679 match(Set dst (DivD src con));
|
|
|
680
|
|
|
681 format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %}
|
|
|
682 ins_cost(150);
|
|
|
683 ins_encode %{
|
|
|
684 __ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con));
|
|
|
685 %}
|
|
|
686 ins_pipe(pipe_slow);
|
|
|
687 %}
|
|
|
688
|
|
|
689 instruct absF_reg(regF dst) %{
|
|
|
690 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
691 match(Set dst (AbsF dst));
|
|
|
692 ins_cost(150);
|
|
|
693 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
|
|
|
694 ins_encode %{
|
|
|
695 __ andps($dst$$XMMRegister, ExternalAddress(float_signmask()));
|
|
|
696 %}
|
|
|
697 ins_pipe(pipe_slow);
|
|
|
698 %}
|
|
|
699
|
|
|
700 instruct vabsF_reg(regF dst, regF src) %{
|
|
|
701 predicate(UseAVX > 0);
|
|
|
702 match(Set dst (AbsF src));
|
|
|
703 ins_cost(150);
|
|
|
704 format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %}
|
|
|
705 ins_encode %{
|
|
|
706 __ vandps($dst$$XMMRegister, $src$$XMMRegister,
|
|
|
707 ExternalAddress(float_signmask()));
|
|
|
708 %}
|
|
|
709 ins_pipe(pipe_slow);
|
|
|
710 %}
|
|
|
711
|
|
|
712 instruct absD_reg(regD dst) %{
|
|
|
713 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
714 match(Set dst (AbsD dst));
|
|
|
715 ins_cost(150);
|
|
|
716 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
|
|
|
717 "# abs double by sign masking" %}
|
|
|
718 ins_encode %{
|
|
|
719 __ andpd($dst$$XMMRegister, ExternalAddress(double_signmask()));
|
|
|
720 %}
|
|
|
721 ins_pipe(pipe_slow);
|
|
|
722 %}
|
|
|
723
|
|
|
724 instruct vabsD_reg(regD dst, regD src) %{
|
|
|
725 predicate(UseAVX > 0);
|
|
|
726 match(Set dst (AbsD src));
|
|
|
727 ins_cost(150);
|
|
|
728 format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t"
|
|
|
729 "# abs double by sign masking" %}
|
|
|
730 ins_encode %{
|
|
|
731 __ vandpd($dst$$XMMRegister, $src$$XMMRegister,
|
|
|
732 ExternalAddress(double_signmask()));
|
|
|
733 %}
|
|
|
734 ins_pipe(pipe_slow);
|
|
|
735 %}
|
|
|
736
|
|
|
737 instruct negF_reg(regF dst) %{
|
|
|
738 predicate((UseSSE>=1) && (UseAVX == 0));
|
|
|
739 match(Set dst (NegF dst));
|
|
|
740 ins_cost(150);
|
|
|
741 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
|
|
|
742 ins_encode %{
|
|
|
743 __ xorps($dst$$XMMRegister, ExternalAddress(float_signflip()));
|
|
|
744 %}
|
|
|
745 ins_pipe(pipe_slow);
|
|
|
746 %}
|
|
|
747
|
|
|
748 instruct vnegF_reg(regF dst, regF src) %{
|
|
|
749 predicate(UseAVX > 0);
|
|
|
750 match(Set dst (NegF src));
|
|
|
751 ins_cost(150);
|
|
|
752 format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %}
|
|
|
753 ins_encode %{
|
|
|
754 __ vxorps($dst$$XMMRegister, $src$$XMMRegister,
|
|
|
755 ExternalAddress(float_signflip()));
|
|
|
756 %}
|
|
|
757 ins_pipe(pipe_slow);
|
|
|
758 %}
|
|
|
759
|
|
|
760 instruct negD_reg(regD dst) %{
|
|
|
761 predicate((UseSSE>=2) && (UseAVX == 0));
|
|
|
762 match(Set dst (NegD dst));
|
|
|
763 ins_cost(150);
|
|
|
764 format %{ "xorpd $dst, [0x8000000000000000]\t"
|
|
|
765 "# neg double by sign flipping" %}
|
|
|
766 ins_encode %{
|
|
|
767 __ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip()));
|
|
|
768 %}
|
|
|
769 ins_pipe(pipe_slow);
|
|
|
770 %}
|
|
|
771
|
|
|
772 instruct vnegD_reg(regD dst, regD src) %{
|
|
|
773 predicate(UseAVX > 0);
|
|
|
774 match(Set dst (NegD src));
|
|
|
775 ins_cost(150);
|
|
|
776 format %{ "vxorpd $dst, $src, [0x8000000000000000]\t"
|
|
|
777 "# neg double by sign flipping" %}
|
|
|
778 ins_encode %{
|
|
|
779 __ vxorpd($dst$$XMMRegister, $src$$XMMRegister,
|
|
|
780 ExternalAddress(double_signflip()));
|
|
|
781 %}
|
|
|
782 ins_pipe(pipe_slow);
|
|
|
783 %}
|
|
|
784
|
|
|
785 instruct sqrtF_reg(regF dst, regF src) %{
|
|
|
786 predicate(UseSSE>=1);
|
|
|
787 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
|
|
|
788
|
|
|
789 format %{ "sqrtss $dst, $src" %}
|
|
|
790 ins_cost(150);
|
|
|
791 ins_encode %{
|
|
|
792 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
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793 %}
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794 ins_pipe(pipe_slow);
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795 %}
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796
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797 instruct sqrtF_mem(regF dst, memory src) %{
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798 predicate(UseSSE>=1);
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|
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799 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
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800
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801 format %{ "sqrtss $dst, $src" %}
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802 ins_cost(150);
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803 ins_encode %{
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804 __ sqrtss($dst$$XMMRegister, $src$$Address);
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805 %}
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806 ins_pipe(pipe_slow);
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807 %}
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|
808
|
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809 instruct sqrtF_imm(regF dst, immF con) %{
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810 predicate(UseSSE>=1);
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|
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811 match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
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|
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812 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
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813 ins_cost(150);
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814 ins_encode %{
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|
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815 __ sqrtss($dst$$XMMRegister, $constantaddress($con));
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|
816 %}
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817 ins_pipe(pipe_slow);
|
|
|
818 %}
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|
|
819
|
|
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820 instruct sqrtD_reg(regD dst, regD src) %{
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|
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821 predicate(UseSSE>=2);
|
|
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822 match(Set dst (SqrtD src));
|
|
|
823
|
|
|
824 format %{ "sqrtsd $dst, $src" %}
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|
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825 ins_cost(150);
|
|
|
826 ins_encode %{
|
|
|
827 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
|
|
|
828 %}
|
|
|
829 ins_pipe(pipe_slow);
|
|
|
830 %}
|
|
|
831
|
|
|
832 instruct sqrtD_mem(regD dst, memory src) %{
|
|
|
833 predicate(UseSSE>=2);
|
|
|
834 match(Set dst (SqrtD (LoadD src)));
|
|
|
835
|
|
|
836 format %{ "sqrtsd $dst, $src" %}
|
|
|
837 ins_cost(150);
|
|
|
838 ins_encode %{
|
|
|
839 __ sqrtsd($dst$$XMMRegister, $src$$Address);
|
|
|
840 %}
|
|
|
841 ins_pipe(pipe_slow);
|
|
|
842 %}
|
|
|
843
|
|
|
844 instruct sqrtD_imm(regD dst, immD con) %{
|
|
|
845 predicate(UseSSE>=2);
|
|
|
846 match(Set dst (SqrtD con));
|
|
|
847 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
|
|
|
848 ins_cost(150);
|
|
|
849 ins_encode %{
|
|
|
850 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
|
|
|
851 %}
|
|
|
852 ins_pipe(pipe_slow);
|
|
|
853 %}
|
|
|
854
|
