Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 6041:3576af4cb939
7160539: JDeveloper crashes on 64-bit Windows
Summary: x64 C1 needs to zero upper 32bits when doing l2i conversion
Reviewed-by: never, kvn
| author | iveresov |
|---|---|
| date | Wed, 11 Apr 2012 19:15:46 -0700 |
| parents | 701a83c86f28 |
| children | 8f972594effc |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
| 1972 | 27 #include "c1/c1_Compilation.hpp" |
| 28 #include "c1/c1_LIRAssembler.hpp" | |
| 29 #include "c1/c1_MacroAssembler.hpp" | |
| 30 #include "c1/c1_Runtime1.hpp" | |
| 31 #include "c1/c1_ValueStack.hpp" | |
| 32 #include "ci/ciArrayKlass.hpp" | |
| 33 #include "ci/ciInstance.hpp" | |
| 34 #include "gc_interface/collectedHeap.hpp" | |
| 35 #include "memory/barrierSet.hpp" | |
| 36 #include "memory/cardTableModRefBS.hpp" | |
| 37 #include "nativeInst_x86.hpp" | |
| 38 #include "oops/objArrayKlass.hpp" | |
| 39 #include "runtime/sharedRuntime.hpp" | |
| 0 | 40 |
| 41 | |
| 42 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 43 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 44 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 45 | |
| 46 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 49 // of 128-bits operands for SSE instructions. | |
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50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); |
| 0 | 51 // Store the value to a 128-bits operand. |
| 52 operand[0] = lo; | |
| 53 operand[1] = hi; | |
| 54 return operand; | |
| 55 } | |
| 56 | |
| 57 // Buffer for 128-bits masks used by SSE instructions. | |
| 58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 59 | |
| 60 // Static initialization during VM startup. | |
| 61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 65 | |
| 66 | |
| 67 | |
| 68 NEEDS_CLEANUP // remove this definitions ? | |
| 69 const Register IC_Klass = rax; // where the IC klass is cached | |
| 70 const Register SYNC_header = rax; // synchronization header | |
| 71 const Register SHIFT_count = rcx; // where count for shift operations must be | |
| 72 | |
| 73 #define __ _masm-> | |
| 74 | |
| 75 | |
| 76 static void select_different_registers(Register preserve, | |
| 77 Register extra, | |
| 78 Register &tmp1, | |
| 79 Register &tmp2) { | |
| 80 if (tmp1 == preserve) { | |
| 81 assert_different_registers(tmp1, tmp2, extra); | |
| 82 tmp1 = extra; | |
| 83 } else if (tmp2 == preserve) { | |
| 84 assert_different_registers(tmp1, tmp2, extra); | |
| 85 tmp2 = extra; | |
| 86 } | |
| 87 assert_different_registers(preserve, tmp1, tmp2); | |
| 88 } | |
| 89 | |
| 90 | |
| 91 | |
| 92 static void select_different_registers(Register preserve, | |
| 93 Register extra, | |
| 94 Register &tmp1, | |
| 95 Register &tmp2, | |
| 96 Register &tmp3) { | |
| 97 if (tmp1 == preserve) { | |
| 98 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 99 tmp1 = extra; | |
| 100 } else if (tmp2 == preserve) { | |
| 101 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 102 tmp2 = extra; | |
| 103 } else if (tmp3 == preserve) { | |
| 104 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 105 tmp3 = extra; | |
| 106 } | |
| 107 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
| 108 } | |
| 109 | |
| 110 | |
| 111 | |
| 112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 113 if (opr->is_constant()) { | |
| 114 LIR_Const* constant = opr->as_constant_ptr(); | |
| 115 switch (constant->type()) { | |
| 116 case T_INT: { | |
| 117 return true; | |
| 118 } | |
| 119 | |
| 120 default: | |
| 121 return false; | |
| 122 } | |
| 123 } | |
| 124 return false; | |
| 125 } | |
| 126 | |
| 127 | |
| 128 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 304 | 129 return FrameMap::receiver_opr; |
| 0 | 130 } |
| 131 | |
| 132 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 304 | 133 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
| 0 | 134 } |
| 135 | |
| 136 //--------------fpu register translations----------------------- | |
| 137 | |
| 138 | |
| 139 address LIR_Assembler::float_constant(float f) { | |
| 140 address const_addr = __ float_constant(f); | |
| 141 if (const_addr == NULL) { | |
| 142 bailout("const section overflow"); | |
| 143 return __ code()->consts()->start(); | |
| 144 } else { | |
| 145 return const_addr; | |
| 146 } | |
| 147 } | |
| 148 | |
| 149 | |
| 150 address LIR_Assembler::double_constant(double d) { | |
| 151 address const_addr = __ double_constant(d); | |
| 152 if (const_addr == NULL) { | |
| 153 bailout("const section overflow"); | |
| 154 return __ code()->consts()->start(); | |
| 155 } else { | |
| 156 return const_addr; | |
| 157 } | |
| 158 } | |
| 159 | |
| 160 | |
| 161 void LIR_Assembler::set_24bit_FPU() { | |
| 162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 163 } | |
| 164 | |
| 165 void LIR_Assembler::reset_FPU() { | |
| 166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 167 } | |
| 168 | |
| 169 void LIR_Assembler::fpop() { | |
| 170 __ fpop(); | |
| 171 } | |
| 172 | |
| 173 void LIR_Assembler::fxch(int i) { | |
| 174 __ fxch(i); | |
| 175 } | |
| 176 | |
| 177 void LIR_Assembler::fld(int i) { | |
| 178 __ fld_s(i); | |
| 179 } | |
| 180 | |
| 181 void LIR_Assembler::ffree(int i) { | |
| 182 __ ffree(i); | |
| 183 } | |
| 184 | |
| 185 void LIR_Assembler::breakpoint() { | |
| 186 __ int3(); | |
| 187 } | |
| 188 | |
| 189 void LIR_Assembler::push(LIR_Opr opr) { | |
| 190 if (opr->is_single_cpu()) { | |
| 191 __ push_reg(opr->as_register()); | |
| 192 } else if (opr->is_double_cpu()) { | |
| 304 | 193 NOT_LP64(__ push_reg(opr->as_register_hi())); |
| 0 | 194 __ push_reg(opr->as_register_lo()); |
| 195 } else if (opr->is_stack()) { | |
| 196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
| 197 } else if (opr->is_constant()) { | |
| 198 LIR_Const* const_opr = opr->as_constant_ptr(); | |
| 199 if (const_opr->type() == T_OBJECT) { | |
| 200 __ push_oop(const_opr->as_jobject()); | |
| 201 } else if (const_opr->type() == T_INT) { | |
| 202 __ push_jint(const_opr->as_jint()); | |
| 203 } else { | |
| 204 ShouldNotReachHere(); | |
| 205 } | |
| 206 | |
| 207 } else { | |
| 208 ShouldNotReachHere(); | |
| 209 } | |
| 210 } | |
| 211 | |
| 212 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 213 if (opr->is_single_cpu()) { | |
| 304 | 214 __ pop_reg(opr->as_register()); |
| 0 | 215 } else { |
| 216 ShouldNotReachHere(); | |
| 217 } | |
| 218 } | |
| 219 | |
| 304 | 220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
| 221 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
| 222 } | |
| 223 | |
| 0 | 224 //------------------------------------------- |
| 304 | 225 |
| 0 | 226 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
| 304 | 227 return as_Address(addr, rscratch1); |
| 228 } | |
| 229 | |
| 230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
| 0 | 231 if (addr->base()->is_illegal()) { |
| 232 assert(addr->index()->is_illegal(), "must be illegal too"); | |
| 304 | 233 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
| 234 if (! __ reachable(laddr)) { | |
| 235 __ movptr(tmp, laddr.addr()); | |
| 236 Address res(tmp, 0); | |
| 237 return res; | |
| 238 } else { | |
| 239 return __ as_Address(laddr); | |
| 240 } | |
| 0 | 241 } |
| 242 | |
| 304 | 243 Register base = addr->base()->as_pointer_register(); |
| 0 | 244 |
| 245 if (addr->index()->is_illegal()) { | |
| 246 return Address( base, addr->disp()); | |
| 304 | 247 } else if (addr->index()->is_cpu_register()) { |
| 248 Register index = addr->index()->as_pointer_register(); | |
| 0 | 249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
| 250 } else if (addr->index()->is_constant()) { | |
| 304 | 251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
| 252 assert(Assembler::is_simm32(addr_offset), "must be"); | |
| 0 | 253 |
| 254 return Address(base, addr_offset); | |
| 255 } else { | |
| 256 Unimplemented(); | |
| 257 return Address(); | |
| 258 } | |
| 259 } | |
| 260 | |
| 261 | |
| 262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 263 Address base = as_Address(addr); | |
| 264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
| 265 } | |
| 266 | |
| 267 | |
| 268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 269 return as_Address(addr); | |
| 270 } | |
| 271 | |
| 272 | |
| 273 void LIR_Assembler::osr_entry() { | |
| 274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 275 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 276 ValueStack* entry_state = osr_entry->state(); | |
| 277 int number_of_locks = entry_state->locks_size(); | |
| 278 | |
| 279 // we jump here if osr happens with the interpreter | |
| 280 // state set up to continue at the beginning of the | |
| 281 // loop that triggered osr - in particular, we have | |
| 282 // the following registers setup: | |
| 283 // | |
| 284 // rcx: osr buffer | |
| 285 // | |
| 286 | |
| 287 // build frame | |
| 288 ciMethod* m = compilation()->method(); | |
| 289 __ build_frame(initial_frame_size_in_bytes()); | |
| 290 | |
| 291 // OSR buffer is | |
| 292 // | |
| 293 // locals[nlocals-1..0] | |
| 294 // monitors[0..number_of_locks] | |
| 295 // | |
| 296 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 297 // so first slot in the local array is the last local from the interpreter | |
| 298 // and last slot is local[0] (receiver) from the interpreter | |
| 299 // | |
| 300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 302 // in the interpreter frame (the method lock if a sync method) | |
| 303 | |
| 304 // Initialize monitors in the compiled activation. | |
| 305 // rcx: pointer to osr buffer | |
| 306 // | |
| 307 // All other registers are dead at this point and the locals will be | |
| 308 // copied into place by code emitted in the IR. | |
| 309 | |
| 304 | 310 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
| 0 | 311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
| 312 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 1060 | 313 (2 * BytesPerWord) * (number_of_locks - 1); |
| 314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
| 315 // the OSR buffer using 2 word entries: first the lock and then | |
| 316 // the oop. | |
| 0 | 317 for (int i = 0; i < number_of_locks; i++) { |
| 1060 | 318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
| 0 | 319 #ifdef ASSERT |
| 320 // verify the interpreter's monitor has a non-null object | |
| 321 { | |
| 322 Label L; | |
| 1060 | 323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
| 0 | 324 __ jcc(Assembler::notZero, L); |
| 325 __ stop("locked object is NULL"); | |
| 326 __ bind(L); | |
| 327 } | |
| 328 #endif | |
| 1060 | 329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
| 304 | 330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
| 1060 | 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
| 304 | 332 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
| 0 | 333 } |
| 334 } | |
| 335 } | |
| 336 | |
| 337 | |
| 338 // inline cache check; done before the frame is built. | |
| 339 int LIR_Assembler::check_icache() { | |
| 340 Register receiver = FrameMap::receiver_opr->as_register(); | |
| 341 Register ic_klass = IC_Klass; | |
| 304 | 342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
| 2002 | 343 const bool do_post_padding = VerifyOops || UseCompressedOops; |
| 344 if (!do_post_padding) { | |
| 0 | 345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
| 304 | 346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
| 0 | 347 __ nop(); |
| 348 } | |
| 349 } | |
| 350 int offset = __ offset(); | |
| 351 __ inline_cache_check(receiver, IC_Klass); | |
| 2002 | 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
| 353 if (do_post_padding) { | |
| 0 | 354 // force alignment after the cache check. |
| 355 // It's been verified to be aligned if !VerifyOops | |
| 356 __ align(CodeEntryAlignment); | |
| 357 } | |
| 358 return offset; | |
| 359 } | |
| 360 | |
| 361 | |
| 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
| 363 jobject o = NULL; | |
| 364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
| 365 __ movoop(reg, o); | |
| 366 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 367 } | |
| 368 | |
| 369 | |
| 370 // This specifies the rsp decrement needed to build the frame | |
| 371 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 372 // if rounding, must let FrameMap know! | |
| 304 | 373 |
| 374 // The frame_map records size in slots (32bit word) | |
| 375 | |
| 376 // subtract two words to account for return address and link | |
| 377 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
| 0 | 378 } |
| 379 | |
| 380 | |
| 1204 | 381 int LIR_Assembler::emit_exception_handler() { |
| 0 | 382 // if the last instruction is a call (typically to do a throw which |
| 383 // is coming at the end after block reordering) the return address | |
| 384 // must still point into the code area in order to avoid assertion | |
| 385 // failures when searching for the corresponding bci => add a nop | |
| 386 // (was bug 5/14/1999 - gri) | |
| 387 __ nop(); | |
| 388 | |
| 389 // generate code for exception handler | |
| 390 address handler_base = __ start_a_stub(exception_handler_size); | |
| 391 if (handler_base == NULL) { | |
| 392 // not enough space left for the handler | |
| 393 bailout("exception handler overflow"); | |
| 1204 | 394 return -1; |
| 0 | 395 } |
| 1204 | 396 |
| 0 | 397 int offset = code_offset(); |
| 398 | |
| 1295 | 399 // the exception oop and pc are in rax, and rdx |
| 0 | 400 // no other registers need to be preserved, so invalidate them |
| 1295 | 401 __ invalidate_registers(false, true, true, false, true, true); |
| 0 | 402 |
| 403 // check that there is really an exception | |
| 404 __ verify_not_null_oop(rax); | |
| 405 | |
| 1295 | 406 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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407 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); |
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408 __ should_not_reach_here(); |
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409 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); |
| 0 | 410 __ end_a_stub(); |
| 1204 | 411 |
| 412 return offset; | |
| 0 | 413 } |
| 414 | |
| 1204 | 415 |
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416 // Emit the code to remove the frame from the stack in the exception |
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417 // unwind path. |
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418 int LIR_Assembler::emit_unwind_handler() { |
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419 #ifndef PRODUCT |
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420 if (CommentedAssembly) { |
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421 _masm->block_comment("Unwind handler"); |
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422 } |
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423 #endif |
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424 |
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425 int offset = code_offset(); |
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426 |
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427 // Fetch the exception from TLS and clear out exception related thread state |
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428 __ get_thread(rsi); |
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429 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
| 3960 | 430 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); |
| 431 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); | |
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432 |
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433 __ bind(_unwind_handler_entry); |
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434 __ verify_not_null_oop(rax); |
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435 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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436 __ mov(rsi, rax); // Preserve the exception |
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437 } |
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438 |
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439 // Preform needed unlocking |
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440 MonitorExitStub* stub = NULL; |
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441 if (method()->is_synchronized()) { |
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442 monitor_address(0, FrameMap::rax_opr); |
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443 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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444 __ unlock_object(rdi, rbx, rax, *stub->entry()); |
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445 __ bind(*stub->continuation()); |
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446 } |
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447 |
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448 if (compilation()->env()->dtrace_method_probes()) { |
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449 __ get_thread(rax); |
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450 __ movptr(Address(rsp, 0), rax); |
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451 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
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452 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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453 } |
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454 |
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455 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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456 __ mov(rax, rsi); // Restore the exception |
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457 } |
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458 |
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459 // remove the activation and dispatch to the unwind handler |
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460 __ remove_frame(initial_frame_size_in_bytes()); |
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461 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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462 |
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463 // Emit the slow path assembly |
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464 if (stub != NULL) { |
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465 stub->emit_code(this); |
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466 } |
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467 |
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468 return offset; |
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469 } |
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470 |
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471 |
| 1204 | 472 int LIR_Assembler::emit_deopt_handler() { |
| 0 | 473 // if the last instruction is a call (typically to do a throw which |
| 474 // is coming at the end after block reordering) the return address | |
| 475 // must still point into the code area in order to avoid assertion | |
| 476 // failures when searching for the corresponding bci => add a nop | |
| 477 // (was bug 5/14/1999 - gri) | |
| 478 __ nop(); | |
| 479 | |
| 480 // generate code for exception handler | |
| 481 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 482 if (handler_base == NULL) { | |
| 483 // not enough space left for the handler | |
| 484 bailout("deopt handler overflow"); | |
| 1204 | 485 return -1; |
| 0 | 486 } |
| 1204 | 487 |
| 0 | 488 int offset = code_offset(); |
| 489 InternalAddress here(__ pc()); | |
| 1295 | 490 |
| 0 | 491 __ pushptr(here.addr()); |
| 492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
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493 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); |
| 0 | 494 __ end_a_stub(); |
| 495 | |
| 1204 | 496 return offset; |
| 0 | 497 } |
| 498 | |
| 499 | |
| 500 // This is the fast version of java.lang.String.compare; it has not | |
| 501 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 502 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
| 304 | 503 __ movptr (rbx, rcx); // receiver is in rcx |
| 504 __ movptr (rax, arg1->as_register()); | |
| 0 | 505 |
| 506 // Get addresses of first characters from both Strings | |
| 2002 | 507 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
| 508 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
| 509 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 510 |
| 511 | |
| 512 // rbx, may be NULL | |
| 513 add_debug_info_for_null_check_here(info); | |
| 2002 | 514 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
| 515 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
| 516 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 517 |
| 518 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
|
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519 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
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520 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
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521 __ mov (rcx, rbx); |
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522 __ subptr(rbx, rax); // subtract lengths |
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523 __ push (rbx); // result |
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524 __ cmov (Assembler::lessEqual, rax, rcx); |
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525 |
| 0 | 526 // is minimum length 0? |
| 527 Label noLoop, haveResult; | |
| 304 | 528 __ testptr (rax, rax); |
| 0 | 529 __ jcc (Assembler::zero, noLoop); |
| 530 | |
| 531 // compare first characters | |
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532 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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533 __ load_unsigned_short(rbx, Address(rsi, 0)); |
| 0 | 534 __ subl(rcx, rbx); |
| 535 __ jcc(Assembler::notZero, haveResult); | |
| 536 // starting loop | |
| 537 __ decrement(rax); // we already tested index: skip one | |
| 538 __ jcc(Assembler::zero, noLoop); | |
| 539 | |
| 540 // set rsi.edi to the end of the arrays (arrays have same length) | |
| 541 // negate the index | |
| 542 | |
| 304 | 543 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
| 544 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
| 545 __ negptr(rax); | |
| 0 | 546 |
| 547 // compare the strings in a loop | |
| 548 | |
| 549 Label loop; | |
| 550 __ align(wordSize); | |
| 551 __ bind(loop); | |
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552 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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553 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
| 0 | 554 __ subl(rcx, rbx); |
| 555 __ jcc(Assembler::notZero, haveResult); | |
| 556 __ increment(rax); | |
| 557 __ jcc(Assembler::notZero, loop); | |
| 558 | |
| 559 // strings are equal up to min length | |
| 560 | |
| 561 __ bind(noLoop); | |
| 304 | 562 __ pop(rax); |
| 0 | 563 return_op(LIR_OprFact::illegalOpr); |
| 564 | |
| 565 __ bind(haveResult); | |
| 566 // leave instruction is going to discard the TOS value | |
| 304 | 567 __ mov (rax, rcx); // result of call is in rax, |
| 0 | 568 } |
| 569 | |
| 570 | |
| 571 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 572 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
| 573 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
| 574 assert(result->fpu() == 0, "result must already be on TOS"); | |
| 575 } | |
| 576 | |
| 577 // Pop the stack before the safepoint code | |
| 1295 | 578 __ remove_frame(initial_frame_size_in_bytes()); |
| 0 | 579 |
| 580 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
| 581 | |
| 582 // Note: we do not need to round double result; float result has the right precision | |
| 583 // the poll sets the condition code, but no data registers | |
| 584 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 585 relocInfo::poll_return_type); | |
| 304 | 586 |
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587 if (Assembler::is_polling_page_far()) { |
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588 __ lea(rscratch1, polling_page); |
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589 __ relocate(relocInfo::poll_return_type); |
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590 __ testl(rax, Address(rscratch1, 0)); |
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591 } else { |
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592 __ testl(rax, polling_page); |
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593 } |
| 0 | 594 __ ret(0); |
| 595 } | |
| 596 | |
| 597 | |
| 598 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 599 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 600 relocInfo::poll_type); | |
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601 guarantee(info != NULL, "Shouldn't be NULL"); |
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602 int offset = __ offset(); |
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603 if (Assembler::is_polling_page_far()) { |
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604 __ lea(rscratch1, polling_page); |
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605 offset = __ offset(); |
| 0 | 606 add_debug_info_for_branch(info); |
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607 __ testl(rax, Address(rscratch1, 0)); |
| 0 | 608 } else { |
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609 add_debug_info_for_branch(info); |
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610 __ testl(rax, polling_page); |
| 0 | 611 } |
| 612 return offset; | |
| 613 } | |
| 614 | |
| 615 | |
| 616 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
| 304 | 617 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
| 0 | 618 } |
| 619 | |
| 620 void LIR_Assembler::swap_reg(Register a, Register b) { | |
| 304 | 621 __ xchgptr(a, b); |
| 0 | 622 } |
| 623 | |
| 624 | |
| 625 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 626 assert(src->is_constant(), "should not call otherwise"); | |
| 627 assert(dest->is_register(), "should not call otherwise"); | |
| 628 LIR_Const* c = src->as_constant_ptr(); | |
| 629 | |
| 630 switch (c->type()) { | |
| 2002 | 631 case T_INT: { |
| 632 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 633 __ movl(dest->as_register(), c->as_jint()); | |
| 634 break; | |
| 635 } | |
| 636 | |
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637 case T_ADDRESS: { |
| 0 | 638 assert(patch_code == lir_patch_none, "no patching handled here"); |
| 2002 | 639 __ movptr(dest->as_register(), c->as_jint()); |
| 0 | 640 break; |
| 641 } | |
| 642 | |
| 643 case T_LONG: { | |
| 644 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 304 | 645 #ifdef _LP64 |
| 646 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
| 647 #else | |
| 648 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
| 649 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
| 650 #endif // _LP64 | |
| 0 | 651 break; |
| 652 } | |
| 653 | |
| 654 case T_OBJECT: { | |
| 655 if (patch_code != lir_patch_none) { | |
| 656 jobject2reg_with_patching(dest->as_register(), info); | |
| 657 } else { | |
| 658 __ movoop(dest->as_register(), c->as_jobject()); | |
| 659 } | |
| 660 break; | |
| 661 } | |
| 662 | |
| 663 case T_FLOAT: { | |
| 664 if (dest->is_single_xmm()) { | |
| 665 if (c->is_zero_float()) { | |
| 666 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
| 667 } else { | |
| 668 __ movflt(dest->as_xmm_float_reg(), | |
| 669 InternalAddress(float_constant(c->as_jfloat()))); | |
| 670 } | |
| 671 } else { | |
| 672 assert(dest->is_single_fpu(), "must be"); | |
| 673 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 674 if (c->is_zero_float()) { | |
| 675 __ fldz(); | |
| 676 } else if (c->is_one_float()) { | |
| 677 __ fld1(); | |
| 678 } else { | |
| 679 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
| 680 } | |
| 681 } | |
| 682 break; | |
| 683 } | |
| 684 | |
| 685 case T_DOUBLE: { | |
| 686 if (dest->is_double_xmm()) { | |
| 687 if (c->is_zero_double()) { | |
| 688 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
| 689 } else { | |
| 690 __ movdbl(dest->as_xmm_double_reg(), | |
| 691 InternalAddress(double_constant(c->as_jdouble()))); | |
| 692 } | |
| 693 } else { | |
| 694 assert(dest->is_double_fpu(), "must be"); | |
| 695 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 696 if (c->is_zero_double()) { | |
| 697 __ fldz(); | |
| 698 } else if (c->is_one_double()) { | |
| 699 __ fld1(); | |
| 700 } else { | |
| 701 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
| 702 } | |
| 703 } | |
| 704 break; | |
| 705 } | |
| 706 | |
| 707 default: | |
| 708 ShouldNotReachHere(); | |
| 709 } | |
| 710 } | |
| 711 | |
| 712 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 713 assert(src->is_constant(), "should not call otherwise"); | |
| 714 assert(dest->is_stack(), "should not call otherwise"); | |
| 715 LIR_Const* c = src->as_constant_ptr(); | |
| 716 | |
| 717 switch (c->type()) { | |
| 718 case T_INT: // fall through | |
| 719 case T_FLOAT: | |
| 2002 | 720 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 721 break; | |
| 722 | |
|
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723 case T_ADDRESS: |
| 2002 | 724 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 0 | 725 break; |
| 726 | |
| 727 case T_OBJECT: | |
| 728 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
| 729 break; | |
| 730 | |
| 731 case T_LONG: // fall through | |
| 732 case T_DOUBLE: | |
| 304 | 733 #ifdef _LP64 |
| 734 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 735 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
| 736 #else | |
| 737 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 738 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
| 739 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 740 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
| 741 #endif // _LP64 | |
| 0 | 742 break; |
| 743 | |
| 744 default: | |
| 745 ShouldNotReachHere(); | |
| 746 } | |
| 747 } | |
| 748 | |
| 2002 | 749 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
| 0 | 750 assert(src->is_constant(), "should not call otherwise"); |
| 751 assert(dest->is_address(), "should not call otherwise"); | |
| 752 LIR_Const* c = src->as_constant_ptr(); | |
| 753 LIR_Address* addr = dest->as_address_ptr(); | |
| 754 | |
| 304 | 755 int null_check_here = code_offset(); |
| 0 | 756 switch (type) { |
| 757 case T_INT: // fall through | |
| 758 case T_FLOAT: | |
| 2002 | 759 __ movl(as_Address(addr), c->as_jint_bits()); |
| 760 break; | |
| 761 | |
|
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762 case T_ADDRESS: |
| 2002 | 763 __ movptr(as_Address(addr), c->as_jint_bits()); |
| 0 | 764 break; |
| 765 | |
| 766 case T_OBJECT: // fall through | |
| 767 case T_ARRAY: | |
| 768 if (c->as_jobject() == NULL) { | |
| 2002 | 769 if (UseCompressedOops && !wide) { |
| 770 __ movl(as_Address(addr), (int32_t)NULL_WORD); | |
| 771 } else { | |
| 772 __ movptr(as_Address(addr), NULL_WORD); | |
| 773 } | |
| 0 | 774 } else { |
| 304 | 775 if (is_literal_address(addr)) { |
| 776 ShouldNotReachHere(); | |
| 777 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
| 778 } else { | |
| 1060 | 779 #ifdef _LP64 |
| 780 __ movoop(rscratch1, c->as_jobject()); | |
| 2002 | 781 if (UseCompressedOops && !wide) { |
| 782 __ encode_heap_oop(rscratch1); | |
| 783 null_check_here = code_offset(); | |
| 784 __ movl(as_Address_lo(addr), rscratch1); | |
| 785 } else { | |
| 786 null_check_here = code_offset(); | |
| 787 __ movptr(as_Address_lo(addr), rscratch1); | |
| 788 } | |
| 1060 | 789 #else |
| 304 | 790 __ movoop(as_Address(addr), c->as_jobject()); |
| 1060 | 791 #endif |
| 304 | 792 } |
| 0 | 793 } |
| 794 break; | |
| 795 | |
| 796 case T_LONG: // fall through | |
| 797 case T_DOUBLE: | |
| 304 | 798 #ifdef _LP64 |
| 799 if (is_literal_address(addr)) { | |
| 800 ShouldNotReachHere(); | |
| 801 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
| 802 } else { | |
| 803 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
| 804 null_check_here = code_offset(); | |
| 805 __ movptr(as_Address_lo(addr), r10); | |
| 806 } | |
| 807 #else | |
| 808 // Always reachable in 32bit so this doesn't produce useless move literal | |
| 809 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
| 810 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
| 811 #endif // _LP64 | |
| 0 | 812 break; |
| 813 | |
| 814 case T_BOOLEAN: // fall through | |
| 815 case T_BYTE: | |
| 816 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
| 817 break; | |
| 818 | |
| 819 case T_CHAR: // fall through | |
| 820 case T_SHORT: | |
| 821 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
| 822 break; | |
| 823 | |
| 824 default: | |
| 825 ShouldNotReachHere(); | |
| 826 }; | |
| 304 | 827 |
| 828 if (info != NULL) { | |
| 829 add_debug_info_for_null_check(null_check_here, info); | |
| 830 } | |
| 0 | 831 } |
| 832 | |
| 833 | |
| 834 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
| 835 assert(src->is_register(), "should not call otherwise"); | |
| 836 assert(dest->is_register(), "should not call otherwise"); | |
| 837 | |
| 838 // move between cpu-registers | |
| 839 if (dest->is_single_cpu()) { | |
| 304 | 840 #ifdef _LP64 |
| 841 if (src->type() == T_LONG) { | |
| 842 // Can do LONG -> OBJECT | |
| 843 move_regs(src->as_register_lo(), dest->as_register()); | |
| 844 return; | |
| 845 } | |
| 846 #endif | |
| 0 | 847 assert(src->is_single_cpu(), "must match"); |
| 848 if (src->type() == T_OBJECT) { | |
| 849 __ verify_oop(src->as_register()); | |
| 850 } | |
| 851 move_regs(src->as_register(), dest->as_register()); | |
| 852 | |
| 853 } else if (dest->is_double_cpu()) { | |
| 304 | 854 #ifdef _LP64 |
| 855 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
| 856 // Surprising to me but we can see move of a long to t_object | |
| 857 __ verify_oop(src->as_register()); | |
| 858 move_regs(src->as_register(), dest->as_register_lo()); | |
| 859 return; | |
| 860 } | |
| 861 #endif | |
| 0 | 862 assert(src->is_double_cpu(), "must match"); |
| 863 Register f_lo = src->as_register_lo(); | |
| 864 Register f_hi = src->as_register_hi(); | |
| 865 Register t_lo = dest->as_register_lo(); | |
| 866 Register t_hi = dest->as_register_hi(); | |
| 304 | 867 #ifdef _LP64 |
| 868 assert(f_hi == f_lo, "must be same"); | |
| 869 assert(t_hi == t_lo, "must be same"); | |
| 870 move_regs(f_lo, t_lo); | |
| 871 #else | |
| 0 | 872 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
| 873 | |
| 304 | 874 |
| 0 | 875 if (f_lo == t_hi && f_hi == t_lo) { |
| 876 swap_reg(f_lo, f_hi); | |
| 877 } else if (f_hi == t_lo) { | |
| 878 assert(f_lo != t_hi, "overwriting register"); | |
| 879 move_regs(f_hi, t_hi); | |
| 880 move_regs(f_lo, t_lo); | |
| 881 } else { | |
| 882 assert(f_hi != t_lo, "overwriting register"); | |
| 883 move_regs(f_lo, t_lo); | |
| 884 move_regs(f_hi, t_hi); | |
| 885 } | |
| 304 | 886 #endif // LP64 |
| 0 | 887 |
| 888 // special moves from fpu-register to xmm-register | |
| 889 // necessary for method results | |
| 890 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
| 891 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
| 892 __ fld_s(Address(rsp, 0)); | |
| 893 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
| 894 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
| 895 __ fld_d(Address(rsp, 0)); | |
| 896 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
| 897 __ fstp_s(Address(rsp, 0)); | |
| 898 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
| 899 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
| 900 __ fstp_d(Address(rsp, 0)); | |
| 901 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
| 902 | |
| 903 // move between xmm-registers | |
| 904 } else if (dest->is_single_xmm()) { | |
| 905 assert(src->is_single_xmm(), "must match"); | |
| 906 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
| 907 } else if (dest->is_double_xmm()) { | |
| 908 assert(src->is_double_xmm(), "must match"); | |
| 909 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
| 910 | |
| 911 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
| 912 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
| 913 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
| 914 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
| 915 } else { | |
| 916 ShouldNotReachHere(); | |
| 917 } | |
| 918 } | |
| 919 | |
| 920 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 921 assert(src->is_register(), "should not call otherwise"); | |
| 922 assert(dest->is_stack(), "should not call otherwise"); | |
| 923 | |
| 924 if (src->is_single_cpu()) { | |
| 925 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 926 if (type == T_OBJECT || type == T_ARRAY) { | |
| 927 __ verify_oop(src->as_register()); | |
| 304 | 928 __ movptr (dst, src->as_register()); |
| 929 } else { | |
| 930 __ movl (dst, src->as_register()); | |
| 0 | 931 } |
| 932 | |
| 933 } else if (src->is_double_cpu()) { | |
| 934 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
| 935 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 936 __ movptr (dstLO, src->as_register_lo()); |
| 937 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
| 0 | 938 |
| 939 } else if (src->is_single_xmm()) { | |
| 940 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 941 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
| 942 | |
| 943 } else if (src->is_double_xmm()) { | |
| 944 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 945 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
| 946 | |
| 947 } else if (src->is_single_fpu()) { | |
| 948 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 949 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 950 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
| 951 else __ fst_s (dst_addr); | |
| 952 | |
| 953 } else if (src->is_double_fpu()) { | |
| 954 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 955 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 956 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
| 957 else __ fst_d (dst_addr); | |
| 958 | |
| 959 } else { | |
| 960 ShouldNotReachHere(); | |
| 961 } | |
| 962 } | |
| 963 | |
| 964 | |
| 2002 | 965 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
| 0 | 966 LIR_Address* to_addr = dest->as_address_ptr(); |
| 967 PatchingStub* patch = NULL; | |
| 2002 | 968 Register compressed_src = rscratch1; |
| 0 | 969 |
| 970 if (type == T_ARRAY || type == T_OBJECT) { | |
| 971 __ verify_oop(src->as_register()); | |
| 2002 | 972 #ifdef _LP64 |
| 973 if (UseCompressedOops && !wide) { | |
| 974 __ movptr(compressed_src, src->as_register()); | |
| 975 __ encode_heap_oop(compressed_src); | |
| 976 } | |
| 977 #endif | |
| 0 | 978 } |
| 2002 | 979 |
| 0 | 980 if (patch_code != lir_patch_none) { |
| 981 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 982 Address toa = as_Address(to_addr); |
| 983 assert(toa.disp() != 0, "must have"); | |
| 0 | 984 } |
| 2002 | 985 |
| 986 int null_check_here = code_offset(); | |
| 0 | 987 switch (type) { |
| 988 case T_FLOAT: { | |
| 989 if (src->is_single_xmm()) { | |
| 990 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
| 991 } else { | |
| 992 assert(src->is_single_fpu(), "must be"); | |
| 993 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 994 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
| 995 else __ fst_s (as_Address(to_addr)); | |
| 996 } | |
| 997 break; | |
| 998 } | |
| 999 | |
| 1000 case T_DOUBLE: { | |
| 1001 if (src->is_double_xmm()) { | |
| 1002 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
| 1003 } else { | |
| 1004 assert(src->is_double_fpu(), "must be"); | |
| 1005 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1006 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
| 1007 else __ fst_d (as_Address(to_addr)); | |
| 1008 } | |
| 1009 break; | |
| 1010 } | |
| 1011 | |
| 1012 case T_ARRAY: // fall through | |
| 1013 case T_OBJECT: // fall through | |
| 2002 | 1014 if (UseCompressedOops && !wide) { |
| 1015 __ movl(as_Address(to_addr), compressed_src); | |
| 1016 } else { | |
| 1017 __ movptr(as_Address(to_addr), src->as_register()); | |
| 1018 } | |
| 1019 break; | |
| 1020 case T_ADDRESS: | |
| 304 | 1021 __ movptr(as_Address(to_addr), src->as_register()); |
| 1022 break; | |
| 0 | 1023 case T_INT: |
| 1024 __ movl(as_Address(to_addr), src->as_register()); | |
| 1025 break; | |
| 1026 | |
| 1027 case T_LONG: { | |
| 1028 Register from_lo = src->as_register_lo(); | |
| 1029 Register from_hi = src->as_register_hi(); | |
| 304 | 1030 #ifdef _LP64 |
| 1031 __ movptr(as_Address_lo(to_addr), from_lo); | |
| 1032 #else | |
| 0 | 1033 Register base = to_addr->base()->as_register(); |
| 1034 Register index = noreg; | |
| 1035 if (to_addr->index()->is_register()) { | |
| 1036 index = to_addr->index()->as_register(); | |
| 1037 } | |
| 1038 if (base == from_lo || index == from_lo) { | |
| 1039 assert(base != from_hi, "can't be"); | |
| 1040 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
| 1041 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1042 if (patch != NULL) { | |
| 1043 patching_epilog(patch, lir_patch_high, base, info); | |
| 1044 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1045 patch_code = lir_patch_low; | |
| 1046 } | |
| 1047 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1048 } else { | |
| 1049 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
| 1050 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1051 if (patch != NULL) { | |
| 1052 patching_epilog(patch, lir_patch_low, base, info); | |
| 1053 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1054 patch_code = lir_patch_high; | |
| 1055 } | |
| 1056 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1057 } | |
| 304 | 1058 #endif // _LP64 |
| 0 | 1059 break; |
| 1060 } | |
| 1061 | |
| 1062 case T_BYTE: // fall through | |
| 1063 case T_BOOLEAN: { | |
| 1064 Register src_reg = src->as_register(); | |
| 1065 Address dst_addr = as_Address(to_addr); | |
| 1066 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1067 __ movb(dst_addr, src_reg); | |
| 1068 break; | |
| 1069 } | |
| 1070 | |
| 1071 case T_CHAR: // fall through | |
| 1072 case T_SHORT: | |
| 1073 __ movw(as_Address(to_addr), src->as_register()); | |
| 1074 break; | |
| 1075 | |
| 1076 default: | |
| 1077 ShouldNotReachHere(); | |
| 1078 } | |
| 2002 | 1079 if (info != NULL) { |
| 1080 add_debug_info_for_null_check(null_check_here, info); | |
| 1081 } | |
| 0 | 1082 |
| 1083 if (patch_code != lir_patch_none) { | |
| 1084 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
| 1085 } | |
| 1086 } | |
| 1087 | |
| 1088 | |
| 1089 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1090 assert(src->is_stack(), "should not call otherwise"); | |
| 1091 assert(dest->is_register(), "should not call otherwise"); | |
| 1092 | |
| 1093 if (dest->is_single_cpu()) { | |
| 1094 if (type == T_ARRAY || type == T_OBJECT) { | |
| 304 | 1095 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
| 0 | 1096 __ verify_oop(dest->as_register()); |
| 304 | 1097 } else { |
| 1098 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
| 0 | 1099 } |
| 1100 | |
| 1101 } else if (dest->is_double_cpu()) { | |
| 1102 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
| 1103 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 1104 __ movptr(dest->as_register_lo(), src_addr_LO); |
| 1105 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
| 0 | 1106 |
| 1107 } else if (dest->is_single_xmm()) { | |
| 1108 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1109 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
| 1110 | |
| 1111 } else if (dest->is_double_xmm()) { | |
| 1112 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1113 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
| 1114 | |
| 1115 } else if (dest->is_single_fpu()) { | |
| 1116 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1118 __ fld_s(src_addr); | |
| 1119 | |
| 1120 } else if (dest->is_double_fpu()) { | |
| 1121 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1122 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1123 __ fld_d(src_addr); | |
| 1124 | |
| 1125 } else { | |
| 1126 ShouldNotReachHere(); | |
| 1127 } | |
| 1128 } | |
| 1129 | |
| 1130 | |
| 1131 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1132 if (src->is_single_stack()) { | |
| 304 | 1133 if (type == T_OBJECT || type == T_ARRAY) { |
| 1134 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1135 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1136 } else { | |
| 1060 | 1137 #ifndef _LP64 |
| 304 | 1138 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
| 1139 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1060 | 1140 #else |
| 1141 //no pushl on 64bits | |
| 1142 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1143 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
| 1144 #endif | |
| 304 | 1145 } |
| 0 | 1146 |
| 1147 } else if (src->is_double_stack()) { | |
| 304 | 1148 #ifdef _LP64 |
| 1149 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
| 1150 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 1151 #else | |
| 0 | 1152 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
| 304 | 1153 // push and pop the part at src + wordSize, adding wordSize for the previous push |
|
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1154 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1155 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
| 0 | 1156 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
| 304 | 1157 #endif // _LP64 |
| 0 | 1158 |
| 1159 } else { | |
| 1160 ShouldNotReachHere(); | |
| 1161 } | |
| 1162 } | |
| 1163 | |
| 1164 | |
| 2002 | 1165 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
| 0 | 1166 assert(src->is_address(), "should not call otherwise"); |
| 1167 assert(dest->is_register(), "should not call otherwise"); | |
| 1168 | |
| 1169 LIR_Address* addr = src->as_address_ptr(); | |
| 1170 Address from_addr = as_Address(addr); | |
| 1171 | |
| 1172 switch (type) { | |
| 1173 case T_BOOLEAN: // fall through | |
| 1174 case T_BYTE: // fall through | |
| 1175 case T_CHAR: // fall through | |
| 1176 case T_SHORT: | |
| 1177 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
| 1178 // on pre P6 processors we may get partial register stalls | |
| 1179 // so blow away the value of to_rinfo before loading a | |
| 1180 // partial word into it. Do it here so that it precedes | |
| 1181 // the potential patch point below. | |
| 304 | 1182 __ xorptr(dest->as_register(), dest->as_register()); |
| 0 | 1183 } |
| 1184 break; | |
| 1185 } | |
| 1186 | |
| 1187 PatchingStub* patch = NULL; | |
| 1188 if (patch_code != lir_patch_none) { | |
| 1189 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1190 assert(from_addr.disp() != 0, "must have"); |
| 0 | 1191 } |
| 1192 if (info != NULL) { | |
| 1193 add_debug_info_for_null_check_here(info); | |
| 1194 } | |
| 1195 | |
| 1196 switch (type) { | |
| 1197 case T_FLOAT: { | |
| 1198 if (dest->is_single_xmm()) { | |
| 1199 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
| 1200 } else { | |
| 1201 assert(dest->is_single_fpu(), "must be"); | |
| 1202 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1203 __ fld_s(from_addr); | |
| 1204 } | |
| 1205 break; | |
| 1206 } | |
| 1207 | |
| 1208 case T_DOUBLE: { | |
| 1209 if (dest->is_double_xmm()) { | |
| 1210 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
| 1211 } else { | |
| 1212 assert(dest->is_double_fpu(), "must be"); | |
| 1213 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1214 __ fld_d(from_addr); | |
| 1215 } | |
| 1216 break; | |
| 1217 } | |
| 1218 | |
| 1219 case T_OBJECT: // fall through | |
| 1220 case T_ARRAY: // fall through | |
| 2002 | 1221 if (UseCompressedOops && !wide) { |
| 1222 __ movl(dest->as_register(), from_addr); | |
| 1223 } else { | |
| 1224 __ movptr(dest->as_register(), from_addr); | |
| 1225 } | |
| 1226 break; | |
| 1227 | |
| 1228 case T_ADDRESS: | |
| 304 | 1229 __ movptr(dest->as_register(), from_addr); |
| 1230 break; | |
| 0 | 1231 case T_INT: |
|
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|
1232 __ movl(dest->as_register(), from_addr); |
| 0 | 1233 break; |
| 1234 | |
| 1235 case T_LONG: { | |
| 1236 Register to_lo = dest->as_register_lo(); | |
| 1237 Register to_hi = dest->as_register_hi(); | |
| 304 | 1238 #ifdef _LP64 |
| 1239 __ movptr(to_lo, as_Address_lo(addr)); | |
| 1240 #else | |
| 0 | 1241 Register base = addr->base()->as_register(); |
| 1242 Register index = noreg; | |
| 1243 if (addr->index()->is_register()) { | |
| 1244 index = addr->index()->as_register(); | |
| 1245 } | |
| 1246 if ((base == to_lo && index == to_hi) || | |
| 1247 (base == to_hi && index == to_lo)) { | |
| 1248 // addresses with 2 registers are only formed as a result of | |
| 1249 // array access so this code will never have to deal with | |
| 1250 // patches or null checks. | |
| 1251 assert(info == NULL && patch == NULL, "must be"); | |
| 304 | 1252 __ lea(to_hi, as_Address(addr)); |
| 0 | 1253 __ movl(to_lo, Address(to_hi, 0)); |
| 1254 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
| 1255 } else if (base == to_lo || index == to_lo) { | |
| 1256 assert(base != to_hi, "can't be"); | |
| 1257 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
| 1258 __ movl(to_hi, as_Address_hi(addr)); | |
| 1259 if (patch != NULL) { | |
| 1260 patching_epilog(patch, lir_patch_high, base, info); | |
| 1261 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1262 patch_code = lir_patch_low; | |
| 1263 } | |
| 1264 __ movl(to_lo, as_Address_lo(addr)); | |
| 1265 } else { | |
| 1266 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
| 1267 __ movl(to_lo, as_Address_lo(addr)); | |
| 1268 if (patch != NULL) { | |
| 1269 patching_epilog(patch, lir_patch_low, base, info); | |
| 1270 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1271 patch_code = lir_patch_high; | |
| 1272 } | |
| 1273 __ movl(to_hi, as_Address_hi(addr)); | |
| 1274 } | |
| 304 | 1275 #endif // _LP64 |
| 0 | 1276 break; |
| 1277 } | |
| 1278 | |
| 1279 case T_BOOLEAN: // fall through | |
| 1280 case T_BYTE: { | |
| 1281 Register dest_reg = dest->as_register(); | |
| 1282 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1283 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1284 __ movsbl(dest_reg, from_addr); |
| 0 | 1285 } else { |
| 1286 __ movb(dest_reg, from_addr); | |
| 1287 __ shll(dest_reg, 24); | |
| 1288 __ sarl(dest_reg, 24); | |
| 1289 } | |
| 1290 break; | |
| 1291 } | |
| 1292 | |
| 1293 case T_CHAR: { | |
| 1294 Register dest_reg = dest->as_register(); | |
| 1295 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1296 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1297 __ movzwl(dest_reg, from_addr); |
| 0 | 1298 } else { |
| 1299 __ movw(dest_reg, from_addr); | |
| 1300 } | |
| 1301 break; | |
| 1302 } | |
| 1303 | |
| 1304 case T_SHORT: { | |
| 1305 Register dest_reg = dest->as_register(); | |
| 1306 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1307 __ movswl(dest_reg, from_addr); |
| 0 | 1308 } else { |
| 1309 __ movw(dest_reg, from_addr); | |
| 1310 __ shll(dest_reg, 16); | |
| 1311 __ sarl(dest_reg, 16); | |
| 1312 } | |
| 1313 break; | |
| 1314 } | |
| 1315 | |
| 1316 default: | |
| 1317 ShouldNotReachHere(); | |
| 1318 } | |
| 1319 | |
| 1320 if (patch != NULL) { | |
| 1321 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
| 1322 } | |
| 1323 | |
| 1324 if (type == T_ARRAY || type == T_OBJECT) { | |
| 2002 | 1325 #ifdef _LP64 |
| 1326 if (UseCompressedOops && !wide) { | |
| 1327 __ decode_heap_oop(dest->as_register()); | |
| 1328 } | |
| 1329 #endif | |
| 0 | 1330 __ verify_oop(dest->as_register()); |
| 1331 } | |
| 1332 } | |
| 1333 | |
| 1334 | |
| 1335 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1336 LIR_Address* addr = src->as_address_ptr(); | |
| 1337 Address from_addr = as_Address(addr); | |
| 1338 | |
| 1339 if (VM_Version::supports_sse()) { | |
| 1340 switch (ReadPrefetchInstr) { | |
| 1341 case 0: | |
| 1342 __ prefetchnta(from_addr); break; | |
| 1343 case 1: | |
| 1344 __ prefetcht0(from_addr); break; | |
| 1345 case 2: | |
| 1346 __ prefetcht2(from_addr); break; | |
| 1347 default: | |
| 1348 ShouldNotReachHere(); break; | |
| 1349 } | |
| 2479 | 1350 } else if (VM_Version::supports_3dnow_prefetch()) { |
| 0 | 1351 __ prefetchr(from_addr); |
| 1352 } | |
| 1353 } | |
| 1354 | |
| 1355 | |
| 1356 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1357 LIR_Address* addr = src->as_address_ptr(); | |
| 1358 Address from_addr = as_Address(addr); | |
| 1359 | |
| 1360 if (VM_Version::supports_sse()) { | |
| 1361 switch (AllocatePrefetchInstr) { | |
| 1362 case 0: | |
| 1363 __ prefetchnta(from_addr); break; | |
| 1364 case 1: | |
| 1365 __ prefetcht0(from_addr); break; | |
| 1366 case 2: | |
| 1367 __ prefetcht2(from_addr); break; | |
| 1368 case 3: | |
| 1369 __ prefetchw(from_addr); break; | |
| 1370 default: | |
| 1371 ShouldNotReachHere(); break; | |
| 1372 } | |
| 2479 | 1373 } else if (VM_Version::supports_3dnow_prefetch()) { |
| 0 | 1374 __ prefetchw(from_addr); |
| 1375 } | |
| 1376 } | |
| 1377 | |
| 1378 | |
| 1379 NEEDS_CLEANUP; // This could be static? | |
| 1380 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
|
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1381 int elem_size = type2aelembytes(type); |
| 0 | 1382 switch (elem_size) { |
| 1383 case 1: return Address::times_1; | |
| 1384 case 2: return Address::times_2; | |
| 1385 case 4: return Address::times_4; | |
| 1386 case 8: return Address::times_8; | |
| 1387 } | |
| 1388 ShouldNotReachHere(); | |
| 1389 return Address::no_scale; | |
| 1390 } | |
| 1391 | |
| 1392 | |
| 1393 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 1394 switch (op->code()) { | |
| 1395 case lir_idiv: | |
| 1396 case lir_irem: | |
| 1397 arithmetic_idiv(op->code(), | |
| 1398 op->in_opr1(), | |
| 1399 op->in_opr2(), | |
| 1400 op->in_opr3(), | |
| 1401 op->result_opr(), | |
| 1402 op->info()); | |
| 1403 break; | |
| 1404 default: ShouldNotReachHere(); break; | |
| 1405 } | |
| 1406 } | |
| 1407 | |
| 1408 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 1409 #ifdef ASSERT | |
| 1410 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 1411 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 1412 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 1413 #endif | |
| 1414 | |
| 1415 if (op->cond() == lir_cond_always) { | |
| 1416 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
| 1417 __ jmp (*(op->label())); | |
| 1418 } else { | |
| 1419 Assembler::Condition acond = Assembler::zero; | |
| 1420 if (op->code() == lir_cond_float_branch) { | |
| 1421 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 1422 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
| 1423 switch(op->cond()) { | |
| 1424 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1425 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1426 case lir_cond_less: acond = Assembler::below; break; | |
| 1427 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
| 1428 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
| 1429 case lir_cond_greater: acond = Assembler::above; break; | |
| 1430 default: ShouldNotReachHere(); | |
| 1431 } | |
| 1432 } else { | |
| 1433 switch (op->cond()) { | |
| 1434 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1435 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1436 case lir_cond_less: acond = Assembler::less; break; | |
| 1437 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1438 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
| 1439 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1440 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
| 1441 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
| 1442 default: ShouldNotReachHere(); | |
| 1443 } | |
| 1444 } | |
| 1445 __ jcc(acond,*(op->label())); | |
| 1446 } | |
| 1447 } | |
| 1448 | |
| 1449 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 1450 LIR_Opr src = op->in_opr(); | |
| 1451 LIR_Opr dest = op->result_opr(); | |
| 1452 | |
| 1453 switch (op->bytecode()) { | |
| 1454 case Bytecodes::_i2l: | |
| 304 | 1455 #ifdef _LP64 |
| 1456 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
| 1457 #else | |
| 0 | 1458 move_regs(src->as_register(), dest->as_register_lo()); |
| 1459 move_regs(src->as_register(), dest->as_register_hi()); | |
| 1460 __ sarl(dest->as_register_hi(), 31); | |
| 304 | 1461 #endif // LP64 |
| 0 | 1462 break; |
| 1463 | |
| 1464 case Bytecodes::_l2i: | |
| 6041 | 1465 #ifdef _LP64 |
| 1466 __ movl(dest->as_register(), src->as_register_lo()); | |
| 1467 #else | |
| 0 | 1468 move_regs(src->as_register_lo(), dest->as_register()); |
| 6041 | 1469 #endif |
| 0 | 1470 break; |
| 1471 | |
| 1472 case Bytecodes::_i2b: | |
| 1473 move_regs(src->as_register(), dest->as_register()); | |
| 1474 __ sign_extend_byte(dest->as_register()); | |
| 1475 break; | |
| 1476 | |
| 1477 case Bytecodes::_i2c: | |
| 1478 move_regs(src->as_register(), dest->as_register()); | |
| 1479 __ andl(dest->as_register(), 0xFFFF); | |
| 1480 break; | |
| 1481 | |
| 1482 case Bytecodes::_i2s: | |
| 1483 move_regs(src->as_register(), dest->as_register()); | |
| 1484 __ sign_extend_short(dest->as_register()); | |
| 1485 break; | |
| 1486 | |
| 1487 | |
| 1488 case Bytecodes::_f2d: | |
| 1489 case Bytecodes::_d2f: | |
| 1490 if (dest->is_single_xmm()) { | |
| 1491 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
| 1492 } else if (dest->is_double_xmm()) { | |
| 1493 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
| 1494 } else { | |
| 1495 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
| 1496 // do nothing (float result is rounded later through spilling) | |
| 1497 } | |
| 1498 break; | |
| 1499 | |
| 1500 case Bytecodes::_i2f: | |
| 1501 case Bytecodes::_i2d: | |
| 1502 if (dest->is_single_xmm()) { | |
| 304 | 1503 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
| 0 | 1504 } else if (dest->is_double_xmm()) { |
| 304 | 1505 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
| 0 | 1506 } else { |
| 1507 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1508 __ movl(Address(rsp, 0), src->as_register()); | |
| 1509 __ fild_s(Address(rsp, 0)); | |
| 1510 } | |
| 1511 break; | |
| 1512 | |
| 1513 case Bytecodes::_f2i: | |
| 1514 case Bytecodes::_d2i: | |
| 1515 if (src->is_single_xmm()) { | |
| 304 | 1516 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
| 0 | 1517 } else if (src->is_double_xmm()) { |
| 304 | 1518 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
| 0 | 1519 } else { |
| 1520 assert(src->fpu() == 0, "input must be on TOS"); | |
| 1521 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 1522 __ fist_s(Address(rsp, 0)); | |
| 1523 __ movl(dest->as_register(), Address(rsp, 0)); | |
| 1524 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1525 } | |
| 1526 | |
| 1527 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
| 1528 assert(op->stub() != NULL, "stub required"); | |
| 1529 __ cmpl(dest->as_register(), 0x80000000); | |
| 1530 __ jcc(Assembler::equal, *op->stub()->entry()); | |
| 1531 __ bind(*op->stub()->continuation()); | |
| 1532 break; | |
| 1533 | |
| 1534 case Bytecodes::_l2f: | |
| 1535 case Bytecodes::_l2d: | |
| 1536 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
| 1537 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1538 | |
| 304 | 1539 __ movptr(Address(rsp, 0), src->as_register_lo()); |
| 1540 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
| 0 | 1541 __ fild_d(Address(rsp, 0)); |
| 1542 // float result is rounded later through spilling | |
| 1543 break; | |
| 1544 | |
| 1545 case Bytecodes::_f2l: | |
| 1546 case Bytecodes::_d2l: | |
| 1547 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
| 1548 assert(src->fpu() == 0, "input must be on TOS"); | |
| 304 | 1549 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
| 0 | 1550 |
| 1551 // instruction sequence too long to inline it here | |
| 1552 { | |
| 1553 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
| 1554 } | |
| 1555 break; | |
| 1556 | |
| 1557 default: ShouldNotReachHere(); | |
| 1558 } | |
| 1559 } | |
| 1560 | |
| 1561 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 1562 if (op->init_check()) { | |
|
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1563 __ cmpb(Address(op->klass()->as_register(), |
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1564 instanceKlass::init_state_offset()), |
| 0 | 1565 instanceKlass::fully_initialized); |
| 1566 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 1567 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
| 1568 } | |
| 1569 __ allocate_object(op->obj()->as_register(), | |
| 1570 op->tmp1()->as_register(), | |
| 1571 op->tmp2()->as_register(), | |
| 1572 op->header_size(), | |
| 1573 op->object_size(), | |
| 1574 op->klass()->as_register(), | |
| 1575 *op->stub()->entry()); | |
| 1576 __ bind(*op->stub()->continuation()); | |
| 1577 } | |
| 1578 | |
| 1579 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
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1580 Register len = op->len()->as_register(); |
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7010618: C1: array length should be treated at int on 64bit during array allocation
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1581 LP64_ONLY( __ movslq(len, len); ) |
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1582 |
| 0 | 1583 if (UseSlowPath || |
| 1584 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 1585 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
| 1586 __ jmp(*op->stub()->entry()); | |
| 1587 } else { | |
| 1588 Register tmp1 = op->tmp1()->as_register(); | |
| 1589 Register tmp2 = op->tmp2()->as_register(); | |
| 1590 Register tmp3 = op->tmp3()->as_register(); | |
| 1591 if (len == tmp1) { | |
| 1592 tmp1 = tmp3; | |
| 1593 } else if (len == tmp2) { | |
| 1594 tmp2 = tmp3; | |
| 1595 } else if (len == tmp3) { | |
| 1596 // everything is ok | |
| 1597 } else { | |
| 304 | 1598 __ mov(tmp3, len); |
| 0 | 1599 } |
| 1600 __ allocate_array(op->obj()->as_register(), | |
| 1601 len, | |
| 1602 tmp1, | |
| 1603 tmp2, | |
| 1604 arrayOopDesc::header_size(op->type()), | |
| 1605 array_element_size(op->type()), | |
| 1606 op->klass()->as_register(), | |
| 1607 *op->stub()->entry()); | |
| 1608 } | |
| 1609 __ bind(*op->stub()->continuation()); | |
| 1610 } | |
| 1611 | |
| 1783 | 1612 void LIR_Assembler::type_profile_helper(Register mdo, |
| 1613 ciMethodData *md, ciProfileData *data, | |
| 1614 Register recv, Label* update_done) { | |
|
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1615 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1616 Label next_test; |
| 1617 // See if the receiver is receiver[n]. | |
| 1618 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
| 1619 __ jccb(Assembler::notEqual, next_test); | |
| 1620 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
| 1621 __ addptr(data_addr, DataLayout::counter_increment); | |
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1622 __ jmp(*update_done); |
| 1783 | 1623 __ bind(next_test); |
| 1624 } | |
| 1625 | |
| 1626 // Didn't find receiver; find next empty slot and fill it in | |
|
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1627 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1628 Label next_test; |
| 1629 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
| 1630 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
| 1631 __ jccb(Assembler::notEqual, next_test); | |
| 1632 __ movptr(recv_addr, recv); | |
| 1633 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
|
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1634 __ jmp(*update_done); |
| 1783 | 1635 __ bind(next_test); |
| 1636 } | |
| 1637 } | |
| 1638 | |
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1639 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
| 1783 | 1640 // we always need a stub for the failure case. |
| 1641 CodeStub* stub = op->stub(); | |
| 1642 Register obj = op->object()->as_register(); | |
| 1643 Register k_RInfo = op->tmp1()->as_register(); | |
| 1644 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1645 Register dst = op->result_opr()->as_register(); | |
| 1646 ciKlass* k = op->klass(); | |
| 1647 Register Rtmp1 = noreg; | |
| 1648 | |
| 1649 // check if it needs to be profiled | |
| 1650 ciMethodData* md; | |
| 1651 ciProfileData* data; | |
| 1652 | |
| 1653 if (op->should_profile()) { | |
| 1654 ciMethod* method = op->profiled_method(); | |
| 1655 assert(method != NULL, "Should have method"); | |
| 1656 int bci = op->profiled_bci(); | |
|
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1657 md = method->method_data_or_null(); |
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1658 assert(md != NULL, "Sanity"); |
| 1783 | 1659 data = md->bci_to_data(bci); |
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1660 assert(data != NULL, "need data for type check"); |
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1661 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
| 1783 | 1662 } |
|
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1663 Label profile_cast_success, profile_cast_failure; |
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1664 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
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1665 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
| 1783 | 1666 |
| 1667 if (obj == k_RInfo) { | |
| 1668 k_RInfo = dst; | |
| 1669 } else if (obj == klass_RInfo) { | |
| 1670 klass_RInfo = dst; | |
| 1671 } | |
| 2002 | 1672 if (k->is_loaded() && !UseCompressedOops) { |
| 1783 | 1673 select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
| 1674 } else { | |
| 1675 Rtmp1 = op->tmp3()->as_register(); | |
| 1676 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
| 1677 } | |
| 1678 | |
| 1679 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
| 1680 if (!k->is_loaded()) { | |
| 1681 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 1682 } else { | |
| 1683 #ifdef _LP64 | |
| 1684 __ movoop(k_RInfo, k->constant_encoding()); | |
| 1685 #endif // _LP64 | |
| 1686 } | |
| 1687 assert(obj != k_RInfo, "must be different"); | |
| 1688 | |
| 1689 __ cmpptr(obj, (int32_t)NULL_WORD); | |
| 1690 if (op->should_profile()) { | |
|
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1691 Label not_null; |
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1692 __ jccb(Assembler::notEqual, not_null); |
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1693 // Object is null; update MDO and exit |
| 1783 | 1694 Register mdo = klass_RInfo; |
| 1695 __ movoop(mdo, md->constant_encoding()); | |
| 1696 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); | |
| 1697 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
| 1698 __ orl(data_addr, header_bits); | |
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1699 __ jmp(*obj_is_null); |
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1700 __ bind(not_null); |
| 1783 | 1701 } else { |
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1702 __ jcc(Assembler::equal, *obj_is_null); |
| 1783 | 1703 } |
| 1704 __ verify_oop(obj); | |
| 1705 | |
| 1706 if (op->fast_check()) { | |
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1707 // get object class |
| 1783 | 1708 // not a safepoint as obj null check happens earlier |
| 1709 #ifdef _LP64 | |
| 2002 | 1710 if (UseCompressedOops) { |
| 1711 __ load_klass(Rtmp1, obj); | |
| 1712 __ cmpptr(k_RInfo, Rtmp1); | |
| 1783 | 1713 } else { |
| 1714 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1715 } | |
| 2002 | 1716 #else |
| 1717 if (k->is_loaded()) { | |
| 1718 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); | |
| 1719 } else { | |
| 1720 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1721 } | |
| 1722 #endif | |
| 1783 | 1723 __ jcc(Assembler::notEqual, *failure_target); |
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1724 // successful cast, fall through to profile or jump |
| 1783 | 1725 } else { |
| 1726 // get object class | |
| 1727 // not a safepoint as obj null check happens earlier | |
| 2002 | 1728 __ load_klass(klass_RInfo, obj); |
| 1783 | 1729 if (k->is_loaded()) { |
| 1730 // See if we get an immediate positive hit | |
| 1731 #ifdef _LP64 | |
| 1732 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
| 1733 #else | |
| 1734 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); | |
| 1735 #endif // _LP64 | |
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1736 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { |
| 1783 | 1737 __ jcc(Assembler::notEqual, *failure_target); |
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1738 // successful cast, fall through to profile or jump |
| 1783 | 1739 } else { |
| 1740 // See if we get an immediate positive hit | |
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1741 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1742 // check for self |
| 1743 #ifdef _LP64 | |
| 1744 __ cmpptr(klass_RInfo, k_RInfo); | |
| 1745 #else | |
| 1746 __ cmpoop(klass_RInfo, k->constant_encoding()); | |
| 1747 #endif // _LP64 | |
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1748 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1749 |
| 1750 __ push(klass_RInfo); | |
| 1751 #ifdef _LP64 | |
| 1752 __ push(k_RInfo); | |
| 1753 #else | |
| 1754 __ pushoop(k->constant_encoding()); | |
| 1755 #endif // _LP64 | |
| 1756 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1757 __ pop(klass_RInfo); | |
| 1758 __ pop(klass_RInfo); | |
| 1759 // result is a boolean | |
| 1760 __ cmpl(klass_RInfo, 0); | |
| 1761 __ jcc(Assembler::equal, *failure_target); | |
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1762 // successful cast, fall through to profile or jump |
| 1783 | 1763 } |
| 1764 } else { | |
| 1765 // perform the fast part of the checking logic | |
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1766 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
| 1783 | 1767 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 1768 __ push(klass_RInfo); | |
| 1769 __ push(k_RInfo); | |
| 1770 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1771 __ pop(klass_RInfo); | |
| 1772 __ pop(k_RInfo); | |
| 1773 // result is a boolean | |
| 1774 __ cmpl(k_RInfo, 0); | |
| 1775 __ jcc(Assembler::equal, *failure_target); | |
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1776 // successful cast, fall through to profile or jump |
| 1783 | 1777 } |
| 1778 } | |
| 1779 if (op->should_profile()) { | |
| 1780 Register mdo = klass_RInfo, recv = k_RInfo; | |
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1781 __ bind(profile_cast_success); |
| 1783 | 1782 __ movoop(mdo, md->constant_encoding()); |
| 2002 | 1783 __ load_klass(recv, obj); |
| 1783 | 1784 Label update_done; |
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1785 type_profile_helper(mdo, md, data, recv, success); |
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1786 __ jmp(*success); |
| 1783 | 1787 |
| 1788 __ bind(profile_cast_failure); | |
| 1789 __ movoop(mdo, md->constant_encoding()); | |
| 1790 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); | |
| 1791 __ subptr(counter_addr, DataLayout::counter_increment); | |
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1792 __ jmp(*failure); |
| 1783 | 1793 } |
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1794 __ jmp(*success); |
| 1783 | 1795 } |
| 0 | 1796 |
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1797 |
| 0 | 1798 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
| 1799 LIR_Code code = op->code(); | |
| 1800 if (code == lir_store_check) { | |
| 1801 Register value = op->object()->as_register(); | |
| 1802 Register array = op->array()->as_register(); | |
| 1803 Register k_RInfo = op->tmp1()->as_register(); | |
| 1804 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1805 Register Rtmp1 = op->tmp3()->as_register(); | |
| 1806 | |
| 1807 CodeStub* stub = op->stub(); | |
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1808 |
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1809 // check if it needs to be profiled |
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1810 ciMethodData* md; |
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1811 ciProfileData* data; |
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1812 |
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1813 if (op->should_profile()) { |
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1814 ciMethod* method = op->profiled_method(); |
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1815 assert(method != NULL, "Should have method"); |
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1816 int bci = op->profiled_bci(); |
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1817 md = method->method_data_or_null(); |
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1818 assert(md != NULL, "Sanity"); |
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1819 data = md->bci_to_data(bci); |
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1820 assert(data != NULL, "need data for type check"); |
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1821 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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1822 } |
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1823 Label profile_cast_success, profile_cast_failure, done; |
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1824 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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1825 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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1826 |
| 304 | 1827 __ cmpptr(value, (int32_t)NULL_WORD); |
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1828 if (op->should_profile()) { |
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1829 Label not_null; |
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1830 __ jccb(Assembler::notEqual, not_null); |
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1831 // Object is null; update MDO and exit |
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1832 Register mdo = klass_RInfo; |
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1833 __ movoop(mdo, md->constant_encoding()); |
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1834 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
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1835 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
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1836 __ orl(data_addr, header_bits); |
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1837 __ jmp(done); |
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1838 __ bind(not_null); |
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1839 } else { |
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1840 __ jcc(Assembler::equal, done); |
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1841 } |
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1842 |
| 0 | 1843 add_debug_info_for_null_check_here(op->info_for_exception()); |
| 2002 | 1844 __ load_klass(k_RInfo, array); |
| 1845 __ load_klass(klass_RInfo, value); | |
| 1846 | |
| 1847 // get instance klass (it's already uncompressed) | |
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1848 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset())); |
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1849 // perform the fast part of the checking logic |
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1850 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
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1851 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 304 | 1852 __ push(klass_RInfo); |
| 1853 __ push(k_RInfo); | |
| 0 | 1854 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
| 304 | 1855 __ pop(klass_RInfo); |
| 1856 __ pop(k_RInfo); | |
| 1857 // result is a boolean | |
| 0 | 1858 __ cmpl(k_RInfo, 0); |
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1859 __ jcc(Assembler::equal, *failure_target); |
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1860 // fall through to the success case |
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1861 |
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1862 if (op->should_profile()) { |
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1863 Register mdo = klass_RInfo, recv = k_RInfo; |
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1864 __ bind(profile_cast_success); |
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1865 __ movoop(mdo, md->constant_encoding()); |
| 2002 | 1866 __ load_klass(recv, value); |
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1867 Label update_done; |
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1868 type_profile_helper(mdo, md, data, recv, &done); |
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1869 __ jmpb(done); |
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1870 |
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1871 __ bind(profile_cast_failure); |
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1872 __ movoop(mdo, md->constant_encoding()); |
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1873 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
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1874 __ subptr(counter_addr, DataLayout::counter_increment); |
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1875 __ jmp(*stub->entry()); |
| 0 | 1876 } |
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1877 |
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1878 __ bind(done); |
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1879 } else |
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1880 if (code == lir_checkcast) { |
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1881 Register obj = op->object()->as_register(); |
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1882 Register dst = op->result_opr()->as_register(); |
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1883 Label success; |
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1884 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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1885 __ bind(success); |
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1886 if (dst != obj) { |
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1887 __ mov(dst, obj); |
| 0 | 1888 } |
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1889 } else |
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1890 if (code == lir_instanceof) { |
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1891 Register obj = op->object()->as_register(); |
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1892 Register dst = op->result_opr()->as_register(); |
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1893 Label success, failure, done; |
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1894 emit_typecheck_helper(op, &success, &failure, &failure); |
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1895 __ bind(failure); |
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1896 __ xorptr(dst, dst); |
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1897 __ jmpb(done); |
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1898 __ bind(success); |
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1899 __ movptr(dst, 1); |
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1900 __ bind(done); |
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1901 } else { |
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1902 ShouldNotReachHere(); |
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1903 } |
| 0 | 1904 |
| 1905 } | |
| 1906 | |
| 1907 | |
| 1908 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 304 | 1909 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
| 0 | 1910 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
| 1911 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
| 1912 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
| 1913 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
| 1914 Register addr = op->addr()->as_register(); | |
| 1915 if (os::is_MP()) { | |
| 1916 __ lock(); | |
| 1917 } | |
| 304 | 1918 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
| 1919 | |
| 1920 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
| 1921 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
| 1922 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 0 | 1923 Register newval = op->new_value()->as_register(); |
| 1924 Register cmpval = op->cmp_value()->as_register(); | |
| 1925 assert(cmpval == rax, "wrong register"); | |
| 1926 assert(newval != NULL, "new val must be register"); | |
| 1927 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1928 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1929 assert(newval != addr, "new value and addr must be in different registers"); | |
| 2002 | 1930 |
| 304 | 1931 if ( op->code() == lir_cas_obj) { |
| 2002 | 1932 #ifdef _LP64 |
| 1933 if (UseCompressedOops) { | |
| 1934 __ encode_heap_oop(cmpval); | |
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1935 __ mov(rscratch1, newval); |
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1936 __ encode_heap_oop(rscratch1); |
| 2002 | 1937 if (os::is_MP()) { |
| 1938 __ lock(); | |
| 1939 } | |
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1940 // cmpval (rax) is implicitly used by this instruction |
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1941 __ cmpxchgl(rscratch1, Address(addr, 0)); |
| 2002 | 1942 } else |
| 1943 #endif | |
| 1944 { | |
| 1945 if (os::is_MP()) { | |
| 1946 __ lock(); | |
| 1947 } | |
| 1948 __ cmpxchgptr(newval, Address(addr, 0)); | |
| 1949 } | |
| 1950 } else { | |
| 1951 assert(op->code() == lir_cas_int, "lir_cas_int expected"); | |
| 1952 if (os::is_MP()) { | |
| 1953 __ lock(); | |
| 1954 } | |
| 304 | 1955 __ cmpxchgl(newval, Address(addr, 0)); |
| 1956 } | |
| 1957 #ifdef _LP64 | |
| 1958 } else if (op->code() == lir_cas_long) { | |
| 1959 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 1960 Register newval = op->new_value()->as_register_lo(); | |
| 1961 Register cmpval = op->cmp_value()->as_register_lo(); | |
| 1962 assert(cmpval == rax, "wrong register"); | |
| 1963 assert(newval != NULL, "new val must be register"); | |
| 1964 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1965 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1966 assert(newval != addr, "new value and addr must be in different registers"); | |
| 1967 if (os::is_MP()) { | |
| 1968 __ lock(); | |
| 1969 } | |
| 1970 __ cmpxchgq(newval, Address(addr, 0)); | |
| 1971 #endif // _LP64 | |
| 0 | 1972 } else { |
| 1973 Unimplemented(); | |
| 1974 } | |
| 1975 } | |
| 1976 | |
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1977 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
| 0 | 1978 Assembler::Condition acond, ncond; |
| 1979 switch (condition) { | |
| 1980 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
| 1981 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
| 1982 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
| 1983 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
| 1984 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
| 1985 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
| 1986 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
| 1987 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
| 1988 default: ShouldNotReachHere(); | |
| 1989 } | |
| 1990 | |
| 1991 if (opr1->is_cpu_register()) { | |
| 1992 reg2reg(opr1, result); | |
| 1993 } else if (opr1->is_stack()) { | |
| 1994 stack2reg(opr1, result, result->type()); | |
| 1995 } else if (opr1->is_constant()) { | |
| 1996 const2reg(opr1, result, lir_patch_none, NULL); | |
| 1997 } else { | |
| 1998 ShouldNotReachHere(); | |
| 1999 } | |
| 2000 | |
| 2001 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
| 2002 // optimized version that does not require a branch | |
| 2003 if (opr2->is_single_cpu()) { | |
| 2004 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
| 304 | 2005 __ cmov(ncond, result->as_register(), opr2->as_register()); |
| 0 | 2006 } else if (opr2->is_double_cpu()) { |
| 2007 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 2008 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 304 | 2009 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
| 2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
| 0 | 2011 } else if (opr2->is_single_stack()) { |
| 2012 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2013 } else if (opr2->is_double_stack()) { | |
| 304 | 2014 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
| 2015 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
| 0 | 2016 } else { |
| 2017 ShouldNotReachHere(); | |
| 2018 } | |
| 2019 | |
| 2020 } else { | |
| 2021 Label skip; | |
| 2022 __ jcc (acond, skip); | |
| 2023 if (opr2->is_cpu_register()) { | |
| 2024 reg2reg(opr2, result); | |
| 2025 } else if (opr2->is_stack()) { | |
| 2026 stack2reg(opr2, result, result->type()); | |
| 2027 } else if (opr2->is_constant()) { | |
| 2028 const2reg(opr2, result, lir_patch_none, NULL); | |
| 2029 } else { | |
| 2030 ShouldNotReachHere(); | |
| 2031 } | |
| 2032 __ bind(skip); | |
| 2033 } | |
| 2034 } | |
| 2035 | |
| 2036 | |
| 2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 2038 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
| 2039 | |
| 2040 if (left->is_single_cpu()) { | |
| 2041 assert(left == dest, "left and dest must be equal"); | |
| 2042 Register lreg = left->as_register(); | |
| 2043 | |
| 2044 if (right->is_single_cpu()) { | |
| 2045 // cpu register - cpu register | |
| 2046 Register rreg = right->as_register(); | |
| 2047 switch (code) { | |
| 2048 case lir_add: __ addl (lreg, rreg); break; | |
| 2049 case lir_sub: __ subl (lreg, rreg); break; | |
| 2050 case lir_mul: __ imull(lreg, rreg); break; | |
| 2051 default: ShouldNotReachHere(); | |
| 2052 } | |
| 2053 | |
| 2054 } else if (right->is_stack()) { | |
| 2055 // cpu register - stack | |
| 2056 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2057 switch (code) { | |
| 2058 case lir_add: __ addl(lreg, raddr); break; | |
| 2059 case lir_sub: __ subl(lreg, raddr); break; | |
| 2060 default: ShouldNotReachHere(); | |
| 2061 } | |
| 2062 | |
| 2063 } else if (right->is_constant()) { | |
| 2064 // cpu register - constant | |
| 2065 jint c = right->as_constant_ptr()->as_jint(); | |
| 2066 switch (code) { | |
| 2067 case lir_add: { | |
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2068 __ incrementl(lreg, c); |
| 0 | 2069 break; |
| 2070 } | |
| 2071 case lir_sub: { | |
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2072 __ decrementl(lreg, c); |
| 0 | 2073 break; |
| 2074 } | |
| 2075 default: ShouldNotReachHere(); | |
| 2076 } | |
| 2077 | |
| 2078 } else { | |
| 2079 ShouldNotReachHere(); | |
| 2080 } | |
| 2081 | |
| 2082 } else if (left->is_double_cpu()) { | |
| 2083 assert(left == dest, "left and dest must be equal"); | |
| 2084 Register lreg_lo = left->as_register_lo(); | |
| 2085 Register lreg_hi = left->as_register_hi(); | |
| 2086 | |
| 2087 if (right->is_double_cpu()) { | |
| 2088 // cpu register - cpu register | |
| 2089 Register rreg_lo = right->as_register_lo(); | |
| 2090 Register rreg_hi = right->as_register_hi(); | |
| 304 | 2091 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
| 2092 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
| 0 | 2093 switch (code) { |
| 2094 case lir_add: | |
| 304 | 2095 __ addptr(lreg_lo, rreg_lo); |
| 2096 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
| 0 | 2097 break; |
| 2098 case lir_sub: | |
| 304 | 2099 __ subptr(lreg_lo, rreg_lo); |
| 2100 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
| 0 | 2101 break; |
| 2102 case lir_mul: | |
| 304 | 2103 #ifdef _LP64 |
| 2104 __ imulq(lreg_lo, rreg_lo); | |
| 2105 #else | |
| 0 | 2106 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
| 2107 __ imull(lreg_hi, rreg_lo); | |
| 2108 __ imull(rreg_hi, lreg_lo); | |
| 2109 __ addl (rreg_hi, lreg_hi); | |
| 2110 __ mull (rreg_lo); | |
| 2111 __ addl (lreg_hi, rreg_hi); | |
| 304 | 2112 #endif // _LP64 |
| 0 | 2113 break; |
| 2114 default: | |
| 2115 ShouldNotReachHere(); | |
| 2116 } | |
| 2117 | |
| 2118 } else if (right->is_constant()) { | |
| 2119 // cpu register - constant | |
| 304 | 2120 #ifdef _LP64 |
| 2121 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
| 2122 __ movptr(r10, (intptr_t) c); | |
| 2123 switch (code) { | |
| 2124 case lir_add: | |
| 2125 __ addptr(lreg_lo, r10); | |
| 2126 break; | |
| 2127 case lir_sub: | |
| 2128 __ subptr(lreg_lo, r10); | |
| 2129 break; | |
| 2130 default: | |
| 2131 ShouldNotReachHere(); | |
| 2132 } | |
| 2133 #else | |
| 0 | 2134 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2135 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2136 switch (code) { | |
| 2137 case lir_add: | |
| 304 | 2138 __ addptr(lreg_lo, c_lo); |
| 0 | 2139 __ adcl(lreg_hi, c_hi); |
| 2140 break; | |
| 2141 case lir_sub: | |
| 304 | 2142 __ subptr(lreg_lo, c_lo); |
| 0 | 2143 __ sbbl(lreg_hi, c_hi); |
| 2144 break; | |
| 2145 default: | |
| 2146 ShouldNotReachHere(); | |
| 2147 } | |
| 304 | 2148 #endif // _LP64 |
| 0 | 2149 |
| 2150 } else { | |
| 2151 ShouldNotReachHere(); | |
| 2152 } | |
| 2153 | |
| 2154 } else if (left->is_single_xmm()) { | |
| 2155 assert(left == dest, "left and dest must be equal"); | |
| 2156 XMMRegister lreg = left->as_xmm_float_reg(); | |
| 2157 | |
| 2158 if (right->is_single_xmm()) { | |
| 2159 XMMRegister rreg = right->as_xmm_float_reg(); | |
| 2160 switch (code) { | |
| 2161 case lir_add: __ addss(lreg, rreg); break; | |
| 2162 case lir_sub: __ subss(lreg, rreg); break; | |
| 2163 case lir_mul_strictfp: // fall through | |
| 2164 case lir_mul: __ mulss(lreg, rreg); break; | |
| 2165 case lir_div_strictfp: // fall through | |
| 2166 case lir_div: __ divss(lreg, rreg); break; | |
| 2167 default: ShouldNotReachHere(); | |
| 2168 } | |
| 2169 } else { | |
| 2170 Address raddr; | |
| 2171 if (right->is_single_stack()) { | |
| 2172 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2173 } else if (right->is_constant()) { | |
| 2174 // hack for now | |
| 2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
| 2176 } else { | |
| 2177 ShouldNotReachHere(); | |
| 2178 } | |
| 2179 switch (code) { | |
| 2180 case lir_add: __ addss(lreg, raddr); break; | |
| 2181 case lir_sub: __ subss(lreg, raddr); break; | |
| 2182 case lir_mul_strictfp: // fall through | |
| 2183 case lir_mul: __ mulss(lreg, raddr); break; | |
| 2184 case lir_div_strictfp: // fall through | |
| 2185 case lir_div: __ divss(lreg, raddr); break; | |
| 2186 default: ShouldNotReachHere(); | |
| 2187 } | |
| 2188 } | |
| 2189 | |
| 2190 } else if (left->is_double_xmm()) { | |
| 2191 assert(left == dest, "left and dest must be equal"); | |
| 2192 | |
| 2193 XMMRegister lreg = left->as_xmm_double_reg(); | |
| 2194 if (right->is_double_xmm()) { | |
| 2195 XMMRegister rreg = right->as_xmm_double_reg(); | |
| 2196 switch (code) { | |
| 2197 case lir_add: __ addsd(lreg, rreg); break; | |
| 2198 case lir_sub: __ subsd(lreg, rreg); break; | |
| 2199 case lir_mul_strictfp: // fall through | |
| 2200 case lir_mul: __ mulsd(lreg, rreg); break; | |
| 2201 case lir_div_strictfp: // fall through | |
| 2202 case lir_div: __ divsd(lreg, rreg); break; | |
| 2203 default: ShouldNotReachHere(); | |
| 2204 } | |
| 2205 } else { | |
| 2206 Address raddr; | |
| 2207 if (right->is_double_stack()) { | |
| 2208 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2209 } else if (right->is_constant()) { | |
| 2210 // hack for now | |
| 2211 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2212 } else { | |
| 2213 ShouldNotReachHere(); | |
| 2214 } | |
| 2215 switch (code) { | |
| 2216 case lir_add: __ addsd(lreg, raddr); break; | |
| 2217 case lir_sub: __ subsd(lreg, raddr); break; | |
| 2218 case lir_mul_strictfp: // fall through | |
| 2219 case lir_mul: __ mulsd(lreg, raddr); break; | |
| 2220 case lir_div_strictfp: // fall through | |
| 2221 case lir_div: __ divsd(lreg, raddr); break; | |
| 2222 default: ShouldNotReachHere(); | |
| 2223 } | |
| 2224 } | |
| 2225 | |
| 2226 } else if (left->is_single_fpu()) { | |
| 2227 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
| 2228 | |
| 2229 if (right->is_single_fpu()) { | |
| 2230 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
| 2231 | |
| 2232 } else { | |
| 2233 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
| 2234 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
| 2235 | |
| 2236 Address raddr; | |
| 2237 if (right->is_single_stack()) { | |
| 2238 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2239 } else if (right->is_constant()) { | |
| 2240 address const_addr = float_constant(right->as_jfloat()); | |
| 2241 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
| 2242 // hack for now | |
| 2243 raddr = __ as_Address(InternalAddress(const_addr)); | |
| 2244 } else { | |
| 2245 ShouldNotReachHere(); | |
| 2246 } | |
| 2247 | |
| 2248 switch (code) { | |
| 2249 case lir_add: __ fadd_s(raddr); break; | |
| 2250 case lir_sub: __ fsub_s(raddr); break; | |
| 2251 case lir_mul_strictfp: // fall through | |
| 2252 case lir_mul: __ fmul_s(raddr); break; | |
| 2253 case lir_div_strictfp: // fall through | |
| 2254 case lir_div: __ fdiv_s(raddr); break; | |
| 2255 default: ShouldNotReachHere(); | |
| 2256 } | |
| 2257 } | |
| 2258 | |
| 2259 } else if (left->is_double_fpu()) { | |
| 2260 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
| 2261 | |
| 2262 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2263 // Double values require special handling for strictfp mul/div on x86 | |
| 2264 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
| 2265 __ fmulp(left->fpu_regnrLo() + 1); | |
| 2266 } | |
| 2267 | |
| 2268 if (right->is_double_fpu()) { | |
| 2269 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
| 2270 | |
| 2271 } else { | |
| 2272 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
| 2273 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
| 2274 | |
| 2275 Address raddr; | |
| 2276 if (right->is_double_stack()) { | |
| 2277 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2278 } else if (right->is_constant()) { | |
| 2279 // hack for now | |
| 2280 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2281 } else { | |
| 2282 ShouldNotReachHere(); | |
| 2283 } | |
| 2284 | |
| 2285 switch (code) { | |
| 2286 case lir_add: __ fadd_d(raddr); break; | |
| 2287 case lir_sub: __ fsub_d(raddr); break; | |
| 2288 case lir_mul_strictfp: // fall through | |
| 2289 case lir_mul: __ fmul_d(raddr); break; | |
| 2290 case lir_div_strictfp: // fall through | |
| 2291 case lir_div: __ fdiv_d(raddr); break; | |
| 2292 default: ShouldNotReachHere(); | |
| 2293 } | |
| 2294 } | |
| 2295 | |
| 2296 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2297 // Double values require special handling for strictfp mul/div on x86 | |
| 2298 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
| 2299 __ fmulp(dest->fpu_regnrLo() + 1); | |
| 2300 } | |
| 2301 | |
| 2302 } else if (left->is_single_stack() || left->is_address()) { | |
| 2303 assert(left == dest, "left and dest must be equal"); | |
| 2304 | |
| 2305 Address laddr; | |
| 2306 if (left->is_single_stack()) { | |
| 2307 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
| 2308 } else if (left->is_address()) { | |
| 2309 laddr = as_Address(left->as_address_ptr()); | |
| 2310 } else { | |
| 2311 ShouldNotReachHere(); | |
| 2312 } | |
| 2313 | |
| 2314 if (right->is_single_cpu()) { | |
| 2315 Register rreg = right->as_register(); | |
| 2316 switch (code) { | |
| 2317 case lir_add: __ addl(laddr, rreg); break; | |
| 2318 case lir_sub: __ subl(laddr, rreg); break; | |
| 2319 default: ShouldNotReachHere(); | |
| 2320 } | |
| 2321 } else if (right->is_constant()) { | |
| 2322 jint c = right->as_constant_ptr()->as_jint(); | |
| 2323 switch (code) { | |
| 2324 case lir_add: { | |
| 304 | 2325 __ incrementl(laddr, c); |
| 0 | 2326 break; |
| 2327 } | |
| 2328 case lir_sub: { | |
| 304 | 2329 __ decrementl(laddr, c); |
| 0 | 2330 break; |
| 2331 } | |
| 2332 default: ShouldNotReachHere(); | |
| 2333 } | |
| 2334 } else { | |
| 2335 ShouldNotReachHere(); | |
| 2336 } | |
| 2337 | |
| 2338 } else { | |
| 2339 ShouldNotReachHere(); | |
| 2340 } | |
| 2341 } | |
| 2342 | |
| 2343 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
| 2344 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
| 2345 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
| 2346 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
| 2347 | |
| 2348 bool left_is_tos = (left_index == 0); | |
| 2349 bool dest_is_tos = (dest_index == 0); | |
| 2350 int non_tos_index = (left_is_tos ? right_index : left_index); | |
| 2351 | |
| 2352 switch (code) { | |
| 2353 case lir_add: | |
| 2354 if (pop_fpu_stack) __ faddp(non_tos_index); | |
| 2355 else if (dest_is_tos) __ fadd (non_tos_index); | |
| 2356 else __ fadda(non_tos_index); | |
| 2357 break; | |
| 2358 | |
| 2359 case lir_sub: | |
| 2360 if (left_is_tos) { | |
| 2361 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
| 2362 else if (dest_is_tos) __ fsub (non_tos_index); | |
| 2363 else __ fsubra(non_tos_index); | |
| 2364 } else { | |
| 2365 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
| 2366 else if (dest_is_tos) __ fsubr (non_tos_index); | |
| 2367 else __ fsuba (non_tos_index); | |
| 2368 } | |
| 2369 break; | |
| 2370 | |
| 2371 case lir_mul_strictfp: // fall through | |
| 2372 case lir_mul: | |
| 2373 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
| 2374 else if (dest_is_tos) __ fmul (non_tos_index); | |
| 2375 else __ fmula(non_tos_index); | |
| 2376 break; | |
| 2377 | |
| 2378 case lir_div_strictfp: // fall through | |
| 2379 case lir_div: | |
| 2380 if (left_is_tos) { | |
| 2381 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
| 2382 else if (dest_is_tos) __ fdiv (non_tos_index); | |
| 2383 else __ fdivra(non_tos_index); | |
| 2384 } else { | |
| 2385 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
| 2386 else if (dest_is_tos) __ fdivr (non_tos_index); | |
| 2387 else __ fdiva (non_tos_index); | |
| 2388 } | |
| 2389 break; | |
| 2390 | |
| 2391 case lir_rem: | |
| 2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
| 2393 __ fremr(noreg); | |
| 2394 break; | |
| 2395 | |
| 2396 default: | |
| 2397 ShouldNotReachHere(); | |
| 2398 } | |
| 2399 } | |
| 2400 | |
| 2401 | |
| 2402 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
| 2403 if (value->is_double_xmm()) { | |
| 2404 switch(code) { | |
| 2405 case lir_abs : | |
| 2406 { | |
| 2407 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
| 2408 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
| 2409 } | |
| 2410 __ andpd(dest->as_xmm_double_reg(), | |
| 2411 ExternalAddress((address)double_signmask_pool)); | |
| 2412 } | |
| 2413 break; | |
| 2414 | |
| 2415 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
| 2416 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
| 2417 default : ShouldNotReachHere(); | |
| 2418 } | |
| 2419 | |
| 2420 } else if (value->is_double_fpu()) { | |
| 2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
| 2422 switch(code) { | |
| 2423 case lir_log : __ flog() ; break; | |
| 2424 case lir_log10 : __ flog10() ; break; | |
| 2425 case lir_abs : __ fabs() ; break; | |
| 2426 case lir_sqrt : __ fsqrt(); break; | |
| 2427 case lir_sin : | |
| 2428 // Should consider not saving rbx, if not necessary | |
| 2429 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
| 2430 break; | |
| 2431 case lir_cos : | |
| 2432 // Should consider not saving rbx, if not necessary | |
| 2433 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
| 2434 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
| 2435 break; | |
| 2436 case lir_tan : | |
| 2437 // Should consider not saving rbx, if not necessary | |
| 2438 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
| 2439 break; | |
| 2440 default : ShouldNotReachHere(); | |
| 2441 } | |
| 2442 } else { | |
| 2443 Unimplemented(); | |
| 2444 } | |
| 2445 } | |
| 2446 | |
| 2447 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
| 2448 // assert(left->destroys_register(), "check"); | |
| 2449 if (left->is_single_cpu()) { | |
| 2450 Register reg = left->as_register(); | |
| 2451 if (right->is_constant()) { | |
| 2452 int val = right->as_constant_ptr()->as_jint(); | |
| 2453 switch (code) { | |
| 2454 case lir_logic_and: __ andl (reg, val); break; | |
| 2455 case lir_logic_or: __ orl (reg, val); break; | |
| 2456 case lir_logic_xor: __ xorl (reg, val); break; | |
| 2457 default: ShouldNotReachHere(); | |
| 2458 } | |
| 2459 } else if (right->is_stack()) { | |
| 2460 // added support for stack operands | |
| 2461 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2462 switch (code) { | |
| 2463 case lir_logic_and: __ andl (reg, raddr); break; | |
| 2464 case lir_logic_or: __ orl (reg, raddr); break; | |
| 2465 case lir_logic_xor: __ xorl (reg, raddr); break; | |
| 2466 default: ShouldNotReachHere(); | |
| 2467 } | |
| 2468 } else { | |
| 2469 Register rright = right->as_register(); | |
| 2470 switch (code) { | |
| 304 | 2471 case lir_logic_and: __ andptr (reg, rright); break; |
| 2472 case lir_logic_or : __ orptr (reg, rright); break; | |
| 2473 case lir_logic_xor: __ xorptr (reg, rright); break; | |
| 0 | 2474 default: ShouldNotReachHere(); |
| 2475 } | |
| 2476 } | |
| 2477 move_regs(reg, dst->as_register()); | |
| 2478 } else { | |
| 2479 Register l_lo = left->as_register_lo(); | |
| 2480 Register l_hi = left->as_register_hi(); | |
| 2481 if (right->is_constant()) { | |
| 304 | 2482 #ifdef _LP64 |
| 2483 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
| 2484 switch (code) { | |
| 2485 case lir_logic_and: | |
| 2486 __ andq(l_lo, rscratch1); | |
| 2487 break; | |
| 2488 case lir_logic_or: | |
| 2489 __ orq(l_lo, rscratch1); | |
| 2490 break; | |
| 2491 case lir_logic_xor: | |
| 2492 __ xorq(l_lo, rscratch1); | |
| 2493 break; | |
| 2494 default: ShouldNotReachHere(); | |
| 2495 } | |
| 2496 #else | |
| 0 | 2497 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2498 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2499 switch (code) { | |
| 2500 case lir_logic_and: | |
| 2501 __ andl(l_lo, r_lo); | |
| 2502 __ andl(l_hi, r_hi); | |
| 2503 break; | |
| 2504 case lir_logic_or: | |
| 2505 __ orl(l_lo, r_lo); | |
| 2506 __ orl(l_hi, r_hi); | |
| 2507 break; | |
| 2508 case lir_logic_xor: | |
| 2509 __ xorl(l_lo, r_lo); | |
| 2510 __ xorl(l_hi, r_hi); | |
| 2511 break; | |
| 2512 default: ShouldNotReachHere(); | |
| 2513 } | |
| 304 | 2514 #endif // _LP64 |
| 0 | 2515 } else { |
| 1572 | 2516 #ifdef _LP64 |
| 2517 Register r_lo; | |
| 2518 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
| 2519 r_lo = right->as_register(); | |
| 2520 } else { | |
| 2521 r_lo = right->as_register_lo(); | |
| 2522 } | |
| 2523 #else | |
| 0 | 2524 Register r_lo = right->as_register_lo(); |
| 2525 Register r_hi = right->as_register_hi(); | |
| 2526 assert(l_lo != r_hi, "overwriting registers"); | |
| 1572 | 2527 #endif |
| 0 | 2528 switch (code) { |
| 2529 case lir_logic_and: | |
| 304 | 2530 __ andptr(l_lo, r_lo); |
| 2531 NOT_LP64(__ andptr(l_hi, r_hi);) | |
| 0 | 2532 break; |
| 2533 case lir_logic_or: | |
| 304 | 2534 __ orptr(l_lo, r_lo); |
| 2535 NOT_LP64(__ orptr(l_hi, r_hi);) | |
| 0 | 2536 break; |
| 2537 case lir_logic_xor: | |
| 304 | 2538 __ xorptr(l_lo, r_lo); |
| 2539 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
| 0 | 2540 break; |
| 2541 default: ShouldNotReachHere(); | |
| 2542 } | |
| 2543 } | |
| 2544 | |
| 2545 Register dst_lo = dst->as_register_lo(); | |
| 2546 Register dst_hi = dst->as_register_hi(); | |
| 2547 | |
| 304 | 2548 #ifdef _LP64 |
| 2549 move_regs(l_lo, dst_lo); | |
| 2550 #else | |
| 0 | 2551 if (dst_lo == l_hi) { |
| 2552 assert(dst_hi != l_lo, "overwriting registers"); | |
| 2553 move_regs(l_hi, dst_hi); | |
| 2554 move_regs(l_lo, dst_lo); | |
| 2555 } else { | |
| 2556 assert(dst_lo != l_hi, "overwriting registers"); | |
| 2557 move_regs(l_lo, dst_lo); | |
| 2558 move_regs(l_hi, dst_hi); | |
| 2559 } | |
| 304 | 2560 #endif // _LP64 |
| 0 | 2561 } |
| 2562 } | |
| 2563 | |
| 2564 | |
| 2565 // we assume that rax, and rdx can be overwritten | |
| 2566 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
| 2567 | |
| 2568 assert(left->is_single_cpu(), "left must be register"); | |
| 2569 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
| 2570 assert(result->is_single_cpu(), "result must be register"); | |
| 2571 | |
| 2572 // assert(left->destroys_register(), "check"); | |
| 2573 // assert(right->destroys_register(), "check"); | |
| 2574 | |
| 2575 Register lreg = left->as_register(); | |
| 2576 Register dreg = result->as_register(); | |
| 2577 | |
| 2578 if (right->is_constant()) { | |
| 2579 int divisor = right->as_constant_ptr()->as_jint(); | |
| 2580 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
| 2581 if (code == lir_idiv) { | |
| 2582 assert(lreg == rax, "must be rax,"); | |
| 2583 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2584 __ cdql(); // sign extend into rdx:rax | |
| 2585 if (divisor == 2) { | |
| 2586 __ subl(lreg, rdx); | |
| 2587 } else { | |
| 2588 __ andl(rdx, divisor - 1); | |
| 2589 __ addl(lreg, rdx); | |
| 2590 } | |
| 2591 __ sarl(lreg, log2_intptr(divisor)); | |
| 2592 move_regs(lreg, dreg); | |
| 2593 } else if (code == lir_irem) { | |
| 2594 Label done; | |
| 304 | 2595 __ mov(dreg, lreg); |
| 0 | 2596 __ andl(dreg, 0x80000000 | (divisor - 1)); |
| 2597 __ jcc(Assembler::positive, done); | |
| 2598 __ decrement(dreg); | |
| 2599 __ orl(dreg, ~(divisor - 1)); | |
| 2600 __ increment(dreg); | |
| 2601 __ bind(done); | |
| 2602 } else { | |
| 2603 ShouldNotReachHere(); | |
| 2604 } | |
| 2605 } else { | |
| 2606 Register rreg = right->as_register(); | |
| 2607 assert(lreg == rax, "left register must be rax,"); | |
| 2608 assert(rreg != rdx, "right register must not be rdx"); | |
| 2609 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2610 | |
| 2611 move_regs(lreg, rax); | |
| 2612 | |
| 2613 int idivl_offset = __ corrected_idivl(rreg); | |
| 2614 add_debug_info_for_div0(idivl_offset, info); | |
| 2615 if (code == lir_irem) { | |
| 2616 move_regs(rdx, dreg); // result is in rdx | |
| 2617 } else { | |
| 2618 move_regs(rax, dreg); | |
| 2619 } | |
| 2620 } | |
| 2621 } | |
| 2622 | |
| 2623 | |
| 2624 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 2625 if (opr1->is_single_cpu()) { | |
| 2626 Register reg1 = opr1->as_register(); | |
| 2627 if (opr2->is_single_cpu()) { | |
| 2628 // cpu register - cpu register | |
| 304 | 2629 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2630 __ cmpptr(reg1, opr2->as_register()); | |
| 2631 } else { | |
| 2632 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
| 2633 __ cmpl(reg1, opr2->as_register()); | |
| 2634 } | |
| 0 | 2635 } else if (opr2->is_stack()) { |
| 2636 // cpu register - stack | |
| 304 | 2637 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2638 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2639 } else { | |
| 2640 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2641 } | |
| 0 | 2642 } else if (opr2->is_constant()) { |
| 2643 // cpu register - constant | |
| 2644 LIR_Const* c = opr2->as_constant_ptr(); | |
| 2645 if (c->type() == T_INT) { | |
| 2646 __ cmpl(reg1, c->as_jint()); | |
| 304 | 2647 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2648 // In 64bit oops are single register | |
| 0 | 2649 jobject o = c->as_jobject(); |
| 2650 if (o == NULL) { | |
| 304 | 2651 __ cmpptr(reg1, (int32_t)NULL_WORD); |
| 0 | 2652 } else { |
| 304 | 2653 #ifdef _LP64 |
| 2654 __ movoop(rscratch1, o); | |
| 2655 __ cmpptr(reg1, rscratch1); | |
| 2656 #else | |
| 0 | 2657 __ cmpoop(reg1, c->as_jobject()); |
| 304 | 2658 #endif // _LP64 |
| 0 | 2659 } |
| 2660 } else { | |
| 2661 ShouldNotReachHere(); | |
| 2662 } | |
| 2663 // cpu register - address | |
| 2664 } else if (opr2->is_address()) { | |
| 2665 if (op->info() != NULL) { | |
| 2666 add_debug_info_for_null_check_here(op->info()); | |
| 2667 } | |
| 2668 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
| 2669 } else { | |
| 2670 ShouldNotReachHere(); | |
| 2671 } | |
| 2672 | |
| 2673 } else if(opr1->is_double_cpu()) { | |
| 2674 Register xlo = opr1->as_register_lo(); | |
| 2675 Register xhi = opr1->as_register_hi(); | |
| 2676 if (opr2->is_double_cpu()) { | |
| 304 | 2677 #ifdef _LP64 |
| 2678 __ cmpptr(xlo, opr2->as_register_lo()); | |
| 2679 #else | |
| 0 | 2680 // cpu register - cpu register |
| 2681 Register ylo = opr2->as_register_lo(); | |
| 2682 Register yhi = opr2->as_register_hi(); | |
| 2683 __ subl(xlo, ylo); | |
| 2684 __ sbbl(xhi, yhi); | |
| 2685 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 2686 __ orl(xhi, xlo); | |
| 2687 } | |
| 304 | 2688 #endif // _LP64 |
| 0 | 2689 } else if (opr2->is_constant()) { |
| 2690 // cpu register - constant 0 | |
| 2691 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
| 304 | 2692 #ifdef _LP64 |
| 2693 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
| 2694 #else | |
| 0 | 2695 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
| 2696 __ orl(xhi, xlo); | |
| 304 | 2697 #endif // _LP64 |
| 0 | 2698 } else { |
| 2699 ShouldNotReachHere(); | |
| 2700 } | |
| 2701 | |
| 2702 } else if (opr1->is_single_xmm()) { | |
| 2703 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
| 2704 if (opr2->is_single_xmm()) { | |
| 2705 // xmm register - xmm register | |
| 2706 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
| 2707 } else if (opr2->is_stack()) { | |
| 2708 // xmm register - stack | |
| 2709 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2710 } else if (opr2->is_constant()) { | |
| 2711 // xmm register - constant | |
| 2712 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
| 2713 } else if (opr2->is_address()) { | |
| 2714 // xmm register - address | |
| 2715 if (op->info() != NULL) { | |
| 2716 add_debug_info_for_null_check_here(op->info()); | |
| 2717 } | |
| 2718 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
| 2719 } else { | |
| 2720 ShouldNotReachHere(); | |
| 2721 } | |
| 2722 | |
| 2723 } else if (opr1->is_double_xmm()) { | |
| 2724 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
| 2725 if (opr2->is_double_xmm()) { | |
| 2726 // xmm register - xmm register | |
| 2727 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
| 2728 } else if (opr2->is_stack()) { | |
| 2729 // xmm register - stack | |
| 2730 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
| 2731 } else if (opr2->is_constant()) { | |
| 2732 // xmm register - constant | |
| 2733 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
| 2734 } else if (opr2->is_address()) { | |
| 2735 // xmm register - address | |
| 2736 if (op->info() != NULL) { | |
| 2737 add_debug_info_for_null_check_here(op->info()); | |
| 2738 } | |
| 2739 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
| 2740 } else { | |
| 2741 ShouldNotReachHere(); | |
| 2742 } | |
| 2743 | |
| 2744 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
| 2745 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
| 2746 assert(opr2->is_fpu_register(), "both must be registers"); | |
| 2747 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2748 | |
| 2749 } else if (opr1->is_address() && opr2->is_constant()) { | |
| 304 | 2750 LIR_Const* c = opr2->as_constant_ptr(); |
| 2751 #ifdef _LP64 | |
| 2752 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
| 2753 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
| 2754 __ movoop(rscratch1, c->as_jobject()); | |
| 2755 } | |
| 2756 #endif // LP64 | |
| 0 | 2757 if (op->info() != NULL) { |
| 2758 add_debug_info_for_null_check_here(op->info()); | |
| 2759 } | |
| 2760 // special case: address - constant | |
| 2761 LIR_Address* addr = opr1->as_address_ptr(); | |
| 2762 if (c->type() == T_INT) { | |
| 2763 __ cmpl(as_Address(addr), c->as_jint()); | |
| 304 | 2764 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2765 #ifdef _LP64 | |
| 2766 // %%% Make this explode if addr isn't reachable until we figure out a | |
| 2767 // better strategy by giving noreg as the temp for as_Address | |
| 2768 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
| 2769 #else | |
| 0 | 2770 __ cmpoop(as_Address(addr), c->as_jobject()); |
| 304 | 2771 #endif // _LP64 |
| 0 | 2772 } else { |
| 2773 ShouldNotReachHere(); | |
| 2774 } | |
| 2775 | |
| 2776 } else { | |
| 2777 ShouldNotReachHere(); | |
| 2778 } | |
| 2779 } | |
| 2780 | |
| 2781 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
| 2782 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 2783 if (left->is_single_xmm()) { | |
| 2784 assert(right->is_single_xmm(), "must match"); | |
| 2785 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2786 } else if (left->is_double_xmm()) { | |
| 2787 assert(right->is_double_xmm(), "must match"); | |
| 2788 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2789 | |
| 2790 } else { | |
| 2791 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
| 2792 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
| 2793 | |
| 2794 assert(left->fpu() == 0, "left must be on TOS"); | |
| 2795 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
| 2796 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2797 } | |
| 2798 } else { | |
| 2799 assert(code == lir_cmp_l2i, "check"); | |
| 304 | 2800 #ifdef _LP64 |
| 1369 | 2801 Label done; |
| 2802 Register dest = dst->as_register(); | |
| 2803 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
| 2804 __ movl(dest, -1); | |
| 2805 __ jccb(Assembler::less, done); | |
| 2806 __ set_byte_if_not_zero(dest); | |
| 2807 __ movzbl(dest, dest); | |
| 2808 __ bind(done); | |
| 304 | 2809 #else |
| 0 | 2810 __ lcmp2int(left->as_register_hi(), |
| 2811 left->as_register_lo(), | |
| 2812 right->as_register_hi(), | |
| 2813 right->as_register_lo()); | |
| 2814 move_regs(left->as_register_hi(), dst->as_register()); | |
| 304 | 2815 #endif // _LP64 |
| 0 | 2816 } |
| 2817 } | |
| 2818 | |
| 2819 | |
| 2820 void LIR_Assembler::align_call(LIR_Code code) { | |
| 2821 if (os::is_MP()) { | |
| 2822 // make sure that the displacement word of the call ends up word aligned | |
| 2823 int offset = __ offset(); | |
| 2824 switch (code) { | |
| 2825 case lir_static_call: | |
| 2826 case lir_optvirtual_call: | |
| 1295 | 2827 case lir_dynamic_call: |
| 0 | 2828 offset += NativeCall::displacement_offset; |
| 2829 break; | |
| 2830 case lir_icvirtual_call: | |
| 2831 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
| 2832 break; | |
| 2833 case lir_virtual_call: // currently, sparc-specific for niagara | |
| 2834 default: ShouldNotReachHere(); | |
| 2835 } | |
| 2836 while (offset++ % BytesPerWord != 0) { | |
| 2837 __ nop(); | |
| 2838 } | |
| 2839 } | |
| 2840 } | |
| 2841 | |
| 2842 | |
| 1295 | 2843 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
| 0 | 2844 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
| 2845 "must be aligned"); | |
| 1295 | 2846 __ call(AddressLiteral(op->addr(), rtype)); |
| 1564 | 2847 add_call_info(code_offset(), op->info()); |
| 0 | 2848 } |
| 2849 | |
| 2850 | |
| 1295 | 2851 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
| 0 | 2852 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
| 2853 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
| 2854 assert(!os::is_MP() || | |
| 2855 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
| 2856 "must be aligned"); | |
| 1295 | 2857 __ call(AddressLiteral(op->addr(), rh)); |
| 1564 | 2858 add_call_info(code_offset(), op->info()); |
| 0 | 2859 } |
| 2860 | |
| 2861 | |
| 2862 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
| 1295 | 2863 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
| 0 | 2864 ShouldNotReachHere(); |
| 2865 } | |
| 2866 | |
| 1295 | 2867 |
| 0 | 2868 void LIR_Assembler::emit_static_call_stub() { |
| 2869 address call_pc = __ pc(); | |
| 2870 address stub = __ start_a_stub(call_stub_size); | |
| 2871 if (stub == NULL) { | |
| 2872 bailout("static call stub overflow"); | |
| 2873 return; | |
| 2874 } | |
| 2875 | |
| 2876 int start = __ offset(); | |
| 2877 if (os::is_MP()) { | |
| 2878 // make sure that the displacement word of the call ends up word aligned | |
| 2879 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
| 2880 while (offset++ % BytesPerWord != 0) { | |
| 2881 __ nop(); | |
| 2882 } | |
| 2883 } | |
| 2884 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 2885 __ movoop(rbx, (jobject)NULL); | |
| 2886 // must be set to -1 at code generation time | |
| 2887 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
| 304 | 2888 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
| 2889 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 2890 |
|
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2891 assert(__ offset() - start <= call_stub_size, "stub too big"); |
| 0 | 2892 __ end_a_stub(); |
| 2893 } | |
| 2894 | |
| 2895 | |
|
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2896 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
| 0 | 2897 assert(exceptionOop->as_register() == rax, "must match"); |
|
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2898 assert(exceptionPC->as_register() == rdx, "must match"); |
| 0 | 2899 |
| 2900 // exception object is not added to oop map by LinearScan | |
| 2901 // (LinearScan assumes that no oops are in fixed registers) | |
| 2902 info->add_register_oop(exceptionOop); | |
| 2903 Runtime1::StubID unwind_id; | |
| 2904 | |
|
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2905 // get current pc information |
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2906 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
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2907 int pc_for_athrow_offset = __ offset(); |
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2908 InternalAddress pc_for_athrow(__ pc()); |
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2909 __ lea(exceptionPC->as_register(), pc_for_athrow); |
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2910 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2911 |
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2912 __ verify_not_null_oop(rax); |
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2913 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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2914 if (compilation()->has_fpu_code()) { |
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2915 unwind_id = Runtime1::handle_exception_id; |
| 0 | 2916 } else { |
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2917 unwind_id = Runtime1::handle_exception_nofpu_id; |
| 0 | 2918 } |
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2919 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
| 0 | 2920 |
| 2921 // enough room for two byte trap | |
| 2922 __ nop(); | |
| 2923 } | |
| 2924 | |
| 2925 | |
|
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2926 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2927 assert(exceptionOop->as_register() == rax, "must match"); |
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2928 |
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2929 __ jmp(_unwind_handler_entry); |
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2930 } |
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2931 |
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2932 |
| 0 | 2933 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
| 2934 | |
| 2935 // optimized version for linear scan: | |
| 2936 // * count must be already in ECX (guaranteed by LinearScan) | |
| 2937 // * left and dest must be equal | |
| 2938 // * tmp must be unused | |
| 2939 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
| 2940 assert(left == dest, "left and dest must be equal"); | |
| 2941 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
| 2942 | |
| 2943 if (left->is_single_cpu()) { | |
| 2944 Register value = left->as_register(); | |
| 2945 assert(value != SHIFT_count, "left cannot be ECX"); | |
| 2946 | |
| 2947 switch (code) { | |
| 2948 case lir_shl: __ shll(value); break; | |
| 2949 case lir_shr: __ sarl(value); break; | |
| 2950 case lir_ushr: __ shrl(value); break; | |
| 2951 default: ShouldNotReachHere(); | |
| 2952 } | |
| 2953 } else if (left->is_double_cpu()) { | |
| 2954 Register lo = left->as_register_lo(); | |
| 2955 Register hi = left->as_register_hi(); | |
| 2956 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
| 304 | 2957 #ifdef _LP64 |
| 2958 switch (code) { | |
| 2959 case lir_shl: __ shlptr(lo); break; | |
| 2960 case lir_shr: __ sarptr(lo); break; | |
| 2961 case lir_ushr: __ shrptr(lo); break; | |
| 2962 default: ShouldNotReachHere(); | |
| 2963 } | |
| 2964 #else | |
| 0 | 2965 |
| 2966 switch (code) { | |
| 2967 case lir_shl: __ lshl(hi, lo); break; | |
| 2968 case lir_shr: __ lshr(hi, lo, true); break; | |
| 2969 case lir_ushr: __ lshr(hi, lo, false); break; | |
| 2970 default: ShouldNotReachHere(); | |
| 2971 } | |
| 304 | 2972 #endif // LP64 |
| 0 | 2973 } else { |
| 2974 ShouldNotReachHere(); | |
| 2975 } | |
| 2976 } | |
| 2977 | |
| 2978 | |
| 2979 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 2980 if (dest->is_single_cpu()) { | |
| 2981 // first move left into dest so that left is not destroyed by the shift | |
| 2982 Register value = dest->as_register(); | |
| 2983 count = count & 0x1F; // Java spec | |
| 2984 | |
| 2985 move_regs(left->as_register(), value); | |
| 2986 switch (code) { | |
| 2987 case lir_shl: __ shll(value, count); break; | |
| 2988 case lir_shr: __ sarl(value, count); break; | |
| 2989 case lir_ushr: __ shrl(value, count); break; | |
| 2990 default: ShouldNotReachHere(); | |
| 2991 } | |
| 2992 } else if (dest->is_double_cpu()) { | |
| 304 | 2993 #ifndef _LP64 |
| 0 | 2994 Unimplemented(); |
| 304 | 2995 #else |
| 2996 // first move left into dest so that left is not destroyed by the shift | |
| 2997 Register value = dest->as_register_lo(); | |
| 2998 count = count & 0x1F; // Java spec | |
| 2999 | |
| 3000 move_regs(left->as_register_lo(), value); | |
| 3001 switch (code) { | |
| 3002 case lir_shl: __ shlptr(value, count); break; | |
| 3003 case lir_shr: __ sarptr(value, count); break; | |
| 3004 case lir_ushr: __ shrptr(value, count); break; | |
| 3005 default: ShouldNotReachHere(); | |
| 3006 } | |
| 3007 #endif // _LP64 | |
| 0 | 3008 } else { |
| 3009 ShouldNotReachHere(); | |
| 3010 } | |
| 3011 } | |
| 3012 | |
| 3013 | |
| 3014 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
| 3015 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3016 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3017 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3018 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
| 0 | 3019 } |
| 3020 | |
| 3021 | |
| 3022 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
| 3023 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3024 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3025 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3026 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
| 0 | 3027 } |
| 3028 | |
| 3029 | |
| 3030 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
| 3031 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3032 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3033 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 3034 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
| 3035 } | |
| 3036 | |
| 3037 | |
| 3038 // This code replaces a call to arraycopy; no exception may | |
| 3039 // be thrown in this code, they must be thrown in the System.arraycopy | |
| 3040 // activation frame; we could save some checks if this would not be the case | |
| 3041 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 3042 ciArrayKlass* default_type = op->expected_type(); | |
| 3043 Register src = op->src()->as_register(); | |
| 3044 Register dst = op->dst()->as_register(); | |
| 3045 Register src_pos = op->src_pos()->as_register(); | |
| 3046 Register dst_pos = op->dst_pos()->as_register(); | |
| 3047 Register length = op->length()->as_register(); | |
| 3048 Register tmp = op->tmp()->as_register(); | |
| 3049 | |
| 3050 CodeStub* stub = op->stub(); | |
| 3051 int flags = op->flags(); | |
| 3052 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 3053 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 3054 | |
| 2446 | 3055 // if we don't know anything, just go through the generic arraycopy |
| 0 | 3056 if (default_type == NULL) { |
| 3057 Label done; | |
| 3058 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
| 3059 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
| 3060 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
| 3061 // For the moment until C1 gets the new register allocator I just force all the | |
| 3062 // args to the right place (except the register args) and then on the back side | |
| 3063 // reload the register args properly if we go slow path. Yuck | |
| 3064 | |
| 3065 // These are proper for the calling convention | |
| 3066 store_parameter(length, 2); | |
| 3067 store_parameter(dst_pos, 1); | |
| 3068 store_parameter(dst, 0); | |
| 3069 | |
| 3070 // these are just temporary placements until we need to reload | |
| 3071 store_parameter(src_pos, 3); | |
| 3072 store_parameter(src, 4); | |
| 304 | 3073 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
| 3074 | |
| 2446 | 3075 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
| 3076 | |
| 3077 address copyfunc_addr = StubRoutines::generic_arraycopy(); | |
| 0 | 3078 |
| 3079 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
| 304 | 3080 #ifdef _LP64 |
| 3081 // The arguments are in java calling convention so we can trivially shift them to C | |
| 3082 // convention | |
| 3083 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3084 __ mov(c_rarg0, j_rarg0); | |
| 3085 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3086 __ mov(c_rarg1, j_rarg1); | |
| 3087 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
| 3088 __ mov(c_rarg2, j_rarg2); | |
| 3089 assert_different_registers(c_rarg3, j_rarg4); | |
| 3090 __ mov(c_rarg3, j_rarg3); | |
| 3091 #ifdef _WIN64 | |
| 3092 // Allocate abi space for args but be sure to keep stack aligned | |
| 3093 __ subptr(rsp, 6*wordSize); | |
| 3094 store_parameter(j_rarg4, 4); | |
| 2446 | 3095 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
| 3096 __ call(RuntimeAddress(C_entry)); | |
| 3097 } else { | |
| 3098 #ifndef PRODUCT | |
| 3099 if (PrintC1Statistics) { | |
| 3100 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
| 3101 } | |
| 3102 #endif | |
| 3103 __ call(RuntimeAddress(copyfunc_addr)); | |
| 3104 } | |
| 304 | 3105 __ addptr(rsp, 6*wordSize); |
| 3106 #else | |
| 3107 __ mov(c_rarg4, j_rarg4); | |
| 2446 | 3108 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
| 3109 __ call(RuntimeAddress(C_entry)); | |
| 3110 } else { | |
| 3111 #ifndef PRODUCT | |
| 3112 if (PrintC1Statistics) { | |
| 3113 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
| 3114 } | |
| 3115 #endif | |
| 3116 __ call(RuntimeAddress(copyfunc_addr)); | |
| 3117 } | |
| 304 | 3118 #endif // _WIN64 |
| 3119 #else | |
| 3120 __ push(length); | |
| 3121 __ push(dst_pos); | |
| 3122 __ push(dst); | |
| 3123 __ push(src_pos); | |
| 3124 __ push(src); | |
| 2446 | 3125 |
| 3126 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
| 3127 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack | |
| 3128 } else { | |
| 3129 #ifndef PRODUCT | |
| 3130 if (PrintC1Statistics) { | |
| 3131 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
| 3132 } | |
| 3133 #endif | |
| 3134 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack | |
| 3135 } | |
| 0 | 3136 |
| 304 | 3137 #endif // _LP64 |
| 3138 | |
| 0 | 3139 __ cmpl(rax, 0); |
| 3140 __ jcc(Assembler::equal, *stub->continuation()); | |
| 3141 | |
| 2446 | 3142 if (copyfunc_addr != NULL) { |
| 3143 __ mov(tmp, rax); | |
| 3144 __ xorl(tmp, -1); | |
| 3145 } | |
| 3146 | |
| 0 | 3147 // Reload values from the stack so they are where the stub |
| 3148 // expects them. | |
| 304 | 3149 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
| 3150 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
| 3151 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
| 3152 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
| 3153 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
| 2446 | 3154 |
| 3155 if (copyfunc_addr != NULL) { | |
| 3156 __ subl(length, tmp); | |
| 3157 __ addl(src_pos, tmp); | |
| 3158 __ addl(dst_pos, tmp); | |
| 3159 } | |
| 0 | 3160 __ jmp(*stub->entry()); |
| 3161 | |
| 3162 __ bind(*stub->continuation()); | |
| 3163 return; | |
| 3164 } | |
| 3165 | |
| 3166 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
| 3167 | |
|
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|
3168 int elem_size = type2aelembytes(basic_type); |
| 0 | 3169 int shift_amount; |
| 3170 Address::ScaleFactor scale; | |
| 3171 | |
| 3172 switch (elem_size) { | |
| 3173 case 1 : | |
| 3174 shift_amount = 0; | |
| 3175 scale = Address::times_1; | |
| 3176 break; | |
| 3177 case 2 : | |
| 3178 shift_amount = 1; | |
| 3179 scale = Address::times_2; | |
| 3180 break; | |
| 3181 case 4 : | |
| 3182 shift_amount = 2; | |
| 3183 scale = Address::times_4; | |
| 3184 break; | |
| 3185 case 8 : | |
| 3186 shift_amount = 3; | |
| 3187 scale = Address::times_8; | |
| 3188 break; | |
| 3189 default: | |
| 3190 ShouldNotReachHere(); | |
| 3191 } | |
| 3192 | |
| 3193 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
| 3194 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
| 3195 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
| 3196 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
| 3197 | |
| 304 | 3198 // length and pos's are all sign extended at this point on 64bit |
| 3199 | |
| 0 | 3200 // test for NULL |
| 3201 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 304 | 3202 __ testptr(src, src); |
| 0 | 3203 __ jcc(Assembler::zero, *stub->entry()); |
| 3204 } | |
| 3205 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 304 | 3206 __ testptr(dst, dst); |
| 0 | 3207 __ jcc(Assembler::zero, *stub->entry()); |
| 3208 } | |
| 3209 | |
| 3210 // check if negative | |
| 3211 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 3212 __ testl(src_pos, src_pos); | |
| 3213 __ jcc(Assembler::less, *stub->entry()); | |
| 3214 } | |
| 3215 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 3216 __ testl(dst_pos, dst_pos); | |
| 3217 __ jcc(Assembler::less, *stub->entry()); | |
| 3218 } | |
| 3219 | |
| 3220 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 304 | 3221 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
| 0 | 3222 __ cmpl(tmp, src_length_addr); |
| 3223 __ jcc(Assembler::above, *stub->entry()); | |
| 3224 } | |
| 3225 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 304 | 3226 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
| 0 | 3227 __ cmpl(tmp, dst_length_addr); |
| 3228 __ jcc(Assembler::above, *stub->entry()); | |
| 3229 } | |
| 3230 | |
| 2446 | 3231 if (flags & LIR_OpArrayCopy::length_positive_check) { |
| 3232 __ testl(length, length); | |
| 3233 __ jcc(Assembler::less, *stub->entry()); | |
| 3234 __ jcc(Assembler::zero, *stub->continuation()); | |
| 3235 } | |
| 3236 | |
| 3237 #ifdef _LP64 | |
| 3238 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null | |
| 3239 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null | |
| 3240 #endif | |
| 3241 | |
| 0 | 3242 if (flags & LIR_OpArrayCopy::type_check) { |
| 2446 | 3243 // We don't know the array types are compatible |
| 3244 if (basic_type != T_OBJECT) { | |
| 3245 // Simple test for basic type arrays | |
| 3246 if (UseCompressedOops) { | |
| 3247 __ movl(tmp, src_klass_addr); | |
| 3248 __ cmpl(tmp, dst_klass_addr); | |
| 3249 } else { | |
| 3250 __ movptr(tmp, src_klass_addr); | |
| 3251 __ cmpptr(tmp, dst_klass_addr); | |
| 3252 } | |
| 3253 __ jcc(Assembler::notEqual, *stub->entry()); | |
| 2002 | 3254 } else { |
| 2446 | 3255 // For object arrays, if src is a sub class of dst then we can |
| 3256 // safely do the copy. | |
| 3257 Label cont, slow; | |
| 3258 | |
| 3259 __ push(src); | |
| 3260 __ push(dst); | |
| 3261 | |
| 3262 __ load_klass(src, src); | |
| 3263 __ load_klass(dst, dst); | |
| 3264 | |
| 3265 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); | |
| 3266 | |
| 3267 __ push(src); | |
| 3268 __ push(dst); | |
| 3269 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 3270 __ pop(dst); | |
| 3271 __ pop(src); | |
| 3272 | |
| 3273 __ cmpl(src, 0); | |
| 3274 __ jcc(Assembler::notEqual, cont); | |
| 3275 | |
| 3276 __ bind(slow); | |
| 3277 __ pop(dst); | |
| 3278 __ pop(src); | |
| 3279 | |
| 3280 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
| 3281 if (copyfunc_addr != NULL) { // use stub if available | |
| 3282 // src is not a sub class of dst so we have to do a | |
| 3283 // per-element check. | |
| 3284 | |
| 3285 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
| 3286 if ((flags & mask) != mask) { | |
| 3287 // Check that at least both of them object arrays. | |
| 3288 assert(flags & mask, "one of the two should be known to be an object array"); | |
| 3289 | |
| 3290 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
| 3291 __ load_klass(tmp, src); | |
| 3292 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
| 3293 __ load_klass(tmp, dst); | |
| 3294 } | |
|
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|
3295 int lh_offset = in_bytes(Klass::layout_helper_offset()); |
| 2446 | 3296 Address klass_lh_addr(tmp, lh_offset); |
| 3297 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
| 3298 __ cmpl(klass_lh_addr, objArray_lh); | |
| 3299 __ jcc(Assembler::notEqual, *stub->entry()); | |
| 3300 } | |
| 3301 | |
|
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|
3302 // Spill because stubs can use any register they like and it's |
|
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|
3303 // easier to restore just those that we care about. |
|
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|
3304 store_parameter(dst, 0); |
|
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|
3305 store_parameter(dst_pos, 1); |
|
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|
3306 store_parameter(length, 2); |
|
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|
3307 store_parameter(src_pos, 3); |
|
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|
3308 store_parameter(src, 4); |
|
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|
3309 |
| 2446 | 3310 #ifndef _LP64 |
| 3311 __ movptr(tmp, dst_klass_addr); | |
|
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|
3312 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset())); |
| 2446 | 3313 __ push(tmp); |
|
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|
3314 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); |
| 2446 | 3315 __ push(tmp); |
| 3316 __ push(length); | |
| 3317 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3318 __ push(tmp); | |
| 3319 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3320 __ push(tmp); | |
| 3321 | |
| 3322 __ call_VM_leaf(copyfunc_addr, 5); | |
| 3323 #else | |
| 3324 __ movl2ptr(length, length); //higher 32bits must be null | |
| 3325 | |
| 3326 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3327 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
| 3328 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3329 assert_different_registers(c_rarg1, dst, length); | |
| 3330 | |
| 3331 __ mov(c_rarg2, length); | |
| 3332 assert_different_registers(c_rarg2, dst); | |
| 3333 | |
| 3334 #ifdef _WIN64 | |
| 3335 // Allocate abi space for args but be sure to keep stack aligned | |
| 3336 __ subptr(rsp, 6*wordSize); | |
| 3337 __ load_klass(c_rarg3, dst); | |
|
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|
3338 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset())); |
| 2446 | 3339 store_parameter(c_rarg3, 4); |
|
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|
3340 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); |
| 2446 | 3341 __ call(RuntimeAddress(copyfunc_addr)); |
| 3342 __ addptr(rsp, 6*wordSize); | |
| 3343 #else | |
| 3344 __ load_klass(c_rarg4, dst); | |
|
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|
3345 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset())); |
|
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|
3346 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); |
| 2446 | 3347 __ call(RuntimeAddress(copyfunc_addr)); |
| 3348 #endif | |
| 3349 | |
| 3350 #endif | |
| 3351 | |
| 3352 #ifndef PRODUCT | |
| 3353 if (PrintC1Statistics) { | |
| 3354 Label failed; | |
| 3355 __ testl(rax, rax); | |
| 3356 __ jcc(Assembler::notZero, failed); | |
| 3357 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); | |
| 3358 __ bind(failed); | |
| 3359 } | |
| 3360 #endif | |
| 3361 | |
| 3362 __ testl(rax, rax); | |
| 3363 __ jcc(Assembler::zero, *stub->continuation()); | |
| 3364 | |
| 3365 #ifndef PRODUCT | |
| 3366 if (PrintC1Statistics) { | |
| 3367 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); | |
| 3368 } | |
| 3369 #endif | |
| 3370 | |
| 3371 __ mov(tmp, rax); | |
| 3372 | |
| 3373 __ xorl(tmp, -1); | |
| 3374 | |
|
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3375 // Restore previously spilled arguments |
|
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|
3376 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
|
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|
3377 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
|
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|
3378 __ movptr (length, Address(rsp, 2*BytesPerWord)); |
|
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|
3379 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
|
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|
3380 __ movptr (src, Address(rsp, 4*BytesPerWord)); |
|
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|
3381 |
| 2446 | 3382 |
| 3383 __ subl(length, tmp); | |
| 3384 __ addl(src_pos, tmp); | |
| 3385 __ addl(dst_pos, tmp); | |
| 3386 } | |
| 3387 | |
| 3388 __ jmp(*stub->entry()); | |
| 3389 | |
| 3390 __ bind(cont); | |
| 3391 __ pop(dst); | |
| 3392 __ pop(src); | |
| 2002 | 3393 } |
| 0 | 3394 } |
| 3395 | |
| 3396 #ifdef ASSERT | |
| 3397 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 3398 // Sanity check the known type with the incoming class. For the | |
| 3399 // primitive case the types must match exactly with src.klass and | |
| 3400 // dst.klass each exactly matching the default type. For the | |
| 3401 // object array case, if no type check is needed then either the | |
| 3402 // dst type is exactly the expected type and the src type is a | |
| 3403 // subtype which we can't check or src is the same array as dst | |
| 3404 // but not necessarily exactly of type default_type. | |
| 3405 Label known_ok, halt; | |
|
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changeset
|
3406 __ movoop(tmp, default_type->constant_encoding()); |
| 2002 | 3407 #ifdef _LP64 |
| 3408 if (UseCompressedOops) { | |
| 3409 __ encode_heap_oop(tmp); | |
| 3410 } | |
| 3411 #endif | |
| 3412 | |
| 0 | 3413 if (basic_type != T_OBJECT) { |
| 2002 | 3414 |
| 3415 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); | |
| 3416 else __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3417 __ jcc(Assembler::notEqual, halt); |
| 2002 | 3418 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); |
| 3419 else __ cmpptr(tmp, src_klass_addr); | |
| 0 | 3420 __ jcc(Assembler::equal, known_ok); |
| 3421 } else { | |
| 2002 | 3422 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
| 3423 else __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3424 __ jcc(Assembler::equal, known_ok); |
| 304 | 3425 __ cmpptr(src, dst); |
| 0 | 3426 __ jcc(Assembler::equal, known_ok); |
| 3427 } | |
| 3428 __ bind(halt); | |
| 3429 __ stop("incorrect type information in arraycopy"); | |
| 3430 __ bind(known_ok); | |
| 3431 } | |
| 3432 #endif | |
| 3433 | |
| 2446 | 3434 #ifndef PRODUCT |
| 3435 if (PrintC1Statistics) { | |
| 3436 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); | |
| 304 | 3437 } |
| 2446 | 3438 #endif |
| 304 | 3439 |
| 3440 #ifdef _LP64 | |
| 3441 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
| 3442 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3443 assert_different_registers(c_rarg1, length); | |
| 3444 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 3445 __ mov(c_rarg2, length); | |
| 3446 | |
| 3447 #else | |
| 3448 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 0 | 3449 store_parameter(tmp, 0); |
| 304 | 3450 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 0 | 3451 store_parameter(tmp, 1); |
| 3452 store_parameter(length, 2); | |
| 304 | 3453 #endif // _LP64 |
| 2446 | 3454 |
| 3455 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; | |
| 3456 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
| 3457 const char *name; | |
| 3458 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
| 3459 __ call_VM_leaf(entry, 0); | |
| 0 | 3460 |
| 3461 __ bind(*stub->continuation()); | |
| 3462 } | |
| 3463 | |
| 3464 | |
| 3465 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 3466 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
| 3467 Register hdr = op->hdr_opr()->as_register(); | |
| 3468 Register lock = op->lock_opr()->as_register(); | |
| 3469 if (!UseFastLocking) { | |
| 3470 __ jmp(*op->stub()->entry()); | |
| 3471 } else if (op->code() == lir_lock) { | |
| 3472 Register scratch = noreg; | |
| 3473 if (UseBiasedLocking) { | |
| 3474 scratch = op->scratch_opr()->as_register(); | |
| 3475 } | |
| 3476 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3477 // add debug info for NullPointerException only if one is possible | |
| 3478 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
| 3479 if (op->info() != NULL) { | |
| 3480 add_debug_info_for_null_check(null_check_offset, op->info()); | |
| 3481 } | |
| 3482 // done | |
| 3483 } else if (op->code() == lir_unlock) { | |
| 3484 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3485 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 3486 } else { | |
| 3487 Unimplemented(); | |
| 3488 } | |
| 3489 __ bind(*op->stub()->continuation()); | |
| 3490 } | |
| 3491 | |
| 3492 | |
| 3493 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 3494 ciMethod* method = op->profiled_method(); | |
| 3495 int bci = op->profiled_bci(); | |
| 3496 | |
| 3497 // Update counter for all call types | |
|
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5ddfcf4b079e
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2002
diff
changeset
|
3498 ciMethodData* md = method->method_data_or_null(); |
|
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2002
diff
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|
3499 assert(md != NULL, "Sanity"); |
| 0 | 3500 ciProfileData* data = md->bci_to_data(bci); |
| 3501 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 3502 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 3503 Register mdo = op->mdo()->as_register(); | |
|
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diff
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|
3504 __ movoop(mdo, md->constant_encoding()); |
| 0 | 3505 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
| 3506 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
| 3507 // Perform additional virtual call profiling for invokevirtual and | |
| 3508 // invokeinterface bytecodes | |
| 3509 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 1783 | 3510 C1ProfileVirtualCalls) { |
| 0 | 3511 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
| 3512 Register recv = op->recv()->as_register(); | |
| 3513 assert_different_registers(mdo, recv); | |
| 3514 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 3515 ciKlass* known_klass = op->known_holder(); | |
| 1783 | 3516 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
| 0 | 3517 // We know the type that will be seen at this call site; we can |
| 3518 // statically update the methodDataOop rather than needing to do | |
| 3519 // dynamic tests on the receiver type | |
| 3520 | |
| 3521 // NOTE: we should probably put a lock around this search to | |
| 3522 // avoid collisions by concurrent compilations | |
| 3523 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 3524 uint i; | |
| 3525 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3526 ciKlass* receiver = vc_data->receiver(i); | |
| 3527 if (known_klass->equals(receiver)) { | |
| 3528 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
| 1783 | 3529 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3530 return; |
| 3531 } | |
| 3532 } | |
| 3533 | |
| 3534 // Receiver type not found in profile data; select an empty slot | |
| 3535 | |
| 3536 // Note that this is less efficient than it should be because it | |
| 3537 // always does a write to the receiver part of the | |
| 3538 // VirtualCallData rather than just the first time | |
| 3539 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3540 ciKlass* receiver = vc_data->receiver(i); | |
| 3541 if (receiver == NULL) { | |
| 3542 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
|
989
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diff
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|
3543 __ movoop(recv_addr, known_klass->constant_encoding()); |
| 0 | 3544 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
| 1783 | 3545 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3546 return; |
| 3547 } | |
| 3548 } | |
| 3549 } else { | |
| 2002 | 3550 __ load_klass(recv, recv); |
| 0 | 3551 Label update_done; |
| 1783 | 3552 type_profile_helper(mdo, md, data, recv, &update_done); |
|
1206
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1204
diff
changeset
|
3553 // Receiver did not match any saved receiver and there is no empty row for it. |
|
1251
576e77447e3c
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kvn
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1206
diff
changeset
|
3554 // Increment total counter to indicate polymorphic case. |
| 1783 | 3555 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3556 |
| 3557 __ bind(update_done); | |
| 3558 } | |
|
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|
3559 } else { |
|
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|
3560 // Static call |
| 1783 | 3561 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3562 } |
| 3563 } | |
| 3564 | |
| 3565 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
| 3566 Unimplemented(); | |
| 3567 } | |
| 3568 | |
| 3569 | |
| 3570 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
| 304 | 3571 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
| 0 | 3572 } |
| 3573 | |
| 3574 | |
| 3575 void LIR_Assembler::align_backward_branch_target() { | |
| 3576 __ align(BytesPerWord); | |
| 3577 } | |
| 3578 | |
| 3579 | |
| 3580 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 3581 if (left->is_single_cpu()) { | |
| 3582 __ negl(left->as_register()); | |
| 3583 move_regs(left->as_register(), dest->as_register()); | |
| 3584 | |
| 3585 } else if (left->is_double_cpu()) { | |
| 3586 Register lo = left->as_register_lo(); | |
| 304 | 3587 #ifdef _LP64 |
| 3588 Register dst = dest->as_register_lo(); | |
| 3589 __ movptr(dst, lo); | |
| 3590 __ negptr(dst); | |
| 3591 #else | |
| 0 | 3592 Register hi = left->as_register_hi(); |
| 3593 __ lneg(hi, lo); | |
| 3594 if (dest->as_register_lo() == hi) { | |
| 3595 assert(dest->as_register_hi() != lo, "destroying register"); | |
| 3596 move_regs(hi, dest->as_register_hi()); | |
| 3597 move_regs(lo, dest->as_register_lo()); | |
| 3598 } else { | |
| 3599 move_regs(lo, dest->as_register_lo()); | |
| 3600 move_regs(hi, dest->as_register_hi()); | |
| 3601 } | |
| 304 | 3602 #endif // _LP64 |
| 0 | 3603 |
| 3604 } else if (dest->is_single_xmm()) { | |
| 3605 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
| 3606 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
| 3607 } | |
| 3608 __ xorps(dest->as_xmm_float_reg(), | |
| 3609 ExternalAddress((address)float_signflip_pool)); | |
| 3610 | |
| 3611 } else if (dest->is_double_xmm()) { | |
| 3612 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
| 3613 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
| 3614 } | |
| 3615 __ xorpd(dest->as_xmm_double_reg(), | |
| 3616 ExternalAddress((address)double_signflip_pool)); | |
| 3617 | |
| 3618 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
| 3619 assert(left->fpu() == 0, "arg must be on TOS"); | |
| 3620 assert(dest->fpu() == 0, "dest must be TOS"); | |
| 3621 __ fchs(); | |
| 3622 | |
| 3623 } else { | |
| 3624 ShouldNotReachHere(); | |
| 3625 } | |
| 3626 } | |
| 3627 | |
| 3628 | |
| 3629 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
| 3630 assert(addr->is_address() && dest->is_register(), "check"); | |
| 304 | 3631 Register reg; |
| 3632 reg = dest->as_pointer_register(); | |
| 3633 __ lea(reg, as_Address(addr->as_address_ptr())); | |
| 0 | 3634 } |
| 3635 | |
| 3636 | |
| 3637 | |
| 3638 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 3639 assert(!tmp->is_valid(), "don't need temporary"); | |
| 3640 __ call(RuntimeAddress(dest)); | |
| 3641 if (info != NULL) { | |
| 3642 add_call_info_here(info); | |
| 3643 } | |
| 3644 } | |
| 3645 | |
| 3646 | |
| 3647 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 3648 assert(type == T_LONG, "only for volatile long fields"); | |
| 3649 | |
| 3650 if (info != NULL) { | |
| 3651 add_debug_info_for_null_check_here(info); | |
| 3652 } | |
| 3653 | |
| 3654 if (src->is_double_xmm()) { | |
| 3655 if (dest->is_double_cpu()) { | |
| 304 | 3656 #ifdef _LP64 |
| 3657 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 3658 #else | |
| 3659 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 0 | 3660 __ psrlq(src->as_xmm_double_reg(), 32); |
| 304 | 3661 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
| 3662 #endif // _LP64 | |
| 0 | 3663 } else if (dest->is_double_stack()) { |
| 3664 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
| 3665 } else if (dest->is_address()) { | |
| 3666 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
| 3667 } else { | |
| 3668 ShouldNotReachHere(); | |
| 3669 } | |
| 3670 | |
| 3671 } else if (dest->is_double_xmm()) { | |
| 3672 if (src->is_double_stack()) { | |
| 3673 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3674 } else if (src->is_address()) { | |
| 3675 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
| 3676 } else { | |
| 3677 ShouldNotReachHere(); | |
| 3678 } | |
| 3679 | |
| 3680 } else if (src->is_double_fpu()) { | |
| 3681 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
| 3682 if (dest->is_double_stack()) { | |
| 3683 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 3684 } else if (dest->is_address()) { | |
| 3685 __ fistp_d(as_Address(dest->as_address_ptr())); | |
| 3686 } else { | |
| 3687 ShouldNotReachHere(); | |
| 3688 } | |
| 3689 | |
| 3690 } else if (dest->is_double_fpu()) { | |
| 3691 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
| 3692 if (src->is_double_stack()) { | |
| 3693 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3694 } else if (src->is_address()) { | |
| 3695 __ fild_d(as_Address(src->as_address_ptr())); | |
| 3696 } else { | |
| 3697 ShouldNotReachHere(); | |
| 3698 } | |
| 3699 } else { | |
| 3700 ShouldNotReachHere(); | |
| 3701 } | |
| 3702 } | |
| 3703 | |
| 3704 | |
| 3705 void LIR_Assembler::membar() { | |
| 304 | 3706 // QQQ sparc TSO uses this, |
| 3707 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
| 0 | 3708 } |
| 3709 | |
| 3710 void LIR_Assembler::membar_acquire() { | |
| 3711 // No x86 machines currently require load fences | |
| 3712 // __ load_fence(); | |
| 3713 } | |
| 3714 | |
| 3715 void LIR_Assembler::membar_release() { | |
| 3716 // No x86 machines currently require store fences | |
| 3717 // __ store_fence(); | |
| 3718 } | |
| 3719 | |
|
4966
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7120481: storeStore barrier in constructor with final field
jiangli
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4808
diff
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|
3720 void LIR_Assembler::membar_loadload() { |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
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parents:
4808
diff
changeset
|
3721 // no-op |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
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4808
diff
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|
3722 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
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4808
diff
changeset
|
3723 } |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
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4808
diff
changeset
|
3724 |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3725 void LIR_Assembler::membar_storestore() { |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3726 // no-op |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3727 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3728 } |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3729 |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3730 void LIR_Assembler::membar_loadstore() { |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3731 // no-op |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3732 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3733 } |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3734 |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3735 void LIR_Assembler::membar_storeload() { |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3736 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3737 } |
|
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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4808
diff
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|
3738 |
| 0 | 3739 void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
| 3740 assert(result_reg->is_register(), "check"); | |
| 304 | 3741 #ifdef _LP64 |
| 3742 // __ get_thread(result_reg->as_register_lo()); | |
| 3743 __ mov(result_reg->as_register(), r15_thread); | |
| 3744 #else | |
| 0 | 3745 __ get_thread(result_reg->as_register()); |
| 304 | 3746 #endif // _LP64 |
| 0 | 3747 } |
| 3748 | |
| 3749 | |
| 3750 void LIR_Assembler::peephole(LIR_List*) { | |
| 3751 // do nothing for now | |
| 3752 } | |
| 3753 | |
| 3754 | |
| 3755 #undef __ |