Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 4874:392a3f07d567
7141637: JSR 292: MH spread invoker crashes with NULL argument on x86_32
Reviewed-by: twisti
Contributed-by: Volker Simonis <volker.simonis@gmail.com>
author | twisti |
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date | Thu, 02 Feb 2012 09:14:38 -0800 |
parents | 22cee0ee8927 |
children | 4a24c4f648bd |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
27 | |
28 #include "runtime/globals_extension.hpp" | |
29 #include "runtime/vm_version.hpp" | |
30 | |
585 | 31 class VM_Version : public Abstract_VM_Version { |
32 public: | |
33 // cpuid result register layouts. These are all unions of a uint32_t | |
34 // (in case anyone wants access to the register as a whole) and a bitfield. | |
35 | |
36 union StdCpuid1Eax { | |
37 uint32_t value; | |
38 struct { | |
39 uint32_t stepping : 4, | |
40 model : 4, | |
41 family : 4, | |
42 proc_type : 2, | |
43 : 2, | |
44 ext_model : 4, | |
45 ext_family : 8, | |
46 : 4; | |
47 } bits; | |
48 }; | |
49 | |
50 union StdCpuid1Ebx { // example, unused | |
51 uint32_t value; | |
52 struct { | |
53 uint32_t brand_id : 8, | |
54 clflush_size : 8, | |
55 threads_per_cpu : 8, | |
56 apic_id : 8; | |
57 } bits; | |
58 }; | |
59 | |
60 union StdCpuid1Ecx { | |
61 uint32_t value; | |
62 struct { | |
63 uint32_t sse3 : 1, | |
64 : 2, | |
65 monitor : 1, | |
66 : 1, | |
67 vmx : 1, | |
68 : 1, | |
69 est : 1, | |
70 : 1, | |
71 ssse3 : 1, | |
72 cid : 1, | |
73 : 2, | |
74 cmpxchg16: 1, | |
75 : 4, | |
76 dca : 1, | |
77 sse4_1 : 1, | |
78 sse4_2 : 1, | |
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79 : 2, |
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80 popcnt : 1, |
4759 | 81 : 3, |
82 osxsave : 1, | |
83 avx : 1, | |
84 : 3; | |
585 | 85 } bits; |
86 }; | |
87 | |
88 union StdCpuid1Edx { | |
89 uint32_t value; | |
90 struct { | |
91 uint32_t : 4, | |
92 tsc : 1, | |
93 : 3, | |
94 cmpxchg8 : 1, | |
95 : 6, | |
96 cmov : 1, | |
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97 : 3, |
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98 clflush : 1, |
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99 : 3, |
585 | 100 mmx : 1, |
101 fxsr : 1, | |
102 sse : 1, | |
103 sse2 : 1, | |
104 : 1, | |
105 ht : 1, | |
106 : 3; | |
107 } bits; | |
108 }; | |
109 | |
110 union DcpCpuid4Eax { | |
111 uint32_t value; | |
112 struct { | |
113 uint32_t cache_type : 5, | |
114 : 21, | |
115 cores_per_cpu : 6; | |
116 } bits; | |
117 }; | |
118 | |
119 union DcpCpuid4Ebx { | |
120 uint32_t value; | |
121 struct { | |
122 uint32_t L1_line_size : 12, | |
123 partitions : 10, | |
124 associativity : 10; | |
125 } bits; | |
126 }; | |
127 | |
1622 | 128 union TplCpuidBEbx { |
129 uint32_t value; | |
130 struct { | |
131 uint32_t logical_cpus : 16, | |
132 : 16; | |
133 } bits; | |
134 }; | |
135 | |
585 | 136 union ExtCpuid1Ecx { |
137 uint32_t value; | |
138 struct { | |
139 uint32_t LahfSahf : 1, | |
140 CmpLegacy : 1, | |
141 : 4, | |
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142 lzcnt : 1, |
585 | 143 sse4a : 1, |
144 misalignsse : 1, | |
145 prefetchw : 1, | |
146 : 22; | |
147 } bits; | |
148 }; | |
149 | |
150 union ExtCpuid1Edx { | |
151 uint32_t value; | |
152 struct { | |
153 uint32_t : 22, | |
154 mmx_amd : 1, | |
155 mmx : 1, | |
156 fxsr : 1, | |
157 : 4, | |
158 long_mode : 1, | |
159 tdnow2 : 1, | |
160 tdnow : 1; | |
161 } bits; | |
162 }; | |
163 | |
164 union ExtCpuid5Ex { | |
165 uint32_t value; | |
166 struct { | |
167 uint32_t L1_line_size : 8, | |
168 L1_tag_lines : 8, | |
169 L1_assoc : 8, | |
170 L1_size : 8; | |
171 } bits; | |
172 }; | |
173 | |
4771 | 174 union ExtCpuid7Edx { |
175 uint32_t value; | |
176 struct { | |
177 uint32_t : 8, | |
178 tsc_invariance : 1, | |
179 : 23; | |
180 } bits; | |
181 }; | |
182 | |
585 | 183 union ExtCpuid8Ecx { |
184 uint32_t value; | |
185 struct { | |
186 uint32_t cores_per_cpu : 8, | |
187 : 24; | |
188 } bits; | |
189 }; | |
190 | |
4759 | 191 union SefCpuid7Eax { |
192 uint32_t value; | |
193 }; | |
194 | |
195 union SefCpuid7Ebx { | |
196 uint32_t value; | |
197 struct { | |
198 uint32_t fsgsbase : 1, | |
199 : 2, | |
200 bmi1 : 1, | |
201 : 1, | |
202 avx2 : 1, | |
203 : 2, | |
204 bmi2 : 1, | |
205 : 23; | |
206 } bits; | |
207 }; | |
208 | |
209 union XemXcr0Eax { | |
210 uint32_t value; | |
211 struct { | |
212 uint32_t x87 : 1, | |
213 sse : 1, | |
214 ymm : 1, | |
215 : 29; | |
216 } bits; | |
217 }; | |
218 | |
585 | 219 protected: |
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220 static int _cpu; |
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221 static int _model; |
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222 static int _stepping; |
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223 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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224 // 0 if this instruction is not available |
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225 static const char* _features_str; |
585 | 226 |
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227 enum { |
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228 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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229 CPU_CMOV = (1 << 1), |
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230 CPU_FXSR = (1 << 2), |
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231 CPU_HT = (1 << 3), |
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232 CPU_MMX = (1 << 4), |
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233 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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234 // may not necessarily support other 3dnow instructions |
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235 CPU_SSE = (1 << 6), |
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236 CPU_SSE2 = (1 << 7), |
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237 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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238 CPU_SSSE3 = (1 << 9), |
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239 CPU_SSE4A = (1 << 10), |
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240 CPU_SSE4_1 = (1 << 11), |
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241 CPU_SSE4_2 = (1 << 12), |
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242 CPU_POPCNT = (1 << 13), |
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243 CPU_LZCNT = (1 << 14), |
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244 CPU_TSC = (1 << 15), |
4771 | 245 CPU_TSCINV = (1 << 16), |
246 CPU_AVX = (1 << 17), | |
247 CPU_AVX2 = (1 << 18) | |
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248 } cpuFeatureFlags; |
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249 |
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250 enum { |
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251 // AMD |
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252 CPU_FAMILY_AMD_11H = 17, |
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253 // Intel |
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254 CPU_FAMILY_INTEL_CORE = 6, |
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255 CPU_MODEL_NEHALEM_EP = 26, |
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256 CPU_MODEL_WESTMERE_EP = 44, |
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257 // CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value |
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258 CPU_MODEL_SANDYBRIDGE_EP = 45 |
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259 } cpuExtendedFamily; |
585 | 260 |
261 // cpuid information block. All info derived from executing cpuid with | |
262 // various function numbers is stored here. Intel and AMD info is | |
263 // merged in this block: accessor methods disentangle it. | |
264 // | |
265 // The info block is laid out in subblocks of 4 dwords corresponding to | |
266 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
267 struct CpuidInfo { | |
268 // cpuid function 0 | |
269 uint32_t std_max_function; | |
270 uint32_t std_vendor_name_0; | |
271 uint32_t std_vendor_name_1; | |
272 uint32_t std_vendor_name_2; | |
273 | |
274 // cpuid function 1 | |
275 StdCpuid1Eax std_cpuid1_eax; | |
276 StdCpuid1Ebx std_cpuid1_ebx; | |
277 StdCpuid1Ecx std_cpuid1_ecx; | |
278 StdCpuid1Edx std_cpuid1_edx; | |
279 | |
280 // cpuid function 4 (deterministic cache parameters) | |
281 DcpCpuid4Eax dcp_cpuid4_eax; | |
282 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
283 uint32_t dcp_cpuid4_ecx; // unused currently | |
284 uint32_t dcp_cpuid4_edx; // unused currently | |
285 | |
4759 | 286 // cpuid function 7 (structured extended features) |
287 SefCpuid7Eax sef_cpuid7_eax; | |
288 SefCpuid7Ebx sef_cpuid7_ebx; | |
289 uint32_t sef_cpuid7_ecx; // unused currently | |
290 uint32_t sef_cpuid7_edx; // unused currently | |
291 | |
1622 | 292 // cpuid function 0xB (processor topology) |
293 // ecx = 0 | |
294 uint32_t tpl_cpuidB0_eax; | |
295 TplCpuidBEbx tpl_cpuidB0_ebx; | |
296 uint32_t tpl_cpuidB0_ecx; // unused currently | |
297 uint32_t tpl_cpuidB0_edx; // unused currently | |
298 | |
299 // ecx = 1 | |
300 uint32_t tpl_cpuidB1_eax; | |
301 TplCpuidBEbx tpl_cpuidB1_ebx; | |
302 uint32_t tpl_cpuidB1_ecx; // unused currently | |
303 uint32_t tpl_cpuidB1_edx; // unused currently | |
304 | |
305 // ecx = 2 | |
306 uint32_t tpl_cpuidB2_eax; | |
307 TplCpuidBEbx tpl_cpuidB2_ebx; | |
308 uint32_t tpl_cpuidB2_ecx; // unused currently | |
309 uint32_t tpl_cpuidB2_edx; // unused currently | |
310 | |
585 | 311 // cpuid function 0x80000000 // example, unused |
312 uint32_t ext_max_function; | |
313 uint32_t ext_vendor_name_0; | |
314 uint32_t ext_vendor_name_1; | |
315 uint32_t ext_vendor_name_2; | |
316 | |
317 // cpuid function 0x80000001 | |
318 uint32_t ext_cpuid1_eax; // reserved | |
319 uint32_t ext_cpuid1_ebx; // reserved | |
320 ExtCpuid1Ecx ext_cpuid1_ecx; | |
321 ExtCpuid1Edx ext_cpuid1_edx; | |
322 | |
323 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
324 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
325 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
326 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
327 | |
328 // cpuid function 0x80000005 //AMD L1, Intel reserved | |
329 uint32_t ext_cpuid5_eax; // unused currently | |
330 uint32_t ext_cpuid5_ebx; // reserved | |
331 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
332 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
333 | |
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334 // cpuid function 0x80000007 |
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335 uint32_t ext_cpuid7_eax; // reserved |
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336 uint32_t ext_cpuid7_ebx; // reserved |
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337 uint32_t ext_cpuid7_ecx; // reserved |
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338 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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339 |
585 | 340 // cpuid function 0x80000008 |
341 uint32_t ext_cpuid8_eax; // unused currently | |
342 uint32_t ext_cpuid8_ebx; // reserved | |
343 ExtCpuid8Ecx ext_cpuid8_ecx; | |
344 uint32_t ext_cpuid8_edx; // reserved | |
4759 | 345 |
346 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
347 XemXcr0Eax xem_xcr0_eax; | |
348 uint32_t xem_xcr0_edx; // reserved | |
585 | 349 }; |
350 | |
351 // The actual cpuid info block | |
352 static CpuidInfo _cpuid_info; | |
353 | |
354 // Extractors and predicates | |
355 static uint32_t extended_cpu_family() { | |
356 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
357 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
358 return result; | |
359 } | |
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360 |
585 | 361 static uint32_t extended_cpu_model() { |
362 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
363 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
364 return result; | |
365 } | |
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366 |
585 | 367 static uint32_t cpu_stepping() { |
368 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
369 return result; | |
370 } | |
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371 |
585 | 372 static uint logical_processor_count() { |
373 uint result = threads_per_core(); | |
374 return result; | |
375 } | |
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376 |
585 | 377 static uint32_t feature_flags() { |
378 uint32_t result = 0; | |
379 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
380 result |= CPU_CX8; | |
381 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
382 result |= CPU_CMOV; | |
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383 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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384 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
585 | 385 result |= CPU_FXSR; |
386 // HT flag is set for multi-core processors also. | |
387 if (threads_per_core() > 1) | |
388 result |= CPU_HT; | |
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389 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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390 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
585 | 391 result |= CPU_MMX; |
392 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
393 result |= CPU_SSE; | |
394 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
395 result |= CPU_SSE2; | |
396 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
397 result |= CPU_SSE3; | |
398 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
399 result |= CPU_SSSE3; | |
400 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
401 result |= CPU_SSE4_1; | |
402 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
403 result |= CPU_SSE4_2; | |
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404 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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405 result |= CPU_POPCNT; |
4759 | 406 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
407 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
408 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
409 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
410 result |= CPU_AVX; | |
411 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
412 result |= CPU_AVX2; | |
413 } | |
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414 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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415 result |= CPU_TSC; |
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416 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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417 result |= CPU_TSCINV; |
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418 |
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419 // AMD features. |
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420 if (is_amd()) { |
2479 | 421 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
422 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
423 result |= CPU_3DNOW_PREFETCH; | |
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424 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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425 result |= CPU_LZCNT; |
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426 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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427 result |= CPU_SSE4A; |
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428 } |
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429 |
585 | 430 return result; |
431 } | |
432 | |
433 static void get_processor_features(); | |
434 | |
435 public: | |
436 // Offsets for cpuid asm stub | |
437 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
438 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
439 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
4759 | 440 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
585 | 441 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
442 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
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443 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
585 | 444 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
1622 | 445 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
446 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
447 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
4759 | 448 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
585 | 449 |
450 // Initialization | |
451 static void initialize(); | |
452 | |
453 // Asserts | |
454 static void assert_is_initialized() { | |
455 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
456 } | |
457 | |
458 // | |
459 // Processor family: | |
460 // 3 - 386 | |
461 // 4 - 486 | |
462 // 5 - Pentium | |
463 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
464 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
465 // family 6 model: 9, 13, 14, 15 | |
466 // 0x0f - Pentium 4, Opteron | |
467 // | |
468 // Note: The cpu family should be used to select between | |
469 // instruction sequences which are valid on all Intel | |
470 // processors. Use the feature test functions below to | |
471 // determine whether a particular instruction is supported. | |
472 // | |
473 static int cpu_family() { return _cpu;} | |
474 static bool is_P6() { return cpu_family() >= 6; } | |
475 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
476 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
477 | |
1647 | 478 static bool supports_processor_topology() { |
479 return (_cpuid_info.std_max_function >= 0xB) && | |
480 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
481 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
482 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); | |
483 } | |
484 | |
585 | 485 static uint cores_per_cpu() { |
486 uint result = 1; | |
487 if (is_intel()) { | |
1647 | 488 if (supports_processor_topology()) { |
1622 | 489 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
490 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
491 } else { | |
492 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
493 } | |
585 | 494 } else if (is_amd()) { |
495 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
496 } | |
497 return result; | |
498 } | |
499 | |
500 static uint threads_per_core() { | |
501 uint result = 1; | |
1647 | 502 if (is_intel() && supports_processor_topology()) { |
1622 | 503 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
504 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
585 | 505 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
506 cores_per_cpu(); | |
507 } | |
508 return result; | |
509 } | |
510 | |
3854 | 511 static intx prefetch_data_size() { |
585 | 512 intx result = 0; |
513 if (is_intel()) { | |
514 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
515 } else if (is_amd()) { | |
516 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
517 } | |
518 if (result < 32) // not defined ? | |
519 result = 32; // 32 bytes by default on x86 and other x64 | |
520 return result; | |
521 } | |
522 | |
523 // | |
524 // Feature identification | |
525 // | |
526 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
527 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
528 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
529 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
530 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
531 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
532 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
533 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
534 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
535 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
536 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
537 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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538 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
4759 | 539 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
540 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
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541 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
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542 |
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543 // Intel features |
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544 static bool is_intel_family_core() { return is_intel() && |
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545 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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546 |
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547 static bool is_intel_tsc_synched_at_init() { |
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548 if (is_intel_family_core()) { |
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549 uint32_t ext_model = extended_cpu_model(); |
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550 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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551 ext_model == CPU_MODEL_WESTMERE_EP || |
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552 // TODO ext_model == CPU_MODEL_IVYBRIDGE_EP || |
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553 ext_model == CPU_MODEL_SANDYBRIDGE_EP) { |
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554 // 2-socket invtsc support. EX versions with 4 sockets are not |
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555 // guaranteed to synchronize tscs at initialization via a double |
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556 // handshake. The tscs can be explicitly set in software. Code |
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557 // that uses tsc values must be prepared for them to arbitrarily |
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558 // jump backward or forward. |
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559 return true; |
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560 } |
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561 } |
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562 return false; |
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563 } |
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564 |
585 | 565 // AMD features |
2479 | 566 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
585 | 567 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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568 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
585 | 569 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
570 | |
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571 static bool is_amd_Barcelona() { return is_amd() && |
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572 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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573 |
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574 // Intel and AMD newer cores support fast timestamps well |
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575 static bool supports_tscinv_bit() { |
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576 return (_cpuFeatures & CPU_TSCINV) != 0; |
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577 } |
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578 static bool supports_tscinv() { |
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579 return supports_tscinv_bit() && |
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580 ( (is_amd() && !is_amd_Barcelona()) || |
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581 is_intel_tsc_synched_at_init() ); |
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582 } |
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583 |
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584 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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585 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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586 supports_sse3() && _model != 0x1C; } |
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587 |
585 | 588 static bool supports_compare_and_exchange() { return true; } |
589 | |
590 static const char* cpu_features() { return _features_str; } | |
591 | |
592 static intx allocate_prefetch_distance() { | |
593 // This method should be called before allocate_prefetch_style(). | |
594 // | |
595 // Hardware prefetching (distance/size in bytes): | |
596 // Pentium 3 - 64 / 32 | |
597 // Pentium 4 - 256 / 128 | |
598 // Athlon - 64 / 32 ???? | |
599 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
600 // Core - 128 / 64 | |
601 // | |
602 // Software prefetching (distance in bytes / instruction with best score): | |
603 // Pentium 3 - 128 / prefetchnta | |
604 // Pentium 4 - 512 / prefetchnta | |
605 // Athlon - 128 / prefetchnta | |
606 // Opteron - 256 / prefetchnta | |
607 // Core - 256 / prefetchnta | |
608 // It will be used only when AllocatePrefetchStyle > 0 | |
609 | |
610 intx count = AllocatePrefetchDistance; | |
611 if (count < 0) { // default ? | |
612 if (is_amd()) { // AMD | |
613 if (supports_sse2()) | |
614 count = 256; // Opteron | |
615 else | |
616 count = 128; // Athlon | |
617 } else { // Intel | |
618 if (supports_sse2()) | |
619 if (cpu_family() == 6) { | |
620 count = 256; // Pentium M, Core, Core2 | |
621 } else { | |
622 count = 512; // Pentium 4 | |
623 } | |
624 else | |
625 count = 128; // Pentium 3 (and all other old CPUs) | |
626 } | |
627 } | |
628 return count; | |
629 } | |
630 static intx allocate_prefetch_style() { | |
631 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
632 // Return 0 if AllocatePrefetchDistance was not defined. | |
633 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
634 } | |
635 | |
636 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
637 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
638 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
639 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
640 | |
641 // gc copy/scan is disabled if prefetchw isn't supported, because | |
642 // Prefetch::write emits an inlined prefetchw on Linux. | |
643 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
644 // The used prefetcht0 instruction works for both amd64 and em64t. | |
645 static intx prefetch_copy_interval_in_bytes() { | |
646 intx interval = PrefetchCopyIntervalInBytes; | |
647 return interval >= 0 ? interval : 576; | |
648 } | |
649 static intx prefetch_scan_interval_in_bytes() { | |
650 intx interval = PrefetchScanIntervalInBytes; | |
651 return interval >= 0 ? interval : 576; | |
652 } | |
653 static intx prefetch_fields_ahead() { | |
654 intx count = PrefetchFieldsAhead; | |
655 return count >= 0 ? count : 1; | |
656 } | |
657 }; | |
1972 | 658 |
659 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |