Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 21603:4437f0da4b26
handle graal.jar that has already had Graal.class patched
author | Doug Simon <doug.simon@oracle.com> |
---|---|
date | Fri, 29 May 2015 16:24:25 +0200 |
parents | 7848fc12602b |
children |
rev | line source |
---|---|
0 | 1 /* |
17910
03214612e77e
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
14261
diff
changeset
|
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
7204
f0c2369fda5a
8003250: SPARC: move MacroAssembler into separate file
twisti
parents:
6848
diff
changeset
|
26 #include "asm/macroAssembler.inline.hpp" |
1972 | 27 #include "memory/resourceArea.hpp" |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_sparc.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
0 | 37 |
38 int VM_Version::_features = VM_Version::unknown_m; | |
39 const char* VM_Version::_features_str = ""; | |
20421
d635fd1ac81c
8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents:
20313
diff
changeset
|
40 unsigned int VM_Version::_L2_cache_line_size = 0; |
0 | 41 |
42 void VM_Version::initialize() { | |
43 _features = determine_features(); | |
44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
46 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
47 | |
3854 | 48 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
49 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
50 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; | |
51 | |
0 | 52 // Allocation prefetch settings |
3854 | 53 intx cache_line_size = prefetch_data_size(); |
0 | 54 if( cache_line_size > AllocatePrefetchStepSize ) |
55 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 56 |
57 assert(AllocatePrefetchLines > 0, "invalid value"); | |
58 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
59 AllocatePrefetchLines = 3; | |
60 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
61 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
62 AllocateInstancePrefetchLines = 1; | |
0 | 63 |
64 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
65 AllocatePrefetchStyle = allocate_prefetch_style(); | |
66 | |
3854 | 67 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
68 (AllocatePrefetchDistance > 0), "invalid value"); | |
69 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || | |
70 (AllocatePrefetchDistance <= 0)) { | |
71 AllocatePrefetchDistance = AllocatePrefetchStepSize; | |
72 } | |
0 | 73 |
3839 | 74 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
75 warning("BIS instructions are not available on this CPU"); | |
76 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
77 } | |
78 | |
10997 | 79 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
80 | |
81 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); | |
82 if (ArraycopySrcPrefetchDistance >= 4096) | |
83 ArraycopySrcPrefetchDistance = 4064; | |
84 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); | |
85 if (ArraycopyDstPrefetchDistance >= 4096) | |
86 ArraycopyDstPrefetchDistance = 4064; | |
3903 | 87 |
0 | 88 UseSSE = 0; // Only on x86 and x64 |
89 | |
3854 | 90 _supports_cx8 = has_v9(); |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6610
diff
changeset
|
91 _supports_atomic_getset4 = true; // swap instruction |
0 | 92 |
13423
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
93 // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
94 // we have to take this check out of the 'is_niagara()' block below. |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
95 if (has_blk_init()) { |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
96 // When using CMS or G1, we cannot use memset() in BOT updates |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
97 // because the sun4v/CMT version in libc_psr uses BIS which |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
98 // exposes "phantom zeros" to concurrent readers. See 6948537. |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
99 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
100 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
101 } |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
102 // Issue a stern warning if the user has explicitly set |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
103 // UseMemSetInBOT (it is known to cause issues), but allow |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
104 // use for experimentation and debugging. |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
105 if (UseConcMarkSweepGC || UseG1GC) { |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
106 if (UseMemSetInBOT) { |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
107 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
108 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
109 " on sun4v; please understand that you are using at your own risk!"); |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
110 } |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
111 } |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
112 } |
eae426d683f6
8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs
simonis
parents:
10997
diff
changeset
|
113 |
2080 | 114 if (is_niagara()) { |
0 | 115 // Indirect branch is the same cost as direct |
116 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
675 | 117 FLAG_SET_DEFAULT(UseInlineCaches, false); |
0 | 118 } |
2080 | 119 // Align loops on a single instruction boundary. |
120 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
121 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
122 } | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
123 #ifdef _LP64 |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
124 // 32-bit oops don't make sense for the 64-bit VM on sparc |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
125 // since the 32-bit VM has the same registers and smaller objects. |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
126 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6797
diff
changeset
|
127 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
128 #endif // _LP64 |
0 | 129 #ifdef COMPILER2 |
130 // Indirect branch is the same cost as direct | |
131 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
675 | 132 FLAG_SET_DEFAULT(UseJumpTables, true); |
0 | 133 } |
134 // Single-issue, so entry and loop tops are | |
135 // aligned on a single instruction boundary | |
136 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
675 | 137 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
0 | 138 } |
2080 | 139 if (is_niagara_plus()) { |
3854 | 140 if (has_blk_init() && UseTLAB && |
141 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | |
142 // Use BIS instruction for TLAB allocation prefetch. | |
143 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); | |
144 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { | |
145 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); | |
146 } | |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
147 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
3854 | 148 // Use smaller prefetch distance with BIS |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
149 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
150 } |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
151 } |
3854 | 152 if (is_T4()) { |
153 // Double number of prefetched cache lines on T4 | |
154 // since L2 cache line size is smaller (32 bytes). | |
155 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { | |
156 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); | |
157 } | |
158 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { | |
159 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); | |
160 } | |
161 } | |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
162 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
163 // Use different prefetch distance without BIS |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
164 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
165 } |
3854 | 166 if (AllocatePrefetchInstr == 1) { |
167 // Need a space at the end of TLAB for BIS since it | |
168 // will fault when accessing memory outside of heap. | |
169 | |
170 // +1 for rounding up to next cache line, +1 to be safe | |
171 int lines = AllocatePrefetchLines + 2; | |
172 int step_size = AllocatePrefetchStepSize; | |
173 int distance = AllocatePrefetchDistance; | |
174 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; | |
175 } | |
0 | 176 } |
177 #endif | |
178 } | |
179 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
180 // Use hardware population count instruction if available. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
181 if (has_hardware_popc()) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
182 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
675 | 183 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
184 } |
3839 | 185 } else if (UsePopCountInstruction) { |
186 warning("POPC instruction is not available on this CPU"); | |
187 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
188 } | |
189 | |
190 // T4 and newer Sparc cpus have new compare and branch instruction. | |
191 if (has_cbcond()) { | |
192 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
193 FLAG_SET_DEFAULT(UseCBCond, true); | |
194 } | |
195 } else if (UseCBCond) { | |
196 warning("CBCOND instruction is not available on this CPU"); | |
197 FLAG_SET_DEFAULT(UseCBCond, false); | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
198 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
199 |
3892 | 200 assert(BlockZeroingLowLimit > 0, "invalid value"); |
20421
d635fd1ac81c
8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents:
20313
diff
changeset
|
201 if (has_block_zeroing() && cache_line_size > 0) { |
3892 | 202 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
203 FLAG_SET_DEFAULT(UseBlockZeroing, true); | |
204 } | |
205 } else if (UseBlockZeroing) { | |
206 warning("BIS zeroing instructions are not available on this CPU"); | |
207 FLAG_SET_DEFAULT(UseBlockZeroing, false); | |
208 } | |
209 | |
3903 | 210 assert(BlockCopyLowLimit > 0, "invalid value"); |
20421
d635fd1ac81c
8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents:
20313
diff
changeset
|
211 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
3903 | 212 if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
213 FLAG_SET_DEFAULT(UseBlockCopy, true); | |
214 } | |
215 } else if (UseBlockCopy) { | |
216 warning("BIS instructions are not available or expensive on this CPU"); | |
217 FLAG_SET_DEFAULT(UseBlockCopy, false); | |
218 } | |
219 | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
220 #ifdef COMPILER2 |
3839 | 221 // T4 and newer Sparc cpus have fast RDPC. |
222 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
4053
e3b0dcc327b9
7104561: UseRDPCForConstantTableBase doesn't work after shorten branches changes
twisti
parents:
3903
diff
changeset
|
223 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
3839 | 224 } |
225 | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
226 // Currently not supported anywhere. |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
227 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
3851 | 228 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4053
diff
changeset
|
229 MaxVectorSize = 8; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4053
diff
changeset
|
230 |
3851 | 231 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
232 #endif |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
233 |
3851 | 234 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
235 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); | |
236 | |
0 | 237 char buf[512]; |
20313
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
238 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
3839 | 239 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
240 (has_hardware_popc() ? ", popc" : ""), |
3839 | 241 (has_vis1() ? ", vis1" : ""), |
242 (has_vis2() ? ", vis2" : ""), | |
243 (has_vis3() ? ", vis3" : ""), | |
244 (has_blk_init() ? ", blk_init" : ""), | |
245 (has_cbcond() ? ", cbcond" : ""), | |
14261 | 246 (has_aes() ? ", aes" : ""), |
20313
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
247 (has_sha1() ? ", sha1" : ""), |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
248 (has_sha256() ? ", sha256" : ""), |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
249 (has_sha512() ? ", sha512" : ""), |
3839 | 250 (is_ultra3() ? ", ultra3" : ""), |
251 (is_sun4v() ? ", sun4v" : ""), | |
252 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
253 (is_sparc64() ? ", sparc64" : ""), | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
254 (!has_hardware_mul32() ? ", no-mul32" : ""), |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
255 (!has_hardware_div32() ? ", no-div32" : ""), |
0 | 256 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
257 | |
258 // buf is started with ", " or is empty | |
259 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
260 | |
3804 | 261 // UseVIS is set to the smallest of what hardware supports and what |
262 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
263 // older UltraSparc which do not support it. | |
264 if (UseVIS > 3) UseVIS=3; | |
265 if (UseVIS < 0) UseVIS=0; | |
266 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
267 UseVIS = MIN2((intx)2,UseVIS); | |
268 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
269 UseVIS = MIN2((intx)1,UseVIS); | |
270 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
271 UseVIS = 0; | |
272 | |
17910
03214612e77e
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
14261
diff
changeset
|
273 // SPARC T4 and above should have support for AES instructions |
14261 | 274 if (has_aes()) { |
17910
03214612e77e
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
14261
diff
changeset
|
275 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 |
14261 | 276 if (FLAG_IS_DEFAULT(UseAES)) { |
277 FLAG_SET_DEFAULT(UseAES, true); | |
278 } | |
279 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { | |
280 FLAG_SET_DEFAULT(UseAESIntrinsics, true); | |
281 } | |
282 // we disable both the AES flags if either of them is disabled on the command line | |
283 if (!UseAES || !UseAESIntrinsics) { | |
284 FLAG_SET_DEFAULT(UseAES, false); | |
285 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
286 } | |
287 } else { | |
288 if (UseAES || UseAESIntrinsics) { | |
17910
03214612e77e
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
14261
diff
changeset
|
289 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
14261 | 290 if (UseAES) { |
291 FLAG_SET_DEFAULT(UseAES, false); | |
292 } | |
293 if (UseAESIntrinsics) { | |
294 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
295 } | |
296 } | |
297 } | |
298 } else if (UseAES || UseAESIntrinsics) { | |
299 warning("AES instructions are not available on this CPU"); | |
300 if (UseAES) { | |
301 FLAG_SET_DEFAULT(UseAES, false); | |
302 } | |
303 if (UseAESIntrinsics) { | |
304 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
305 } | |
306 } | |
307 | |
20313
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
308 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
309 if (has_sha1() || has_sha256() || has_sha512()) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
310 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
311 if (FLAG_IS_DEFAULT(UseSHA)) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
312 FLAG_SET_DEFAULT(UseSHA, true); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
313 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
314 } else { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
315 if (UseSHA) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
316 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
317 FLAG_SET_DEFAULT(UseSHA, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
318 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
319 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
320 } else if (UseSHA) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
321 warning("SHA instructions are not available on this CPU"); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
322 FLAG_SET_DEFAULT(UseSHA, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
323 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
324 |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
325 if (!UseSHA) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
326 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
327 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
328 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
329 } else { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
330 if (has_sha1()) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
331 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
332 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
333 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
334 } else if (UseSHA1Intrinsics) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
335 warning("SHA1 instruction is not available on this CPU."); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
336 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
337 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
338 if (has_sha256()) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
339 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
340 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
341 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
342 } else if (UseSHA256Intrinsics) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
343 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
344 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
345 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
346 |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
347 if (has_sha512()) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
348 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
349 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
350 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
351 } else if (UseSHA512Intrinsics) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
352 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
353 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
354 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
355 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
356 FLAG_SET_DEFAULT(UseSHA, false); |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
357 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
358 } |
b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
17937
diff
changeset
|
359 |
7587 | 360 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
361 (cache_line_size > ContendedPaddingWidth)) | |
362 ContendedPaddingWidth = cache_line_size; | |
363 | |
0 | 364 #ifndef PRODUCT |
365 if (PrintMiscellaneous && Verbose) { | |
20421
d635fd1ac81c
8056124: Hotspot should use PICL interface to get cacheline size on SPARC
iveresov
parents:
20313
diff
changeset
|
366 tty->print_cr("L2 cache line size: %u", L2_cache_line_size()); |
3854 | 367 tty->print("Allocation"); |
0 | 368 if (AllocatePrefetchStyle <= 0) { |
3854 | 369 tty->print_cr(": no prefetching"); |
0 | 370 } else { |
3854 | 371 tty->print(" prefetching: "); |
372 if (AllocatePrefetchInstr == 0) { | |
373 tty->print("PREFETCH"); | |
374 } else if (AllocatePrefetchInstr == 1) { | |
375 tty->print("BIS"); | |
376 } | |
0 | 377 if (AllocatePrefetchLines > 1) { |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
378 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
0 | 379 } else { |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
380 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
0 | 381 } |
382 } | |
383 if (PrefetchCopyIntervalInBytes > 0) { | |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
384 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
0 | 385 } |
386 if (PrefetchScanIntervalInBytes > 0) { | |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
387 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
0 | 388 } |
389 if (PrefetchFieldsAhead > 0) { | |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
390 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
0 | 391 } |
7587 | 392 if (ContendedPaddingWidth > 0) { |
17937
78bbf4d43a14
8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents:
17910
diff
changeset
|
393 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
7587 | 394 } |
0 | 395 } |
396 #endif // PRODUCT | |
397 } | |
398 | |
399 void VM_Version::print_features() { | |
400 tty->print_cr("Version:%s", cpu_features()); | |
401 } | |
402 | |
403 int VM_Version::determine_features() { | |
404 if (UseV8InstrsOnly) { | |
405 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
406 return generic_v8_m; | |
407 } | |
408 | |
409 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
410 | |
411 if (features == unknown_m) { | |
412 features = generic_v9_m; | |
413 warning("Cannot recognize SPARC version. Default to V9"); | |
414 } | |
415 | |
2080 | 416 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
417 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
418 if (is_T_family(features)) { | |
0 | 419 // Happy to accomodate... |
420 } else { | |
421 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
2080 | 422 features |= T_family_m; |
0 | 423 } |
424 } else { | |
2080 | 425 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
0 | 426 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
2080 | 427 features &= ~(T_family_m | T1_model_m); |
0 | 428 } else { |
429 // Happy to accomodate... | |
430 } | |
431 } | |
432 | |
433 return features; | |
434 } | |
435 | |
436 static int saved_features = 0; | |
437 | |
438 void VM_Version::allow_all() { | |
439 saved_features = _features; | |
440 _features = all_features_m; | |
441 } | |
442 | |
443 void VM_Version::revert() { | |
444 _features = saved_features; | |
445 } | |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
446 |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
447 unsigned int VM_Version::calc_parallel_worker_threads() { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
448 unsigned int result; |
6797
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
449 if (is_M_series()) { |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
450 // for now, use same gc thread calculation for M-series as for niagara-plus |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
451 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
452 result = nof_parallel_worker_threads(5, 16, 8); |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
453 } else if (is_niagara_plus()) { |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
454 result = nof_parallel_worker_threads(5, 16, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
455 } else { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
456 result = nof_parallel_worker_threads(5, 8, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
457 } |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
458 return result; |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
459 } |