Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 20495:58925d1f325e
8057722: G1: Code root hashtable updated incorrectly when evacuation failed
Reviewed-by: brutisso, jwilhelm
author | mgerdin |
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date | Mon, 08 Sep 2014 17:47:43 +0200 |
parents | d635fd1ac81c |
children | 7848fc12602b |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
1972 | 27 #include "memory/resourceArea.hpp" |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_sparc.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
0 | 37 |
38 int VM_Version::_features = VM_Version::unknown_m; | |
39 const char* VM_Version::_features_str = ""; | |
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40 unsigned int VM_Version::_L2_cache_line_size = 0; |
0 | 41 |
42 void VM_Version::initialize() { | |
43 _features = determine_features(); | |
44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
46 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
47 | |
3854 | 48 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
49 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
50 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; | |
51 | |
0 | 52 // Allocation prefetch settings |
3854 | 53 intx cache_line_size = prefetch_data_size(); |
0 | 54 if( cache_line_size > AllocatePrefetchStepSize ) |
55 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 56 |
57 assert(AllocatePrefetchLines > 0, "invalid value"); | |
58 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
59 AllocatePrefetchLines = 3; | |
60 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
61 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
62 AllocateInstancePrefetchLines = 1; | |
0 | 63 |
64 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
65 AllocatePrefetchStyle = allocate_prefetch_style(); | |
66 | |
3854 | 67 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
68 (AllocatePrefetchDistance > 0), "invalid value"); | |
69 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || | |
70 (AllocatePrefetchDistance <= 0)) { | |
71 AllocatePrefetchDistance = AllocatePrefetchStepSize; | |
72 } | |
0 | 73 |
3839 | 74 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
75 warning("BIS instructions are not available on this CPU"); | |
76 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
77 } | |
78 | |
10997 | 79 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
80 | |
81 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); | |
82 if (ArraycopySrcPrefetchDistance >= 4096) | |
83 ArraycopySrcPrefetchDistance = 4064; | |
84 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); | |
85 if (ArraycopyDstPrefetchDistance >= 4096) | |
86 ArraycopyDstPrefetchDistance = 4064; | |
3903 | 87 |
0 | 88 UseSSE = 0; // Only on x86 and x64 |
89 | |
3854 | 90 _supports_cx8 = has_v9(); |
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91 _supports_atomic_getset4 = true; // swap instruction |
0 | 92 |
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93 // There are Fujitsu Sparc64 CPUs which support blk_init as well so |
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94 // we have to take this check out of the 'is_niagara()' block below. |
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95 if (has_blk_init()) { |
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96 // When using CMS or G1, we cannot use memset() in BOT updates |
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97 // because the sun4v/CMT version in libc_psr uses BIS which |
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98 // exposes "phantom zeros" to concurrent readers. See 6948537. |
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99 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { |
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100 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
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101 } |
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102 // Issue a stern warning if the user has explicitly set |
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103 // UseMemSetInBOT (it is known to cause issues), but allow |
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104 // use for experimentation and debugging. |
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105 if (UseConcMarkSweepGC || UseG1GC) { |
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106 if (UseMemSetInBOT) { |
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107 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); |
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108 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" |
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109 " on sun4v; please understand that you are using at your own risk!"); |
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110 } |
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111 } |
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112 } |
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113 |
2080 | 114 if (is_niagara()) { |
0 | 115 // Indirect branch is the same cost as direct |
116 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
675 | 117 FLAG_SET_DEFAULT(UseInlineCaches, false); |
0 | 118 } |
2080 | 119 // Align loops on a single instruction boundary. |
120 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
121 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
122 } | |
113
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123 #ifdef _LP64 |
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124 // 32-bit oops don't make sense for the 64-bit VM on sparc |
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125 // since the 32-bit VM has the same registers and smaller objects. |
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126 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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127 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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128 #endif // _LP64 |
0 | 129 #ifdef COMPILER2 |
130 // Indirect branch is the same cost as direct | |
131 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
675 | 132 FLAG_SET_DEFAULT(UseJumpTables, true); |
0 | 133 } |
134 // Single-issue, so entry and loop tops are | |
135 // aligned on a single instruction boundary | |
136 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
675 | 137 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
0 | 138 } |
2080 | 139 if (is_niagara_plus()) { |
3854 | 140 if (has_blk_init() && UseTLAB && |
141 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | |
142 // Use BIS instruction for TLAB allocation prefetch. | |
143 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); | |
144 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { | |
145 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); | |
146 } | |
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147 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
3854 | 148 // Use smaller prefetch distance with BIS |
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149 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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150 } |
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151 } |
3854 | 152 if (is_T4()) { |
153 // Double number of prefetched cache lines on T4 | |
154 // since L2 cache line size is smaller (32 bytes). | |
155 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { | |
156 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); | |
157 } | |
158 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { | |
159 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); | |
160 } | |
161 } | |
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162 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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163 // Use different prefetch distance without BIS |
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164 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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165 } |
3854 | 166 if (AllocatePrefetchInstr == 1) { |
167 // Need a space at the end of TLAB for BIS since it | |
168 // will fault when accessing memory outside of heap. | |
169 | |
170 // +1 for rounding up to next cache line, +1 to be safe | |
171 int lines = AllocatePrefetchLines + 2; | |
172 int step_size = AllocatePrefetchStepSize; | |
173 int distance = AllocatePrefetchDistance; | |
174 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; | |
175 } | |
0 | 176 } |
177 #endif | |
178 } | |
179 | |
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180 // Use hardware population count instruction if available. |
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181 if (has_hardware_popc()) { |
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182 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
675 | 183 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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184 } |
3839 | 185 } else if (UsePopCountInstruction) { |
186 warning("POPC instruction is not available on this CPU"); | |
187 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
188 } | |
189 | |
190 // T4 and newer Sparc cpus have new compare and branch instruction. | |
191 if (has_cbcond()) { | |
192 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
193 FLAG_SET_DEFAULT(UseCBCond, true); | |
194 } | |
195 } else if (UseCBCond) { | |
196 warning("CBCOND instruction is not available on this CPU"); | |
197 FLAG_SET_DEFAULT(UseCBCond, false); | |
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198 } |
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199 |
3892 | 200 assert(BlockZeroingLowLimit > 0, "invalid value"); |
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201 if (has_block_zeroing() && cache_line_size > 0) { |
3892 | 202 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
203 FLAG_SET_DEFAULT(UseBlockZeroing, true); | |
204 } | |
205 } else if (UseBlockZeroing) { | |
206 warning("BIS zeroing instructions are not available on this CPU"); | |
207 FLAG_SET_DEFAULT(UseBlockZeroing, false); | |
208 } | |
209 | |
3903 | 210 assert(BlockCopyLowLimit > 0, "invalid value"); |
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211 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
3903 | 212 if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
213 FLAG_SET_DEFAULT(UseBlockCopy, true); | |
214 } | |
215 } else if (UseBlockCopy) { | |
216 warning("BIS instructions are not available or expensive on this CPU"); | |
217 FLAG_SET_DEFAULT(UseBlockCopy, false); | |
218 } | |
219 | |
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220 #ifdef COMPILER2 |
3839 | 221 // T4 and newer Sparc cpus have fast RDPC. |
222 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
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223 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
3839 | 224 } |
225 | |
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226 // Currently not supported anywhere. |
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227 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
3851 | 228 |
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229 MaxVectorSize = 8; |
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230 |
3851 | 231 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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232 #endif |
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233 |
3851 | 234 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
235 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); | |
236 | |
0 | 237 char buf[512]; |
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238 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
3839 | 239 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
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240 (has_hardware_popc() ? ", popc" : ""), |
3839 | 241 (has_vis1() ? ", vis1" : ""), |
242 (has_vis2() ? ", vis2" : ""), | |
243 (has_vis3() ? ", vis3" : ""), | |
244 (has_blk_init() ? ", blk_init" : ""), | |
245 (has_cbcond() ? ", cbcond" : ""), | |
17670 | 246 (has_aes() ? ", aes" : ""), |
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247 (has_sha1() ? ", sha1" : ""), |
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248 (has_sha256() ? ", sha256" : ""), |
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249 (has_sha512() ? ", sha512" : ""), |
3839 | 250 (is_ultra3() ? ", ultra3" : ""), |
251 (is_sun4v() ? ", sun4v" : ""), | |
252 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
253 (is_sparc64() ? ", sparc64" : ""), | |
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254 (!has_hardware_mul32() ? ", no-mul32" : ""), |
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255 (!has_hardware_div32() ? ", no-div32" : ""), |
0 | 256 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
257 | |
258 // buf is started with ", " or is empty | |
259 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
260 | |
3804 | 261 // UseVIS is set to the smallest of what hardware supports and what |
262 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
263 // older UltraSparc which do not support it. | |
264 if (UseVIS > 3) UseVIS=3; | |
265 if (UseVIS < 0) UseVIS=0; | |
266 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
267 UseVIS = MIN2((intx)2,UseVIS); | |
268 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
269 UseVIS = MIN2((intx)1,UseVIS); | |
270 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
271 UseVIS = 0; | |
272 | |
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273 // SPARC T4 and above should have support for AES instructions |
17670 | 274 if (has_aes()) { |
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275 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 |
17670 | 276 if (FLAG_IS_DEFAULT(UseAES)) { |
277 FLAG_SET_DEFAULT(UseAES, true); | |
278 } | |
279 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { | |
280 FLAG_SET_DEFAULT(UseAESIntrinsics, true); | |
281 } | |
282 // we disable both the AES flags if either of them is disabled on the command line | |
283 if (!UseAES || !UseAESIntrinsics) { | |
284 FLAG_SET_DEFAULT(UseAES, false); | |
285 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
286 } | |
287 } else { | |
288 if (UseAES || UseAESIntrinsics) { | |
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289 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
17670 | 290 if (UseAES) { |
291 FLAG_SET_DEFAULT(UseAES, false); | |
292 } | |
293 if (UseAESIntrinsics) { | |
294 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
295 } | |
296 } | |
297 } | |
298 } else if (UseAES || UseAESIntrinsics) { | |
299 warning("AES instructions are not available on this CPU"); | |
300 if (UseAES) { | |
301 FLAG_SET_DEFAULT(UseAES, false); | |
302 } | |
303 if (UseAESIntrinsics) { | |
304 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | |
305 } | |
306 } | |
307 | |
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308 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
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309 if (has_sha1() || has_sha256() || has_sha512()) { |
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310 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
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311 if (FLAG_IS_DEFAULT(UseSHA)) { |
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312 FLAG_SET_DEFAULT(UseSHA, true); |
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313 } |
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314 } else { |
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315 if (UseSHA) { |
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316 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
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317 FLAG_SET_DEFAULT(UseSHA, false); |
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318 } |
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319 } |
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320 } else if (UseSHA) { |
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321 warning("SHA instructions are not available on this CPU"); |
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322 FLAG_SET_DEFAULT(UseSHA, false); |
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323 } |
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324 |
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325 if (!UseSHA) { |
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326 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
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327 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
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328 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
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329 } else { |
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330 if (has_sha1()) { |
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331 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
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332 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
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333 } |
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334 } else if (UseSHA1Intrinsics) { |
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335 warning("SHA1 instruction is not available on this CPU."); |
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336 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
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337 } |
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338 if (has_sha256()) { |
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339 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
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340 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
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341 } |
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342 } else if (UseSHA256Intrinsics) { |
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343 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); |
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344 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
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345 } |
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346 |
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347 if (has_sha512()) { |
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348 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
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349 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
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350 } |
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351 } else if (UseSHA512Intrinsics) { |
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352 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); |
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353 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
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354 } |
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355 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
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356 FLAG_SET_DEFAULT(UseSHA, false); |
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357 } |
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358 } |
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359 |
7587 | 360 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
361 (cache_line_size > ContendedPaddingWidth)) | |
362 ContendedPaddingWidth = cache_line_size; | |
363 | |
0 | 364 #ifndef PRODUCT |
365 if (PrintMiscellaneous && Verbose) { | |
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366 tty->print_cr("L2 cache line size: %u", L2_cache_line_size()); |
3854 | 367 tty->print("Allocation"); |
0 | 368 if (AllocatePrefetchStyle <= 0) { |
3854 | 369 tty->print_cr(": no prefetching"); |
0 | 370 } else { |
3854 | 371 tty->print(" prefetching: "); |
372 if (AllocatePrefetchInstr == 0) { | |
373 tty->print("PREFETCH"); | |
374 } else if (AllocatePrefetchInstr == 1) { | |
375 tty->print("BIS"); | |
376 } | |
0 | 377 if (AllocatePrefetchLines > 1) { |
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378 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
0 | 379 } else { |
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380 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
0 | 381 } |
382 } | |
383 if (PrefetchCopyIntervalInBytes > 0) { | |
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384 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
0 | 385 } |
386 if (PrefetchScanIntervalInBytes > 0) { | |
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387 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
0 | 388 } |
389 if (PrefetchFieldsAhead > 0) { | |
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390 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
0 | 391 } |
7587 | 392 if (ContendedPaddingWidth > 0) { |
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393 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
7587 | 394 } |
0 | 395 } |
396 #endif // PRODUCT | |
397 } | |
398 | |
399 void VM_Version::print_features() { | |
400 tty->print_cr("Version:%s", cpu_features()); | |
401 } | |
402 | |
403 int VM_Version::determine_features() { | |
404 if (UseV8InstrsOnly) { | |
405 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
406 return generic_v8_m; | |
407 } | |
408 | |
409 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
410 | |
411 if (features == unknown_m) { | |
412 features = generic_v9_m; | |
413 warning("Cannot recognize SPARC version. Default to V9"); | |
414 } | |
415 | |
2080 | 416 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
417 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
418 if (is_T_family(features)) { | |
0 | 419 // Happy to accomodate... |
420 } else { | |
421 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
2080 | 422 features |= T_family_m; |
0 | 423 } |
424 } else { | |
2080 | 425 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
0 | 426 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
2080 | 427 features &= ~(T_family_m | T1_model_m); |
0 | 428 } else { |
429 // Happy to accomodate... | |
430 } | |
431 } | |
432 | |
433 return features; | |
434 } | |
435 | |
436 static int saved_features = 0; | |
437 | |
438 void VM_Version::allow_all() { | |
439 saved_features = _features; | |
440 _features = all_features_m; | |
441 } | |
442 | |
443 void VM_Version::revert() { | |
444 _features = saved_features; | |
445 } | |
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446 |
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447 unsigned int VM_Version::calc_parallel_worker_threads() { |
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448 unsigned int result; |
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449 if (is_M_series()) { |
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450 // for now, use same gc thread calculation for M-series as for niagara-plus |
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451 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
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452 result = nof_parallel_worker_threads(5, 16, 8); |
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453 } else if (is_niagara_plus()) { |
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454 result = nof_parallel_worker_threads(5, 16, 8); |
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455 } else { |
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456 result = nof_parallel_worker_threads(5, 8, 8); |
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457 } |
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458 return result; |
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459 } |