Mercurial > hg > truffle
annotate src/share/vm/c1/c1_LIRAssembler.hpp @ 4966:701a83c86f28
7120481: storeStore barrier in constructor with final field
Summary: Issue storestore barrier before constructor return if the constructor write final field.
Reviewed-by: dholmes, jrose, roland, coleenp
Contributed-by: Jiangli Zhou <jiangli.zhou@oracle.com>
| author | jiangli |
|---|---|
| date | Tue, 21 Feb 2012 13:14:55 -0500 |
| parents | c124e2e7463e |
| children | da91efe96a93 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP |
| 26 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP | |
| 27 | |
| 28 #include "c1/c1_CodeStubs.hpp" | |
| 29 #include "ci/ciMethodData.hpp" | |
| 30 #include "oops/methodDataOop.hpp" | |
| 31 #include "utilities/top.hpp" | |
| 32 | |
| 0 | 33 class Compilation; |
| 34 class ScopeValue; | |
| 342 | 35 class BarrierSet; |
| 0 | 36 |
| 37 class LIR_Assembler: public CompilationResourceObj { | |
| 38 private: | |
| 39 C1_MacroAssembler* _masm; | |
| 40 CodeStubList* _slow_case_stubs; | |
| 342 | 41 BarrierSet* _bs; |
| 0 | 42 |
| 43 Compilation* _compilation; | |
| 44 FrameMap* _frame_map; | |
| 45 BlockBegin* _current_block; | |
| 46 | |
| 47 Instruction* _pending_non_safepoint; | |
| 48 int _pending_non_safepoint_offset; | |
| 49 | |
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50 Label _unwind_handler_entry; |
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51 |
| 0 | 52 #ifdef ASSERT |
| 53 BlockList _branch_target_blocks; | |
| 54 void check_no_unbound_labels(); | |
| 55 #endif | |
| 56 | |
| 57 FrameMap* frame_map() const { return _frame_map; } | |
| 58 | |
| 59 void set_current_block(BlockBegin* b) { _current_block = b; } | |
| 60 BlockBegin* current_block() const { return _current_block; } | |
| 61 | |
| 62 // non-safepoint debug info management | |
| 63 void flush_debug_info(int before_pc_offset) { | |
| 64 if (_pending_non_safepoint != NULL) { | |
| 65 if (_pending_non_safepoint_offset < before_pc_offset) | |
| 66 record_non_safepoint_debug_info(); | |
| 67 _pending_non_safepoint = NULL; | |
| 68 } | |
| 69 } | |
| 70 void process_debug_info(LIR_Op* op); | |
| 71 void record_non_safepoint_debug_info(); | |
| 72 | |
| 73 // unified bailout support | |
| 74 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
| 75 bool bailed_out() const { return compilation()->bailed_out(); } | |
| 76 | |
| 77 // code emission patterns and accessors | |
| 78 void check_codespace(); | |
| 79 bool needs_icache(ciMethod* method) const; | |
| 80 | |
| 81 // returns offset of icache check | |
| 82 int check_icache(); | |
| 83 | |
| 84 void jobject2reg(jobject o, Register reg); | |
| 85 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info); | |
| 86 | |
| 87 void emit_stubs(CodeStubList* stub_list); | |
| 88 | |
| 89 // addresses | |
| 304 | 90 Address as_Address(LIR_Address* addr); |
| 91 Address as_Address_lo(LIR_Address* addr); | |
| 92 Address as_Address_hi(LIR_Address* addr); | |
| 0 | 93 |
| 94 // debug information | |
| 1564 | 95 void add_call_info(int pc_offset, CodeEmitInfo* cinfo); |
| 0 | 96 void add_debug_info_for_branch(CodeEmitInfo* info); |
| 97 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); | |
| 98 void add_debug_info_for_div0_here(CodeEmitInfo* info); | |
| 99 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); | |
| 100 void add_debug_info_for_null_check_here(CodeEmitInfo* info); | |
| 101 | |
| 102 void set_24bit_FPU(); | |
| 103 void reset_FPU(); | |
| 104 void fpop(); | |
| 105 void fxch(int i); | |
| 106 void fld(int i); | |
| 107 void ffree(int i); | |
| 108 | |
| 109 void breakpoint(); | |
| 110 void push(LIR_Opr opr); | |
| 111 void pop(LIR_Opr opr); | |
| 112 | |
| 113 // patching | |
| 114 void append_patching_stub(PatchingStub* stub); | |
| 115 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info); | |
| 116 | |
| 117 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op); | |
| 118 | |
| 119 public: | |
| 120 LIR_Assembler(Compilation* c); | |
| 121 ~LIR_Assembler(); | |
| 122 C1_MacroAssembler* masm() const { return _masm; } | |
| 123 Compilation* compilation() const { return _compilation; } | |
| 124 ciMethod* method() const { return compilation()->method(); } | |
| 125 | |
| 126 CodeOffsets* offsets() const { return _compilation->offsets(); } | |
| 127 int code_offset() const; | |
| 128 address pc() const; | |
| 129 | |
| 130 int initial_frame_size_in_bytes(); | |
| 131 | |
| 132 // test for constants which can be encoded directly in instructions | |
| 133 static bool is_small_constant(LIR_Opr opr); | |
| 134 | |
| 135 static LIR_Opr receiverOpr(); | |
| 136 static LIR_Opr osrBufferPointer(); | |
| 137 | |
| 138 // stubs | |
| 139 void emit_slow_case_stubs(); | |
| 140 void emit_static_call_stub(); | |
| 141 void emit_code_stub(CodeStub* op); | |
| 142 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); } | |
| 143 | |
| 144 // code patterns | |
| 1204 | 145 int emit_exception_handler(); |
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146 int emit_unwind_handler(); |
| 0 | 147 void emit_exception_entries(ExceptionInfoList* info_list); |
| 1204 | 148 int emit_deopt_handler(); |
| 0 | 149 |
| 150 void emit_code(BlockList* hir); | |
| 151 void emit_block(BlockBegin* block); | |
| 152 void emit_lir_list(LIR_List* list); | |
| 153 | |
| 154 // any last minute peephole optimizations are performed here. In | |
| 155 // particular sparc uses this for delay slot filling. | |
| 156 void peephole(LIR_List* list); | |
| 157 | |
| 158 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info); | |
| 159 | |
| 160 void return_op(LIR_Opr result); | |
| 161 | |
| 162 // returns offset of poll instruction | |
| 163 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info); | |
| 164 | |
| 165 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); | |
| 166 void const2stack(LIR_Opr src, LIR_Opr dest); | |
| 2002 | 167 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide); |
| 0 | 168 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); |
| 169 void reg2reg (LIR_Opr src, LIR_Opr dest); | |
| 2002 | 170 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, |
| 171 LIR_PatchCode patch_code, CodeEmitInfo* info, | |
| 172 bool pop_fpu_stack, bool wide, bool unaligned); | |
| 0 | 173 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); |
| 174 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); | |
| 175 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, | |
| 2002 | 176 LIR_PatchCode patch_code, |
| 177 CodeEmitInfo* info, bool wide, bool unaligned); | |
| 0 | 178 |
| 179 void prefetchr (LIR_Opr src); | |
| 180 void prefetchw (LIR_Opr src); | |
| 181 | |
| 182 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp); | |
| 183 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest); | |
| 184 | |
| 185 void move_regs(Register from_reg, Register to_reg); | |
| 186 void swap_reg(Register a, Register b); | |
| 187 | |
| 188 void emit_op0(LIR_Op0* op); | |
| 189 void emit_op1(LIR_Op1* op); | |
| 190 void emit_op2(LIR_Op2* op); | |
| 191 void emit_op3(LIR_Op3* op); | |
| 192 void emit_opBranch(LIR_OpBranch* op); | |
| 193 void emit_opLabel(LIR_OpLabel* op); | |
| 194 void emit_arraycopy(LIR_OpArrayCopy* op); | |
| 195 void emit_opConvert(LIR_OpConvert* op); | |
| 196 void emit_alloc_obj(LIR_OpAllocObj* op); | |
| 197 void emit_alloc_array(LIR_OpAllocArray* op); | |
| 198 void emit_opTypeCheck(LIR_OpTypeCheck* op); | |
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199 void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null); |
| 0 | 200 void emit_compare_and_swap(LIR_OpCompareAndSwap* op); |
| 201 void emit_lock(LIR_OpLock* op); | |
| 202 void emit_call(LIR_OpJavaCall* op); | |
| 203 void emit_rtcall(LIR_OpRTCall* op); | |
| 204 void emit_profile_call(LIR_OpProfileCall* op); | |
| 205 void emit_delay(LIR_OpDelay* op); | |
| 206 | |
| 207 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); | |
| 208 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); | |
| 209 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); | |
| 210 | |
| 211 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); | |
| 212 | |
| 213 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack); | |
| 214 void move_op(LIR_Opr src, LIR_Opr result, BasicType type, | |
| 2002 | 215 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide); |
| 0 | 216 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); |
| 217 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions | |
| 218 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); | |
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219 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); |
| 0 | 220 |
| 1295 | 221 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); |
| 222 void ic_call( LIR_OpJavaCall* op); | |
| 223 void vtable_call( LIR_OpJavaCall* op); | |
| 224 | |
| 0 | 225 void osr_entry(); |
| 226 | |
| 227 void build_frame(); | |
| 228 | |
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229 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info); |
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230 void unwind_op(LIR_Opr exceptionOop); |
| 0 | 231 void monitor_address(int monitor_ix, LIR_Opr dst); |
| 232 | |
| 233 void align_backward_branch_target(); | |
| 234 void align_call(LIR_Code code); | |
| 235 | |
| 236 void negate(LIR_Opr left, LIR_Opr dest); | |
| 237 void leal(LIR_Opr left, LIR_Opr dest); | |
| 238 | |
| 239 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info); | |
| 240 | |
| 241 void membar(); | |
| 242 void membar_acquire(); | |
| 243 void membar_release(); | |
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244 void membar_loadload(); |
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245 void membar_storestore(); |
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246 void membar_loadstore(); |
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247 void membar_storeload(); |
| 0 | 248 void get_thread(LIR_Opr result); |
| 249 | |
| 250 void verify_oop_map(CodeEmitInfo* info); | |
| 251 | |
| 1972 | 252 #ifdef TARGET_ARCH_x86 |
| 253 # include "c1_LIRAssembler_x86.hpp" | |
| 254 #endif | |
| 255 #ifdef TARGET_ARCH_sparc | |
| 256 # include "c1_LIRAssembler_sparc.hpp" | |
| 257 #endif | |
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258 #ifdef TARGET_ARCH_arm |
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259 # include "c1_LIRAssembler_arm.hpp" |
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260 #endif |
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261 #ifdef TARGET_ARCH_ppc |
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262 # include "c1_LIRAssembler_ppc.hpp" |
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263 #endif |
| 1972 | 264 |
| 0 | 265 }; |
| 1972 | 266 |
| 267 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP |