Mercurial > hg > truffle
annotate src/share/vm/opto/chaitin.cpp @ 6182:765ee2d1674b
7157365: jruby/bench.bench_timeout crashes with JVM internal error
Reviewed-by: jrose, kvn
| author | twisti |
|---|---|
| date | Mon, 18 Jun 2012 15:17:30 -0700 |
| parents | 8c92982cbbc4 |
| children | 6c5b7a6becc8 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 4950 | 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "compiler/compileLog.hpp" | |
| 27 #include "compiler/oopMap.hpp" | |
| 28 #include "memory/allocation.inline.hpp" | |
| 29 #include "opto/addnode.hpp" | |
| 30 #include "opto/block.hpp" | |
| 31 #include "opto/callnode.hpp" | |
| 32 #include "opto/cfgnode.hpp" | |
| 33 #include "opto/chaitin.hpp" | |
| 34 #include "opto/coalesce.hpp" | |
| 35 #include "opto/connode.hpp" | |
| 36 #include "opto/idealGraphPrinter.hpp" | |
| 37 #include "opto/indexSet.hpp" | |
| 38 #include "opto/machnode.hpp" | |
| 39 #include "opto/memnode.hpp" | |
| 40 #include "opto/opcodes.hpp" | |
| 41 #include "opto/rootnode.hpp" | |
| 0 | 42 |
| 43 //============================================================================= | |
| 44 | |
| 45 #ifndef PRODUCT | |
| 46 void LRG::dump( ) const { | |
| 47 ttyLocker ttyl; | |
| 48 tty->print("%d ",num_regs()); | |
| 49 _mask.dump(); | |
| 50 if( _msize_valid ) { | |
| 51 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); | |
| 52 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); | |
| 53 } else { | |
| 54 tty->print(", #?(%d) ",_mask.Size()); | |
| 55 } | |
| 56 | |
| 57 tty->print("EffDeg: "); | |
| 58 if( _degree_valid ) tty->print( "%d ", _eff_degree ); | |
| 59 else tty->print("? "); | |
| 60 | |
|
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61 if( is_multidef() ) { |
| 0 | 62 tty->print("MultiDef "); |
| 63 if (_defs != NULL) { | |
| 64 tty->print("("); | |
| 65 for (int i = 0; i < _defs->length(); i++) { | |
| 66 tty->print("N%d ", _defs->at(i)->_idx); | |
| 67 } | |
| 68 tty->print(") "); | |
| 69 } | |
| 70 } | |
| 71 else if( _def == 0 ) tty->print("Dead "); | |
| 72 else tty->print("Def: N%d ",_def->_idx); | |
| 73 | |
| 74 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); | |
| 75 // Flags | |
| 76 if( _is_oop ) tty->print("Oop "); | |
| 77 if( _is_float ) tty->print("Float "); | |
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78 if( _is_vector ) tty->print("Vector "); |
| 0 | 79 if( _was_spilled1 ) tty->print("Spilled "); |
| 80 if( _was_spilled2 ) tty->print("Spilled2 "); | |
| 81 if( _direct_conflict ) tty->print("Direct_conflict "); | |
| 82 if( _fat_proj ) tty->print("Fat "); | |
| 83 if( _was_lo ) tty->print("Lo "); | |
| 84 if( _has_copy ) tty->print("Copy "); | |
| 85 if( _at_risk ) tty->print("Risk "); | |
| 86 | |
| 87 if( _must_spill ) tty->print("Must_spill "); | |
| 88 if( _is_bound ) tty->print("Bound "); | |
| 89 if( _msize_valid ) { | |
| 90 if( _degree_valid && lo_degree() ) tty->print("Trivial "); | |
| 91 } | |
| 92 | |
| 93 tty->cr(); | |
| 94 } | |
| 95 #endif | |
| 96 | |
| 97 //------------------------------score------------------------------------------ | |
| 98 // Compute score from cost and area. Low score is best to spill. | |
| 99 static double raw_score( double cost, double area ) { | |
| 100 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; | |
| 101 } | |
| 102 | |
| 103 double LRG::score() const { | |
| 104 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. | |
| 105 // Bigger area lowers score, encourages spilling this live range. | |
| 106 // Bigger cost raise score, prevents spilling this live range. | |
| 107 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer | |
| 108 // to turn a divide by a constant into a multiply by the reciprical). | |
| 109 double score = raw_score( _cost, _area); | |
| 110 | |
| 111 // Account for area. Basically, LRGs covering large areas are better | |
| 112 // to spill because more other LRGs get freed up. | |
| 113 if( _area == 0.0 ) // No area? Then no progress to spill | |
| 114 return 1e35; | |
| 115 | |
| 116 if( _was_spilled2 ) // If spilled once before, we are unlikely | |
| 117 return score + 1e30; // to make progress again. | |
| 118 | |
| 119 if( _cost >= _area*3.0 ) // Tiny area relative to cost | |
| 120 return score + 1e17; // Probably no progress to spill | |
| 121 | |
| 122 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost | |
| 123 return score + 1e10; // Likely no progress to spill | |
| 124 | |
| 125 return score; | |
| 126 } | |
| 127 | |
| 128 //------------------------------LRG_List--------------------------------------- | |
| 129 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { | |
| 130 memset( _lidxs, 0, sizeof(uint)*max ); | |
| 131 } | |
| 132 | |
| 133 void LRG_List::extend( uint nidx, uint lidx ) { | |
| 134 _nesting.check(); | |
| 135 if( nidx >= _max ) { | |
| 136 uint size = 16; | |
| 137 while( size <= nidx ) size <<=1; | |
| 138 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size ); | |
| 139 _max = size; | |
| 140 } | |
| 141 while( _cnt <= nidx ) | |
| 142 _lidxs[_cnt++] = 0; | |
| 143 _lidxs[nidx] = lidx; | |
| 144 } | |
| 145 | |
| 146 #define NUMBUCKS 3 | |
| 147 | |
| 148 //------------------------------Chaitin---------------------------------------- | |
| 149 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) | |
| 150 : PhaseRegAlloc(unique, cfg, matcher, | |
| 151 #ifndef PRODUCT | |
| 152 print_chaitin_statistics | |
| 153 #else | |
| 154 NULL | |
| 155 #endif | |
| 156 ), | |
| 157 _names(unique), _uf_map(unique), | |
| 158 _maxlrg(0), _live(0), | |
| 159 _spilled_once(Thread::current()->resource_area()), | |
| 160 _spilled_twice(Thread::current()->resource_area()), | |
| 161 _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0), | |
| 162 _oldphi(unique) | |
| 163 #ifndef PRODUCT | |
| 164 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) | |
| 165 #endif | |
| 166 { | |
| 167 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) | |
| 673 | 168 |
| 169 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq); | |
| 170 | |
| 0 | 171 uint i,j; |
| 172 // Build a list of basic blocks, sorted by frequency | |
| 173 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); | |
| 174 // Experiment with sorting strategies to speed compilation | |
| 175 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket | |
| 176 Block **buckets[NUMBUCKS]; // Array of buckets | |
| 177 uint buckcnt[NUMBUCKS]; // Array of bucket counters | |
| 178 double buckval[NUMBUCKS]; // Array of bucket value cutoffs | |
| 179 for( i = 0; i < NUMBUCKS; i++ ) { | |
| 180 buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); | |
| 181 buckcnt[i] = 0; | |
| 182 // Bump by three orders of magnitude each time | |
| 183 cutoff *= 0.001; | |
| 184 buckval[i] = cutoff; | |
| 185 for( j = 0; j < _cfg._num_blocks; j++ ) { | |
| 186 buckets[i][j] = NULL; | |
| 187 } | |
| 188 } | |
| 189 // Sort blocks into buckets | |
| 190 for( i = 0; i < _cfg._num_blocks; i++ ) { | |
| 191 for( j = 0; j < NUMBUCKS; j++ ) { | |
| 192 if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) { | |
| 193 // Assign block to end of list for appropriate bucket | |
| 194 buckets[j][buckcnt[j]++] = _cfg._blocks[i]; | |
| 195 break; // kick out of inner loop | |
| 196 } | |
| 197 } | |
| 198 } | |
| 199 // Dump buckets into final block array | |
| 200 uint blkcnt = 0; | |
| 201 for( i = 0; i < NUMBUCKS; i++ ) { | |
| 202 for( j = 0; j < buckcnt[i]; j++ ) { | |
| 203 _blks[blkcnt++] = buckets[i][j]; | |
| 204 } | |
| 205 } | |
| 206 | |
| 207 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled"); | |
| 208 } | |
| 209 | |
| 210 void PhaseChaitin::Register_Allocate() { | |
| 211 | |
| 212 // Above the OLD FP (and in registers) are the incoming arguments. Stack | |
| 213 // slots in this area are called "arg_slots". Above the NEW FP (and in | |
| 214 // registers) is the outgoing argument area; above that is the spill/temp | |
| 215 // area. These are all "frame_slots". Arg_slots start at the zero | |
| 216 // stack_slots and count up to the known arg_size. Frame_slots start at | |
| 217 // the stack_slot #arg_size and go up. After allocation I map stack | |
| 218 // slots to actual offsets. Stack-slots in the arg_slot area are biased | |
| 219 // by the frame_size; stack-slots in the frame_slot area are biased by 0. | |
| 220 | |
| 221 _trip_cnt = 0; | |
| 222 _alternate = 0; | |
| 223 _matcher._allocation_started = true; | |
| 224 | |
| 225 ResourceArea live_arena; // Arena for liveness & IFG info | |
| 226 ResourceMark rm(&live_arena); | |
| 227 | |
| 228 // Need live-ness for the IFG; need the IFG for coalescing. If the | |
| 229 // liveness is JUST for coalescing, then I can get some mileage by renaming | |
| 230 // all copy-related live ranges low and then using the max copy-related | |
| 231 // live range as a cut-off for LIVE and the IFG. In other words, I can | |
| 232 // build a subset of LIVE and IFG just for copies. | |
| 233 PhaseLive live(_cfg,_names,&live_arena); | |
| 234 | |
| 235 // Need IFG for coalescing and coloring | |
| 236 PhaseIFG ifg( &live_arena ); | |
| 237 _ifg = &ifg; | |
| 238 | |
| 239 if (C->unique() > _names.Size()) _names.extend(C->unique()-1, 0); | |
| 240 | |
| 241 // Come out of SSA world to the Named world. Assign (virtual) registers to | |
| 242 // Nodes. Use the same register for all inputs and the output of PhiNodes | |
| 243 // - effectively ending SSA form. This requires either coalescing live | |
| 244 // ranges or inserting copies. For the moment, we insert "virtual copies" | |
| 245 // - we pretend there is a copy prior to each Phi in predecessor blocks. | |
| 246 // We will attempt to coalesce such "virtual copies" before we manifest | |
| 247 // them for real. | |
| 248 de_ssa(); | |
| 249 | |
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250 #ifdef ASSERT |
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251 // Veify the graph before RA. |
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252 verify(&live_arena); |
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253 #endif |
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254 |
| 0 | 255 { |
| 256 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 257 _live = NULL; // Mark live as being not available | |
| 258 rm.reset_to_mark(); // Reclaim working storage | |
| 259 IndexSet::reset_memory(C, &live_arena); | |
| 260 ifg.init(_maxlrg); // Empty IFG | |
| 261 gather_lrg_masks( false ); // Collect LRG masks | |
| 262 live.compute( _maxlrg ); // Compute liveness | |
| 263 _live = &live; // Mark LIVE as being available | |
| 264 } | |
| 265 | |
| 266 // Base pointers are currently "used" by instructions which define new | |
| 267 // derived pointers. This makes base pointers live up to the where the | |
| 268 // derived pointer is made, but not beyond. Really, they need to be live | |
| 269 // across any GC point where the derived value is live. So this code looks | |
| 270 // at all the GC points, and "stretches" the live range of any base pointer | |
| 271 // to the GC point. | |
| 272 if( stretch_base_pointer_live_ranges(&live_arena) ) { | |
| 273 NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); ) | |
| 274 // Since some live range stretched, I need to recompute live | |
| 275 _live = NULL; | |
| 276 rm.reset_to_mark(); // Reclaim working storage | |
| 277 IndexSet::reset_memory(C, &live_arena); | |
| 278 ifg.init(_maxlrg); | |
| 279 gather_lrg_masks( false ); | |
| 280 live.compute( _maxlrg ); | |
| 281 _live = &live; | |
| 282 } | |
| 283 // Create the interference graph using virtual copies | |
| 284 build_ifg_virtual( ); // Include stack slots this time | |
| 285 | |
| 286 // Aggressive (but pessimistic) copy coalescing. | |
| 287 // This pass works on virtual copies. Any virtual copies which are not | |
| 288 // coalesced get manifested as actual copies | |
| 289 { | |
| 290 // The IFG is/was triangular. I am 'squaring it up' so Union can run | |
| 291 // faster. Union requires a 'for all' operation which is slow on the | |
| 292 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - | |
| 293 // meaning I can visit all the Nodes neighbors less than a Node in time | |
| 294 // O(# of neighbors), but I have to visit all the Nodes greater than a | |
| 295 // given Node and search them for an instance, i.e., time O(#MaxLRG)). | |
| 296 _ifg->SquareUp(); | |
| 297 | |
| 298 PhaseAggressiveCoalesce coalesce( *this ); | |
| 299 coalesce.coalesce_driver( ); | |
| 300 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do | |
| 301 // not match the Phi itself, insert a copy. | |
| 302 coalesce.insert_copies(_matcher); | |
| 303 } | |
| 304 | |
| 305 // After aggressive coalesce, attempt a first cut at coloring. | |
| 306 // To color, we need the IFG and for that we need LIVE. | |
| 307 { | |
| 308 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 309 _live = NULL; | |
| 310 rm.reset_to_mark(); // Reclaim working storage | |
| 311 IndexSet::reset_memory(C, &live_arena); | |
| 312 ifg.init(_maxlrg); | |
| 313 gather_lrg_masks( true ); | |
| 314 live.compute( _maxlrg ); | |
| 315 _live = &live; | |
| 316 } | |
| 317 | |
| 318 // Build physical interference graph | |
| 319 uint must_spill = 0; | |
| 320 must_spill = build_ifg_physical( &live_arena ); | |
| 321 // If we have a guaranteed spill, might as well spill now | |
| 322 if( must_spill ) { | |
| 323 if( !_maxlrg ) return; | |
| 324 // Bail out if unique gets too large (ie - unique > MaxNodeLimit) | |
| 325 C->check_node_count(10*must_spill, "out of nodes before split"); | |
| 326 if (C->failing()) return; | |
| 327 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere | |
| 328 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) | |
| 329 // or we failed to split | |
| 330 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); | |
| 331 if (C->failing()) return; | |
| 332 | |
| 333 NOT_PRODUCT( C->verify_graph_edges(); ) | |
| 334 | |
| 335 compact(); // Compact LRGs; return new lower max lrg | |
| 336 | |
| 337 { | |
| 338 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 339 _live = NULL; | |
| 340 rm.reset_to_mark(); // Reclaim working storage | |
| 341 IndexSet::reset_memory(C, &live_arena); | |
| 342 ifg.init(_maxlrg); // Build a new interference graph | |
| 343 gather_lrg_masks( true ); // Collect intersect mask | |
| 344 live.compute( _maxlrg ); // Compute LIVE | |
| 345 _live = &live; | |
| 346 } | |
| 347 build_ifg_physical( &live_arena ); | |
| 348 _ifg->SquareUp(); | |
| 349 _ifg->Compute_Effective_Degree(); | |
| 350 // Only do conservative coalescing if requested | |
| 351 if( OptoCoalesce ) { | |
| 352 // Conservative (and pessimistic) copy coalescing of those spills | |
| 353 PhaseConservativeCoalesce coalesce( *this ); | |
| 354 // If max live ranges greater than cutoff, don't color the stack. | |
| 355 // This cutoff can be larger than below since it is only done once. | |
| 356 coalesce.coalesce_driver( ); | |
| 357 } | |
| 358 compress_uf_map_for_nodes(); | |
| 359 | |
| 360 #ifdef ASSERT | |
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361 verify(&live_arena, true); |
| 0 | 362 #endif |
| 363 } else { | |
| 364 ifg.SquareUp(); | |
| 365 ifg.Compute_Effective_Degree(); | |
| 366 #ifdef ASSERT | |
| 367 set_was_low(); | |
| 368 #endif | |
| 369 } | |
| 370 | |
| 371 // Prepare for Simplify & Select | |
| 372 cache_lrg_info(); // Count degree of LRGs | |
| 373 | |
| 374 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 375 // LRGs of low degree are trivially colorable. | |
| 376 Simplify(); | |
| 377 | |
| 378 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 379 // Return whether or not something spills. | |
| 380 uint spills = Select( ); | |
| 381 | |
| 382 // If we spill, split and recycle the entire thing | |
| 383 while( spills ) { | |
| 384 if( _trip_cnt++ > 24 ) { | |
| 385 DEBUG_ONLY( dump_for_spill_split_recycle(); ) | |
| 386 if( _trip_cnt > 27 ) { | |
| 387 C->record_method_not_compilable("failed spill-split-recycle sanity check"); | |
| 388 return; | |
| 389 } | |
| 390 } | |
| 391 | |
| 392 if( !_maxlrg ) return; | |
| 393 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere | |
| 394 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) | |
| 395 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split"); | |
| 396 if (C->failing()) return; | |
| 397 | |
| 398 compact(); // Compact LRGs; return new lower max lrg | |
| 399 | |
| 400 // Nuke the live-ness and interference graph and LiveRanGe info | |
| 401 { | |
| 402 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 403 _live = NULL; | |
| 404 rm.reset_to_mark(); // Reclaim working storage | |
| 405 IndexSet::reset_memory(C, &live_arena); | |
| 406 ifg.init(_maxlrg); | |
| 407 | |
| 408 // Create LiveRanGe array. | |
| 409 // Intersect register masks for all USEs and DEFs | |
| 410 gather_lrg_masks( true ); | |
| 411 live.compute( _maxlrg ); | |
| 412 _live = &live; | |
| 413 } | |
| 414 must_spill = build_ifg_physical( &live_arena ); | |
| 415 _ifg->SquareUp(); | |
| 416 _ifg->Compute_Effective_Degree(); | |
| 417 | |
| 418 // Only do conservative coalescing if requested | |
| 419 if( OptoCoalesce ) { | |
| 420 // Conservative (and pessimistic) copy coalescing | |
| 421 PhaseConservativeCoalesce coalesce( *this ); | |
| 422 // Check for few live ranges determines how aggressive coalesce is. | |
| 423 coalesce.coalesce_driver( ); | |
| 424 } | |
| 425 compress_uf_map_for_nodes(); | |
| 426 #ifdef ASSERT | |
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427 verify(&live_arena, true); |
| 0 | 428 #endif |
| 429 cache_lrg_info(); // Count degree of LRGs | |
| 430 | |
| 431 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 432 // LRGs of low degree are trivially colorable. | |
| 433 Simplify(); | |
| 434 | |
| 435 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 436 // Return whether or not something spills. | |
| 437 spills = Select( ); | |
| 438 } | |
| 439 | |
| 440 // Count number of Simplify-Select trips per coloring success. | |
| 441 _allocator_attempts += _trip_cnt + 1; | |
| 442 _allocator_successes += 1; | |
| 443 | |
| 444 // Peephole remove copies | |
| 445 post_allocate_copy_removal(); | |
| 446 | |
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447 #ifdef ASSERT |
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448 // Veify the graph after RA. |
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449 verify(&live_arena); |
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450 #endif |
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451 |
| 0 | 452 // max_reg is past the largest *register* used. |
| 453 // Convert that to a frame_slot number. | |
| 454 if( _max_reg <= _matcher._new_SP ) | |
| 455 _framesize = C->out_preserve_stack_slots(); | |
| 456 else _framesize = _max_reg -_matcher._new_SP; | |
| 457 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); | |
| 458 | |
| 459 // This frame must preserve the required fp alignment | |
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460 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); |
| 0 | 461 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" ); |
| 462 #ifndef PRODUCT | |
| 463 _total_framesize += _framesize; | |
| 464 if( (int)_framesize > _max_framesize ) | |
| 465 _max_framesize = _framesize; | |
| 466 #endif | |
| 467 | |
| 468 // Convert CISC spills | |
| 469 fixup_spills(); | |
| 470 | |
| 471 // Log regalloc results | |
| 472 CompileLog* log = Compile::current()->log(); | |
| 473 if (log != NULL) { | |
| 474 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); | |
| 475 } | |
| 476 | |
| 477 if (C->failing()) return; | |
| 478 | |
| 479 NOT_PRODUCT( C->verify_graph_edges(); ) | |
| 480 | |
| 481 // Move important info out of the live_arena to longer lasting storage. | |
| 482 alloc_node_regs(_names.Size()); | |
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483 for (uint i=0; i < _names.Size(); i++) { |
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484 if (_names[i]) { // Live range associated with Node? |
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485 LRG &lrg = lrgs(_names[i]); |
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486 if (!lrg.alive()) { |
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487 _node_regs[i].set_bad(); |
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488 } else if (lrg.num_regs() == 1) { |
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489 _node_regs[i].set1(lrg.reg()); |
| 0 | 490 } else { // Must be a register-pair |
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491 if (!lrg._fat_proj) { // Must be aligned adjacent register pair |
| 0 | 492 // Live ranges record the highest register in their mask. |
| 493 // We want the low register for the AD file writer's convenience. | |
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494 _node_regs[i].set2( OptoReg::add(lrg.reg(),(1-lrg.num_regs())) ); |
| 0 | 495 } else { // Misaligned; extract 2 bits |
| 496 OptoReg::Name hi = lrg.reg(); // Get hi register | |
| 497 lrg.Remove(hi); // Yank from mask | |
| 498 int lo = lrg.mask().find_first_elem(); // Find lo | |
| 499 _node_regs[i].set_pair( hi, lo ); | |
| 500 } | |
| 501 } | |
| 502 if( lrg._is_oop ) _node_oops.set(i); | |
| 503 } else { | |
| 504 _node_regs[i].set_bad(); | |
| 505 } | |
| 506 } | |
| 507 | |
| 508 // Done! | |
| 509 _live = NULL; | |
| 510 _ifg = NULL; | |
| 511 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope | |
| 512 } | |
| 513 | |
| 514 //------------------------------de_ssa----------------------------------------- | |
| 515 void PhaseChaitin::de_ssa() { | |
| 516 // Set initial Names for all Nodes. Most Nodes get the virtual register | |
| 517 // number. A few get the ZERO live range number. These do not | |
| 518 // get allocated, but instead rely on correct scheduling to ensure that | |
| 519 // only one instance is simultaneously live at a time. | |
| 520 uint lr_counter = 1; | |
| 521 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | |
| 522 Block *b = _cfg._blocks[i]; | |
| 523 uint cnt = b->_nodes.size(); | |
| 524 | |
| 525 // Handle all the normal Nodes in the block | |
| 526 for( uint j = 0; j < cnt; j++ ) { | |
| 527 Node *n = b->_nodes[j]; | |
| 528 // Pre-color to the zero live range, or pick virtual register | |
| 529 const RegMask &rm = n->out_RegMask(); | |
| 530 _names.map( n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0 ); | |
| 531 } | |
| 532 } | |
| 533 // Reset the Union-Find mapping to be identity | |
| 534 reset_uf_map(lr_counter); | |
| 535 } | |
| 536 | |
| 537 | |
| 538 //------------------------------gather_lrg_masks------------------------------- | |
| 539 // Gather LiveRanGe information, including register masks. Modification of | |
| 540 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. | |
| 541 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { | |
| 542 | |
| 543 // Nail down the frame pointer live range | |
| 544 uint fp_lrg = n2lidx(_cfg._root->in(1)->in(TypeFunc::FramePtr)); | |
| 545 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite | |
| 546 | |
| 547 // For all blocks | |
| 548 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | |
| 549 Block *b = _cfg._blocks[i]; | |
| 550 | |
| 551 // For all instructions | |
| 552 for( uint j = 1; j < b->_nodes.size(); j++ ) { | |
| 553 Node *n = b->_nodes[j]; | |
| 554 uint input_edge_start =1; // Skip control most nodes | |
| 555 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base(); | |
| 556 uint idx = n->is_Copy(); | |
| 557 | |
| 558 // Get virtual register number, same as LiveRanGe index | |
| 559 uint vreg = n2lidx(n); | |
| 560 LRG &lrg = lrgs(vreg); | |
| 561 if( vreg ) { // No vreg means un-allocable (e.g. memory) | |
| 562 | |
| 563 // Collect has-copy bit | |
| 564 if( idx ) { | |
| 565 lrg._has_copy = 1; | |
| 566 uint clidx = n2lidx(n->in(idx)); | |
| 567 LRG ©_src = lrgs(clidx); | |
| 568 copy_src._has_copy = 1; | |
| 569 } | |
| 570 | |
| 571 // Check for float-vs-int live range (used in register-pressure | |
| 572 // calculations) | |
| 573 const Type *n_type = n->bottom_type(); | |
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574 if (n_type->is_floatingpoint()) |
| 0 | 575 lrg._is_float = 1; |
| 576 | |
| 577 // Check for twice prior spilling. Once prior spilling might have | |
| 578 // spilled 'soft', 2nd prior spill should have spilled 'hard' and | |
| 579 // further spilling is unlikely to make progress. | |
| 580 if( _spilled_once.test(n->_idx) ) { | |
| 581 lrg._was_spilled1 = 1; | |
| 582 if( _spilled_twice.test(n->_idx) ) | |
| 583 lrg._was_spilled2 = 1; | |
| 584 } | |
| 585 | |
| 586 #ifndef PRODUCT | |
| 587 if (trace_spilling() && lrg._def != NULL) { | |
| 588 // collect defs for MultiDef printing | |
| 589 if (lrg._defs == NULL) { | |
| 1685 | 590 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL); |
| 0 | 591 lrg._defs->append(lrg._def); |
| 592 } | |
| 593 lrg._defs->append(n); | |
| 594 } | |
| 595 #endif | |
| 596 | |
| 597 // Check for a single def LRG; these can spill nicely | |
| 598 // via rematerialization. Flag as NULL for no def found | |
| 599 // yet, or 'n' for single def or -1 for many defs. | |
| 600 lrg._def = lrg._def ? NodeSentinel : n; | |
| 601 | |
| 602 // Limit result register mask to acceptable registers | |
| 603 const RegMask &rm = n->out_RegMask(); | |
| 604 lrg.AND( rm ); | |
| 605 | |
| 606 int ireg = n->ideal_reg(); | |
| 607 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, | |
| 608 "oops must be in Op_RegP's" ); | |
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609 |
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610 // Check for vector live range (only if vector register is used). |
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611 // On SPARC vector uses RegD which could be misaligned so it is not |
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612 // processes as vector in RA. |
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613 if (RegMask::is_vector(ireg)) |
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614 lrg._is_vector = 1; |
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615 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
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616 "vector must be in vector registers"); |
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617 |
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618 // Check for bound register masks |
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619 const RegMask &lrgmask = lrg.mask(); |
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620 if (lrgmask.is_bound(ireg)) |
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621 lrg._is_bound = 1; |
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622 |
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623 // Check for maximum frequency value |
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624 if (lrg._maxfreq < b->_freq) |
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625 lrg._maxfreq = b->_freq; |
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626 |
| 0 | 627 // Check for oop-iness, or long/double |
| 628 // Check for multi-kill projection | |
| 629 switch( ireg ) { | |
| 630 case MachProjNode::fat_proj: | |
| 631 // Fat projections have size equal to number of registers killed | |
| 632 lrg.set_num_regs(rm.Size()); | |
| 633 lrg.set_reg_pressure(lrg.num_regs()); | |
| 634 lrg._fat_proj = 1; | |
| 635 lrg._is_bound = 1; | |
| 636 break; | |
| 637 case Op_RegP: | |
| 638 #ifdef _LP64 | |
| 639 lrg.set_num_regs(2); // Size is 2 stack words | |
| 640 #else | |
| 641 lrg.set_num_regs(1); // Size is 1 stack word | |
| 642 #endif | |
| 643 // Register pressure is tracked relative to the maximum values | |
| 644 // suggested for that platform, INTPRESSURE and FLOATPRESSURE, | |
| 645 // and relative to other types which compete for the same regs. | |
| 646 // | |
| 647 // The following table contains suggested values based on the | |
| 648 // architectures as defined in each .ad file. | |
| 649 // INTPRESSURE and FLOATPRESSURE may be tuned differently for | |
| 650 // compile-speed or performance. | |
| 651 // Note1: | |
| 652 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 | |
| 653 // since .ad registers are defined as high and low halves. | |
| 654 // These reg_pressure values remain compatible with the code | |
| 655 // in is_high_pressure() which relates get_invalid_mask_size(), | |
| 656 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. | |
| 657 // Note2: | |
| 658 // SPARC -d32 has 24 registers available for integral values, | |
| 659 // but only 10 of these are safe for 64-bit longs. | |
| 660 // Using set_reg_pressure(2) for both int and long means | |
| 661 // the allocator will believe it can fit 26 longs into | |
| 662 // registers. Using 2 for longs and 1 for ints means the | |
| 663 // allocator will attempt to put 52 integers into registers. | |
| 664 // The settings below limit this problem to methods with | |
| 665 // many long values which are being run on 32-bit SPARC. | |
| 666 // | |
| 667 // ------------------- reg_pressure -------------------- | |
| 668 // Each entry is reg_pressure_per_value,number_of_regs | |
| 669 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE | |
| 670 // IA32 2 1 1 1 1 6 6 | |
| 671 // IA64 1 1 1 1 1 50 41 | |
| 672 // SPARC 2 2 2 2 2 48 (24) 52 (26) | |
| 673 // SPARCV9 2 2 2 2 2 48 (24) 52 (26) | |
| 674 // AMD64 1 1 1 1 1 14 15 | |
| 675 // ----------------------------------------------------- | |
| 676 #if defined(SPARC) | |
| 677 lrg.set_reg_pressure(2); // use for v9 as well | |
| 678 #else | |
| 679 lrg.set_reg_pressure(1); // normally one value per register | |
| 680 #endif | |
| 681 if( n_type->isa_oop_ptr() ) { | |
| 682 lrg._is_oop = 1; | |
| 683 } | |
| 684 break; | |
| 685 case Op_RegL: // Check for long or double | |
| 686 case Op_RegD: | |
| 687 lrg.set_num_regs(2); | |
| 688 // Define platform specific register pressure | |
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689 #if defined(SPARC) || defined(ARM) |
| 0 | 690 lrg.set_reg_pressure(2); |
| 691 #elif defined(IA32) | |
| 692 if( ireg == Op_RegL ) { | |
| 693 lrg.set_reg_pressure(2); | |
| 694 } else { | |
| 695 lrg.set_reg_pressure(1); | |
| 696 } | |
| 697 #else | |
| 698 lrg.set_reg_pressure(1); // normally one value per register | |
| 699 #endif | |
| 700 // If this def of a double forces a mis-aligned double, | |
| 701 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 702 // AND changes how we count interferences. A mis-aligned | |
| 703 // double can interfere with TWO aligned pairs, or effectively | |
| 704 // FOUR registers! | |
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705 if (rm.is_misaligned_pair()) { |
| 0 | 706 lrg._fat_proj = 1; |
| 707 lrg._is_bound = 1; | |
| 708 } | |
| 709 break; | |
| 710 case Op_RegF: | |
| 711 case Op_RegI: | |
|
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712 case Op_RegN: |
| 0 | 713 case Op_RegFlags: |
| 714 case 0: // not an ideal register | |
| 715 lrg.set_num_regs(1); | |
| 716 #ifdef SPARC | |
| 717 lrg.set_reg_pressure(2); | |
| 718 #else | |
| 719 lrg.set_reg_pressure(1); | |
| 720 #endif | |
| 721 break; | |
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722 case Op_VecS: |
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723 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); |
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724 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); |
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725 lrg.set_num_regs(RegMask::SlotsPerVecS); |
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726 lrg.set_reg_pressure(1); |
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727 break; |
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728 case Op_VecD: |
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729 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); |
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730 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); |
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731 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); |
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732 lrg.set_num_regs(RegMask::SlotsPerVecD); |
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733 lrg.set_reg_pressure(1); |
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734 break; |
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735 case Op_VecX: |
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736 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); |
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737 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); |
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738 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); |
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739 lrg.set_num_regs(RegMask::SlotsPerVecX); |
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740 lrg.set_reg_pressure(1); |
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741 break; |
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742 case Op_VecY: |
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743 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); |
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744 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); |
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745 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); |
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746 lrg.set_num_regs(RegMask::SlotsPerVecY); |
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747 lrg.set_reg_pressure(1); |
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748 break; |
| 0 | 749 default: |
| 750 ShouldNotReachHere(); | |
| 751 } | |
| 752 } | |
| 753 | |
| 754 // Now do the same for inputs | |
| 755 uint cnt = n->req(); | |
| 756 // Setup for CISC SPILLING | |
| 757 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; | |
| 758 if( UseCISCSpill && after_aggressive ) { | |
| 759 inp = n->cisc_operand(); | |
| 760 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) | |
| 761 // Convert operand number to edge index number | |
| 762 inp = n->as_Mach()->operand_index(inp); | |
| 763 } | |
| 764 // Prepare register mask for each input | |
| 765 for( uint k = input_edge_start; k < cnt; k++ ) { | |
| 766 uint vreg = n2lidx(n->in(k)); | |
| 767 if( !vreg ) continue; | |
| 768 | |
| 769 // If this instruction is CISC Spillable, add the flags | |
| 770 // bit to its appropriate input | |
| 771 if( UseCISCSpill && after_aggressive && inp == k ) { | |
| 772 #ifndef PRODUCT | |
| 773 if( TraceCISCSpill ) { | |
| 774 tty->print(" use_cisc_RegMask: "); | |
| 775 n->dump(); | |
| 776 } | |
| 777 #endif | |
| 778 n->as_Mach()->use_cisc_RegMask(); | |
| 779 } | |
| 780 | |
| 781 LRG &lrg = lrgs(vreg); | |
| 782 // // Testing for floating point code shape | |
| 783 // Node *test = n->in(k); | |
| 784 // if( test->is_Mach() ) { | |
| 785 // MachNode *m = test->as_Mach(); | |
| 786 // int op = m->ideal_Opcode(); | |
| 787 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { | |
| 788 // int zzz = 1; | |
| 789 // } | |
| 790 // } | |
| 791 | |
| 792 // Limit result register mask to acceptable registers. | |
| 793 // Do not limit registers from uncommon uses before | |
| 794 // AggressiveCoalesce. This effectively pre-virtual-splits | |
| 795 // around uncommon uses of common defs. | |
| 796 const RegMask &rm = n->in_RegMask(k); | |
| 797 if( !after_aggressive && | |
| 798 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) { | |
| 799 // Since we are BEFORE aggressive coalesce, leave the register | |
| 800 // mask untrimmed by the call. This encourages more coalescing. | |
| 801 // Later, AFTER aggressive, this live range will have to spill | |
| 802 // but the spiller handles slow-path calls very nicely. | |
| 803 } else { | |
| 804 lrg.AND( rm ); | |
| 805 } | |
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806 |
| 0 | 807 // Check for bound register masks |
| 808 const RegMask &lrgmask = lrg.mask(); | |
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809 int kreg = n->in(k)->ideal_reg(); |
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810 bool is_vect = RegMask::is_vector(kreg); |
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811 assert(n->in(k)->bottom_type()->isa_vect() == NULL || |
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812 is_vect || kreg == Op_RegD, |
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813 "vector must be in vector registers"); |
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814 if (lrgmask.is_bound(kreg)) |
| 0 | 815 lrg._is_bound = 1; |
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816 |
| 0 | 817 // If this use of a double forces a mis-aligned double, |
| 818 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 819 // AND changes how we count interferences. A mis-aligned | |
| 820 // double can interfere with TWO aligned pairs, or effectively | |
| 821 // FOUR registers! | |
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822 #ifdef ASSERT |
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823 if (is_vect) { |
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824 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); |
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825 assert(!lrg._fat_proj, "sanity"); |
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826 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); |
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827 } |
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828 #endif |
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829 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { |
| 0 | 830 lrg._fat_proj = 1; |
| 831 lrg._is_bound = 1; | |
| 832 } | |
| 833 // if the LRG is an unaligned pair, we will have to spill | |
| 834 // so clear the LRG's register mask if it is not already spilled | |
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835 if (!is_vect && !n->is_SpillCopy() && |
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836 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
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837 lrgmask.is_misaligned_pair()) { |
| 0 | 838 lrg.Clear(); |
| 839 } | |
| 840 | |
| 841 // Check for maximum frequency value | |
| 842 if( lrg._maxfreq < b->_freq ) | |
| 843 lrg._maxfreq = b->_freq; | |
| 844 | |
| 845 } // End for all allocated inputs | |
| 846 } // end for all instructions | |
| 847 } // end for all blocks | |
| 848 | |
| 849 // Final per-liverange setup | |
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850 for (uint i2=0; i2<_maxlrg; i2++) { |
| 0 | 851 LRG &lrg = lrgs(i2); |
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852 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); |
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853 if (lrg.num_regs() > 1 && !lrg._fat_proj) { |
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854 lrg.clear_to_sets(); |
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855 } |
| 0 | 856 lrg.compute_set_mask_size(); |
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857 if (lrg.not_free()) { // Handle case where we lose from the start |
| 0 | 858 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
| 859 lrg._direct_conflict = 1; | |
| 860 } | |
| 861 lrg.set_degree(0); // no neighbors in IFG yet | |
| 862 } | |
| 863 } | |
| 864 | |
| 865 //------------------------------set_was_low------------------------------------ | |
| 866 // Set the was-lo-degree bit. Conservative coalescing should not change the | |
| 867 // colorability of the graph. If any live range was of low-degree before | |
| 868 // coalescing, it should Simplify. This call sets the was-lo-degree bit. | |
| 869 // The bit is checked in Simplify. | |
| 870 void PhaseChaitin::set_was_low() { | |
| 871 #ifdef ASSERT | |
| 872 for( uint i = 1; i < _maxlrg; i++ ) { | |
| 873 int size = lrgs(i).num_regs(); | |
| 874 uint old_was_lo = lrgs(i)._was_lo; | |
| 875 lrgs(i)._was_lo = 0; | |
| 876 if( lrgs(i).lo_degree() ) { | |
| 877 lrgs(i)._was_lo = 1; // Trivially of low degree | |
| 878 } else { // Else check the Brigg's assertion | |
| 879 // Brigg's observation is that the lo-degree neighbors of a | |
| 880 // hi-degree live range will not interfere with the color choices | |
| 881 // of said hi-degree live range. The Simplify reverse-stack-coloring | |
| 882 // order takes care of the details. Hence you do not have to count | |
| 883 // low-degree neighbors when determining if this guy colors. | |
| 884 int briggs_degree = 0; | |
| 885 IndexSet *s = _ifg->neighbors(i); | |
| 886 IndexSetIterator elements(s); | |
| 887 uint lidx; | |
| 888 while((lidx = elements.next()) != 0) { | |
| 889 if( !lrgs(lidx).lo_degree() ) | |
| 890 briggs_degree += MAX2(size,lrgs(lidx).num_regs()); | |
| 891 } | |
| 892 if( briggs_degree < lrgs(i).degrees_of_freedom() ) | |
| 893 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion | |
| 894 } | |
| 895 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); | |
| 896 } | |
| 897 #endif | |
| 898 } | |
| 899 | |
| 900 #define REGISTER_CONSTRAINED 16 | |
| 901 | |
| 902 //------------------------------cache_lrg_info--------------------------------- | |
| 903 // Compute cost/area ratio, in case we spill. Build the lo-degree list. | |
| 904 void PhaseChaitin::cache_lrg_info( ) { | |
| 905 | |
| 906 for( uint i = 1; i < _maxlrg; i++ ) { | |
| 907 LRG &lrg = lrgs(i); | |
| 908 | |
| 909 // Check for being of low degree: means we can be trivially colored. | |
| 910 // Low degree, dead or must-spill guys just get to simplify right away | |
| 911 if( lrg.lo_degree() || | |
| 912 !lrg.alive() || | |
| 913 lrg._must_spill ) { | |
| 914 // Split low degree list into those guys that must get a | |
| 915 // register and those that can go to register or stack. | |
| 916 // The idea is LRGs that can go register or stack color first when | |
| 917 // they have a good chance of getting a register. The register-only | |
| 918 // lo-degree live ranges always get a register. | |
| 919 OptoReg::Name hi_reg = lrg.mask().find_last_elem(); | |
| 920 if( OptoReg::is_stack(hi_reg)) { // Can go to stack? | |
| 921 lrg._next = _lo_stk_degree; | |
| 922 _lo_stk_degree = i; | |
| 923 } else { | |
| 924 lrg._next = _lo_degree; | |
| 925 _lo_degree = i; | |
| 926 } | |
| 927 } else { // Else high degree | |
| 928 lrgs(_hi_degree)._prev = i; | |
| 929 lrg._next = _hi_degree; | |
| 930 lrg._prev = 0; | |
| 931 _hi_degree = i; | |
| 932 } | |
| 933 } | |
| 934 } | |
| 935 | |
| 936 //------------------------------Pre-Simplify----------------------------------- | |
| 937 // Simplify the IFG by removing LRGs of low degree that have NO copies | |
| 938 void PhaseChaitin::Pre_Simplify( ) { | |
| 939 | |
| 940 // Warm up the lo-degree no-copy list | |
| 941 int lo_no_copy = 0; | |
| 942 for( uint i = 1; i < _maxlrg; i++ ) { | |
| 943 if( (lrgs(i).lo_degree() && !lrgs(i)._has_copy) || | |
| 944 !lrgs(i).alive() || | |
| 945 lrgs(i)._must_spill ) { | |
| 946 lrgs(i)._next = lo_no_copy; | |
| 947 lo_no_copy = i; | |
| 948 } | |
| 949 } | |
| 950 | |
| 951 while( lo_no_copy ) { | |
| 952 uint lo = lo_no_copy; | |
| 953 lo_no_copy = lrgs(lo)._next; | |
| 954 int size = lrgs(lo).num_regs(); | |
| 955 | |
| 956 // Put the simplified guy on the simplified list. | |
| 957 lrgs(lo)._next = _simplified; | |
| 958 _simplified = lo; | |
| 959 | |
| 960 // Yank this guy from the IFG. | |
| 961 IndexSet *adj = _ifg->remove_node( lo ); | |
| 962 | |
| 963 // If any neighbors' degrees fall below their number of | |
| 964 // allowed registers, then put that neighbor on the low degree | |
| 965 // list. Note that 'degree' can only fall and 'numregs' is | |
| 966 // unchanged by this action. Thus the two are equal at most once, | |
| 967 // so LRGs hit the lo-degree worklists at most once. | |
| 968 IndexSetIterator elements(adj); | |
| 969 uint neighbor; | |
| 970 while ((neighbor = elements.next()) != 0) { | |
| 971 LRG *n = &lrgs(neighbor); | |
| 972 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); | |
| 973 | |
| 974 // Check for just becoming of-low-degree | |
| 975 if( n->just_lo_degree() && !n->_has_copy ) { | |
| 976 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 977 // Put on lo-degree list | |
| 978 n->_next = lo_no_copy; | |
| 979 lo_no_copy = neighbor; | |
| 980 } | |
| 981 } | |
| 982 } // End of while lo-degree no_copy worklist not empty | |
| 983 | |
| 984 // No more lo-degree no-copy live ranges to simplify | |
| 985 } | |
| 986 | |
| 987 //------------------------------Simplify--------------------------------------- | |
| 988 // Simplify the IFG by removing LRGs of low degree. | |
| 989 void PhaseChaitin::Simplify( ) { | |
| 990 | |
| 991 while( 1 ) { // Repeat till simplified it all | |
| 992 // May want to explore simplifying lo_degree before _lo_stk_degree. | |
| 993 // This might result in more spills coloring into registers during | |
| 994 // Select(). | |
| 995 while( _lo_degree || _lo_stk_degree ) { | |
| 996 // If possible, pull from lo_stk first | |
| 997 uint lo; | |
| 998 if( _lo_degree ) { | |
| 999 lo = _lo_degree; | |
| 1000 _lo_degree = lrgs(lo)._next; | |
| 1001 } else { | |
| 1002 lo = _lo_stk_degree; | |
| 1003 _lo_stk_degree = lrgs(lo)._next; | |
| 1004 } | |
| 1005 | |
| 1006 // Put the simplified guy on the simplified list. | |
| 1007 lrgs(lo)._next = _simplified; | |
| 1008 _simplified = lo; | |
| 1009 // If this guy is "at risk" then mark his current neighbors | |
| 1010 if( lrgs(lo)._at_risk ) { | |
| 1011 IndexSetIterator elements(_ifg->neighbors(lo)); | |
| 1012 uint datum; | |
| 1013 while ((datum = elements.next()) != 0) { | |
| 1014 lrgs(datum)._risk_bias = lo; | |
| 1015 } | |
| 1016 } | |
| 1017 | |
| 1018 // Yank this guy from the IFG. | |
| 1019 IndexSet *adj = _ifg->remove_node( lo ); | |
| 1020 | |
| 1021 // If any neighbors' degrees fall below their number of | |
| 1022 // allowed registers, then put that neighbor on the low degree | |
| 1023 // list. Note that 'degree' can only fall and 'numregs' is | |
| 1024 // unchanged by this action. Thus the two are equal at most once, | |
| 1025 // so LRGs hit the lo-degree worklist at most once. | |
| 1026 IndexSetIterator elements(adj); | |
| 1027 uint neighbor; | |
| 1028 while ((neighbor = elements.next()) != 0) { | |
| 1029 LRG *n = &lrgs(neighbor); | |
| 1030 #ifdef ASSERT | |
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1031 if( VerifyOpto || VerifyRegisterAllocator ) { |
| 0 | 1032 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); |
| 1033 } | |
| 1034 #endif | |
| 1035 | |
| 1036 // Check for just becoming of-low-degree just counting registers. | |
| 1037 // _must_spill live ranges are already on the low degree list. | |
| 1038 if( n->just_lo_degree() && !n->_must_spill ) { | |
| 1039 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 1040 // Pull from hi-degree list | |
| 1041 uint prev = n->_prev; | |
| 1042 uint next = n->_next; | |
| 1043 if( prev ) lrgs(prev)._next = next; | |
| 1044 else _hi_degree = next; | |
| 1045 lrgs(next)._prev = prev; | |
| 1046 n->_next = _lo_degree; | |
| 1047 _lo_degree = neighbor; | |
| 1048 } | |
| 1049 } | |
| 1050 } // End of while lo-degree/lo_stk_degree worklist not empty | |
| 1051 | |
| 1052 // Check for got everything: is hi-degree list empty? | |
| 1053 if( !_hi_degree ) break; | |
| 1054 | |
| 1055 // Time to pick a potential spill guy | |
| 1056 uint lo_score = _hi_degree; | |
| 1057 double score = lrgs(lo_score).score(); | |
| 1058 double area = lrgs(lo_score)._area; | |
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1059 double cost = lrgs(lo_score)._cost; |
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1060 bool bound = lrgs(lo_score)._is_bound; |
| 0 | 1061 |
| 1062 // Find cheapest guy | |
| 1063 debug_only( int lo_no_simplify=0; ); | |
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1064 for( uint i = _hi_degree; i; i = lrgs(i)._next ) { |
| 0 | 1065 assert( !(*_ifg->_yanked)[i], "" ); |
| 1066 // It's just vaguely possible to move hi-degree to lo-degree without | |
| 1067 // going through a just-lo-degree stage: If you remove a double from | |
| 1068 // a float live range it's degree will drop by 2 and you can skip the | |
| 1069 // just-lo-degree stage. It's very rare (shows up after 5000+ methods | |
| 1070 // in -Xcomp of Java2Demo). So just choose this guy to simplify next. | |
| 1071 if( lrgs(i).lo_degree() ) { | |
| 1072 lo_score = i; | |
| 1073 break; | |
| 1074 } | |
| 1075 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); | |
| 1076 double iscore = lrgs(i).score(); | |
| 1077 double iarea = lrgs(i)._area; | |
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1078 double icost = lrgs(i)._cost; |
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1079 bool ibound = lrgs(i)._is_bound; |
| 0 | 1080 |
| 1081 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area | |
| 1082 // wins. Ties happen because all live ranges in question have spilled | |
| 1083 // a few times before and the spill-score adds a huge number which | |
| 1084 // washes out the low order bits. We are choosing the lesser of 2 | |
| 1085 // evils; in this case pick largest area to spill. | |
|
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1086 // Ties also happen when live ranges are defined and used only inside |
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1087 // one block. In which case their area is 0 and score set to max. |
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1088 // In such case choose bound live range over unbound to free registers |
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1089 // or with smaller cost to spill. |
| 0 | 1090 if( iscore < score || |
|
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1091 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) || |
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1092 (iscore == score && iarea == area && |
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1093 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) { |
| 0 | 1094 lo_score = i; |
| 1095 score = iscore; | |
| 1096 area = iarea; | |
|
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1097 cost = icost; |
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1098 bound = ibound; |
| 0 | 1099 } |
| 1100 } | |
| 1101 LRG *lo_lrg = &lrgs(lo_score); | |
| 1102 // The live range we choose for spilling is either hi-degree, or very | |
| 1103 // rarely it can be low-degree. If we choose a hi-degree live range | |
| 1104 // there better not be any lo-degree choices. | |
| 1105 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); | |
| 1106 | |
| 1107 // Pull from hi-degree list | |
| 1108 uint prev = lo_lrg->_prev; | |
| 1109 uint next = lo_lrg->_next; | |
| 1110 if( prev ) lrgs(prev)._next = next; | |
| 1111 else _hi_degree = next; | |
| 1112 lrgs(next)._prev = prev; | |
| 1113 // Jam him on the lo-degree list, despite his high degree. | |
| 1114 // Maybe he'll get a color, and maybe he'll spill. | |
| 1115 // Only Select() will know. | |
| 1116 lrgs(lo_score)._at_risk = true; | |
| 1117 _lo_degree = lo_score; | |
| 1118 lo_lrg->_next = 0; | |
| 1119 | |
| 1120 } // End of while not simplified everything | |
| 1121 | |
| 1122 } | |
| 1123 | |
| 1124 //------------------------------bias_color------------------------------------- | |
| 1125 // Choose a color using the biasing heuristic | |
| 1126 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { | |
| 1127 | |
| 1128 // Check for "at_risk" LRG's | |
| 1129 uint risk_lrg = Find(lrg._risk_bias); | |
| 1130 if( risk_lrg != 0 ) { | |
| 1131 // Walk the colored neighbors of the "at_risk" candidate | |
| 1132 // Choose a color which is both legal and already taken by a neighbor | |
| 1133 // of the "at_risk" candidate in order to improve the chances of the | |
| 1134 // "at_risk" candidate of coloring | |
| 1135 IndexSetIterator elements(_ifg->neighbors(risk_lrg)); | |
| 1136 uint datum; | |
| 1137 while ((datum = elements.next()) != 0) { | |
| 1138 OptoReg::Name reg = lrgs(datum).reg(); | |
| 1139 // If this LRG's register is legal for us, choose it | |
| 1140 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE && | |
| 1141 lrg.mask().Member(OptoReg::add(reg,-chunk)) && | |
| 1142 (lrg.num_regs()==1 || // either size 1 | |
| 1143 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs) | |
| 1144 return reg; | |
| 1145 } | |
| 1146 } | |
| 1147 | |
| 1148 uint copy_lrg = Find(lrg._copy_bias); | |
| 1149 if( copy_lrg != 0 ) { | |
| 1150 // If he has a color, | |
| 1151 if( !(*(_ifg->_yanked))[copy_lrg] ) { | |
| 1152 OptoReg::Name reg = lrgs(copy_lrg).reg(); | |
| 1153 // And it is legal for you, | |
| 1154 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE && | |
| 1155 lrg.mask().Member(OptoReg::add(reg,-chunk)) && | |
| 1156 (lrg.num_regs()==1 || // either size 1 | |
| 1157 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs) | |
| 1158 return reg; | |
| 1159 } else if( chunk == 0 ) { | |
| 1160 // Choose a color which is legal for him | |
| 1161 RegMask tempmask = lrg.mask(); | |
| 1162 tempmask.AND(lrgs(copy_lrg).mask()); | |
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1163 tempmask.clear_to_sets(lrg.num_regs()); |
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1164 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); |
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1165 if (OptoReg::is_valid(reg)) |
| 0 | 1166 return reg; |
| 1167 } | |
| 1168 } | |
| 1169 | |
| 1170 // If no bias info exists, just go with the register selection ordering | |
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1171 if (lrg._is_vector || lrg.num_regs() == 2) { |
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1172 // Find an aligned set |
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1173 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); |
| 0 | 1174 } |
| 1175 | |
| 1176 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate | |
| 1177 // copy removal to remove many more copies, by preventing a just-assigned | |
| 1178 // register from being repeatedly assigned. | |
| 1179 OptoReg::Name reg = lrg.mask().find_first_elem(); | |
| 1180 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { | |
| 1181 // This 'Remove; find; Insert' idiom is an expensive way to find the | |
| 1182 // SECOND element in the mask. | |
| 1183 lrg.Remove(reg); | |
| 1184 OptoReg::Name reg2 = lrg.mask().find_first_elem(); | |
| 1185 lrg.Insert(reg); | |
| 1186 if( OptoReg::is_reg(reg2)) | |
| 1187 reg = reg2; | |
| 1188 } | |
| 1189 return OptoReg::add( reg, chunk ); | |
| 1190 } | |
| 1191 | |
| 1192 //------------------------------choose_color----------------------------------- | |
| 1193 // Choose a color in the current chunk | |
| 1194 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { | |
| 1195 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); | |
| 1196 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); | |
| 1197 | |
| 1198 if( lrg.num_regs() == 1 || // Common Case | |
| 1199 !lrg._fat_proj ) // Aligned+adjacent pairs ok | |
| 1200 // Use a heuristic to "bias" the color choice | |
| 1201 return bias_color(lrg, chunk); | |
| 1202 | |
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1203 assert(!lrg._is_vector, "should be not vector here" ); |
| 0 | 1204 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
| 1205 | |
| 1206 // Fat-proj case or misaligned double argument. | |
| 1207 assert(lrg.compute_mask_size() == lrg.num_regs() || | |
| 1208 lrg.num_regs() == 2,"fat projs exactly color" ); | |
| 1209 assert( !chunk, "always color in 1st chunk" ); | |
| 1210 // Return the highest element in the set. | |
| 1211 return lrg.mask().find_last_elem(); | |
| 1212 } | |
| 1213 | |
| 1214 //------------------------------Select----------------------------------------- | |
| 1215 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted | |
| 1216 // in reverse order of removal. As long as nothing of hi-degree was yanked, | |
| 1217 // everything going back is guaranteed a color. Select that color. If some | |
| 1218 // hi-degree LRG cannot get a color then we record that we must spill. | |
| 1219 uint PhaseChaitin::Select( ) { | |
| 1220 uint spill_reg = LRG::SPILL_REG; | |
| 1221 _max_reg = OptoReg::Name(0); // Past max register used | |
| 1222 while( _simplified ) { | |
| 1223 // Pull next LRG from the simplified list - in reverse order of removal | |
| 1224 uint lidx = _simplified; | |
| 1225 LRG *lrg = &lrgs(lidx); | |
| 1226 _simplified = lrg->_next; | |
| 1227 | |
| 1228 | |
| 1229 #ifndef PRODUCT | |
| 1230 if (trace_spilling()) { | |
| 1231 ttyLocker ttyl; | |
| 1232 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), | |
| 1233 lrg->degrees_of_freedom()); | |
| 1234 lrg->dump(); | |
| 1235 } | |
| 1236 #endif | |
| 1237 | |
| 1238 // Re-insert into the IFG | |
| 1239 _ifg->re_insert(lidx); | |
| 1240 if( !lrg->alive() ) continue; | |
| 1241 // capture allstackedness flag before mask is hacked | |
| 1242 const int is_allstack = lrg->mask().is_AllStack(); | |
| 1243 | |
| 1244 // Yeah, yeah, yeah, I know, I know. I can refactor this | |
| 1245 // to avoid the GOTO, although the refactored code will not | |
| 1246 // be much clearer. We arrive here IFF we have a stack-based | |
| 1247 // live range that cannot color in the current chunk, and it | |
| 1248 // has to move into the next free stack chunk. | |
| 1249 int chunk = 0; // Current chunk is first chunk | |
| 1250 retry_next_chunk: | |
| 1251 | |
| 1252 // Remove neighbor colors | |
| 1253 IndexSet *s = _ifg->neighbors(lidx); | |
| 1254 | |
| 1255 debug_only(RegMask orig_mask = lrg->mask();) | |
| 1256 IndexSetIterator elements(s); | |
| 1257 uint neighbor; | |
| 1258 while ((neighbor = elements.next()) != 0) { | |
| 1259 // Note that neighbor might be a spill_reg. In this case, exclusion | |
| 1260 // of its color will be a no-op, since the spill_reg chunk is in outer | |
| 1261 // space. Also, if neighbor is in a different chunk, this exclusion | |
| 1262 // will be a no-op. (Later on, if lrg runs out of possible colors in | |
| 1263 // its chunk, a new chunk of color may be tried, in which case | |
| 1264 // examination of neighbors is started again, at retry_next_chunk.) | |
| 1265 LRG &nlrg = lrgs(neighbor); | |
| 1266 OptoReg::Name nreg = nlrg.reg(); | |
| 1267 // Only subtract masks in the same chunk | |
| 1268 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { | |
| 1269 #ifndef PRODUCT | |
| 1270 uint size = lrg->mask().Size(); | |
| 1271 RegMask rm = lrg->mask(); | |
| 1272 #endif | |
| 1273 lrg->SUBTRACT(nlrg.mask()); | |
| 1274 #ifndef PRODUCT | |
| 1275 if (trace_spilling() && lrg->mask().Size() != size) { | |
| 1276 ttyLocker ttyl; | |
| 1277 tty->print("L%d ", lidx); | |
| 1278 rm.dump(); | |
| 1279 tty->print(" intersected L%d ", neighbor); | |
| 1280 nlrg.mask().dump(); | |
| 1281 tty->print(" removed "); | |
| 1282 rm.SUBTRACT(lrg->mask()); | |
| 1283 rm.dump(); | |
| 1284 tty->print(" leaving "); | |
| 1285 lrg->mask().dump(); | |
| 1286 tty->cr(); | |
| 1287 } | |
| 1288 #endif | |
| 1289 } | |
| 1290 } | |
| 1291 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); | |
| 1292 // Aligned pairs need aligned masks | |
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1293 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
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1294 if (lrg->num_regs() > 1 && !lrg->_fat_proj) { |
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1295 lrg->clear_to_sets(); |
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1296 } |
| 0 | 1297 |
| 1298 // Check if a color is available and if so pick the color | |
| 1299 OptoReg::Name reg = choose_color( *lrg, chunk ); | |
| 1300 #ifdef SPARC | |
| 1301 debug_only(lrg->compute_set_mask_size()); | |
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1302 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
| 0 | 1303 #endif |
| 1304 | |
| 1305 //--------------- | |
| 1306 // If we fail to color and the AllStack flag is set, trigger | |
| 1307 // a chunk-rollover event | |
| 1308 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { | |
| 1309 // Bump register mask up to next stack chunk | |
| 1310 chunk += RegMask::CHUNK_SIZE; | |
| 1311 lrg->Set_All(); | |
| 1312 | |
| 1313 goto retry_next_chunk; | |
| 1314 } | |
| 1315 | |
| 1316 //--------------- | |
| 1317 // Did we get a color? | |
| 1318 else if( OptoReg::is_valid(reg)) { | |
| 1319 #ifndef PRODUCT | |
| 1320 RegMask avail_rm = lrg->mask(); | |
| 1321 #endif | |
| 1322 | |
| 1323 // Record selected register | |
| 1324 lrg->set_reg(reg); | |
| 1325 | |
| 1326 if( reg >= _max_reg ) // Compute max register limit | |
| 1327 _max_reg = OptoReg::add(reg,1); | |
| 1328 // Fold reg back into normal space | |
| 1329 reg = OptoReg::add(reg,-chunk); | |
| 1330 | |
| 1331 // If the live range is not bound, then we actually had some choices | |
| 1332 // to make. In this case, the mask has more bits in it than the colors | |
| 605 | 1333 // chosen. Restrict the mask to just what was picked. |
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1334 int n_regs = lrg->num_regs(); |
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1335 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
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1336 if (n_regs == 1 || !lrg->_fat_proj) { |
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1337 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity"); |
| 0 | 1338 lrg->Clear(); // Clear the mask |
| 1339 lrg->Insert(reg); // Set regmask to match selected reg | |
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1340 // For vectors and pairs, also insert the low bit of the pair |
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1341 for (int i = 1; i < n_regs; i++) |
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1342 lrg->Insert(OptoReg::add(reg,-i)); |
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1343 lrg->set_mask_size(n_regs); |
| 0 | 1344 } else { // Else fatproj |
| 1345 // mask must be equal to fatproj bits, by definition | |
| 1346 } | |
| 1347 #ifndef PRODUCT | |
| 1348 if (trace_spilling()) { | |
| 1349 ttyLocker ttyl; | |
| 1350 tty->print("L%d selected ", lidx); | |
| 1351 lrg->mask().dump(); | |
| 1352 tty->print(" from "); | |
| 1353 avail_rm.dump(); | |
| 1354 tty->cr(); | |
| 1355 } | |
| 1356 #endif | |
| 1357 // Note that reg is the highest-numbered register in the newly-bound mask. | |
| 1358 } // end color available case | |
| 1359 | |
| 1360 //--------------- | |
| 1361 // Live range is live and no colors available | |
| 1362 else { | |
| 1363 assert( lrg->alive(), "" ); | |
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1364 assert( !lrg->_fat_proj || lrg->is_multidef() || |
| 0 | 1365 lrg->_def->outcnt() > 0, "fat_proj cannot spill"); |
| 1366 assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); | |
| 1367 | |
| 1368 // Assign the special spillreg register | |
| 1369 lrg->set_reg(OptoReg::Name(spill_reg++)); | |
| 1370 // Do not empty the regmask; leave mask_size lying around | |
| 1371 // for use during Spilling | |
| 1372 #ifndef PRODUCT | |
| 1373 if( trace_spilling() ) { | |
| 1374 ttyLocker ttyl; | |
| 1375 tty->print("L%d spilling with neighbors: ", lidx); | |
| 1376 s->dump(); | |
| 1377 debug_only(tty->print(" original mask: ")); | |
| 1378 debug_only(orig_mask.dump()); | |
| 1379 dump_lrg(lidx); | |
| 1380 } | |
| 1381 #endif | |
| 1382 } // end spill case | |
| 1383 | |
| 1384 } | |
| 1385 | |
| 1386 return spill_reg-LRG::SPILL_REG; // Return number of spills | |
| 1387 } | |
| 1388 | |
| 1389 | |
| 1390 //------------------------------copy_was_spilled------------------------------- | |
| 1391 // Copy 'was_spilled'-edness from the source Node to the dst Node. | |
| 1392 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { | |
| 1393 if( _spilled_once.test(src->_idx) ) { | |
| 1394 _spilled_once.set(dst->_idx); | |
| 1395 lrgs(Find(dst))._was_spilled1 = 1; | |
| 1396 if( _spilled_twice.test(src->_idx) ) { | |
| 1397 _spilled_twice.set(dst->_idx); | |
| 1398 lrgs(Find(dst))._was_spilled2 = 1; | |
| 1399 } | |
| 1400 } | |
| 1401 } | |
| 1402 | |
| 1403 //------------------------------set_was_spilled-------------------------------- | |
| 1404 // Set the 'spilled_once' or 'spilled_twice' flag on a node. | |
| 1405 void PhaseChaitin::set_was_spilled( Node *n ) { | |
| 1406 if( _spilled_once.test_set(n->_idx) ) | |
| 1407 _spilled_twice.set(n->_idx); | |
| 1408 } | |
| 1409 | |
| 1410 //------------------------------fixup_spills----------------------------------- | |
| 1411 // Convert Ideal spill instructions into proper FramePtr + offset Loads and | |
| 1412 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. | |
| 1413 void PhaseChaitin::fixup_spills() { | |
| 1414 // This function does only cisc spill work. | |
| 1415 if( !UseCISCSpill ) return; | |
| 1416 | |
| 1417 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) | |
| 1418 | |
| 1419 // Grab the Frame Pointer | |
| 1420 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr); | |
| 1421 | |
| 1422 // For all blocks | |
| 1423 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | |
| 1424 Block *b = _cfg._blocks[i]; | |
| 1425 | |
| 1426 // For all instructions in block | |
| 1427 uint last_inst = b->end_idx(); | |
| 1428 for( uint j = 1; j <= last_inst; j++ ) { | |
| 1429 Node *n = b->_nodes[j]; | |
| 1430 | |
| 1431 // Dead instruction??? | |
| 1432 assert( n->outcnt() != 0 ||// Nothing dead after post alloc | |
| 1433 C->top() == n || // Or the random TOP node | |
| 1434 n->is_Proj(), // Or a fat-proj kill node | |
| 1435 "No dead instructions after post-alloc" ); | |
| 1436 | |
| 1437 int inp = n->cisc_operand(); | |
| 1438 if( inp != AdlcVMDeps::Not_cisc_spillable ) { | |
| 1439 // Convert operand number to edge index number | |
| 1440 MachNode *mach = n->as_Mach(); | |
| 1441 inp = mach->operand_index(inp); | |
| 1442 Node *src = n->in(inp); // Value to load or store | |
| 1443 LRG &lrg_cisc = lrgs( Find_const(src) ); | |
| 1444 OptoReg::Name src_reg = lrg_cisc.reg(); | |
| 1445 // Doubles record the HIGH register of an adjacent pair. | |
| 1446 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); | |
| 1447 if( OptoReg::is_stack(src_reg) ) { // If input is on stack | |
| 1448 // This is a CISC Spill, get stack offset and construct new node | |
| 1449 #ifndef PRODUCT | |
| 1450 if( TraceCISCSpill ) { | |
| 1451 tty->print(" reg-instr: "); | |
| 1452 n->dump(); | |
| 1453 } | |
| 1454 #endif | |
| 1455 int stk_offset = reg2offset(src_reg); | |
| 1456 // Bailout if we might exceed node limit when spilling this instruction | |
| 1457 C->check_node_count(0, "out of nodes fixing spills"); | |
| 1458 if (C->failing()) return; | |
| 1459 // Transform node | |
| 1460 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach(); | |
| 1461 cisc->set_req(inp,fp); // Base register is frame pointer | |
| 1462 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { | |
| 1463 assert( cisc->oper_input_base() == 2, "Only adding one edge"); | |
| 1464 cisc->ins_req(1,src); // Requires a memory edge | |
| 1465 } | |
| 1466 b->_nodes.map(j,cisc); // Insert into basic block | |
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1467 n->subsume_by(cisc); // Correct graph |
| 0 | 1468 // |
| 1469 ++_used_cisc_instructions; | |
| 1470 #ifndef PRODUCT | |
| 1471 if( TraceCISCSpill ) { | |
| 1472 tty->print(" cisc-instr: "); | |
| 1473 cisc->dump(); | |
| 1474 } | |
| 1475 #endif | |
| 1476 } else { | |
| 1477 #ifndef PRODUCT | |
| 1478 if( TraceCISCSpill ) { | |
| 1479 tty->print(" using reg-instr: "); | |
| 1480 n->dump(); | |
| 1481 } | |
| 1482 #endif | |
| 1483 ++_unused_cisc_instructions; // input can be on stack | |
| 1484 } | |
| 1485 } | |
| 1486 | |
| 1487 } // End of for all instructions | |
| 1488 | |
| 1489 } // End of for all blocks | |
| 1490 } | |
| 1491 | |
| 1492 //------------------------------find_base_for_derived-------------------------- | |
| 1493 // Helper to stretch above; recursively discover the base Node for a | |
| 1494 // given derived Node. Easy for AddP-related machine nodes, but needs | |
| 1495 // to be recursive for derived Phis. | |
| 1496 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { | |
| 1497 // See if already computed; if so return it | |
| 1498 if( derived_base_map[derived->_idx] ) | |
| 1499 return derived_base_map[derived->_idx]; | |
| 1500 | |
| 1501 // See if this happens to be a base. | |
| 1502 // NOTE: we use TypePtr instead of TypeOopPtr because we can have | |
| 1503 // pointers derived from NULL! These are always along paths that | |
| 1504 // can't happen at run-time but the optimizer cannot deduce it so | |
| 1505 // we have to handle it gracefully. | |
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1506 assert(!derived->bottom_type()->isa_narrowoop() || |
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1507 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1508 const TypePtr *tj = derived->bottom_type()->isa_ptr(); |
| 1509 // If its an OOP with a non-zero offset, then it is derived. | |
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1510 if( tj == NULL || tj->_offset == 0 ) { |
| 0 | 1511 derived_base_map[derived->_idx] = derived; |
| 1512 return derived; | |
| 1513 } | |
| 1514 // Derived is NULL+offset? Base is NULL! | |
| 1515 if( derived->is_Con() ) { | |
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1516 Node *base = _matcher.mach_null(); |
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1517 assert(base != NULL, "sanity"); |
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1518 if (base->in(0) == NULL) { |
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1519 // Initialize it once and make it shared: |
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1520 // set control to _root and place it into Start block |
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1521 // (where top() node is placed). |
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1522 base->init_req(0, _cfg._root); |
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1523 Block *startb = _cfg._bbs[C->top()->_idx]; |
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1524 startb->_nodes.insert(startb->find_node(C->top()), base ); |
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1525 _cfg._bbs.map( base->_idx, startb ); |
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1526 assert (n2lidx(base) == 0, "should not have LRG yet"); |
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1527 } |
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1528 if (n2lidx(base) == 0) { |
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1529 new_lrg(base, maxlrg++); |
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1530 } |
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1531 assert(base->in(0) == _cfg._root && |
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1532 _cfg._bbs[base->_idx] == _cfg._bbs[C->top()->_idx], "base NULL should be shared"); |
| 0 | 1533 derived_base_map[derived->_idx] = base; |
| 1534 return base; | |
| 1535 } | |
| 1536 | |
| 1537 // Check for AddP-related opcodes | |
| 1538 if( !derived->is_Phi() ) { | |
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1539 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg("but is: %s", derived->Name())); |
| 0 | 1540 Node *base = derived->in(AddPNode::Base); |
| 1541 derived_base_map[derived->_idx] = base; | |
| 1542 return base; | |
| 1543 } | |
| 1544 | |
| 1545 // Recursively find bases for Phis. | |
| 1546 // First check to see if we can avoid a base Phi here. | |
| 1547 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); | |
| 1548 uint i; | |
| 1549 for( i = 2; i < derived->req(); i++ ) | |
| 1550 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) | |
| 1551 break; | |
| 1552 // Went to the end without finding any different bases? | |
| 1553 if( i == derived->req() ) { // No need for a base Phi here | |
| 1554 derived_base_map[derived->_idx] = base; | |
| 1555 return base; | |
| 1556 } | |
| 1557 | |
| 1558 // Now we see we need a base-Phi here to merge the bases | |
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1559 const Type *t = base->bottom_type(); |
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1560 base = new (C, derived->req()) PhiNode( derived->in(0), t ); |
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1561 for( i = 1; i < derived->req(); i++ ) { |
| 0 | 1562 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); |
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1563 t = t->meet(base->in(i)->bottom_type()); |
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1564 } |
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1565 base->as_Phi()->set_type(t); |
| 0 | 1566 |
| 1567 // Search the current block for an existing base-Phi | |
| 1568 Block *b = _cfg._bbs[derived->_idx]; | |
| 1569 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi | |
| 1570 Node *phi = b->_nodes[i]; | |
| 1571 if( !phi->is_Phi() ) { // Found end of Phis with no match? | |
| 1572 b->_nodes.insert( i, base ); // Must insert created Phi here as base | |
| 1573 _cfg._bbs.map( base->_idx, b ); | |
| 1574 new_lrg(base,maxlrg++); | |
| 1575 break; | |
| 1576 } | |
| 1577 // See if Phi matches. | |
| 1578 uint j; | |
| 1579 for( j = 1; j < base->req(); j++ ) | |
| 1580 if( phi->in(j) != base->in(j) && | |
| 1581 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs | |
| 1582 break; | |
| 1583 if( j == base->req() ) { // All inputs match? | |
| 1584 base = phi; // Then use existing 'phi' and drop 'base' | |
| 1585 break; | |
| 1586 } | |
| 1587 } | |
| 1588 | |
| 1589 | |
| 1590 // Cache info for later passes | |
| 1591 derived_base_map[derived->_idx] = base; | |
| 1592 return base; | |
| 1593 } | |
| 1594 | |
| 1595 | |
| 1596 //------------------------------stretch_base_pointer_live_ranges--------------- | |
| 1597 // At each Safepoint, insert extra debug edges for each pair of derived value/ | |
| 1598 // base pointer that is live across the Safepoint for oopmap building. The | |
| 1599 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the | |
| 1600 // required edge set. | |
| 1601 bool PhaseChaitin::stretch_base_pointer_live_ranges( ResourceArea *a ) { | |
| 1602 int must_recompute_live = false; | |
| 1603 uint maxlrg = _maxlrg; | |
| 1604 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); | |
| 1605 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); | |
| 1606 | |
| 1607 // For all blocks in RPO do... | |
| 1608 for( uint i=0; i<_cfg._num_blocks; i++ ) { | |
| 1609 Block *b = _cfg._blocks[i]; | |
| 1610 // Note use of deep-copy constructor. I cannot hammer the original | |
| 1611 // liveout bits, because they are needed by the following coalesce pass. | |
| 1612 IndexSet liveout(_live->live(b)); | |
| 1613 | |
| 1614 for( uint j = b->end_idx() + 1; j > 1; j-- ) { | |
| 1615 Node *n = b->_nodes[j-1]; | |
| 1616 | |
| 1617 // Pre-split compares of loop-phis. Loop-phis form a cycle we would | |
| 1618 // like to see in the same register. Compare uses the loop-phi and so | |
| 1619 // extends its live range BUT cannot be part of the cycle. If this | |
| 1620 // extended live range overlaps with the update of the loop-phi value | |
| 1621 // we need both alive at the same time -- which requires at least 1 | |
| 1622 // copy. But because Intel has only 2-address registers we end up with | |
| 1623 // at least 2 copies, one before the loop-phi update instruction and | |
| 1624 // one after. Instead we split the input to the compare just after the | |
| 1625 // phi. | |
| 1626 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { | |
| 1627 Node *phi = n->in(1); | |
| 1628 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { | |
| 1629 Block *phi_block = _cfg._bbs[phi->_idx]; | |
| 1630 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) { | |
| 1631 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; | |
| 1632 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); | |
| 1633 insert_proj( phi_block, 1, spill, maxlrg++ ); | |
| 1634 n->set_req(1,spill); | |
| 1635 must_recompute_live = true; | |
| 1636 } | |
| 1637 } | |
| 1638 } | |
| 1639 | |
| 1640 // Get value being defined | |
| 1641 uint lidx = n2lidx(n); | |
| 1642 if( lidx && lidx < _maxlrg /* Ignore the occasional brand-new live range */) { | |
| 1643 // Remove from live-out set | |
| 1644 liveout.remove(lidx); | |
| 1645 | |
| 1646 // Copies do not define a new value and so do not interfere. | |
| 1647 // Remove the copies source from the liveout set before interfering. | |
| 1648 uint idx = n->is_Copy(); | |
| 1649 if( idx ) liveout.remove( n2lidx(n->in(idx)) ); | |
| 1650 } | |
| 1651 | |
| 1652 // Found a safepoint? | |
| 1653 JVMState *jvms = n->jvms(); | |
| 1654 if( jvms ) { | |
| 1655 // Now scan for a live derived pointer | |
| 1656 IndexSetIterator elements(&liveout); | |
| 1657 uint neighbor; | |
| 1658 while ((neighbor = elements.next()) != 0) { | |
| 1659 // Find reaching DEF for base and derived values | |
| 1660 // This works because we are still in SSA during this call. | |
| 1661 Node *derived = lrgs(neighbor)._def; | |
| 1662 const TypePtr *tj = derived->bottom_type()->isa_ptr(); | |
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1663 assert(!derived->bottom_type()->isa_narrowoop() || |
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1664 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1665 // If its an OOP with a non-zero offset, then it is derived. |
| 1666 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { | |
| 1667 Node *base = find_base_for_derived( derived_base_map, derived, maxlrg ); | |
| 1668 assert( base->_idx < _names.Size(), "" ); | |
| 1669 // Add reaching DEFs of derived pointer and base pointer as a | |
| 1670 // pair of inputs | |
| 1671 n->add_req( derived ); | |
| 1672 n->add_req( base ); | |
| 1673 | |
| 1674 // See if the base pointer is already live to this point. | |
| 1675 // Since I'm working on the SSA form, live-ness amounts to | |
| 1676 // reaching def's. So if I find the base's live range then | |
| 1677 // I know the base's def reaches here. | |
| 1678 if( (n2lidx(base) >= _maxlrg ||// (Brand new base (hence not live) or | |
| 1679 !liveout.member( n2lidx(base) ) ) && // not live) AND | |
| 1680 (n2lidx(base) > 0) && // not a constant | |
| 1681 _cfg._bbs[base->_idx] != b ) { // base not def'd in blk) | |
| 1682 // Base pointer is not currently live. Since I stretched | |
| 1683 // the base pointer to here and it crosses basic-block | |
| 1684 // boundaries, the global live info is now incorrect. | |
| 1685 // Recompute live. | |
| 1686 must_recompute_live = true; | |
| 1687 } // End of if base pointer is not live to debug info | |
| 1688 } | |
| 1689 } // End of scan all live data for derived ptrs crossing GC point | |
| 1690 } // End of if found a GC point | |
| 1691 | |
| 1692 // Make all inputs live | |
| 1693 if( !n->is_Phi() ) { // Phi function uses come from prior block | |
| 1694 for( uint k = 1; k < n->req(); k++ ) { | |
| 1695 uint lidx = n2lidx(n->in(k)); | |
| 1696 if( lidx < _maxlrg ) | |
| 1697 liveout.insert( lidx ); | |
| 1698 } | |
| 1699 } | |
| 1700 | |
| 1701 } // End of forall instructions in block | |
| 1702 liveout.clear(); // Free the memory used by liveout. | |
| 1703 | |
| 1704 } // End of forall blocks | |
| 1705 _maxlrg = maxlrg; | |
| 1706 | |
| 1707 // If I created a new live range I need to recompute live | |
| 1708 if( maxlrg != _ifg->_maxlrg ) | |
| 1709 must_recompute_live = true; | |
| 1710 | |
| 1711 return must_recompute_live != 0; | |
| 1712 } | |
| 1713 | |
| 1714 | |
| 1715 //------------------------------add_reference---------------------------------- | |
| 1716 // Extend the node to LRG mapping | |
| 1717 void PhaseChaitin::add_reference( const Node *node, const Node *old_node ) { | |
| 1718 _names.extend( node->_idx, n2lidx(old_node) ); | |
| 1719 } | |
| 1720 | |
| 1721 //------------------------------dump------------------------------------------- | |
| 1722 #ifndef PRODUCT | |
| 1723 void PhaseChaitin::dump( const Node *n ) const { | |
| 1724 uint r = (n->_idx < _names.Size() ) ? Find_const(n) : 0; | |
| 1725 tty->print("L%d",r); | |
| 1726 if( r && n->Opcode() != Op_Phi ) { | |
| 1727 if( _node_regs ) { // Got a post-allocation copy of allocation? | |
| 1728 tty->print("["); | |
| 1729 OptoReg::Name second = get_reg_second(n); | |
| 1730 if( OptoReg::is_valid(second) ) { | |
| 1731 if( OptoReg::is_reg(second) ) | |
| 1732 tty->print("%s:",Matcher::regName[second]); | |
| 1733 else | |
| 1734 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); | |
| 1735 } | |
| 1736 OptoReg::Name first = get_reg_first(n); | |
| 1737 if( OptoReg::is_reg(first) ) | |
| 1738 tty->print("%s]",Matcher::regName[first]); | |
| 1739 else | |
| 1740 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); | |
| 1741 } else | |
| 1742 n->out_RegMask().dump(); | |
| 1743 } | |
| 1744 tty->print("/N%d\t",n->_idx); | |
| 1745 tty->print("%s === ", n->Name()); | |
| 1746 uint k; | |
| 1747 for( k = 0; k < n->req(); k++) { | |
| 1748 Node *m = n->in(k); | |
| 1749 if( !m ) tty->print("_ "); | |
| 1750 else { | |
| 1751 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0; | |
| 1752 tty->print("L%d",r); | |
| 1753 // Data MultiNode's can have projections with no real registers. | |
| 1754 // Don't die while dumping them. | |
| 1755 int op = n->Opcode(); | |
| 1756 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { | |
| 1757 if( _node_regs ) { | |
| 1758 tty->print("["); | |
| 1759 OptoReg::Name second = get_reg_second(n->in(k)); | |
| 1760 if( OptoReg::is_valid(second) ) { | |
| 1761 if( OptoReg::is_reg(second) ) | |
| 1762 tty->print("%s:",Matcher::regName[second]); | |
| 1763 else | |
| 1764 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1765 reg2offset_unchecked(second)); | |
| 1766 } | |
| 1767 OptoReg::Name first = get_reg_first(n->in(k)); | |
| 1768 if( OptoReg::is_reg(first) ) | |
| 1769 tty->print("%s]",Matcher::regName[first]); | |
| 1770 else | |
| 1771 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1772 reg2offset_unchecked(first)); | |
| 1773 } else | |
| 1774 n->in_RegMask(k).dump(); | |
| 1775 } | |
| 1776 tty->print("/N%d ",m->_idx); | |
| 1777 } | |
| 1778 } | |
| 1779 if( k < n->len() && n->in(k) ) tty->print("| "); | |
| 1780 for( ; k < n->len(); k++ ) { | |
| 1781 Node *m = n->in(k); | |
| 1782 if( !m ) break; | |
| 1783 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0; | |
| 1784 tty->print("L%d",r); | |
| 1785 tty->print("/N%d ",m->_idx); | |
| 1786 } | |
| 1787 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); | |
| 1788 else n->dump_spec(tty); | |
| 1789 if( _spilled_once.test(n->_idx ) ) { | |
| 1790 tty->print(" Spill_1"); | |
| 1791 if( _spilled_twice.test(n->_idx ) ) | |
| 1792 tty->print(" Spill_2"); | |
| 1793 } | |
| 1794 tty->print("\n"); | |
| 1795 } | |
| 1796 | |
| 1797 void PhaseChaitin::dump( const Block * b ) const { | |
| 1798 b->dump_head( &_cfg._bbs ); | |
| 1799 | |
| 1800 // For all instructions | |
| 1801 for( uint j = 0; j < b->_nodes.size(); j++ ) | |
| 1802 dump(b->_nodes[j]); | |
| 1803 // Print live-out info at end of block | |
| 1804 if( _live ) { | |
| 1805 tty->print("Liveout: "); | |
| 1806 IndexSet *live = _live->live(b); | |
| 1807 IndexSetIterator elements(live); | |
| 1808 tty->print("{"); | |
| 1809 uint i; | |
| 1810 while ((i = elements.next()) != 0) { | |
| 1811 tty->print("L%d ", Find_const(i)); | |
| 1812 } | |
| 1813 tty->print_cr("}"); | |
| 1814 } | |
| 1815 tty->print("\n"); | |
| 1816 } | |
| 1817 | |
| 1818 void PhaseChaitin::dump() const { | |
| 1819 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", | |
| 1820 _matcher._new_SP, _framesize ); | |
| 1821 | |
| 1822 // For all blocks | |
| 1823 for( uint i = 0; i < _cfg._num_blocks; i++ ) | |
| 1824 dump(_cfg._blocks[i]); | |
| 1825 // End of per-block dump | |
| 1826 tty->print("\n"); | |
| 1827 | |
| 1828 if (!_ifg) { | |
| 1829 tty->print("(No IFG.)\n"); | |
| 1830 return; | |
| 1831 } | |
| 1832 | |
| 1833 // Dump LRG array | |
| 1834 tty->print("--- Live RanGe Array ---\n"); | |
| 1835 for(uint i2 = 1; i2 < _maxlrg; i2++ ) { | |
| 1836 tty->print("L%d: ",i2); | |
| 1837 if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( ); | |
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1838 else tty->print_cr("new LRG"); |
| 0 | 1839 } |
| 1840 tty->print_cr(""); | |
| 1841 | |
| 1842 // Dump lo-degree list | |
| 1843 tty->print("Lo degree: "); | |
| 1844 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) | |
| 1845 tty->print("L%d ",i3); | |
| 1846 tty->print_cr(""); | |
| 1847 | |
| 1848 // Dump lo-stk-degree list | |
| 1849 tty->print("Lo stk degree: "); | |
| 1850 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) | |
| 1851 tty->print("L%d ",i4); | |
| 1852 tty->print_cr(""); | |
| 1853 | |
| 1854 // Dump lo-degree list | |
| 1855 tty->print("Hi degree: "); | |
| 1856 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) | |
| 1857 tty->print("L%d ",i5); | |
| 1858 tty->print_cr(""); | |
| 1859 } | |
| 1860 | |
| 1861 //------------------------------dump_degree_lists------------------------------ | |
| 1862 void PhaseChaitin::dump_degree_lists() const { | |
| 1863 // Dump lo-degree list | |
| 1864 tty->print("Lo degree: "); | |
| 1865 for( uint i = _lo_degree; i; i = lrgs(i)._next ) | |
| 1866 tty->print("L%d ",i); | |
| 1867 tty->print_cr(""); | |
| 1868 | |
| 1869 // Dump lo-stk-degree list | |
| 1870 tty->print("Lo stk degree: "); | |
| 1871 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) | |
| 1872 tty->print("L%d ",i2); | |
| 1873 tty->print_cr(""); | |
| 1874 | |
| 1875 // Dump lo-degree list | |
| 1876 tty->print("Hi degree: "); | |
| 1877 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) | |
| 1878 tty->print("L%d ",i3); | |
| 1879 tty->print_cr(""); | |
| 1880 } | |
| 1881 | |
| 1882 //------------------------------dump_simplified-------------------------------- | |
| 1883 void PhaseChaitin::dump_simplified() const { | |
| 1884 tty->print("Simplified: "); | |
| 1885 for( uint i = _simplified; i; i = lrgs(i)._next ) | |
| 1886 tty->print("L%d ",i); | |
| 1887 tty->print_cr(""); | |
| 1888 } | |
| 1889 | |
| 1890 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { | |
| 1891 if ((int)reg < 0) | |
| 1892 sprintf(buf, "<OptoReg::%d>", (int)reg); | |
| 1893 else if (OptoReg::is_reg(reg)) | |
| 1894 strcpy(buf, Matcher::regName[reg]); | |
| 1895 else | |
| 1896 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1897 pc->reg2offset(reg)); | |
| 1898 return buf+strlen(buf); | |
| 1899 } | |
| 1900 | |
| 1901 //------------------------------dump_register---------------------------------- | |
| 1902 // Dump a register name into a buffer. Be intelligent if we get called | |
| 1903 // before allocation is complete. | |
| 1904 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { | |
| 1905 if( !this ) { // Not got anything? | |
| 1906 sprintf(buf,"N%d",n->_idx); // Then use Node index | |
| 1907 } else if( _node_regs ) { | |
| 1908 // Post allocation, use direct mappings, no LRG info available | |
| 1909 print_reg( get_reg_first(n), this, buf ); | |
| 1910 } else { | |
| 1911 uint lidx = Find_const(n); // Grab LRG number | |
| 1912 if( !_ifg ) { | |
| 1913 sprintf(buf,"L%d",lidx); // No register binding yet | |
| 1914 } else if( !lidx ) { // Special, not allocated value | |
| 1915 strcpy(buf,"Special"); | |
|
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1916 } else { |
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1917 if (lrgs(lidx)._is_vector) { |
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1918 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) |
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1919 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register |
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1920 else |
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1921 sprintf(buf,"L%d",lidx); // No register binding yet |
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1922 } else if( (lrgs(lidx).num_regs() == 1) |
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1923 ? lrgs(lidx).mask().is_bound1() |
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1924 : lrgs(lidx).mask().is_bound_pair() ) { |
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1925 // Hah! We have a bound machine register |
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1926 print_reg( lrgs(lidx).reg(), this, buf ); |
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1927 } else { |
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1928 sprintf(buf,"L%d",lidx); // No register binding yet |
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1929 } |
| 0 | 1930 } |
| 1931 } | |
| 1932 return buf+strlen(buf); | |
| 1933 } | |
| 1934 | |
| 1935 //----------------------dump_for_spill_split_recycle-------------------------- | |
| 1936 void PhaseChaitin::dump_for_spill_split_recycle() const { | |
| 1937 if( WizardMode && (PrintCompilation || PrintOpto) ) { | |
| 1938 // Display which live ranges need to be split and the allocator's state | |
| 1939 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); | |
| 1940 for( uint bidx = 1; bidx < _maxlrg; bidx++ ) { | |
| 1941 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { | |
| 1942 tty->print("L%d: ", bidx); | |
| 1943 lrgs(bidx).dump(); | |
| 1944 } | |
| 1945 } | |
| 1946 tty->cr(); | |
| 1947 dump(); | |
| 1948 } | |
| 1949 } | |
| 1950 | |
| 1951 //------------------------------dump_frame------------------------------------ | |
| 1952 void PhaseChaitin::dump_frame() const { | |
| 1953 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); | |
| 1954 const TypeTuple *domain = C->tf()->domain(); | |
| 1955 const int argcnt = domain->cnt() - TypeFunc::Parms; | |
| 1956 | |
| 1957 // Incoming arguments in registers dump | |
| 1958 for( int k = 0; k < argcnt; k++ ) { | |
| 1959 OptoReg::Name parmreg = _matcher._parm_regs[k].first(); | |
| 1960 if( OptoReg::is_reg(parmreg)) { | |
| 1961 const char *reg_name = OptoReg::regname(parmreg); | |
| 1962 tty->print("#r%3.3d %s", parmreg, reg_name); | |
| 1963 parmreg = _matcher._parm_regs[k].second(); | |
| 1964 if( OptoReg::is_reg(parmreg)) { | |
| 1965 tty->print(":%s", OptoReg::regname(parmreg)); | |
| 1966 } | |
| 1967 tty->print(" : parm %d: ", k); | |
| 1968 domain->field_at(k + TypeFunc::Parms)->dump(); | |
| 1969 tty->print_cr(""); | |
| 1970 } | |
| 1971 } | |
| 1972 | |
| 1973 // Check for un-owned padding above incoming args | |
| 1974 OptoReg::Name reg = _matcher._new_SP; | |
| 1975 if( reg > _matcher._in_arg_limit ) { | |
| 1976 reg = OptoReg::add(reg, -1); | |
| 1977 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); | |
| 1978 } | |
| 1979 | |
| 1980 // Incoming argument area dump | |
| 1981 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); | |
| 1982 while( reg > begin_in_arg ) { | |
| 1983 reg = OptoReg::add(reg, -1); | |
| 1984 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); | |
| 1985 int j; | |
| 1986 for( j = 0; j < argcnt; j++) { | |
| 1987 if( _matcher._parm_regs[j].first() == reg || | |
| 1988 _matcher._parm_regs[j].second() == reg ) { | |
| 1989 tty->print("parm %d: ",j); | |
| 1990 domain->field_at(j + TypeFunc::Parms)->dump(); | |
| 1991 tty->print_cr(""); | |
| 1992 break; | |
| 1993 } | |
| 1994 } | |
| 1995 if( j >= argcnt ) | |
| 1996 tty->print_cr("HOLE, owned by SELF"); | |
| 1997 } | |
| 1998 | |
| 1999 // Old outgoing preserve area | |
| 2000 while( reg > _matcher._old_SP ) { | |
| 2001 reg = OptoReg::add(reg, -1); | |
| 2002 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2003 } | |
| 2004 | |
| 2005 // Old SP | |
| 2006 tty->print_cr("# -- Old %s -- Framesize: %d --",fp, | |
| 2007 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); | |
| 2008 | |
| 2009 // Preserve area dump | |
| 4950 | 2010 int fixed_slots = C->fixed_slots(); |
| 2011 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots()); | |
| 2012 OptoReg::Name return_addr = _matcher.return_addr(); | |
| 2013 | |
| 0 | 2014 reg = OptoReg::add(reg, -1); |
| 4950 | 2015 while (OptoReg::is_stack(reg)) { |
| 0 | 2016 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); |
| 4950 | 2017 if (return_addr == reg) { |
| 0 | 2018 tty->print_cr("return address"); |
| 4950 | 2019 } else if (reg >= begin_in_preserve) { |
| 2020 // Preserved slots are present on x86 | |
| 2021 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word)) | |
| 2022 tty->print_cr("saved fp register"); | |
| 2023 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) && | |
| 2024 VerifyStackAtCalls) | |
| 2025 tty->print_cr("0xBADB100D +VerifyStackAtCalls"); | |
| 2026 else | |
| 2027 tty->print_cr("in_preserve"); | |
| 2028 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) { | |
| 0 | 2029 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); |
| 4950 | 2030 } else { |
| 2031 tty->print_cr("pad2, stack alignment"); | |
| 2032 } | |
| 0 | 2033 reg = OptoReg::add(reg, -1); |
| 2034 } | |
| 2035 | |
| 2036 // Spill area dump | |
| 2037 reg = OptoReg::add(_matcher._new_SP, _framesize ); | |
| 2038 while( reg > _matcher._out_arg_limit ) { | |
| 2039 reg = OptoReg::add(reg, -1); | |
| 2040 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); | |
| 2041 } | |
| 2042 | |
| 2043 // Outgoing argument area dump | |
| 2044 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { | |
| 2045 reg = OptoReg::add(reg, -1); | |
| 2046 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); | |
| 2047 } | |
| 2048 | |
| 2049 // Outgoing new preserve area | |
| 2050 while( reg > _matcher._new_SP ) { | |
| 2051 reg = OptoReg::add(reg, -1); | |
| 2052 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2053 } | |
| 2054 tty->print_cr("#"); | |
| 2055 } | |
| 2056 | |
| 2057 //------------------------------dump_bb---------------------------------------- | |
| 2058 void PhaseChaitin::dump_bb( uint pre_order ) const { | |
| 2059 tty->print_cr("---dump of B%d---",pre_order); | |
| 2060 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | |
| 2061 Block *b = _cfg._blocks[i]; | |
| 2062 if( b->_pre_order == pre_order ) | |
| 2063 dump(b); | |
| 2064 } | |
| 2065 } | |
| 2066 | |
| 2067 //------------------------------dump_lrg--------------------------------------- | |
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2068 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
| 0 | 2069 tty->print_cr("---dump of L%d---",lidx); |
| 2070 | |
| 2071 if( _ifg ) { | |
| 2072 if( lidx >= _maxlrg ) { | |
| 2073 tty->print("Attempt to print live range index beyond max live range.\n"); | |
| 2074 return; | |
| 2075 } | |
| 2076 tty->print("L%d: ",lidx); | |
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2077 if( lidx < _ifg->_maxlrg ) lrgs(lidx).dump( ); |
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2078 else tty->print_cr("new LRG"); |
| 0 | 2079 } |
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2080 if( _ifg && lidx < _ifg->_maxlrg) { |
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2081 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
| 0 | 2082 _ifg->neighbors(lidx)->dump(); |
| 2083 tty->cr(); | |
| 2084 } | |
| 2085 // For all blocks | |
| 2086 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | |
| 2087 Block *b = _cfg._blocks[i]; | |
| 2088 int dump_once = 0; | |
| 2089 | |
| 2090 // For all instructions | |
| 2091 for( uint j = 0; j < b->_nodes.size(); j++ ) { | |
| 2092 Node *n = b->_nodes[j]; | |
| 2093 if( Find_const(n) == lidx ) { | |
| 2094 if( !dump_once++ ) { | |
| 2095 tty->cr(); | |
| 2096 b->dump_head( &_cfg._bbs ); | |
| 2097 } | |
| 2098 dump(n); | |
| 2099 continue; | |
| 2100 } | |
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2101 if (!defs_only) { |
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2102 uint cnt = n->req(); |
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2103 for( uint k = 1; k < cnt; k++ ) { |
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2104 Node *m = n->in(k); |
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2105 if (!m) continue; // be robust in the dumper |
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2106 if( Find_const(m) == lidx ) { |
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2107 if( !dump_once++ ) { |
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2108 tty->cr(); |
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2109 b->dump_head( &_cfg._bbs ); |
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2110 } |
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2111 dump(n); |
| 0 | 2112 } |
| 2113 } | |
| 2114 } | |
| 2115 } | |
| 2116 } // End of per-block dump | |
| 2117 tty->cr(); | |
| 2118 } | |
| 2119 #endif // not PRODUCT | |
| 2120 | |
| 2121 //------------------------------print_chaitin_statistics------------------------------- | |
| 2122 int PhaseChaitin::_final_loads = 0; | |
| 2123 int PhaseChaitin::_final_stores = 0; | |
| 2124 int PhaseChaitin::_final_memoves= 0; | |
| 2125 int PhaseChaitin::_final_copies = 0; | |
| 2126 double PhaseChaitin::_final_load_cost = 0; | |
| 2127 double PhaseChaitin::_final_store_cost = 0; | |
| 2128 double PhaseChaitin::_final_memove_cost= 0; | |
| 2129 double PhaseChaitin::_final_copy_cost = 0; | |
| 2130 int PhaseChaitin::_conserv_coalesce = 0; | |
| 2131 int PhaseChaitin::_conserv_coalesce_pair = 0; | |
| 2132 int PhaseChaitin::_conserv_coalesce_trie = 0; | |
| 2133 int PhaseChaitin::_conserv_coalesce_quad = 0; | |
| 2134 int PhaseChaitin::_post_alloc = 0; | |
| 2135 int PhaseChaitin::_lost_opp_pp_coalesce = 0; | |
| 2136 int PhaseChaitin::_lost_opp_cflow_coalesce = 0; | |
| 2137 int PhaseChaitin::_used_cisc_instructions = 0; | |
| 2138 int PhaseChaitin::_unused_cisc_instructions = 0; | |
| 2139 int PhaseChaitin::_allocator_attempts = 0; | |
| 2140 int PhaseChaitin::_allocator_successes = 0; | |
| 2141 | |
| 2142 #ifndef PRODUCT | |
| 2143 uint PhaseChaitin::_high_pressure = 0; | |
| 2144 uint PhaseChaitin::_low_pressure = 0; | |
| 2145 | |
| 2146 void PhaseChaitin::print_chaitin_statistics() { | |
| 2147 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); | |
| 2148 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); | |
| 2149 tty->print_cr("Adjusted spill cost = %7.0f.", | |
| 2150 _final_load_cost*4.0 + _final_store_cost * 2.0 + | |
| 2151 _final_copy_cost*1.0 + _final_memove_cost*12.0); | |
| 2152 tty->print("Conservatively coalesced %d copies, %d pairs", | |
| 2153 _conserv_coalesce, _conserv_coalesce_pair); | |
| 2154 if( _conserv_coalesce_trie || _conserv_coalesce_quad ) | |
| 2155 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); | |
| 2156 tty->print_cr(", %d post alloc.", _post_alloc); | |
| 2157 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) | |
| 2158 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", | |
| 2159 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); | |
| 2160 if( _used_cisc_instructions || _unused_cisc_instructions ) | |
| 2161 tty->print_cr("Used cisc instruction %d, remained in register %d", | |
| 2162 _used_cisc_instructions, _unused_cisc_instructions); | |
| 2163 if( _allocator_successes != 0 ) | |
| 2164 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); | |
| 2165 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); | |
| 2166 } | |
| 2167 #endif // not PRODUCT |