Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.hpp @ 11320:80de3bbfa8b9
Truffle-DSL: fixed inconsistent children for polymorphic -> generic rewrites. (GRAAL-425)
author | Christian Humer <christian.humer@gmail.com> |
---|---|
date | Fri, 16 Aug 2013 14:00:17 +0200 |
parents | 46c544b8fbfc |
children | eae426d683f6 |
rev | line source |
---|---|
0 | 1 /* |
6797
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6269
diff
changeset
|
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
643
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
643
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
643
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP | |
27 | |
28 #include "runtime/globals_extension.hpp" | |
29 #include "runtime/vm_version.hpp" | |
30 | |
0 | 31 class VM_Version: public Abstract_VM_Version { |
32 protected: | |
33 enum Feature_Flag { | |
3839 | 34 v8_instructions = 0, |
35 hardware_mul32 = 1, | |
36 hardware_div32 = 2, | |
37 hardware_fsmuld = 3, | |
38 hardware_popc = 4, | |
39 v9_instructions = 5, | |
40 vis1_instructions = 6, | |
41 vis2_instructions = 7, | |
42 sun4v_instructions = 8, | |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1552
diff
changeset
|
43 blk_init_instructions = 9, |
3839 | 44 fmaf_instructions = 10, |
45 fmau_instructions = 11, | |
46 vis3_instructions = 12, | |
6269 | 47 cbcond_instructions = 13, |
48 sparc64_family = 14, | |
49 M_family = 15, | |
50 T_family = 16, | |
51 T1_model = 17 | |
0 | 52 }; |
53 | |
54 enum Feature_Flag_Set { | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
55 unknown_m = 0, |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
56 all_features_m = -1, |
0 | 57 |
3839 | 58 v8_instructions_m = 1 << v8_instructions, |
59 hardware_mul32_m = 1 << hardware_mul32, | |
60 hardware_div32_m = 1 << hardware_div32, | |
61 hardware_fsmuld_m = 1 << hardware_fsmuld, | |
62 hardware_popc_m = 1 << hardware_popc, | |
63 v9_instructions_m = 1 << v9_instructions, | |
64 vis1_instructions_m = 1 << vis1_instructions, | |
65 vis2_instructions_m = 1 << vis2_instructions, | |
66 sun4v_m = 1 << sun4v_instructions, | |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1552
diff
changeset
|
67 blk_init_instructions_m = 1 << blk_init_instructions, |
3839 | 68 fmaf_instructions_m = 1 << fmaf_instructions, |
69 fmau_instructions_m = 1 << fmau_instructions, | |
70 vis3_instructions_m = 1 << vis3_instructions, | |
6269 | 71 cbcond_instructions_m = 1 << cbcond_instructions, |
3839 | 72 sparc64_family_m = 1 << sparc64_family, |
6269 | 73 M_family_m = 1 << M_family, |
3839 | 74 T_family_m = 1 << T_family, |
75 T1_model_m = 1 << T1_model, | |
0 | 76 |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
77 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
78 generic_v9_m = generic_v8_m | v9_instructions_m, |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
79 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
0 | 80 |
81 // Temporary until we have something more accurate | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
82 niagara1_unique_m = sun4v_m, |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
83 niagara1_m = generic_v9_m | niagara1_unique_m |
0 | 84 }; |
85 | |
86 static int _features; | |
87 static const char* _features_str; | |
88 | |
89 static void print_features(); | |
90 static int determine_features(); | |
91 static int platform_features(int features); | |
92 | |
2080 | 93 // Returns true if the platform is in the niagara line (T series) |
6269 | 94 static bool is_M_family(int features) { return (features & M_family_m) != 0; } |
2080 | 95 static bool is_T_family(int features) { return (features & T_family_m) != 0; } |
96 static bool is_niagara() { return is_T_family(_features); } | |
97 DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } ) | |
98 | |
99 // Returns true if it is niagara1 (T1). | |
100 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } | |
0 | 101 |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
102 static int maximum_niagara1_processor_count() { return 32; } |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
103 |
0 | 104 public: |
105 // Initialization | |
106 static void initialize(); | |
107 | |
108 // Instruction support | |
109 static bool has_v8() { return (_features & v8_instructions_m) != 0; } | |
110 static bool has_v9() { return (_features & v9_instructions_m) != 0; } | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
111 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
112 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
0 | 113 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
641
diff
changeset
|
114 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
0 | 115 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
116 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } | |
2080 | 117 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1552
diff
changeset
|
118 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } |
3839 | 119 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } |
0 | 120 |
121 static bool supports_compare_and_exchange() | |
122 { return has_v9(); } | |
123 | |
2080 | 124 // Returns true if the platform is in the niagara line (T series) |
125 // and newer than the niagara1. | |
126 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } | |
6797
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6269
diff
changeset
|
127 |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6269
diff
changeset
|
128 static bool is_M_series() { return is_M_family(_features); } |
3854 | 129 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } |
3839 | 130 |
2080 | 131 // Fujitsu SPARC64 |
132 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } | |
0 | 133 |
3839 | 134 static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
135 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } | |
136 | |
2080 | 137 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } |
138 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } | |
3854 | 139 |
3839 | 140 // T4 and newer Sparc have fast RDPC instruction. |
3854 | 141 static bool has_fast_rdpc() { return is_T4(); } |
142 | |
3892 | 143 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. |
144 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } | |
0 | 145 |
146 static const char* cpu_features() { return _features_str; } | |
147 | |
3854 | 148 static intx prefetch_data_size() { |
149 return is_T4() ? 32 : 64; // default prefetch block size on sparc | |
0 | 150 } |
151 | |
152 // Prefetch | |
153 static intx prefetch_copy_interval_in_bytes() { | |
154 intx interval = PrefetchCopyIntervalInBytes; | |
155 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
156 } | |
157 static intx prefetch_scan_interval_in_bytes() { | |
158 intx interval = PrefetchScanIntervalInBytes; | |
159 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
160 } | |
161 static intx prefetch_fields_ahead() { | |
162 intx count = PrefetchFieldsAhead; | |
163 return count >= 0 ? count : (is_ultra3() ? 1 : 0); | |
164 } | |
165 | |
166 static intx allocate_prefetch_distance() { | |
167 // This method should be called before allocate_prefetch_style(). | |
168 intx count = AllocatePrefetchDistance; | |
169 if (count < 0) { // default is not defined ? | |
170 count = 512; | |
171 } | |
172 return count; | |
173 } | |
174 static intx allocate_prefetch_style() { | |
175 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
176 // Return 0 if AllocatePrefetchDistance was not defined. | |
177 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
178 } | |
179 | |
180 // Assembler testing | |
181 static void allow_all(); | |
182 static void revert(); | |
183 | |
184 // Override the Abstract_VM_Version implementation. | |
185 static uint page_size_count() { return is_sun4v() ? 4 : 2; } | |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
186 |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
187 // Calculates the number of parallel threads |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
188 static unsigned int calc_parallel_worker_threads(); |
0 | 189 }; |
1972 | 190 |
191 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP |