Mercurial > hg > truffle
annotate src/share/vm/c1/c1_LIR.cpp @ 10408:836a62f43af9
Merge with http://hg.openjdk.java.net/hsx/hsx25/hotspot/
author | Doug Simon <doug.simon@oracle.com> |
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date | Wed, 19 Jun 2013 10:45:56 +0200 |
parents | acadb114c818 |
children | 87a6f2df28e2 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_InstructionPrinter.hpp" | |
27 #include "c1/c1_LIR.hpp" | |
28 #include "c1/c1_LIRAssembler.hpp" | |
29 #include "c1/c1_ValueStack.hpp" | |
30 #include "ci/ciInstance.hpp" | |
31 #include "runtime/sharedRuntime.hpp" | |
0 | 32 |
33 Register LIR_OprDesc::as_register() const { | |
34 return FrameMap::cpu_rnr2reg(cpu_regnr()); | |
35 } | |
36 | |
37 Register LIR_OprDesc::as_register_lo() const { | |
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); | |
39 } | |
40 | |
41 Register LIR_OprDesc::as_register_hi() const { | |
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); | |
43 } | |
44 | |
304 | 45 #if defined(X86) |
0 | 46 |
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { | |
48 return FrameMap::nr2xmmreg(xmm_regnr()); | |
49 } | |
50 | |
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { | |
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); | |
53 return FrameMap::nr2xmmreg(xmm_regnrLo()); | |
54 } | |
55 | |
304 | 56 #endif // X86 |
0 | 57 |
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58 #if defined(SPARC) || defined(PPC) |
0 | 59 |
60 FloatRegister LIR_OprDesc::as_float_reg() const { | |
61 return FrameMap::nr2floatreg(fpu_regnr()); | |
62 } | |
63 | |
64 FloatRegister LIR_OprDesc::as_double_reg() const { | |
65 return FrameMap::nr2floatreg(fpu_regnrHi()); | |
66 } | |
67 | |
68 #endif | |
69 | |
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70 #ifdef ARM |
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71 |
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72 FloatRegister LIR_OprDesc::as_float_reg() const { |
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73 return as_FloatRegister(fpu_regnr()); |
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74 } |
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75 |
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76 FloatRegister LIR_OprDesc::as_double_reg() const { |
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77 return as_FloatRegister(fpu_regnrLo()); |
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78 } |
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79 |
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80 #endif |
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81 |
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82 |
0 | 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
84 | |
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { | |
86 ValueTag tag = type->tag(); | |
87 switch (tag) { | |
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88 case metaDataTag : { |
0 | 89 ClassConstant* c = type->as_ClassConstant(); |
90 if (c != NULL && !c->value()->is_loaded()) { | |
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91 return LIR_OprFact::metadataConst(NULL); |
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92 } else if (c != NULL) { |
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93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); |
0 | 94 } else { |
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95 MethodConstant* m = type->as_MethodConstant(); |
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96 assert (m != NULL, "not a class or a method?"); |
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97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); |
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98 } |
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99 } |
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100 case objectTag : { |
0 | 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); |
102 } | |
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103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
0 | 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); | |
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); | |
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); | |
304 | 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
0 | 109 } |
110 } | |
111 | |
112 | |
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { | |
114 switch (type->tag()) { | |
115 case objectTag: return LIR_OprFact::oopConst(NULL); | |
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116 case addressTag:return LIR_OprFact::addressConst(0); |
0 | 117 case intTag: return LIR_OprFact::intConst(0); |
118 case floatTag: return LIR_OprFact::floatConst(0.0); | |
119 case longTag: return LIR_OprFact::longConst(0); | |
120 case doubleTag: return LIR_OprFact::doubleConst(0.0); | |
304 | 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
0 | 122 } |
123 return illegalOpr; | |
124 } | |
125 | |
126 | |
127 | |
128 //--------------------------------------------------- | |
129 | |
130 | |
131 LIR_Address::Scale LIR_Address::scale(BasicType type) { | |
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132 int elem_size = type2aelembytes(type); |
0 | 133 switch (elem_size) { |
134 case 1: return LIR_Address::times_1; | |
135 case 2: return LIR_Address::times_2; | |
136 case 4: return LIR_Address::times_4; | |
137 case 8: return LIR_Address::times_8; | |
138 } | |
139 ShouldNotReachHere(); | |
140 return LIR_Address::times_1; | |
141 } | |
142 | |
143 | |
144 #ifndef PRODUCT | |
145 void LIR_Address::verify() const { | |
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146 #if defined(SPARC) || defined(PPC) |
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147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
0 | 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
149 #endif | |
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150 #ifdef ARM |
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151 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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152 // Note: offsets higher than 4096 must not be rejected here. They can |
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153 // be handled by the back-end or will be rejected if not. |
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154 #endif |
0 | 155 #ifdef _LP64 |
156 assert(base()->is_cpu_register(), "wrong base operand"); | |
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); | |
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158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
0 | 159 "wrong type for addresses"); |
160 #else | |
161 assert(base()->is_single_cpu(), "wrong base operand"); | |
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); | |
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163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
0 | 164 "wrong type for addresses"); |
165 #endif | |
166 } | |
167 #endif | |
168 | |
169 | |
170 //--------------------------------------------------- | |
171 | |
172 char LIR_OprDesc::type_char(BasicType t) { | |
173 switch (t) { | |
174 case T_ARRAY: | |
175 t = T_OBJECT; | |
176 case T_BOOLEAN: | |
177 case T_CHAR: | |
178 case T_FLOAT: | |
179 case T_DOUBLE: | |
180 case T_BYTE: | |
181 case T_SHORT: | |
182 case T_INT: | |
183 case T_LONG: | |
184 case T_OBJECT: | |
185 case T_ADDRESS: | |
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186 case T_METADATA: |
0 | 187 case T_VOID: |
188 return ::type2char(t); | |
189 | |
190 case T_ILLEGAL: | |
191 return '?'; | |
192 | |
193 default: | |
194 ShouldNotReachHere(); | |
304 | 195 return '?'; |
0 | 196 } |
197 } | |
198 | |
199 #ifndef PRODUCT | |
200 void LIR_OprDesc::validate_type() const { | |
201 | |
202 #ifdef ASSERT | |
203 if (!is_pointer() && !is_illegal()) { | |
204 switch (as_BasicType(type_field())) { | |
205 case T_LONG: | |
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206 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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207 size_field() == double_size, "must match"); |
0 | 208 break; |
209 case T_FLOAT: | |
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210 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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211 assert((kind_field() == fpu_register || kind_field() == stack_value |
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212 ARM_ONLY(|| kind_field() == cpu_register) |
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213 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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214 size_field() == single_size, "must match"); |
0 | 215 break; |
216 case T_DOUBLE: | |
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217 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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218 assert((kind_field() == fpu_register || kind_field() == stack_value |
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219 ARM_ONLY(|| kind_field() == cpu_register) |
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220 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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221 size_field() == double_size, "must match"); |
0 | 222 break; |
223 case T_BOOLEAN: | |
224 case T_CHAR: | |
225 case T_BYTE: | |
226 case T_SHORT: | |
227 case T_INT: | |
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228 case T_ADDRESS: |
0 | 229 case T_OBJECT: |
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230 case T_METADATA: |
0 | 231 case T_ARRAY: |
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232 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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233 size_field() == single_size, "must match"); |
0 | 234 break; |
235 | |
236 case T_ILLEGAL: | |
237 // XXX TKR also means unknown right now | |
238 // assert(is_illegal(), "must match"); | |
239 break; | |
240 | |
241 default: | |
242 ShouldNotReachHere(); | |
243 } | |
244 } | |
245 #endif | |
246 | |
247 } | |
248 #endif // PRODUCT | |
249 | |
250 | |
251 bool LIR_OprDesc::is_oop() const { | |
252 if (is_pointer()) { | |
253 return pointer()->is_oop_pointer(); | |
254 } else { | |
255 OprType t= type_field(); | |
256 assert(t != unknown_type, "not set"); | |
257 return t == object_type; | |
258 } | |
259 } | |
260 | |
261 | |
262 | |
263 void LIR_Op2::verify() const { | |
264 #ifdef ASSERT | |
265 switch (code()) { | |
266 case lir_cmove: | |
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267 case lir_xchg: |
0 | 268 break; |
269 | |
270 default: | |
271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), | |
272 "can't produce oops from arith"); | |
273 } | |
274 | |
275 if (TwoOperandLIRForm) { | |
276 switch (code()) { | |
277 case lir_add: | |
278 case lir_sub: | |
279 case lir_mul: | |
280 case lir_mul_strictfp: | |
281 case lir_div: | |
282 case lir_div_strictfp: | |
283 case lir_rem: | |
284 case lir_logic_and: | |
285 case lir_logic_or: | |
286 case lir_logic_xor: | |
287 case lir_shl: | |
288 case lir_shr: | |
289 assert(in_opr1() == result_opr(), "opr1 and result must match"); | |
290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
291 break; | |
292 | |
293 // special handling for lir_ushr because of write barriers | |
294 case lir_ushr: | |
295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); | |
296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
297 break; | |
298 | |
299 } | |
300 } | |
301 #endif | |
302 } | |
303 | |
304 | |
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) | |
306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
307 , _cond(cond) | |
308 , _type(type) | |
309 , _label(block->label()) | |
310 , _block(block) | |
311 , _ublock(NULL) | |
312 , _stub(NULL) { | |
313 } | |
314 | |
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : | |
316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
317 , _cond(cond) | |
318 , _type(type) | |
319 , _label(stub->entry()) | |
320 , _block(NULL) | |
321 , _ublock(NULL) | |
322 , _stub(stub) { | |
323 } | |
324 | |
325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) | |
326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
327 , _cond(cond) | |
328 , _type(type) | |
329 , _label(block->label()) | |
330 , _block(block) | |
331 , _ublock(ublock) | |
332 , _stub(NULL) | |
333 { | |
334 } | |
335 | |
336 void LIR_OpBranch::change_block(BlockBegin* b) { | |
337 assert(_block != NULL, "must have old block"); | |
338 assert(_block->label() == label(), "must be equal"); | |
339 | |
340 _block = b; | |
341 _label = b->label(); | |
342 } | |
343 | |
344 void LIR_OpBranch::change_ublock(BlockBegin* b) { | |
345 assert(_ublock != NULL, "must have old block"); | |
346 _ublock = b; | |
347 } | |
348 | |
349 void LIR_OpBranch::negate_cond() { | |
350 switch (_cond) { | |
351 case lir_cond_equal: _cond = lir_cond_notEqual; break; | |
352 case lir_cond_notEqual: _cond = lir_cond_equal; break; | |
353 case lir_cond_less: _cond = lir_cond_greaterEqual; break; | |
354 case lir_cond_lessEqual: _cond = lir_cond_greater; break; | |
355 case lir_cond_greaterEqual: _cond = lir_cond_less; break; | |
356 case lir_cond_greater: _cond = lir_cond_lessEqual; break; | |
357 default: ShouldNotReachHere(); | |
358 } | |
359 } | |
360 | |
361 | |
362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, | |
364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, | |
1783 | 365 CodeStub* stub) |
366 | |
0 | 367 : LIR_Op(code, result, NULL) |
368 , _object(object) | |
369 , _array(LIR_OprFact::illegalOpr) | |
370 , _klass(klass) | |
371 , _tmp1(tmp1) | |
372 , _tmp2(tmp2) | |
373 , _tmp3(tmp3) | |
374 , _fast_check(fast_check) | |
375 , _stub(stub) | |
376 , _info_for_patch(info_for_patch) | |
377 , _info_for_exception(info_for_exception) | |
1783 | 378 , _profiled_method(NULL) |
379 , _profiled_bci(-1) | |
380 , _should_profile(false) | |
381 { | |
0 | 382 if (code == lir_checkcast) { |
383 assert(info_for_exception != NULL, "checkcast throws exceptions"); | |
384 } else if (code == lir_instanceof) { | |
385 assert(info_for_exception == NULL, "instanceof throws no exceptions"); | |
386 } else { | |
387 ShouldNotReachHere(); | |
388 } | |
389 } | |
390 | |
391 | |
392 | |
1783 | 393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) |
0 | 394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) |
395 , _object(object) | |
396 , _array(array) | |
397 , _klass(NULL) | |
398 , _tmp1(tmp1) | |
399 , _tmp2(tmp2) | |
400 , _tmp3(tmp3) | |
401 , _fast_check(false) | |
402 , _stub(NULL) | |
403 , _info_for_patch(NULL) | |
404 , _info_for_exception(info_for_exception) | |
1783 | 405 , _profiled_method(NULL) |
406 , _profiled_bci(-1) | |
407 , _should_profile(false) | |
408 { | |
0 | 409 if (code == lir_store_check) { |
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410 _stub = new ArrayStoreExceptionStub(object, info_for_exception); |
0 | 411 assert(info_for_exception != NULL, "store_check throws exceptions"); |
412 } else { | |
413 ShouldNotReachHere(); | |
414 } | |
415 } | |
416 | |
417 | |
418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, | |
419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) | |
420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) | |
421 , _tmp(tmp) | |
422 , _src(src) | |
423 , _src_pos(src_pos) | |
424 , _dst(dst) | |
425 , _dst_pos(dst_pos) | |
426 , _flags(flags) | |
427 , _expected_type(expected_type) | |
428 , _length(length) { | |
429 _stub = new ArrayCopyStub(this); | |
430 } | |
431 | |
432 | |
433 //-------------------verify-------------------------- | |
434 | |
435 void LIR_Op1::verify() const { | |
436 switch(code()) { | |
437 case lir_move: | |
438 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); | |
439 break; | |
440 case lir_null_check: | |
441 assert(in_opr()->is_register(), "must be"); | |
442 break; | |
443 case lir_return: | |
444 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); | |
445 break; | |
446 } | |
447 } | |
448 | |
449 void LIR_OpRTCall::verify() const { | |
450 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); | |
451 } | |
452 | |
453 //-------------------visits-------------------------- | |
454 | |
455 // complete rework of LIR instruction visitor. | |
456 // The virtual calls for each instruction type is replaced by a big | |
457 // switch that adds the operands for each instruction | |
458 | |
459 void LIR_OpVisitState::visit(LIR_Op* op) { | |
460 // copy information from the LIR_Op | |
461 reset(); | |
462 set_op(op); | |
463 | |
464 switch (op->code()) { | |
465 | |
466 // LIR_Op0 | |
467 case lir_word_align: // result and info always invalid | |
468 case lir_backwardbranch_target: // result and info always invalid | |
469 case lir_build_frame: // result and info always invalid | |
470 case lir_fpop_raw: // result and info always invalid | |
471 case lir_24bit_FPU: // result and info always invalid | |
472 case lir_reset_FPU: // result and info always invalid | |
473 case lir_breakpoint: // result and info always invalid | |
474 case lir_membar: // result and info always invalid | |
475 case lir_membar_acquire: // result and info always invalid | |
476 case lir_membar_release: // result and info always invalid | |
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477 case lir_membar_loadload: // result and info always invalid |
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478 case lir_membar_storestore: // result and info always invalid |
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479 case lir_membar_loadstore: // result and info always invalid |
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480 case lir_membar_storeload: // result and info always invalid |
0 | 481 { |
482 assert(op->as_Op0() != NULL, "must be"); | |
483 assert(op->_info == NULL, "info not used by this instruction"); | |
484 assert(op->_result->is_illegal(), "not used"); | |
485 break; | |
486 } | |
487 | |
488 case lir_nop: // may have info, result always invalid | |
489 case lir_std_entry: // may have result, info always invalid | |
490 case lir_osr_entry: // may have result, info always invalid | |
491 case lir_get_thread: // may have result, info always invalid | |
492 { | |
493 assert(op->as_Op0() != NULL, "must be"); | |
494 if (op->_info != NULL) do_info(op->_info); | |
495 if (op->_result->is_valid()) do_output(op->_result); | |
496 break; | |
497 } | |
498 | |
499 | |
500 // LIR_OpLabel | |
501 case lir_label: // result and info always invalid | |
502 { | |
503 assert(op->as_OpLabel() != NULL, "must be"); | |
504 assert(op->_info == NULL, "info not used by this instruction"); | |
505 assert(op->_result->is_illegal(), "not used"); | |
506 break; | |
507 } | |
508 | |
509 | |
510 // LIR_Op1 | |
511 case lir_fxch: // input always valid, result and info always invalid | |
512 case lir_fld: // input always valid, result and info always invalid | |
513 case lir_ffree: // input always valid, result and info always invalid | |
514 case lir_push: // input always valid, result and info always invalid | |
515 case lir_pop: // input always valid, result and info always invalid | |
516 case lir_return: // input always valid, result and info always invalid | |
517 case lir_leal: // input and result always valid, info always invalid | |
518 case lir_neg: // input and result always valid, info always invalid | |
519 case lir_monaddr: // input and result always valid, info always invalid | |
520 case lir_null_check: // input and info always valid, result always invalid | |
521 case lir_move: // input and result always valid, may have info | |
1783 | 522 case lir_pack64: // input and result always valid |
523 case lir_unpack64: // input and result always valid | |
0 | 524 case lir_prefetchr: // input always valid, result and info always invalid |
525 case lir_prefetchw: // input always valid, result and info always invalid | |
526 { | |
527 assert(op->as_Op1() != NULL, "must be"); | |
528 LIR_Op1* op1 = (LIR_Op1*)op; | |
529 | |
530 if (op1->_info) do_info(op1->_info); | |
531 if (op1->_opr->is_valid()) do_input(op1->_opr); | |
532 if (op1->_result->is_valid()) do_output(op1->_result); | |
533 | |
534 break; | |
535 } | |
536 | |
537 case lir_safepoint: | |
538 { | |
539 assert(op->as_Op1() != NULL, "must be"); | |
540 LIR_Op1* op1 = (LIR_Op1*)op; | |
541 | |
542 assert(op1->_info != NULL, ""); do_info(op1->_info); | |
543 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register | |
544 assert(op1->_result->is_illegal(), "safepoint does not produce value"); | |
545 | |
546 break; | |
547 } | |
548 | |
549 // LIR_OpConvert; | |
550 case lir_convert: // input and result always valid, info always invalid | |
551 { | |
552 assert(op->as_OpConvert() != NULL, "must be"); | |
553 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; | |
554 | |
555 assert(opConvert->_info == NULL, "must be"); | |
556 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); | |
557 if (opConvert->_result->is_valid()) do_output(opConvert->_result); | |
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558 #ifdef PPC |
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559 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
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560 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
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561 #endif |
0 | 562 do_stub(opConvert->_stub); |
563 | |
564 break; | |
565 } | |
566 | |
567 // LIR_OpBranch; | |
568 case lir_branch: // may have info, input and result register always invalid | |
569 case lir_cond_float_branch: // may have info, input and result register always invalid | |
570 { | |
571 assert(op->as_OpBranch() != NULL, "must be"); | |
572 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; | |
573 | |
574 if (opBranch->_info != NULL) do_info(opBranch->_info); | |
575 assert(opBranch->_result->is_illegal(), "not used"); | |
576 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); | |
577 | |
578 break; | |
579 } | |
580 | |
581 | |
582 // LIR_OpAllocObj | |
583 case lir_alloc_object: | |
584 { | |
585 assert(op->as_OpAllocObj() != NULL, "must be"); | |
586 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; | |
587 | |
588 if (opAllocObj->_info) do_info(opAllocObj->_info); | |
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589 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
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590 do_temp(opAllocObj->_opr); |
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591 } |
0 | 592 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
593 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); | |
594 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); | |
595 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); | |
596 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); | |
597 do_stub(opAllocObj->_stub); | |
598 break; | |
599 } | |
600 | |
601 | |
602 // LIR_OpRoundFP; | |
603 case lir_roundfp: { | |
604 assert(op->as_OpRoundFP() != NULL, "must be"); | |
605 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; | |
606 | |
607 assert(op->_info == NULL, "info not used by this instruction"); | |
608 assert(opRoundFP->_tmp->is_illegal(), "not used"); | |
609 do_input(opRoundFP->_opr); | |
610 do_output(opRoundFP->_result); | |
611 | |
612 break; | |
613 } | |
614 | |
615 | |
616 // LIR_Op2 | |
617 case lir_cmp: | |
618 case lir_cmp_l2i: | |
619 case lir_ucmp_fd2i: | |
620 case lir_cmp_fd2i: | |
621 case lir_add: | |
622 case lir_sub: | |
623 case lir_mul: | |
624 case lir_div: | |
625 case lir_rem: | |
626 case lir_sqrt: | |
627 case lir_abs: | |
628 case lir_logic_and: | |
629 case lir_logic_or: | |
630 case lir_logic_xor: | |
631 case lir_shl: | |
632 case lir_shr: | |
633 case lir_ushr: | |
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634 case lir_xadd: |
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635 case lir_xchg: |
8860 | 636 case lir_assert: |
0 | 637 { |
638 assert(op->as_Op2() != NULL, "must be"); | |
639 LIR_Op2* op2 = (LIR_Op2*)op; | |
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640 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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641 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 642 |
643 if (op2->_info) do_info(op2->_info); | |
644 if (op2->_opr1->is_valid()) do_input(op2->_opr1); | |
645 if (op2->_opr2->is_valid()) do_input(op2->_opr2); | |
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646 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
0 | 647 if (op2->_result->is_valid()) do_output(op2->_result); |
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648 if (op->code() == lir_xchg || op->code() == lir_xadd) { |
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649 // on ARM and PPC, return value is loaded first so could |
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650 // destroy inputs. On other platforms that implement those |
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651 // (x86, sparc), the extra constrainsts are harmless. |
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652 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); |
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653 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); |
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654 } |
0 | 655 |
656 break; | |
657 } | |
658 | |
659 // special handling for cmove: right input operand must not be equal | |
660 // to the result operand, otherwise the backend fails | |
661 case lir_cmove: | |
662 { | |
663 assert(op->as_Op2() != NULL, "must be"); | |
664 LIR_Op2* op2 = (LIR_Op2*)op; | |
665 | |
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666 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && |
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667 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 668 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); |
669 | |
670 do_input(op2->_opr1); | |
671 do_input(op2->_opr2); | |
672 do_temp(op2->_opr2); | |
673 do_output(op2->_result); | |
674 | |
675 break; | |
676 } | |
677 | |
678 // vspecial handling for strict operations: register input operands | |
679 // as temp to guarantee that they do not overlap with other | |
680 // registers | |
681 case lir_mul_strictfp: | |
682 case lir_div_strictfp: | |
683 { | |
684 assert(op->as_Op2() != NULL, "must be"); | |
685 LIR_Op2* op2 = (LIR_Op2*)op; | |
686 | |
687 assert(op2->_info == NULL, "not used"); | |
688 assert(op2->_opr1->is_valid(), "used"); | |
689 assert(op2->_opr2->is_valid(), "used"); | |
690 assert(op2->_result->is_valid(), "used"); | |
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691 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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692 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 693 |
694 do_input(op2->_opr1); do_temp(op2->_opr1); | |
695 do_input(op2->_opr2); do_temp(op2->_opr2); | |
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696 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
0 | 697 do_output(op2->_result); |
698 | |
699 break; | |
700 } | |
701 | |
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702 case lir_throw: { |
0 | 703 assert(op->as_Op2() != NULL, "must be"); |
704 LIR_Op2* op2 = (LIR_Op2*)op; | |
705 | |
706 if (op2->_info) do_info(op2->_info); | |
707 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); | |
708 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter | |
709 assert(op2->_result->is_illegal(), "no result"); | |
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710 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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711 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 712 |
713 break; | |
714 } | |
715 | |
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716 case lir_unwind: { |
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717 assert(op->as_Op1() != NULL, "must be"); |
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718 LIR_Op1* op1 = (LIR_Op1*)op; |
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719 |
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720 assert(op1->_info == NULL, "no info"); |
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721 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
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722 assert(op1->_result->is_illegal(), "no result"); |
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723 |
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724 break; |
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725 } |
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726 |
0 | 727 |
728 case lir_tan: | |
729 case lir_sin: | |
953
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730 case lir_cos: |
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731 case lir_log: |
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732 case lir_log10: |
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733 case lir_exp: { |
0 | 734 assert(op->as_Op2() != NULL, "must be"); |
735 LIR_Op2* op2 = (LIR_Op2*)op; | |
736 | |
953
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737 // On x86 tan/sin/cos need two temporary fpu stack slots and |
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738 // log/log10 need one so handle opr2 and tmp as temp inputs. |
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739 // Register input operand as temp to guarantee that it doesn't |
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740 // overlap with the input. |
0 | 741 assert(op2->_info == NULL, "not used"); |
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742 assert(op2->_tmp5->is_illegal(), "not used"); |
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743 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); |
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744 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); |
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745 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); |
0 | 746 assert(op2->_opr1->is_valid(), "used"); |
747 do_input(op2->_opr1); do_temp(op2->_opr1); | |
748 | |
749 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); | |
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750 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
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751 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); |
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752 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); |
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753 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); |
0 | 754 if (op2->_result->is_valid()) do_output(op2->_result); |
755 | |
756 break; | |
757 } | |
758 | |
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759 case lir_pow: { |
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760 assert(op->as_Op2() != NULL, "must be"); |
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761 LIR_Op2* op2 = (LIR_Op2*)op; |
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762 |
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763 // On x86 pow needs two temporary fpu stack slots: tmp1 and |
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764 // tmp2. Register input operands as temps to guarantee that it |
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765 // doesn't overlap with the temporary slots. |
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766 assert(op2->_info == NULL, "not used"); |
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767 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); |
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768 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() |
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769 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); |
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770 assert(op2->_result->is_valid(), "used"); |
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771 |
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772 do_input(op2->_opr1); do_temp(op2->_opr1); |
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773 do_input(op2->_opr2); do_temp(op2->_opr2); |
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774 do_temp(op2->_tmp1); |
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775 do_temp(op2->_tmp2); |
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776 do_temp(op2->_tmp3); |
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777 do_temp(op2->_tmp4); |
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778 do_temp(op2->_tmp5); |
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779 do_output(op2->_result); |
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780 |
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781 break; |
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782 } |
0 | 783 |
784 // LIR_Op3 | |
785 case lir_idiv: | |
786 case lir_irem: { | |
787 assert(op->as_Op3() != NULL, "must be"); | |
788 LIR_Op3* op3= (LIR_Op3*)op; | |
789 | |
790 if (op3->_info) do_info(op3->_info); | |
791 if (op3->_opr1->is_valid()) do_input(op3->_opr1); | |
792 | |
793 // second operand is input and temp, so ensure that second operand | |
794 // and third operand get not the same register | |
795 if (op3->_opr2->is_valid()) do_input(op3->_opr2); | |
796 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); | |
797 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); | |
798 | |
799 if (op3->_result->is_valid()) do_output(op3->_result); | |
800 | |
801 break; | |
802 } | |
803 | |
804 | |
805 // LIR_OpJavaCall | |
806 case lir_static_call: | |
807 case lir_optvirtual_call: | |
808 case lir_icvirtual_call: | |
1295 | 809 case lir_virtual_call: |
810 case lir_dynamic_call: { | |
811 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); | |
812 assert(opJavaCall != NULL, "must be"); | |
0 | 813 |
814 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); | |
815 | |
816 // only visit register parameters | |
817 int n = opJavaCall->_arguments->length(); | |
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818 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { |
0 | 819 if (!opJavaCall->_arguments->at(i)->is_pointer()) { |
820 do_input(*opJavaCall->_arguments->adr_at(i)); | |
821 } | |
822 } | |
823 | |
824 if (opJavaCall->_info) do_info(opJavaCall->_info); | |
1564 | 825 if (opJavaCall->is_method_handle_invoke()) { |
826 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); | |
827 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); | |
828 } | |
0 | 829 do_call(); |
830 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); | |
831 | |
832 break; | |
833 } | |
834 | |
835 | |
836 // LIR_OpRTCall | |
837 case lir_rtcall: { | |
838 assert(op->as_OpRTCall() != NULL, "must be"); | |
839 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; | |
840 | |
841 // only visit register parameters | |
842 int n = opRTCall->_arguments->length(); | |
843 for (int i = 0; i < n; i++) { | |
844 if (!opRTCall->_arguments->at(i)->is_pointer()) { | |
845 do_input(*opRTCall->_arguments->adr_at(i)); | |
846 } | |
847 } | |
848 if (opRTCall->_info) do_info(opRTCall->_info); | |
849 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); | |
850 do_call(); | |
851 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); | |
852 | |
853 break; | |
854 } | |
855 | |
856 | |
857 // LIR_OpArrayCopy | |
858 case lir_arraycopy: { | |
859 assert(op->as_OpArrayCopy() != NULL, "must be"); | |
860 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; | |
861 | |
862 assert(opArrayCopy->_result->is_illegal(), "unused"); | |
863 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); | |
864 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); | |
865 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); | |
866 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); | |
867 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); | |
868 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); | |
869 if (opArrayCopy->_info) do_info(opArrayCopy->_info); | |
870 | |
871 // the implementation of arraycopy always has a call into the runtime | |
872 do_call(); | |
873 | |
874 break; | |
875 } | |
876 | |
877 | |
878 // LIR_OpLock | |
879 case lir_lock: | |
880 case lir_unlock: { | |
881 assert(op->as_OpLock() != NULL, "must be"); | |
882 LIR_OpLock* opLock = (LIR_OpLock*)op; | |
883 | |
884 if (opLock->_info) do_info(opLock->_info); | |
885 | |
886 // TODO: check if these operands really have to be temp | |
887 // (or if input is sufficient). This may have influence on the oop map! | |
888 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); | |
889 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); | |
890 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); | |
891 | |
892 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); | |
893 assert(opLock->_result->is_illegal(), "unused"); | |
894 | |
895 do_stub(opLock->_stub); | |
896 | |
897 break; | |
898 } | |
899 | |
900 | |
901 // LIR_OpDelay | |
902 case lir_delay_slot: { | |
903 assert(op->as_OpDelay() != NULL, "must be"); | |
904 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; | |
905 | |
906 visit(opDelay->delay_op()); | |
907 break; | |
908 } | |
909 | |
910 // LIR_OpTypeCheck | |
911 case lir_instanceof: | |
912 case lir_checkcast: | |
913 case lir_store_check: { | |
914 assert(op->as_OpTypeCheck() != NULL, "must be"); | |
915 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; | |
916 | |
917 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); | |
918 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); | |
919 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); | |
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920 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { |
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921 do_temp(opTypeCheck->_object); |
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922 } |
0 | 923 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); |
924 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); | |
925 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); | |
926 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); | |
927 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); | |
928 do_stub(opTypeCheck->_stub); | |
929 break; | |
930 } | |
931 | |
932 // LIR_OpCompareAndSwap | |
933 case lir_cas_long: | |
934 case lir_cas_obj: | |
935 case lir_cas_int: { | |
936 assert(op->as_OpCompareAndSwap() != NULL, "must be"); | |
937 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; | |
938 | |
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939 assert(opCompareAndSwap->_addr->is_valid(), "used"); |
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940 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
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941 assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
0 | 942 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
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943 do_input(opCompareAndSwap->_addr); |
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944 do_temp(opCompareAndSwap->_addr); |
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945 do_input(opCompareAndSwap->_cmp_value); |
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946 do_temp(opCompareAndSwap->_cmp_value); |
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947 do_input(opCompareAndSwap->_new_value); |
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948 do_temp(opCompareAndSwap->_new_value); |
0 | 949 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
950 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); | |
951 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); | |
952 | |
953 break; | |
954 } | |
955 | |
956 | |
957 // LIR_OpAllocArray; | |
958 case lir_alloc_array: { | |
959 assert(op->as_OpAllocArray() != NULL, "must be"); | |
960 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; | |
961 | |
962 if (opAllocArray->_info) do_info(opAllocArray->_info); | |
963 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); | |
964 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); | |
965 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); | |
966 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); | |
967 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); | |
968 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); | |
969 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); | |
970 do_stub(opAllocArray->_stub); | |
971 break; | |
972 } | |
973 | |
974 // LIR_OpProfileCall: | |
975 case lir_profile_call: { | |
976 assert(op->as_OpProfileCall() != NULL, "must be"); | |
977 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; | |
978 | |
979 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); | |
980 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); | |
981 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); | |
982 break; | |
983 } | |
984 default: | |
985 ShouldNotReachHere(); | |
986 } | |
987 } | |
988 | |
989 | |
990 void LIR_OpVisitState::do_stub(CodeStub* stub) { | |
991 if (stub != NULL) { | |
992 stub->visit(this); | |
993 } | |
994 } | |
995 | |
996 XHandlers* LIR_OpVisitState::all_xhandler() { | |
997 XHandlers* result = NULL; | |
998 | |
999 int i; | |
1000 for (i = 0; i < info_count(); i++) { | |
1001 if (info_at(i)->exception_handlers() != NULL) { | |
1002 result = info_at(i)->exception_handlers(); | |
1003 break; | |
1004 } | |
1005 } | |
1006 | |
1007 #ifdef ASSERT | |
1008 for (i = 0; i < info_count(); i++) { | |
1009 assert(info_at(i)->exception_handlers() == NULL || | |
1010 info_at(i)->exception_handlers() == result, | |
1011 "only one xhandler list allowed per LIR-operation"); | |
1012 } | |
1013 #endif | |
1014 | |
1015 if (result != NULL) { | |
1016 return result; | |
1017 } else { | |
1018 return new XHandlers(); | |
1019 } | |
1020 | |
1021 return result; | |
1022 } | |
1023 | |
1024 | |
1025 #ifdef ASSERT | |
1026 bool LIR_OpVisitState::no_operands(LIR_Op* op) { | |
1027 visit(op); | |
1028 | |
1029 return opr_count(inputMode) == 0 && | |
1030 opr_count(outputMode) == 0 && | |
1031 opr_count(tempMode) == 0 && | |
1032 info_count() == 0 && | |
1033 !has_call() && | |
1034 !has_slow_case(); | |
1035 } | |
1036 #endif | |
1037 | |
1038 //--------------------------------------------------- | |
1039 | |
1040 | |
1041 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { | |
1042 masm->emit_call(this); | |
1043 } | |
1044 | |
1045 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { | |
1046 masm->emit_rtcall(this); | |
1047 } | |
1048 | |
1049 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { | |
1050 masm->emit_opLabel(this); | |
1051 } | |
1052 | |
1053 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { | |
1054 masm->emit_arraycopy(this); | |
1055 masm->emit_code_stub(stub()); | |
1056 } | |
1057 | |
1058 void LIR_Op0::emit_code(LIR_Assembler* masm) { | |
1059 masm->emit_op0(this); | |
1060 } | |
1061 | |
1062 void LIR_Op1::emit_code(LIR_Assembler* masm) { | |
1063 masm->emit_op1(this); | |
1064 } | |
1065 | |
1066 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { | |
1067 masm->emit_alloc_obj(this); | |
1068 masm->emit_code_stub(stub()); | |
1069 } | |
1070 | |
1071 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { | |
1072 masm->emit_opBranch(this); | |
1073 if (stub()) { | |
1074 masm->emit_code_stub(stub()); | |
1075 } | |
1076 } | |
1077 | |
1078 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { | |
1079 masm->emit_opConvert(this); | |
1080 if (stub() != NULL) { | |
1081 masm->emit_code_stub(stub()); | |
1082 } | |
1083 } | |
1084 | |
1085 void LIR_Op2::emit_code(LIR_Assembler* masm) { | |
1086 masm->emit_op2(this); | |
1087 } | |
1088 | |
1089 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { | |
1090 masm->emit_alloc_array(this); | |
1091 masm->emit_code_stub(stub()); | |
1092 } | |
1093 | |
1094 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { | |
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1095 masm->emit_opTypeCheck(this); |
0 | 1096 if (stub()) { |
1097 masm->emit_code_stub(stub()); | |
1098 } | |
1099 } | |
1100 | |
1101 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { | |
1102 masm->emit_compare_and_swap(this); | |
1103 } | |
1104 | |
1105 void LIR_Op3::emit_code(LIR_Assembler* masm) { | |
1106 masm->emit_op3(this); | |
1107 } | |
1108 | |
1109 void LIR_OpLock::emit_code(LIR_Assembler* masm) { | |
1110 masm->emit_lock(this); | |
1111 if (stub()) { | |
1112 masm->emit_code_stub(stub()); | |
1113 } | |
1114 } | |
1115 | |
8860 | 1116 #ifdef ASSERT |
1117 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { | |
1118 masm->emit_assert(this); | |
1119 } | |
1120 #endif | |
0 | 1121 |
1122 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { | |
1123 masm->emit_delay(this); | |
1124 } | |
1125 | |
1126 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { | |
1127 masm->emit_profile_call(this); | |
1128 } | |
1129 | |
1130 // LIR_List | |
1131 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) | |
1132 : _operations(8) | |
1133 , _compilation(compilation) | |
1134 #ifndef PRODUCT | |
1135 , _block(block) | |
1136 #endif | |
1137 #ifdef ASSERT | |
1138 , _file(NULL) | |
1139 , _line(0) | |
1140 #endif | |
1141 { } | |
1142 | |
1143 | |
1144 #ifdef ASSERT | |
1145 void LIR_List::set_file_and_line(const char * file, int line) { | |
1146 const char * f = strrchr(file, '/'); | |
1147 if (f == NULL) f = strrchr(file, '\\'); | |
1148 if (f == NULL) { | |
1149 f = file; | |
1150 } else { | |
1151 f++; | |
1152 } | |
1153 _file = f; | |
1154 _line = line; | |
1155 } | |
1156 #endif | |
1157 | |
1158 | |
1159 void LIR_List::append(LIR_InsertionBuffer* buffer) { | |
1160 assert(this == buffer->lir_list(), "wrong lir list"); | |
1161 const int n = _operations.length(); | |
1162 | |
1163 if (buffer->number_of_ops() > 0) { | |
1164 // increase size of instructions list | |
1165 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); | |
1166 // insert ops from buffer into instructions list | |
1167 int op_index = buffer->number_of_ops() - 1; | |
1168 int ip_index = buffer->number_of_insertion_points() - 1; | |
1169 int from_index = n - 1; | |
1170 int to_index = _operations.length() - 1; | |
1171 for (; ip_index >= 0; ip_index --) { | |
1172 int index = buffer->index_at(ip_index); | |
1173 // make room after insertion point | |
1174 while (index < from_index) { | |
1175 _operations.at_put(to_index --, _operations.at(from_index --)); | |
1176 } | |
1177 // insert ops from buffer | |
1178 for (int i = buffer->count_at(ip_index); i > 0; i --) { | |
1179 _operations.at_put(to_index --, buffer->op_at(op_index --)); | |
1180 } | |
1181 } | |
1182 } | |
1183 | |
1184 buffer->finish(); | |
1185 } | |
1186 | |
1187 | |
1188 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { | |
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1189 assert(reg->type() == T_OBJECT, "bad reg"); |
0 | 1190 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); |
1191 } | |
1192 | |
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1193 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { |
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1194 assert(reg->type() == T_METADATA, "bad reg"); |
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1195 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); |
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1196 } |
0 | 1197 |
1198 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1199 append(new LIR_Op1( | |
1200 lir_move, | |
1201 LIR_OprFact::address(addr), | |
1202 src, | |
1203 addr->type(), | |
1204 patch_code, | |
1205 info)); | |
1206 } | |
1207 | |
1208 | |
1209 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1210 append(new LIR_Op1( | |
1211 lir_move, | |
1212 LIR_OprFact::address(address), | |
1213 dst, | |
1214 address->type(), | |
1215 patch_code, | |
1216 info, lir_move_volatile)); | |
1217 } | |
1218 | |
1219 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1220 append(new LIR_Op1( | |
1221 lir_move, | |
1222 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
1223 dst, | |
1224 type, | |
1225 patch_code, | |
1226 info, lir_move_volatile)); | |
1227 } | |
1228 | |
1229 | |
1230 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { | |
1231 append(new LIR_Op1( | |
1232 is_store ? lir_prefetchw : lir_prefetchr, | |
1233 LIR_OprFact::address(addr))); | |
1234 } | |
1235 | |
1236 | |
1237 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1238 append(new LIR_Op1( | |
1239 lir_move, | |
1240 LIR_OprFact::intConst(v), | |
1241 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
1242 type, | |
1243 patch_code, | |
1244 info)); | |
1245 } | |
1246 | |
1247 | |
1248 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1249 append(new LIR_Op1( | |
1250 lir_move, | |
1251 LIR_OprFact::oopConst(o), | |
1252 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
1253 type, | |
1254 patch_code, | |
1255 info)); | |
1256 } | |
1257 | |
1258 | |
1259 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1260 append(new LIR_Op1( | |
1261 lir_move, | |
1262 src, | |
1263 LIR_OprFact::address(addr), | |
1264 addr->type(), | |
1265 patch_code, | |
1266 info)); | |
1267 } | |
1268 | |
1269 | |
1270 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1271 append(new LIR_Op1( | |
1272 lir_move, | |
1273 src, | |
1274 LIR_OprFact::address(addr), | |
1275 addr->type(), | |
1276 patch_code, | |
1277 info, | |
1278 lir_move_volatile)); | |
1279 } | |
1280 | |
1281 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1282 append(new LIR_Op1( | |
1283 lir_move, | |
1284 src, | |
1285 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
1286 type, | |
1287 patch_code, | |
1288 info, lir_move_volatile)); | |
1289 } | |
1290 | |
1291 | |
1292 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1293 append(new LIR_Op3( | |
1294 lir_idiv, | |
1295 left, | |
1296 right, | |
1297 tmp, | |
1298 res, | |
1299 info)); | |
1300 } | |
1301 | |
1302 | |
1303 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1304 append(new LIR_Op3( | |
1305 lir_idiv, | |
1306 left, | |
1307 LIR_OprFact::intConst(right), | |
1308 tmp, | |
1309 res, | |
1310 info)); | |
1311 } | |
1312 | |
1313 | |
1314 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1315 append(new LIR_Op3( | |
1316 lir_irem, | |
1317 left, | |
1318 right, | |
1319 tmp, | |
1320 res, | |
1321 info)); | |
1322 } | |
1323 | |
1324 | |
1325 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1326 append(new LIR_Op3( | |
1327 lir_irem, | |
1328 left, | |
1329 LIR_OprFact::intConst(right), | |
1330 tmp, | |
1331 res, | |
1332 info)); | |
1333 } | |
1334 | |
1335 | |
1336 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { | |
1337 append(new LIR_Op2( | |
1338 lir_cmp, | |
1339 condition, | |
1340 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), | |
1341 LIR_OprFact::intConst(c), | |
1342 info)); | |
1343 } | |
1344 | |
1345 | |
1346 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { | |
1347 append(new LIR_Op2( | |
1348 lir_cmp, | |
1349 condition, | |
1350 reg, | |
1351 LIR_OprFact::address(addr), | |
1352 info)); | |
1353 } | |
1354 | |
1355 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, | |
1356 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { | |
1357 append(new LIR_OpAllocObj( | |
1358 klass, | |
1359 dst, | |
1360 t1, | |
1361 t2, | |
1362 t3, | |
1363 t4, | |
1364 header_size, | |
1365 object_size, | |
1366 init_check, | |
1367 stub)); | |
1368 } | |
1369 | |
1370 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { | |
1371 append(new LIR_OpAllocArray( | |
1372 klass, | |
1373 len, | |
1374 dst, | |
1375 t1, | |
1376 t2, | |
1377 t3, | |
1378 t4, | |
1379 type, | |
1380 stub)); | |
1381 } | |
1382 | |
1383 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1384 append(new LIR_Op2( | |
1385 lir_shl, | |
1386 value, | |
1387 count, | |
1388 dst, | |
1389 tmp)); | |
1390 } | |
1391 | |
1392 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1393 append(new LIR_Op2( | |
1394 lir_shr, | |
1395 value, | |
1396 count, | |
1397 dst, | |
1398 tmp)); | |
1399 } | |
1400 | |
1401 | |
1402 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1403 append(new LIR_Op2( | |
1404 lir_ushr, | |
1405 value, | |
1406 count, | |
1407 dst, | |
1408 tmp)); | |
1409 } | |
1410 | |
1411 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { | |
1412 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, | |
1413 left, | |
1414 right, | |
1415 dst)); | |
1416 } | |
1417 | |
1418 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { | |
1419 append(new LIR_OpLock( | |
1420 lir_lock, | |
1421 hdr, | |
1422 obj, | |
1423 lock, | |
1424 scratch, | |
1425 stub, | |
1426 info)); | |
1427 } | |
1428 | |
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1429 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
0 | 1430 append(new LIR_OpLock( |
1431 lir_unlock, | |
1432 hdr, | |
1433 obj, | |
1434 lock, | |
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1435 scratch, |
0 | 1436 stub, |
1437 NULL)); | |
1438 } | |
1439 | |
1440 | |
1441 void check_LIR() { | |
1442 // cannot do the proper checking as PRODUCT and other modes return different results | |
1443 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); | |
1444 } | |
1445 | |
1446 | |
1447 | |
1448 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
1449 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, | |
1450 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, | |
1451 ciMethod* profiled_method, int profiled_bci) { | |
1783 | 1452 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, |
1453 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); | |
1454 if (profiled_method != NULL) { | |
1455 c->set_profiled_method(profiled_method); | |
1456 c->set_profiled_bci(profiled_bci); | |
1457 c->set_should_profile(true); | |
1458 } | |
1459 append(c); | |
0 | 1460 } |
1461 | |
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1462 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { |
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1463 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); |
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1464 if (profiled_method != NULL) { |
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1465 c->set_profiled_method(profiled_method); |
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1466 c->set_profiled_bci(profiled_bci); |
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1467 c->set_should_profile(true); |
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1468 } |
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1469 append(c); |
0 | 1470 } |
1471 | |
1472 | |
3957 | 1473 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
1474 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { | |
1475 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); | |
1476 if (profiled_method != NULL) { | |
1477 c->set_profiled_method(profiled_method); | |
1478 c->set_profiled_bci(profiled_bci); | |
1479 c->set_should_profile(true); | |
1480 } | |
1481 append(c); | |
0 | 1482 } |
1483 | |
1484 | |
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1485 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1486 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1487 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1488 } |
1489 | |
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1490 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1491 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1492 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1493 } |
1494 | |
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1495 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1496 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1497 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1498 } |
1499 | |
1500 | |
1501 #ifdef PRODUCT | |
1502 | |
1503 void print_LIR(BlockList* blocks) { | |
1504 } | |
1505 | |
1506 #else | |
1507 // LIR_OprDesc | |
1508 void LIR_OprDesc::print() const { | |
1509 print(tty); | |
1510 } | |
1511 | |
1512 void LIR_OprDesc::print(outputStream* out) const { | |
1513 if (is_illegal()) { | |
1514 return; | |
1515 } | |
1516 | |
1517 out->print("["); | |
1518 if (is_pointer()) { | |
1519 pointer()->print_value_on(out); | |
1520 } else if (is_single_stack()) { | |
1521 out->print("stack:%d", single_stack_ix()); | |
1522 } else if (is_double_stack()) { | |
1523 out->print("dbl_stack:%d",double_stack_ix()); | |
1524 } else if (is_virtual()) { | |
1525 out->print("R%d", vreg_number()); | |
1526 } else if (is_single_cpu()) { | |
1527 out->print(as_register()->name()); | |
1528 } else if (is_double_cpu()) { | |
1529 out->print(as_register_hi()->name()); | |
1530 out->print(as_register_lo()->name()); | |
304 | 1531 #if defined(X86) |
0 | 1532 } else if (is_single_xmm()) { |
1533 out->print(as_xmm_float_reg()->name()); | |
1534 } else if (is_double_xmm()) { | |
1535 out->print(as_xmm_double_reg()->name()); | |
1536 } else if (is_single_fpu()) { | |
1537 out->print("fpu%d", fpu_regnr()); | |
1538 } else if (is_double_fpu()) { | |
1539 out->print("fpu%d", fpu_regnrLo()); | |
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1540 #elif defined(ARM) |
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1541 } else if (is_single_fpu()) { |
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1542 out->print("s%d", fpu_regnr()); |
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1543 } else if (is_double_fpu()) { |
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1544 out->print("d%d", fpu_regnrLo() >> 1); |
0 | 1545 #else |
1546 } else if (is_single_fpu()) { | |
1547 out->print(as_float_reg()->name()); | |
1548 } else if (is_double_fpu()) { | |
1549 out->print(as_double_reg()->name()); | |
1550 #endif | |
1551 | |
1552 } else if (is_illegal()) { | |
1553 out->print("-"); | |
1554 } else { | |
1555 out->print("Unknown Operand"); | |
1556 } | |
1557 if (!is_illegal()) { | |
1558 out->print("|%c", type_char()); | |
1559 } | |
1560 if (is_register() && is_last_use()) { | |
1561 out->print("(last_use)"); | |
1562 } | |
1563 out->print("]"); | |
1564 } | |
1565 | |
1566 | |
1567 // LIR_Address | |
1568 void LIR_Const::print_value_on(outputStream* out) const { | |
1569 switch (type()) { | |
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1570 case T_ADDRESS:out->print("address:%d",as_jint()); break; |
0 | 1571 case T_INT: out->print("int:%d", as_jint()); break; |
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1572 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; |
0 | 1573 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; |
1574 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; | |
1575 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; | |
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1576 case T_METADATA: out->print("metadata:0x%x", as_metadata());break; |
0 | 1577 default: out->print("%3d:0x%x",type(), as_jdouble()); break; |
1578 } | |
1579 } | |
1580 | |
1581 // LIR_Address | |
1582 void LIR_Address::print_value_on(outputStream* out) const { | |
1583 out->print("Base:"); _base->print(out); | |
1584 if (!_index->is_illegal()) { | |
1585 out->print(" Index:"); _index->print(out); | |
1586 switch (scale()) { | |
1587 case times_1: break; | |
1588 case times_2: out->print(" * 2"); break; | |
1589 case times_4: out->print(" * 4"); break; | |
1590 case times_8: out->print(" * 8"); break; | |
1591 } | |
1592 } | |
1593 out->print(" Disp: %d", _disp); | |
1594 } | |
1595 | |
1596 // debug output of block header without InstructionPrinter | |
1597 // (because phi functions are not necessary for LIR) | |
1598 static void print_block(BlockBegin* x) { | |
1599 // print block id | |
1600 BlockEnd* end = x->end(); | |
1601 tty->print("B%d ", x->block_id()); | |
1602 | |
1603 // print flags | |
1604 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); | |
1605 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); | |
1606 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); | |
1607 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); | |
1608 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); | |
1609 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); | |
1610 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); | |
1611 | |
1612 // print block bci range | |
1819 | 1613 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); |
0 | 1614 |
1615 // print predecessors and successors | |
1616 if (x->number_of_preds() > 0) { | |
1617 tty->print("preds: "); | |
1618 for (int i = 0; i < x->number_of_preds(); i ++) { | |
1619 tty->print("B%d ", x->pred_at(i)->block_id()); | |
1620 } | |
1621 } | |
1622 | |
1623 if (x->number_of_sux() > 0) { | |
1624 tty->print("sux: "); | |
1625 for (int i = 0; i < x->number_of_sux(); i ++) { | |
1626 tty->print("B%d ", x->sux_at(i)->block_id()); | |
1627 } | |
1628 } | |
1629 | |
1630 // print exception handlers | |
1631 if (x->number_of_exception_handlers() > 0) { | |
1632 tty->print("xhandler: "); | |
1633 for (int i = 0; i < x->number_of_exception_handlers(); i++) { | |
1634 tty->print("B%d ", x->exception_handler_at(i)->block_id()); | |
1635 } | |
1636 } | |
1637 | |
1638 tty->cr(); | |
1639 } | |
1640 | |
1641 void print_LIR(BlockList* blocks) { | |
1642 tty->print_cr("LIR:"); | |
1643 int i; | |
1644 for (i = 0; i < blocks->length(); i++) { | |
1645 BlockBegin* bb = blocks->at(i); | |
1646 print_block(bb); | |
1647 tty->print("__id_Instruction___________________________________________"); tty->cr(); | |
1648 bb->lir()->print_instructions(); | |
1649 } | |
1650 } | |
1651 | |
1652 void LIR_List::print_instructions() { | |
1653 for (int i = 0; i < _operations.length(); i++) { | |
1654 _operations.at(i)->print(); tty->cr(); | |
1655 } | |
1656 tty->cr(); | |
1657 } | |
1658 | |
1659 // LIR_Ops printing routines | |
1660 // LIR_Op | |
1661 void LIR_Op::print_on(outputStream* out) const { | |
1662 if (id() != -1 || PrintCFGToFile) { | |
1663 out->print("%4d ", id()); | |
1664 } else { | |
1665 out->print(" "); | |
1666 } | |
1667 out->print(name()); out->print(" "); | |
1668 print_instr(out); | |
1819 | 1669 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); |
0 | 1670 #ifdef ASSERT |
1671 if (Verbose && _file != NULL) { | |
1672 out->print(" (%s:%d)", _file, _line); | |
1673 } | |
1674 #endif | |
1675 } | |
1676 | |
1677 const char * LIR_Op::name() const { | |
1678 const char* s = NULL; | |
1679 switch(code()) { | |
1680 // LIR_Op0 | |
1681 case lir_membar: s = "membar"; break; | |
1682 case lir_membar_acquire: s = "membar_acquire"; break; | |
1683 case lir_membar_release: s = "membar_release"; break; | |
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1684 case lir_membar_loadload: s = "membar_loadload"; break; |
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1685 case lir_membar_storestore: s = "membar_storestore"; break; |
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1686 case lir_membar_loadstore: s = "membar_loadstore"; break; |
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1687 case lir_membar_storeload: s = "membar_storeload"; break; |
0 | 1688 case lir_word_align: s = "word_align"; break; |
1689 case lir_label: s = "label"; break; | |
1690 case lir_nop: s = "nop"; break; | |
1691 case lir_backwardbranch_target: s = "backbranch"; break; | |
1692 case lir_std_entry: s = "std_entry"; break; | |
1693 case lir_osr_entry: s = "osr_entry"; break; | |
1694 case lir_build_frame: s = "build_frm"; break; | |
1695 case lir_fpop_raw: s = "fpop_raw"; break; | |
1696 case lir_24bit_FPU: s = "24bit_FPU"; break; | |
1697 case lir_reset_FPU: s = "reset_FPU"; break; | |
1698 case lir_breakpoint: s = "breakpoint"; break; | |
1699 case lir_get_thread: s = "get_thread"; break; | |
1700 // LIR_Op1 | |
1701 case lir_fxch: s = "fxch"; break; | |
1702 case lir_fld: s = "fld"; break; | |
1703 case lir_ffree: s = "ffree"; break; | |
1704 case lir_push: s = "push"; break; | |
1705 case lir_pop: s = "pop"; break; | |
1706 case lir_null_check: s = "null_check"; break; | |
1707 case lir_return: s = "return"; break; | |
1708 case lir_safepoint: s = "safepoint"; break; | |
1709 case lir_neg: s = "neg"; break; | |
1710 case lir_leal: s = "leal"; break; | |
1711 case lir_branch: s = "branch"; break; | |
1712 case lir_cond_float_branch: s = "flt_cond_br"; break; | |
1713 case lir_move: s = "move"; break; | |
1714 case lir_roundfp: s = "roundfp"; break; | |
1715 case lir_rtcall: s = "rtcall"; break; | |
1716 case lir_throw: s = "throw"; break; | |
1717 case lir_unwind: s = "unwind"; break; | |
1718 case lir_convert: s = "convert"; break; | |
1719 case lir_alloc_object: s = "alloc_obj"; break; | |
1720 case lir_monaddr: s = "mon_addr"; break; | |
1783 | 1721 case lir_pack64: s = "pack64"; break; |
1722 case lir_unpack64: s = "unpack64"; break; | |
0 | 1723 // LIR_Op2 |
1724 case lir_cmp: s = "cmp"; break; | |
1725 case lir_cmp_l2i: s = "cmp_l2i"; break; | |
1726 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; | |
1727 case lir_cmp_fd2i: s = "comp_fd2i"; break; | |
1728 case lir_cmove: s = "cmove"; break; | |
1729 case lir_add: s = "add"; break; | |
1730 case lir_sub: s = "sub"; break; | |
1731 case lir_mul: s = "mul"; break; | |
1732 case lir_mul_strictfp: s = "mul_strictfp"; break; | |
1733 case lir_div: s = "div"; break; | |
1734 case lir_div_strictfp: s = "div_strictfp"; break; | |
1735 case lir_rem: s = "rem"; break; | |
1736 case lir_abs: s = "abs"; break; | |
1737 case lir_sqrt: s = "sqrt"; break; | |
1738 case lir_sin: s = "sin"; break; | |
1739 case lir_cos: s = "cos"; break; | |
1740 case lir_tan: s = "tan"; break; | |
1741 case lir_log: s = "log"; break; | |
1742 case lir_log10: s = "log10"; break; | |
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1743 case lir_exp: s = "exp"; break; |
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1744 case lir_pow: s = "pow"; break; |
0 | 1745 case lir_logic_and: s = "logic_and"; break; |
1746 case lir_logic_or: s = "logic_or"; break; | |
1747 case lir_logic_xor: s = "logic_xor"; break; | |
1748 case lir_shl: s = "shift_left"; break; | |
1749 case lir_shr: s = "shift_right"; break; | |
1750 case lir_ushr: s = "ushift_right"; break; | |
1751 case lir_alloc_array: s = "alloc_array"; break; | |
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1752 case lir_xadd: s = "xadd"; break; |
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1753 case lir_xchg: s = "xchg"; break; |
0 | 1754 // LIR_Op3 |
1755 case lir_idiv: s = "idiv"; break; | |
1756 case lir_irem: s = "irem"; break; | |
1757 // LIR_OpJavaCall | |
1758 case lir_static_call: s = "static"; break; | |
1759 case lir_optvirtual_call: s = "optvirtual"; break; | |
1760 case lir_icvirtual_call: s = "icvirtual"; break; | |
1761 case lir_virtual_call: s = "virtual"; break; | |
1295 | 1762 case lir_dynamic_call: s = "dynamic"; break; |
0 | 1763 // LIR_OpArrayCopy |
1764 case lir_arraycopy: s = "arraycopy"; break; | |
1765 // LIR_OpLock | |
1766 case lir_lock: s = "lock"; break; | |
1767 case lir_unlock: s = "unlock"; break; | |
1768 // LIR_OpDelay | |
1769 case lir_delay_slot: s = "delay"; break; | |
1770 // LIR_OpTypeCheck | |
1771 case lir_instanceof: s = "instanceof"; break; | |
1772 case lir_checkcast: s = "checkcast"; break; | |
1773 case lir_store_check: s = "store_check"; break; | |
1774 // LIR_OpCompareAndSwap | |
1775 case lir_cas_long: s = "cas_long"; break; | |
1776 case lir_cas_obj: s = "cas_obj"; break; | |
1777 case lir_cas_int: s = "cas_int"; break; | |
1778 // LIR_OpProfileCall | |
1779 case lir_profile_call: s = "profile_call"; break; | |
8860 | 1780 // LIR_OpAssert |
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1781 #ifdef ASSERT |
8860 | 1782 case lir_assert: s = "assert"; break; |
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1783 #endif |
0 | 1784 case lir_none: ShouldNotReachHere();break; |
1785 default: s = "illegal_op"; break; | |
1786 } | |
1787 return s; | |
1788 } | |
1789 | |
1790 // LIR_OpJavaCall | |
1791 void LIR_OpJavaCall::print_instr(outputStream* out) const { | |
1792 out->print("call: "); | |
1793 out->print("[addr: 0x%x]", address()); | |
1794 if (receiver()->is_valid()) { | |
1795 out->print(" [recv: "); receiver()->print(out); out->print("]"); | |
1796 } | |
1797 if (result_opr()->is_valid()) { | |
1798 out->print(" [result: "); result_opr()->print(out); out->print("]"); | |
1799 } | |
1800 } | |
1801 | |
1802 // LIR_OpLabel | |
1803 void LIR_OpLabel::print_instr(outputStream* out) const { | |
1804 out->print("[label:0x%x]", _label); | |
1805 } | |
1806 | |
1807 // LIR_OpArrayCopy | |
1808 void LIR_OpArrayCopy::print_instr(outputStream* out) const { | |
1809 src()->print(out); out->print(" "); | |
1810 src_pos()->print(out); out->print(" "); | |
1811 dst()->print(out); out->print(" "); | |
1812 dst_pos()->print(out); out->print(" "); | |
1813 length()->print(out); out->print(" "); | |
1814 tmp()->print(out); out->print(" "); | |
1815 } | |
1816 | |
1817 // LIR_OpCompareAndSwap | |
1818 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { | |
1819 addr()->print(out); out->print(" "); | |
1820 cmp_value()->print(out); out->print(" "); | |
1821 new_value()->print(out); out->print(" "); | |
1822 tmp1()->print(out); out->print(" "); | |
1823 tmp2()->print(out); out->print(" "); | |
1824 | |
1825 } | |
1826 | |
1827 // LIR_Op0 | |
1828 void LIR_Op0::print_instr(outputStream* out) const { | |
1829 result_opr()->print(out); | |
1830 } | |
1831 | |
1832 // LIR_Op1 | |
1833 const char * LIR_Op1::name() const { | |
1834 if (code() == lir_move) { | |
1835 switch (move_kind()) { | |
1836 case lir_move_normal: | |
1837 return "move"; | |
1838 case lir_move_unaligned: | |
1839 return "unaligned move"; | |
1840 case lir_move_volatile: | |
1841 return "volatile_move"; | |
2002 | 1842 case lir_move_wide: |
1843 return "wide_move"; | |
0 | 1844 default: |
1845 ShouldNotReachHere(); | |
1846 return "illegal_op"; | |
1847 } | |
1848 } else { | |
1849 return LIR_Op::name(); | |
1850 } | |
1851 } | |
1852 | |
1853 | |
1854 void LIR_Op1::print_instr(outputStream* out) const { | |
1855 _opr->print(out); out->print(" "); | |
1856 result_opr()->print(out); out->print(" "); | |
1857 print_patch_code(out, patch_code()); | |
1858 } | |
1859 | |
1860 | |
1861 // LIR_Op1 | |
1862 void LIR_OpRTCall::print_instr(outputStream* out) const { | |
1863 intx a = (intx)addr(); | |
1864 out->print(Runtime1::name_for_address(addr())); | |
1865 out->print(" "); | |
1866 tmp()->print(out); | |
1867 } | |
1868 | |
1869 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { | |
1870 switch(code) { | |
1871 case lir_patch_none: break; | |
1872 case lir_patch_low: out->print("[patch_low]"); break; | |
1873 case lir_patch_high: out->print("[patch_high]"); break; | |
1874 case lir_patch_normal: out->print("[patch_normal]"); break; | |
1875 default: ShouldNotReachHere(); | |
1876 } | |
1877 } | |
1878 | |
1879 // LIR_OpBranch | |
1880 void LIR_OpBranch::print_instr(outputStream* out) const { | |
1881 print_condition(out, cond()); out->print(" "); | |
1882 if (block() != NULL) { | |
1883 out->print("[B%d] ", block()->block_id()); | |
1884 } else if (stub() != NULL) { | |
1885 out->print("["); | |
1886 stub()->print_name(out); | |
1887 out->print(": 0x%x]", stub()); | |
1819 | 1888 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); |
0 | 1889 } else { |
1890 out->print("[label:0x%x] ", label()); | |
1891 } | |
1892 if (ublock() != NULL) { | |
1893 out->print("unordered: [B%d] ", ublock()->block_id()); | |
1894 } | |
1895 } | |
1896 | |
1897 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { | |
1898 switch(cond) { | |
1899 case lir_cond_equal: out->print("[EQ]"); break; | |
1900 case lir_cond_notEqual: out->print("[NE]"); break; | |
1901 case lir_cond_less: out->print("[LT]"); break; | |
1902 case lir_cond_lessEqual: out->print("[LE]"); break; | |
1903 case lir_cond_greaterEqual: out->print("[GE]"); break; | |
1904 case lir_cond_greater: out->print("[GT]"); break; | |
1905 case lir_cond_belowEqual: out->print("[BE]"); break; | |
1906 case lir_cond_aboveEqual: out->print("[AE]"); break; | |
1907 case lir_cond_always: out->print("[AL]"); break; | |
1908 default: out->print("[%d]",cond); break; | |
1909 } | |
1910 } | |
1911 | |
1912 // LIR_OpConvert | |
1913 void LIR_OpConvert::print_instr(outputStream* out) const { | |
1914 print_bytecode(out, bytecode()); | |
1915 in_opr()->print(out); out->print(" "); | |
1916 result_opr()->print(out); out->print(" "); | |
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1917 #ifdef PPC |
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1918 if(tmp1()->is_valid()) { |
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1919 tmp1()->print(out); out->print(" "); |
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1920 tmp2()->print(out); out->print(" "); |
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1921 } |
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1922 #endif |
0 | 1923 } |
1924 | |
1925 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { | |
1926 switch(code) { | |
1927 case Bytecodes::_d2f: out->print("[d2f] "); break; | |
1928 case Bytecodes::_d2i: out->print("[d2i] "); break; | |
1929 case Bytecodes::_d2l: out->print("[d2l] "); break; | |
1930 case Bytecodes::_f2d: out->print("[f2d] "); break; | |
1931 case Bytecodes::_f2i: out->print("[f2i] "); break; | |
1932 case Bytecodes::_f2l: out->print("[f2l] "); break; | |
1933 case Bytecodes::_i2b: out->print("[i2b] "); break; | |
1934 case Bytecodes::_i2c: out->print("[i2c] "); break; | |
1935 case Bytecodes::_i2d: out->print("[i2d] "); break; | |
1936 case Bytecodes::_i2f: out->print("[i2f] "); break; | |
1937 case Bytecodes::_i2l: out->print("[i2l] "); break; | |
1938 case Bytecodes::_i2s: out->print("[i2s] "); break; | |
1939 case Bytecodes::_l2i: out->print("[l2i] "); break; | |
1940 case Bytecodes::_l2f: out->print("[l2f] "); break; | |
1941 case Bytecodes::_l2d: out->print("[l2d] "); break; | |
1942 default: | |
1943 out->print("[?%d]",code); | |
1944 break; | |
1945 } | |
1946 } | |
1947 | |
1948 void LIR_OpAllocObj::print_instr(outputStream* out) const { | |
1949 klass()->print(out); out->print(" "); | |
1950 obj()->print(out); out->print(" "); | |
1951 tmp1()->print(out); out->print(" "); | |
1952 tmp2()->print(out); out->print(" "); | |
1953 tmp3()->print(out); out->print(" "); | |
1954 tmp4()->print(out); out->print(" "); | |
1955 out->print("[hdr:%d]", header_size()); out->print(" "); | |
1956 out->print("[obj:%d]", object_size()); out->print(" "); | |
1957 out->print("[lbl:0x%x]", stub()->entry()); | |
1958 } | |
1959 | |
1960 void LIR_OpRoundFP::print_instr(outputStream* out) const { | |
1961 _opr->print(out); out->print(" "); | |
1962 tmp()->print(out); out->print(" "); | |
1963 result_opr()->print(out); out->print(" "); | |
1964 } | |
1965 | |
1966 // LIR_Op2 | |
1967 void LIR_Op2::print_instr(outputStream* out) const { | |
1968 if (code() == lir_cmove) { | |
1969 print_condition(out, condition()); out->print(" "); | |
1970 } | |
1971 in_opr1()->print(out); out->print(" "); | |
1972 in_opr2()->print(out); out->print(" "); | |
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1973 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } |
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1974 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } |
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1975 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } |
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1976 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } |
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1977 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } |
0 | 1978 result_opr()->print(out); |
1979 } | |
1980 | |
1981 void LIR_OpAllocArray::print_instr(outputStream* out) const { | |
1982 klass()->print(out); out->print(" "); | |
1983 len()->print(out); out->print(" "); | |
1984 obj()->print(out); out->print(" "); | |
1985 tmp1()->print(out); out->print(" "); | |
1986 tmp2()->print(out); out->print(" "); | |
1987 tmp3()->print(out); out->print(" "); | |
1988 tmp4()->print(out); out->print(" "); | |
1989 out->print("[type:0x%x]", type()); out->print(" "); | |
1990 out->print("[label:0x%x]", stub()->entry()); | |
1991 } | |
1992 | |
1993 | |
1994 void LIR_OpTypeCheck::print_instr(outputStream* out) const { | |
1995 object()->print(out); out->print(" "); | |
1996 if (code() == lir_store_check) { | |
1997 array()->print(out); out->print(" "); | |
1998 } | |
1999 if (code() != lir_store_check) { | |
2000 klass()->print_name_on(out); out->print(" "); | |
2001 if (fast_check()) out->print("fast_check "); | |
2002 } | |
2003 tmp1()->print(out); out->print(" "); | |
2004 tmp2()->print(out); out->print(" "); | |
2005 tmp3()->print(out); out->print(" "); | |
2006 result_opr()->print(out); out->print(" "); | |
1819 | 2007 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); |
0 | 2008 } |
2009 | |
2010 | |
2011 // LIR_Op3 | |
2012 void LIR_Op3::print_instr(outputStream* out) const { | |
2013 in_opr1()->print(out); out->print(" "); | |
2014 in_opr2()->print(out); out->print(" "); | |
2015 in_opr3()->print(out); out->print(" "); | |
2016 result_opr()->print(out); | |
2017 } | |
2018 | |
2019 | |
2020 void LIR_OpLock::print_instr(outputStream* out) const { | |
2021 hdr_opr()->print(out); out->print(" "); | |
2022 obj_opr()->print(out); out->print(" "); | |
2023 lock_opr()->print(out); out->print(" "); | |
2024 if (_scratch->is_valid()) { | |
2025 _scratch->print(out); out->print(" "); | |
2026 } | |
2027 out->print("[lbl:0x%x]", stub()->entry()); | |
2028 } | |
2029 | |
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2030 #ifdef ASSERT |
8860 | 2031 void LIR_OpAssert::print_instr(outputStream* out) const { |
2032 print_condition(out, condition()); out->print(" "); | |
2033 in_opr1()->print(out); out->print(" "); | |
2034 in_opr2()->print(out); out->print(", \""); | |
2035 out->print(msg()); out->print("\""); | |
2036 } | |
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2037 #endif |
8860 | 2038 |
0 | 2039 |
2040 void LIR_OpDelay::print_instr(outputStream* out) const { | |
2041 _op->print_on(out); | |
2042 } | |
2043 | |
2044 | |
2045 // LIR_OpProfileCall | |
2046 void LIR_OpProfileCall::print_instr(outputStream* out) const { | |
2047 profiled_method()->name()->print_symbol_on(out); | |
2048 out->print("."); | |
2049 profiled_method()->holder()->name()->print_symbol_on(out); | |
2050 out->print(" @ %d ", profiled_bci()); | |
2051 mdo()->print(out); out->print(" "); | |
2052 recv()->print(out); out->print(" "); | |
2053 tmp1()->print(out); out->print(" "); | |
2054 } | |
2055 | |
2056 #endif // PRODUCT | |
2057 | |
2058 // Implementation of LIR_InsertionBuffer | |
2059 | |
2060 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { | |
2061 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); | |
2062 | |
2063 int i = number_of_insertion_points() - 1; | |
2064 if (i < 0 || index_at(i) < index) { | |
2065 append_new(index, 1); | |
2066 } else { | |
2067 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); | |
2068 assert(count_at(i) > 0, "check"); | |
2069 set_count_at(i, count_at(i) + 1); | |
2070 } | |
2071 _ops.push(op); | |
2072 | |
2073 DEBUG_ONLY(verify()); | |
2074 } | |
2075 | |
2076 #ifdef ASSERT | |
2077 void LIR_InsertionBuffer::verify() { | |
2078 int sum = 0; | |
2079 int prev_idx = -1; | |
2080 | |
2081 for (int i = 0; i < number_of_insertion_points(); i++) { | |
2082 assert(prev_idx < index_at(i), "index must be ordered ascending"); | |
2083 sum += count_at(i); | |
2084 } | |
2085 assert(sum == number_of_ops(), "wrong total sum"); | |
2086 } | |
2087 #endif |