Mercurial > hg > truffle
annotate src/share/vm/c1/c1_LIRAssembler.hpp @ 6862:8a5ea0a9ccc4
7127708: G1: change task num types from int to uint in concurrent mark
Summary: Change the type of various task num fields, parameters etc to unsigned and rename them to be more consistent with the other collectors. Code changes were also reviewed by Vitaly Davidovich.
Reviewed-by: johnc
Contributed-by: Kaushik Srenevasan <kaushik@twitter.com>
| author | johnc |
|---|---|
| date | Sat, 06 Oct 2012 01:17:44 -0700 |
| parents | 7eca5de9e0b6 |
| children | 46f6f063b272 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP |
| 26 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP | |
| 27 | |
| 28 #include "c1/c1_CodeStubs.hpp" | |
| 29 #include "ci/ciMethodData.hpp" | |
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30 #include "oops/methodData.hpp" |
| 1972 | 31 #include "utilities/top.hpp" |
| 32 | |
| 0 | 33 class Compilation; |
| 34 class ScopeValue; | |
| 342 | 35 class BarrierSet; |
| 0 | 36 |
| 37 class LIR_Assembler: public CompilationResourceObj { | |
| 38 private: | |
| 39 C1_MacroAssembler* _masm; | |
| 40 CodeStubList* _slow_case_stubs; | |
| 342 | 41 BarrierSet* _bs; |
| 0 | 42 |
| 43 Compilation* _compilation; | |
| 44 FrameMap* _frame_map; | |
| 45 BlockBegin* _current_block; | |
| 46 | |
| 47 Instruction* _pending_non_safepoint; | |
| 48 int _pending_non_safepoint_offset; | |
| 49 | |
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50 Label _unwind_handler_entry; |
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51 |
| 0 | 52 #ifdef ASSERT |
| 53 BlockList _branch_target_blocks; | |
| 54 void check_no_unbound_labels(); | |
| 55 #endif | |
| 56 | |
| 57 FrameMap* frame_map() const { return _frame_map; } | |
| 58 | |
| 59 void set_current_block(BlockBegin* b) { _current_block = b; } | |
| 60 BlockBegin* current_block() const { return _current_block; } | |
| 61 | |
| 62 // non-safepoint debug info management | |
| 63 void flush_debug_info(int before_pc_offset) { | |
| 64 if (_pending_non_safepoint != NULL) { | |
| 65 if (_pending_non_safepoint_offset < before_pc_offset) | |
| 66 record_non_safepoint_debug_info(); | |
| 67 _pending_non_safepoint = NULL; | |
| 68 } | |
| 69 } | |
| 70 void process_debug_info(LIR_Op* op); | |
| 71 void record_non_safepoint_debug_info(); | |
| 72 | |
| 73 // unified bailout support | |
| 74 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
| 75 bool bailed_out() const { return compilation()->bailed_out(); } | |
| 76 | |
| 77 // code emission patterns and accessors | |
| 78 void check_codespace(); | |
| 79 bool needs_icache(ciMethod* method) const; | |
| 80 | |
| 81 // returns offset of icache check | |
| 82 int check_icache(); | |
| 83 | |
| 84 void jobject2reg(jobject o, Register reg); | |
| 85 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info); | |
| 86 | |
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87 void metadata2reg(Metadata* o, Register reg); |
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88 void klass2reg_with_patching(Register reg, CodeEmitInfo* info); |
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89 |
| 0 | 90 void emit_stubs(CodeStubList* stub_list); |
| 91 | |
| 92 // addresses | |
| 304 | 93 Address as_Address(LIR_Address* addr); |
| 94 Address as_Address_lo(LIR_Address* addr); | |
| 95 Address as_Address_hi(LIR_Address* addr); | |
| 0 | 96 |
| 97 // debug information | |
| 1564 | 98 void add_call_info(int pc_offset, CodeEmitInfo* cinfo); |
| 0 | 99 void add_debug_info_for_branch(CodeEmitInfo* info); |
| 100 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); | |
| 101 void add_debug_info_for_div0_here(CodeEmitInfo* info); | |
| 102 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); | |
| 103 void add_debug_info_for_null_check_here(CodeEmitInfo* info); | |
| 104 | |
| 105 void set_24bit_FPU(); | |
| 106 void reset_FPU(); | |
| 107 void fpop(); | |
| 108 void fxch(int i); | |
| 109 void fld(int i); | |
| 110 void ffree(int i); | |
| 111 | |
| 112 void breakpoint(); | |
| 113 void push(LIR_Opr opr); | |
| 114 void pop(LIR_Opr opr); | |
| 115 | |
| 116 // patching | |
| 117 void append_patching_stub(PatchingStub* stub); | |
| 118 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info); | |
| 119 | |
| 120 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op); | |
| 121 | |
| 122 public: | |
| 123 LIR_Assembler(Compilation* c); | |
| 124 ~LIR_Assembler(); | |
| 125 C1_MacroAssembler* masm() const { return _masm; } | |
| 126 Compilation* compilation() const { return _compilation; } | |
| 127 ciMethod* method() const { return compilation()->method(); } | |
| 128 | |
| 129 CodeOffsets* offsets() const { return _compilation->offsets(); } | |
| 130 int code_offset() const; | |
| 131 address pc() const; | |
| 132 | |
| 133 int initial_frame_size_in_bytes(); | |
| 134 | |
| 135 // test for constants which can be encoded directly in instructions | |
| 136 static bool is_small_constant(LIR_Opr opr); | |
| 137 | |
| 138 static LIR_Opr receiverOpr(); | |
| 139 static LIR_Opr osrBufferPointer(); | |
| 140 | |
| 141 // stubs | |
| 142 void emit_slow_case_stubs(); | |
| 143 void emit_static_call_stub(); | |
| 144 void emit_code_stub(CodeStub* op); | |
| 145 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); } | |
| 146 | |
| 147 // code patterns | |
| 1204 | 148 int emit_exception_handler(); |
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149 int emit_unwind_handler(); |
| 0 | 150 void emit_exception_entries(ExceptionInfoList* info_list); |
| 1204 | 151 int emit_deopt_handler(); |
| 0 | 152 |
| 153 void emit_code(BlockList* hir); | |
| 154 void emit_block(BlockBegin* block); | |
| 155 void emit_lir_list(LIR_List* list); | |
| 156 | |
| 157 // any last minute peephole optimizations are performed here. In | |
| 158 // particular sparc uses this for delay slot filling. | |
| 159 void peephole(LIR_List* list); | |
| 160 | |
| 161 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info); | |
| 162 | |
| 163 void return_op(LIR_Opr result); | |
| 164 | |
| 165 // returns offset of poll instruction | |
| 166 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info); | |
| 167 | |
| 168 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); | |
| 169 void const2stack(LIR_Opr src, LIR_Opr dest); | |
| 2002 | 170 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide); |
| 0 | 171 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); |
| 172 void reg2reg (LIR_Opr src, LIR_Opr dest); | |
| 2002 | 173 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, |
| 174 LIR_PatchCode patch_code, CodeEmitInfo* info, | |
| 175 bool pop_fpu_stack, bool wide, bool unaligned); | |
| 0 | 176 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); |
| 177 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); | |
| 178 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, | |
| 2002 | 179 LIR_PatchCode patch_code, |
| 180 CodeEmitInfo* info, bool wide, bool unaligned); | |
| 0 | 181 |
| 182 void prefetchr (LIR_Opr src); | |
| 183 void prefetchw (LIR_Opr src); | |
| 184 | |
| 185 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp); | |
| 186 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest); | |
| 187 | |
| 188 void move_regs(Register from_reg, Register to_reg); | |
| 189 void swap_reg(Register a, Register b); | |
| 190 | |
| 191 void emit_op0(LIR_Op0* op); | |
| 192 void emit_op1(LIR_Op1* op); | |
| 193 void emit_op2(LIR_Op2* op); | |
| 194 void emit_op3(LIR_Op3* op); | |
| 195 void emit_opBranch(LIR_OpBranch* op); | |
| 196 void emit_opLabel(LIR_OpLabel* op); | |
| 197 void emit_arraycopy(LIR_OpArrayCopy* op); | |
| 198 void emit_opConvert(LIR_OpConvert* op); | |
| 199 void emit_alloc_obj(LIR_OpAllocObj* op); | |
| 200 void emit_alloc_array(LIR_OpAllocArray* op); | |
| 201 void emit_opTypeCheck(LIR_OpTypeCheck* op); | |
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202 void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null); |
| 0 | 203 void emit_compare_and_swap(LIR_OpCompareAndSwap* op); |
| 204 void emit_lock(LIR_OpLock* op); | |
| 205 void emit_call(LIR_OpJavaCall* op); | |
| 206 void emit_rtcall(LIR_OpRTCall* op); | |
| 207 void emit_profile_call(LIR_OpProfileCall* op); | |
| 208 void emit_delay(LIR_OpDelay* op); | |
| 209 | |
| 210 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); | |
| 211 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); | |
| 212 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); | |
| 213 | |
| 214 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); | |
| 215 | |
| 216 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack); | |
| 217 void move_op(LIR_Opr src, LIR_Opr result, BasicType type, | |
| 2002 | 218 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide); |
| 0 | 219 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); |
| 220 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions | |
| 221 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); | |
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222 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); |
| 0 | 223 |
| 1295 | 224 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); |
| 225 void ic_call( LIR_OpJavaCall* op); | |
| 226 void vtable_call( LIR_OpJavaCall* op); | |
| 227 | |
| 0 | 228 void osr_entry(); |
| 229 | |
| 230 void build_frame(); | |
| 231 | |
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232 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info); |
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233 void unwind_op(LIR_Opr exceptionOop); |
| 0 | 234 void monitor_address(int monitor_ix, LIR_Opr dst); |
| 235 | |
| 236 void align_backward_branch_target(); | |
| 237 void align_call(LIR_Code code); | |
| 238 | |
| 239 void negate(LIR_Opr left, LIR_Opr dest); | |
| 240 void leal(LIR_Opr left, LIR_Opr dest); | |
| 241 | |
| 242 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info); | |
| 243 | |
| 244 void membar(); | |
| 245 void membar_acquire(); | |
| 246 void membar_release(); | |
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247 void membar_loadload(); |
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248 void membar_storestore(); |
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249 void membar_loadstore(); |
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250 void membar_storeload(); |
| 0 | 251 void get_thread(LIR_Opr result); |
| 252 | |
| 253 void verify_oop_map(CodeEmitInfo* info); | |
| 254 | |
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255 void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp); |
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256 |
| 1972 | 257 #ifdef TARGET_ARCH_x86 |
| 258 # include "c1_LIRAssembler_x86.hpp" | |
| 259 #endif | |
| 260 #ifdef TARGET_ARCH_sparc | |
| 261 # include "c1_LIRAssembler_sparc.hpp" | |
| 262 #endif | |
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263 #ifdef TARGET_ARCH_arm |
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264 # include "c1_LIRAssembler_arm.hpp" |
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265 #endif |
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266 #ifdef TARGET_ARCH_ppc |
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267 # include "c1_LIRAssembler_ppc.hpp" |
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268 #endif |
| 1972 | 269 |
| 0 | 270 }; |
| 1972 | 271 |
| 272 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP |