Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86.ad @ 6438:bbf47e2d519f
Allow calls without a FrameState in the backend
author | Christian Wimmer <christian.wimmer@oracle.com> |
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date | Tue, 25 Sep 2012 09:20:18 -0700 |
parents | 2c368ea3e844 |
children | 006050192a5a |
rev | line source |
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4761 | 1 // |
4950 | 2 // Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. |
4761 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |
20 // or visit www.oracle.com if you need additional information or have any | |
21 // questions. | |
22 // | |
23 // | |
24 | |
25 // X86 Common Architecture Description File | |
26 | |
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------ |
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28 // This information is used by the matcher and the register allocator to |
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29 // describe individual registers and classes of registers within the target |
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30 // archtecture. |
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31 |
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32 register %{ |
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33 //----------Architecture Description Register Definitions---------------------- |
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34 // General Registers |
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35 // "reg_def" name ( register save type, C convention save type, |
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36 // ideal register type, encoding ); |
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37 // Register Save Types: |
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38 // |
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39 // NS = No-Save: The register allocator assumes that these registers |
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40 // can be used without saving upon entry to the method, & |
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41 // that they do not need to be saved at call sites. |
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42 // |
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43 // SOC = Save-On-Call: The register allocator assumes that these registers |
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44 // can be used without saving upon entry to the method, |
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45 // but that they must be saved at call sites. |
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46 // |
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47 // SOE = Save-On-Entry: The register allocator assumes that these registers |
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48 // must be saved before using them upon entry to the |
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49 // method, but they do not need to be saved at call |
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50 // sites. |
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51 // |
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52 // AS = Always-Save: The register allocator assumes that these registers |
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53 // must be saved before using them upon entry to the |
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54 // method, & that they must be saved at call sites. |
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55 // |
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56 // Ideal Register Type is used to determine how to save & restore a |
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57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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59 // |
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60 // The encoding number is the actual bit-pattern placed into the opcodes. |
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61 |
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62 // XMM registers. 256-bit registers or 8 words each, labeled (a)-h. |
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63 // Word a in each register holds a Float, words ab hold a Double. |
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64 // The whole registers are used in SSE4.2 version intrinsics, |
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65 // array copy stubs and superword operations (see UseSSE42Intrinsics, |
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66 // UseXMMForArrayCopy and UseSuperword flags). |
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67 // XMM8-XMM15 must be encoded with REX (VEX for UseAVX). |
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68 // Linux ABI: No register preserved across function calls |
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69 // XMM0-XMM7 might hold parameters |
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70 // Windows ABI: XMM6-XMM15 preserved across function calls |
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71 // XMM0-XMM3 might hold parameters |
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72 |
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73 reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); |
6225 | 74 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(1)); |
75 reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(2)); | |
76 reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(3)); | |
77 reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(4)); | |
78 reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(5)); | |
79 reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(6)); | |
80 reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(7)); | |
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81 |
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82 reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); |
6225 | 83 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(1)); |
84 reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(2)); | |
85 reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(3)); | |
86 reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(4)); | |
87 reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(5)); | |
88 reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(6)); | |
89 reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(7)); | |
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90 |
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91 reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); |
6225 | 92 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(1)); |
93 reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(2)); | |
94 reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(3)); | |
95 reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(4)); | |
96 reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(5)); | |
97 reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(6)); | |
98 reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(7)); | |
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99 |
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100 reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); |
6225 | 101 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(1)); |
102 reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(2)); | |
103 reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(3)); | |
104 reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(4)); | |
105 reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(5)); | |
106 reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(6)); | |
107 reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(7)); | |
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108 |
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109 reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); |
6225 | 110 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(1)); |
111 reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(2)); | |
112 reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(3)); | |
113 reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(4)); | |
114 reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(5)); | |
115 reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(6)); | |
116 reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(7)); | |
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117 |
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118 reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); |
6225 | 119 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(1)); |
120 reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(2)); | |
121 reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(3)); | |
122 reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(4)); | |
123 reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(5)); | |
124 reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(6)); | |
125 reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(7)); | |
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126 |
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127 #ifdef _WIN64 |
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128 |
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129 reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); |
6225 | 130 reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
131 reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(2)); | |
132 reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(3)); | |
133 reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(4)); | |
134 reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(5)); | |
135 reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(6)); | |
136 reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(7)); | |
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137 |
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138 reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); |
6225 | 139 reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
140 reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(2)); | |
141 reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(3)); | |
142 reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(4)); | |
143 reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(5)); | |
144 reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(6)); | |
145 reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(7)); | |
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146 |
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147 reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); |
6225 | 148 reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
149 reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(2)); | |
150 reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(3)); | |
151 reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(4)); | |
152 reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(5)); | |
153 reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(6)); | |
154 reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(7)); | |
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155 |
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156 reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); |
6225 | 157 reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
158 reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(2)); | |
159 reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(3)); | |
160 reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(4)); | |
161 reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(5)); | |
162 reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(6)); | |
163 reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(7)); | |
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164 |
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165 reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); |
6225 | 166 reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
167 reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(2)); | |
168 reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(3)); | |
169 reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(4)); | |
170 reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(5)); | |
171 reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(6)); | |
172 reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(7)); | |
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173 |
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174 reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); |
6225 | 175 reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
176 reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(2)); | |
177 reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(3)); | |
178 reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(4)); | |
179 reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(5)); | |
180 reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(6)); | |
181 reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(7)); | |
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182 |
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183 reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); |
6225 | 184 reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
185 reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(2)); | |
186 reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(3)); | |
187 reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(4)); | |
188 reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(5)); | |
189 reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(6)); | |
190 reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(7)); | |
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191 |
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192 reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); |
6225 | 193 reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
194 reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(2)); | |
195 reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(3)); | |
196 reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(4)); | |
197 reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(5)); | |
198 reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(6)); | |
199 reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(7)); | |
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200 |
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201 reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); |
6225 | 202 reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
203 reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(2)); | |
204 reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(3)); | |
205 reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(4)); | |
206 reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(5)); | |
207 reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(6)); | |
208 reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(7)); | |
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209 |
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210 reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); |
6225 | 211 reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
212 reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(2)); | |
213 reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(3)); | |
214 reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(4)); | |
215 reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(5)); | |
216 reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(6)); | |
217 reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(7)); | |
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218 |
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219 #else // _WIN64 |
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220 |
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221 reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); |
6225 | 222 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
223 reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(2)); | |
224 reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(3)); | |
225 reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(4)); | |
226 reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(5)); | |
227 reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(6)); | |
228 reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(7)); | |
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229 |
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230 reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); |
6225 | 231 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
232 reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(2)); | |
233 reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(3)); | |
234 reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(4)); | |
235 reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(5)); | |
236 reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(6)); | |
237 reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(7)); | |
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238 |
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239 #ifdef _LP64 |
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240 |
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241 reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); |
6225 | 242 reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
243 reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(2)); | |
244 reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(3)); | |
245 reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(4)); | |
246 reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(5)); | |
247 reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(6)); | |
248 reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(7)); | |
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249 |
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250 reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); |
6225 | 251 reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
252 reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(2)); | |
253 reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(3)); | |
254 reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(4)); | |
255 reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(5)); | |
256 reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(6)); | |
257 reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(7)); | |
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258 |
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259 reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); |
6225 | 260 reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
261 reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(2)); | |
262 reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(3)); | |
263 reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(4)); | |
264 reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(5)); | |
265 reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(6)); | |
266 reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(7)); | |
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267 |
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268 reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); |
6225 | 269 reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
270 reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(2)); | |
271 reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(3)); | |
272 reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(4)); | |
273 reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(5)); | |
274 reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(6)); | |
275 reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(7)); | |
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276 |
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277 reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); |
6225 | 278 reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
279 reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(2)); | |
280 reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(3)); | |
281 reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(4)); | |
282 reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(5)); | |
283 reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(6)); | |
284 reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(7)); | |
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285 |
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286 reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); |
6225 | 287 reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
288 reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(2)); | |
289 reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(3)); | |
290 reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(4)); | |
291 reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(5)); | |
292 reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(6)); | |
293 reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(7)); | |
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294 |
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295 reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); |
6225 | 296 reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
297 reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(2)); | |
298 reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(3)); | |
299 reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(4)); | |
300 reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(5)); | |
301 reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(6)); | |
302 reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(7)); | |
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303 |
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304 reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); |
6225 | 305 reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
306 reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(2)); | |
307 reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(3)); | |
308 reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(4)); | |
309 reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(5)); | |
310 reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(6)); | |
311 reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(7)); | |
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312 |
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313 #endif // _LP64 |
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314 |
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315 #endif // _WIN64 |
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316 |
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317 #ifdef _LP64 |
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318 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); |
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319 #else |
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320 reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); |
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321 #endif // _LP64 |
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322 |
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323 alloc_class chunk1(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
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324 XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
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325 XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
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326 XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
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327 XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
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328 XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
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329 XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
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330 XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
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331 #ifdef _LP64 |
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332 ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
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333 XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
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334 XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
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335 XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
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336 XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
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337 XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
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338 XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
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339 XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
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340 #endif |
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|
341 ); |
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|
342 |
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|
343 // flags allocation class should be last. |
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|
344 alloc_class chunk2(RFLAGS); |
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|
345 |
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|
346 // Singleton class for condition codes |
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|
347 reg_class int_flags(RFLAGS); |
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|
348 |
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|
349 // Class for all float registers |
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|
350 reg_class float_reg(XMM0, |
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|
351 XMM1, |
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|
352 XMM2, |
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|
353 XMM3, |
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|
354 XMM4, |
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kvn
parents:
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diff
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|
355 XMM5, |
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kvn
parents:
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diff
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|
356 XMM6, |
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|
357 XMM7 |
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|
358 #ifdef _LP64 |
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|
359 ,XMM8, |
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kvn
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|
360 XMM9, |
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kvn
parents:
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diff
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|
361 XMM10, |
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kvn
parents:
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|
362 XMM11, |
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kvn
parents:
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diff
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|
363 XMM12, |
8c92982cbbc4
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kvn
parents:
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|
364 XMM13, |
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kvn
parents:
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diff
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|
365 XMM14, |
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kvn
parents:
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|
366 XMM15 |
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367 #endif |
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|
368 ); |
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|
369 |
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370 // Class for all double registers |
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|
371 reg_class double_reg(XMM0, XMM0b, |
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372 XMM1, XMM1b, |
8c92982cbbc4
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kvn
parents:
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|
373 XMM2, XMM2b, |
8c92982cbbc4
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kvn
parents:
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diff
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|
374 XMM3, XMM3b, |
8c92982cbbc4
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kvn
parents:
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|
375 XMM4, XMM4b, |
8c92982cbbc4
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kvn
parents:
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diff
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|
376 XMM5, XMM5b, |
8c92982cbbc4
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kvn
parents:
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diff
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|
377 XMM6, XMM6b, |
8c92982cbbc4
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kvn
parents:
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|
378 XMM7, XMM7b |
8c92982cbbc4
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kvn
parents:
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|
379 #ifdef _LP64 |
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|
380 ,XMM8, XMM8b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
381 XMM9, XMM9b, |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
382 XMM10, XMM10b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
383 XMM11, XMM11b, |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
384 XMM12, XMM12b, |
8c92982cbbc4
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kvn
parents:
4950
diff
changeset
|
385 XMM13, XMM13b, |
8c92982cbbc4
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kvn
parents:
4950
diff
changeset
|
386 XMM14, XMM14b, |
8c92982cbbc4
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kvn
parents:
4950
diff
changeset
|
387 XMM15, XMM15b |
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kvn
parents:
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|
388 #endif |
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|
389 ); |
8c92982cbbc4
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kvn
parents:
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|
390 |
8c92982cbbc4
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kvn
parents:
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|
391 // Class for all 32bit vector registers |
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kvn
parents:
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|
392 reg_class vectors_reg(XMM0, |
8c92982cbbc4
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parents:
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|
393 XMM1, |
8c92982cbbc4
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kvn
parents:
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changeset
|
394 XMM2, |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
395 XMM3, |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
396 XMM4, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
397 XMM5, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
398 XMM6, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
399 XMM7 |
8c92982cbbc4
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kvn
parents:
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changeset
|
400 #ifdef _LP64 |
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|
401 ,XMM8, |
8c92982cbbc4
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kvn
parents:
4950
diff
changeset
|
402 XMM9, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
403 XMM10, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
404 XMM11, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
405 XMM12, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
406 XMM13, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
407 XMM14, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
408 XMM15 |
8c92982cbbc4
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kvn
parents:
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changeset
|
409 #endif |
8c92982cbbc4
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kvn
parents:
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|
410 ); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
411 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
412 // Class for all 64bit vector registers |
8c92982cbbc4
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kvn
parents:
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|
413 reg_class vectord_reg(XMM0, XMM0b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
414 XMM1, XMM1b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
415 XMM2, XMM2b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
416 XMM3, XMM3b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
417 XMM4, XMM4b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
418 XMM5, XMM5b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
419 XMM6, XMM6b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
420 XMM7, XMM7b |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
421 #ifdef _LP64 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
422 ,XMM8, XMM8b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
423 XMM9, XMM9b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
424 XMM10, XMM10b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
425 XMM11, XMM11b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
426 XMM12, XMM12b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
427 XMM13, XMM13b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
428 XMM14, XMM14b, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
429 XMM15, XMM15b |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
430 #endif |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
431 ); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
432 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
433 // Class for all 128bit vector registers |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
434 reg_class vectorx_reg(XMM0, XMM0b, XMM0c, XMM0d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
435 XMM1, XMM1b, XMM1c, XMM1d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
436 XMM2, XMM2b, XMM2c, XMM2d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
437 XMM3, XMM3b, XMM3c, XMM3d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
438 XMM4, XMM4b, XMM4c, XMM4d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
439 XMM5, XMM5b, XMM5c, XMM5d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
440 XMM6, XMM6b, XMM6c, XMM6d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
441 XMM7, XMM7b, XMM7c, XMM7d |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
442 #ifdef _LP64 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
443 ,XMM8, XMM8b, XMM8c, XMM8d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
444 XMM9, XMM9b, XMM9c, XMM9d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
445 XMM10, XMM10b, XMM10c, XMM10d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
446 XMM11, XMM11b, XMM11c, XMM11d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
447 XMM12, XMM12b, XMM12c, XMM12d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
448 XMM13, XMM13b, XMM13c, XMM13d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
449 XMM14, XMM14b, XMM14c, XMM14d, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
450 XMM15, XMM15b, XMM15c, XMM15d |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
451 #endif |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
452 ); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
453 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
454 // Class for all 256bit vector registers |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
455 reg_class vectory_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
456 XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
457 XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
458 XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
459 XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
460 XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
461 XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
462 XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
463 #ifdef _LP64 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
464 ,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
465 XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
changeset
|
466 XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4950
diff
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|
467 XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
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468 XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
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469 XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
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470 XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
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471 XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
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472 #endif |
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473 ); |
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474 |
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475 %} |
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476 |
4761 | 477 source %{ |
478 // Float masks come from different places depending on platform. | |
479 #ifdef _LP64 | |
480 static address float_signmask() { return StubRoutines::x86::float_sign_mask(); } | |
481 static address float_signflip() { return StubRoutines::x86::float_sign_flip(); } | |
482 static address double_signmask() { return StubRoutines::x86::double_sign_mask(); } | |
483 static address double_signflip() { return StubRoutines::x86::double_sign_flip(); } | |
484 #else | |
485 static address float_signmask() { return (address)float_signmask_pool; } | |
486 static address float_signflip() { return (address)float_signflip_pool; } | |
487 static address double_signmask() { return (address)double_signmask_pool; } | |
488 static address double_signflip() { return (address)double_signflip_pool; } | |
489 #endif | |
4950 | 490 |
6179
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491 // Map Types to machine register types |
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492 const int Matcher::base2reg[Type::lastype] = { |
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493 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN, |
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494 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */ |
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495 Op_VecS, Op_VecD, Op_VecX, Op_VecY, /* Vectors */ |
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496 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */ |
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497 0, 0/*abio*/, |
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498 Op_RegP /* Return address */, 0, /* the memories */ |
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499 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD, |
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500 0 /*bottom*/ |
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501 }; |
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502 |
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503 // Max vector size in bytes. 0 if not supported. |
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504 const int Matcher::vector_width_in_bytes(BasicType bt) { |
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505 assert(is_java_primitive(bt), "only primitive type vectors"); |
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506 if (UseSSE < 2) return 0; |
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507 // SSE2 supports 128bit vectors for all types. |
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508 // AVX2 supports 256bit vectors for all types. |
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509 int size = (UseAVX > 1) ? 32 : 16; |
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510 // AVX1 supports 256bit vectors only for FLOAT and DOUBLE. |
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511 if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE)) |
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512 size = 32; |
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513 // Use flag to limit vector size. |
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514 size = MIN2(size,(int)MaxVectorSize); |
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515 // Minimum 2 values in vector (or 4 for bytes). |
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516 switch (bt) { |
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517 case T_DOUBLE: |
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518 case T_LONG: |
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519 if (size < 16) return 0; |
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520 case T_FLOAT: |
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521 case T_INT: |
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522 if (size < 8) return 0; |
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523 case T_BOOLEAN: |
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524 case T_BYTE: |
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525 case T_CHAR: |
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526 case T_SHORT: |
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527 if (size < 4) return 0; |
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528 break; |
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529 default: |
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530 ShouldNotReachHere(); |
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531 } |
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532 return size; |
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533 } |
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534 |
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535 // Limits on vector size (number of elements) loaded into vector. |
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536 const int Matcher::max_vector_size(const BasicType bt) { |
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537 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
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538 } |
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539 const int Matcher::min_vector_size(const BasicType bt) { |
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540 int max_size = max_vector_size(bt); |
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541 // Min size which can be loaded into vector is 4 bytes. |
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542 int size = (type2aelembytes(bt) == 1) ? 4 : 2; |
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543 return MIN2(size,max_size); |
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544 } |
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545 |
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546 // Vector ideal reg corresponding to specidied size in bytes |
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547 const int Matcher::vector_ideal_reg(int size) { |
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548 assert(MaxVectorSize >= size, ""); |
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549 switch(size) { |
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550 case 4: return Op_VecS; |
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551 case 8: return Op_VecD; |
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552 case 16: return Op_VecX; |
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553 case 32: return Op_VecY; |
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554 } |
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555 ShouldNotReachHere(); |
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556 return 0; |
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|
557 } |
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558 |
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559 // x86 supports misaligned vectors store/load. |
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560 const bool Matcher::misaligned_vectors_ok() { |
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561 return !AlignVector; // can be changed by flag |
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562 } |
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563 |
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564 // Helper methods for MachSpillCopyNode::implementation(). |
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565 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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566 int src_hi, int dst_hi, uint ireg, outputStream* st) { |
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567 // In 64-bit VM size calculation is very complex. Emitting instructions |
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568 // into scratch buffer is used to get size in 64-bit VM. |
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569 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
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570 assert(ireg == Op_VecS || // 32bit vector |
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571 (src_lo & 1) == 0 && (src_lo + 1) == src_hi && |
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572 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi, |
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573 "no non-adjacent vector moves" ); |
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574 if (cbuf) { |
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575 MacroAssembler _masm(cbuf); |
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576 int offset = __ offset(); |
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577 switch (ireg) { |
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578 case Op_VecS: // copy whole register |
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579 case Op_VecD: |
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580 case Op_VecX: |
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581 __ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
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582 break; |
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583 case Op_VecY: |
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584 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
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585 break; |
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586 default: |
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587 ShouldNotReachHere(); |
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588 } |
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589 int size = __ offset() - offset; |
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590 #ifdef ASSERT |
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591 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
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592 assert(!do_size || size == 4, "incorrect size calculattion"); |
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593 #endif |
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594 return size; |
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595 #ifndef PRODUCT |
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596 } else if (!do_size) { |
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597 switch (ireg) { |
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598 case Op_VecS: |
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599 case Op_VecD: |
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600 case Op_VecX: |
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601 st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
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602 break; |
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603 case Op_VecY: |
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|
604 st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
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|
605 break; |
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|
606 default: |
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|
607 ShouldNotReachHere(); |
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parents:
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|
608 } |
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diff
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|
609 #endif |
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|
610 } |
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|
611 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
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|
612 return 4; |
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parents:
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|
613 } |
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diff
changeset
|
614 |
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|
615 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
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616 int stack_offset, int reg, uint ireg, outputStream* st) { |
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617 // In 64-bit VM size calculation is very complex. Emitting instructions |
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618 // into scratch buffer is used to get size in 64-bit VM. |
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619 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
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620 if (cbuf) { |
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621 MacroAssembler _masm(cbuf); |
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622 int offset = __ offset(); |
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|
623 if (is_load) { |
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|
624 switch (ireg) { |
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|
625 case Op_VecS: |
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|
626 __ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
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|
627 break; |
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|
628 case Op_VecD: |
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|
629 __ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
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|
630 break; |
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|
631 case Op_VecX: |
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|
632 __ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
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|
633 break; |
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|
634 case Op_VecY: |
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635 __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
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|
636 break; |
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|
637 default: |
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|
638 ShouldNotReachHere(); |
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|
639 } |
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|
640 } else { // store |
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|
641 switch (ireg) { |
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|
642 case Op_VecS: |
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|
643 __ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
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|
644 break; |
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|
645 case Op_VecD: |
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|
646 __ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
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|
647 break; |
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|
648 case Op_VecX: |
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|
649 __ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
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|
650 break; |
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|
651 case Op_VecY: |
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|
652 __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
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|
653 break; |
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parents:
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|
654 default: |
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changeset
|
655 ShouldNotReachHere(); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
656 } |
8c92982cbbc4
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|
657 } |
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|
658 int size = __ offset() - offset; |
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changeset
|
659 #ifdef ASSERT |
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|
660 int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
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661 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
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662 assert(!do_size || size == (5+offset_size), "incorrect size calculattion"); |
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|
663 #endif |
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|
664 return size; |
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|
665 #ifndef PRODUCT |
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|
666 } else if (!do_size) { |
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|
667 if (is_load) { |
8c92982cbbc4
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|
668 switch (ireg) { |
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|
669 case Op_VecS: |
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|
670 st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
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|
671 break; |
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changeset
|
672 case Op_VecD: |
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|
673 st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
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7119644: Increase superword's vector size up to 256 bits
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parents:
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|
674 break; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
675 case Op_VecX: |
8c92982cbbc4
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|
676 st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
677 break; |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
678 case Op_VecY: |
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kvn
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|
679 st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
680 break; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
681 default: |
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kvn
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changeset
|
682 ShouldNotReachHere(); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
683 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
684 } else { // store |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
685 switch (ireg) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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diff
changeset
|
686 case Op_VecS: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
687 st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
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7119644: Increase superword's vector size up to 256 bits
kvn
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|
688 break; |
8c92982cbbc4
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kvn
parents:
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diff
changeset
|
689 case Op_VecD: |
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kvn
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|
690 st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
691 break; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
692 case Op_VecX: |
8c92982cbbc4
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kvn
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|
693 st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
694 break; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
695 case Op_VecY: |
8c92982cbbc4
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kvn
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|
696 st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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changeset
|
697 break; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
698 default: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
699 ShouldNotReachHere(); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
700 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
701 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
702 #endif |
8c92982cbbc4
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kvn
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|
703 } |
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|
704 int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
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|
705 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
706 return 5+offset_size; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
707 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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diff
changeset
|
708 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
709 static inline jfloat replicate4_imm(int con, int width) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
710 // Load a constant of "width" (in bytes) and replicate it to fill 32bit. |
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|
711 assert(width == 1 || width == 2, "only byte or short types here"); |
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7119644: Increase superword's vector size up to 256 bits
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|
712 int bit_width = width * 8; |
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7119644: Increase superword's vector size up to 256 bits
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|
713 jint val = con; |
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7119644: Increase superword's vector size up to 256 bits
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|
714 val &= (1 << bit_width) - 1; // mask off sign bits |
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changeset
|
715 while(bit_width < 32) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
716 val |= (val << bit_width); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
717 bit_width <<= 1; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
718 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
719 jfloat fval = *((jfloat*) &val); // coerce to float type |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
720 return fval; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
721 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
722 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
723 static inline jdouble replicate8_imm(int con, int width) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
724 // Load a constant of "width" (in bytes) and replicate it to fill 64bit. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
725 assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here"); |
8c92982cbbc4
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|
726 int bit_width = width * 8; |
8c92982cbbc4
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|
727 jlong val = con; |
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|
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
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changeset
|
729 while(bit_width < 64) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
730 val |= (val << bit_width); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
731 bit_width <<= 1; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
changeset
|
732 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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733 jdouble dval = *((jdouble*) &val); // coerce to double type |
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734 return dval; |
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735 } |
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736 |
4950 | 737 #ifndef PRODUCT |
738 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const { | |
739 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
740 } | |
741 #endif | |
742 | |
743 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const { | |
744 MacroAssembler _masm(&cbuf); | |
745 __ nop(_count); | |
746 } | |
747 | |
748 uint MachNopNode::size(PhaseRegAlloc*) const { | |
749 return _count; | |
750 } | |
751 | |
752 #ifndef PRODUCT | |
753 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const { | |
754 st->print("# breakpoint"); | |
755 } | |
756 #endif | |
757 | |
758 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const { | |
759 MacroAssembler _masm(&cbuf); | |
760 __ int3(); | |
761 } | |
762 | |
763 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { | |
764 return MachNode::size(ra_); | |
765 } | |
766 | |
767 %} | |
768 | |
769 encode %{ | |
770 | |
771 enc_class preserve_SP %{ | |
772 debug_only(int off0 = cbuf.insts_size()); | |
773 MacroAssembler _masm(&cbuf); | |
774 // RBP is preserved across all calls, even compiled calls. | |
775 // Use it to preserve RSP in places where the callee might change the SP. | |
776 __ movptr(rbp_mh_SP_save, rsp); | |
777 debug_only(int off1 = cbuf.insts_size()); | |
778 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); | |
779 %} | |
780 | |
781 enc_class restore_SP %{ | |
782 MacroAssembler _masm(&cbuf); | |
783 __ movptr(rsp, rbp_mh_SP_save); | |
784 %} | |
785 | |
786 enc_class call_epilog %{ | |
787 if (VerifyStackAtCalls) { | |
788 // Check that stack depth is unchanged: find majik cookie on stack | |
789 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); | |
790 MacroAssembler _masm(&cbuf); | |
791 Label L; | |
792 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d); | |
793 __ jccb(Assembler::equal, L); | |
794 // Die if stack mismatch | |
795 __ int3(); | |
796 __ bind(L); | |
797 } | |
798 %} | |
799 | |
4761 | 800 %} |
801 | |
6179
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802 |
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803 //----------OPERANDS----------------------------------------------------------- |
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804 // Operand definitions must precede instruction definitions for correct parsing |
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805 // in the ADLC because operands constitute user defined types which are used in |
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806 // instruction definitions. |
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807 |
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808 // Vectors |
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809 operand vecS() %{ |
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810 constraint(ALLOC_IN_RC(vectors_reg)); |
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811 match(VecS); |
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812 |
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813 format %{ %} |
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814 interface(REG_INTER); |
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815 %} |
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816 |
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817 operand vecD() %{ |
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818 constraint(ALLOC_IN_RC(vectord_reg)); |
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819 match(VecD); |
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820 |
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821 format %{ %} |
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822 interface(REG_INTER); |
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823 %} |
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824 |
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825 operand vecX() %{ |
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826 constraint(ALLOC_IN_RC(vectorx_reg)); |
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827 match(VecX); |
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828 |
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829 format %{ %} |
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830 interface(REG_INTER); |
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831 %} |
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832 |
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833 operand vecY() %{ |
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834 constraint(ALLOC_IN_RC(vectory_reg)); |
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835 match(VecY); |
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836 |
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837 format %{ %} |
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838 interface(REG_INTER); |
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839 %} |
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840 |
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841 |
4761 | 842 // INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit) |
843 | |
4950 | 844 // ============================================================================ |
845 | |
846 instruct ShouldNotReachHere() %{ | |
847 match(Halt); | |
848 format %{ "int3\t# ShouldNotReachHere" %} | |
849 ins_encode %{ | |
850 __ int3(); | |
851 %} | |
852 ins_pipe(pipe_slow); | |
853 %} | |
854 | |
855 // ============================================================================ | |
856 | |
4761 | 857 instruct addF_reg(regF dst, regF src) %{ |
858 predicate((UseSSE>=1) && (UseAVX == 0)); | |
859 match(Set dst (AddF dst src)); | |
860 | |
861 format %{ "addss $dst, $src" %} | |
862 ins_cost(150); | |
863 ins_encode %{ | |
864 __ addss($dst$$XMMRegister, $src$$XMMRegister); | |
865 %} | |
866 ins_pipe(pipe_slow); | |
867 %} | |
868 | |
869 instruct addF_mem(regF dst, memory src) %{ | |
870 predicate((UseSSE>=1) && (UseAVX == 0)); | |
871 match(Set dst (AddF dst (LoadF src))); | |
872 | |
873 format %{ "addss $dst, $src" %} | |
874 ins_cost(150); | |
875 ins_encode %{ | |
876 __ addss($dst$$XMMRegister, $src$$Address); | |
877 %} | |
878 ins_pipe(pipe_slow); | |
879 %} | |
880 | |
881 instruct addF_imm(regF dst, immF con) %{ | |
882 predicate((UseSSE>=1) && (UseAVX == 0)); | |
883 match(Set dst (AddF dst con)); | |
884 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
885 ins_cost(150); | |
886 ins_encode %{ | |
887 __ addss($dst$$XMMRegister, $constantaddress($con)); | |
888 %} | |
889 ins_pipe(pipe_slow); | |
890 %} | |
891 | |
6225 | 892 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ |
4761 | 893 predicate(UseAVX > 0); |
894 match(Set dst (AddF src1 src2)); | |
895 | |
896 format %{ "vaddss $dst, $src1, $src2" %} | |
897 ins_cost(150); | |
898 ins_encode %{ | |
899 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
900 %} | |
901 ins_pipe(pipe_slow); | |
902 %} | |
903 | |
6225 | 904 instruct addF_reg_mem(regF dst, regF src1, memory src2) %{ |
4761 | 905 predicate(UseAVX > 0); |
906 match(Set dst (AddF src1 (LoadF src2))); | |
907 | |
908 format %{ "vaddss $dst, $src1, $src2" %} | |
909 ins_cost(150); | |
910 ins_encode %{ | |
911 __ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
912 %} | |
913 ins_pipe(pipe_slow); | |
914 %} | |
915 | |
6225 | 916 instruct addF_reg_imm(regF dst, regF src, immF con) %{ |
4761 | 917 predicate(UseAVX > 0); |
918 match(Set dst (AddF src con)); | |
919 | |
920 format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} | |
921 ins_cost(150); | |
922 ins_encode %{ | |
923 __ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
924 %} | |
925 ins_pipe(pipe_slow); | |
926 %} | |
927 | |
928 instruct addD_reg(regD dst, regD src) %{ | |
929 predicate((UseSSE>=2) && (UseAVX == 0)); | |
930 match(Set dst (AddD dst src)); | |
931 | |
932 format %{ "addsd $dst, $src" %} | |
933 ins_cost(150); | |
934 ins_encode %{ | |
935 __ addsd($dst$$XMMRegister, $src$$XMMRegister); | |
936 %} | |
937 ins_pipe(pipe_slow); | |
938 %} | |
939 | |
940 instruct addD_mem(regD dst, memory src) %{ | |
941 predicate((UseSSE>=2) && (UseAVX == 0)); | |
942 match(Set dst (AddD dst (LoadD src))); | |
943 | |
944 format %{ "addsd $dst, $src" %} | |
945 ins_cost(150); | |
946 ins_encode %{ | |
947 __ addsd($dst$$XMMRegister, $src$$Address); | |
948 %} | |
949 ins_pipe(pipe_slow); | |
950 %} | |
951 | |
952 instruct addD_imm(regD dst, immD con) %{ | |
953 predicate((UseSSE>=2) && (UseAVX == 0)); | |
954 match(Set dst (AddD dst con)); | |
955 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
956 ins_cost(150); | |
957 ins_encode %{ | |
958 __ addsd($dst$$XMMRegister, $constantaddress($con)); | |
959 %} | |
960 ins_pipe(pipe_slow); | |
961 %} | |
962 | |
6225 | 963 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ |
4761 | 964 predicate(UseAVX > 0); |
965 match(Set dst (AddD src1 src2)); | |
966 | |
967 format %{ "vaddsd $dst, $src1, $src2" %} | |
968 ins_cost(150); | |
969 ins_encode %{ | |
970 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
971 %} | |
972 ins_pipe(pipe_slow); | |
973 %} | |
974 | |
6225 | 975 instruct addD_reg_mem(regD dst, regD src1, memory src2) %{ |
4761 | 976 predicate(UseAVX > 0); |
977 match(Set dst (AddD src1 (LoadD src2))); | |
978 | |
979 format %{ "vaddsd $dst, $src1, $src2" %} | |
980 ins_cost(150); | |
981 ins_encode %{ | |
982 __ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
983 %} | |
984 ins_pipe(pipe_slow); | |
985 %} | |
986 | |
6225 | 987 instruct addD_reg_imm(regD dst, regD src, immD con) %{ |
4761 | 988 predicate(UseAVX > 0); |
989 match(Set dst (AddD src con)); | |
990 | |
991 format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} | |
992 ins_cost(150); | |
993 ins_encode %{ | |
994 __ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
995 %} | |
996 ins_pipe(pipe_slow); | |
997 %} | |
998 | |
999 instruct subF_reg(regF dst, regF src) %{ | |
1000 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1001 match(Set dst (SubF dst src)); | |
1002 | |
1003 format %{ "subss $dst, $src" %} | |
1004 ins_cost(150); | |
1005 ins_encode %{ | |
1006 __ subss($dst$$XMMRegister, $src$$XMMRegister); | |
1007 %} | |
1008 ins_pipe(pipe_slow); | |
1009 %} | |
1010 | |
1011 instruct subF_mem(regF dst, memory src) %{ | |
1012 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1013 match(Set dst (SubF dst (LoadF src))); | |
1014 | |
1015 format %{ "subss $dst, $src" %} | |
1016 ins_cost(150); | |
1017 ins_encode %{ | |
1018 __ subss($dst$$XMMRegister, $src$$Address); | |
1019 %} | |
1020 ins_pipe(pipe_slow); | |
1021 %} | |
1022 | |
1023 instruct subF_imm(regF dst, immF con) %{ | |
1024 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1025 match(Set dst (SubF dst con)); | |
1026 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
1027 ins_cost(150); | |
1028 ins_encode %{ | |
1029 __ subss($dst$$XMMRegister, $constantaddress($con)); | |
1030 %} | |
1031 ins_pipe(pipe_slow); | |
1032 %} | |
1033 | |
6225 | 1034 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ |
4761 | 1035 predicate(UseAVX > 0); |
1036 match(Set dst (SubF src1 src2)); | |
1037 | |
1038 format %{ "vsubss $dst, $src1, $src2" %} | |
1039 ins_cost(150); | |
1040 ins_encode %{ | |
1041 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1042 %} | |
1043 ins_pipe(pipe_slow); | |
1044 %} | |
1045 | |
6225 | 1046 instruct subF_reg_mem(regF dst, regF src1, memory src2) %{ |
4761 | 1047 predicate(UseAVX > 0); |
1048 match(Set dst (SubF src1 (LoadF src2))); | |
1049 | |
1050 format %{ "vsubss $dst, $src1, $src2" %} | |
1051 ins_cost(150); | |
1052 ins_encode %{ | |
1053 __ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1054 %} | |
1055 ins_pipe(pipe_slow); | |
1056 %} | |
1057 | |
6225 | 1058 instruct subF_reg_imm(regF dst, regF src, immF con) %{ |
4761 | 1059 predicate(UseAVX > 0); |
1060 match(Set dst (SubF src con)); | |
1061 | |
1062 format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} | |
1063 ins_cost(150); | |
1064 ins_encode %{ | |
1065 __ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1066 %} | |
1067 ins_pipe(pipe_slow); | |
1068 %} | |
1069 | |
1070 instruct subD_reg(regD dst, regD src) %{ | |
1071 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1072 match(Set dst (SubD dst src)); | |
1073 | |
1074 format %{ "subsd $dst, $src" %} | |
1075 ins_cost(150); | |
1076 ins_encode %{ | |
1077 __ subsd($dst$$XMMRegister, $src$$XMMRegister); | |
1078 %} | |
1079 ins_pipe(pipe_slow); | |
1080 %} | |
1081 | |
1082 instruct subD_mem(regD dst, memory src) %{ | |
1083 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1084 match(Set dst (SubD dst (LoadD src))); | |
1085 | |
1086 format %{ "subsd $dst, $src" %} | |
1087 ins_cost(150); | |
1088 ins_encode %{ | |
1089 __ subsd($dst$$XMMRegister, $src$$Address); | |
1090 %} | |
1091 ins_pipe(pipe_slow); | |
1092 %} | |
1093 | |
1094 instruct subD_imm(regD dst, immD con) %{ | |
1095 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1096 match(Set dst (SubD dst con)); | |
1097 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
1098 ins_cost(150); | |
1099 ins_encode %{ | |
1100 __ subsd($dst$$XMMRegister, $constantaddress($con)); | |
1101 %} | |
1102 ins_pipe(pipe_slow); | |
1103 %} | |
1104 | |
6225 | 1105 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ |
4761 | 1106 predicate(UseAVX > 0); |
1107 match(Set dst (SubD src1 src2)); | |
1108 | |
1109 format %{ "vsubsd $dst, $src1, $src2" %} | |
1110 ins_cost(150); | |
1111 ins_encode %{ | |
1112 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1113 %} | |
1114 ins_pipe(pipe_slow); | |
1115 %} | |
1116 | |
6225 | 1117 instruct subD_reg_mem(regD dst, regD src1, memory src2) %{ |
4761 | 1118 predicate(UseAVX > 0); |
1119 match(Set dst (SubD src1 (LoadD src2))); | |
1120 | |
1121 format %{ "vsubsd $dst, $src1, $src2" %} | |
1122 ins_cost(150); | |
1123 ins_encode %{ | |
1124 __ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1125 %} | |
1126 ins_pipe(pipe_slow); | |
1127 %} | |
1128 | |
6225 | 1129 instruct subD_reg_imm(regD dst, regD src, immD con) %{ |
4761 | 1130 predicate(UseAVX > 0); |
1131 match(Set dst (SubD src con)); | |
1132 | |
1133 format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} | |
1134 ins_cost(150); | |
1135 ins_encode %{ | |
1136 __ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1137 %} | |
1138 ins_pipe(pipe_slow); | |
1139 %} | |
1140 | |
1141 instruct mulF_reg(regF dst, regF src) %{ | |
1142 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1143 match(Set dst (MulF dst src)); | |
1144 | |
1145 format %{ "mulss $dst, $src" %} | |
1146 ins_cost(150); | |
1147 ins_encode %{ | |
1148 __ mulss($dst$$XMMRegister, $src$$XMMRegister); | |
1149 %} | |
1150 ins_pipe(pipe_slow); | |
1151 %} | |
1152 | |
1153 instruct mulF_mem(regF dst, memory src) %{ | |
1154 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1155 match(Set dst (MulF dst (LoadF src))); | |
1156 | |
1157 format %{ "mulss $dst, $src" %} | |
1158 ins_cost(150); | |
1159 ins_encode %{ | |
1160 __ mulss($dst$$XMMRegister, $src$$Address); | |
1161 %} | |
1162 ins_pipe(pipe_slow); | |
1163 %} | |
1164 | |
1165 instruct mulF_imm(regF dst, immF con) %{ | |
1166 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1167 match(Set dst (MulF dst con)); | |
1168 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
1169 ins_cost(150); | |
1170 ins_encode %{ | |
1171 __ mulss($dst$$XMMRegister, $constantaddress($con)); | |
1172 %} | |
1173 ins_pipe(pipe_slow); | |
1174 %} | |
1175 | |
6225 | 1176 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ |
4761 | 1177 predicate(UseAVX > 0); |
1178 match(Set dst (MulF src1 src2)); | |
1179 | |
1180 format %{ "vmulss $dst, $src1, $src2" %} | |
1181 ins_cost(150); | |
1182 ins_encode %{ | |
1183 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1184 %} | |
1185 ins_pipe(pipe_slow); | |
1186 %} | |
1187 | |
6225 | 1188 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ |
4761 | 1189 predicate(UseAVX > 0); |
1190 match(Set dst (MulF src1 (LoadF src2))); | |
1191 | |
1192 format %{ "vmulss $dst, $src1, $src2" %} | |
1193 ins_cost(150); | |
1194 ins_encode %{ | |
1195 __ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1196 %} | |
1197 ins_pipe(pipe_slow); | |
1198 %} | |
1199 | |
6225 | 1200 instruct mulF_reg_imm(regF dst, regF src, immF con) %{ |
4761 | 1201 predicate(UseAVX > 0); |
1202 match(Set dst (MulF src con)); | |
1203 | |
1204 format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} | |
1205 ins_cost(150); | |
1206 ins_encode %{ | |
1207 __ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1208 %} | |
1209 ins_pipe(pipe_slow); | |
1210 %} | |
1211 | |
1212 instruct mulD_reg(regD dst, regD src) %{ | |
1213 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1214 match(Set dst (MulD dst src)); | |
1215 | |
1216 format %{ "mulsd $dst, $src" %} | |
1217 ins_cost(150); | |
1218 ins_encode %{ | |
1219 __ mulsd($dst$$XMMRegister, $src$$XMMRegister); | |
1220 %} | |
1221 ins_pipe(pipe_slow); | |
1222 %} | |
1223 | |
1224 instruct mulD_mem(regD dst, memory src) %{ | |
1225 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1226 match(Set dst (MulD dst (LoadD src))); | |
1227 | |
1228 format %{ "mulsd $dst, $src" %} | |
1229 ins_cost(150); | |
1230 ins_encode %{ | |
1231 __ mulsd($dst$$XMMRegister, $src$$Address); | |
1232 %} | |
1233 ins_pipe(pipe_slow); | |
1234 %} | |
1235 | |
1236 instruct mulD_imm(regD dst, immD con) %{ | |
1237 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1238 match(Set dst (MulD dst con)); | |
1239 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
1240 ins_cost(150); | |
1241 ins_encode %{ | |
1242 __ mulsd($dst$$XMMRegister, $constantaddress($con)); | |
1243 %} | |
1244 ins_pipe(pipe_slow); | |
1245 %} | |
1246 | |
6225 | 1247 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ |
4761 | 1248 predicate(UseAVX > 0); |
1249 match(Set dst (MulD src1 src2)); | |
1250 | |
1251 format %{ "vmulsd $dst, $src1, $src2" %} | |
1252 ins_cost(150); | |
1253 ins_encode %{ | |
1254 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1255 %} | |
1256 ins_pipe(pipe_slow); | |
1257 %} | |
1258 | |
6225 | 1259 instruct mulD_reg_mem(regD dst, regD src1, memory src2) %{ |
4761 | 1260 predicate(UseAVX > 0); |
1261 match(Set dst (MulD src1 (LoadD src2))); | |
1262 | |
1263 format %{ "vmulsd $dst, $src1, $src2" %} | |
1264 ins_cost(150); | |
1265 ins_encode %{ | |
1266 __ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1267 %} | |
1268 ins_pipe(pipe_slow); | |
1269 %} | |
1270 | |
6225 | 1271 instruct mulD_reg_imm(regD dst, regD src, immD con) %{ |
4761 | 1272 predicate(UseAVX > 0); |
1273 match(Set dst (MulD src con)); | |
1274 | |
1275 format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} | |
1276 ins_cost(150); | |
1277 ins_encode %{ | |
1278 __ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1279 %} | |
1280 ins_pipe(pipe_slow); | |
1281 %} | |
1282 | |
1283 instruct divF_reg(regF dst, regF src) %{ | |
1284 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1285 match(Set dst (DivF dst src)); | |
1286 | |
1287 format %{ "divss $dst, $src" %} | |
1288 ins_cost(150); | |
1289 ins_encode %{ | |
1290 __ divss($dst$$XMMRegister, $src$$XMMRegister); | |
1291 %} | |
1292 ins_pipe(pipe_slow); | |
1293 %} | |
1294 | |
1295 instruct divF_mem(regF dst, memory src) %{ | |
1296 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1297 match(Set dst (DivF dst (LoadF src))); | |
1298 | |
1299 format %{ "divss $dst, $src" %} | |
1300 ins_cost(150); | |
1301 ins_encode %{ | |
1302 __ divss($dst$$XMMRegister, $src$$Address); | |
1303 %} | |
1304 ins_pipe(pipe_slow); | |
1305 %} | |
1306 | |
1307 instruct divF_imm(regF dst, immF con) %{ | |
1308 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1309 match(Set dst (DivF dst con)); | |
1310 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
1311 ins_cost(150); | |
1312 ins_encode %{ | |
1313 __ divss($dst$$XMMRegister, $constantaddress($con)); | |
1314 %} | |
1315 ins_pipe(pipe_slow); | |
1316 %} | |
1317 | |
6225 | 1318 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ |
4761 | 1319 predicate(UseAVX > 0); |
1320 match(Set dst (DivF src1 src2)); | |
1321 | |
1322 format %{ "vdivss $dst, $src1, $src2" %} | |
1323 ins_cost(150); | |
1324 ins_encode %{ | |
1325 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1326 %} | |
1327 ins_pipe(pipe_slow); | |
1328 %} | |
1329 | |
6225 | 1330 instruct divF_reg_mem(regF dst, regF src1, memory src2) %{ |
4761 | 1331 predicate(UseAVX > 0); |
1332 match(Set dst (DivF src1 (LoadF src2))); | |
1333 | |
1334 format %{ "vdivss $dst, $src1, $src2" %} | |
1335 ins_cost(150); | |
1336 ins_encode %{ | |
1337 __ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1338 %} | |
1339 ins_pipe(pipe_slow); | |
1340 %} | |
1341 | |
6225 | 1342 instruct divF_reg_imm(regF dst, regF src, immF con) %{ |
4761 | 1343 predicate(UseAVX > 0); |
1344 match(Set dst (DivF src con)); | |
1345 | |
1346 format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} | |
1347 ins_cost(150); | |
1348 ins_encode %{ | |
1349 __ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1350 %} | |
1351 ins_pipe(pipe_slow); | |
1352 %} | |
1353 | |
1354 instruct divD_reg(regD dst, regD src) %{ | |
1355 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1356 match(Set dst (DivD dst src)); | |
1357 | |
1358 format %{ "divsd $dst, $src" %} | |
1359 ins_cost(150); | |
1360 ins_encode %{ | |
1361 __ divsd($dst$$XMMRegister, $src$$XMMRegister); | |
1362 %} | |
1363 ins_pipe(pipe_slow); | |
1364 %} | |
1365 | |
1366 instruct divD_mem(regD dst, memory src) %{ | |
1367 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1368 match(Set dst (DivD dst (LoadD src))); | |
1369 | |
1370 format %{ "divsd $dst, $src" %} | |
1371 ins_cost(150); | |
1372 ins_encode %{ | |
1373 __ divsd($dst$$XMMRegister, $src$$Address); | |
1374 %} | |
1375 ins_pipe(pipe_slow); | |
1376 %} | |
1377 | |
1378 instruct divD_imm(regD dst, immD con) %{ | |
1379 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1380 match(Set dst (DivD dst con)); | |
1381 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
1382 ins_cost(150); | |
1383 ins_encode %{ | |
1384 __ divsd($dst$$XMMRegister, $constantaddress($con)); | |
1385 %} | |
1386 ins_pipe(pipe_slow); | |
1387 %} | |
1388 | |
6225 | 1389 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ |
4761 | 1390 predicate(UseAVX > 0); |
1391 match(Set dst (DivD src1 src2)); | |
1392 | |
1393 format %{ "vdivsd $dst, $src1, $src2" %} | |
1394 ins_cost(150); | |
1395 ins_encode %{ | |
1396 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); | |
1397 %} | |
1398 ins_pipe(pipe_slow); | |
1399 %} | |
1400 | |
6225 | 1401 instruct divD_reg_mem(regD dst, regD src1, memory src2) %{ |
4761 | 1402 predicate(UseAVX > 0); |
1403 match(Set dst (DivD src1 (LoadD src2))); | |
1404 | |
1405 format %{ "vdivsd $dst, $src1, $src2" %} | |
1406 ins_cost(150); | |
1407 ins_encode %{ | |
1408 __ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); | |
1409 %} | |
1410 ins_pipe(pipe_slow); | |
1411 %} | |
1412 | |
6225 | 1413 instruct divD_reg_imm(regD dst, regD src, immD con) %{ |
4761 | 1414 predicate(UseAVX > 0); |
1415 match(Set dst (DivD src con)); | |
1416 | |
1417 format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} | |
1418 ins_cost(150); | |
1419 ins_encode %{ | |
1420 __ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); | |
1421 %} | |
1422 ins_pipe(pipe_slow); | |
1423 %} | |
1424 | |
1425 instruct absF_reg(regF dst) %{ | |
1426 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1427 match(Set dst (AbsF dst)); | |
1428 ins_cost(150); | |
1429 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
1430 ins_encode %{ | |
1431 __ andps($dst$$XMMRegister, ExternalAddress(float_signmask())); | |
1432 %} | |
1433 ins_pipe(pipe_slow); | |
1434 %} | |
1435 | |
6225 | 1436 instruct absF_reg_reg(regF dst, regF src) %{ |
4761 | 1437 predicate(UseAVX > 0); |
1438 match(Set dst (AbsF src)); | |
1439 ins_cost(150); | |
1440 format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %} | |
1441 ins_encode %{ | |
1442 __ vandps($dst$$XMMRegister, $src$$XMMRegister, | |
1443 ExternalAddress(float_signmask())); | |
1444 %} | |
1445 ins_pipe(pipe_slow); | |
1446 %} | |
1447 | |
1448 instruct absD_reg(regD dst) %{ | |
1449 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1450 match(Set dst (AbsD dst)); | |
1451 ins_cost(150); | |
1452 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
1453 "# abs double by sign masking" %} | |
1454 ins_encode %{ | |
1455 __ andpd($dst$$XMMRegister, ExternalAddress(double_signmask())); | |
1456 %} | |
1457 ins_pipe(pipe_slow); | |
1458 %} | |
1459 | |
6225 | 1460 instruct absD_reg_reg(regD dst, regD src) %{ |
4761 | 1461 predicate(UseAVX > 0); |
1462 match(Set dst (AbsD src)); | |
1463 ins_cost(150); | |
1464 format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t" | |
1465 "# abs double by sign masking" %} | |
1466 ins_encode %{ | |
1467 __ vandpd($dst$$XMMRegister, $src$$XMMRegister, | |
1468 ExternalAddress(double_signmask())); | |
1469 %} | |
1470 ins_pipe(pipe_slow); | |
1471 %} | |
1472 | |
1473 instruct negF_reg(regF dst) %{ | |
1474 predicate((UseSSE>=1) && (UseAVX == 0)); | |
1475 match(Set dst (NegF dst)); | |
1476 ins_cost(150); | |
1477 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
1478 ins_encode %{ | |
1479 __ xorps($dst$$XMMRegister, ExternalAddress(float_signflip())); | |
1480 %} | |
1481 ins_pipe(pipe_slow); | |
1482 %} | |
1483 | |
6225 | 1484 instruct negF_reg_reg(regF dst, regF src) %{ |
4761 | 1485 predicate(UseAVX > 0); |
1486 match(Set dst (NegF src)); | |
1487 ins_cost(150); | |
1488 format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %} | |
1489 ins_encode %{ | |
1490 __ vxorps($dst$$XMMRegister, $src$$XMMRegister, | |
1491 ExternalAddress(float_signflip())); | |
1492 %} | |
1493 ins_pipe(pipe_slow); | |
1494 %} | |
1495 | |
1496 instruct negD_reg(regD dst) %{ | |
1497 predicate((UseSSE>=2) && (UseAVX == 0)); | |
1498 match(Set dst (NegD dst)); | |
1499 ins_cost(150); | |
1500 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
1501 "# neg double by sign flipping" %} | |
1502 ins_encode %{ | |
1503 __ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip())); | |
1504 %} | |
1505 ins_pipe(pipe_slow); | |
1506 %} | |
1507 | |
6225 | 1508 instruct negD_reg_reg(regD dst, regD src) %{ |
4761 | 1509 predicate(UseAVX > 0); |
1510 match(Set dst (NegD src)); | |
1511 ins_cost(150); | |
1512 format %{ "vxorpd $dst, $src, [0x8000000000000000]\t" | |
1513 "# neg double by sign flipping" %} | |
1514 ins_encode %{ | |
1515 __ vxorpd($dst$$XMMRegister, $src$$XMMRegister, | |
1516 ExternalAddress(double_signflip())); | |
1517 %} | |
1518 ins_pipe(pipe_slow); | |
1519 %} | |
1520 | |
1521 instruct sqrtF_reg(regF dst, regF src) %{ | |
1522 predicate(UseSSE>=1); | |
1523 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
1524 | |
1525 format %{ "sqrtss $dst, $src" %} | |
1526 ins_cost(150); | |
1527 ins_encode %{ | |
1528 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister); | |
1529 %} | |
1530 ins_pipe(pipe_slow); | |
1531 %} | |
1532 | |
1533 instruct sqrtF_mem(regF dst, memory src) %{ | |
1534 predicate(UseSSE>=1); | |
1535 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
1536 | |
1537 format %{ "sqrtss $dst, $src" %} | |
1538 ins_cost(150); | |
1539 ins_encode %{ | |
1540 __ sqrtss($dst$$XMMRegister, $src$$Address); | |
1541 %} | |
1542 ins_pipe(pipe_slow); | |
1543 %} | |
1544 | |
1545 instruct sqrtF_imm(regF dst, immF con) %{ | |
1546 predicate(UseSSE>=1); | |
1547 match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); | |
1548 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
1549 ins_cost(150); | |
1550 ins_encode %{ | |
1551 __ sqrtss($dst$$XMMRegister, $constantaddress($con)); | |
1552 %} | |
1553 ins_pipe(pipe_slow); | |
1554 %} | |
1555 | |
1556 instruct sqrtD_reg(regD dst, regD src) %{ | |
1557 predicate(UseSSE>=2); | |
1558 match(Set dst (SqrtD src)); | |
1559 | |
1560 format %{ "sqrtsd $dst, $src" %} | |
1561 ins_cost(150); | |
1562 ins_encode %{ | |
1563 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister); | |
1564 %} | |
1565 ins_pipe(pipe_slow); | |
1566 %} | |
1567 | |
1568 instruct sqrtD_mem(regD dst, memory src) %{ | |
1569 predicate(UseSSE>=2); | |
1570 match(Set dst (SqrtD (LoadD src))); | |
1571 | |
1572 format %{ "sqrtsd $dst, $src" %} | |
1573 ins_cost(150); | |
1574 ins_encode %{ | |
1575 __ sqrtsd($dst$$XMMRegister, $src$$Address); | |
1576 %} | |
1577 ins_pipe(pipe_slow); | |
1578 %} | |
1579 | |
1580 instruct sqrtD_imm(regD dst, immD con) %{ | |
1581 predicate(UseSSE>=2); | |
1582 match(Set dst (SqrtD con)); | |
1583 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
1584 ins_cost(150); | |
1585 ins_encode %{ | |
1586 __ sqrtsd($dst$$XMMRegister, $constantaddress($con)); | |
1587 %} | |
1588 ins_pipe(pipe_slow); | |
1589 %} | |
1590 | |
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1591 |
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1592 // ====================VECTOR INSTRUCTIONS===================================== |
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1593 |
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1594 // Load vectors (4 bytes long) |
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1595 instruct loadV4(vecS dst, memory mem) %{ |
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1596 predicate(n->as_LoadVector()->memory_size() == 4); |
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1597 match(Set dst (LoadVector mem)); |
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1598 ins_cost(125); |
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1599 format %{ "movd $dst,$mem\t! load vector (4 bytes)" %} |
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1600 ins_encode %{ |
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1601 __ movdl($dst$$XMMRegister, $mem$$Address); |
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1602 %} |
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1603 ins_pipe( pipe_slow ); |
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1604 %} |
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1605 |
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1606 // Load vectors (8 bytes long) |
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1607 instruct loadV8(vecD dst, memory mem) %{ |
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1608 predicate(n->as_LoadVector()->memory_size() == 8); |
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1609 match(Set dst (LoadVector mem)); |
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1610 ins_cost(125); |
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1611 format %{ "movq $dst,$mem\t! load vector (8 bytes)" %} |
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1612 ins_encode %{ |
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1613 __ movq($dst$$XMMRegister, $mem$$Address); |
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1614 %} |
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1615 ins_pipe( pipe_slow ); |
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1616 %} |
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1617 |
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1618 // Load vectors (16 bytes long) |
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1619 instruct loadV16(vecX dst, memory mem) %{ |
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1620 predicate(n->as_LoadVector()->memory_size() == 16); |
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1621 match(Set dst (LoadVector mem)); |
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1622 ins_cost(125); |
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1623 format %{ "movdqu $dst,$mem\t! load vector (16 bytes)" %} |
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1624 ins_encode %{ |
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1625 __ movdqu($dst$$XMMRegister, $mem$$Address); |
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|
1626 %} |
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|
1627 ins_pipe( pipe_slow ); |
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|
1628 %} |
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|
1629 |
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|
1630 // Load vectors (32 bytes long) |
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1631 instruct loadV32(vecY dst, memory mem) %{ |
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1632 predicate(n->as_LoadVector()->memory_size() == 32); |
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1633 match(Set dst (LoadVector mem)); |
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|
1634 ins_cost(125); |
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1635 format %{ "vmovdqu $dst,$mem\t! load vector (32 bytes)" %} |
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|
1636 ins_encode %{ |
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1637 __ vmovdqu($dst$$XMMRegister, $mem$$Address); |
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|
1638 %} |
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|
1639 ins_pipe( pipe_slow ); |
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|
1640 %} |
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|
1641 |
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1642 // Store vectors |
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1643 instruct storeV4(memory mem, vecS src) %{ |
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1644 predicate(n->as_StoreVector()->memory_size() == 4); |
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1645 match(Set mem (StoreVector mem src)); |
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|
1646 ins_cost(145); |
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1647 format %{ "movd $mem,$src\t! store vector (4 bytes)" %} |
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1648 ins_encode %{ |
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1649 __ movdl($mem$$Address, $src$$XMMRegister); |
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|
1650 %} |
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1651 ins_pipe( pipe_slow ); |
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|
1652 %} |
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|
1653 |
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1654 instruct storeV8(memory mem, vecD src) %{ |
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1655 predicate(n->as_StoreVector()->memory_size() == 8); |
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1656 match(Set mem (StoreVector mem src)); |
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|
1657 ins_cost(145); |
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1658 format %{ "movq $mem,$src\t! store vector (8 bytes)" %} |
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|
1659 ins_encode %{ |
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|
1660 __ movq($mem$$Address, $src$$XMMRegister); |
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|
1661 %} |
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|
1662 ins_pipe( pipe_slow ); |
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|
1663 %} |
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|
1664 |
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1665 instruct storeV16(memory mem, vecX src) %{ |
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1666 predicate(n->as_StoreVector()->memory_size() == 16); |
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1667 match(Set mem (StoreVector mem src)); |
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|
1668 ins_cost(145); |
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|
1669 format %{ "movdqu $mem,$src\t! store vector (16 bytes)" %} |
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|
1670 ins_encode %{ |
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|
1671 __ movdqu($mem$$Address, $src$$XMMRegister); |
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|
1672 %} |
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|
1673 ins_pipe( pipe_slow ); |
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|
1674 %} |
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|
1675 |
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|
1676 instruct storeV32(memory mem, vecY src) %{ |
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|
1677 predicate(n->as_StoreVector()->memory_size() == 32); |
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|
1678 match(Set mem (StoreVector mem src)); |
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|
1679 ins_cost(145); |
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|
1680 format %{ "vmovdqu $mem,$src\t! store vector (32 bytes)" %} |
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|
1681 ins_encode %{ |
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|
1682 __ vmovdqu($mem$$Address, $src$$XMMRegister); |
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|
1683 %} |
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|
1684 ins_pipe( pipe_slow ); |
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|
1685 %} |
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changeset
|
1686 |
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|
1687 // Replicate byte scalar to be vector |
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|
1688 instruct Repl4B(vecS dst, rRegI src) %{ |
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|
1689 predicate(n->as_Vector()->length() == 4); |
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|
1690 match(Set dst (ReplicateB src)); |
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changeset
|
1691 format %{ "movd $dst,$src\n\t" |
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|
1692 "punpcklbw $dst,$dst\n\t" |
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|
1693 "pshuflw $dst,$dst,0x00\t! replicate4B" %} |
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|
1694 ins_encode %{ |
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|
1695 __ movdl($dst$$XMMRegister, $src$$Register); |
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|
1696 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
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|
1697 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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7119644: Increase superword's vector size up to 256 bits
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|
1698 %} |
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4950
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changeset
|
1699 ins_pipe( pipe_slow ); |
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4950
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|
1700 %} |
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changeset
|
1701 |
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|
1702 instruct Repl8B(vecD dst, rRegI src) %{ |
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|
1703 predicate(n->as_Vector()->length() == 8); |
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|
1704 match(Set dst (ReplicateB src)); |
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changeset
|
1705 format %{ "movd $dst,$src\n\t" |
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|
1706 "punpcklbw $dst,$dst\n\t" |
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|
1707 "pshuflw $dst,$dst,0x00\t! replicate8B" %} |
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|
1708 ins_encode %{ |
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|
1709 __ movdl($dst$$XMMRegister, $src$$Register); |
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|
1710 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
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|
1711 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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changeset
|
1712 %} |
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4950
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changeset
|
1713 ins_pipe( pipe_slow ); |
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4950
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changeset
|
1714 %} |
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changeset
|
1715 |
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|
1716 instruct Repl16B(vecX dst, rRegI src) %{ |
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|
1717 predicate(n->as_Vector()->length() == 16); |
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|
1718 match(Set dst (ReplicateB src)); |
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changeset
|
1719 format %{ "movd $dst,$src\n\t" |
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|
1720 "punpcklbw $dst,$dst\n\t" |
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|
1721 "pshuflw $dst,$dst,0x00\n\t" |
6225 | 1722 "punpcklqdq $dst,$dst\t! replicate16B" %} |
6179
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|
1723 ins_encode %{ |
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|
1724 __ movdl($dst$$XMMRegister, $src$$Register); |
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|
1725 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
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|
1726 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 1727 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
6179
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|
1728 %} |
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changeset
|
1729 ins_pipe( pipe_slow ); |
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changeset
|
1730 %} |
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|
1731 |
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|
1732 instruct Repl32B(vecY dst, rRegI src) %{ |
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|
1733 predicate(n->as_Vector()->length() == 32); |
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changeset
|
1734 match(Set dst (ReplicateB src)); |
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changeset
|
1735 format %{ "movd $dst,$src\n\t" |
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changeset
|
1736 "punpcklbw $dst,$dst\n\t" |
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|
1737 "pshuflw $dst,$dst,0x00\n\t" |
6225 | 1738 "punpcklqdq $dst,$dst\n\t" |
1739 "vinserti128h $dst,$dst,$dst\t! replicate32B" %} | |
6179
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|
1740 ins_encode %{ |
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|
1741 __ movdl($dst$$XMMRegister, $src$$Register); |
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changeset
|
1742 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
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|
1743 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 1744 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
1745 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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changeset
|
1746 %} |
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changeset
|
1747 ins_pipe( pipe_slow ); |
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changeset
|
1748 %} |
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changeset
|
1749 |
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|
1750 // Replicate byte scalar immediate to be vector by loading from const table. |
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|
1751 instruct Repl4B_imm(vecS dst, immI con) %{ |
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|
1752 predicate(n->as_Vector()->length() == 4); |
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changeset
|
1753 match(Set dst (ReplicateB con)); |
6225 | 1754 format %{ "movdl $dst,[$constantaddress]\t! replicate4B($con)" %} |
6179
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|
1755 ins_encode %{ |
6225 | 1756 __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1))); |
6179
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1757 %} |
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1758 ins_pipe( pipe_slow ); |
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1759 %} |
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1760 |
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1761 instruct Repl8B_imm(vecD dst, immI con) %{ |
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1762 predicate(n->as_Vector()->length() == 8); |
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1763 match(Set dst (ReplicateB con)); |
6225 | 1764 format %{ "movq $dst,[$constantaddress]\t! replicate8B($con)" %} |
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1765 ins_encode %{ |
6225 | 1766 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
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1767 %} |
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1768 ins_pipe( pipe_slow ); |
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1769 %} |
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1770 |
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1771 instruct Repl16B_imm(vecX dst, immI con) %{ |
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1772 predicate(n->as_Vector()->length() == 16); |
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1773 match(Set dst (ReplicateB con)); |
6225 | 1774 format %{ "movq $dst,[$constantaddress]\n\t" |
1775 "punpcklqdq $dst,$dst\t! replicate16B($con)" %} | |
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1776 ins_encode %{ |
6225 | 1777 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
1778 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
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1779 %} |
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1780 ins_pipe( pipe_slow ); |
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1781 %} |
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1782 |
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1783 instruct Repl32B_imm(vecY dst, immI con) %{ |
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1784 predicate(n->as_Vector()->length() == 32); |
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1785 match(Set dst (ReplicateB con)); |
6225 | 1786 format %{ "movq $dst,[$constantaddress]\n\t" |
1787 "punpcklqdq $dst,$dst\n\t" | |
1788 "vinserti128h $dst,$dst,$dst\t! lreplicate32B($con)" %} | |
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1789 ins_encode %{ |
6225 | 1790 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
1791 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
1792 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
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1793 %} |
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1794 ins_pipe( pipe_slow ); |
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1795 %} |
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1796 |
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1797 // Replicate byte scalar zero to be vector |
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1798 instruct Repl4B_zero(vecS dst, immI0 zero) %{ |
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1799 predicate(n->as_Vector()->length() == 4); |
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1800 match(Set dst (ReplicateB zero)); |
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1801 format %{ "pxor $dst,$dst\t! replicate4B zero" %} |
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1802 ins_encode %{ |
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1803 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1804 %} |
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1805 ins_pipe( fpu_reg_reg ); |
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1806 %} |
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1807 |
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1808 instruct Repl8B_zero(vecD dst, immI0 zero) %{ |
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1809 predicate(n->as_Vector()->length() == 8); |
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1810 match(Set dst (ReplicateB zero)); |
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1811 format %{ "pxor $dst,$dst\t! replicate8B zero" %} |
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1812 ins_encode %{ |
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1813 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1814 %} |
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1815 ins_pipe( fpu_reg_reg ); |
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1816 %} |
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1817 |
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1818 instruct Repl16B_zero(vecX dst, immI0 zero) %{ |
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1819 predicate(n->as_Vector()->length() == 16); |
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1820 match(Set dst (ReplicateB zero)); |
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1821 format %{ "pxor $dst,$dst\t! replicate16B zero" %} |
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1822 ins_encode %{ |
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1823 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1824 %} |
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1825 ins_pipe( fpu_reg_reg ); |
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1826 %} |
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|
1827 |
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1828 instruct Repl32B_zero(vecY dst, immI0 zero) %{ |
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1829 predicate(n->as_Vector()->length() == 32); |
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1830 match(Set dst (ReplicateB zero)); |
6225 | 1831 format %{ "vpxor $dst,$dst,$dst\t! replicate32B zero" %} |
6179
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1832 ins_encode %{ |
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1833 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
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1834 bool vector256 = true; |
6225 | 1835 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
6179
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1836 %} |
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1837 ins_pipe( fpu_reg_reg ); |
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1838 %} |
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1839 |
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1840 // Replicate char/short (2 byte) scalar to be vector |
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1841 instruct Repl2S(vecS dst, rRegI src) %{ |
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1842 predicate(n->as_Vector()->length() == 2); |
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1843 match(Set dst (ReplicateS src)); |
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1844 format %{ "movd $dst,$src\n\t" |
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1845 "pshuflw $dst,$dst,0x00\t! replicate2S" %} |
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1846 ins_encode %{ |
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1847 __ movdl($dst$$XMMRegister, $src$$Register); |
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1848 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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1849 %} |
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1850 ins_pipe( fpu_reg_reg ); |
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1851 %} |
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|
1852 |
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1853 instruct Repl4S(vecD dst, rRegI src) %{ |
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1854 predicate(n->as_Vector()->length() == 4); |
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1855 match(Set dst (ReplicateS src)); |
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1856 format %{ "movd $dst,$src\n\t" |
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1857 "pshuflw $dst,$dst,0x00\t! replicate4S" %} |
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1858 ins_encode %{ |
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1859 __ movdl($dst$$XMMRegister, $src$$Register); |
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1860 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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1861 %} |
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1862 ins_pipe( fpu_reg_reg ); |
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|
1863 %} |
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|
1864 |
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1865 instruct Repl8S(vecX dst, rRegI src) %{ |
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1866 predicate(n->as_Vector()->length() == 8); |
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1867 match(Set dst (ReplicateS src)); |
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1868 format %{ "movd $dst,$src\n\t" |
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1869 "pshuflw $dst,$dst,0x00\n\t" |
6225 | 1870 "punpcklqdq $dst,$dst\t! replicate8S" %} |
6179
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1871 ins_encode %{ |
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1872 __ movdl($dst$$XMMRegister, $src$$Register); |
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1873 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 1874 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
6179
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1875 %} |
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1876 ins_pipe( pipe_slow ); |
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1877 %} |
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1878 |
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1879 instruct Repl16S(vecY dst, rRegI src) %{ |
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1880 predicate(n->as_Vector()->length() == 16); |
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1881 match(Set dst (ReplicateS src)); |
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1882 format %{ "movd $dst,$src\n\t" |
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1883 "pshuflw $dst,$dst,0x00\n\t" |
6225 | 1884 "punpcklqdq $dst,$dst\n\t" |
1885 "vinserti128h $dst,$dst,$dst\t! replicate16S" %} | |
6179
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1886 ins_encode %{ |
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1887 __ movdl($dst$$XMMRegister, $src$$Register); |
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1888 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 1889 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
1890 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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1891 %} |
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1892 ins_pipe( pipe_slow ); |
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1893 %} |
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1894 |
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1895 // Replicate char/short (2 byte) scalar immediate to be vector by loading from const table. |
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1896 instruct Repl2S_imm(vecS dst, immI con) %{ |
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1897 predicate(n->as_Vector()->length() == 2); |
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1898 match(Set dst (ReplicateS con)); |
6225 | 1899 format %{ "movdl $dst,[$constantaddress]\t! replicate2S($con)" %} |
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1900 ins_encode %{ |
6225 | 1901 __ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2))); |
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1902 %} |
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1903 ins_pipe( fpu_reg_reg ); |
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1904 %} |
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1905 |
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1906 instruct Repl4S_imm(vecD dst, immI con) %{ |
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1907 predicate(n->as_Vector()->length() == 4); |
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1908 match(Set dst (ReplicateS con)); |
6225 | 1909 format %{ "movq $dst,[$constantaddress]\t! replicate4S($con)" %} |
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1910 ins_encode %{ |
6225 | 1911 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
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1912 %} |
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1913 ins_pipe( fpu_reg_reg ); |
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1914 %} |
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1915 |
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1916 instruct Repl8S_imm(vecX dst, immI con) %{ |
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1917 predicate(n->as_Vector()->length() == 8); |
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1918 match(Set dst (ReplicateS con)); |
6225 | 1919 format %{ "movq $dst,[$constantaddress]\n\t" |
1920 "punpcklqdq $dst,$dst\t! replicate8S($con)" %} | |
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1921 ins_encode %{ |
6225 | 1922 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
1923 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
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1924 %} |
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1925 ins_pipe( pipe_slow ); |
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1926 %} |
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1927 |
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1928 instruct Repl16S_imm(vecY dst, immI con) %{ |
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1929 predicate(n->as_Vector()->length() == 16); |
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1930 match(Set dst (ReplicateS con)); |
6225 | 1931 format %{ "movq $dst,[$constantaddress]\n\t" |
1932 "punpcklqdq $dst,$dst\n\t" | |
1933 "vinserti128h $dst,$dst,$dst\t! replicate16S($con)" %} | |
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1934 ins_encode %{ |
6225 | 1935 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
1936 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
1937 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
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1938 %} |
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1939 ins_pipe( pipe_slow ); |
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1940 %} |
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1941 |
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1942 // Replicate char/short (2 byte) scalar zero to be vector |
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1943 instruct Repl2S_zero(vecS dst, immI0 zero) %{ |
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1944 predicate(n->as_Vector()->length() == 2); |
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1945 match(Set dst (ReplicateS zero)); |
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1946 format %{ "pxor $dst,$dst\t! replicate2S zero" %} |
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1947 ins_encode %{ |
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1948 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1949 %} |
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1950 ins_pipe( fpu_reg_reg ); |
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1951 %} |
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1952 |
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1953 instruct Repl4S_zero(vecD dst, immI0 zero) %{ |
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1954 predicate(n->as_Vector()->length() == 4); |
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1955 match(Set dst (ReplicateS zero)); |
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1956 format %{ "pxor $dst,$dst\t! replicate4S zero" %} |
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1957 ins_encode %{ |
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1958 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1959 %} |
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1960 ins_pipe( fpu_reg_reg ); |
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1961 %} |
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1962 |
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1963 instruct Repl8S_zero(vecX dst, immI0 zero) %{ |
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1964 predicate(n->as_Vector()->length() == 8); |
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1965 match(Set dst (ReplicateS zero)); |
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1966 format %{ "pxor $dst,$dst\t! replicate8S zero" %} |
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1967 ins_encode %{ |
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1968 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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1969 %} |
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1970 ins_pipe( fpu_reg_reg ); |
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1971 %} |
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1972 |
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1973 instruct Repl16S_zero(vecY dst, immI0 zero) %{ |
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1974 predicate(n->as_Vector()->length() == 16); |
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1975 match(Set dst (ReplicateS zero)); |
6225 | 1976 format %{ "vpxor $dst,$dst,$dst\t! replicate16S zero" %} |
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1977 ins_encode %{ |
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1978 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
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1979 bool vector256 = true; |
6225 | 1980 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
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1981 %} |
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1982 ins_pipe( fpu_reg_reg ); |
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1983 %} |
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1984 |
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1985 // Replicate integer (4 byte) scalar to be vector |
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1986 instruct Repl2I(vecD dst, rRegI src) %{ |
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1987 predicate(n->as_Vector()->length() == 2); |
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1988 match(Set dst (ReplicateI src)); |
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1989 format %{ "movd $dst,$src\n\t" |
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1990 "pshufd $dst,$dst,0x00\t! replicate2I" %} |
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1991 ins_encode %{ |
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1992 __ movdl($dst$$XMMRegister, $src$$Register); |
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1993 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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1994 %} |
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1995 ins_pipe( fpu_reg_reg ); |
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1996 %} |
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1997 |
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1998 instruct Repl4I(vecX dst, rRegI src) %{ |
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1999 predicate(n->as_Vector()->length() == 4); |
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2000 match(Set dst (ReplicateI src)); |
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2001 format %{ "movd $dst,$src\n\t" |
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2002 "pshufd $dst,$dst,0x00\t! replicate4I" %} |
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2003 ins_encode %{ |
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2004 __ movdl($dst$$XMMRegister, $src$$Register); |
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2005 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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2006 %} |
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2007 ins_pipe( pipe_slow ); |
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2008 %} |
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2009 |
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2010 instruct Repl8I(vecY dst, rRegI src) %{ |
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2011 predicate(n->as_Vector()->length() == 8); |
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2012 match(Set dst (ReplicateI src)); |
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2013 format %{ "movd $dst,$src\n\t" |
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2014 "pshufd $dst,$dst,0x00\n\t" |
6225 | 2015 "vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
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2016 ins_encode %{ |
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2017 __ movdl($dst$$XMMRegister, $src$$Register); |
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2018 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 2019 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
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2020 %} |
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2021 ins_pipe( pipe_slow ); |
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2022 %} |
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2023 |
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2024 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table. |
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2025 instruct Repl2I_imm(vecD dst, immI con) %{ |
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2026 predicate(n->as_Vector()->length() == 2); |
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2027 match(Set dst (ReplicateI con)); |
6225 | 2028 format %{ "movq $dst,[$constantaddress]\t! replicate2I($con)" %} |
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2029 ins_encode %{ |
6225 | 2030 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
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2031 %} |
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2032 ins_pipe( fpu_reg_reg ); |
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2033 %} |
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2034 |
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2035 instruct Repl4I_imm(vecX dst, immI con) %{ |
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2036 predicate(n->as_Vector()->length() == 4); |
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2037 match(Set dst (ReplicateI con)); |
6225 | 2038 format %{ "movq $dst,[$constantaddress]\t! replicate4I($con)\n\t" |
2039 "punpcklqdq $dst,$dst" %} | |
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2040 ins_encode %{ |
6225 | 2041 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
2042 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
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2043 %} |
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2044 ins_pipe( pipe_slow ); |
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2045 %} |
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2046 |
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2047 instruct Repl8I_imm(vecY dst, immI con) %{ |
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2048 predicate(n->as_Vector()->length() == 8); |
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2049 match(Set dst (ReplicateI con)); |
6225 | 2050 format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
2051 "punpcklqdq $dst,$dst\n\t" | |
2052 "vinserti128h $dst,$dst,$dst" %} | |
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2053 ins_encode %{ |
6225 | 2054 __ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
2055 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
2056 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
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2057 %} |
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2058 ins_pipe( pipe_slow ); |
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2059 %} |
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2060 |
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2061 // Integer could be loaded into xmm register directly from memory. |
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2062 instruct Repl2I_mem(vecD dst, memory mem) %{ |
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2063 predicate(n->as_Vector()->length() == 2); |
6225 | 2064 match(Set dst (ReplicateI (LoadI mem))); |
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2065 format %{ "movd $dst,$mem\n\t" |
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2066 "pshufd $dst,$dst,0x00\t! replicate2I" %} |
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2067 ins_encode %{ |
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2068 __ movdl($dst$$XMMRegister, $mem$$Address); |
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2069 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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2070 %} |
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2071 ins_pipe( fpu_reg_reg ); |
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2072 %} |
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2073 |
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2074 instruct Repl4I_mem(vecX dst, memory mem) %{ |
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2075 predicate(n->as_Vector()->length() == 4); |
6225 | 2076 match(Set dst (ReplicateI (LoadI mem))); |
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2077 format %{ "movd $dst,$mem\n\t" |
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2078 "pshufd $dst,$dst,0x00\t! replicate4I" %} |
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2079 ins_encode %{ |
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2080 __ movdl($dst$$XMMRegister, $mem$$Address); |
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2081 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
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2082 %} |
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2083 ins_pipe( pipe_slow ); |
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2084 %} |
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2085 |
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2086 instruct Repl8I_mem(vecY dst, memory mem) %{ |
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2087 predicate(n->as_Vector()->length() == 8); |
6225 | 2088 match(Set dst (ReplicateI (LoadI mem))); |
6179
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2089 format %{ "movd $dst,$mem\n\t" |
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2090 "pshufd $dst,$dst,0x00\n\t" |
6225 | 2091 "vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
6179
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2092 ins_encode %{ |
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2093 __ movdl($dst$$XMMRegister, $mem$$Address); |
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2094 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
6225 | 2095 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
6179
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2096 %} |
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2097 ins_pipe( pipe_slow ); |
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2098 %} |
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2099 |
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2100 // Replicate integer (4 byte) scalar zero to be vector |
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2101 instruct Repl2I_zero(vecD dst, immI0 zero) %{ |
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2102 predicate(n->as_Vector()->length() == 2); |
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2103 match(Set dst (ReplicateI zero)); |
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2104 format %{ "pxor $dst,$dst\t! replicate2I" %} |
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2105 ins_encode %{ |
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2106 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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2107 %} |
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2108 ins_pipe( fpu_reg_reg ); |
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|
2109 %} |
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|
2110 |
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2111 instruct Repl4I_zero(vecX dst, immI0 zero) %{ |
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2112 predicate(n->as_Vector()->length() == 4); |
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2113 match(Set dst (ReplicateI zero)); |
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2114 format %{ "pxor $dst,$dst\t! replicate4I zero)" %} |
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|
2115 ins_encode %{ |
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2116 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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|
2117 %} |
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|
2118 ins_pipe( fpu_reg_reg ); |
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|
2119 %} |
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|
2120 |
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|
2121 instruct Repl8I_zero(vecY dst, immI0 zero) %{ |
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2122 predicate(n->as_Vector()->length() == 8); |
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2123 match(Set dst (ReplicateI zero)); |
6225 | 2124 format %{ "vpxor $dst,$dst,$dst\t! replicate8I zero" %} |
6179
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|
2125 ins_encode %{ |
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|
2126 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
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2127 bool vector256 = true; |
6225 | 2128 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
6179
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|
2129 %} |
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|
2130 ins_pipe( fpu_reg_reg ); |
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|
2131 %} |
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|
2132 |
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|
2133 // Replicate long (8 byte) scalar to be vector |
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|
2134 #ifdef _LP64 |
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|
2135 instruct Repl2L(vecX dst, rRegL src) %{ |
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2136 predicate(n->as_Vector()->length() == 2); |
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|
2137 match(Set dst (ReplicateL src)); |
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|
2138 format %{ "movdq $dst,$src\n\t" |
6225 | 2139 "punpcklqdq $dst,$dst\t! replicate2L" %} |
6179
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|
2140 ins_encode %{ |
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|
2141 __ movdq($dst$$XMMRegister, $src$$Register); |
6225 | 2142 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
6179
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|
2143 %} |
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|
2144 ins_pipe( pipe_slow ); |
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|
2145 %} |
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|
2146 |
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2147 instruct Repl4L(vecY dst, rRegL src) %{ |
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|
2148 predicate(n->as_Vector()->length() == 4); |
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|
2149 match(Set dst (ReplicateL src)); |
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|
2150 format %{ "movdq $dst,$src\n\t" |
6225 | 2151 "punpcklqdq $dst,$dst\n\t" |
2152 "vinserti128h $dst,$dst,$dst\t! replicate4L" %} | |
6179
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|
2153 ins_encode %{ |
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|
2154 __ movdq($dst$$XMMRegister, $src$$Register); |
6225 | 2155 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2156 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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|
2157 %} |
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|
2158 ins_pipe( pipe_slow ); |
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|
2159 %} |
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|
2160 #else // _LP64 |
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2161 instruct Repl2L(vecX dst, eRegL src, regD tmp) %{ |
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2162 predicate(n->as_Vector()->length() == 2); |
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2163 match(Set dst (ReplicateL src)); |
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|
2164 effect(TEMP dst, USE src, TEMP tmp); |
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|
2165 format %{ "movdl $dst,$src.lo\n\t" |
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|
2166 "movdl $tmp,$src.hi\n\t" |
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|
2167 "punpckldq $dst,$tmp\n\t" |
6225 | 2168 "punpcklqdq $dst,$dst\t! replicate2L"%} |
6179
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|
2169 ins_encode %{ |
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|
2170 __ movdl($dst$$XMMRegister, $src$$Register); |
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|
2171 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
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2172 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
6225 | 2173 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
6179
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|
2174 %} |
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changeset
|
2175 ins_pipe( pipe_slow ); |
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|
2176 %} |
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|
2177 |
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2178 instruct Repl4L(vecY dst, eRegL src, regD tmp) %{ |
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2179 predicate(n->as_Vector()->length() == 4); |
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2180 match(Set dst (ReplicateL src)); |
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2181 effect(TEMP dst, USE src, TEMP tmp); |
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2182 format %{ "movdl $dst,$src.lo\n\t" |
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2183 "movdl $tmp,$src.hi\n\t" |
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2184 "punpckldq $dst,$tmp\n\t" |
6225 | 2185 "punpcklqdq $dst,$dst\n\t" |
2186 "vinserti128h $dst,$dst,$dst\t! replicate4L" %} | |
6179
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2187 ins_encode %{ |
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2188 __ movdl($dst$$XMMRegister, $src$$Register); |
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2189 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
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2190 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
6225 | 2191 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2192 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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2193 %} |
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2194 ins_pipe( pipe_slow ); |
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2195 %} |
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2196 #endif // _LP64 |
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2197 |
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2198 // Replicate long (8 byte) scalar immediate to be vector by loading from const table. |
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2199 instruct Repl2L_imm(vecX dst, immL con) %{ |
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2200 predicate(n->as_Vector()->length() == 2); |
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2201 match(Set dst (ReplicateL con)); |
6225 | 2202 format %{ "movq $dst,[$constantaddress]\n\t" |
2203 "punpcklqdq $dst,$dst\t! replicate2L($con)" %} | |
6179
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2204 ins_encode %{ |
6225 | 2205 __ movq($dst$$XMMRegister, $constantaddress($con)); |
2206 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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2207 %} |
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2208 ins_pipe( pipe_slow ); |
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2209 %} |
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2210 |
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2211 instruct Repl4L_imm(vecY dst, immL con) %{ |
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2212 predicate(n->as_Vector()->length() == 4); |
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2213 match(Set dst (ReplicateL con)); |
6225 | 2214 format %{ "movq $dst,[$constantaddress]\n\t" |
2215 "punpcklqdq $dst,$dst\n\t" | |
2216 "vinserti128h $dst,$dst,$dst\t! replicate4L($con)" %} | |
6179
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2217 ins_encode %{ |
6225 | 2218 __ movq($dst$$XMMRegister, $constantaddress($con)); |
2219 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); | |
2220 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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2221 %} |
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2222 ins_pipe( pipe_slow ); |
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2223 %} |
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2224 |
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2225 // Long could be loaded into xmm register directly from memory. |
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2226 instruct Repl2L_mem(vecX dst, memory mem) %{ |
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2227 predicate(n->as_Vector()->length() == 2); |
6225 | 2228 match(Set dst (ReplicateL (LoadL mem))); |
6179
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2229 format %{ "movq $dst,$mem\n\t" |
6225 | 2230 "punpcklqdq $dst,$dst\t! replicate2L" %} |
6179
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2231 ins_encode %{ |
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2232 __ movq($dst$$XMMRegister, $mem$$Address); |
6225 | 2233 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
6179
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2234 %} |
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2235 ins_pipe( pipe_slow ); |
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2236 %} |
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2237 |
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2238 instruct Repl4L_mem(vecY dst, memory mem) %{ |
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2239 predicate(n->as_Vector()->length() == 4); |
6225 | 2240 match(Set dst (ReplicateL (LoadL mem))); |
6179
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2241 format %{ "movq $dst,$mem\n\t" |
6225 | 2242 "punpcklqdq $dst,$dst\n\t" |
2243 "vinserti128h $dst,$dst,$dst\t! replicate4L" %} | |
6179
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2244 ins_encode %{ |
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2245 __ movq($dst$$XMMRegister, $mem$$Address); |
6225 | 2246 __ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2247 __ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); | |
6179
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2248 %} |
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2249 ins_pipe( pipe_slow ); |
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2250 %} |
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2251 |
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2252 // Replicate long (8 byte) scalar zero to be vector |
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2253 instruct Repl2L_zero(vecX dst, immL0 zero) %{ |
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2254 predicate(n->as_Vector()->length() == 2); |
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2255 match(Set dst (ReplicateL zero)); |
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2256 format %{ "pxor $dst,$dst\t! replicate2L zero" %} |
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2257 ins_encode %{ |
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2258 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
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2259 %} |
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2260 ins_pipe( fpu_reg_reg ); |
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2261 %} |
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|
2262 |
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2263 instruct Repl4L_zero(vecY dst, immL0 zero) %{ |
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2264 predicate(n->as_Vector()->length() == 4); |
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2265 match(Set dst (ReplicateL zero)); |
6225 | 2266 format %{ "vpxor $dst,$dst,$dst\t! replicate4L zero" %} |
6179
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2267 ins_encode %{ |
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2268 // Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
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2269 bool vector256 = true; |
6225 | 2270 __ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
6179
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2271 %} |
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2272 ins_pipe( fpu_reg_reg ); |
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|
2273 %} |
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|
2274 |
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2275 // Replicate float (4 byte) scalar to be vector |
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2276 instruct Repl2F(vecD dst, regF src) %{ |
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2277 predicate(n->as_Vector()->length() == 2); |
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2278 match(Set dst (ReplicateF src)); |
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2279 format %{ "pshufd $dst,$dst,0x00\t! replicate2F" %} |
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2280 ins_encode %{ |
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2281 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
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2282 %} |
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2283 ins_pipe( fpu_reg_reg ); |
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2284 %} |
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|
2285 |
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2286 instruct Repl4F(vecX dst, regF src) %{ |
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2287 predicate(n->as_Vector()->length() == 4); |
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2288 match(Set dst (ReplicateF src)); |
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2289 format %{ "pshufd $dst,$dst,0x00\t! replicate4F" %} |
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2290 ins_encode %{ |
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2291 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
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2292 %} |
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2293 ins_pipe( pipe_slow ); |
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2294 %} |
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2295 |
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2296 instruct Repl8F(vecY dst, regF src) %{ |
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2297 predicate(n->as_Vector()->length() == 8); |
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2298 match(Set dst (ReplicateF src)); |
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2299 format %{ "pshufd $dst,$src,0x00\n\t" |
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2300 "vinsertf128h $dst,$dst,$dst\t! replicate8F" %} |
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2301 ins_encode %{ |
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2302 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
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2303 __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
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2304 %} |
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2305 ins_pipe( pipe_slow ); |
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2306 %} |
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2307 |
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2308 // Replicate float (4 byte) scalar zero to be vector |
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2309 instruct Repl2F_zero(vecD dst, immF0 zero) %{ |
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2310 predicate(n->as_Vector()->length() == 2); |
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2311 match(Set dst (ReplicateF zero)); |
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2312 format %{ "xorps $dst,$dst\t! replicate2F zero" %} |
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2313 ins_encode %{ |
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2314 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
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2315 %} |
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2316 ins_pipe( fpu_reg_reg ); |
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2317 %} |
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2318 |
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2319 instruct Repl4F_zero(vecX dst, immF0 zero) %{ |
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2320 predicate(n->as_Vector()->length() == 4); |
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2321 match(Set dst (ReplicateF zero)); |
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2322 format %{ "xorps $dst,$dst\t! replicate4F zero" %} |
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2323 ins_encode %{ |
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2324 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
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2325 %} |
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2326 ins_pipe( fpu_reg_reg ); |
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2327 %} |
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2328 |
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2329 instruct Repl8F_zero(vecY dst, immF0 zero) %{ |
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2330 predicate(n->as_Vector()->length() == 8); |
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2331 match(Set dst (ReplicateF zero)); |
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2332 format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %} |
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2333 ins_encode %{ |
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2334 bool vector256 = true; |
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2335 __ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
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2336 %} |
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2337 ins_pipe( fpu_reg_reg ); |
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2338 %} |
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2339 |
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2340 // Replicate double (8 bytes) scalar to be vector |
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2341 instruct Repl2D(vecX dst, regD src) %{ |
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2342 predicate(n->as_Vector()->length() == 2); |
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2343 match(Set dst (ReplicateD src)); |
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2344 format %{ "pshufd $dst,$src,0x44\t! replicate2D" %} |
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2345 ins_encode %{ |
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2346 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
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2347 %} |
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2348 ins_pipe( pipe_slow ); |
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2349 %} |
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2350 |
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2351 instruct Repl4D(vecY dst, regD src) %{ |
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2352 predicate(n->as_Vector()->length() == 4); |
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2353 match(Set dst (ReplicateD src)); |
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2354 format %{ "pshufd $dst,$src,0x44\n\t" |
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2355 "vinsertf128h $dst,$dst,$dst\t! replicate4D" %} |
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2356 ins_encode %{ |
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2357 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
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2358 __ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
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2359 %} |
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2360 ins_pipe( pipe_slow ); |
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2361 %} |
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2362 |
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2363 // Replicate double (8 byte) scalar zero to be vector |
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2364 instruct Repl2D_zero(vecX dst, immD0 zero) %{ |
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2365 predicate(n->as_Vector()->length() == 2); |
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2366 match(Set dst (ReplicateD zero)); |
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2367 format %{ "xorpd $dst,$dst\t! replicate2D zero" %} |
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2368 ins_encode %{ |
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2369 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister); |
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2370 %} |
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2371 ins_pipe( fpu_reg_reg ); |
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2372 %} |
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2373 |
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2374 instruct Repl4D_zero(vecY dst, immD0 zero) %{ |
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2375 predicate(n->as_Vector()->length() == 4); |
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2376 match(Set dst (ReplicateD zero)); |
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2377 format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %} |
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2378 ins_encode %{ |
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2379 bool vector256 = true; |
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2380 __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
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2381 %} |
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2382 ins_pipe( fpu_reg_reg ); |
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2383 %} |
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2384 |