annotate src/share/vm/opto/mulnode.cpp @ 17716:cdb71841f4bc

6498581: ThreadInterruptTest3 produces wrong output on Windows Summary: There is race condition between os::interrupt and os::is_interrupted on Windows. In JVM_Sleep(Thread.sleep), check if thread gets interrupted, it may see interrupted but not really interrupted so cause spurious waking up (early return from sleep). Fix by checking if interrupt event really gets set thus prevent false return. For intrinsic of _isInterrupted, on Windows, go fastpath only on bit not set. Reviewed-by: acorn, kvn Contributed-by: david.holmes@oracle.com, yumin.qi@oracle.com
author minqi
date Wed, 26 Feb 2014 15:20:41 -0800
parents 67f4c477c9ab
children 2113136690bc
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "memory/allocation.inline.hpp"
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27 #include "opto/addnode.hpp"
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28 #include "opto/connode.hpp"
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29 #include "opto/memnode.hpp"
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30 #include "opto/mulnode.hpp"
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31 #include "opto/phaseX.hpp"
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32 #include "opto/subnode.hpp"
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33
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34 // Portions of code courtesy of Clifford Click
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35
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36
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37 //=============================================================================
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38 //------------------------------hash-------------------------------------------
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39 // Hash function over MulNodes. Needs to be commutative; i.e., I swap
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40 // (commute) inputs to MulNodes willy-nilly so the hash function must return
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41 // the same value in the presence of edge swapping.
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42 uint MulNode::hash() const {
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43 return (uintptr_t)in(1) + (uintptr_t)in(2) + Opcode();
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44 }
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45
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46 //------------------------------Identity---------------------------------------
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47 // Multiplying a one preserves the other argument
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48 Node *MulNode::Identity( PhaseTransform *phase ) {
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49 register const Type *one = mul_id(); // The multiplicative identity
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50 if( phase->type( in(1) )->higher_equal( one ) ) return in(2);
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51 if( phase->type( in(2) )->higher_equal( one ) ) return in(1);
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52
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53 return this;
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54 }
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55
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56 //------------------------------Ideal------------------------------------------
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57 // We also canonicalize the Node, moving constants to the right input,
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58 // and flatten expressions (so that 1+x+2 becomes x+3).
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59 Node *MulNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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60 const Type *t1 = phase->type( in(1) );
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61 const Type *t2 = phase->type( in(2) );
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62 Node *progress = NULL; // Progress flag
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63 // We are OK if right is a constant, or right is a load and
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64 // left is a non-constant.
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65 if( !(t2->singleton() ||
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66 (in(2)->is_Load() && !(t1->singleton() || in(1)->is_Load())) ) ) {
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67 if( t1->singleton() || // Left input is a constant?
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68 // Otherwise, sort inputs (commutativity) to help value numbering.
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69 (in(1)->_idx > in(2)->_idx) ) {
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70 swap_edges(1, 2);
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71 const Type *t = t1;
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72 t1 = t2;
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73 t2 = t;
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74 progress = this; // Made progress
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75 }
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76 }
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77
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78 // If the right input is a constant, and the left input is a product of a
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79 // constant, flatten the expression tree.
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80 uint op = Opcode();
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81 if( t2->singleton() && // Right input is a constant?
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82 op != Op_MulF && // Float & double cannot reassociate
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83 op != Op_MulD ) {
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84 if( t2 == Type::TOP ) return NULL;
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85 Node *mul1 = in(1);
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86 #ifdef ASSERT
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87 // Check for dead loop
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88 int op1 = mul1->Opcode();
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89 if( phase->eqv( mul1, this ) || phase->eqv( in(2), this ) ||
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90 ( op1 == mul_opcode() || op1 == add_opcode() ) &&
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91 ( phase->eqv( mul1->in(1), this ) || phase->eqv( mul1->in(2), this ) ||
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92 phase->eqv( mul1->in(1), mul1 ) || phase->eqv( mul1->in(2), mul1 ) ) )
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93 assert(false, "dead loop in MulNode::Ideal");
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94 #endif
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95
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96 if( mul1->Opcode() == mul_opcode() ) { // Left input is a multiply?
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97 // Mul of a constant?
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98 const Type *t12 = phase->type( mul1->in(2) );
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99 if( t12->singleton() && t12 != Type::TOP) { // Left input is an add of a constant?
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100 // Compute new constant; check for overflow
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101 const Type *tcon01 = ((MulNode*)mul1)->mul_ring(t2,t12);
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102 if( tcon01->singleton() ) {
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103 // The Mul of the flattened expression
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104 set_req(1, mul1->in(1));
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105 set_req(2, phase->makecon( tcon01 ));
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106 t2 = tcon01;
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107 progress = this; // Made progress
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108 }
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109 }
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110 }
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111 // If the right input is a constant, and the left input is an add of a
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112 // constant, flatten the tree: (X+con1)*con0 ==> X*con0 + con1*con0
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113 const Node *add1 = in(1);
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114 if( add1->Opcode() == add_opcode() ) { // Left input is an add?
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115 // Add of a constant?
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116 const Type *t12 = phase->type( add1->in(2) );
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117 if( t12->singleton() && t12 != Type::TOP ) { // Left input is an add of a constant?
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118 assert( add1->in(1) != add1, "dead loop in MulNode::Ideal" );
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119 // Compute new constant; check for overflow
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120 const Type *tcon01 = mul_ring(t2,t12);
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121 if( tcon01->singleton() ) {
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122
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123 // Convert (X+con1)*con0 into X*con0
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124 Node *mul = clone(); // mul = ()*con0
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125 mul->set_req(1,add1->in(1)); // mul = X*con0
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126 mul = phase->transform(mul);
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127
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128 Node *add2 = add1->clone();
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129 add2->set_req(1, mul); // X*con0 + con0*con1
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130 add2->set_req(2, phase->makecon(tcon01) );
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131 progress = add2;
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132 }
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133 }
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134 } // End of is left input an add
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135 } // End of is right input a Mul
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136
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137 return progress;
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138 }
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139
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140 //------------------------------Value-----------------------------------------
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141 const Type *MulNode::Value( PhaseTransform *phase ) const {
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142 const Type *t1 = phase->type( in(1) );
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143 const Type *t2 = phase->type( in(2) );
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144 // Either input is TOP ==> the result is TOP
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145 if( t1 == Type::TOP ) return Type::TOP;
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146 if( t2 == Type::TOP ) return Type::TOP;
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147
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148 // Either input is ZERO ==> the result is ZERO.
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149 // Not valid for floats or doubles since +0.0 * -0.0 --> +0.0
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150 int op = Opcode();
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151 if( op == Op_MulI || op == Op_AndI || op == Op_MulL || op == Op_AndL ) {
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152 const Type *zero = add_id(); // The multiplicative zero
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153 if( t1->higher_equal( zero ) ) return zero;
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154 if( t2->higher_equal( zero ) ) return zero;
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155 }
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156
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157 // Either input is BOTTOM ==> the result is the local BOTTOM
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158 if( t1 == Type::BOTTOM || t2 == Type::BOTTOM )
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159 return bottom_type();
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160
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161 #if defined(IA32)
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162 // Can't trust native compilers to properly fold strict double
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163 // multiplication with round-to-zero on this platform.
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164 if (op == Op_MulD && phase->C->method()->is_strict()) {
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165 return TypeD::DOUBLE;
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166 }
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167 #endif
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168
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169 return mul_ring(t1,t2); // Local flavor of type multiplication
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170 }
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171
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172
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173 //=============================================================================
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174 //------------------------------Ideal------------------------------------------
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175 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
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176 Node *MulINode::Ideal(PhaseGVN *phase, bool can_reshape) {
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177 // Swap constant to right
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178 jint con;
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179 if ((con = in(1)->find_int_con(0)) != 0) {
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180 swap_edges(1, 2);
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181 // Finish rest of method to use info in 'con'
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182 } else if ((con = in(2)->find_int_con(0)) == 0) {
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183 return MulNode::Ideal(phase, can_reshape);
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184 }
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185
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186 // Now we have a constant Node on the right and the constant in con
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187 if( con == 0 ) return NULL; // By zero is handled by Value call
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188 if( con == 1 ) return NULL; // By one is handled by Identity call
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189
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190 // Check for negative constant; if so negate the final result
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191 bool sign_flip = false;
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192 if( con < 0 ) {
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193 con = -con;
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194 sign_flip = true;
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195 }
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196
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197 // Get low bit; check for being the only bit
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198 Node *res = NULL;
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199 jint bit1 = con & -con; // Extract low bit
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200 if( bit1 == con ) { // Found a power of 2?
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201 res = new (phase->C) LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) );
0
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202 } else {
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203
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204 // Check for constant with 2 bits set
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205 jint bit2 = con-bit1;
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206 bit2 = bit2 & -bit2; // Extract 2nd bit
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207 if( bit2 + bit1 == con ) { // Found all bits in con?
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208 Node *n1 = phase->transform( new (phase->C) LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) ) );
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209 Node *n2 = phase->transform( new (phase->C) LShiftINode( in(1), phase->intcon(log2_intptr(bit2)) ) );
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210 res = new (phase->C) AddINode( n2, n1 );
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211
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212 } else if (is_power_of_2(con+1)) {
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213 // Sleezy: power-of-2 -1. Next time be generic.
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214 jint temp = (jint) (con + 1);
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215 Node *n1 = phase->transform( new (phase->C) LShiftINode( in(1), phase->intcon(log2_intptr(temp)) ) );
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216 res = new (phase->C) SubINode( n1, in(1) );
0
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217 } else {
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218 return MulNode::Ideal(phase, can_reshape);
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219 }
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220 }
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221
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222 if( sign_flip ) { // Need to negate result?
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223 res = phase->transform(res);// Transform, before making the zero con
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224 res = new (phase->C) SubINode(phase->intcon(0),res);
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225 }
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226
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227 return res; // Return final result
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228 }
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229
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230 //------------------------------mul_ring---------------------------------------
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231 // Compute the product type of two integer ranges into this node.
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232 const Type *MulINode::mul_ring(const Type *t0, const Type *t1) const {
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233 const TypeInt *r0 = t0->is_int(); // Handy access
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234 const TypeInt *r1 = t1->is_int();
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235
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236 // Fetch endpoints of all ranges
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237 int32 lo0 = r0->_lo;
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238 double a = (double)lo0;
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239 int32 hi0 = r0->_hi;
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240 double b = (double)hi0;
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241 int32 lo1 = r1->_lo;
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242 double c = (double)lo1;
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243 int32 hi1 = r1->_hi;
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244 double d = (double)hi1;
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245
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246 // Compute all endpoints & check for overflow
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247 int32 A = lo0*lo1;
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248 if( (double)A != a*c ) return TypeInt::INT; // Overflow?
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249 int32 B = lo0*hi1;
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250 if( (double)B != a*d ) return TypeInt::INT; // Overflow?
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251 int32 C = hi0*lo1;
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252 if( (double)C != b*c ) return TypeInt::INT; // Overflow?
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253 int32 D = hi0*hi1;
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254 if( (double)D != b*d ) return TypeInt::INT; // Overflow?
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255
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256 if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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257 else { lo0 = B; hi0 = A; }
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258 if( C < D ) {
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259 if( C < lo0 ) lo0 = C;
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260 if( D > hi0 ) hi0 = D;
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261 } else {
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262 if( D < lo0 ) lo0 = D;
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263 if( C > hi0 ) hi0 = C;
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264 }
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265 return TypeInt::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
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266 }
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267
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268
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269 //=============================================================================
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270 //------------------------------Ideal------------------------------------------
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271 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
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272 Node *MulLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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273 // Swap constant to right
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274 jlong con;
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275 if ((con = in(1)->find_long_con(0)) != 0) {
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276 swap_edges(1, 2);
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277 // Finish rest of method to use info in 'con'
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278 } else if ((con = in(2)->find_long_con(0)) == 0) {
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279 return MulNode::Ideal(phase, can_reshape);
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280 }
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281
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282 // Now we have a constant Node on the right and the constant in con
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283 if( con == CONST64(0) ) return NULL; // By zero is handled by Value call
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284 if( con == CONST64(1) ) return NULL; // By one is handled by Identity call
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285
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286 // Check for negative constant; if so negate the final result
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287 bool sign_flip = false;
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288 if( con < 0 ) {
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289 con = -con;
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290 sign_flip = true;
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291 }
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292
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293 // Get low bit; check for being the only bit
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294 Node *res = NULL;
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295 jlong bit1 = con & -con; // Extract low bit
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296 if( bit1 == con ) { // Found a power of 2?
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297 res = new (phase->C) LShiftLNode( in(1), phase->intcon(log2_long(bit1)) );
0
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298 } else {
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299
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300 // Check for constant with 2 bits set
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301 jlong bit2 = con-bit1;
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302 bit2 = bit2 & -bit2; // Extract 2nd bit
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303 if( bit2 + bit1 == con ) { // Found all bits in con?
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304 Node *n1 = phase->transform( new (phase->C) LShiftLNode( in(1), phase->intcon(log2_long(bit1)) ) );
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305 Node *n2 = phase->transform( new (phase->C) LShiftLNode( in(1), phase->intcon(log2_long(bit2)) ) );
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306 res = new (phase->C) AddLNode( n2, n1 );
0
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307
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308 } else if (is_power_of_2_long(con+1)) {
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309 // Sleezy: power-of-2 -1. Next time be generic.
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310 jlong temp = (jlong) (con + 1);
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311 Node *n1 = phase->transform( new (phase->C) LShiftLNode( in(1), phase->intcon(log2_long(temp)) ) );
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312 res = new (phase->C) SubLNode( n1, in(1) );
0
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313 } else {
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314 return MulNode::Ideal(phase, can_reshape);
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315 }
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316 }
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317
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318 if( sign_flip ) { // Need to negate result?
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319 res = phase->transform(res);// Transform, before making the zero con
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320 res = new (phase->C) SubLNode(phase->longcon(0),res);
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321 }
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322
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323 return res; // Return final result
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324 }
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325
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326 //------------------------------mul_ring---------------------------------------
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327 // Compute the product type of two integer ranges into this node.
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328 const Type *MulLNode::mul_ring(const Type *t0, const Type *t1) const {
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329 const TypeLong *r0 = t0->is_long(); // Handy access
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330 const TypeLong *r1 = t1->is_long();
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331
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332 // Fetch endpoints of all ranges
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333 jlong lo0 = r0->_lo;
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334 double a = (double)lo0;
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335 jlong hi0 = r0->_hi;
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336 double b = (double)hi0;
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337 jlong lo1 = r1->_lo;
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338 double c = (double)lo1;
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339 jlong hi1 = r1->_hi;
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340 double d = (double)hi1;
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341
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342 // Compute all endpoints & check for overflow
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343 jlong A = lo0*lo1;
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344 if( (double)A != a*c ) return TypeLong::LONG; // Overflow?
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345 jlong B = lo0*hi1;
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346 if( (double)B != a*d ) return TypeLong::LONG; // Overflow?
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347 jlong C = hi0*lo1;
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348 if( (double)C != b*c ) return TypeLong::LONG; // Overflow?
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349 jlong D = hi0*hi1;
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350 if( (double)D != b*d ) return TypeLong::LONG; // Overflow?
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351
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352 if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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353 else { lo0 = B; hi0 = A; }
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354 if( C < D ) {
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355 if( C < lo0 ) lo0 = C;
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356 if( D > hi0 ) hi0 = D;
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357 } else {
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358 if( D < lo0 ) lo0 = D;
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359 if( C > hi0 ) hi0 = C;
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360 }
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361 return TypeLong::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
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362 }
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363
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364 //=============================================================================
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365 //------------------------------mul_ring---------------------------------------
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366 // Compute the product type of two double ranges into this node.
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367 const Type *MulFNode::mul_ring(const Type *t0, const Type *t1) const {
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368 if( t0 == Type::FLOAT || t1 == Type::FLOAT ) return Type::FLOAT;
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369 return TypeF::make( t0->getf() * t1->getf() );
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370 }
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371
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372 //=============================================================================
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373 //------------------------------mul_ring---------------------------------------
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374 // Compute the product type of two double ranges into this node.
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375 const Type *MulDNode::mul_ring(const Type *t0, const Type *t1) const {
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376 if( t0 == Type::DOUBLE || t1 == Type::DOUBLE ) return Type::DOUBLE;
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377 // We must be multiplying 2 double constants.
0
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378 return TypeD::make( t0->getd() * t1->getd() );
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379 }
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380
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381 //=============================================================================
145
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382 //------------------------------Value------------------------------------------
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383 const Type *MulHiLNode::Value( PhaseTransform *phase ) const {
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384 // Either input is TOP ==> the result is TOP
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385 const Type *t1 = phase->type( in(1) );
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386 const Type *t2 = phase->type( in(2) );
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387 if( t1 == Type::TOP ) return Type::TOP;
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388 if( t2 == Type::TOP ) return Type::TOP;
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389
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390 // Either input is BOTTOM ==> the result is the local BOTTOM
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391 const Type *bot = bottom_type();
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392 if( (t1 == bot) || (t2 == bot) ||
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393 (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
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394 return bot;
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395
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396 // It is not worth trying to constant fold this stuff!
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397 return TypeLong::LONG;
f3de1255b035 6603011: RFE: Optimize long division
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398 }
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399
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400 //=============================================================================
0
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401 //------------------------------mul_ring---------------------------------------
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parents:
diff changeset
402 // Supplied function returns the product of the inputs IN THE CURRENT RING.
a61af66fc99e Initial load
duke
parents:
diff changeset
403 // For the logical operations the ring's MUL is really a logical AND function.
a61af66fc99e Initial load
duke
parents:
diff changeset
404 // This also type-checks the inputs for sanity. Guaranteed never to
a61af66fc99e Initial load
duke
parents:
diff changeset
405 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
a61af66fc99e Initial load
duke
parents:
diff changeset
406 const Type *AndINode::mul_ring( const Type *t0, const Type *t1 ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
407 const TypeInt *r0 = t0->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
408 const TypeInt *r1 = t1->is_int();
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duke
parents:
diff changeset
409 int widen = MAX2(r0->_widen,r1->_widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
410
a61af66fc99e Initial load
duke
parents:
diff changeset
411 // If either input is a constant, might be able to trim cases
a61af66fc99e Initial load
duke
parents:
diff changeset
412 if( !r0->is_con() && !r1->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
413 return TypeInt::INT; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
414
a61af66fc99e Initial load
duke
parents:
diff changeset
415 // Both constants? Return bits
a61af66fc99e Initial load
duke
parents:
diff changeset
416 if( r0->is_con() && r1->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
417 return TypeInt::make( r0->get_con() & r1->get_con() );
a61af66fc99e Initial load
duke
parents:
diff changeset
418
a61af66fc99e Initial load
duke
parents:
diff changeset
419 if( r0->is_con() && r0->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
420 return TypeInt::make(0, r0->get_con(), widen);
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duke
parents:
diff changeset
421
a61af66fc99e Initial load
duke
parents:
diff changeset
422 if( r1->is_con() && r1->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
423 return TypeInt::make(0, r1->get_con(), widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
424
a61af66fc99e Initial load
duke
parents:
diff changeset
425 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
426 return TypeInt::BOOL;
a61af66fc99e Initial load
duke
parents:
diff changeset
427 }
a61af66fc99e Initial load
duke
parents:
diff changeset
428
a61af66fc99e Initial load
duke
parents:
diff changeset
429 return TypeInt::INT; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
430 }
a61af66fc99e Initial load
duke
parents:
diff changeset
431
a61af66fc99e Initial load
duke
parents:
diff changeset
432 //------------------------------Identity---------------------------------------
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duke
parents:
diff changeset
433 // Masking off the high bits of an unsigned load is not required
a61af66fc99e Initial load
duke
parents:
diff changeset
434 Node *AndINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
435
a61af66fc99e Initial load
duke
parents:
diff changeset
436 // x & x => x
a61af66fc99e Initial load
duke
parents:
diff changeset
437 if (phase->eqv(in(1), in(2))) return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
438
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
439 Node* in1 = in(1);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
440 uint op = in1->Opcode();
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
441 const TypeInt* t2 = phase->type(in(2))->isa_int();
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
442 if (t2 && t2->is_con()) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
443 int con = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
444 // Masking off high bits which are always zero is useless.
a61af66fc99e Initial load
duke
parents:
diff changeset
445 const TypeInt* t1 = phase->type( in(1) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
446 if (t1 != NULL && t1->_lo >= 0) {
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
447 jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
448 if ((t1_support & con) == t1_support)
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
449 return in1;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
450 }
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duke
parents:
diff changeset
451 // Masking off the high bits of a unsigned-shift-right is not
a61af66fc99e Initial load
duke
parents:
diff changeset
452 // needed either.
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
453 if (op == Op_URShiftI) {
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
454 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
455 if (t12 && t12->is_con()) { // Shift is by a constant
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
456 int shift = t12->get_con();
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
457 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
458 int mask = max_juint >> shift;
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
459 if ((mask & con) == mask) // If AND is useless, skip it
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
460 return in1;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
461 }
a61af66fc99e Initial load
duke
parents:
diff changeset
462 }
a61af66fc99e Initial load
duke
parents:
diff changeset
463 }
a61af66fc99e Initial load
duke
parents:
diff changeset
464 return MulNode::Identity(phase);
a61af66fc99e Initial load
duke
parents:
diff changeset
465 }
a61af66fc99e Initial load
duke
parents:
diff changeset
466
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parents:
diff changeset
467 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
468 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
469 // Special case constant AND mask
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duke
parents:
diff changeset
470 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
471 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
duke
parents:
diff changeset
472 const int mask = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
473 Node *load = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
474 uint lop = load->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
475
a61af66fc99e Initial load
duke
parents:
diff changeset
476 // Masking bits off of a Character? Hi bits are already zero.
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 404
diff changeset
477 if( lop == Op_LoadUS &&
0
a61af66fc99e Initial load
duke
parents:
diff changeset
478 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
479 return new (phase->C) AndINode(load,phase->intcon(mask&0xFFFF));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
480
a61af66fc99e Initial load
duke
parents:
diff changeset
481 // Masking bits off of a Short? Loading a Character does some masking
6891
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
482 if (can_reshape &&
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
483 load->outcnt() == 1 && load->unique_out() == this) {
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
484 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
485 Node *ldus = new (phase->C) LoadUSNode(load->in(MemNode::Control),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
486 load->in(MemNode::Memory),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
487 load->in(MemNode::Address),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
488 load->adr_type());
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
489 ldus = phase->transform(ldus);
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
490 return new (phase->C) AndINode(ldus, phase->intcon(mask & 0xFFFF));
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
491 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
492
6891
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
493 // Masking sign bits off of a Byte? Do an unsigned byte load plus
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
494 // an and.
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
495 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
496 Node* ldub = new (phase->C) LoadUBNode(load->in(MemNode::Control),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
497 load->in(MemNode::Memory),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
498 load->in(MemNode::Address),
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
499 load->adr_type());
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
500 ldub = phase->transform(ldub);
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
501 return new (phase->C) AndINode(ldub, phase->intcon(mask));
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
502 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
503 }
a61af66fc99e Initial load
duke
parents:
diff changeset
504
a61af66fc99e Initial load
duke
parents:
diff changeset
505 // Masking off sign bits? Dont make them!
a61af66fc99e Initial load
duke
parents:
diff changeset
506 if( lop == Op_RShiftI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
507 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
508 if( t12 && t12->is_con() ) { // Shift is by a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
509 int shift = t12->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
510 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
511 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
a61af66fc99e Initial load
duke
parents:
diff changeset
512 // If the AND'ing of the 2 masks has no bits, then only original shifted
a61af66fc99e Initial load
duke
parents:
diff changeset
513 // bits survive. NO sign-extension bits survive the maskings.
a61af66fc99e Initial load
duke
parents:
diff changeset
514 if( (sign_bits_mask & mask) == 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
515 // Use zero-fill shift instead
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
516 Node *zshift = phase->transform(new (phase->C) URShiftINode(load->in(1),load->in(2)));
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
517 return new (phase->C) AndINode( zshift, in(2) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
518 }
a61af66fc99e Initial load
duke
parents:
diff changeset
519 }
a61af66fc99e Initial load
duke
parents:
diff changeset
520 }
a61af66fc99e Initial load
duke
parents:
diff changeset
521
a61af66fc99e Initial load
duke
parents:
diff changeset
522 // Check for 'negate/and-1', a pattern emitted when someone asks for
a61af66fc99e Initial load
duke
parents:
diff changeset
523 // 'mod 2'. Negate leaves the low order bit unchanged (think: complement
a61af66fc99e Initial load
duke
parents:
diff changeset
524 // plus 1) and the mask is of the low order bit. Skip the negate.
a61af66fc99e Initial load
duke
parents:
diff changeset
525 if( lop == Op_SubI && mask == 1 && load->in(1) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
526 phase->type(load->in(1)) == TypeInt::ZERO )
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
527 return new (phase->C) AndINode( load->in(2), in(2) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
528
a61af66fc99e Initial load
duke
parents:
diff changeset
529 return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
duke
parents:
diff changeset
530 }
a61af66fc99e Initial load
duke
parents:
diff changeset
531
a61af66fc99e Initial load
duke
parents:
diff changeset
532 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
533 //------------------------------mul_ring---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
534 // Supplied function returns the product of the inputs IN THE CURRENT RING.
a61af66fc99e Initial load
duke
parents:
diff changeset
535 // For the logical operations the ring's MUL is really a logical AND function.
a61af66fc99e Initial load
duke
parents:
diff changeset
536 // This also type-checks the inputs for sanity. Guaranteed never to
a61af66fc99e Initial load
duke
parents:
diff changeset
537 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
a61af66fc99e Initial load
duke
parents:
diff changeset
538 const Type *AndLNode::mul_ring( const Type *t0, const Type *t1 ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
539 const TypeLong *r0 = t0->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
540 const TypeLong *r1 = t1->is_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
541 int widen = MAX2(r0->_widen,r1->_widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
542
a61af66fc99e Initial load
duke
parents:
diff changeset
543 // If either input is a constant, might be able to trim cases
a61af66fc99e Initial load
duke
parents:
diff changeset
544 if( !r0->is_con() && !r1->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
545 return TypeLong::LONG; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
546
a61af66fc99e Initial load
duke
parents:
diff changeset
547 // Both constants? Return bits
a61af66fc99e Initial load
duke
parents:
diff changeset
548 if( r0->is_con() && r1->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
549 return TypeLong::make( r0->get_con() & r1->get_con() );
a61af66fc99e Initial load
duke
parents:
diff changeset
550
a61af66fc99e Initial load
duke
parents:
diff changeset
551 if( r0->is_con() && r0->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
552 return TypeLong::make(CONST64(0), r0->get_con(), widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
553
a61af66fc99e Initial load
duke
parents:
diff changeset
554 if( r1->is_con() && r1->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
555 return TypeLong::make(CONST64(0), r1->get_con(), widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
556
a61af66fc99e Initial load
duke
parents:
diff changeset
557 return TypeLong::LONG; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
558 }
a61af66fc99e Initial load
duke
parents:
diff changeset
559
a61af66fc99e Initial load
duke
parents:
diff changeset
560 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
561 // Masking off the high bits of an unsigned load is not required
a61af66fc99e Initial load
duke
parents:
diff changeset
562 Node *AndLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
563
a61af66fc99e Initial load
duke
parents:
diff changeset
564 // x & x => x
a61af66fc99e Initial load
duke
parents:
diff changeset
565 if (phase->eqv(in(1), in(2))) return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
566
a61af66fc99e Initial load
duke
parents:
diff changeset
567 Node *usr = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
568 const TypeLong *t2 = phase->type( in(2) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
569 if( t2 && t2->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
570 jlong con = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
571 // Masking off high bits which are always zero is useless.
a61af66fc99e Initial load
duke
parents:
diff changeset
572 const TypeLong* t1 = phase->type( in(1) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
573 if (t1 != NULL && t1->_lo >= 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
574 jlong t1_support = ((jlong)1 << (1 + log2_long(t1->_hi))) - 1;
a61af66fc99e Initial load
duke
parents:
diff changeset
575 if ((t1_support & con) == t1_support)
a61af66fc99e Initial load
duke
parents:
diff changeset
576 return usr;
a61af66fc99e Initial load
duke
parents:
diff changeset
577 }
a61af66fc99e Initial load
duke
parents:
diff changeset
578 uint lop = usr->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
579 // Masking off the high bits of a unsigned-shift-right is not
a61af66fc99e Initial load
duke
parents:
diff changeset
580 // needed either.
a61af66fc99e Initial load
duke
parents:
diff changeset
581 if( lop == Op_URShiftL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
582 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
583 if( t12 && t12->is_con() ) { // Shift is by a constant
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
584 int shift = t12->get_con();
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
585 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
586 jlong mask = max_julong >> shift;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
587 if( (mask&con) == mask ) // If AND is useless, skip it
a61af66fc99e Initial load
duke
parents:
diff changeset
588 return usr;
a61af66fc99e Initial load
duke
parents:
diff changeset
589 }
a61af66fc99e Initial load
duke
parents:
diff changeset
590 }
a61af66fc99e Initial load
duke
parents:
diff changeset
591 }
a61af66fc99e Initial load
duke
parents:
diff changeset
592 return MulNode::Identity(phase);
a61af66fc99e Initial load
duke
parents:
diff changeset
593 }
a61af66fc99e Initial load
duke
parents:
diff changeset
594
a61af66fc99e Initial load
duke
parents:
diff changeset
595 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
596 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
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parents:
diff changeset
597 // Special case constant AND mask
a61af66fc99e Initial load
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parents:
diff changeset
598 const TypeLong *t2 = phase->type( in(2) )->isa_long();
a61af66fc99e Initial load
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parents:
diff changeset
599 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
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parents:
diff changeset
600 const jlong mask = t2->get_con();
a61af66fc99e Initial load
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parents:
diff changeset
601
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 559
diff changeset
602 Node* in1 = in(1);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 559
diff changeset
603 uint op = in1->Opcode();
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 559
diff changeset
604
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
605 // Are we masking a long that was converted from an int with a mask
897
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
606 // that fits in 32-bits? Commute them and use an AndINode. Don't
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
607 // convert masks which would cause a sign extension of the integer
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
608 // value. This check includes UI2L masks (0x00000000FFFFFFFF) which
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
609 // would be optimized away later in Identity.
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
610 if (op == Op_ConvI2L && (mask & CONST64(0xFFFFFFFF80000000)) == 0) {
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
611 Node* andi = new (phase->C) AndINode(in1->in(1), phase->intcon(mask));
897
52898b0c43e9 6863155: Server compiler generates incorrect code (x86, long, bitshift, bitmask)
twisti
parents: 824
diff changeset
612 andi = phase->transform(andi);
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
613 return new (phase->C) ConvI2LNode(andi);
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
614 }
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
615
0
a61af66fc99e Initial load
duke
parents:
diff changeset
616 // Masking off sign bits? Dont make them!
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 559
diff changeset
617 if (op == Op_RShiftL) {
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 624
diff changeset
618 const TypeInt* t12 = phase->type(in1->in(2))->isa_int();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
619 if( t12 && t12->is_con() ) { // Shift is by a constant
a61af66fc99e Initial load
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parents:
diff changeset
620 int shift = t12->get_con();
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
621 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
622 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - shift)) -1);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
623 // If the AND'ing of the 2 masks has no bits, then only original shifted
a61af66fc99e Initial load
duke
parents:
diff changeset
624 // bits survive. NO sign-extension bits survive the maskings.
a61af66fc99e Initial load
duke
parents:
diff changeset
625 if( (sign_bits_mask & mask) == 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
626 // Use zero-fill shift instead
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
627 Node *zshift = phase->transform(new (phase->C) URShiftLNode(in1->in(1), in1->in(2)));
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
628 return new (phase->C) AndLNode(zshift, in(2));
0
a61af66fc99e Initial load
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parents:
diff changeset
629 }
a61af66fc99e Initial load
duke
parents:
diff changeset
630 }
a61af66fc99e Initial load
duke
parents:
diff changeset
631 }
a61af66fc99e Initial load
duke
parents:
diff changeset
632
a61af66fc99e Initial load
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parents:
diff changeset
633 return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
duke
parents:
diff changeset
634 }
a61af66fc99e Initial load
duke
parents:
diff changeset
635
a61af66fc99e Initial load
duke
parents:
diff changeset
636 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
637 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
638 Node *LShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
639 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
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parents:
diff changeset
640 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
641 }
a61af66fc99e Initial load
duke
parents:
diff changeset
642
a61af66fc99e Initial load
duke
parents:
diff changeset
643 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
644 // If the right input is a constant, and the left input is an add of a
a61af66fc99e Initial load
duke
parents:
diff changeset
645 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
a61af66fc99e Initial load
duke
parents:
diff changeset
646 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
647 const Type *t = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
648 if( t == Type::TOP ) return NULL; // Right input is dead
a61af66fc99e Initial load
duke
parents:
diff changeset
649 const TypeInt *t2 = t->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
650 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
651 const int con = t2->get_con() & ( BitsPerInt - 1 ); // masked shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
652
a61af66fc99e Initial load
duke
parents:
diff changeset
653 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
654
a61af66fc99e Initial load
duke
parents:
diff changeset
655 // Left input is an add of a constant?
a61af66fc99e Initial load
duke
parents:
diff changeset
656 Node *add1 = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
657 int add1_op = add1->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
658 if( add1_op == Op_AddI ) { // Left input is an add?
a61af66fc99e Initial load
duke
parents:
diff changeset
659 assert( add1 != add1->in(1), "dead loop in LShiftINode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
660 const TypeInt *t12 = phase->type(add1->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
661 if( t12 && t12->is_con() ){ // Left input is an add of a con?
a61af66fc99e Initial load
duke
parents:
diff changeset
662 // Transform is legal, but check for profit. Avoid breaking 'i2s'
a61af66fc99e Initial load
duke
parents:
diff changeset
663 // and 'i2b' patterns which typically fold into 'StoreC/StoreB'.
a61af66fc99e Initial load
duke
parents:
diff changeset
664 if( con < 16 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
665 // Compute X << con0
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
666 Node *lsh = phase->transform( new (phase->C) LShiftINode( add1->in(1), in(2) ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
667 // Compute X<<con0 + (con1<<con0)
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
668 return new (phase->C) AddINode( lsh, phase->intcon(t12->get_con() << con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
669 }
a61af66fc99e Initial load
duke
parents:
diff changeset
670 }
a61af66fc99e Initial load
duke
parents:
diff changeset
671 }
a61af66fc99e Initial load
duke
parents:
diff changeset
672
a61af66fc99e Initial load
duke
parents:
diff changeset
673 // Check for "(x>>c0)<<c0" which just masks off low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
674 if( (add1_op == Op_RShiftI || add1_op == Op_URShiftI ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
675 add1->in(2) == in(2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
676 // Convert to "(x & -(1<<c0))"
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
677 return new (phase->C) AndINode(add1->in(1),phase->intcon( -(1<<con)));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
678
a61af66fc99e Initial load
duke
parents:
diff changeset
679 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
680 if( add1_op == Op_AndI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
681 Node *add2 = add1->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
682 int add2_op = add2->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
683 if( (add2_op == Op_RShiftI || add2_op == Op_URShiftI ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
684 add2->in(2) == in(2) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
685 // Convert to "(x & (Y<<c0))"
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
686 Node *y_sh = phase->transform( new (phase->C) LShiftINode( add1->in(2), in(2) ) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
687 return new (phase->C) AndINode( add2->in(1), y_sh );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
688 }
a61af66fc99e Initial load
duke
parents:
diff changeset
689 }
a61af66fc99e Initial load
duke
parents:
diff changeset
690
a61af66fc99e Initial load
duke
parents:
diff changeset
691 // Check for ((x & ((1<<(32-c0))-1)) << c0) which ANDs off high bits
a61af66fc99e Initial load
duke
parents:
diff changeset
692 // before shifting them away.
a61af66fc99e Initial load
duke
parents:
diff changeset
693 const jint bits_mask = right_n_bits(BitsPerJavaInteger-con);
a61af66fc99e Initial load
duke
parents:
diff changeset
694 if( add1_op == Op_AndI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
695 phase->type(add1->in(2)) == TypeInt::make( bits_mask ) )
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
696 return new (phase->C) LShiftINode( add1->in(1), in(2) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
697
a61af66fc99e Initial load
duke
parents:
diff changeset
698 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
699 }
a61af66fc99e Initial load
duke
parents:
diff changeset
700
a61af66fc99e Initial load
duke
parents:
diff changeset
701 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
702 // A LShiftINode shifts its input2 left by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
703 const Type *LShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
704 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
705 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
706 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
707 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
708 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
709
a61af66fc99e Initial load
duke
parents:
diff changeset
710 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
711 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
712 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
713 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
714
a61af66fc99e Initial load
duke
parents:
diff changeset
715 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
716 if( (t1 == TypeInt::INT) || (t2 == TypeInt::INT) ||
a61af66fc99e Initial load
duke
parents:
diff changeset
717 (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
a61af66fc99e Initial load
duke
parents:
diff changeset
718 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
719
a61af66fc99e Initial load
duke
parents:
diff changeset
720 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
721 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
722
a61af66fc99e Initial load
duke
parents:
diff changeset
723 if (!r2->is_con())
a61af66fc99e Initial load
duke
parents:
diff changeset
724 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
725
a61af66fc99e Initial load
duke
parents:
diff changeset
726 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
727 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
728 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
729 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
730
a61af66fc99e Initial load
duke
parents:
diff changeset
731 // If the shift is a constant, shift the bounds of the type,
a61af66fc99e Initial load
duke
parents:
diff changeset
732 // unless this could lead to an overflow.
a61af66fc99e Initial load
duke
parents:
diff changeset
733 if (!r1->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
734 jint lo = r1->_lo, hi = r1->_hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
735 if (((lo << shift) >> shift) == lo &&
a61af66fc99e Initial load
duke
parents:
diff changeset
736 ((hi << shift) >> shift) == hi) {
a61af66fc99e Initial load
duke
parents:
diff changeset
737 // No overflow. The range shifts up cleanly.
a61af66fc99e Initial load
duke
parents:
diff changeset
738 return TypeInt::make((jint)lo << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
739 (jint)hi << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
740 MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
741 }
a61af66fc99e Initial load
duke
parents:
diff changeset
742 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
743 }
a61af66fc99e Initial load
duke
parents:
diff changeset
744
a61af66fc99e Initial load
duke
parents:
diff changeset
745 return TypeInt::make( (jint)r1->get_con() << (jint)shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
746 }
a61af66fc99e Initial load
duke
parents:
diff changeset
747
a61af66fc99e Initial load
duke
parents:
diff changeset
748 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
749 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
750 Node *LShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
751 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
752 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
753 }
a61af66fc99e Initial load
duke
parents:
diff changeset
754
a61af66fc99e Initial load
duke
parents:
diff changeset
755 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
756 // If the right input is a constant, and the left input is an add of a
a61af66fc99e Initial load
duke
parents:
diff changeset
757 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
a61af66fc99e Initial load
duke
parents:
diff changeset
758 Node *LShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
759 const Type *t = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
760 if( t == Type::TOP ) return NULL; // Right input is dead
a61af66fc99e Initial load
duke
parents:
diff changeset
761 const TypeInt *t2 = t->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
762 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
763 const int con = t2->get_con() & ( BitsPerLong - 1 ); // masked shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
764
a61af66fc99e Initial load
duke
parents:
diff changeset
765 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
766
a61af66fc99e Initial load
duke
parents:
diff changeset
767 // Left input is an add of a constant?
a61af66fc99e Initial load
duke
parents:
diff changeset
768 Node *add1 = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
769 int add1_op = add1->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
770 if( add1_op == Op_AddL ) { // Left input is an add?
a61af66fc99e Initial load
duke
parents:
diff changeset
771 // Avoid dead data cycles from dead loops
a61af66fc99e Initial load
duke
parents:
diff changeset
772 assert( add1 != add1->in(1), "dead loop in LShiftLNode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
773 const TypeLong *t12 = phase->type(add1->in(2))->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
774 if( t12 && t12->is_con() ){ // Left input is an add of a con?
a61af66fc99e Initial load
duke
parents:
diff changeset
775 // Compute X << con0
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
776 Node *lsh = phase->transform( new (phase->C) LShiftLNode( add1->in(1), in(2) ) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
777 // Compute X<<con0 + (con1<<con0)
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
778 return new (phase->C) AddLNode( lsh, phase->longcon(t12->get_con() << con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
779 }
a61af66fc99e Initial load
duke
parents:
diff changeset
780 }
a61af66fc99e Initial load
duke
parents:
diff changeset
781
a61af66fc99e Initial load
duke
parents:
diff changeset
782 // Check for "(x>>c0)<<c0" which just masks off low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
783 if( (add1_op == Op_RShiftL || add1_op == Op_URShiftL ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
784 add1->in(2) == in(2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
785 // Convert to "(x & -(1<<c0))"
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
786 return new (phase->C) AndLNode(add1->in(1),phase->longcon( -(CONST64(1)<<con)));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
787
a61af66fc99e Initial load
duke
parents:
diff changeset
788 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
789 if( add1_op == Op_AndL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
790 Node *add2 = add1->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
791 int add2_op = add2->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
792 if( (add2_op == Op_RShiftL || add2_op == Op_URShiftL ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
793 add2->in(2) == in(2) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
794 // Convert to "(x & (Y<<c0))"
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
795 Node *y_sh = phase->transform( new (phase->C) LShiftLNode( add1->in(2), in(2) ) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
796 return new (phase->C) AndLNode( add2->in(1), y_sh );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
797 }
a61af66fc99e Initial load
duke
parents:
diff changeset
798 }
a61af66fc99e Initial load
duke
parents:
diff changeset
799
a61af66fc99e Initial load
duke
parents:
diff changeset
800 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
a61af66fc99e Initial load
duke
parents:
diff changeset
801 // before shifting them away.
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
802 const jlong bits_mask = ((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - con)) - CONST64(1);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
803 if( add1_op == Op_AndL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
804 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
805 return new (phase->C) LShiftLNode( add1->in(1), in(2) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
806
a61af66fc99e Initial load
duke
parents:
diff changeset
807 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
808 }
a61af66fc99e Initial load
duke
parents:
diff changeset
809
a61af66fc99e Initial load
duke
parents:
diff changeset
810 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
811 // A LShiftLNode shifts its input2 left by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
812 const Type *LShiftLNode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
813 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
814 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
815 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
816 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
817 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
818
a61af66fc99e Initial load
duke
parents:
diff changeset
819 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
820 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
821 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
822 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
823
a61af66fc99e Initial load
duke
parents:
diff changeset
824 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
825 if( (t1 == TypeLong::LONG) || (t2 == TypeInt::INT) ||
a61af66fc99e Initial load
duke
parents:
diff changeset
826 (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
a61af66fc99e Initial load
duke
parents:
diff changeset
827 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
828
a61af66fc99e Initial load
duke
parents:
diff changeset
829 const TypeLong *r1 = t1->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
830 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
831
a61af66fc99e Initial load
duke
parents:
diff changeset
832 if (!r2->is_con())
a61af66fc99e Initial load
duke
parents:
diff changeset
833 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
834
a61af66fc99e Initial load
duke
parents:
diff changeset
835 uint shift = r2->get_con();
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
836 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
0
a61af66fc99e Initial load
duke
parents:
diff changeset
837 // Shift by a multiple of 64 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
838 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
839
a61af66fc99e Initial load
duke
parents:
diff changeset
840 // If the shift is a constant, shift the bounds of the type,
a61af66fc99e Initial load
duke
parents:
diff changeset
841 // unless this could lead to an overflow.
a61af66fc99e Initial load
duke
parents:
diff changeset
842 if (!r1->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
843 jlong lo = r1->_lo, hi = r1->_hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
844 if (((lo << shift) >> shift) == lo &&
a61af66fc99e Initial load
duke
parents:
diff changeset
845 ((hi << shift) >> shift) == hi) {
a61af66fc99e Initial load
duke
parents:
diff changeset
846 // No overflow. The range shifts up cleanly.
a61af66fc99e Initial load
duke
parents:
diff changeset
847 return TypeLong::make((jlong)lo << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
848 (jlong)hi << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
849 MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
850 }
a61af66fc99e Initial load
duke
parents:
diff changeset
851 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
852 }
a61af66fc99e Initial load
duke
parents:
diff changeset
853
a61af66fc99e Initial load
duke
parents:
diff changeset
854 return TypeLong::make( (jlong)r1->get_con() << (jint)shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
855 }
a61af66fc99e Initial load
duke
parents:
diff changeset
856
a61af66fc99e Initial load
duke
parents:
diff changeset
857 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
858 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
859 Node *RShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
860 const TypeInt *t2 = phase->type(in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
861 if( !t2 ) return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
862 if ( t2->is_con() && ( t2->get_con() & ( BitsPerInt - 1 ) ) == 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
863 return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
864
a61af66fc99e Initial load
duke
parents:
diff changeset
865 // Check for useless sign-masking
a61af66fc99e Initial load
duke
parents:
diff changeset
866 if( in(1)->Opcode() == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
867 in(1)->req() == 3 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
868 in(1)->in(2) == in(2) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
869 t2->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
870 uint shift = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
871 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
872 // Compute masks for which this shifting doesn't change
a61af66fc99e Initial load
duke
parents:
diff changeset
873 int lo = (-1 << (BitsPerJavaInteger - shift-1)); // FFFF8000
a61af66fc99e Initial load
duke
parents:
diff changeset
874 int hi = ~lo; // 00007FFF
a61af66fc99e Initial load
duke
parents:
diff changeset
875 const TypeInt *t11 = phase->type(in(1)->in(1))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
876 if( !t11 ) return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
877 // Does actual value fit inside of mask?
a61af66fc99e Initial load
duke
parents:
diff changeset
878 if( lo <= t11->_lo && t11->_hi <= hi )
a61af66fc99e Initial load
duke
parents:
diff changeset
879 return in(1)->in(1); // Then shifting is a nop
a61af66fc99e Initial load
duke
parents:
diff changeset
880 }
a61af66fc99e Initial load
duke
parents:
diff changeset
881
a61af66fc99e Initial load
duke
parents:
diff changeset
882 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
883 }
a61af66fc99e Initial load
duke
parents:
diff changeset
884
a61af66fc99e Initial load
duke
parents:
diff changeset
885 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
886 Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
887 // Inputs may be TOP if they are dead.
a61af66fc99e Initial load
duke
parents:
diff changeset
888 const TypeInt *t1 = phase->type( in(1) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
889 if( !t1 ) return NULL; // Left input is an integer
a61af66fc99e Initial load
duke
parents:
diff changeset
890 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
891 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
892 const TypeInt *t3; // type of in(1).in(2)
a61af66fc99e Initial load
duke
parents:
diff changeset
893 int shift = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
894 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
895
a61af66fc99e Initial load
duke
parents:
diff changeset
896 if ( shift == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
897
a61af66fc99e Initial load
duke
parents:
diff changeset
898 // Check for (x & 0xFF000000) >> 24, whose mask can be made smaller.
a61af66fc99e Initial load
duke
parents:
diff changeset
899 // Such expressions arise normally from shift chains like (byte)(x >> 24).
a61af66fc99e Initial load
duke
parents:
diff changeset
900 const Node *mask = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
901 if( mask->Opcode() == Op_AndI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
902 (t3 = phase->type(mask->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
903 t3->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
904 Node *x = mask->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
905 jint maskbits = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
906 // Convert to "(x >> shift) & (mask >> shift)"
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
907 Node *shr_nomask = phase->transform( new (phase->C) RShiftINode(mask->in(1), in(2)) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
908 return new (phase->C) AndINode(shr_nomask, phase->intcon( maskbits >> shift));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
909 }
a61af66fc99e Initial load
duke
parents:
diff changeset
910
a61af66fc99e Initial load
duke
parents:
diff changeset
911 // Check for "(short[i] <<16)>>16" which simply sign-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
912 const Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
913 if( shl->Opcode() != Op_LShiftI ) return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
914
a61af66fc99e Initial load
duke
parents:
diff changeset
915 if( shift == 16 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
916 (t3 = phase->type(shl->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
917 t3->is_con(16) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
918 Node *ld = shl->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
919 if( ld->Opcode() == Op_LoadS ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
920 // Sign extension is just useless here. Return a RShiftI of zero instead
a61af66fc99e Initial load
duke
parents:
diff changeset
921 // returning 'ld' directly. We cannot return an old Node directly as
a61af66fc99e Initial load
duke
parents:
diff changeset
922 // that is the job of 'Identity' calls and Identity calls only work on
a61af66fc99e Initial load
duke
parents:
diff changeset
923 // direct inputs ('ld' is an extra Node removed from 'this'). The
a61af66fc99e Initial load
duke
parents:
diff changeset
924 // combined optimization requires Identity only return direct inputs.
a61af66fc99e Initial load
duke
parents:
diff changeset
925 set_req(1, ld);
a61af66fc99e Initial load
duke
parents:
diff changeset
926 set_req(2, phase->intcon(0));
a61af66fc99e Initial load
duke
parents:
diff changeset
927 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
928 }
6891
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
929 else if( can_reshape &&
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
930 ld->Opcode() == Op_LoadUS &&
67f4c477c9ab 8000805: JMM issue: short loads are non-atomic
vlivanov
parents: 6853
diff changeset
931 ld->outcnt() == 1 && ld->unique_out() == shl)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
932 // Replace zero-extension-load with sign-extension-load
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
933 return new (phase->C) LoadSNode( ld->in(MemNode::Control),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
934 ld->in(MemNode::Memory),
a61af66fc99e Initial load
duke
parents:
diff changeset
935 ld->in(MemNode::Address),
a61af66fc99e Initial load
duke
parents:
diff changeset
936 ld->adr_type());
a61af66fc99e Initial load
duke
parents:
diff changeset
937 }
a61af66fc99e Initial load
duke
parents:
diff changeset
938
a61af66fc99e Initial load
duke
parents:
diff changeset
939 // Check for "(byte[i] <<24)>>24" which simply sign-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
940 if( shift == 24 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
941 (t3 = phase->type(shl->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
942 t3->is_con(24) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
943 Node *ld = shl->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
944 if( ld->Opcode() == Op_LoadB ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
945 // Sign extension is just useless here
a61af66fc99e Initial load
duke
parents:
diff changeset
946 set_req(1, ld);
a61af66fc99e Initial load
duke
parents:
diff changeset
947 set_req(2, phase->intcon(0));
a61af66fc99e Initial load
duke
parents:
diff changeset
948 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
949 }
a61af66fc99e Initial load
duke
parents:
diff changeset
950 }
a61af66fc99e Initial load
duke
parents:
diff changeset
951
a61af66fc99e Initial load
duke
parents:
diff changeset
952 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
953 }
a61af66fc99e Initial load
duke
parents:
diff changeset
954
a61af66fc99e Initial load
duke
parents:
diff changeset
955 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
956 // A RShiftINode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
957 const Type *RShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
958 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
959 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
960 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
961 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
962 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
963
a61af66fc99e Initial load
duke
parents:
diff changeset
964 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
965 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
966 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
967 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
968
a61af66fc99e Initial load
duke
parents:
diff changeset
969 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
970 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
971 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
972
a61af66fc99e Initial load
duke
parents:
diff changeset
973 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
974 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
975
a61af66fc99e Initial load
duke
parents:
diff changeset
976 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
977 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
978
a61af66fc99e Initial load
duke
parents:
diff changeset
979 // If the shift is a constant, just shift the bounds of the type.
a61af66fc99e Initial load
duke
parents:
diff changeset
980 // For example, if the shift is 31, we just propagate sign bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
981 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
982 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
983 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
984 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
985 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
986 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
987 // This is necessary if we are to correctly type things
a61af66fc99e Initial load
duke
parents:
diff changeset
988 // like (x<<24>>24) == ((byte)x).
a61af66fc99e Initial load
duke
parents:
diff changeset
989 jint lo = (jint)r1->_lo >> (jint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
990 jint hi = (jint)r1->_hi >> (jint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
991 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
992 const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
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parents:
diff changeset
993 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
994 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
995 if (shift == BitsPerJavaInteger-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
996 if (r1->_lo >= 0) assert(ti == TypeInt::ZERO, ">>31 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
997 if (r1->_hi < 0) assert(ti == TypeInt::MINUS_1, ">>31 of - is -1");
a61af66fc99e Initial load
duke
parents:
diff changeset
998 }
a61af66fc99e Initial load
duke
parents:
diff changeset
999 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 return ti;
a61af66fc99e Initial load
duke
parents:
diff changeset
1001 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1002
a61af66fc99e Initial load
duke
parents:
diff changeset
1003 if( !r1->is_con() || !r2->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1004 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1005
a61af66fc99e Initial load
duke
parents:
diff changeset
1006 // Signed shift right
a61af66fc99e Initial load
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parents:
diff changeset
1007 return TypeInt::make( r1->get_con() >> (r2->get_con()&31) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1008 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1009
a61af66fc99e Initial load
duke
parents:
diff changeset
1010 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1011 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1012 Node *RShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1013 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1016
a61af66fc99e Initial load
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parents:
diff changeset
1017 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
1018 // A RShiftLNode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 const Type *RShiftLNode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1022 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
1023 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1025
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
1028 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1030
a61af66fc99e Initial load
duke
parents:
diff changeset
1031 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
1032 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
1033 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
1034
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
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parents:
diff changeset
1036 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
1037
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 const TypeLong *r1 = t1->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 const TypeInt *r2 = t2->is_int (); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1040
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 // If the shift is a constant, just shift the bounds of the type.
a61af66fc99e Initial load
duke
parents:
diff changeset
1042 // For example, if the shift is 63, we just propagate sign bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
1043 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1044 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1045 shift &= (2*BitsPerJavaInteger)-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
1046 // Shift by a multiple of 64 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
1047 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1048 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
1049 // This is necessary if we are to correctly type things
a61af66fc99e Initial load
duke
parents:
diff changeset
1050 // like (x<<24>>24) == ((byte)x).
a61af66fc99e Initial load
duke
parents:
diff changeset
1051 jlong lo = (jlong)r1->_lo >> (jlong)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1052 jlong hi = (jlong)r1->_hi >> (jlong)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1053 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
1054 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
1055 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1056 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
1057 if (shift == (2*BitsPerJavaInteger)-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1058 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>63 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
1059 if (r1->_hi < 0) assert(tl == TypeLong::MINUS_1, ">>63 of - is -1");
a61af66fc99e Initial load
duke
parents:
diff changeset
1060 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1061 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 return tl;
a61af66fc99e Initial load
duke
parents:
diff changeset
1063 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1064
a61af66fc99e Initial load
duke
parents:
diff changeset
1065 return TypeLong::LONG; // Give up
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1067
a61af66fc99e Initial load
duke
parents:
diff changeset
1068 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1070 Node *URShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 const TypeInt *ti = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 if ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1073
a61af66fc99e Initial load
duke
parents:
diff changeset
1074 // Check for "((x << LogBytesPerWord) + (wordSize-1)) >> LogBytesPerWord" which is just "x".
a61af66fc99e Initial load
duke
parents:
diff changeset
1075 // Happens during new-array length computation.
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 // Safe if 'x' is in the range [0..(max_int>>LogBytesPerWord)]
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1078 if( add->Opcode() == Op_AddI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1079 const TypeInt *t2 = phase->type(add->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 if( t2 && t2->is_con(wordSize - 1) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 add->in(1)->Opcode() == Op_LShiftI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1082 // Check that shift_counts are LogBytesPerWord
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 Node *lshift_count = add->in(1)->in(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1084 const TypeInt *t_lshift_count = phase->type(lshift_count)->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 if( t_lshift_count && t_lshift_count->is_con(LogBytesPerWord) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1086 t_lshift_count == phase->type(in(2)) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 Node *x = add->in(1)->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 const TypeInt *t_x = phase->type(x)->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 if( t_x != NULL && 0 <= t_x->_lo && t_x->_hi <= (max_jint>>LogBytesPerWord) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 return x;
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1093 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1094 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1095
a61af66fc99e Initial load
duke
parents:
diff changeset
1096 return (phase->type(in(2))->higher_equal(TypeInt::ZERO)) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
1097 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1098
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 Node *URShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1103 const int con = t2->get_con() & 31; // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1104 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1105 // We'll be wanting the right-shift amount as a mask of that many bits
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 const int mask = right_n_bits(BitsPerJavaInteger - con);
a61af66fc99e Initial load
duke
parents:
diff changeset
1107
a61af66fc99e Initial load
duke
parents:
diff changeset
1108 int in1_op = in(1)->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
1109
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 // Check for ((x>>>a)>>>b) and replace with (x>>>(a+b)) when a+b < 32
a61af66fc99e Initial load
duke
parents:
diff changeset
1111 if( in1_op == Op_URShiftI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 const TypeInt *t12 = phase->type( in(1)->in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1113 if( t12 && t12->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 assert( in(1) != in(1)->in(1), "dead loop in URShiftINode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1115 const int con2 = t12->get_con() & 31; // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1116 const int con3 = con+con2;
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 if( con3 < 32 ) // Only merge shifts if total is < 32
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1118 return new (phase->C) URShiftINode( in(1)->in(1), phase->intcon(con3) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1120 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1121
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 // If Q is "X << z" the rounding is useless. Look for patterns like
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 if( in1_op == Op_AddI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 Node *lshl = add->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 if( lshl->Opcode() == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1130 phase->type(lshl->in(2)) == t2 ) {
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1131 Node *y_z = phase->transform( new (phase->C) URShiftINode(add->in(2),in(2)) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1132 Node *sum = phase->transform( new (phase->C) AddINode( lshl->in(1), y_z ) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1133 return new (phase->C) AndINode( sum, phase->intcon(mask) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1136
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 // This shortens the mask. Also, if we are extracting a high byte and
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 // storing it to a buffer, the mask will be removed completely.
a61af66fc99e Initial load
duke
parents:
diff changeset
1140 Node *andi = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1141 if( in1_op == Op_AndI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1142 const TypeInt *t3 = phase->type( andi->in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 if( t3 && t3->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 jint mask2 = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1146 Node *newshr = phase->transform( new (phase->C) URShiftINode(andi->in(1), in(2)) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1147 return new (phase->C) AndINode(newshr, phase->intcon(mask2));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 // The negative values are easier to materialize than positive ones.
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 // A typical case from address arithmetic is ((x & ~15) >> 4).
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 // It's better to change that to ((x >> 4) & ~0) versus
a61af66fc99e Initial load
duke
parents:
diff changeset
1151 // ((x >> 4) & 0x0FFFFFFF). The difference is greatest in LP64.
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1154
a61af66fc99e Initial load
duke
parents:
diff changeset
1155 // Check for "(X << z ) >>> z" which simply zero-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1157 if( in1_op == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 phase->type(shl->in(2)) == t2 )
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1159 return new (phase->C) AndINode( shl->in(1), phase->intcon(mask) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1160
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1163
a61af66fc99e Initial load
duke
parents:
diff changeset
1164 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 // A URShiftINode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 const Type *URShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1167 // (This is a near clone of RShiftINode::Value.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1173
a61af66fc99e Initial load
duke
parents:
diff changeset
1174 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
1175 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
1177 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1178
a61af66fc99e Initial load
duke
parents:
diff changeset
1179 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1182
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1185
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1188
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
1195 jint lo = (juint)r1->_lo >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 jint hi = (juint)r1->_hi >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 if (r1->_hi >= 0 && r1->_lo < 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 // If the type has both negative and positive values,
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 // there are two separate sub-domains to worry about:
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 // The positive half and the negative half.
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 jint neg_lo = lo;
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 jint neg_hi = (juint)-1 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 jint pos_lo = (juint) 0 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 jint pos_hi = hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 lo = MIN2(neg_lo, pos_lo); // == 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 hi = MAX2(neg_hi, pos_hi); // == -1 >>> shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 if (shift == BitsPerJavaInteger-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 if (r1->_lo >= 0) assert(ti == TypeInt::ZERO, ">>>31 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 if (r1->_hi < 0) assert(ti == TypeInt::ONE, ">>>31 of - is +1");
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 return ti;
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1219
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 // Do not support shifted oops in info for GC
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 // else if( t1->base() == Type::InstPtr ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1225 // const TypeInstPtr *o = t1->is_instptr();
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 // if( t1->singleton() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 // return TypeInt::make( ((uint32)o->const_oop() + o->_offset) >> shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 // }
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 // else if( t1->base() == Type::KlassPtr ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 // const TypeKlassPtr *o = t1->is_klassptr();
a61af66fc99e Initial load
duke
parents:
diff changeset
1231 // if( t1->singleton() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1232 // return TypeInt::make( ((uint32)o->const_oop() + o->_offset) >> shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 // }
a61af66fc99e Initial load
duke
parents:
diff changeset
1234
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1237
a61af66fc99e Initial load
duke
parents:
diff changeset
1238 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 Node *URShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1241 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1244
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 Node *URShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1247 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1248 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1249 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 // note: mask computation below does not work for 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1252 // We'll be wanting the right-shift amount as a mask of that many bits
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
1253 const jlong mask = (((jlong)CONST64(1) << (jlong)(BitsPerJavaLong - con)) -1);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1254
a61af66fc99e Initial load
duke
parents:
diff changeset
1255 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
a61af66fc99e Initial load
duke
parents:
diff changeset
1256 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
a61af66fc99e Initial load
duke
parents:
diff changeset
1257 // If Q is "X << z" the rounding is useless. Look for patterns like
a61af66fc99e Initial load
duke
parents:
diff changeset
1258 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
a61af66fc99e Initial load
duke
parents:
diff changeset
1259 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1260 if( add->Opcode() == Op_AddL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 Node *lshl = add->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1262 if( lshl->Opcode() == Op_LShiftL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1263 phase->type(lshl->in(2)) == t2 ) {
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1264 Node *y_z = phase->transform( new (phase->C) URShiftLNode(add->in(2),in(2)) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1265 Node *sum = phase->transform( new (phase->C) AddLNode( lshl->in(1), y_z ) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1266 return new (phase->C) AndLNode( sum, phase->longcon(mask) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1267 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1269
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 // This shortens the mask. Also, if we are extracting a high byte and
a61af66fc99e Initial load
duke
parents:
diff changeset
1272 // storing it to a buffer, the mask will be removed completely.
a61af66fc99e Initial load
duke
parents:
diff changeset
1273 Node *andi = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1274 if( andi->Opcode() == Op_AndL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1275 const TypeLong *t3 = phase->type( andi->in(2) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 if( t3 && t3->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1277 jlong mask2 = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1279 Node *newshr = phase->transform( new (phase->C) URShiftLNode(andi->in(1), in(2)) );
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1280 return new (phase->C) AndLNode(newshr, phase->longcon(mask2));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1282 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1283
a61af66fc99e Initial load
duke
parents:
diff changeset
1284 // Check for "(X << z ) >>> z" which simply zero-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 if( shl->Opcode() == Op_LShiftL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 phase->type(shl->in(2)) == t2 )
6804
e626685e9f6c 7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents: 3842
diff changeset
1288 return new (phase->C) AndLNode( shl->in(1), phase->longcon(mask) );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1289
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1291 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1292
a61af66fc99e Initial load
duke
parents:
diff changeset
1293 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1294 // A URShiftINode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
1295 const Type *URShiftLNode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 // (This is a near clone of RShiftLNode::Value.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1297 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1298 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1299 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1301 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1302
a61af66fc99e Initial load
duke
parents:
diff changeset
1303 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
1304 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
1305 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
1306 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1307
a61af66fc99e Initial load
duke
parents:
diff changeset
1308 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
1309 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
1311
a61af66fc99e Initial load
duke
parents:
diff changeset
1312 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
1313 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
1314
a61af66fc99e Initial load
duke
parents:
diff changeset
1315 const TypeLong *r1 = t1->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1316 const TypeInt *r2 = t2->is_int (); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1317
a61af66fc99e Initial load
duke
parents:
diff changeset
1318 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1319 uint shift = r2->get_con();
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
1320 shift &= BitsPerJavaLong - 1; // semantics of Java shifts
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1321 // Shift by a multiple of 64 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1323 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
1324 jlong lo = (julong)r1->_lo >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1325 jlong hi = (julong)r1->_hi >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1326 if (r1->_hi >= 0 && r1->_lo < 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1327 // If the type has both negative and positive values,
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 // there are two separate sub-domains to worry about:
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 // The positive half and the negative half.
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 jlong neg_lo = lo;
a61af66fc99e Initial load
duke
parents:
diff changeset
1331 jlong neg_hi = (julong)-1 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1332 jlong pos_lo = (julong) 0 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 jlong pos_hi = hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1334 //lo = MIN2(neg_lo, pos_lo); // == 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 lo = neg_lo < pos_lo ? neg_lo : pos_lo;
a61af66fc99e Initial load
duke
parents:
diff changeset
1336 //hi = MAX2(neg_hi, pos_hi); // == -1 >>> shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1337 hi = neg_hi > pos_hi ? neg_hi : pos_hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1338 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1339 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
1341 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 // Make sure we get the sign-capture idiom correct.
559
7628781568e1 6795362: 32bit server compiler leads to wrong results on solaris-x86
twisti
parents: 558
diff changeset
1343 if (shift == BitsPerJavaLong - 1) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>>63 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
1345 if (r1->_hi < 0) assert(tl == TypeLong::ONE, ">>>63 of - is +1");
a61af66fc99e Initial load
duke
parents:
diff changeset
1346 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1347 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 return tl;
a61af66fc99e Initial load
duke
parents:
diff changeset
1349 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1350
a61af66fc99e Initial load
duke
parents:
diff changeset
1351 return TypeLong::LONG; // Give up
a61af66fc99e Initial load
duke
parents:
diff changeset
1352 }