Mercurial > hg > truffle
annotate src/cpu/sparc/vm/nativeInst_sparc.cpp @ 2375:d673ef06fe96
7028374: race in fix_oop_relocations for scavengeable nmethods
Reviewed-by: kvn
| author | never |
|---|---|
| date | Fri, 18 Mar 2011 15:52:42 -0700 |
| parents | f95d63e2154a |
| children | 1d1603768966 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1579 | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_sparc.inline.hpp" | |
| 27 #include "memory/resourceArea.hpp" | |
| 28 #include "nativeInst_sparc.hpp" | |
| 29 #include "oops/oop.inline.hpp" | |
| 30 #include "runtime/handles.hpp" | |
| 31 #include "runtime/sharedRuntime.hpp" | |
| 32 #include "runtime/stubRoutines.hpp" | |
| 33 #include "utilities/ostream.hpp" | |
| 34 #ifdef COMPILER1 | |
| 35 #include "c1/c1_Runtime1.hpp" | |
| 36 #endif | |
| 0 | 37 |
| 38 | |
|
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39 bool NativeInstruction::is_dtrace_trap() { |
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40 return !is_nop(); |
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41 } |
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42 |
| 0 | 43 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) { |
| 44 ResourceMark rm; | |
| 45 CodeBuffer buf(instaddr, 10 * BytesPerInstWord ); | |
| 46 MacroAssembler* _masm = new MacroAssembler(&buf); | |
| 47 Register destreg; | |
| 48 | |
| 49 destreg = inv_rd(*(unsigned int *)instaddr); | |
| 50 // Generate a the new sequence | |
| 727 | 51 _masm->patchable_sethi(x, destreg); |
| 0 | 52 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord); |
| 53 } | |
| 54 | |
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55 void NativeInstruction::verify_data64_sethi(address instaddr, intptr_t x) { |
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56 ResourceMark rm; |
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57 unsigned char buffer[10 * BytesPerInstWord]; |
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58 CodeBuffer buf(buffer, 10 * BytesPerInstWord); |
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59 MacroAssembler masm(&buf); |
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60 |
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61 Register destreg = inv_rd(*(unsigned int *)instaddr); |
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62 // Generate the proper sequence into a temporary buffer and compare |
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63 // it with the original sequence. |
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64 masm.patchable_sethi(x, destreg); |
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65 int len = buffer - masm.pc(); |
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66 for (int i = 0; i < len; i++) { |
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67 assert(instaddr[i] == buffer[i], "instructions must match"); |
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68 } |
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69 } |
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70 |
| 0 | 71 void NativeInstruction::verify() { |
| 72 // make sure code pattern is actually an instruction address | |
| 73 address addr = addr_at(0); | |
| 74 if (addr == 0 || ((intptr_t)addr & 3) != 0) { | |
| 75 fatal("not an instruction address"); | |
| 76 } | |
| 77 } | |
| 78 | |
| 79 void NativeInstruction::print() { | |
| 80 tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0)); | |
| 81 } | |
| 82 | |
| 83 void NativeInstruction::set_long_at(int offset, int i) { | |
| 84 address addr = addr_at(offset); | |
| 85 *(int*)addr = i; | |
| 86 ICache::invalidate_word(addr); | |
| 87 } | |
| 88 | |
| 89 void NativeInstruction::set_jlong_at(int offset, jlong i) { | |
| 90 address addr = addr_at(offset); | |
| 91 *(jlong*)addr = i; | |
| 92 // Don't need to invalidate 2 words here, because | |
| 93 // the flush instruction operates on doublewords. | |
| 94 ICache::invalidate_word(addr); | |
| 95 } | |
| 96 | |
| 97 void NativeInstruction::set_addr_at(int offset, address x) { | |
| 98 address addr = addr_at(offset); | |
| 99 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment"); | |
| 100 *(uintptr_t*)addr = (uintptr_t)x; | |
| 101 // Don't need to invalidate 2 words here in the 64-bit case, | |
| 102 // because the flush instruction operates on doublewords. | |
| 103 ICache::invalidate_word(addr); | |
| 104 // The Intel code has this assertion for NativeCall::set_destination, | |
| 105 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset, | |
| 106 // NativeJump::set_jump_destination, and NativePushImm32::set_data | |
| 107 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction") | |
| 108 } | |
| 109 | |
| 110 bool NativeInstruction::is_zero_test(Register ®) { | |
| 111 int x = long_at(0); | |
| 112 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3); | |
| 113 if (is_op3(x, temp, Assembler::arith_op) && | |
| 114 inv_immed(x) && inv_rd(x) == G0) { | |
| 115 if (inv_rs1(x) == G0) { | |
| 116 reg = inv_rs2(x); | |
| 117 return true; | |
| 118 } else if (inv_rs2(x) == G0) { | |
| 119 reg = inv_rs1(x); | |
| 120 return true; | |
| 121 } | |
| 122 } | |
| 123 return false; | |
| 124 } | |
| 125 | |
| 126 bool NativeInstruction::is_load_store_with_small_offset(Register reg) { | |
| 127 int x = long_at(0); | |
| 128 if (is_op(x, Assembler::ldst_op) && | |
| 129 inv_rs1(x) == reg && inv_immed(x)) { | |
| 130 return true; | |
| 131 } | |
| 132 return false; | |
| 133 } | |
| 134 | |
| 135 void NativeCall::verify() { | |
| 136 NativeInstruction::verify(); | |
| 137 // make sure code pattern is actually a call instruction | |
| 138 if (!is_op(long_at(0), Assembler::call_op)) { | |
| 139 fatal("not a call"); | |
| 140 } | |
| 141 } | |
| 142 | |
| 143 void NativeCall::print() { | |
| 144 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); | |
| 145 } | |
| 146 | |
| 147 | |
| 148 // MT-safe patching of a call instruction (and following word). | |
| 149 // First patches the second word, and then atomicly replaces | |
| 150 // the first word with the first new instruction word. | |
| 151 // Other processors might briefly see the old first word | |
| 152 // followed by the new second word. This is OK if the old | |
| 153 // second word is harmless, and the new second word may be | |
| 154 // harmlessly executed in the delay slot of the call. | |
| 155 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { | |
| 156 assert(Patching_lock->is_locked() || | |
| 157 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
| 158 assert (instr_addr != NULL, "illegal address for code patching"); | |
| 159 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call | |
| 160 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8"); | |
| 161 int i0 = ((int*)code_buffer)[0]; | |
| 162 int i1 = ((int*)code_buffer)[1]; | |
| 163 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord); | |
| 164 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
| 165 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), | |
| 166 "must not interfere with original call"); | |
| 167 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order | |
| 168 n_call->set_long_at(1*BytesPerInstWord, i1); | |
| 169 n_call->set_long_at(0*BytesPerInstWord, i0); | |
| 170 // NOTE: It is possible that another thread T will execute | |
| 171 // only the second patched word. | |
| 172 // In other words, since the original instruction is this | |
| 173 // call patching_stub; nop (NativeCall) | |
| 174 // and the new sequence from the buffer is this: | |
| 175 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) | |
| 176 // what T will execute is this: | |
| 177 // call patching_stub; add %r, %lo(K), %r | |
| 178 // thereby putting garbage into %r before calling the patching stub. | |
| 179 // This is OK, because the patching stub ignores the value of %r. | |
| 180 | |
| 181 // Make sure the first-patched instruction, which may co-exist | |
| 182 // briefly with the call, will do something harmless. | |
| 183 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
| 184 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), | |
| 185 "must not interfere with original call"); | |
| 186 } | |
| 187 | |
| 188 // Similar to replace_mt_safe, but just changes the destination. The | |
| 189 // important thing is that free-running threads are able to execute this | |
| 190 // call instruction at all times. Thus, the displacement field must be | |
| 191 // instruction-word-aligned. This is always true on SPARC. | |
| 192 // | |
| 193 // Used in the runtime linkage of calls; see class CompiledIC. | |
| 194 void NativeCall::set_destination_mt_safe(address dest) { | |
| 195 assert(Patching_lock->is_locked() || | |
| 196 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
| 197 // set_destination uses set_long_at which does the ICache::invalidate | |
| 198 set_destination(dest); | |
| 199 } | |
| 200 | |
| 201 // Code for unit testing implementation of NativeCall class | |
| 202 void NativeCall::test() { | |
| 203 #ifdef ASSERT | |
| 204 ResourceMark rm; | |
| 205 CodeBuffer cb("test", 100, 100); | |
| 206 MacroAssembler* a = new MacroAssembler(&cb); | |
| 207 NativeCall *nc; | |
| 208 uint idx; | |
| 209 int offsets[] = { | |
| 210 0x0, | |
| 211 0xfffffff0, | |
| 212 0x7ffffff0, | |
| 213 0x80000000, | |
| 214 0x20, | |
| 215 0x4000, | |
| 216 }; | |
| 217 | |
| 218 VM_Version::allow_all(); | |
| 219 | |
| 220 a->call( a->pc(), relocInfo::none ); | |
| 221 a->delayed()->nop(); | |
| 1748 | 222 nc = nativeCall_at( cb.insts_begin() ); |
| 0 | 223 nc->print(); |
| 224 | |
| 225 nc = nativeCall_overwriting_at( nc->next_instruction_address() ); | |
| 226 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
| 1748 | 227 nc->set_destination( cb.insts_begin() + offsets[idx] ); |
| 228 assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test"); | |
| 0 | 229 nc->print(); |
| 230 } | |
| 231 | |
| 1748 | 232 nc = nativeCall_before( cb.insts_begin() + 8 ); |
| 0 | 233 nc->print(); |
| 234 | |
| 235 VM_Version::revert(); | |
| 236 #endif | |
| 237 } | |
| 238 // End code for unit testing implementation of NativeCall class | |
| 239 | |
| 240 //------------------------------------------------------------------- | |
| 241 | |
| 242 #ifdef _LP64 | |
| 243 | |
| 244 void NativeFarCall::set_destination(address dest) { | |
| 245 // Address materialized in the instruction stream, so nothing to do. | |
| 246 return; | |
| 247 #if 0 // What we'd do if we really did want to change the destination | |
| 248 if (destination() == dest) { | |
| 249 return; | |
| 250 } | |
| 251 ResourceMark rm; | |
| 252 CodeBuffer buf(addr_at(0), instruction_size + 1); | |
| 253 MacroAssembler* _masm = new MacroAssembler(&buf); | |
| 254 // Generate the new sequence | |
| 727 | 255 AddressLiteral(dest); |
| 256 _masm->jumpl_to(dest, O7, O7); | |
| 0 | 257 ICache::invalidate_range(addr_at(0), instruction_size ); |
| 258 #endif | |
| 259 } | |
| 260 | |
| 261 void NativeFarCall::verify() { | |
| 262 // make sure code pattern is actually a jumpl_to instruction | |
| 263 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to"); | |
| 264 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
| 265 nativeJump_at(addr_at(0))->verify(); | |
| 266 } | |
| 267 | |
| 268 bool NativeFarCall::is_call_at(address instr) { | |
| 269 return nativeInstruction_at(instr)->is_sethi(); | |
| 270 } | |
| 271 | |
| 272 void NativeFarCall::print() { | |
| 273 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); | |
| 274 } | |
| 275 | |
| 276 bool NativeFarCall::destination_is_compiled_verified_entry_point() { | |
| 277 nmethod* callee = CodeCache::find_nmethod(destination()); | |
| 278 if (callee == NULL) { | |
| 279 return false; | |
| 280 } else { | |
| 281 return destination() == callee->verified_entry_point(); | |
| 282 } | |
| 283 } | |
| 284 | |
| 285 // MT-safe patching of a far call. | |
| 286 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) { | |
| 287 Unimplemented(); | |
| 288 } | |
| 289 | |
| 290 // Code for unit testing implementation of NativeFarCall class | |
| 291 void NativeFarCall::test() { | |
| 292 Unimplemented(); | |
| 293 } | |
| 294 // End code for unit testing implementation of NativeFarCall class | |
| 295 | |
| 296 #endif // _LP64 | |
| 297 | |
| 298 //------------------------------------------------------------------- | |
| 299 | |
| 300 | |
| 301 void NativeMovConstReg::verify() { | |
| 302 NativeInstruction::verify(); | |
| 303 // make sure code pattern is actually a "set_oop" synthetic instruction | |
| 304 // see MacroAssembler::set_oop() | |
| 305 int i0 = long_at(sethi_offset); | |
| 306 int i1 = long_at(add_offset); | |
| 307 | |
| 308 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" | |
| 309 Register rd = inv_rd(i0); | |
| 310 #ifndef _LP64 | |
| 311 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && | |
| 312 is_op3(i1, Assembler::add_op3, Assembler::arith_op) && | |
| 313 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && | |
| 314 rd == inv_rs1(i1) && rd == inv_rd(i1))) { | |
| 315 fatal("not a set_oop"); | |
| 316 } | |
| 317 #else | |
| 318 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { | |
| 319 fatal("not a set_oop"); | |
| 320 } | |
| 321 #endif | |
| 322 } | |
| 323 | |
| 324 | |
| 325 void NativeMovConstReg::print() { | |
| 326 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); | |
| 327 } | |
| 328 | |
| 329 | |
| 330 #ifdef _LP64 | |
| 331 intptr_t NativeMovConstReg::data() const { | |
| 332 return data64(addr_at(sethi_offset), long_at(add_offset)); | |
| 333 } | |
| 334 #else | |
| 335 intptr_t NativeMovConstReg::data() const { | |
| 336 return data32(long_at(sethi_offset), long_at(add_offset)); | |
| 337 } | |
| 338 #endif | |
| 339 | |
| 340 | |
| 341 void NativeMovConstReg::set_data(intptr_t x) { | |
| 342 #ifdef _LP64 | |
| 343 set_data64_sethi(addr_at(sethi_offset), x); | |
| 344 #else | |
| 345 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); | |
| 346 #endif | |
| 347 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); | |
| 348 | |
| 349 // also store the value into an oop_Relocation cell, if any | |
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350 CodeBlob* cb = CodeCache::find_blob(instruction_address()); |
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351 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; |
| 0 | 352 if (nm != NULL) { |
| 353 RelocIterator iter(nm, instruction_address(), next_instruction_address()); | |
| 354 oop* oop_addr = NULL; | |
| 355 while (iter.next()) { | |
| 356 if (iter.type() == relocInfo::oop_type) { | |
| 357 oop_Relocation *r = iter.oop_reloc(); | |
| 358 if (oop_addr == NULL) { | |
| 359 oop_addr = r->oop_addr(); | |
| 360 *oop_addr = (oop)x; | |
| 361 } else { | |
| 362 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); | |
| 363 } | |
| 364 } | |
| 365 } | |
| 366 } | |
| 367 } | |
| 368 | |
| 369 | |
| 370 // Code for unit testing implementation of NativeMovConstReg class | |
| 371 void NativeMovConstReg::test() { | |
| 372 #ifdef ASSERT | |
| 373 ResourceMark rm; | |
| 374 CodeBuffer cb("test", 100, 100); | |
| 375 MacroAssembler* a = new MacroAssembler(&cb); | |
| 376 NativeMovConstReg* nm; | |
| 377 uint idx; | |
| 378 int offsets[] = { | |
| 379 0x0, | |
| 380 0x7fffffff, | |
| 381 0x80000000, | |
| 382 0xffffffff, | |
| 383 0x20, | |
| 384 4096, | |
| 385 4097, | |
| 386 }; | |
| 387 | |
| 388 VM_Version::allow_all(); | |
| 389 | |
| 727 | 390 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
| 391 a->sethi(al1, I3); | |
| 392 a->add(I3, al1.low10(), I3); | |
| 393 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); | |
| 394 a->sethi(al2, O2); | |
| 395 a->add(O2, al2.low10(), O2); | |
| 0 | 396 |
| 1748 | 397 nm = nativeMovConstReg_at( cb.insts_begin() ); |
| 0 | 398 nm->print(); |
| 399 | |
| 400 nm = nativeMovConstReg_at( nm->next_instruction_address() ); | |
| 401 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
| 402 nm->set_data( offsets[idx] ); | |
| 403 assert(nm->data() == offsets[idx], "check unit test"); | |
| 404 } | |
| 405 nm->print(); | |
| 406 | |
| 407 VM_Version::revert(); | |
| 408 #endif | |
| 409 } | |
| 410 // End code for unit testing implementation of NativeMovConstReg class | |
| 411 | |
| 412 //------------------------------------------------------------------- | |
| 413 | |
| 414 void NativeMovConstRegPatching::verify() { | |
| 415 NativeInstruction::verify(); | |
| 416 // Make sure code pattern is sethi/nop/add. | |
| 417 int i0 = long_at(sethi_offset); | |
| 418 int i1 = long_at(nop_offset); | |
| 419 int i2 = long_at(add_offset); | |
| 420 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
| 421 | |
| 422 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg" | |
| 423 // The casual reader should note that on Sparc a nop is a special case if sethi | |
| 424 // in which the destination register is %g0. | |
| 425 Register rd0 = inv_rd(i0); | |
| 426 Register rd1 = inv_rd(i1); | |
| 427 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 && | |
| 428 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi | |
| 429 is_op3(i2, Assembler::add_op3, Assembler::arith_op) && | |
| 430 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) && | |
| 431 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) { | |
| 432 fatal("not a set_oop"); | |
| 433 } | |
| 434 } | |
| 435 | |
| 436 | |
| 437 void NativeMovConstRegPatching::print() { | |
| 438 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); | |
| 439 } | |
| 440 | |
| 441 | |
| 442 int NativeMovConstRegPatching::data() const { | |
| 443 #ifdef _LP64 | |
| 444 return data64(addr_at(sethi_offset), long_at(add_offset)); | |
| 445 #else | |
| 446 return data32(long_at(sethi_offset), long_at(add_offset)); | |
| 447 #endif | |
| 448 } | |
| 449 | |
| 450 | |
| 451 void NativeMovConstRegPatching::set_data(int x) { | |
| 452 #ifdef _LP64 | |
| 453 set_data64_sethi(addr_at(sethi_offset), x); | |
| 454 #else | |
| 455 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x)); | |
| 456 #endif | |
| 457 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x)); | |
| 458 | |
| 459 // also store the value into an oop_Relocation cell, if any | |
|
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460 CodeBlob* cb = CodeCache::find_blob(instruction_address()); |
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461 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; |
| 0 | 462 if (nm != NULL) { |
| 463 RelocIterator iter(nm, instruction_address(), next_instruction_address()); | |
| 464 oop* oop_addr = NULL; | |
| 465 while (iter.next()) { | |
| 466 if (iter.type() == relocInfo::oop_type) { | |
| 467 oop_Relocation *r = iter.oop_reloc(); | |
| 468 if (oop_addr == NULL) { | |
| 469 oop_addr = r->oop_addr(); | |
| 470 *oop_addr = (oop)x; | |
| 471 } else { | |
| 472 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); | |
| 473 } | |
| 474 } | |
| 475 } | |
| 476 } | |
| 477 } | |
| 478 | |
| 479 | |
| 480 // Code for unit testing implementation of NativeMovConstRegPatching class | |
| 481 void NativeMovConstRegPatching::test() { | |
| 482 #ifdef ASSERT | |
| 483 ResourceMark rm; | |
| 484 CodeBuffer cb("test", 100, 100); | |
| 485 MacroAssembler* a = new MacroAssembler(&cb); | |
| 486 NativeMovConstRegPatching* nm; | |
| 487 uint idx; | |
| 488 int offsets[] = { | |
| 489 0x0, | |
| 490 0x7fffffff, | |
| 491 0x80000000, | |
| 492 0xffffffff, | |
| 493 0x20, | |
| 494 4096, | |
| 495 4097, | |
| 496 }; | |
| 497 | |
| 498 VM_Version::allow_all(); | |
| 499 | |
| 727 | 500 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
| 501 a->sethi(al1, I3); | |
| 0 | 502 a->nop(); |
| 727 | 503 a->add(I3, al1.low10(), I3); |
| 504 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); | |
| 505 a->sethi(al2, O2); | |
| 0 | 506 a->nop(); |
| 727 | 507 a->add(O2, al2.low10(), O2); |
| 0 | 508 |
| 1748 | 509 nm = nativeMovConstRegPatching_at( cb.insts_begin() ); |
| 0 | 510 nm->print(); |
| 511 | |
| 512 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() ); | |
| 513 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
| 514 nm->set_data( offsets[idx] ); | |
| 515 assert(nm->data() == offsets[idx], "check unit test"); | |
| 516 } | |
| 517 nm->print(); | |
| 518 | |
| 519 VM_Version::revert(); | |
| 520 #endif // ASSERT | |
| 521 } | |
| 522 // End code for unit testing implementation of NativeMovConstRegPatching class | |
| 523 | |
| 524 | |
| 525 //------------------------------------------------------------------- | |
| 526 | |
| 527 | |
| 528 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { | |
| 529 Untested("copy_instruction_to"); | |
| 530 int instruction_size = next_instruction_address() - instruction_address(); | |
| 531 for (int i = 0; i < instruction_size; i += BytesPerInstWord) { | |
| 532 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i); | |
| 533 } | |
| 534 } | |
| 535 | |
| 536 | |
| 537 void NativeMovRegMem::verify() { | |
| 538 NativeInstruction::verify(); | |
| 539 // make sure code pattern is actually a "ld" or "st" of some sort. | |
| 540 int i0 = long_at(0); | |
| 541 int op3 = inv_op3(i0); | |
| 542 | |
| 543 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok"); | |
| 544 | |
| 545 if (!(is_op(i0, Assembler::ldst_op) && | |
| 546 inv_immed(i0) && | |
| 547 0 != (op3 < op3_ldst_int_limit | |
| 548 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
| 549 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) | |
| 550 { | |
| 551 int i1 = long_at(ldst_offset); | |
| 552 Register rd = inv_rd(i0); | |
| 553 | |
| 554 op3 = inv_op3(i1); | |
| 555 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && | |
| 556 0 != (op3 < op3_ldst_int_limit | |
| 557 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
| 558 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { | |
| 559 fatal("not a ld* or st* op"); | |
| 560 } | |
| 561 } | |
| 562 } | |
| 563 | |
| 564 | |
| 565 void NativeMovRegMem::print() { | |
| 566 if (is_immediate()) { | |
| 567 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); | |
| 568 } else { | |
| 569 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); | |
| 570 } | |
| 571 } | |
| 572 | |
| 573 | |
| 574 // Code for unit testing implementation of NativeMovRegMem class | |
| 575 void NativeMovRegMem::test() { | |
| 576 #ifdef ASSERT | |
| 577 ResourceMark rm; | |
| 578 CodeBuffer cb("test", 1000, 1000); | |
| 579 MacroAssembler* a = new MacroAssembler(&cb); | |
| 580 NativeMovRegMem* nm; | |
| 581 uint idx = 0; | |
| 582 uint idx1; | |
| 583 int offsets[] = { | |
| 584 0x0, | |
| 585 0xffffffff, | |
| 586 0x7fffffff, | |
| 587 0x80000000, | |
| 588 4096, | |
| 589 4097, | |
| 590 0x20, | |
| 591 0x4000, | |
| 592 }; | |
| 593 | |
| 594 VM_Version::allow_all(); | |
| 595 | |
| 727 | 596 AddressLiteral al1(0xffffffff, relocInfo::external_word_type); |
| 597 AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type); | |
| 598 a->ldsw( G5, al1.low10(), G4 ); idx++; | |
| 599 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 600 a->ldsw( G5, I3, G4 ); idx++; |
| 727 | 601 a->ldsb( G5, al1.low10(), G4 ); idx++; |
| 602 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 603 a->ldsb( G5, I3, G4 ); idx++; |
| 727 | 604 a->ldsh( G5, al1.low10(), G4 ); idx++; |
| 605 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 606 a->ldsh( G5, I3, G4 ); idx++; |
| 727 | 607 a->lduw( G5, al1.low10(), G4 ); idx++; |
| 608 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 609 a->lduw( G5, I3, G4 ); idx++; |
| 727 | 610 a->ldub( G5, al1.low10(), G4 ); idx++; |
| 611 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 612 a->ldub( G5, I3, G4 ); idx++; |
| 727 | 613 a->lduh( G5, al1.low10(), G4 ); idx++; |
| 614 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 615 a->lduh( G5, I3, G4 ); idx++; |
| 727 | 616 a->ldx( G5, al1.low10(), G4 ); idx++; |
| 617 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 618 a->ldx( G5, I3, G4 ); idx++; |
| 727 | 619 a->ldd( G5, al1.low10(), G4 ); idx++; |
| 620 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 621 a->ldd( G5, I3, G4 ); idx++; |
| 622 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; | |
| 727 | 623 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
| 0 | 624 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; |
| 625 | |
| 727 | 626 a->stw( G5, G4, al1.low10() ); idx++; |
| 627 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 628 a->stw( G5, G4, I3 ); idx++; |
| 727 | 629 a->stb( G5, G4, al1.low10() ); idx++; |
| 630 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 631 a->stb( G5, G4, I3 ); idx++; |
| 727 | 632 a->sth( G5, G4, al1.low10() ); idx++; |
| 633 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 634 a->sth( G5, G4, I3 ); idx++; |
| 727 | 635 a->stx( G5, G4, al1.low10() ); idx++; |
| 636 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 637 a->stx( G5, G4, I3 ); idx++; |
| 727 | 638 a->std( G5, G4, al1.low10() ); idx++; |
| 639 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
| 0 | 640 a->std( G5, G4, I3 ); idx++; |
| 641 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; | |
| 727 | 642 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
| 0 | 643 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
| 644 | |
| 1748 | 645 nm = nativeMovRegMem_at( cb.insts_begin() ); |
| 0 | 646 nm->print(); |
| 647 nm->set_offset( low10(0) ); | |
| 648 nm->print(); | |
| 649 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
| 650 nm->print(); | |
| 651 | |
| 652 while (--idx) { | |
| 653 nm = nativeMovRegMem_at( nm->next_instruction_address() ); | |
| 654 nm->print(); | |
| 655 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { | |
| 656 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); | |
| 657 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), | |
| 658 "check unit test"); | |
| 659 nm->print(); | |
| 660 } | |
| 661 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
| 662 nm->print(); | |
| 663 } | |
| 664 | |
| 665 VM_Version::revert(); | |
| 666 #endif // ASSERT | |
| 667 } | |
| 668 | |
| 669 // End code for unit testing implementation of NativeMovRegMem class | |
| 670 | |
| 671 //-------------------------------------------------------------------------------- | |
| 672 | |
| 673 | |
| 674 void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) { | |
| 675 Untested("copy_instruction_to"); | |
| 676 int instruction_size = next_instruction_address() - instruction_address(); | |
| 677 for (int i = 0; i < instruction_size; i += wordSize) { | |
| 678 *(long*)(new_instruction_address + i) = *(long*)(address(this) + i); | |
| 679 } | |
| 680 } | |
| 681 | |
| 682 | |
| 683 void NativeMovRegMemPatching::verify() { | |
| 684 NativeInstruction::verify(); | |
| 685 // make sure code pattern is actually a "ld" or "st" of some sort. | |
| 686 int i0 = long_at(0); | |
| 687 int op3 = inv_op3(i0); | |
| 688 | |
| 689 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
| 690 | |
| 691 if (!(is_op(i0, Assembler::ldst_op) && | |
| 692 inv_immed(i0) && | |
| 693 0 != (op3 < op3_ldst_int_limit | |
| 694 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
| 695 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) { | |
| 696 int i1 = long_at(ldst_offset); | |
| 697 Register rd = inv_rd(i0); | |
| 698 | |
| 699 op3 = inv_op3(i1); | |
| 700 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && | |
| 701 0 != (op3 < op3_ldst_int_limit | |
| 702 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
| 703 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { | |
| 704 fatal("not a ld* or st* op"); | |
| 705 } | |
| 706 } | |
| 707 } | |
| 708 | |
| 709 | |
| 710 void NativeMovRegMemPatching::print() { | |
| 711 if (is_immediate()) { | |
| 712 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); | |
| 713 } else { | |
| 714 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); | |
| 715 } | |
| 716 } | |
| 717 | |
| 718 | |
| 719 // Code for unit testing implementation of NativeMovRegMemPatching class | |
| 720 void NativeMovRegMemPatching::test() { | |
| 721 #ifdef ASSERT | |
| 722 ResourceMark rm; | |
| 723 CodeBuffer cb("test", 1000, 1000); | |
| 724 MacroAssembler* a = new MacroAssembler(&cb); | |
| 725 NativeMovRegMemPatching* nm; | |
| 726 uint idx = 0; | |
| 727 uint idx1; | |
| 728 int offsets[] = { | |
| 729 0x0, | |
| 730 0xffffffff, | |
| 731 0x7fffffff, | |
| 732 0x80000000, | |
| 733 4096, | |
| 734 4097, | |
| 735 0x20, | |
| 736 0x4000, | |
| 737 }; | |
| 738 | |
| 739 VM_Version::allow_all(); | |
| 740 | |
| 727 | 741 AddressLiteral al(0xffffffff, relocInfo::external_word_type); |
| 742 a->ldsw( G5, al.low10(), G4); idx++; | |
| 743 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 744 a->ldsw( G5, I3, G4 ); idx++; |
| 727 | 745 a->ldsb( G5, al.low10(), G4); idx++; |
| 746 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 747 a->ldsb( G5, I3, G4 ); idx++; |
| 727 | 748 a->ldsh( G5, al.low10(), G4); idx++; |
| 749 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 750 a->ldsh( G5, I3, G4 ); idx++; |
| 727 | 751 a->lduw( G5, al.low10(), G4); idx++; |
| 752 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 753 a->lduw( G5, I3, G4 ); idx++; |
| 727 | 754 a->ldub( G5, al.low10(), G4); idx++; |
| 755 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 756 a->ldub( G5, I3, G4 ); idx++; |
| 727 | 757 a->lduh( G5, al.low10(), G4); idx++; |
| 758 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 759 a->lduh( G5, I3, G4 ); idx++; |
| 727 | 760 a->ldx( G5, al.low10(), G4); idx++; |
| 761 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 762 a->ldx( G5, I3, G4 ); idx++; | |
| 763 a->ldd( G5, al.low10(), G4); idx++; | |
| 764 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 765 a->ldd( G5, I3, G4 ); idx++; | |
| 766 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; | |
| 767 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 768 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; | |
| 0 | 769 |
| 727 | 770 a->stw( G5, G4, al.low10()); idx++; |
| 771 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 772 a->stw( G5, G4, I3 ); idx++; |
| 727 | 773 a->stb( G5, G4, al.low10()); idx++; |
| 774 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 775 a->stb( G5, G4, I3 ); idx++; |
| 727 | 776 a->sth( G5, G4, al.low10()); idx++; |
| 777 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 778 a->sth( G5, G4, I3 ); idx++; |
| 727 | 779 a->stx( G5, G4, al.low10()); idx++; |
| 780 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 781 a->stx( G5, G4, I3 ); idx++; |
| 727 | 782 a->std( G5, G4, al.low10()); idx++; |
| 783 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
| 0 | 784 a->std( G5, G4, I3 ); idx++; |
| 785 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; | |
| 727 | 786 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
| 0 | 787 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
| 788 | |
| 1748 | 789 nm = nativeMovRegMemPatching_at( cb.insts_begin() ); |
| 0 | 790 nm->print(); |
| 791 nm->set_offset( low10(0) ); | |
| 792 nm->print(); | |
| 793 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
| 794 nm->print(); | |
| 795 | |
| 796 while (--idx) { | |
| 797 nm = nativeMovRegMemPatching_at( nm->next_instruction_address() ); | |
| 798 nm->print(); | |
| 799 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { | |
| 800 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); | |
| 801 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), | |
| 802 "check unit test"); | |
| 803 nm->print(); | |
| 804 } | |
| 805 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
| 806 nm->print(); | |
| 807 } | |
| 808 | |
| 809 VM_Version::revert(); | |
| 810 #endif // ASSERT | |
| 811 } | |
| 812 // End code for unit testing implementation of NativeMovRegMemPatching class | |
| 813 | |
| 814 | |
| 815 //-------------------------------------------------------------------------------- | |
| 816 | |
| 817 | |
| 818 void NativeJump::verify() { | |
| 819 NativeInstruction::verify(); | |
| 820 int i0 = long_at(sethi_offset); | |
| 821 int i1 = long_at(jmpl_offset); | |
| 822 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
| 823 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg" | |
| 824 Register rd = inv_rd(i0); | |
| 825 #ifndef _LP64 | |
| 826 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && | |
| 827 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) || | |
| 828 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) && | |
| 829 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && | |
| 830 rd == inv_rs1(i1))) { | |
| 831 fatal("not a jump_to instruction"); | |
| 832 } | |
| 833 #else | |
| 834 // In LP64, the jump instruction location varies for non relocatable | |
| 835 // jumps, for example is could be sethi, xor, jmp instead of the | |
| 836 // 7 instructions for sethi. So let's check sethi only. | |
| 837 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { | |
| 838 fatal("not a jump_to instruction"); | |
| 839 } | |
| 840 #endif | |
| 841 } | |
| 842 | |
| 843 | |
| 844 void NativeJump::print() { | |
| 845 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination()); | |
| 846 } | |
| 847 | |
| 848 | |
| 849 // Code for unit testing implementation of NativeJump class | |
| 850 void NativeJump::test() { | |
| 851 #ifdef ASSERT | |
| 852 ResourceMark rm; | |
| 853 CodeBuffer cb("test", 100, 100); | |
| 854 MacroAssembler* a = new MacroAssembler(&cb); | |
| 855 NativeJump* nj; | |
| 856 uint idx; | |
| 857 int offsets[] = { | |
| 858 0x0, | |
| 859 0xffffffff, | |
| 860 0x7fffffff, | |
| 861 0x80000000, | |
| 862 4096, | |
| 863 4097, | |
| 864 0x20, | |
| 865 0x4000, | |
| 866 }; | |
| 867 | |
| 868 VM_Version::allow_all(); | |
| 869 | |
| 727 | 870 AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type); |
| 871 a->sethi(al, I3); | |
| 872 a->jmpl(I3, al.low10(), G0, RelocationHolder::none); | |
| 0 | 873 a->delayed()->nop(); |
| 727 | 874 a->sethi(al, I3); |
| 875 a->jmpl(I3, al.low10(), L3, RelocationHolder::none); | |
| 0 | 876 a->delayed()->nop(); |
| 877 | |
| 1748 | 878 nj = nativeJump_at( cb.insts_begin() ); |
| 0 | 879 nj->print(); |
| 880 | |
| 881 nj = nativeJump_at( nj->next_instruction_address() ); | |
| 882 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
| 883 nj->set_jump_destination( nj->instruction_address() + offsets[idx] ); | |
| 884 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test"); | |
| 885 nj->print(); | |
| 886 } | |
| 887 | |
| 888 VM_Version::revert(); | |
| 889 #endif // ASSERT | |
| 890 } | |
| 891 // End code for unit testing implementation of NativeJump class | |
| 892 | |
| 893 | |
| 894 void NativeJump::insert(address code_pos, address entry) { | |
| 895 Unimplemented(); | |
| 896 } | |
| 897 | |
| 898 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) | |
| 899 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot). | |
| 900 // Atomic write can be only with 1 word. | |
| 901 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { | |
| 902 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere | |
| 903 // in the header of the nmethod, within a short branch's span of the patch point. | |
| 904 // Set up the jump sequence using NativeJump::insert, and then use an annulled | |
| 905 // unconditional branch at the target site (an atomic 1-word update). | |
| 906 // Limitations: You can only patch nmethods, with any given nmethod patched at | |
| 907 // most once, and the patch must be in the nmethod's header. | |
| 908 // It's messy, but you can ask the CodeCache for the nmethod containing the | |
| 909 // target address. | |
| 910 | |
| 911 // %%%%% For now, do something MT-stupid: | |
| 912 ResourceMark rm; | |
| 913 int code_size = 1 * BytesPerInstWord; | |
| 914 CodeBuffer cb(verified_entry, code_size + 1); | |
| 915 MacroAssembler* a = new MacroAssembler(&cb); | |
| 916 if (VM_Version::v9_instructions_work()) { | |
| 917 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler | |
| 918 } else { | |
| 919 a->lduw(G0, 0, O7); // "ld" must agree with code in the signal handler | |
| 920 } | |
| 921 ICache::invalidate_range(verified_entry, code_size); | |
| 922 } | |
| 923 | |
| 924 | |
| 925 void NativeIllegalInstruction::insert(address code_pos) { | |
| 926 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos); | |
| 927 nii->set_long_at(0, illegal_instruction()); | |
| 928 } | |
| 929 | |
| 930 static int illegal_instruction_bits = 0; | |
| 931 | |
| 932 int NativeInstruction::illegal_instruction() { | |
| 933 if (illegal_instruction_bits == 0) { | |
| 934 ResourceMark rm; | |
| 935 char buf[40]; | |
| 936 CodeBuffer cbuf((address)&buf[0], 20); | |
| 937 MacroAssembler* a = new MacroAssembler(&cbuf); | |
| 938 address ia = a->pc(); | |
| 939 a->trap(ST_RESERVED_FOR_USER_0 + 1); | |
| 940 int bits = *(int*)ia; | |
| 941 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); | |
| 942 illegal_instruction_bits = bits; | |
| 943 assert(illegal_instruction_bits != 0, "oops"); | |
| 944 } | |
| 945 return illegal_instruction_bits; | |
| 946 } | |
| 947 | |
| 948 static int ic_miss_trap_bits = 0; | |
| 949 | |
| 950 bool NativeInstruction::is_ic_miss_trap() { | |
| 951 if (ic_miss_trap_bits == 0) { | |
| 952 ResourceMark rm; | |
| 953 char buf[40]; | |
| 954 CodeBuffer cbuf((address)&buf[0], 20); | |
| 955 MacroAssembler* a = new MacroAssembler(&cbuf); | |
| 956 address ia = a->pc(); | |
| 957 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2); | |
| 958 int bits = *(int*)ia; | |
| 959 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); | |
| 960 ic_miss_trap_bits = bits; | |
| 961 assert(ic_miss_trap_bits != 0, "oops"); | |
| 962 } | |
| 963 return long_at(0) == ic_miss_trap_bits; | |
| 964 } | |
| 965 | |
| 966 | |
| 967 bool NativeInstruction::is_illegal() { | |
| 968 if (illegal_instruction_bits == 0) { | |
| 969 return false; | |
| 970 } | |
| 971 return long_at(0) == illegal_instruction_bits; | |
| 972 } | |
| 973 | |
| 974 | |
| 975 void NativeGeneralJump::verify() { | |
| 976 assert(((NativeInstruction *)this)->is_jump() || | |
| 977 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); | |
| 978 } | |
| 979 | |
| 980 | |
| 981 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { | |
| 982 Assembler::Condition condition = Assembler::always; | |
| 983 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) | | |
| 984 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22); | |
| 985 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos); | |
| 986 ni->set_long_at(0, x); | |
| 987 } | |
| 988 | |
| 989 | |
| 990 // MT-safe patching of a jmp instruction (and following word). | |
| 991 // First patches the second word, and then atomicly replaces | |
| 992 // the first word with the first new instruction word. | |
| 993 // Other processors might briefly see the old first word | |
| 994 // followed by the new second word. This is OK if the old | |
| 995 // second word is harmless, and the new second word may be | |
| 996 // harmlessly executed in the delay slot of the call. | |
| 997 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { | |
| 998 assert(Patching_lock->is_locked() || | |
| 999 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
| 1000 assert (instr_addr != NULL, "illegal address for code patching"); | |
| 1001 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call | |
| 1002 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8"); | |
| 1003 int i0 = ((int*)code_buffer)[0]; | |
| 1004 int i1 = ((int*)code_buffer)[1]; | |
| 1005 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord); | |
| 1006 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
| 1007 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), | |
| 1008 "must not interfere with original call"); | |
| 1009 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order | |
| 1010 h_jump->set_long_at(1*BytesPerInstWord, i1); | |
| 1011 h_jump->set_long_at(0*BytesPerInstWord, i0); | |
| 1012 // NOTE: It is possible that another thread T will execute | |
| 1013 // only the second patched word. | |
| 1014 // In other words, since the original instruction is this | |
| 1015 // jmp patching_stub; nop (NativeGeneralJump) | |
| 1016 // and the new sequence from the buffer is this: | |
| 1017 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) | |
| 1018 // what T will execute is this: | |
| 1019 // jmp patching_stub; add %r, %lo(K), %r | |
| 1020 // thereby putting garbage into %r before calling the patching stub. | |
| 1021 // This is OK, because the patching stub ignores the value of %r. | |
| 1022 | |
| 1023 // Make sure the first-patched instruction, which may co-exist | |
| 1024 // briefly with the call, will do something harmless. | |
| 1025 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
| 1026 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(), | |
| 1027 "must not interfere with original call"); | |
| 1028 } |