Mercurial > hg > truffle
annotate graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64Arithmetic.java @ 4323:df5547057954
Remove LIROpcode and use non-anonymous subclasses of LIRInstruction
author | Christian Wimmer <Christian.Wimmer@Oracle.com> |
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date | Wed, 25 Jan 2012 14:34:53 -0800 |
parents | graal/com.oracle.max.graal.compiler/src/com/oracle/max/graal/compiler/target/amd64/AMD64ArithmeticOpcode.java@1cf920630944 |
children | 0d122ed933b6 |
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1 /* |
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2 * Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.oracle.max.graal.compiler.target.amd64; |
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24 |
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25 import static com.oracle.max.cri.ci.CiValueUtil.*; |
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26 |
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27 import java.util.*; |
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28 |
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29 import com.oracle.max.asm.*; |
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30 import com.oracle.max.asm.target.amd64.*; |
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31 import com.oracle.max.asm.target.amd64.AMD64Assembler.ConditionFlag; |
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32 import com.oracle.max.cri.ci.*; |
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33 import com.oracle.max.graal.compiler.asm.*; |
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34 import com.oracle.max.graal.compiler.lir.*; |
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35 import com.oracle.max.graal.compiler.util.*; |
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36 |
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37 public enum AMD64Arithmetic { |
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38 IADD, ISUB, IMUL, IDIV, IREM, IUDIV, IUREM, IAND, IOR, IXOR, ISHL, ISHR, IUSHR, |
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39 LADD, LSUB, LMUL, LDIV, LREM, LUDIV, LUREM, LAND, LOR, LXOR, LSHL, LSHR, LUSHR, |
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40 FADD, FSUB, FMUL, FDIV, FAND, FOR, FXOR, |
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41 DADD, DSUB, DMUL, DDIV, DAND, DOR, DXOR, |
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42 INEG, LNEG, |
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43 I2L, L2I, I2B, I2C, I2S, |
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44 F2D, D2F, |
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45 I2F, I2D, F2I, D2I, |
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46 L2F, L2D, F2L, D2L, |
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47 MOV_I2F, MOV_L2D, MOV_F2I, MOV_D2L; |
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48 |
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49 |
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50 public static class Op1Reg extends AMD64LIRInstruction { |
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51 public Op1Reg(AMD64Arithmetic opcode, CiValue result, CiValue x) { |
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52 super(opcode, new CiValue[] {result}, null, new CiValue[] {x}, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS); |
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53 } |
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54 |
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55 @Override |
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56 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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57 CiValue result = output(0); |
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58 CiValue x = input(0); |
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59 |
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60 emit(tasm, masm, (AMD64Arithmetic) code, result, x, null); |
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61 } |
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62 |
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63 @Override |
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64 protected EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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65 if (mode == OperandMode.Input && index == 0) { |
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66 return EnumSet.of(OperandFlag.Register); |
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67 } else if (mode == OperandMode.Output && index == 0) { |
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68 return EnumSet.of(OperandFlag.Register); |
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69 } |
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70 throw Util.shouldNotReachHere(); |
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71 } |
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72 } |
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73 |
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74 public static class Op1Stack extends AMD64LIRInstruction { |
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75 public Op1Stack(AMD64Arithmetic opcode, CiValue result, CiValue x) { |
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76 super(opcode, new CiValue[] {result}, null, new CiValue[] {x}, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS); |
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77 } |
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78 |
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79 @Override |
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80 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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81 CiValue result = output(0); |
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82 CiValue x = input(0); |
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83 |
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84 AMD64Move.move(tasm, masm, result, x); |
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85 emit(tasm, masm, (AMD64Arithmetic) code, result); |
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86 } |
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87 |
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88 @Override |
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89 public EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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90 if (mode == OperandMode.Input && index == 0) { |
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91 return EnumSet.of(OperandFlag.Register, OperandFlag.Stack, OperandFlag.Constant); |
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92 } else if (mode == OperandMode.Output && index == 0) { |
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93 return EnumSet.of(OperandFlag.Register, OperandFlag.RegisterHint); |
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94 } |
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95 throw Util.shouldNotReachHere(); |
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96 } |
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97 } |
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98 |
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99 public static class Op2Stack extends AMD64LIRInstruction { |
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100 public Op2Stack(AMD64Arithmetic opcode, CiValue result, CiValue x, CiValue y) { |
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101 super(opcode, new CiValue[] {result}, null, new CiValue[] {x}, new CiValue[] {y}, LIRInstruction.NO_OPERANDS); |
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102 } |
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103 |
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104 @Override |
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105 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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106 CiValue result = output(0); |
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107 CiValue x = input(0); |
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108 CiValue y = alive(0); |
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109 |
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110 AMD64Move.move(tasm, masm, result, x); |
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111 emit(tasm, masm, (AMD64Arithmetic) code, result, y, null); |
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112 } |
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113 |
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114 @Override |
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115 protected EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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116 if (mode == OperandMode.Input && index == 0) { |
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117 return EnumSet.of(OperandFlag.Register, OperandFlag.Stack, OperandFlag.Constant); |
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118 } else if (mode == OperandMode.Alive && index == 0) { |
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119 return EnumSet.of(OperandFlag.Register, OperandFlag.Stack, OperandFlag.Constant); |
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120 } else if (mode == OperandMode.Output && index == 0) { |
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121 return EnumSet.of(OperandFlag.Register, OperandFlag.RegisterHint); |
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122 } |
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123 throw Util.shouldNotReachHere(); |
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124 } |
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125 |
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126 @Override |
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127 public void verify() { |
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128 CiValue result = output(0); |
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129 CiValue x = input(0); |
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130 CiValue y = alive(0); |
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131 |
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132 super.verify(); |
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133 assert differentRegisters(result, y) || sameRegister(x, y); |
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134 verifyKind((AMD64Arithmetic) code, result, x, y); |
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135 } |
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136 } |
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137 |
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138 public static class Op2RegCommutative extends AMD64LIRInstruction { |
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139 public Op2RegCommutative(AMD64Arithmetic opcode, CiValue result, CiValue x, CiValue y) { |
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140 super(opcode, new CiValue[] {result}, null, new CiValue[] {x, y}, LIRInstruction.NO_OPERANDS, LIRInstruction.NO_OPERANDS); |
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141 } |
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142 |
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143 @Override |
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144 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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145 CiValue result = output(0); |
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146 CiValue x = input(0); |
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147 CiValue y = input(1); |
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148 |
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149 if (sameRegister(result, y)) { |
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150 emit(tasm, masm, (AMD64Arithmetic) code, result, x, null); |
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151 } else { |
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152 AMD64Move.move(tasm, masm, result, x); |
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153 emit(tasm, masm, (AMD64Arithmetic) code, result, y, null); |
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154 } |
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155 } |
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156 |
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157 @Override |
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158 public EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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159 if (mode == OperandMode.Input && index == 0) { |
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160 return EnumSet.of(OperandFlag.Register, OperandFlag.Stack, OperandFlag.Constant); |
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161 } else if (mode == OperandMode.Input && index == 1) { |
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162 return EnumSet.of(OperandFlag.Register, OperandFlag.Constant); |
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163 } else if (mode == OperandMode.Output && index == 0) { |
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164 return EnumSet.of(OperandFlag.Register, OperandFlag.RegisterHint); |
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165 } |
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166 throw Util.shouldNotReachHere(); |
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167 } |
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168 |
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169 @Override |
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170 protected void verify() { |
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171 CiValue result = output(0); |
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172 CiValue x = input(0); |
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173 CiValue y = input(1); |
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174 |
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175 super.verify(); |
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176 assert differentRegisters(result, y) || sameRegister(x, y); |
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177 verifyKind((AMD64Arithmetic) code, result, x, y); |
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178 } |
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179 } |
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180 |
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181 public static class ShiftOp extends AMD64LIRInstruction { |
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182 public ShiftOp(AMD64Arithmetic opcode, CiValue result, CiValue x, CiValue y) { |
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183 super(opcode, new CiValue[] {result}, null, new CiValue[] {x}, new CiValue[] {y}, LIRInstruction.NO_OPERANDS); |
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184 } |
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185 |
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186 @Override |
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187 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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188 CiValue result = output(0); |
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189 CiValue x = input(0); |
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190 CiValue y = alive(0); |
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191 |
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192 AMD64Move.move(tasm, masm, result, x); |
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193 emit(tasm, masm, (AMD64Arithmetic) code, result, y, null); |
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194 } |
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195 |
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196 @Override |
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197 public EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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198 if (mode == OperandMode.Input && index == 0) { |
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199 return EnumSet.of(OperandFlag.Register, OperandFlag.Stack, OperandFlag.Constant); |
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200 } else if (mode == OperandMode.Alive && index == 0) { |
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201 return EnumSet.of(OperandFlag.Register, OperandFlag.Constant); |
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202 } else if (mode == OperandMode.Output && index == 0) { |
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203 return EnumSet.of(OperandFlag.Register, OperandFlag.RegisterHint); |
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204 } |
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205 throw Util.shouldNotReachHere(); |
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206 } |
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207 |
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208 @Override |
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209 public void verify() { |
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210 CiValue result = output(0); |
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211 CiValue x = input(0); |
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212 CiValue y = alive(0); |
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213 |
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214 super.verify(); |
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215 assert isConstant(y) || asRegister(y) == AMD64.rcx; |
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216 assert differentRegisters(result, y) || sameRegister(x, y); |
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217 verifyKind((AMD64Arithmetic) code, result, x, x); |
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218 assert y.kind.stackKind() == CiKind.Int; |
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219 } |
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220 } |
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221 |
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222 public static class DivOp extends AMD64LIRInstruction { |
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223 public DivOp(AMD64Arithmetic opcode, CiValue result, CiValue x, CiValue y, LIRDebugInfo info) { |
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224 super(opcode, new CiValue[] {result}, info, new CiValue[] {x}, new CiValue[] {y}, new CiValue[] {asRegister(result) == AMD64.rax ? AMD64.rdx.asValue(result.kind) : AMD64.rax.asValue(result.kind)}); |
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225 } |
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226 |
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227 @Override |
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228 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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229 CiValue result = output(0); |
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230 CiValue y = alive(0); |
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231 |
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232 emit(tasm, masm, (AMD64Arithmetic) code, result, y, info); |
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233 } |
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234 |
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235 @Override |
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236 public EnumSet<OperandFlag> flagsFor(OperandMode mode, int index) { |
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237 if (mode == OperandMode.Input && index == 0) { |
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238 return EnumSet.of(OperandFlag.Register); |
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239 } else if (mode == OperandMode.Alive && index == 0) { |
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240 return EnumSet.of(OperandFlag.Register); |
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241 } else if (mode == OperandMode.Temp && index == 0) { |
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242 return EnumSet.of(OperandFlag.Register); |
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243 } else if (mode == OperandMode.Output && index == 0) { |
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244 return EnumSet.of(OperandFlag.Register); |
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245 } |
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246 throw Util.shouldNotReachHere(); |
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247 } |
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248 |
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249 @Override |
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250 protected void verify() { |
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251 CiValue result = output(0); |
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252 CiValue x = input(0); |
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253 CiValue y = alive(0); |
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254 |
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255 super.verify(); |
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256 // left input in rax, right input in any register but rax and rdx, result quotient in rax, result remainder in rdx |
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257 assert asRegister(x) == AMD64.rax; |
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258 assert differentRegisters(y, AMD64.rax.asValue(), AMD64.rdx.asValue()); |
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259 assert (name().endsWith("DIV") && asRegister(result) == AMD64.rax) || (name().endsWith("REM") && asRegister(result) == AMD64.rdx); |
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260 verifyKind((AMD64Arithmetic) code, result, x, y); |
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261 } |
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262 } |
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263 |
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264 |
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265 @SuppressWarnings("unused") |
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266 protected static void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AMD64Arithmetic opcode, CiValue result) { |
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267 switch (opcode) { |
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268 case INEG: masm.negl(asIntReg(result)); break; |
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269 case LNEG: masm.negq(asLongReg(result)); break; |
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270 case L2I: masm.andl(asIntReg(result), 0xFFFFFFFF); break; |
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271 case I2B: masm.signExtendByte(asIntReg(result)); break; |
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272 case I2C: masm.andl(asIntReg(result), 0xFFFF); break; |
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273 case I2S: masm.signExtendShort(asIntReg(result)); break; |
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274 default: throw Util.shouldNotReachHere(); |
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275 } |
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276 } |
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277 |
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278 protected static void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AMD64Arithmetic opcode, CiValue dst, CiValue src, LIRDebugInfo info) { |
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279 int exceptionOffset = -1; |
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280 if (isRegister(src)) { |
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281 switch (opcode) { |
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282 case IADD: masm.addl(asIntReg(dst), asIntReg(src)); break; |
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283 case ISUB: masm.subl(asIntReg(dst), asIntReg(src)); break; |
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284 case IAND: masm.andl(asIntReg(dst), asIntReg(src)); break; |
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285 case IMUL: masm.imull(asIntReg(dst), asIntReg(src)); break; |
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286 case IOR: masm.orl(asIntReg(dst), asIntReg(src)); break; |
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287 case IXOR: masm.xorl(asIntReg(dst), asIntReg(src)); break; |
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288 case ISHL: masm.shll(asIntReg(dst)); break; |
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289 case ISHR: masm.sarl(asIntReg(dst)); break; |
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290 case IUSHR:masm.shrl(asIntReg(dst)); break; |
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291 |
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292 case LADD: masm.addq(asLongReg(dst), asLongReg(src)); break; |
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293 case LSUB: masm.subq(asLongReg(dst), asLongReg(src)); break; |
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294 case LMUL: masm.imulq(asLongReg(dst), asLongReg(src)); break; |
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295 case LAND: masm.andq(asLongReg(dst), asLongReg(src)); break; |
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296 case LOR: masm.orq(asLongReg(dst), asLongReg(src)); break; |
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297 case LXOR: masm.xorq(asLongReg(dst), asLongReg(src)); break; |
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298 case LSHL: masm.shlq(asLongReg(dst)); break; |
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299 case LSHR: masm.sarq(asLongReg(dst)); break; |
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300 case LUSHR:masm.shrq(asLongReg(dst)); break; |
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301 |
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302 case FADD: masm.addss(asFloatReg(dst), asFloatReg(src)); break; |
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303 case FSUB: masm.subss(asFloatReg(dst), asFloatReg(src)); break; |
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304 case FMUL: masm.mulss(asFloatReg(dst), asFloatReg(src)); break; |
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305 case FDIV: masm.divss(asFloatReg(dst), asFloatReg(src)); break; |
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306 case FAND: masm.andps(asFloatReg(dst), asFloatReg(src)); break; |
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307 case FOR: masm.orps(asFloatReg(dst), asFloatReg(src)); break; |
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308 case FXOR: masm.xorps(asFloatReg(dst), asFloatReg(src)); break; |
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309 |
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310 case DADD: masm.addsd(asDoubleReg(dst), asDoubleReg(src)); break; |
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311 case DSUB: masm.subsd(asDoubleReg(dst), asDoubleReg(src)); break; |
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312 case DMUL: masm.mulsd(asDoubleReg(dst), asDoubleReg(src)); break; |
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313 case DDIV: masm.divsd(asDoubleReg(dst), asDoubleReg(src)); break; |
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314 case DAND: masm.andpd(asDoubleReg(dst), asDoubleReg(src)); break; |
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315 case DOR: masm.orpd(asDoubleReg(dst), asDoubleReg(src)); break; |
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316 case DXOR: masm.xorpd(asDoubleReg(dst), asDoubleReg(src)); break; |
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317 |
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318 case I2L: masm.movslq(asLongReg(dst), asIntReg(src)); break; |
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319 case F2D: masm.cvtss2sd(asDoubleReg(dst), asFloatReg(src)); break; |
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320 case D2F: masm.cvtsd2ss(asFloatReg(dst), asDoubleReg(src)); break; |
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321 case I2F: masm.cvtsi2ssl(asFloatReg(dst), asIntReg(src)); break; |
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322 case I2D: masm.cvtsi2sdl(asDoubleReg(dst), asIntReg(src)); break; |
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323 case L2F: masm.cvtsi2ssq(asFloatReg(dst), asLongReg(src)); break; |
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324 case L2D: masm.cvtsi2sdq(asDoubleReg(dst), asLongReg(src)); break; |
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325 case F2I: |
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326 masm.cvttss2sil(asIntReg(dst), asFloatReg(src)); |
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327 emitConvertFixup(tasm, masm, dst, src); |
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328 break; |
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329 case D2I: |
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330 masm.cvttsd2sil(asIntReg(dst), asDoubleReg(src)); |
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331 emitConvertFixup(tasm, masm, dst, src); |
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332 break; |
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333 case F2L: |
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334 masm.cvttss2siq(asLongReg(dst), asFloatReg(src)); |
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335 emitConvertFixup(tasm, masm, dst, src); |
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336 break; |
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337 case D2L: |
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338 masm.cvttsd2siq(asLongReg(dst), asDoubleReg(src)); |
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339 emitConvertFixup(tasm, masm, dst, src); |
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340 break; |
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341 case MOV_I2F: masm.movdl(asFloatReg(dst), asIntReg(src)); break; |
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342 case MOV_L2D: masm.movdq(asDoubleReg(dst), asLongReg(src)); break; |
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343 case MOV_F2I: masm.movdl(asIntReg(dst), asFloatReg(src)); break; |
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344 case MOV_D2L: masm.movdq(asLongReg(dst), asDoubleReg(src)); break; |
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345 |
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346 case IDIV: |
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347 case IREM: |
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348 masm.cdql(); |
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349 exceptionOffset = masm.codeBuffer.position(); |
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350 masm.idivl(asRegister(src)); |
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351 break; |
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352 |
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353 case LDIV: |
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354 case LREM: |
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355 Label continuation = new Label(); |
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356 if (opcode == LDIV) { |
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357 // check for special case of Long.MIN_VALUE / -1 |
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358 Label normalCase = new Label(); |
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359 masm.movq(AMD64.rdx, java.lang.Long.MIN_VALUE); |
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360 masm.cmpq(AMD64.rax, AMD64.rdx); |
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361 masm.jcc(ConditionFlag.notEqual, normalCase); |
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362 masm.cmpl(asRegister(src), -1); |
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363 masm.jcc(ConditionFlag.equal, continuation); |
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364 masm.bind(normalCase); |
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365 } |
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366 |
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367 masm.cdqq(); |
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368 exceptionOffset = masm.codeBuffer.position(); |
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369 masm.idivq(asRegister(src)); |
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370 masm.bind(continuation); |
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371 break; |
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372 |
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373 case IUDIV: |
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374 case IUREM: |
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375 // Must zero the high 64-bit word (in RDX) of the dividend |
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376 masm.xorq(AMD64.rdx, AMD64.rdx); |
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377 exceptionOffset = masm.codeBuffer.position(); |
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378 masm.divl(asRegister(src)); |
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379 break; |
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380 |
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381 case LUDIV: |
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382 case LUREM: |
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383 // Must zero the high 64-bit word (in RDX) of the dividend |
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384 masm.xorq(AMD64.rdx, AMD64.rdx); |
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385 exceptionOffset = masm.codeBuffer.position(); |
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386 masm.divq(asRegister(src)); |
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387 break; |
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388 default: |
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389 throw Util.shouldNotReachHere(); |
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390 } |
4323
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391 } else if (isConstant(src)) { |
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392 switch (opcode) { |
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393 case IADD: masm.incrementl(asIntReg(dst), tasm.asIntConst(src)); break; |
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394 case ISUB: masm.decrementl(asIntReg(dst), tasm.asIntConst(src)); break; |
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395 case IMUL: masm.imull(asIntReg(dst), asIntReg(dst), tasm.asIntConst(src)); break; |
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396 case IAND: masm.andl(asIntReg(dst), tasm.asIntConst(src)); break; |
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397 case IOR: masm.orl(asIntReg(dst), tasm.asIntConst(src)); break; |
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398 case IXOR: masm.xorl(asIntReg(dst), tasm.asIntConst(src)); break; |
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399 case ISHL: masm.shll(asIntReg(dst), tasm.asIntConst(src) & 31); break; |
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400 case ISHR: masm.sarl(asIntReg(dst), tasm.asIntConst(src) & 31); break; |
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401 case IUSHR:masm.shrl(asIntReg(dst), tasm.asIntConst(src) & 31); break; |
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402 |
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403 case LADD: masm.addq(asLongReg(dst), tasm.asIntConst(src)); break; |
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404 case LSUB: masm.subq(asLongReg(dst), tasm.asIntConst(src)); break; |
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405 case LMUL: masm.imulq(asLongReg(dst), asLongReg(dst), tasm.asIntConst(src)); break; |
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406 case LAND: masm.andq(asLongReg(dst), tasm.asIntConst(src)); break; |
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407 case LOR: masm.orq(asLongReg(dst), tasm.asIntConst(src)); break; |
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408 case LXOR: masm.xorq(asLongReg(dst), tasm.asIntConst(src)); break; |
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409 case LSHL: masm.shlq(asLongReg(dst), tasm.asIntConst(src) & 63); break; |
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410 case LSHR: masm.sarq(asLongReg(dst), tasm.asIntConst(src) & 63); break; |
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411 case LUSHR:masm.shrq(asLongReg(dst), tasm.asIntConst(src) & 63); break; |
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412 |
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413 case FADD: masm.addss(asFloatReg(dst), tasm.asFloatConstRef(src)); break; |
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414 case FSUB: masm.subss(asFloatReg(dst), tasm.asFloatConstRef(src)); break; |
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415 case FMUL: masm.mulss(asFloatReg(dst), tasm.asFloatConstRef(src)); break; |
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416 case FAND: masm.andps(asFloatReg(dst), tasm.asFloatConstRef(src, 16)); break; |
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417 case FOR: masm.orps(asFloatReg(dst), tasm.asFloatConstRef(src, 16)); break; |
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418 case FXOR: masm.xorps(asFloatReg(dst), tasm.asFloatConstRef(src, 16)); break; |
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419 case FDIV: masm.divss(asFloatReg(dst), tasm.asFloatConstRef(src)); break; |
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420 |
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421 case DADD: masm.addsd(asDoubleReg(dst), tasm.asDoubleConstRef(src)); break; |
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422 case DSUB: masm.subsd(asDoubleReg(dst), tasm.asDoubleConstRef(src)); break; |
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423 case DMUL: masm.mulsd(asDoubleReg(dst), tasm.asDoubleConstRef(src)); break; |
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424 case DDIV: masm.divsd(asDoubleReg(dst), tasm.asDoubleConstRef(src)); break; |
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425 case DAND: masm.andpd(asDoubleReg(dst), tasm.asDoubleConstRef(src, 16)); break; |
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426 case DOR: masm.orpd(asDoubleReg(dst), tasm.asDoubleConstRef(src, 16)); break; |
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427 case DXOR: masm.xorpd(asDoubleReg(dst), tasm.asDoubleConstRef(src, 16)); break; |
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428 default: throw Util.shouldNotReachHere(); |
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429 } |
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430 } else { |
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431 switch (opcode) { |
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432 case IADD: masm.addl(asIntReg(dst), tasm.asIntAddr(src)); break; |
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433 case ISUB: masm.subl(asIntReg(dst), tasm.asIntAddr(src)); break; |
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434 case IAND: masm.andl(asIntReg(dst), tasm.asIntAddr(src)); break; |
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435 case IOR: masm.orl(asIntReg(dst), tasm.asIntAddr(src)); break; |
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436 case IXOR: masm.xorl(asIntReg(dst), tasm.asIntAddr(src)); break; |
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437 |
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438 case LADD: masm.addq(asLongReg(dst), tasm.asLongAddr(src)); break; |
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439 case LSUB: masm.subq(asLongReg(dst), tasm.asLongAddr(src)); break; |
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440 case LAND: masm.andq(asLongReg(dst), tasm.asLongAddr(src)); break; |
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441 case LOR: masm.orq(asLongReg(dst), tasm.asLongAddr(src)); break; |
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442 case LXOR: masm.xorq(asLongReg(dst), tasm.asLongAddr(src)); break; |
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443 |
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444 case FADD: masm.addss(asFloatReg(dst), tasm.asFloatAddr(src)); break; |
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445 case FSUB: masm.subss(asFloatReg(dst), tasm.asFloatAddr(src)); break; |
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446 case FMUL: masm.mulss(asFloatReg(dst), tasm.asFloatAddr(src)); break; |
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447 case FDIV: masm.divss(asFloatReg(dst), tasm.asFloatAddr(src)); break; |
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448 |
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449 case DADD: masm.addsd(asDoubleReg(dst), tasm.asDoubleAddr(src)); break; |
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450 case DSUB: masm.subsd(asDoubleReg(dst), tasm.asDoubleAddr(src)); break; |
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451 case DMUL: masm.mulsd(asDoubleReg(dst), tasm.asDoubleAddr(src)); break; |
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452 case DDIV: masm.divsd(asDoubleReg(dst), tasm.asDoubleAddr(src)); break; |
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453 default: throw Util.shouldNotReachHere(); |
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454 } |
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455 } |
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456 |
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457 if (info != null) { |
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458 assert exceptionOffset != -1; |
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459 tasm.recordImplicitException(exceptionOffset, info); |
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460 } |
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461 } |
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462 |
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463 private static void emitConvertFixup(TargetMethodAssembler tasm, AMD64MacroAssembler masm, CiValue result, CiValue x) { |
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464 ConvertSlowPath slowPath = new ConvertSlowPath(result, x); |
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465 tasm.slowPaths.add(slowPath); |
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466 switch (result.kind) { |
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467 case Int: masm.cmpl(asIntReg(result), Integer.MIN_VALUE); break; |
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468 case Long: masm.cmpq(asLongReg(result), tasm.asLongConstRef(CiConstant.forLong(java.lang.Long.MIN_VALUE))); break; |
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469 default: throw Util.shouldNotReachHere(); |
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470 } |
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471 masm.jcc(ConditionFlag.equal, slowPath.start); |
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472 masm.bind(slowPath.continuation); |
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473 } |
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474 |
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475 private static class ConvertSlowPath extends AMD64SlowPath { |
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476 public final Label start = new Label(); |
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477 public final Label continuation = new Label(); |
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478 private final CiValue result; |
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479 private final CiValue x; |
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480 |
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481 public ConvertSlowPath(CiValue result, CiValue x) { |
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482 this.result = result; |
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483 this.x = x; |
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484 } |
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485 |
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486 @Override |
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487 public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { |
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488 masm.bind(start); |
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489 switch (x.kind) { |
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490 case Float: masm.ucomiss(asFloatReg(x), tasm.asFloatConstRef(CiConstant.FLOAT_0)); break; |
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491 case Double: masm.ucomisd(asDoubleReg(x), tasm.asDoubleConstRef(CiConstant.DOUBLE_0)); break; |
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492 default: throw Util.shouldNotReachHere(); |
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493 } |
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494 Label nan = new Label(); |
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495 masm.jcc(ConditionFlag.parity, nan); |
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496 masm.jcc(ConditionFlag.below, continuation); |
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497 |
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498 // input is > 0 -> return maxInt |
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499 // result register already contains 0x80000000, so subtracting 1 gives 0x7fffffff |
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500 switch (result.kind) { |
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501 case Int: masm.decrementl(asIntReg(result), 1); break; |
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502 case Long: masm.decrementq(asLongReg(result), 1); break; |
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503 default: throw Util.shouldNotReachHere(); |
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504 } |
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505 masm.jmp(continuation); |
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506 |
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507 // input is NaN -> return 0 |
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508 masm.bind(nan); |
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509 masm.xorptr(asRegister(result), asRegister(result)); |
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510 masm.jmp(continuation); |
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511 } |
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512 } |
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513 |
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514 |
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515 private static void verifyKind(AMD64Arithmetic opcode, CiValue result, CiValue x, CiValue y) { |
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516 assert (opcode.name().startsWith("I") && result.kind == CiKind.Int && x.kind.stackKind() == CiKind.Int && y.kind.stackKind() == CiKind.Int) |
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517 || (opcode.name().startsWith("L") && result.kind == CiKind.Long && x.kind == CiKind.Long && y.kind == CiKind.Long) |
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518 || (opcode.name().startsWith("F") && result.kind == CiKind.Float && x.kind == CiKind.Float && y.kind == CiKind.Float) |
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519 || (opcode.name().startsWith("D") && result.kind == CiKind.Double && x.kind == CiKind.Double && y.kind == CiKind.Double); |
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520 } |
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521 } |