Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 255:ef72a36b968e
Merge
author | kvn |
---|---|
date | Wed, 30 Jul 2008 09:54:21 -0700 |
parents | 9c2ecc2ffb12 |
children | dc7f315e41f7 |
rev | line source |
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0 | 1 // |
196 | 2 // Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
21 // have any questions. | |
22 // | |
23 // | |
24 | |
25 // AMD64 Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 | |
32 register %{ | |
33 //----------Architecture Description Register Definitions---------------------- | |
34 // General Registers | |
35 // "reg_def" name ( register save type, C convention save type, | |
36 // ideal register type, encoding ); | |
37 // Register Save Types: | |
38 // | |
39 // NS = No-Save: The register allocator assumes that these registers | |
40 // can be used without saving upon entry to the method, & | |
41 // that they do not need to be saved at call sites. | |
42 // | |
43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
44 // can be used without saving upon entry to the method, | |
45 // but that they must be saved at call sites. | |
46 // | |
47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
48 // must be saved before using them upon entry to the | |
49 // method, but they do not need to be saved at call | |
50 // sites. | |
51 // | |
52 // AS = Always-Save: The register allocator assumes that these registers | |
53 // must be saved before using them upon entry to the | |
54 // method, & that they must be saved at call sites. | |
55 // | |
56 // Ideal Register Type is used to determine how to save & restore a | |
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
59 // | |
60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
61 | |
62 // General Registers | |
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
64 // used as byte registers) | |
65 | |
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
69 | |
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
72 | |
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
75 | |
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
78 | |
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
81 | |
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
84 | |
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
88 | |
89 #ifdef _WIN64 | |
90 | |
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
93 | |
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
96 | |
97 #else | |
98 | |
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
101 | |
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
104 | |
105 #endif | |
106 | |
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
109 | |
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
112 | |
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
115 | |
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
118 | |
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
121 | |
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
124 | |
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
127 | |
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
130 | |
131 | |
132 // Floating Point Registers | |
133 | |
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
135 // Word a in each register holds a Float, words ab hold a Double. We | |
136 // currently do not use the SIMD capabilities, so registers cd are | |
137 // unused at the moment. | |
138 // XMM8-XMM15 must be encoded with REX. | |
139 // Linux ABI: No register preserved across function calls | |
140 // XMM0-XMM7 might hold parameters | |
141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
142 // XMM0-XMM3 might hold parameters | |
143 | |
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
146 | |
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
149 | |
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
152 | |
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
155 | |
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
158 | |
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
161 | |
162 #ifdef _WIN64 | |
163 | |
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
166 | |
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
169 | |
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
172 | |
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
175 | |
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
178 | |
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
181 | |
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
184 | |
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
187 | |
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
190 | |
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
193 | |
194 #else | |
195 | |
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
198 | |
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
201 | |
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
204 | |
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
207 | |
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
210 | |
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
213 | |
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
216 | |
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
219 | |
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
222 | |
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
225 | |
226 #endif // _WIN64 | |
227 | |
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
229 | |
230 // Specify priority of register selection within phases of register | |
231 // allocation. Highest priority is first. A useful heuristic is to | |
232 // give registers a low priority when they are required by machine | |
233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
235 // which participate in fixed calling sequences should come last. | |
236 // Registers which are used as pairs must fall on an even boundary. | |
237 | |
238 alloc_class chunk0(R10, R10_H, | |
239 R11, R11_H, | |
240 R8, R8_H, | |
241 R9, R9_H, | |
242 R12, R12_H, | |
243 RCX, RCX_H, | |
244 RBX, RBX_H, | |
245 RDI, RDI_H, | |
246 RDX, RDX_H, | |
247 RSI, RSI_H, | |
248 RAX, RAX_H, | |
249 RBP, RBP_H, | |
250 R13, R13_H, | |
251 R14, R14_H, | |
252 R15, R15_H, | |
253 RSP, RSP_H); | |
254 | |
255 // XXX probably use 8-15 first on Linux | |
256 alloc_class chunk1(XMM0, XMM0_H, | |
257 XMM1, XMM1_H, | |
258 XMM2, XMM2_H, | |
259 XMM3, XMM3_H, | |
260 XMM4, XMM4_H, | |
261 XMM5, XMM5_H, | |
262 XMM6, XMM6_H, | |
263 XMM7, XMM7_H, | |
264 XMM8, XMM8_H, | |
265 XMM9, XMM9_H, | |
266 XMM10, XMM10_H, | |
267 XMM11, XMM11_H, | |
268 XMM12, XMM12_H, | |
269 XMM13, XMM13_H, | |
270 XMM14, XMM14_H, | |
271 XMM15, XMM15_H); | |
272 | |
273 alloc_class chunk2(RFLAGS); | |
274 | |
275 | |
276 //----------Architecture Description Register Classes-------------------------- | |
277 // Several register classes are automatically defined based upon information in | |
278 // this architecture description. | |
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // Class for all pointer registers (including RSP) | |
286 reg_class any_reg(RAX, RAX_H, | |
287 RDX, RDX_H, | |
288 RBP, RBP_H, | |
289 RDI, RDI_H, | |
290 RSI, RSI_H, | |
291 RCX, RCX_H, | |
292 RBX, RBX_H, | |
293 RSP, RSP_H, | |
294 R8, R8_H, | |
295 R9, R9_H, | |
296 R10, R10_H, | |
297 R11, R11_H, | |
298 R12, R12_H, | |
299 R13, R13_H, | |
300 R14, R14_H, | |
301 R15, R15_H); | |
302 | |
303 // Class for all pointer registers except RSP | |
304 reg_class ptr_reg(RAX, RAX_H, | |
305 RDX, RDX_H, | |
306 RBP, RBP_H, | |
307 RDI, RDI_H, | |
308 RSI, RSI_H, | |
309 RCX, RCX_H, | |
310 RBX, RBX_H, | |
311 R8, R8_H, | |
312 R9, R9_H, | |
313 R10, R10_H, | |
314 R11, R11_H, | |
315 R13, R13_H, | |
316 R14, R14_H); | |
317 | |
318 // Class for all pointer registers except RAX and RSP | |
319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
320 RBP, RBP_H, | |
321 RDI, RDI_H, | |
322 RSI, RSI_H, | |
323 RCX, RCX_H, | |
324 RBX, RBX_H, | |
325 R8, R8_H, | |
326 R9, R9_H, | |
327 R10, R10_H, | |
328 R11, R11_H, | |
329 R12, R12_H, | |
330 R13, R13_H, | |
331 R14, R14_H); | |
332 | |
333 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
334 RAX, RAX_H, | |
335 RDI, RDI_H, | |
336 RSI, RSI_H, | |
337 RCX, RCX_H, | |
338 RBX, RBX_H, | |
339 R8, R8_H, | |
340 R9, R9_H, | |
341 R10, R10_H, | |
342 R11, R11_H, | |
343 R12, R12_H, | |
344 R13, R13_H, | |
345 R14, R14_H); | |
346 | |
347 // Class for all pointer registers except RAX, RBX and RSP | |
348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
349 RBP, RBP_H, | |
350 RDI, RDI_H, | |
351 RSI, RSI_H, | |
352 RCX, RCX_H, | |
353 R8, R8_H, | |
354 R9, R9_H, | |
355 R10, R10_H, | |
356 R11, R11_H, | |
357 R12, R12_H, | |
358 R13, R13_H, | |
359 R14, R14_H); | |
360 | |
361 // Singleton class for RAX pointer register | |
362 reg_class ptr_rax_reg(RAX, RAX_H); | |
363 | |
364 // Singleton class for RBX pointer register | |
365 reg_class ptr_rbx_reg(RBX, RBX_H); | |
366 | |
367 // Singleton class for RSI pointer register | |
368 reg_class ptr_rsi_reg(RSI, RSI_H); | |
369 | |
370 // Singleton class for RDI pointer register | |
371 reg_class ptr_rdi_reg(RDI, RDI_H); | |
372 | |
373 // Singleton class for RBP pointer register | |
374 reg_class ptr_rbp_reg(RBP, RBP_H); | |
375 | |
376 // Singleton class for stack pointer | |
377 reg_class ptr_rsp_reg(RSP, RSP_H); | |
378 | |
379 // Singleton class for TLS pointer | |
380 reg_class ptr_r15_reg(R15, R15_H); | |
381 | |
382 // Class for all long registers (except RSP) | |
383 reg_class long_reg(RAX, RAX_H, | |
384 RDX, RDX_H, | |
385 RBP, RBP_H, | |
386 RDI, RDI_H, | |
387 RSI, RSI_H, | |
388 RCX, RCX_H, | |
389 RBX, RBX_H, | |
390 R8, R8_H, | |
391 R9, R9_H, | |
392 R10, R10_H, | |
393 R11, R11_H, | |
394 R13, R13_H, | |
395 R14, R14_H); | |
396 | |
397 // Class for all long registers except RAX, RDX (and RSP) | |
398 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
399 RDI, RDI_H, | |
400 RSI, RSI_H, | |
401 RCX, RCX_H, | |
402 RBX, RBX_H, | |
403 R8, R8_H, | |
404 R9, R9_H, | |
405 R10, R10_H, | |
406 R11, R11_H, | |
407 R13, R13_H, | |
408 R14, R14_H); | |
409 | |
410 // Class for all long registers except RCX (and RSP) | |
411 reg_class long_no_rcx_reg(RBP, RBP_H, | |
412 RDI, RDI_H, | |
413 RSI, RSI_H, | |
414 RAX, RAX_H, | |
415 RDX, RDX_H, | |
416 RBX, RBX_H, | |
417 R8, R8_H, | |
418 R9, R9_H, | |
419 R10, R10_H, | |
420 R11, R11_H, | |
421 R13, R13_H, | |
422 R14, R14_H); | |
423 | |
424 // Class for all long registers except RAX (and RSP) | |
425 reg_class long_no_rax_reg(RBP, RBP_H, | |
426 RDX, RDX_H, | |
427 RDI, RDI_H, | |
428 RSI, RSI_H, | |
429 RCX, RCX_H, | |
430 RBX, RBX_H, | |
431 R8, R8_H, | |
432 R9, R9_H, | |
433 R10, R10_H, | |
434 R11, R11_H, | |
435 R13, R13_H, | |
436 R14, R14_H); | |
437 | |
438 // Singleton class for RAX long register | |
439 reg_class long_rax_reg(RAX, RAX_H); | |
440 | |
441 // Singleton class for RCX long register | |
442 reg_class long_rcx_reg(RCX, RCX_H); | |
443 | |
444 // Singleton class for RDX long register | |
445 reg_class long_rdx_reg(RDX, RDX_H); | |
446 | |
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447 // Singleton class for R12 long register |
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448 reg_class long_r12_reg(R12, R12_H); |
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449 |
0 | 450 // Class for all int registers (except RSP) |
451 reg_class int_reg(RAX, | |
452 RDX, | |
453 RBP, | |
454 RDI, | |
455 RSI, | |
456 RCX, | |
457 RBX, | |
458 R8, | |
459 R9, | |
460 R10, | |
461 R11, | |
462 R13, | |
463 R14); | |
464 | |
465 // Class for all int registers except RCX (and RSP) | |
466 reg_class int_no_rcx_reg(RAX, | |
467 RDX, | |
468 RBP, | |
469 RDI, | |
470 RSI, | |
471 RBX, | |
472 R8, | |
473 R9, | |
474 R10, | |
475 R11, | |
476 R13, | |
477 R14); | |
478 | |
479 // Class for all int registers except RAX, RDX (and RSP) | |
480 reg_class int_no_rax_rdx_reg(RBP, | |
481 RDI | |
482 RSI, | |
483 RCX, | |
484 RBX, | |
485 R8, | |
486 R9, | |
487 R10, | |
488 R11, | |
489 R13, | |
490 R14); | |
491 | |
492 // Singleton class for RAX int register | |
493 reg_class int_rax_reg(RAX); | |
494 | |
495 // Singleton class for RBX int register | |
496 reg_class int_rbx_reg(RBX); | |
497 | |
498 // Singleton class for RCX int register | |
499 reg_class int_rcx_reg(RCX); | |
500 | |
501 // Singleton class for RCX int register | |
502 reg_class int_rdx_reg(RDX); | |
503 | |
504 // Singleton class for RCX int register | |
505 reg_class int_rdi_reg(RDI); | |
506 | |
507 // Singleton class for instruction pointer | |
508 // reg_class ip_reg(RIP); | |
509 | |
510 // Singleton class for condition codes | |
511 reg_class int_flags(RFLAGS); | |
512 | |
513 // Class for all float registers | |
514 reg_class float_reg(XMM0, | |
515 XMM1, | |
516 XMM2, | |
517 XMM3, | |
518 XMM4, | |
519 XMM5, | |
520 XMM6, | |
521 XMM7, | |
522 XMM8, | |
523 XMM9, | |
524 XMM10, | |
525 XMM11, | |
526 XMM12, | |
527 XMM13, | |
528 XMM14, | |
529 XMM15); | |
530 | |
531 // Class for all double registers | |
532 reg_class double_reg(XMM0, XMM0_H, | |
533 XMM1, XMM1_H, | |
534 XMM2, XMM2_H, | |
535 XMM3, XMM3_H, | |
536 XMM4, XMM4_H, | |
537 XMM5, XMM5_H, | |
538 XMM6, XMM6_H, | |
539 XMM7, XMM7_H, | |
540 XMM8, XMM8_H, | |
541 XMM9, XMM9_H, | |
542 XMM10, XMM10_H, | |
543 XMM11, XMM11_H, | |
544 XMM12, XMM12_H, | |
545 XMM13, XMM13_H, | |
546 XMM14, XMM14_H, | |
547 XMM15, XMM15_H); | |
548 %} | |
549 | |
550 | |
551 //----------SOURCE BLOCK------------------------------------------------------- | |
552 // This is a block of C++ code which provides values, functions, and | |
553 // definitions necessary in the rest of the architecture description | |
554 source %{ | |
555 #define RELOC_IMM64 Assembler::imm64_operand | |
556 #define RELOC_DISP32 Assembler::disp32_operand | |
557 | |
558 #define __ _masm. | |
559 | |
560 // !!!!! Special hack to get all types of calls to specify the byte offset | |
561 // from the start of the call to the point where the return address | |
562 // will point. | |
563 int MachCallStaticJavaNode::ret_addr_offset() | |
564 { | |
565 return 5; // 5 bytes from start of call to where return address points | |
566 } | |
567 | |
568 int MachCallDynamicJavaNode::ret_addr_offset() | |
569 { | |
570 return 15; // 15 bytes from start of call to where return address points | |
571 } | |
572 | |
573 // In os_cpu .ad file | |
574 // int MachCallRuntimeNode::ret_addr_offset() | |
575 | |
576 // Indicate if the safepoint node needs the polling page as an input. | |
577 // Since amd64 does not have absolute addressing but RIP-relative | |
578 // addressing and the polling page is within 2G, it doesn't. | |
579 bool SafePointNode::needs_polling_address_input() | |
580 { | |
581 return false; | |
582 } | |
583 | |
584 // | |
585 // Compute padding required for nodes which need alignment | |
586 // | |
587 | |
588 // The address of the call instruction needs to be 4-byte aligned to | |
589 // ensure that it does not span a cache line so that it can be patched. | |
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
591 { | |
592 current_offset += 1; // skip call opcode byte | |
593 return round_to(current_offset, alignment_required()) - current_offset; | |
594 } | |
595 | |
596 // The address of the call instruction needs to be 4-byte aligned to | |
597 // ensure that it does not span a cache line so that it can be patched. | |
598 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const | |
599 { | |
600 current_offset += 11; // skip movq instruction + call opcode byte | |
601 return round_to(current_offset, alignment_required()) - current_offset; | |
602 } | |
603 | |
604 #ifndef PRODUCT | |
605 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
606 { | |
607 st->print("INT3"); | |
608 } | |
609 #endif | |
610 | |
611 // EMIT_RM() | |
612 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) | |
613 { | |
614 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); | |
615 *(cbuf.code_end()) = c; | |
616 cbuf.set_code_end(cbuf.code_end() + 1); | |
617 } | |
618 | |
619 // EMIT_CC() | |
620 void emit_cc(CodeBuffer &cbuf, int f1, int f2) | |
621 { | |
622 unsigned char c = (unsigned char) (f1 | f2); | |
623 *(cbuf.code_end()) = c; | |
624 cbuf.set_code_end(cbuf.code_end() + 1); | |
625 } | |
626 | |
627 // EMIT_OPCODE() | |
628 void emit_opcode(CodeBuffer &cbuf, int code) | |
629 { | |
630 *(cbuf.code_end()) = (unsigned char) code; | |
631 cbuf.set_code_end(cbuf.code_end() + 1); | |
632 } | |
633 | |
634 // EMIT_OPCODE() w/ relocation information | |
635 void emit_opcode(CodeBuffer &cbuf, | |
636 int code, relocInfo::relocType reloc, int offset, int format) | |
637 { | |
638 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format); | |
639 emit_opcode(cbuf, code); | |
640 } | |
641 | |
642 // EMIT_D8() | |
643 void emit_d8(CodeBuffer &cbuf, int d8) | |
644 { | |
645 *(cbuf.code_end()) = (unsigned char) d8; | |
646 cbuf.set_code_end(cbuf.code_end() + 1); | |
647 } | |
648 | |
649 // EMIT_D16() | |
650 void emit_d16(CodeBuffer &cbuf, int d16) | |
651 { | |
652 *((short *)(cbuf.code_end())) = d16; | |
653 cbuf.set_code_end(cbuf.code_end() + 2); | |
654 } | |
655 | |
656 // EMIT_D32() | |
657 void emit_d32(CodeBuffer &cbuf, int d32) | |
658 { | |
659 *((int *)(cbuf.code_end())) = d32; | |
660 cbuf.set_code_end(cbuf.code_end() + 4); | |
661 } | |
662 | |
663 // EMIT_D64() | |
664 void emit_d64(CodeBuffer &cbuf, int64_t d64) | |
665 { | |
666 *((int64_t*) (cbuf.code_end())) = d64; | |
667 cbuf.set_code_end(cbuf.code_end() + 8); | |
668 } | |
669 | |
670 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
671 void emit_d32_reloc(CodeBuffer& cbuf, | |
672 int d32, | |
673 relocInfo::relocType reloc, | |
674 int format) | |
675 { | |
676 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
677 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
678 | |
679 *((int*) (cbuf.code_end())) = d32; | |
680 cbuf.set_code_end(cbuf.code_end() + 4); | |
681 } | |
682 | |
683 // emit 32 bit value and construct relocation entry from RelocationHolder | |
684 void emit_d32_reloc(CodeBuffer& cbuf, | |
685 int d32, | |
686 RelocationHolder const& rspec, | |
687 int format) | |
688 { | |
689 #ifdef ASSERT | |
690 if (rspec.reloc()->type() == relocInfo::oop_type && | |
691 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
692 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code"); | |
693 } | |
694 #endif | |
695 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
696 | |
697 *((int* )(cbuf.code_end())) = d32; | |
698 cbuf.set_code_end(cbuf.code_end() + 4); | |
699 } | |
700 | |
701 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
702 address next_ip = cbuf.code_end() + 4; | |
703 emit_d32_reloc(cbuf, (int) (addr - next_ip), | |
704 external_word_Relocation::spec(addr), | |
705 RELOC_DISP32); | |
706 } | |
707 | |
708 | |
709 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
710 void emit_d64_reloc(CodeBuffer& cbuf, | |
711 int64_t d64, | |
712 relocInfo::relocType reloc, | |
713 int format) | |
714 { | |
715 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
716 | |
717 *((int64_t*) (cbuf.code_end())) = d64; | |
718 cbuf.set_code_end(cbuf.code_end() + 8); | |
719 } | |
720 | |
721 // emit 64 bit value and construct relocation entry from RelocationHolder | |
722 void emit_d64_reloc(CodeBuffer& cbuf, | |
723 int64_t d64, | |
724 RelocationHolder const& rspec, | |
725 int format) | |
726 { | |
727 #ifdef ASSERT | |
728 if (rspec.reloc()->type() == relocInfo::oop_type && | |
729 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
730 assert(oop(d64)->is_oop() && oop(d64)->is_perm(), | |
731 "cannot embed non-perm oops in code"); | |
732 } | |
733 #endif | |
734 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
735 | |
736 *((int64_t*) (cbuf.code_end())) = d64; | |
737 cbuf.set_code_end(cbuf.code_end() + 8); | |
738 } | |
739 | |
740 // Access stack slot for load or store | |
741 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
742 { | |
743 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
744 if (-0x80 <= disp && disp < 0x80) { | |
745 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
746 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
747 emit_d8(cbuf, disp); // Displacement // R/M byte | |
748 } else { | |
749 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
750 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
751 emit_d32(cbuf, disp); // Displacement // R/M byte | |
752 } | |
753 } | |
754 | |
755 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
756 void encode_RegMem(CodeBuffer &cbuf, | |
757 int reg, | |
758 int base, int index, int scale, int disp, bool disp_is_oop) | |
759 { | |
760 assert(!disp_is_oop, "cannot have disp"); | |
761 int regenc = reg & 7; | |
762 int baseenc = base & 7; | |
763 int indexenc = index & 7; | |
764 | |
765 // There is no index & no scale, use form without SIB byte | |
766 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
767 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
768 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
769 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
770 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
771 // If 8-bit displacement, mode 0x1 | |
772 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
773 emit_d8(cbuf, disp); | |
774 } else { | |
775 // If 32-bit displacement | |
776 if (base == -1) { // Special flag for absolute address | |
777 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
778 if (disp_is_oop) { | |
779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
780 } else { | |
781 emit_d32(cbuf, disp); | |
782 } | |
783 } else { | |
784 // Normal base + offset | |
785 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
786 if (disp_is_oop) { | |
787 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
788 } else { | |
789 emit_d32(cbuf, disp); | |
790 } | |
791 } | |
792 } | |
793 } else { | |
794 // Else, encode with the SIB byte | |
795 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
796 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
797 // If no displacement | |
798 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
799 emit_rm(cbuf, scale, indexenc, baseenc); | |
800 } else { | |
801 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
802 // If 8-bit displacement, mode 0x1 | |
803 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
804 emit_rm(cbuf, scale, indexenc, baseenc); | |
805 emit_d8(cbuf, disp); | |
806 } else { | |
807 // If 32-bit displacement | |
808 if (base == 0x04 ) { | |
809 emit_rm(cbuf, 0x2, regenc, 0x4); | |
810 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
811 } else { | |
812 emit_rm(cbuf, 0x2, regenc, 0x4); | |
813 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
814 } | |
815 if (disp_is_oop) { | |
816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
817 } else { | |
818 emit_d32(cbuf, disp); | |
819 } | |
820 } | |
821 } | |
822 } | |
823 } | |
824 | |
825 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
826 { | |
827 if (dstenc != srcenc) { | |
828 if (dstenc < 8) { | |
829 if (srcenc >= 8) { | |
830 emit_opcode(cbuf, Assembler::REX_B); | |
831 srcenc -= 8; | |
832 } | |
833 } else { | |
834 if (srcenc < 8) { | |
835 emit_opcode(cbuf, Assembler::REX_R); | |
836 } else { | |
837 emit_opcode(cbuf, Assembler::REX_RB); | |
838 srcenc -= 8; | |
839 } | |
840 dstenc -= 8; | |
841 } | |
842 | |
843 emit_opcode(cbuf, 0x8B); | |
844 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
845 } | |
846 } | |
847 | |
848 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
849 if( dst_encoding == src_encoding ) { | |
850 // reg-reg copy, use an empty encoding | |
851 } else { | |
852 MacroAssembler _masm(&cbuf); | |
853 | |
854 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
855 } | |
856 } | |
857 | |
858 | |
859 //============================================================================= | |
860 #ifndef PRODUCT | |
861 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
862 { | |
863 Compile* C = ra_->C; | |
864 | |
865 int framesize = C->frame_slots() << LogBytesPerInt; | |
866 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
867 // Remove wordSize for return adr already pushed | |
868 // and another for the RBP we are going to save | |
869 framesize -= 2*wordSize; | |
870 bool need_nop = true; | |
871 | |
872 // Calls to C2R adapters often do not accept exceptional returns. | |
873 // We require that their callers must bang for them. But be | |
874 // careful, because some VM calls (such as call site linkage) can | |
875 // use several kilobytes of stack. But the stack safety zone should | |
876 // account for that. See bugs 4446381, 4468289, 4497237. | |
877 if (C->need_stack_bang(framesize)) { | |
878 st->print_cr("# stack bang"); st->print("\t"); | |
879 need_nop = false; | |
880 } | |
881 st->print_cr("pushq rbp"); st->print("\t"); | |
882 | |
883 if (VerifyStackAtCalls) { | |
884 // Majik cookie to verify stack depth | |
885 st->print_cr("pushq 0xffffffffbadb100d" | |
886 "\t# Majik cookie for stack depth check"); | |
887 st->print("\t"); | |
888 framesize -= wordSize; // Remove 2 for cookie | |
889 need_nop = false; | |
890 } | |
891 | |
892 if (framesize) { | |
893 st->print("subq rsp, #%d\t# Create frame", framesize); | |
894 if (framesize < 0x80 && need_nop) { | |
895 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
896 } | |
897 } | |
898 } | |
899 #endif | |
900 | |
901 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
902 { | |
903 Compile* C = ra_->C; | |
904 | |
905 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
906 // NativeJump::patch_verified_entry will be able to patch out the entry | |
907 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
908 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
909 // 6 bytes. So if we don't do the fldcw or the push then we must | |
910 // use the 6 byte frame allocation even if we have no frame. :-( | |
911 // If method sets FPU control word do it now | |
912 | |
913 int framesize = C->frame_slots() << LogBytesPerInt; | |
914 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
915 // Remove wordSize for return adr already pushed | |
916 // and another for the RBP we are going to save | |
917 framesize -= 2*wordSize; | |
918 bool need_nop = true; | |
919 | |
920 // Calls to C2R adapters often do not accept exceptional returns. | |
921 // We require that their callers must bang for them. But be | |
922 // careful, because some VM calls (such as call site linkage) can | |
923 // use several kilobytes of stack. But the stack safety zone should | |
924 // account for that. See bugs 4446381, 4468289, 4497237. | |
925 if (C->need_stack_bang(framesize)) { | |
926 MacroAssembler masm(&cbuf); | |
927 masm.generate_stack_overflow_check(framesize); | |
928 need_nop = false; | |
929 } | |
930 | |
931 // We always push rbp so that on return to interpreter rbp will be | |
932 // restored correctly and we can correct the stack. | |
933 emit_opcode(cbuf, 0x50 | RBP_enc); | |
934 | |
935 if (VerifyStackAtCalls) { | |
936 // Majik cookie to verify stack depth | |
937 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
938 emit_d32(cbuf, 0xbadb100d); | |
939 framesize -= wordSize; // Remove 2 for cookie | |
940 need_nop = false; | |
941 } | |
942 | |
943 if (framesize) { | |
944 emit_opcode(cbuf, Assembler::REX_W); | |
945 if (framesize < 0x80) { | |
946 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
947 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
948 emit_d8(cbuf, framesize); | |
949 if (need_nop) { | |
950 emit_opcode(cbuf, 0x90); // nop | |
951 } | |
952 } else { | |
953 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
954 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
955 emit_d32(cbuf, framesize); | |
956 } | |
957 } | |
958 | |
959 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); | |
960 | |
961 #ifdef ASSERT | |
962 if (VerifyStackAtCalls) { | |
963 Label L; | |
964 MacroAssembler masm(&cbuf); | |
965 masm.pushq(rax); | |
966 masm.movq(rax, rsp); | |
967 masm.andq(rax, StackAlignmentInBytes-1); | |
968 masm.cmpq(rax, StackAlignmentInBytes-wordSize); | |
969 masm.popq(rax); | |
970 masm.jcc(Assembler::equal, L); | |
971 masm.stop("Stack is not properly aligned!"); | |
972 masm.bind(L); | |
973 } | |
974 #endif | |
975 } | |
976 | |
977 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
978 { | |
979 return MachNode::size(ra_); // too many variables; just compute it | |
980 // the hard way | |
981 } | |
982 | |
983 int MachPrologNode::reloc() const | |
984 { | |
985 return 0; // a large enough number | |
986 } | |
987 | |
988 //============================================================================= | |
989 #ifndef PRODUCT | |
990 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
991 { | |
992 Compile* C = ra_->C; | |
993 int framesize = C->frame_slots() << LogBytesPerInt; | |
994 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
995 // Remove word for return adr already pushed | |
996 // and RBP | |
997 framesize -= 2*wordSize; | |
998 | |
999 if (framesize) { | |
1000 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize); | |
1001 st->print("\t"); | |
1002 } | |
1003 | |
1004 st->print_cr("popq\trbp"); | |
1005 if (do_polling() && C->is_method_compilation()) { | |
1006 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t" | |
1007 "# Safepoint: poll for GC"); | |
1008 st->print("\t"); | |
1009 } | |
1010 } | |
1011 #endif | |
1012 | |
1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
1014 { | |
1015 Compile* C = ra_->C; | |
1016 int framesize = C->frame_slots() << LogBytesPerInt; | |
1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
1018 // Remove word for return adr already pushed | |
1019 // and RBP | |
1020 framesize -= 2*wordSize; | |
1021 | |
1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
1023 | |
1024 if (framesize) { | |
1025 emit_opcode(cbuf, Assembler::REX_W); | |
1026 if (framesize < 0x80) { | |
1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
1029 emit_d8(cbuf, framesize); | |
1030 } else { | |
1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
1033 emit_d32(cbuf, framesize); | |
1034 } | |
1035 } | |
1036 | |
1037 // popq rbp | |
1038 emit_opcode(cbuf, 0x58 | RBP_enc); | |
1039 | |
1040 if (do_polling() && C->is_method_compilation()) { | |
1041 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
1042 // XXX reg_mem doesn't support RIP-relative addressing yet | |
1043 cbuf.set_inst_mark(); | |
1044 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX | |
1045 emit_opcode(cbuf, 0x85); // testl | |
1046 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
1047 // cbuf.inst_mark() is beginning of instruction | |
1048 emit_d32_reloc(cbuf, os::get_polling_page()); | |
1049 // relocInfo::poll_return_type, | |
1050 } | |
1051 } | |
1052 | |
1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
1054 { | |
1055 Compile* C = ra_->C; | |
1056 int framesize = C->frame_slots() << LogBytesPerInt; | |
1057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
1058 // Remove word for return adr already pushed | |
1059 // and RBP | |
1060 framesize -= 2*wordSize; | |
1061 | |
1062 uint size = 0; | |
1063 | |
1064 if (do_polling() && C->is_method_compilation()) { | |
1065 size += 6; | |
1066 } | |
1067 | |
1068 // count popq rbp | |
1069 size++; | |
1070 | |
1071 if (framesize) { | |
1072 if (framesize < 0x80) { | |
1073 size += 4; | |
1074 } else if (framesize) { | |
1075 size += 7; | |
1076 } | |
1077 } | |
1078 | |
1079 return size; | |
1080 } | |
1081 | |
1082 int MachEpilogNode::reloc() const | |
1083 { | |
1084 return 2; // a large enough number | |
1085 } | |
1086 | |
1087 const Pipeline* MachEpilogNode::pipeline() const | |
1088 { | |
1089 return MachNode::pipeline_class(); | |
1090 } | |
1091 | |
1092 int MachEpilogNode::safepoint_offset() const | |
1093 { | |
1094 return 0; | |
1095 } | |
1096 | |
1097 //============================================================================= | |
1098 | |
1099 enum RC { | |
1100 rc_bad, | |
1101 rc_int, | |
1102 rc_float, | |
1103 rc_stack | |
1104 }; | |
1105 | |
1106 static enum RC rc_class(OptoReg::Name reg) | |
1107 { | |
1108 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1109 | |
1110 if (OptoReg::is_stack(reg)) return rc_stack; | |
1111 | |
1112 VMReg r = OptoReg::as_VMReg(reg); | |
1113 | |
1114 if (r->is_Register()) return rc_int; | |
1115 | |
1116 assert(r->is_XMMRegister(), "must be"); | |
1117 return rc_float; | |
1118 } | |
1119 | |
1120 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
1121 PhaseRegAlloc* ra_, | |
1122 bool do_size, | |
1123 outputStream* st) const | |
1124 { | |
1125 | |
1126 // Get registers to move | |
1127 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1128 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1129 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
1130 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
1131 | |
1132 enum RC src_second_rc = rc_class(src_second); | |
1133 enum RC src_first_rc = rc_class(src_first); | |
1134 enum RC dst_second_rc = rc_class(dst_second); | |
1135 enum RC dst_first_rc = rc_class(dst_first); | |
1136 | |
1137 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
1138 "must move at least 1 register" ); | |
1139 | |
1140 if (src_first == dst_first && src_second == dst_second) { | |
1141 // Self copy, no move | |
1142 return 0; | |
1143 } else if (src_first_rc == rc_stack) { | |
1144 // mem -> | |
1145 if (dst_first_rc == rc_stack) { | |
1146 // mem -> mem | |
1147 assert(src_second != dst_first, "overlap"); | |
1148 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1149 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1150 // 64-bit | |
1151 int src_offset = ra_->reg2offset(src_first); | |
1152 int dst_offset = ra_->reg2offset(dst_first); | |
1153 if (cbuf) { | |
1154 emit_opcode(*cbuf, 0xFF); | |
1155 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
1156 | |
1157 emit_opcode(*cbuf, 0x8F); | |
1158 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
1159 | |
1160 #ifndef PRODUCT | |
1161 } else if (!do_size) { | |
1162 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
1163 "popq [rsp + #%d]", | |
1164 src_offset, | |
1165 dst_offset); | |
1166 #endif | |
1167 } | |
1168 return | |
1169 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
1170 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
1171 } else { | |
1172 // 32-bit | |
1173 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1174 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1175 // No pushl/popl, so: | |
1176 int src_offset = ra_->reg2offset(src_first); | |
1177 int dst_offset = ra_->reg2offset(dst_first); | |
1178 if (cbuf) { | |
1179 emit_opcode(*cbuf, Assembler::REX_W); | |
1180 emit_opcode(*cbuf, 0x89); | |
1181 emit_opcode(*cbuf, 0x44); | |
1182 emit_opcode(*cbuf, 0x24); | |
1183 emit_opcode(*cbuf, 0xF8); | |
1184 | |
1185 emit_opcode(*cbuf, 0x8B); | |
1186 encode_RegMem(*cbuf, | |
1187 RAX_enc, | |
1188 RSP_enc, 0x4, 0, src_offset, | |
1189 false); | |
1190 | |
1191 emit_opcode(*cbuf, 0x89); | |
1192 encode_RegMem(*cbuf, | |
1193 RAX_enc, | |
1194 RSP_enc, 0x4, 0, dst_offset, | |
1195 false); | |
1196 | |
1197 emit_opcode(*cbuf, Assembler::REX_W); | |
1198 emit_opcode(*cbuf, 0x8B); | |
1199 emit_opcode(*cbuf, 0x44); | |
1200 emit_opcode(*cbuf, 0x24); | |
1201 emit_opcode(*cbuf, 0xF8); | |
1202 | |
1203 #ifndef PRODUCT | |
1204 } else if (!do_size) { | |
1205 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
1206 "movl rax, [rsp + #%d]\n\t" | |
1207 "movl [rsp + #%d], rax\n\t" | |
1208 "movq rax, [rsp - #8]", | |
1209 src_offset, | |
1210 dst_offset); | |
1211 #endif | |
1212 } | |
1213 return | |
1214 5 + // movq | |
1215 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
1216 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
1217 5; // movq | |
1218 } | |
1219 } else if (dst_first_rc == rc_int) { | |
1220 // mem -> gpr | |
1221 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1223 // 64-bit | |
1224 int offset = ra_->reg2offset(src_first); | |
1225 if (cbuf) { | |
1226 if (Matcher::_regEncode[dst_first] < 8) { | |
1227 emit_opcode(*cbuf, Assembler::REX_W); | |
1228 } else { | |
1229 emit_opcode(*cbuf, Assembler::REX_WR); | |
1230 } | |
1231 emit_opcode(*cbuf, 0x8B); | |
1232 encode_RegMem(*cbuf, | |
1233 Matcher::_regEncode[dst_first], | |
1234 RSP_enc, 0x4, 0, offset, | |
1235 false); | |
1236 #ifndef PRODUCT | |
1237 } else if (!do_size) { | |
1238 st->print("movq %s, [rsp + #%d]\t# spill", | |
1239 Matcher::regName[dst_first], | |
1240 offset); | |
1241 #endif | |
1242 } | |
1243 return | |
1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
1245 } else { | |
1246 // 32-bit | |
1247 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1248 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1249 int offset = ra_->reg2offset(src_first); | |
1250 if (cbuf) { | |
1251 if (Matcher::_regEncode[dst_first] >= 8) { | |
1252 emit_opcode(*cbuf, Assembler::REX_R); | |
1253 } | |
1254 emit_opcode(*cbuf, 0x8B); | |
1255 encode_RegMem(*cbuf, | |
1256 Matcher::_regEncode[dst_first], | |
1257 RSP_enc, 0x4, 0, offset, | |
1258 false); | |
1259 #ifndef PRODUCT | |
1260 } else if (!do_size) { | |
1261 st->print("movl %s, [rsp + #%d]\t# spill", | |
1262 Matcher::regName[dst_first], | |
1263 offset); | |
1264 #endif | |
1265 } | |
1266 return | |
1267 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1268 ((Matcher::_regEncode[dst_first] < 8) | |
1269 ? 3 | |
1270 : 4); // REX | |
1271 } | |
1272 } else if (dst_first_rc == rc_float) { | |
1273 // mem-> xmm | |
1274 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1275 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1276 // 64-bit | |
1277 int offset = ra_->reg2offset(src_first); | |
1278 if (cbuf) { | |
1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
1280 if (Matcher::_regEncode[dst_first] >= 8) { | |
1281 emit_opcode(*cbuf, Assembler::REX_R); | |
1282 } | |
1283 emit_opcode(*cbuf, 0x0F); | |
1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
1285 encode_RegMem(*cbuf, | |
1286 Matcher::_regEncode[dst_first], | |
1287 RSP_enc, 0x4, 0, offset, | |
1288 false); | |
1289 #ifndef PRODUCT | |
1290 } else if (!do_size) { | |
1291 st->print("%s %s, [rsp + #%d]\t# spill", | |
1292 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
1293 Matcher::regName[dst_first], | |
1294 offset); | |
1295 #endif | |
1296 } | |
1297 return | |
1298 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1299 ((Matcher::_regEncode[dst_first] < 8) | |
1300 ? 5 | |
1301 : 6); // REX | |
1302 } else { | |
1303 // 32-bit | |
1304 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1305 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1306 int offset = ra_->reg2offset(src_first); | |
1307 if (cbuf) { | |
1308 emit_opcode(*cbuf, 0xF3); | |
1309 if (Matcher::_regEncode[dst_first] >= 8) { | |
1310 emit_opcode(*cbuf, Assembler::REX_R); | |
1311 } | |
1312 emit_opcode(*cbuf, 0x0F); | |
1313 emit_opcode(*cbuf, 0x10); | |
1314 encode_RegMem(*cbuf, | |
1315 Matcher::_regEncode[dst_first], | |
1316 RSP_enc, 0x4, 0, offset, | |
1317 false); | |
1318 #ifndef PRODUCT | |
1319 } else if (!do_size) { | |
1320 st->print("movss %s, [rsp + #%d]\t# spill", | |
1321 Matcher::regName[dst_first], | |
1322 offset); | |
1323 #endif | |
1324 } | |
1325 return | |
1326 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1327 ((Matcher::_regEncode[dst_first] < 8) | |
1328 ? 5 | |
1329 : 6); // REX | |
1330 } | |
1331 } | |
1332 } else if (src_first_rc == rc_int) { | |
1333 // gpr -> | |
1334 if (dst_first_rc == rc_stack) { | |
1335 // gpr -> mem | |
1336 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1337 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1338 // 64-bit | |
1339 int offset = ra_->reg2offset(dst_first); | |
1340 if (cbuf) { | |
1341 if (Matcher::_regEncode[src_first] < 8) { | |
1342 emit_opcode(*cbuf, Assembler::REX_W); | |
1343 } else { | |
1344 emit_opcode(*cbuf, Assembler::REX_WR); | |
1345 } | |
1346 emit_opcode(*cbuf, 0x89); | |
1347 encode_RegMem(*cbuf, | |
1348 Matcher::_regEncode[src_first], | |
1349 RSP_enc, 0x4, 0, offset, | |
1350 false); | |
1351 #ifndef PRODUCT | |
1352 } else if (!do_size) { | |
1353 st->print("movq [rsp + #%d], %s\t# spill", | |
1354 offset, | |
1355 Matcher::regName[src_first]); | |
1356 #endif | |
1357 } | |
1358 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
1359 } else { | |
1360 // 32-bit | |
1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1363 int offset = ra_->reg2offset(dst_first); | |
1364 if (cbuf) { | |
1365 if (Matcher::_regEncode[src_first] >= 8) { | |
1366 emit_opcode(*cbuf, Assembler::REX_R); | |
1367 } | |
1368 emit_opcode(*cbuf, 0x89); | |
1369 encode_RegMem(*cbuf, | |
1370 Matcher::_regEncode[src_first], | |
1371 RSP_enc, 0x4, 0, offset, | |
1372 false); | |
1373 #ifndef PRODUCT | |
1374 } else if (!do_size) { | |
1375 st->print("movl [rsp + #%d], %s\t# spill", | |
1376 offset, | |
1377 Matcher::regName[src_first]); | |
1378 #endif | |
1379 } | |
1380 return | |
1381 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1382 ((Matcher::_regEncode[src_first] < 8) | |
1383 ? 3 | |
1384 : 4); // REX | |
1385 } | |
1386 } else if (dst_first_rc == rc_int) { | |
1387 // gpr -> gpr | |
1388 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1389 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1390 // 64-bit | |
1391 if (cbuf) { | |
1392 if (Matcher::_regEncode[dst_first] < 8) { | |
1393 if (Matcher::_regEncode[src_first] < 8) { | |
1394 emit_opcode(*cbuf, Assembler::REX_W); | |
1395 } else { | |
1396 emit_opcode(*cbuf, Assembler::REX_WB); | |
1397 } | |
1398 } else { | |
1399 if (Matcher::_regEncode[src_first] < 8) { | |
1400 emit_opcode(*cbuf, Assembler::REX_WR); | |
1401 } else { | |
1402 emit_opcode(*cbuf, Assembler::REX_WRB); | |
1403 } | |
1404 } | |
1405 emit_opcode(*cbuf, 0x8B); | |
1406 emit_rm(*cbuf, 0x3, | |
1407 Matcher::_regEncode[dst_first] & 7, | |
1408 Matcher::_regEncode[src_first] & 7); | |
1409 #ifndef PRODUCT | |
1410 } else if (!do_size) { | |
1411 st->print("movq %s, %s\t# spill", | |
1412 Matcher::regName[dst_first], | |
1413 Matcher::regName[src_first]); | |
1414 #endif | |
1415 } | |
1416 return 3; // REX | |
1417 } else { | |
1418 // 32-bit | |
1419 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1420 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1421 if (cbuf) { | |
1422 if (Matcher::_regEncode[dst_first] < 8) { | |
1423 if (Matcher::_regEncode[src_first] >= 8) { | |
1424 emit_opcode(*cbuf, Assembler::REX_B); | |
1425 } | |
1426 } else { | |
1427 if (Matcher::_regEncode[src_first] < 8) { | |
1428 emit_opcode(*cbuf, Assembler::REX_R); | |
1429 } else { | |
1430 emit_opcode(*cbuf, Assembler::REX_RB); | |
1431 } | |
1432 } | |
1433 emit_opcode(*cbuf, 0x8B); | |
1434 emit_rm(*cbuf, 0x3, | |
1435 Matcher::_regEncode[dst_first] & 7, | |
1436 Matcher::_regEncode[src_first] & 7); | |
1437 #ifndef PRODUCT | |
1438 } else if (!do_size) { | |
1439 st->print("movl %s, %s\t# spill", | |
1440 Matcher::regName[dst_first], | |
1441 Matcher::regName[src_first]); | |
1442 #endif | |
1443 } | |
1444 return | |
1445 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
1446 ? 2 | |
1447 : 3; // REX | |
1448 } | |
1449 } else if (dst_first_rc == rc_float) { | |
1450 // gpr -> xmm | |
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1453 // 64-bit | |
1454 if (cbuf) { | |
1455 emit_opcode(*cbuf, 0x66); | |
1456 if (Matcher::_regEncode[dst_first] < 8) { | |
1457 if (Matcher::_regEncode[src_first] < 8) { | |
1458 emit_opcode(*cbuf, Assembler::REX_W); | |
1459 } else { | |
1460 emit_opcode(*cbuf, Assembler::REX_WB); | |
1461 } | |
1462 } else { | |
1463 if (Matcher::_regEncode[src_first] < 8) { | |
1464 emit_opcode(*cbuf, Assembler::REX_WR); | |
1465 } else { | |
1466 emit_opcode(*cbuf, Assembler::REX_WRB); | |
1467 } | |
1468 } | |
1469 emit_opcode(*cbuf, 0x0F); | |
1470 emit_opcode(*cbuf, 0x6E); | |
1471 emit_rm(*cbuf, 0x3, | |
1472 Matcher::_regEncode[dst_first] & 7, | |
1473 Matcher::_regEncode[src_first] & 7); | |
1474 #ifndef PRODUCT | |
1475 } else if (!do_size) { | |
1476 st->print("movdq %s, %s\t# spill", | |
1477 Matcher::regName[dst_first], | |
1478 Matcher::regName[src_first]); | |
1479 #endif | |
1480 } | |
1481 return 5; // REX | |
1482 } else { | |
1483 // 32-bit | |
1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1486 if (cbuf) { | |
1487 emit_opcode(*cbuf, 0x66); | |
1488 if (Matcher::_regEncode[dst_first] < 8) { | |
1489 if (Matcher::_regEncode[src_first] >= 8) { | |
1490 emit_opcode(*cbuf, Assembler::REX_B); | |
1491 } | |
1492 } else { | |
1493 if (Matcher::_regEncode[src_first] < 8) { | |
1494 emit_opcode(*cbuf, Assembler::REX_R); | |
1495 } else { | |
1496 emit_opcode(*cbuf, Assembler::REX_RB); | |
1497 } | |
1498 } | |
1499 emit_opcode(*cbuf, 0x0F); | |
1500 emit_opcode(*cbuf, 0x6E); | |
1501 emit_rm(*cbuf, 0x3, | |
1502 Matcher::_regEncode[dst_first] & 7, | |
1503 Matcher::_regEncode[src_first] & 7); | |
1504 #ifndef PRODUCT | |
1505 } else if (!do_size) { | |
1506 st->print("movdl %s, %s\t# spill", | |
1507 Matcher::regName[dst_first], | |
1508 Matcher::regName[src_first]); | |
1509 #endif | |
1510 } | |
1511 return | |
1512 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
1513 ? 4 | |
1514 : 5; // REX | |
1515 } | |
1516 } | |
1517 } else if (src_first_rc == rc_float) { | |
1518 // xmm -> | |
1519 if (dst_first_rc == rc_stack) { | |
1520 // xmm -> mem | |
1521 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1522 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1523 // 64-bit | |
1524 int offset = ra_->reg2offset(dst_first); | |
1525 if (cbuf) { | |
1526 emit_opcode(*cbuf, 0xF2); | |
1527 if (Matcher::_regEncode[src_first] >= 8) { | |
1528 emit_opcode(*cbuf, Assembler::REX_R); | |
1529 } | |
1530 emit_opcode(*cbuf, 0x0F); | |
1531 emit_opcode(*cbuf, 0x11); | |
1532 encode_RegMem(*cbuf, | |
1533 Matcher::_regEncode[src_first], | |
1534 RSP_enc, 0x4, 0, offset, | |
1535 false); | |
1536 #ifndef PRODUCT | |
1537 } else if (!do_size) { | |
1538 st->print("movsd [rsp + #%d], %s\t# spill", | |
1539 offset, | |
1540 Matcher::regName[src_first]); | |
1541 #endif | |
1542 } | |
1543 return | |
1544 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1545 ((Matcher::_regEncode[src_first] < 8) | |
1546 ? 5 | |
1547 : 6); // REX | |
1548 } else { | |
1549 // 32-bit | |
1550 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1551 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1552 int offset = ra_->reg2offset(dst_first); | |
1553 if (cbuf) { | |
1554 emit_opcode(*cbuf, 0xF3); | |
1555 if (Matcher::_regEncode[src_first] >= 8) { | |
1556 emit_opcode(*cbuf, Assembler::REX_R); | |
1557 } | |
1558 emit_opcode(*cbuf, 0x0F); | |
1559 emit_opcode(*cbuf, 0x11); | |
1560 encode_RegMem(*cbuf, | |
1561 Matcher::_regEncode[src_first], | |
1562 RSP_enc, 0x4, 0, offset, | |
1563 false); | |
1564 #ifndef PRODUCT | |
1565 } else if (!do_size) { | |
1566 st->print("movss [rsp + #%d], %s\t# spill", | |
1567 offset, | |
1568 Matcher::regName[src_first]); | |
1569 #endif | |
1570 } | |
1571 return | |
1572 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
1573 ((Matcher::_regEncode[src_first] < 8) | |
1574 ? 5 | |
1575 : 6); // REX | |
1576 } | |
1577 } else if (dst_first_rc == rc_int) { | |
1578 // xmm -> gpr | |
1579 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1580 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1581 // 64-bit | |
1582 if (cbuf) { | |
1583 emit_opcode(*cbuf, 0x66); | |
1584 if (Matcher::_regEncode[dst_first] < 8) { | |
1585 if (Matcher::_regEncode[src_first] < 8) { | |
1586 emit_opcode(*cbuf, Assembler::REX_W); | |
1587 } else { | |
1588 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
1589 } | |
1590 } else { | |
1591 if (Matcher::_regEncode[src_first] < 8) { | |
1592 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
1593 } else { | |
1594 emit_opcode(*cbuf, Assembler::REX_WRB); | |
1595 } | |
1596 } | |
1597 emit_opcode(*cbuf, 0x0F); | |
1598 emit_opcode(*cbuf, 0x7E); | |
1599 emit_rm(*cbuf, 0x3, | |
1600 Matcher::_regEncode[dst_first] & 7, | |
1601 Matcher::_regEncode[src_first] & 7); | |
1602 #ifndef PRODUCT | |
1603 } else if (!do_size) { | |
1604 st->print("movdq %s, %s\t# spill", | |
1605 Matcher::regName[dst_first], | |
1606 Matcher::regName[src_first]); | |
1607 #endif | |
1608 } | |
1609 return 5; // REX | |
1610 } else { | |
1611 // 32-bit | |
1612 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1613 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1614 if (cbuf) { | |
1615 emit_opcode(*cbuf, 0x66); | |
1616 if (Matcher::_regEncode[dst_first] < 8) { | |
1617 if (Matcher::_regEncode[src_first] >= 8) { | |
1618 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
1619 } | |
1620 } else { | |
1621 if (Matcher::_regEncode[src_first] < 8) { | |
1622 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
1623 } else { | |
1624 emit_opcode(*cbuf, Assembler::REX_RB); | |
1625 } | |
1626 } | |
1627 emit_opcode(*cbuf, 0x0F); | |
1628 emit_opcode(*cbuf, 0x7E); | |
1629 emit_rm(*cbuf, 0x3, | |
1630 Matcher::_regEncode[dst_first] & 7, | |
1631 Matcher::_regEncode[src_first] & 7); | |
1632 #ifndef PRODUCT | |
1633 } else if (!do_size) { | |
1634 st->print("movdl %s, %s\t# spill", | |
1635 Matcher::regName[dst_first], | |
1636 Matcher::regName[src_first]); | |
1637 #endif | |
1638 } | |
1639 return | |
1640 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
1641 ? 4 | |
1642 : 5; // REX | |
1643 } | |
1644 } else if (dst_first_rc == rc_float) { | |
1645 // xmm -> xmm | |
1646 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
1647 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
1648 // 64-bit | |
1649 if (cbuf) { | |
1650 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
1651 if (Matcher::_regEncode[dst_first] < 8) { | |
1652 if (Matcher::_regEncode[src_first] >= 8) { | |
1653 emit_opcode(*cbuf, Assembler::REX_B); | |
1654 } | |
1655 } else { | |
1656 if (Matcher::_regEncode[src_first] < 8) { | |
1657 emit_opcode(*cbuf, Assembler::REX_R); | |
1658 } else { | |
1659 emit_opcode(*cbuf, Assembler::REX_RB); | |
1660 } | |
1661 } | |
1662 emit_opcode(*cbuf, 0x0F); | |
1663 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
1664 emit_rm(*cbuf, 0x3, | |
1665 Matcher::_regEncode[dst_first] & 7, | |
1666 Matcher::_regEncode[src_first] & 7); | |
1667 #ifndef PRODUCT | |
1668 } else if (!do_size) { | |
1669 st->print("%s %s, %s\t# spill", | |
1670 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
1671 Matcher::regName[dst_first], | |
1672 Matcher::regName[src_first]); | |
1673 #endif | |
1674 } | |
1675 return | |
1676 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
1677 ? 4 | |
1678 : 5; // REX | |
1679 } else { | |
1680 // 32-bit | |
1681 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
1682 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
1683 if (cbuf) { | |
1684 if (!UseXmmRegToRegMoveAll) | |
1685 emit_opcode(*cbuf, 0xF3); | |
1686 if (Matcher::_regEncode[dst_first] < 8) { | |
1687 if (Matcher::_regEncode[src_first] >= 8) { | |
1688 emit_opcode(*cbuf, Assembler::REX_B); | |
1689 } | |
1690 } else { | |
1691 if (Matcher::_regEncode[src_first] < 8) { | |
1692 emit_opcode(*cbuf, Assembler::REX_R); | |
1693 } else { | |
1694 emit_opcode(*cbuf, Assembler::REX_RB); | |
1695 } | |
1696 } | |
1697 emit_opcode(*cbuf, 0x0F); | |
1698 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
1699 emit_rm(*cbuf, 0x3, | |
1700 Matcher::_regEncode[dst_first] & 7, | |
1701 Matcher::_regEncode[src_first] & 7); | |
1702 #ifndef PRODUCT | |
1703 } else if (!do_size) { | |
1704 st->print("%s %s, %s\t# spill", | |
1705 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
1706 Matcher::regName[dst_first], | |
1707 Matcher::regName[src_first]); | |
1708 #endif | |
1709 } | |
1710 return | |
1711 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
1712 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
1713 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | |
1714 } | |
1715 } | |
1716 } | |
1717 | |
1718 assert(0," foo "); | |
1719 Unimplemented(); | |
1720 | |
1721 return 0; | |
1722 } | |
1723 | |
1724 #ifndef PRODUCT | |
1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
1726 { | |
1727 implementation(NULL, ra_, false, st); | |
1728 } | |
1729 #endif | |
1730 | |
1731 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
1732 { | |
1733 implementation(&cbuf, ra_, false, NULL); | |
1734 } | |
1735 | |
1736 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
1737 { | |
1738 return implementation(NULL, ra_, true, NULL); | |
1739 } | |
1740 | |
1741 //============================================================================= | |
1742 #ifndef PRODUCT | |
1743 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
1744 { | |
1745 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
1746 } | |
1747 #endif | |
1748 | |
1749 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
1750 { | |
1751 MacroAssembler _masm(&cbuf); | |
1752 __ nop(_count); | |
1753 } | |
1754 | |
1755 uint MachNopNode::size(PhaseRegAlloc*) const | |
1756 { | |
1757 return _count; | |
1758 } | |
1759 | |
1760 | |
1761 //============================================================================= | |
1762 #ifndef PRODUCT | |
1763 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
1764 { | |
1765 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1766 int reg = ra_->get_reg_first(this); | |
1767 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
1768 Matcher::regName[reg], offset); | |
1769 } | |
1770 #endif | |
1771 | |
1772 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
1773 { | |
1774 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1775 int reg = ra_->get_encode(this); | |
1776 if (offset >= 0x80) { | |
1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
1779 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
1781 emit_d32(cbuf, offset); | |
1782 } else { | |
1783 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
1784 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
1785 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
1786 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
1787 emit_d8(cbuf, offset); | |
1788 } | |
1789 } | |
1790 | |
1791 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
1792 { | |
1793 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1794 return (offset < 0x80) ? 5 : 8; // REX | |
1795 } | |
1796 | |
1797 //============================================================================= | |
1798 | |
1799 // emit call stub, compiled java to interpreter | |
1800 void emit_java_to_interp(CodeBuffer& cbuf) | |
1801 { | |
1802 // Stub is fixed up when the corresponding call is converted from | |
1803 // calling compiled code to calling interpreted code. | |
1804 // movq rbx, 0 | |
1805 // jmp -5 # to self | |
1806 | |
1807 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
1808 | |
1809 // Note that the code buffer's inst_mark is always relative to insts. | |
1810 // That's why we must use the macroassembler to generate a stub. | |
1811 MacroAssembler _masm(&cbuf); | |
1812 | |
1813 address base = | |
1814 __ start_a_stub(Compile::MAX_stubs_size); | |
1815 if (base == NULL) return; // CodeBuffer::expand failed | |
1816 // static stub relocation stores the instruction address of the call | |
1817 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
1818 // static stub relocation also tags the methodOop in the code-stream. | |
1819 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
1820 __ jump(RuntimeAddress(__ pc())); | |
1821 | |
1822 // Update current stubs pointer and restore code_end. | |
1823 __ end_a_stub(); | |
1824 } | |
1825 | |
1826 // size of call stub, compiled java to interpretor | |
1827 uint size_java_to_interp() | |
1828 { | |
1829 return 15; // movq (1+1+8); jmp (1+4) | |
1830 } | |
1831 | |
1832 // relocation entries for call stub, compiled java to interpretor | |
1833 uint reloc_java_to_interp() | |
1834 { | |
1835 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
1836 } | |
1837 | |
1838 //============================================================================= | |
1839 #ifndef PRODUCT | |
1840 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
1841 { | |
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1842 if (UseCompressedOops) { |
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1843 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes()); |
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1844 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]"); |
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1845 st->print_cr("cmpq rax, rscratch1\t # Inline cache check"); |
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1846 } else { |
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1847 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t" |
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1848 "# Inline cache check", oopDesc::klass_offset_in_bytes()); |
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1849 } |
0 | 1850 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
1851 st->print_cr("\tnop"); | |
1852 if (!OptoBreakpoint) { | |
1853 st->print_cr("\tnop"); | |
1854 } | |
1855 } | |
1856 #endif | |
1857 | |
1858 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
1859 { | |
1860 MacroAssembler masm(&cbuf); | |
1861 #ifdef ASSERT | |
1862 uint code_size = cbuf.code_size(); | |
1863 #endif | |
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1864 if (UseCompressedOops) { |
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1865 masm.load_klass(rscratch1, j_rarg0); |
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1866 masm.cmpq(rax, rscratch1); |
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1867 } else { |
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1868 masm.cmpq(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1869 } |
0 | 1870 |
1871 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
1872 | |
1873 /* WARNING these NOPs are critical so that verified entry point is properly | |
1874 aligned for patching by NativeJump::patch_verified_entry() */ | |
1875 int nops_cnt = 1; | |
1876 if (!OptoBreakpoint) { | |
1877 // Leave space for int3 | |
1878 nops_cnt += 1; | |
1879 } | |
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1880 if (UseCompressedOops) { |
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1881 // ??? divisible by 4 is aligned? |
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1882 nops_cnt += 1; |
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1883 } |
0 | 1884 masm.nop(nops_cnt); |
1885 | |
1886 assert(cbuf.code_size() - code_size == size(ra_), | |
1887 "checking code size of inline cache node"); | |
1888 } | |
1889 | |
1890 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
1891 { | |
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1892 if (UseCompressedOops) { |
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1893 return OptoBreakpoint ? 19 : 20; |
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1894 } else { |
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1895 return OptoBreakpoint ? 11 : 12; |
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1896 } |
0 | 1897 } |
1898 | |
1899 | |
1900 //============================================================================= | |
1901 uint size_exception_handler() | |
1902 { | |
1903 // NativeCall instruction size is the same as NativeJump. | |
1904 // Note that this value is also credited (in output.cpp) to | |
1905 // the size of the code section. | |
1906 return NativeJump::instruction_size; | |
1907 } | |
1908 | |
1909 // Emit exception handler code. | |
1910 int emit_exception_handler(CodeBuffer& cbuf) | |
1911 { | |
1912 | |
1913 // Note that the code buffer's inst_mark is always relative to insts. | |
1914 // That's why we must use the macroassembler to generate a handler. | |
1915 MacroAssembler _masm(&cbuf); | |
1916 address base = | |
1917 __ start_a_stub(size_exception_handler()); | |
1918 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1919 int offset = __ offset(); | |
1920 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); | |
1921 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1922 __ end_a_stub(); | |
1923 return offset; | |
1924 } | |
1925 | |
1926 uint size_deopt_handler() | |
1927 { | |
1928 // three 5 byte instructions | |
1929 return 15; | |
1930 } | |
1931 | |
1932 // Emit deopt handler code. | |
1933 int emit_deopt_handler(CodeBuffer& cbuf) | |
1934 { | |
1935 | |
1936 // Note that the code buffer's inst_mark is always relative to insts. | |
1937 // That's why we must use the macroassembler to generate a handler. | |
1938 MacroAssembler _masm(&cbuf); | |
1939 address base = | |
1940 __ start_a_stub(size_deopt_handler()); | |
1941 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1942 int offset = __ offset(); | |
1943 address the_pc = (address) __ pc(); | |
1944 Label next; | |
1945 // push a "the_pc" on the stack without destroying any registers | |
1946 // as they all may be live. | |
1947 | |
1948 // push address of "next" | |
1949 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
1950 __ bind(next); | |
1951 // adjust it so it matches "the_pc" | |
1952 __ subq(Address(rsp, 0), __ offset() - offset); | |
1953 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
1954 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1955 __ end_a_stub(); | |
1956 return offset; | |
1957 } | |
1958 | |
1959 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
1960 int mark = cbuf.insts()->mark_off(); | |
1961 MacroAssembler _masm(&cbuf); | |
1962 address double_address = __ double_constant(x); | |
1963 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
1964 emit_d32_reloc(cbuf, | |
1965 (int) (double_address - cbuf.code_end() - 4), | |
1966 internal_word_Relocation::spec(double_address), | |
1967 RELOC_DISP32); | |
1968 } | |
1969 | |
1970 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
1971 int mark = cbuf.insts()->mark_off(); | |
1972 MacroAssembler _masm(&cbuf); | |
1973 address float_address = __ float_constant(x); | |
1974 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
1975 emit_d32_reloc(cbuf, | |
1976 (int) (float_address - cbuf.code_end() - 4), | |
1977 internal_word_Relocation::spec(float_address), | |
1978 RELOC_DISP32); | |
1979 } | |
1980 | |
1981 | |
1982 int Matcher::regnum_to_fpu_offset(int regnum) | |
1983 { | |
1984 return regnum - 32; // The FP registers are in the second chunk | |
1985 } | |
1986 | |
1987 // This is UltraSparc specific, true just means we have fast l2f conversion | |
1988 const bool Matcher::convL2FSupported(void) { | |
1989 return true; | |
1990 } | |
1991 | |
1992 // Vector width in bytes | |
1993 const uint Matcher::vector_width_in_bytes(void) { | |
1994 return 8; | |
1995 } | |
1996 | |
1997 // Vector ideal reg | |
1998 const uint Matcher::vector_ideal_reg(void) { | |
1999 return Op_RegD; | |
2000 } | |
2001 | |
2002 // Is this branch offset short enough that a short branch can be used? | |
2003 // | |
2004 // NOTE: If the platform does not provide any short branch variants, then | |
2005 // this method should return false for offset 0. | |
2006 bool Matcher::is_short_branch_offset(int offset) | |
2007 { | |
2008 return -0x80 <= offset && offset < 0x80; | |
2009 } | |
2010 | |
2011 const bool Matcher::isSimpleConstant64(jlong value) { | |
2012 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
2013 //return value == (int) value; // Cf. storeImmL and immL32. | |
2014 | |
2015 // Probably always true, even if a temp register is required. | |
2016 return true; | |
2017 } | |
2018 | |
2019 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
2020 const bool Matcher::init_array_count_is_in_bytes = false; | |
2021 | |
2022 // Threshold size for cleararray. | |
2023 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
2024 | |
2025 // Should the Matcher clone shifts on addressing modes, expecting them | |
2026 // to be subsumed into complex addressing expressions or compute them | |
2027 // into registers? True for Intel but false for most RISCs | |
2028 const bool Matcher::clone_shift_expressions = true; | |
2029 | |
2030 // Is it better to copy float constants, or load them directly from | |
2031 // memory? Intel can load a float constant from a direct address, | |
2032 // requiring no extra registers. Most RISCs will have to materialize | |
2033 // an address into a register first, so they would do better to copy | |
2034 // the constant from stack. | |
2035 const bool Matcher::rematerialize_float_constants = true; // XXX | |
2036 | |
2037 // If CPU can load and store mis-aligned doubles directly then no | |
2038 // fixup is needed. Else we split the double into 2 integer pieces | |
2039 // and move it piece-by-piece. Only happens when passing doubles into | |
2040 // C code as the Java calling convention forces doubles to be aligned. | |
2041 const bool Matcher::misaligned_doubles_ok = true; | |
2042 | |
2043 // No-op on amd64 | |
2044 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
2045 | |
2046 // Advertise here if the CPU requires explicit rounding operations to | |
2047 // implement the UseStrictFP mode. | |
2048 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
2049 | |
2050 // Do floats take an entire double register or just half? | |
2051 const bool Matcher::float_in_double = true; | |
2052 // Do ints take an entire long register or just half? | |
2053 const bool Matcher::int_in_long = true; | |
2054 | |
2055 // Return whether or not this register is ever used as an argument. | |
2056 // This function is used on startup to build the trampoline stubs in | |
2057 // generateOptoStub. Registers not mentioned will be killed by the VM | |
2058 // call in the trampoline, and arguments in those registers not be | |
2059 // available to the callee. | |
2060 bool Matcher::can_be_java_arg(int reg) | |
2061 { | |
2062 return | |
2063 reg == RDI_num || reg == RDI_H_num || | |
2064 reg == RSI_num || reg == RSI_H_num || | |
2065 reg == RDX_num || reg == RDX_H_num || | |
2066 reg == RCX_num || reg == RCX_H_num || | |
2067 reg == R8_num || reg == R8_H_num || | |
2068 reg == R9_num || reg == R9_H_num || | |
113
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2069 reg == R12_num || reg == R12_H_num || |
0 | 2070 reg == XMM0_num || reg == XMM0_H_num || |
2071 reg == XMM1_num || reg == XMM1_H_num || | |
2072 reg == XMM2_num || reg == XMM2_H_num || | |
2073 reg == XMM3_num || reg == XMM3_H_num || | |
2074 reg == XMM4_num || reg == XMM4_H_num || | |
2075 reg == XMM5_num || reg == XMM5_H_num || | |
2076 reg == XMM6_num || reg == XMM6_H_num || | |
2077 reg == XMM7_num || reg == XMM7_H_num; | |
2078 } | |
2079 | |
2080 bool Matcher::is_spillable_arg(int reg) | |
2081 { | |
2082 return can_be_java_arg(reg); | |
2083 } | |
2084 | |
2085 // Register for DIVI projection of divmodI | |
2086 RegMask Matcher::divI_proj_mask() { | |
2087 return INT_RAX_REG_mask; | |
2088 } | |
2089 | |
2090 // Register for MODI projection of divmodI | |
2091 RegMask Matcher::modI_proj_mask() { | |
2092 return INT_RDX_REG_mask; | |
2093 } | |
2094 | |
2095 // Register for DIVL projection of divmodL | |
2096 RegMask Matcher::divL_proj_mask() { | |
2097 return LONG_RAX_REG_mask; | |
2098 } | |
2099 | |
2100 // Register for MODL projection of divmodL | |
2101 RegMask Matcher::modL_proj_mask() { | |
2102 return LONG_RDX_REG_mask; | |
2103 } | |
2104 | |
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2105 static Address build_address(int b, int i, int s, int d) { |
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2106 Register index = as_Register(i); |
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2107 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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2108 if (index == rsp) { |
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2109 index = noreg; |
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2110 scale = Address::no_scale; |
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2111 } |
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2112 Address addr(as_Register(b), index, scale, d); |
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2113 return addr; |
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2114 } |
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2115 |
0 | 2116 %} |
2117 | |
2118 //----------ENCODING BLOCK----------------------------------------------------- | |
2119 // This block specifies the encoding classes used by the compiler to | |
2120 // output byte streams. Encoding classes are parameterized macros | |
2121 // used by Machine Instruction Nodes in order to generate the bit | |
2122 // encoding of the instruction. Operands specify their base encoding | |
2123 // interface with the interface keyword. There are currently | |
2124 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
2125 // COND_INTER. REG_INTER causes an operand to generate a function | |
2126 // which returns its register number when queried. CONST_INTER causes | |
2127 // an operand to generate a function which returns the value of the | |
2128 // constant when queried. MEMORY_INTER causes an operand to generate | |
2129 // four functions which return the Base Register, the Index Register, | |
2130 // the Scale Value, and the Offset Value of the operand when queried. | |
2131 // COND_INTER causes an operand to generate six functions which return | |
2132 // the encoding code (ie - encoding bits for the instruction) | |
2133 // associated with each basic boolean condition for a conditional | |
2134 // instruction. | |
2135 // | |
2136 // Instructions specify two basic values for encoding. Again, a | |
2137 // function is available to check if the constant displacement is an | |
2138 // oop. They use the ins_encode keyword to specify their encoding | |
2139 // classes (which must be a sequence of enc_class names, and their | |
2140 // parameters, specified in the encoding block), and they use the | |
2141 // opcode keyword to specify, in order, their primary, secondary, and | |
2142 // tertiary opcode. Only the opcode sections which a particular | |
2143 // instruction needs for encoding need to be specified. | |
2144 encode %{ | |
2145 // Build emit functions for each basic byte or larger field in the | |
2146 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
2147 // from C++ code in the enc_class source block. Emit functions will | |
2148 // live in the main source block for now. In future, we can | |
2149 // generalize this by adding a syntax that specifies the sizes of | |
2150 // fields in an order, so that the adlc can build the emit functions | |
2151 // automagically | |
2152 | |
2153 // Emit primary opcode | |
2154 enc_class OpcP | |
2155 %{ | |
2156 emit_opcode(cbuf, $primary); | |
2157 %} | |
2158 | |
2159 // Emit secondary opcode | |
2160 enc_class OpcS | |
2161 %{ | |
2162 emit_opcode(cbuf, $secondary); | |
2163 %} | |
2164 | |
2165 // Emit tertiary opcode | |
2166 enc_class OpcT | |
2167 %{ | |
2168 emit_opcode(cbuf, $tertiary); | |
2169 %} | |
2170 | |
2171 // Emit opcode directly | |
2172 enc_class Opcode(immI d8) | |
2173 %{ | |
2174 emit_opcode(cbuf, $d8$$constant); | |
2175 %} | |
2176 | |
2177 // Emit size prefix | |
2178 enc_class SizePrefix | |
2179 %{ | |
2180 emit_opcode(cbuf, 0x66); | |
2181 %} | |
2182 | |
2183 enc_class reg(rRegI reg) | |
2184 %{ | |
2185 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
2186 %} | |
2187 | |
2188 enc_class reg_reg(rRegI dst, rRegI src) | |
2189 %{ | |
2190 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2191 %} | |
2192 | |
2193 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
2194 %{ | |
2195 emit_opcode(cbuf, $opcode$$constant); | |
2196 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2197 %} | |
2198 | |
2199 enc_class cmpfp_fixup() | |
2200 %{ | |
2201 // jnp,s exit | |
2202 emit_opcode(cbuf, 0x7B); | |
2203 emit_d8(cbuf, 0x0A); | |
2204 | |
2205 // pushfq | |
2206 emit_opcode(cbuf, 0x9C); | |
2207 | |
2208 // andq $0xffffff2b, (%rsp) | |
2209 emit_opcode(cbuf, Assembler::REX_W); | |
2210 emit_opcode(cbuf, 0x81); | |
2211 emit_opcode(cbuf, 0x24); | |
2212 emit_opcode(cbuf, 0x24); | |
2213 emit_d32(cbuf, 0xffffff2b); | |
2214 | |
2215 // popfq | |
2216 emit_opcode(cbuf, 0x9D); | |
2217 | |
2218 // nop (target for branch to avoid branch to branch) | |
2219 emit_opcode(cbuf, 0x90); | |
2220 %} | |
2221 | |
2222 enc_class cmpfp3(rRegI dst) | |
2223 %{ | |
2224 int dstenc = $dst$$reg; | |
2225 | |
2226 // movl $dst, -1 | |
2227 if (dstenc >= 8) { | |
2228 emit_opcode(cbuf, Assembler::REX_B); | |
2229 } | |
2230 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
2231 emit_d32(cbuf, -1); | |
2232 | |
2233 // jp,s done | |
2234 emit_opcode(cbuf, 0x7A); | |
2235 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
2236 | |
2237 // jb,s done | |
2238 emit_opcode(cbuf, 0x72); | |
2239 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
2240 | |
2241 // setne $dst | |
2242 if (dstenc >= 4) { | |
2243 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
2244 } | |
2245 emit_opcode(cbuf, 0x0F); | |
2246 emit_opcode(cbuf, 0x95); | |
2247 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
2248 | |
2249 // movzbl $dst, $dst | |
2250 if (dstenc >= 4) { | |
2251 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
2252 } | |
2253 emit_opcode(cbuf, 0x0F); | |
2254 emit_opcode(cbuf, 0xB6); | |
2255 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
2256 %} | |
2257 | |
2258 enc_class cdql_enc(no_rax_rdx_RegI div) | |
2259 %{ | |
2260 // Full implementation of Java idiv and irem; checks for | |
2261 // special case as described in JVM spec., p.243 & p.271. | |
2262 // | |
2263 // normal case special case | |
2264 // | |
2265 // input : rax: dividend min_int | |
2266 // reg: divisor -1 | |
2267 // | |
2268 // output: rax: quotient (= rax idiv reg) min_int | |
2269 // rdx: remainder (= rax irem reg) 0 | |
2270 // | |
2271 // Code sequnce: | |
2272 // | |
2273 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
2274 // 5: 75 07/08 jne e <normal> | |
2275 // 7: 33 d2 xor %edx,%edx | |
2276 // [div >= 8 -> offset + 1] | |
2277 // [REX_B] | |
2278 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
2279 // c: 74 03/04 je 11 <done> | |
2280 // 000000000000000e <normal>: | |
2281 // e: 99 cltd | |
2282 // [div >= 8 -> offset + 1] | |
2283 // [REX_B] | |
2284 // f: f7 f9 idiv $div | |
2285 // 0000000000000011 <done>: | |
2286 | |
2287 // cmp $0x80000000,%eax | |
2288 emit_opcode(cbuf, 0x3d); | |
2289 emit_d8(cbuf, 0x00); | |
2290 emit_d8(cbuf, 0x00); | |
2291 emit_d8(cbuf, 0x00); | |
2292 emit_d8(cbuf, 0x80); | |
2293 | |
2294 // jne e <normal> | |
2295 emit_opcode(cbuf, 0x75); | |
2296 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
2297 | |
2298 // xor %edx,%edx | |
2299 emit_opcode(cbuf, 0x33); | |
2300 emit_d8(cbuf, 0xD2); | |
2301 | |
2302 // cmp $0xffffffffffffffff,%ecx | |
2303 if ($div$$reg >= 8) { | |
2304 emit_opcode(cbuf, Assembler::REX_B); | |
2305 } | |
2306 emit_opcode(cbuf, 0x83); | |
2307 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
2308 emit_d8(cbuf, 0xFF); | |
2309 | |
2310 // je 11 <done> | |
2311 emit_opcode(cbuf, 0x74); | |
2312 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
2313 | |
2314 // <normal> | |
2315 // cltd | |
2316 emit_opcode(cbuf, 0x99); | |
2317 | |
2318 // idivl (note: must be emitted by the user of this rule) | |
2319 // <done> | |
2320 %} | |
2321 | |
2322 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
2323 %{ | |
2324 // Full implementation of Java ldiv and lrem; checks for | |
2325 // special case as described in JVM spec., p.243 & p.271. | |
2326 // | |
2327 // normal case special case | |
2328 // | |
2329 // input : rax: dividend min_long | |
2330 // reg: divisor -1 | |
2331 // | |
2332 // output: rax: quotient (= rax idiv reg) min_long | |
2333 // rdx: remainder (= rax irem reg) 0 | |
2334 // | |
2335 // Code sequnce: | |
2336 // | |
2337 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
2338 // 7: 00 00 80 | |
2339 // a: 48 39 d0 cmp %rdx,%rax | |
2340 // d: 75 08 jne 17 <normal> | |
2341 // f: 33 d2 xor %edx,%edx | |
2342 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
2343 // 15: 74 05 je 1c <done> | |
2344 // 0000000000000017 <normal>: | |
2345 // 17: 48 99 cqto | |
2346 // 19: 48 f7 f9 idiv $div | |
2347 // 000000000000001c <done>: | |
2348 | |
2349 // mov $0x8000000000000000,%rdx | |
2350 emit_opcode(cbuf, Assembler::REX_W); | |
2351 emit_opcode(cbuf, 0xBA); | |
2352 emit_d8(cbuf, 0x00); | |
2353 emit_d8(cbuf, 0x00); | |
2354 emit_d8(cbuf, 0x00); | |
2355 emit_d8(cbuf, 0x00); | |
2356 emit_d8(cbuf, 0x00); | |
2357 emit_d8(cbuf, 0x00); | |
2358 emit_d8(cbuf, 0x00); | |
2359 emit_d8(cbuf, 0x80); | |
2360 | |
2361 // cmp %rdx,%rax | |
2362 emit_opcode(cbuf, Assembler::REX_W); | |
2363 emit_opcode(cbuf, 0x39); | |
2364 emit_d8(cbuf, 0xD0); | |
2365 | |
2366 // jne 17 <normal> | |
2367 emit_opcode(cbuf, 0x75); | |
2368 emit_d8(cbuf, 0x08); | |
2369 | |
2370 // xor %edx,%edx | |
2371 emit_opcode(cbuf, 0x33); | |
2372 emit_d8(cbuf, 0xD2); | |
2373 | |
2374 // cmp $0xffffffffffffffff,$div | |
2375 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
2376 emit_opcode(cbuf, 0x83); | |
2377 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
2378 emit_d8(cbuf, 0xFF); | |
2379 | |
2380 // je 1e <done> | |
2381 emit_opcode(cbuf, 0x74); | |
2382 emit_d8(cbuf, 0x05); | |
2383 | |
2384 // <normal> | |
2385 // cqto | |
2386 emit_opcode(cbuf, Assembler::REX_W); | |
2387 emit_opcode(cbuf, 0x99); | |
2388 | |
2389 // idivq (note: must be emitted by the user of this rule) | |
2390 // <done> | |
2391 %} | |
2392 | |
2393 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
2394 enc_class OpcSE(immI imm) | |
2395 %{ | |
2396 // Emit primary opcode and set sign-extend bit | |
2397 // Check for 8-bit immediate, and set sign extend bit in opcode | |
2398 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
2399 emit_opcode(cbuf, $primary | 0x02); | |
2400 } else { | |
2401 // 32-bit immediate | |
2402 emit_opcode(cbuf, $primary); | |
2403 } | |
2404 %} | |
2405 | |
2406 enc_class OpcSErm(rRegI dst, immI imm) | |
2407 %{ | |
2408 // OpcSEr/m | |
2409 int dstenc = $dst$$reg; | |
2410 if (dstenc >= 8) { | |
2411 emit_opcode(cbuf, Assembler::REX_B); | |
2412 dstenc -= 8; | |
2413 } | |
2414 // Emit primary opcode and set sign-extend bit | |
2415 // Check for 8-bit immediate, and set sign extend bit in opcode | |
2416 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
2417 emit_opcode(cbuf, $primary | 0x02); | |
2418 } else { | |
2419 // 32-bit immediate | |
2420 emit_opcode(cbuf, $primary); | |
2421 } | |
2422 // Emit r/m byte with secondary opcode, after primary opcode. | |
2423 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
2424 %} | |
2425 | |
2426 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
2427 %{ | |
2428 // OpcSEr/m | |
2429 int dstenc = $dst$$reg; | |
2430 if (dstenc < 8) { | |
2431 emit_opcode(cbuf, Assembler::REX_W); | |
2432 } else { | |
2433 emit_opcode(cbuf, Assembler::REX_WB); | |
2434 dstenc -= 8; | |
2435 } | |
2436 // Emit primary opcode and set sign-extend bit | |
2437 // Check for 8-bit immediate, and set sign extend bit in opcode | |
2438 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
2439 emit_opcode(cbuf, $primary | 0x02); | |
2440 } else { | |
2441 // 32-bit immediate | |
2442 emit_opcode(cbuf, $primary); | |
2443 } | |
2444 // Emit r/m byte with secondary opcode, after primary opcode. | |
2445 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
2446 %} | |
2447 | |
2448 enc_class Con8or32(immI imm) | |
2449 %{ | |
2450 // Check for 8-bit immediate, and set sign extend bit in opcode | |
2451 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
2452 $$$emit8$imm$$constant; | |
2453 } else { | |
2454 // 32-bit immediate | |
2455 $$$emit32$imm$$constant; | |
2456 } | |
2457 %} | |
2458 | |
2459 enc_class Lbl(label labl) | |
2460 %{ | |
2461 // JMP, CALL | |
2462 Label* l = $labl$$label; | |
2463 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
2464 %} | |
2465 | |
2466 enc_class LblShort(label labl) | |
2467 %{ | |
2468 // JMP, CALL | |
2469 Label* l = $labl$$label; | |
2470 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
2471 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
2472 emit_d8(cbuf, disp); | |
2473 %} | |
2474 | |
2475 enc_class opc2_reg(rRegI dst) | |
2476 %{ | |
2477 // BSWAP | |
2478 emit_cc(cbuf, $secondary, $dst$$reg); | |
2479 %} | |
2480 | |
2481 enc_class opc3_reg(rRegI dst) | |
2482 %{ | |
2483 // BSWAP | |
2484 emit_cc(cbuf, $tertiary, $dst$$reg); | |
2485 %} | |
2486 | |
2487 enc_class reg_opc(rRegI div) | |
2488 %{ | |
2489 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
2490 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
2491 %} | |
2492 | |
2493 enc_class Jcc(cmpOp cop, label labl) | |
2494 %{ | |
2495 // JCC | |
2496 Label* l = $labl$$label; | |
2497 $$$emit8$primary; | |
2498 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
2499 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
2500 %} | |
2501 | |
2502 enc_class JccShort (cmpOp cop, label labl) | |
2503 %{ | |
2504 // JCC | |
2505 Label *l = $labl$$label; | |
2506 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
2507 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
2508 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
2509 emit_d8(cbuf, disp); | |
2510 %} | |
2511 | |
2512 enc_class enc_cmov(cmpOp cop) | |
2513 %{ | |
2514 // CMOV | |
2515 $$$emit8$primary; | |
2516 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
2517 %} | |
2518 | |
2519 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
2520 %{ | |
2521 // Invert sense of branch from sense of cmov | |
2522 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
2523 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
2524 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
2525 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
2526 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
2527 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
2528 if ($dst$$reg < 8) { | |
2529 if ($src$$reg >= 8) { | |
2530 emit_opcode(cbuf, Assembler::REX_B); | |
2531 } | |
2532 } else { | |
2533 if ($src$$reg < 8) { | |
2534 emit_opcode(cbuf, Assembler::REX_R); | |
2535 } else { | |
2536 emit_opcode(cbuf, Assembler::REX_RB); | |
2537 } | |
2538 } | |
2539 emit_opcode(cbuf, 0x0F); | |
2540 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
2541 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2542 %} | |
2543 | |
2544 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
2545 %{ | |
2546 // Invert sense of branch from sense of cmov | |
2547 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
2548 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
2549 | |
2550 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
2551 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
2552 if ($dst$$reg < 8) { | |
2553 if ($src$$reg >= 8) { | |
2554 emit_opcode(cbuf, Assembler::REX_B); | |
2555 } | |
2556 } else { | |
2557 if ($src$$reg < 8) { | |
2558 emit_opcode(cbuf, Assembler::REX_R); | |
2559 } else { | |
2560 emit_opcode(cbuf, Assembler::REX_RB); | |
2561 } | |
2562 } | |
2563 emit_opcode(cbuf, 0x0F); | |
2564 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
2565 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
2566 %} | |
2567 | |
2568 enc_class enc_PartialSubtypeCheck() | |
2569 %{ | |
2570 Register Rrdi = as_Register(RDI_enc); // result register | |
2571 Register Rrax = as_Register(RAX_enc); // super class | |
2572 Register Rrcx = as_Register(RCX_enc); // killed | |
2573 Register Rrsi = as_Register(RSI_enc); // sub class | |
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2574 Label hit, miss, cmiss; |
0 | 2575 |
2576 MacroAssembler _masm(&cbuf); | |
2577 // Compare super with sub directly, since super is not in its own SSA. | |
2578 // The compiler used to emit this test, but we fold it in here, | |
2579 // to allow platform-specific tweaking on sparc. | |
2580 __ cmpq(Rrax, Rrsi); | |
2581 __ jcc(Assembler::equal, hit); | |
2582 #ifndef PRODUCT | |
2583 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); | |
2584 __ incrementl(Address(Rrcx, 0)); | |
2585 #endif //PRODUCT | |
2586 __ movq(Rrdi, Address(Rrsi, | |
2587 sizeof(oopDesc) + | |
2588 Klass::secondary_supers_offset_in_bytes())); | |
2589 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes())); | |
2590 __ addq(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); | |
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2591 if (UseCompressedOops) { |
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2592 __ encode_heap_oop(Rrax); |
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2593 __ repne_scanl(); |
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2594 __ jcc(Assembler::notEqual, cmiss); |
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2595 __ decode_heap_oop(Rrax); |
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2596 __ movq(Address(Rrsi, |
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2597 sizeof(oopDesc) + |
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2598 Klass::secondary_super_cache_offset_in_bytes()), |
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2599 Rrax); |
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2600 __ jmp(hit); |
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2601 __ bind(cmiss); |
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2602 __ decode_heap_oop(Rrax); |
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2603 __ jmp(miss); |
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2604 } else { |
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2605 __ repne_scanq(); |
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2606 __ jcc(Assembler::notEqual, miss); |
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2607 __ movq(Address(Rrsi, |
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2608 sizeof(oopDesc) + |
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2609 Klass::secondary_super_cache_offset_in_bytes()), |
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2610 Rrax); |
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2611 } |
0 | 2612 __ bind(hit); |
2613 if ($primary) { | |
2614 __ xorq(Rrdi, Rrdi); | |
2615 } | |
2616 __ bind(miss); | |
2617 %} | |
2618 | |
2619 enc_class Java_To_Interpreter(method meth) | |
2620 %{ | |
2621 // CALL Java_To_Interpreter | |
2622 // This is the instruction starting address for relocation info. | |
2623 cbuf.set_inst_mark(); | |
2624 $$$emit8$primary; | |
2625 // CALL directly to the runtime | |
2626 emit_d32_reloc(cbuf, | |
2627 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
2628 runtime_call_Relocation::spec(), | |
2629 RELOC_DISP32); | |
2630 %} | |
2631 | |
2632 enc_class Java_Static_Call(method meth) | |
2633 %{ | |
2634 // JAVA STATIC CALL | |
2635 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
2636 // determine who we intended to call. | |
2637 cbuf.set_inst_mark(); | |
2638 $$$emit8$primary; | |
2639 | |
2640 if (!_method) { | |
2641 emit_d32_reloc(cbuf, | |
2642 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
2643 runtime_call_Relocation::spec(), | |
2644 RELOC_DISP32); | |
2645 } else if (_optimized_virtual) { | |
2646 emit_d32_reloc(cbuf, | |
2647 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
2648 opt_virtual_call_Relocation::spec(), | |
2649 RELOC_DISP32); | |
2650 } else { | |
2651 emit_d32_reloc(cbuf, | |
2652 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
2653 static_call_Relocation::spec(), | |
2654 RELOC_DISP32); | |
2655 } | |
2656 if (_method) { | |
2657 // Emit stub for static call | |
2658 emit_java_to_interp(cbuf); | |
2659 } | |
2660 %} | |
2661 | |
2662 enc_class Java_Dynamic_Call(method meth) | |
2663 %{ | |
2664 // JAVA DYNAMIC CALL | |
2665 // !!!!! | |
2666 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
2667 // emit_call_dynamic_prologue( cbuf ); | |
2668 cbuf.set_inst_mark(); | |
2669 | |
2670 // movq rax, -1 | |
2671 emit_opcode(cbuf, Assembler::REX_W); | |
2672 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
2673 emit_d64_reloc(cbuf, | |
2674 (int64_t) Universe::non_oop_word(), | |
2675 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
2676 address virtual_call_oop_addr = cbuf.inst_mark(); | |
2677 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2678 // who we intended to call. | |
2679 cbuf.set_inst_mark(); | |
2680 $$$emit8$primary; | |
2681 emit_d32_reloc(cbuf, | |
2682 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
2683 virtual_call_Relocation::spec(virtual_call_oop_addr), | |
2684 RELOC_DISP32); | |
2685 %} | |
2686 | |
2687 enc_class Java_Compiled_Call(method meth) | |
2688 %{ | |
2689 // JAVA COMPILED CALL | |
2690 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
2691 | |
2692 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
2693 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
2694 | |
2695 // callq *disp(%rax) | |
2696 cbuf.set_inst_mark(); | |
2697 $$$emit8$primary; | |
2698 if (disp < 0x80) { | |
2699 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
2700 emit_d8(cbuf, disp); // Displacement | |
2701 } else { | |
2702 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
2703 emit_d32(cbuf, disp); // Displacement | |
2704 } | |
2705 %} | |
2706 | |
2707 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
2708 %{ | |
2709 // SAL, SAR, SHR | |
2710 int dstenc = $dst$$reg; | |
2711 if (dstenc >= 8) { | |
2712 emit_opcode(cbuf, Assembler::REX_B); | |
2713 dstenc -= 8; | |
2714 } | |
2715 $$$emit8$primary; | |
2716 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
2717 $$$emit8$shift$$constant; | |
2718 %} | |
2719 | |
2720 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
2721 %{ | |
2722 // SAL, SAR, SHR | |
2723 int dstenc = $dst$$reg; | |
2724 if (dstenc < 8) { | |
2725 emit_opcode(cbuf, Assembler::REX_W); | |
2726 } else { | |
2727 emit_opcode(cbuf, Assembler::REX_WB); | |
2728 dstenc -= 8; | |
2729 } | |
2730 $$$emit8$primary; | |
2731 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
2732 $$$emit8$shift$$constant; | |
2733 %} | |
2734 | |
2735 enc_class load_immI(rRegI dst, immI src) | |
2736 %{ | |
2737 int dstenc = $dst$$reg; | |
2738 if (dstenc >= 8) { | |
2739 emit_opcode(cbuf, Assembler::REX_B); | |
2740 dstenc -= 8; | |
2741 } | |
2742 emit_opcode(cbuf, 0xB8 | dstenc); | |
2743 $$$emit32$src$$constant; | |
2744 %} | |
2745 | |
2746 enc_class load_immL(rRegL dst, immL src) | |
2747 %{ | |
2748 int dstenc = $dst$$reg; | |
2749 if (dstenc < 8) { | |
2750 emit_opcode(cbuf, Assembler::REX_W); | |
2751 } else { | |
2752 emit_opcode(cbuf, Assembler::REX_WB); | |
2753 dstenc -= 8; | |
2754 } | |
2755 emit_opcode(cbuf, 0xB8 | dstenc); | |
2756 emit_d64(cbuf, $src$$constant); | |
2757 %} | |
2758 | |
2759 enc_class load_immUL32(rRegL dst, immUL32 src) | |
2760 %{ | |
2761 // same as load_immI, but this time we care about zeroes in the high word | |
2762 int dstenc = $dst$$reg; | |
2763 if (dstenc >= 8) { | |
2764 emit_opcode(cbuf, Assembler::REX_B); | |
2765 dstenc -= 8; | |
2766 } | |
2767 emit_opcode(cbuf, 0xB8 | dstenc); | |
2768 $$$emit32$src$$constant; | |
2769 %} | |
2770 | |
2771 enc_class load_immL32(rRegL dst, immL32 src) | |
2772 %{ | |
2773 int dstenc = $dst$$reg; | |
2774 if (dstenc < 8) { | |
2775 emit_opcode(cbuf, Assembler::REX_W); | |
2776 } else { | |
2777 emit_opcode(cbuf, Assembler::REX_WB); | |
2778 dstenc -= 8; | |
2779 } | |
2780 emit_opcode(cbuf, 0xC7); | |
2781 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
2782 $$$emit32$src$$constant; | |
2783 %} | |
2784 | |
2785 enc_class load_immP31(rRegP dst, immP32 src) | |
2786 %{ | |
2787 // same as load_immI, but this time we care about zeroes in the high word | |
2788 int dstenc = $dst$$reg; | |
2789 if (dstenc >= 8) { | |
2790 emit_opcode(cbuf, Assembler::REX_B); | |
2791 dstenc -= 8; | |
2792 } | |
2793 emit_opcode(cbuf, 0xB8 | dstenc); | |
2794 $$$emit32$src$$constant; | |
2795 %} | |
2796 | |
2797 enc_class load_immP(rRegP dst, immP src) | |
2798 %{ | |
2799 int dstenc = $dst$$reg; | |
2800 if (dstenc < 8) { | |
2801 emit_opcode(cbuf, Assembler::REX_W); | |
2802 } else { | |
2803 emit_opcode(cbuf, Assembler::REX_WB); | |
2804 dstenc -= 8; | |
2805 } | |
2806 emit_opcode(cbuf, 0xB8 | dstenc); | |
2807 // This next line should be generated from ADLC | |
2808 if ($src->constant_is_oop()) { | |
2809 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
2810 } else { | |
2811 emit_d64(cbuf, $src$$constant); | |
2812 } | |
2813 %} | |
2814 | |
2815 enc_class load_immF(regF dst, immF con) | |
2816 %{ | |
2817 // XXX reg_mem doesn't support RIP-relative addressing yet | |
2818 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
2819 emit_float_constant(cbuf, $con$$constant); | |
2820 %} | |
2821 | |
2822 enc_class load_immD(regD dst, immD con) | |
2823 %{ | |
2824 // XXX reg_mem doesn't support RIP-relative addressing yet | |
2825 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
2826 emit_double_constant(cbuf, $con$$constant); | |
2827 %} | |
2828 | |
2829 enc_class load_conF (regF dst, immF con) %{ // Load float constant | |
2830 emit_opcode(cbuf, 0xF3); | |
2831 if ($dst$$reg >= 8) { | |
2832 emit_opcode(cbuf, Assembler::REX_R); | |
2833 } | |
2834 emit_opcode(cbuf, 0x0F); | |
2835 emit_opcode(cbuf, 0x10); | |
2836 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
2837 emit_float_constant(cbuf, $con$$constant); | |
2838 %} | |
2839 | |
2840 enc_class load_conD (regD dst, immD con) %{ // Load double constant | |
2841 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
2842 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
2843 if ($dst$$reg >= 8) { | |
2844 emit_opcode(cbuf, Assembler::REX_R); | |
2845 } | |
2846 emit_opcode(cbuf, 0x0F); | |
2847 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
2848 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
2849 emit_double_constant(cbuf, $con$$constant); | |
2850 %} | |
2851 | |
2852 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2853 enc_class enc_copy(rRegI dst, rRegI src) | |
2854 %{ | |
2855 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
2856 %} | |
2857 | |
2858 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
2859 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
2860 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
2861 %} | |
2862 | |
2863 enc_class enc_copy_always(rRegI dst, rRegI src) | |
2864 %{ | |
2865 int srcenc = $src$$reg; | |
2866 int dstenc = $dst$$reg; | |
2867 | |
2868 if (dstenc < 8) { | |
2869 if (srcenc >= 8) { | |
2870 emit_opcode(cbuf, Assembler::REX_B); | |
2871 srcenc -= 8; | |
2872 } | |
2873 } else { | |
2874 if (srcenc < 8) { | |
2875 emit_opcode(cbuf, Assembler::REX_R); | |
2876 } else { | |
2877 emit_opcode(cbuf, Assembler::REX_RB); | |
2878 srcenc -= 8; | |
2879 } | |
2880 dstenc -= 8; | |
2881 } | |
2882 | |
2883 emit_opcode(cbuf, 0x8B); | |
2884 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
2885 %} | |
2886 | |
2887 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
2888 %{ | |
2889 int srcenc = $src$$reg; | |
2890 int dstenc = $dst$$reg; | |
2891 | |
2892 if (dstenc != srcenc) { | |
2893 if (dstenc < 8) { | |
2894 if (srcenc < 8) { | |
2895 emit_opcode(cbuf, Assembler::REX_W); | |
2896 } else { | |
2897 emit_opcode(cbuf, Assembler::REX_WB); | |
2898 srcenc -= 8; | |
2899 } | |
2900 } else { | |
2901 if (srcenc < 8) { | |
2902 emit_opcode(cbuf, Assembler::REX_WR); | |
2903 } else { | |
2904 emit_opcode(cbuf, Assembler::REX_WRB); | |
2905 srcenc -= 8; | |
2906 } | |
2907 dstenc -= 8; | |
2908 } | |
2909 emit_opcode(cbuf, 0x8B); | |
2910 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
2911 } | |
2912 %} | |
2913 | |
2914 enc_class Con32(immI src) | |
2915 %{ | |
2916 // Output immediate | |
2917 $$$emit32$src$$constant; | |
2918 %} | |
2919 | |
2920 enc_class Con64(immL src) | |
2921 %{ | |
2922 // Output immediate | |
2923 emit_d64($src$$constant); | |
2924 %} | |
2925 | |
2926 enc_class Con32F_as_bits(immF src) | |
2927 %{ | |
2928 // Output Float immediate bits | |
2929 jfloat jf = $src$$constant; | |
2930 jint jf_as_bits = jint_cast(jf); | |
2931 emit_d32(cbuf, jf_as_bits); | |
2932 %} | |
2933 | |
2934 enc_class Con16(immI src) | |
2935 %{ | |
2936 // Output immediate | |
2937 $$$emit16$src$$constant; | |
2938 %} | |
2939 | |
2940 // How is this different from Con32??? XXX | |
2941 enc_class Con_d32(immI src) | |
2942 %{ | |
2943 emit_d32(cbuf,$src$$constant); | |
2944 %} | |
2945 | |
2946 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
2947 // Output immediate memory reference | |
2948 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
2949 emit_d32(cbuf, 0x00); | |
2950 %} | |
2951 | |
2952 enc_class jump_enc(rRegL switch_val, rRegI dest) %{ | |
2953 MacroAssembler masm(&cbuf); | |
2954 | |
2955 Register switch_reg = as_Register($switch_val$$reg); | |
2956 Register dest_reg = as_Register($dest$$reg); | |
2957 address table_base = masm.address_table_constant(_index2label); | |
2958 | |
2959 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
2960 // to do that and the compiler is using that register as one it can allocate. | |
2961 // So we build it all by hand. | |
2962 // Address index(noreg, switch_reg, Address::times_1); | |
2963 // ArrayAddress dispatch(table, index); | |
2964 | |
2965 Address dispatch(dest_reg, switch_reg, Address::times_1); | |
2966 | |
2967 masm.lea(dest_reg, InternalAddress(table_base)); | |
2968 masm.jmp(dispatch); | |
2969 %} | |
2970 | |
2971 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
2972 MacroAssembler masm(&cbuf); | |
2973 | |
2974 Register switch_reg = as_Register($switch_val$$reg); | |
2975 Register dest_reg = as_Register($dest$$reg); | |
2976 address table_base = masm.address_table_constant(_index2label); | |
2977 | |
2978 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
2979 // to do that and the compiler is using that register as one it can allocate. | |
2980 // So we build it all by hand. | |
2981 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
2982 // ArrayAddress dispatch(table, index); | |
2983 | |
2984 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
2985 | |
2986 masm.lea(dest_reg, InternalAddress(table_base)); | |
2987 masm.jmp(dispatch); | |
2988 %} | |
2989 | |
2990 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
2991 MacroAssembler masm(&cbuf); | |
2992 | |
2993 Register switch_reg = as_Register($switch_val$$reg); | |
2994 Register dest_reg = as_Register($dest$$reg); | |
2995 address table_base = masm.address_table_constant(_index2label); | |
2996 | |
2997 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
2998 // to do that and the compiler is using that register as one it can allocate. | |
2999 // So we build it all by hand. | |
3000 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
3001 // ArrayAddress dispatch(table, index); | |
3002 | |
3003 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
3004 masm.lea(dest_reg, InternalAddress(table_base)); | |
3005 masm.jmp(dispatch); | |
3006 | |
3007 %} | |
3008 | |
3009 enc_class lock_prefix() | |
3010 %{ | |
3011 if (os::is_MP()) { | |
3012 emit_opcode(cbuf, 0xF0); // lock | |
3013 } | |
3014 %} | |
3015 | |
3016 enc_class REX_mem(memory mem) | |
3017 %{ | |
3018 if ($mem$$base >= 8) { | |
3019 if ($mem$$index < 8) { | |
3020 emit_opcode(cbuf, Assembler::REX_B); | |
3021 } else { | |
3022 emit_opcode(cbuf, Assembler::REX_XB); | |
3023 } | |
3024 } else { | |
3025 if ($mem$$index >= 8) { | |
3026 emit_opcode(cbuf, Assembler::REX_X); | |
3027 } | |
3028 } | |
3029 %} | |
3030 | |
3031 enc_class REX_mem_wide(memory mem) | |
3032 %{ | |
3033 if ($mem$$base >= 8) { | |
3034 if ($mem$$index < 8) { | |
3035 emit_opcode(cbuf, Assembler::REX_WB); | |
3036 } else { | |
3037 emit_opcode(cbuf, Assembler::REX_WXB); | |
3038 } | |
3039 } else { | |
3040 if ($mem$$index < 8) { | |
3041 emit_opcode(cbuf, Assembler::REX_W); | |
3042 } else { | |
3043 emit_opcode(cbuf, Assembler::REX_WX); | |
3044 } | |
3045 } | |
3046 %} | |
3047 | |
3048 // for byte regs | |
3049 enc_class REX_breg(rRegI reg) | |
3050 %{ | |
3051 if ($reg$$reg >= 4) { | |
3052 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
3053 } | |
3054 %} | |
3055 | |
3056 // for byte regs | |
3057 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
3058 %{ | |
3059 if ($dst$$reg < 8) { | |
3060 if ($src$$reg >= 4) { | |
3061 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
3062 } | |
3063 } else { | |
3064 if ($src$$reg < 8) { | |
3065 emit_opcode(cbuf, Assembler::REX_R); | |
3066 } else { | |
3067 emit_opcode(cbuf, Assembler::REX_RB); | |
3068 } | |
3069 } | |
3070 %} | |
3071 | |
3072 // for byte regs | |
3073 enc_class REX_breg_mem(rRegI reg, memory mem) | |
3074 %{ | |
3075 if ($reg$$reg < 8) { | |
3076 if ($mem$$base < 8) { | |
3077 if ($mem$$index >= 8) { | |
3078 emit_opcode(cbuf, Assembler::REX_X); | |
3079 } else if ($reg$$reg >= 4) { | |
3080 emit_opcode(cbuf, Assembler::REX); | |
3081 } | |
3082 } else { | |
3083 if ($mem$$index < 8) { | |
3084 emit_opcode(cbuf, Assembler::REX_B); | |
3085 } else { | |
3086 emit_opcode(cbuf, Assembler::REX_XB); | |
3087 } | |
3088 } | |
3089 } else { | |
3090 if ($mem$$base < 8) { | |
3091 if ($mem$$index < 8) { | |
3092 emit_opcode(cbuf, Assembler::REX_R); | |
3093 } else { | |
3094 emit_opcode(cbuf, Assembler::REX_RX); | |
3095 } | |
3096 } else { | |
3097 if ($mem$$index < 8) { | |
3098 emit_opcode(cbuf, Assembler::REX_RB); | |
3099 } else { | |
3100 emit_opcode(cbuf, Assembler::REX_RXB); | |
3101 } | |
3102 } | |
3103 } | |
3104 %} | |
3105 | |
3106 enc_class REX_reg(rRegI reg) | |
3107 %{ | |
3108 if ($reg$$reg >= 8) { | |
3109 emit_opcode(cbuf, Assembler::REX_B); | |
3110 } | |
3111 %} | |
3112 | |
3113 enc_class REX_reg_wide(rRegI reg) | |
3114 %{ | |
3115 if ($reg$$reg < 8) { | |
3116 emit_opcode(cbuf, Assembler::REX_W); | |
3117 } else { | |
3118 emit_opcode(cbuf, Assembler::REX_WB); | |
3119 } | |
3120 %} | |
3121 | |
3122 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
3123 %{ | |
3124 if ($dst$$reg < 8) { | |
3125 if ($src$$reg >= 8) { | |
3126 emit_opcode(cbuf, Assembler::REX_B); | |
3127 } | |
3128 } else { | |
3129 if ($src$$reg < 8) { | |
3130 emit_opcode(cbuf, Assembler::REX_R); | |
3131 } else { | |
3132 emit_opcode(cbuf, Assembler::REX_RB); | |
3133 } | |
3134 } | |
3135 %} | |
3136 | |
3137 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
3138 %{ | |
3139 if ($dst$$reg < 8) { | |
3140 if ($src$$reg < 8) { | |
3141 emit_opcode(cbuf, Assembler::REX_W); | |
3142 } else { | |
3143 emit_opcode(cbuf, Assembler::REX_WB); | |
3144 } | |
3145 } else { | |
3146 if ($src$$reg < 8) { | |
3147 emit_opcode(cbuf, Assembler::REX_WR); | |
3148 } else { | |
3149 emit_opcode(cbuf, Assembler::REX_WRB); | |
3150 } | |
3151 } | |
3152 %} | |
3153 | |
3154 enc_class REX_reg_mem(rRegI reg, memory mem) | |
3155 %{ | |
3156 if ($reg$$reg < 8) { | |
3157 if ($mem$$base < 8) { | |
3158 if ($mem$$index >= 8) { | |
3159 emit_opcode(cbuf, Assembler::REX_X); | |
3160 } | |
3161 } else { | |
3162 if ($mem$$index < 8) { | |
3163 emit_opcode(cbuf, Assembler::REX_B); | |
3164 } else { | |
3165 emit_opcode(cbuf, Assembler::REX_XB); | |
3166 } | |
3167 } | |
3168 } else { | |
3169 if ($mem$$base < 8) { | |
3170 if ($mem$$index < 8) { | |
3171 emit_opcode(cbuf, Assembler::REX_R); | |
3172 } else { | |
3173 emit_opcode(cbuf, Assembler::REX_RX); | |
3174 } | |
3175 } else { | |
3176 if ($mem$$index < 8) { | |
3177 emit_opcode(cbuf, Assembler::REX_RB); | |
3178 } else { | |
3179 emit_opcode(cbuf, Assembler::REX_RXB); | |
3180 } | |
3181 } | |
3182 } | |
3183 %} | |
3184 | |
3185 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
3186 %{ | |
3187 if ($reg$$reg < 8) { | |
3188 if ($mem$$base < 8) { | |
3189 if ($mem$$index < 8) { | |
3190 emit_opcode(cbuf, Assembler::REX_W); | |
3191 } else { | |
3192 emit_opcode(cbuf, Assembler::REX_WX); | |
3193 } | |
3194 } else { | |
3195 if ($mem$$index < 8) { | |
3196 emit_opcode(cbuf, Assembler::REX_WB); | |
3197 } else { | |
3198 emit_opcode(cbuf, Assembler::REX_WXB); | |
3199 } | |
3200 } | |
3201 } else { | |
3202 if ($mem$$base < 8) { | |
3203 if ($mem$$index < 8) { | |
3204 emit_opcode(cbuf, Assembler::REX_WR); | |
3205 } else { | |
3206 emit_opcode(cbuf, Assembler::REX_WRX); | |
3207 } | |
3208 } else { | |
3209 if ($mem$$index < 8) { | |
3210 emit_opcode(cbuf, Assembler::REX_WRB); | |
3211 } else { | |
3212 emit_opcode(cbuf, Assembler::REX_WRXB); | |
3213 } | |
3214 } | |
3215 } | |
3216 %} | |
3217 | |
3218 enc_class reg_mem(rRegI ereg, memory mem) | |
3219 %{ | |
3220 // High registers handle in encode_RegMem | |
3221 int reg = $ereg$$reg; | |
3222 int base = $mem$$base; | |
3223 int index = $mem$$index; | |
3224 int scale = $mem$$scale; | |
3225 int disp = $mem$$disp; | |
3226 bool disp_is_oop = $mem->disp_is_oop(); | |
3227 | |
3228 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
3229 %} | |
3230 | |
3231 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
3232 %{ | |
3233 int rm_byte_opcode = $rm_opcode$$constant; | |
3234 | |
3235 // High registers handle in encode_RegMem | |
3236 int base = $mem$$base; | |
3237 int index = $mem$$index; | |
3238 int scale = $mem$$scale; | |
3239 int displace = $mem$$disp; | |
3240 | |
3241 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
3242 // working with static | |
3243 // globals | |
3244 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
3245 disp_is_oop); | |
3246 %} | |
3247 | |
3248 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
3249 %{ | |
3250 int reg_encoding = $dst$$reg; | |
3251 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
3252 int index = 0x04; // 0x04 indicates no index | |
3253 int scale = 0x00; // 0x00 indicates no scale | |
3254 int displace = $src1$$constant; // 0x00 indicates no displacement | |
3255 bool disp_is_oop = false; | |
3256 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
3257 disp_is_oop); | |
3258 %} | |
3259 | |
3260 enc_class neg_reg(rRegI dst) | |
3261 %{ | |
3262 int dstenc = $dst$$reg; | |
3263 if (dstenc >= 8) { | |
3264 emit_opcode(cbuf, Assembler::REX_B); | |
3265 dstenc -= 8; | |
3266 } | |
3267 // NEG $dst | |
3268 emit_opcode(cbuf, 0xF7); | |
3269 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
3270 %} | |
3271 | |
3272 enc_class neg_reg_wide(rRegI dst) | |
3273 %{ | |
3274 int dstenc = $dst$$reg; | |
3275 if (dstenc < 8) { | |
3276 emit_opcode(cbuf, Assembler::REX_W); | |
3277 } else { | |
3278 emit_opcode(cbuf, Assembler::REX_WB); | |
3279 dstenc -= 8; | |
3280 } | |
3281 // NEG $dst | |
3282 emit_opcode(cbuf, 0xF7); | |
3283 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
3284 %} | |
3285 | |
3286 enc_class setLT_reg(rRegI dst) | |
3287 %{ | |
3288 int dstenc = $dst$$reg; | |
3289 if (dstenc >= 8) { | |
3290 emit_opcode(cbuf, Assembler::REX_B); | |
3291 dstenc -= 8; | |
3292 } else if (dstenc >= 4) { | |
3293 emit_opcode(cbuf, Assembler::REX); | |
3294 } | |
3295 // SETLT $dst | |
3296 emit_opcode(cbuf, 0x0F); | |
3297 emit_opcode(cbuf, 0x9C); | |
3298 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
3299 %} | |
3300 | |
3301 enc_class setNZ_reg(rRegI dst) | |
3302 %{ | |
3303 int dstenc = $dst$$reg; | |
3304 if (dstenc >= 8) { | |
3305 emit_opcode(cbuf, Assembler::REX_B); | |
3306 dstenc -= 8; | |
3307 } else if (dstenc >= 4) { | |
3308 emit_opcode(cbuf, Assembler::REX); | |
3309 } | |
3310 // SETNZ $dst | |
3311 emit_opcode(cbuf, 0x0F); | |
3312 emit_opcode(cbuf, 0x95); | |
3313 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
3314 %} | |
3315 | |
3316 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y, | |
3317 rcx_RegI tmp) | |
3318 %{ | |
3319 // cadd_cmpLT | |
3320 | |
3321 int tmpReg = $tmp$$reg; | |
3322 | |
3323 int penc = $p$$reg; | |
3324 int qenc = $q$$reg; | |
3325 int yenc = $y$$reg; | |
3326 | |
3327 // subl $p,$q | |
3328 if (penc < 8) { | |
3329 if (qenc >= 8) { | |
3330 emit_opcode(cbuf, Assembler::REX_B); | |
3331 } | |
3332 } else { | |
3333 if (qenc < 8) { | |
3334 emit_opcode(cbuf, Assembler::REX_R); | |
3335 } else { | |
3336 emit_opcode(cbuf, Assembler::REX_RB); | |
3337 } | |
3338 } | |
3339 emit_opcode(cbuf, 0x2B); | |
3340 emit_rm(cbuf, 0x3, penc & 7, qenc & 7); | |
3341 | |
3342 // sbbl $tmp, $tmp | |
3343 emit_opcode(cbuf, 0x1B); | |
3344 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
3345 | |
3346 // andl $tmp, $y | |
3347 if (yenc >= 8) { | |
3348 emit_opcode(cbuf, Assembler::REX_B); | |
3349 } | |
3350 emit_opcode(cbuf, 0x23); | |
3351 emit_rm(cbuf, 0x3, tmpReg, yenc & 7); | |
3352 | |
3353 // addl $p,$tmp | |
3354 if (penc >= 8) { | |
3355 emit_opcode(cbuf, Assembler::REX_R); | |
3356 } | |
3357 emit_opcode(cbuf, 0x03); | |
3358 emit_rm(cbuf, 0x3, penc & 7, tmpReg); | |
3359 %} | |
3360 | |
3361 // Compare the lonogs and set -1, 0, or 1 into dst | |
3362 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
3363 %{ | |
3364 int src1enc = $src1$$reg; | |
3365 int src2enc = $src2$$reg; | |
3366 int dstenc = $dst$$reg; | |
3367 | |
3368 // cmpq $src1, $src2 | |
3369 if (src1enc < 8) { | |
3370 if (src2enc < 8) { | |
3371 emit_opcode(cbuf, Assembler::REX_W); | |
3372 } else { | |
3373 emit_opcode(cbuf, Assembler::REX_WB); | |
3374 } | |
3375 } else { | |
3376 if (src2enc < 8) { | |
3377 emit_opcode(cbuf, Assembler::REX_WR); | |
3378 } else { | |
3379 emit_opcode(cbuf, Assembler::REX_WRB); | |
3380 } | |
3381 } | |
3382 emit_opcode(cbuf, 0x3B); | |
3383 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
3384 | |
3385 // movl $dst, -1 | |
3386 if (dstenc >= 8) { | |
3387 emit_opcode(cbuf, Assembler::REX_B); | |
3388 } | |
3389 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
3390 emit_d32(cbuf, -1); | |
3391 | |
3392 // jl,s done | |
3393 emit_opcode(cbuf, 0x7C); | |
3394 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
3395 | |
3396 // setne $dst | |
3397 if (dstenc >= 4) { | |
3398 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
3399 } | |
3400 emit_opcode(cbuf, 0x0F); | |
3401 emit_opcode(cbuf, 0x95); | |
3402 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
3403 | |
3404 // movzbl $dst, $dst | |
3405 if (dstenc >= 4) { | |
3406 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
3407 } | |
3408 emit_opcode(cbuf, 0x0F); | |
3409 emit_opcode(cbuf, 0xB6); | |
3410 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
3411 %} | |
3412 | |
3413 enc_class Push_ResultXD(regD dst) %{ | |
3414 int dstenc = $dst$$reg; | |
3415 | |
3416 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | |
3417 | |
3418 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
3419 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
3420 if (dstenc >= 8) { | |
3421 emit_opcode(cbuf, Assembler::REX_R); | |
3422 } | |
3423 emit_opcode (cbuf, 0x0F ); | |
3424 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
3425 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
3426 | |
3427 // add rsp,8 | |
3428 emit_opcode(cbuf, Assembler::REX_W); | |
3429 emit_opcode(cbuf,0x83); | |
3430 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
3431 emit_d8(cbuf,0x08); | |
3432 %} | |
3433 | |
3434 enc_class Push_SrcXD(regD src) %{ | |
3435 int srcenc = $src$$reg; | |
3436 | |
3437 // subq rsp,#8 | |
3438 emit_opcode(cbuf, Assembler::REX_W); | |
3439 emit_opcode(cbuf, 0x83); | |
3440 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3441 emit_d8(cbuf, 0x8); | |
3442 | |
3443 // movsd [rsp],src | |
3444 emit_opcode(cbuf, 0xF2); | |
3445 if (srcenc >= 8) { | |
3446 emit_opcode(cbuf, Assembler::REX_R); | |
3447 } | |
3448 emit_opcode(cbuf, 0x0F); | |
3449 emit_opcode(cbuf, 0x11); | |
3450 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
3451 | |
3452 // fldd [rsp] | |
3453 emit_opcode(cbuf, 0x66); | |
3454 emit_opcode(cbuf, 0xDD); | |
3455 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
3456 %} | |
3457 | |
3458 | |
3459 enc_class movq_ld(regD dst, memory mem) %{ | |
3460 MacroAssembler _masm(&cbuf); | |
3461 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | |
3462 __ movq(as_XMMRegister($dst$$reg), madr); | |
3463 %} | |
3464 | |
3465 enc_class movq_st(memory mem, regD src) %{ | |
3466 MacroAssembler _masm(&cbuf); | |
3467 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); | |
3468 __ movq(madr, as_XMMRegister($src$$reg)); | |
3469 %} | |
3470 | |
3471 enc_class pshufd_8x8(regF dst, regF src) %{ | |
3472 MacroAssembler _masm(&cbuf); | |
3473 | |
3474 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
3475 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
3476 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
3477 %} | |
3478 | |
3479 enc_class pshufd_4x16(regF dst, regF src) %{ | |
3480 MacroAssembler _masm(&cbuf); | |
3481 | |
3482 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
3483 %} | |
3484 | |
3485 enc_class pshufd(regD dst, regD src, int mode) %{ | |
3486 MacroAssembler _masm(&cbuf); | |
3487 | |
3488 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
3489 %} | |
3490 | |
3491 enc_class pxor(regD dst, regD src) %{ | |
3492 MacroAssembler _masm(&cbuf); | |
3493 | |
3494 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
3495 %} | |
3496 | |
3497 enc_class mov_i2x(regD dst, rRegI src) %{ | |
3498 MacroAssembler _masm(&cbuf); | |
3499 | |
3500 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
3501 %} | |
3502 | |
3503 // obj: object to lock | |
3504 // box: box address (header location) -- killed | |
3505 // tmp: rax -- killed | |
3506 // scr: rbx -- killed | |
3507 // | |
3508 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
3509 // from i486.ad. See that file for comments. | |
3510 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
3511 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
3512 | |
3513 | |
3514 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
3515 %{ | |
3516 Register objReg = as_Register((int)$obj$$reg); | |
3517 Register boxReg = as_Register((int)$box$$reg); | |
3518 Register tmpReg = as_Register($tmp$$reg); | |
3519 Register scrReg = as_Register($scr$$reg); | |
3520 MacroAssembler masm(&cbuf); | |
3521 | |
3522 // Verify uniqueness of register assignments -- necessary but not sufficient | |
3523 assert (objReg != boxReg && objReg != tmpReg && | |
3524 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
3525 | |
3526 if (_counters != NULL) { | |
3527 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
3528 } | |
3529 if (EmitSync & 1) { | |
3530 masm.movptr (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ; | |
3531 masm.cmpq (rsp, 0) ; | |
3532 } else | |
3533 if (EmitSync & 2) { | |
3534 Label DONE_LABEL; | |
3535 if (UseBiasedLocking) { | |
3536 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
3537 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
3538 } | |
3539 masm.movl(tmpReg, 0x1); | |
3540 masm.orq(tmpReg, Address(objReg, 0)); | |
3541 masm.movq(Address(boxReg, 0), tmpReg); | |
3542 if (os::is_MP()) { | |
3543 masm.lock(); | |
3544 } | |
3545 masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg | |
3546 masm.jcc(Assembler::equal, DONE_LABEL); | |
3547 | |
3548 // Recursive locking | |
3549 masm.subq(tmpReg, rsp); | |
3550 masm.andq(tmpReg, 7 - os::vm_page_size()); | |
3551 masm.movq(Address(boxReg, 0), tmpReg); | |
3552 | |
3553 masm.bind(DONE_LABEL); | |
3554 masm.nop(); // avoid branch to branch | |
3555 } else { | |
3556 Label DONE_LABEL, IsInflated, Egress; | |
3557 | |
3558 masm.movq (tmpReg, Address(objReg, 0)) ; | |
3559 masm.testq (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased | |
3560 masm.jcc (Assembler::notZero, IsInflated) ; | |
3561 | |
3562 // it's stack-locked, biased or neutral | |
3563 // TODO: optimize markword triage order to reduce the number of | |
3564 // conditional branches in the most common cases. | |
3565 // Beware -- there's a subtle invariant that fetch of the markword | |
3566 // at [FETCH], below, will never observe a biased encoding (*101b). | |
3567 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
3568 | |
3569 if (UseBiasedLocking) { | |
3570 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); | |
3571 masm.movq (tmpReg, Address(objReg, 0)) ; // [FETCH] | |
3572 } | |
3573 | |
3574 masm.orq (tmpReg, 1) ; | |
3575 masm.movq (Address(boxReg, 0), tmpReg) ; | |
3576 if (os::is_MP()) { masm.lock(); } | |
3577 masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg | |
3578 if (_counters != NULL) { | |
3579 masm.cond_inc32(Assembler::equal, | |
3580 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
3581 } | |
3582 masm.jcc (Assembler::equal, DONE_LABEL); | |
3583 | |
3584 // Recursive locking | |
3585 masm.subq (tmpReg, rsp); | |
3586 masm.andq (tmpReg, 7 - os::vm_page_size()); | |
3587 masm.movq (Address(boxReg, 0), tmpReg); | |
3588 if (_counters != NULL) { | |
3589 masm.cond_inc32(Assembler::equal, | |
3590 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
3591 } | |
3592 masm.jmp (DONE_LABEL) ; | |
3593 | |
3594 masm.bind (IsInflated) ; | |
3595 // It's inflated | |
3596 | |
3597 // TODO: someday avoid the ST-before-CAS penalty by | |
3598 // relocating (deferring) the following ST. | |
3599 // We should also think about trying a CAS without having | |
3600 // fetched _owner. If the CAS is successful we may | |
3601 // avoid an RTO->RTS upgrade on the $line. | |
3602 masm.movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ; | |
3603 | |
3604 masm.movq (boxReg, tmpReg) ; | |
3605 masm.movq (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3606 masm.testq (tmpReg, tmpReg) ; | |
3607 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
3608 | |
3609 // It's inflated and appears unlocked | |
3610 if (os::is_MP()) { masm.lock(); } | |
3611 masm.cmpxchgq(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3612 // Intentional fall-through into DONE_LABEL ... | |
3613 | |
3614 masm.bind (DONE_LABEL) ; | |
3615 masm.nop () ; // avoid jmp to jmp | |
3616 } | |
3617 %} | |
3618 | |
3619 // obj: object to unlock | |
3620 // box: box address (displaced header location), killed | |
3621 // RBX: killed tmp; cannot be obj nor box | |
3622 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
3623 %{ | |
3624 | |
3625 Register objReg = as_Register($obj$$reg); | |
3626 Register boxReg = as_Register($box$$reg); | |
3627 Register tmpReg = as_Register($tmp$$reg); | |
3628 MacroAssembler masm(&cbuf); | |
3629 | |
3630 if (EmitSync & 4) { | |
3631 masm.cmpq (rsp, 0) ; | |
3632 } else | |
3633 if (EmitSync & 8) { | |
3634 Label DONE_LABEL; | |
3635 if (UseBiasedLocking) { | |
3636 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
3637 } | |
3638 | |
3639 // Check whether the displaced header is 0 | |
3640 //(=> recursive unlock) | |
3641 masm.movq(tmpReg, Address(boxReg, 0)); | |
3642 masm.testq(tmpReg, tmpReg); | |
3643 masm.jcc(Assembler::zero, DONE_LABEL); | |
3644 | |
3645 // If not recursive lock, reset the header to displaced header | |
3646 if (os::is_MP()) { | |
3647 masm.lock(); | |
3648 } | |
3649 masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
3650 masm.bind(DONE_LABEL); | |
3651 masm.nop(); // avoid branch to branch | |
3652 } else { | |
3653 Label DONE_LABEL, Stacked, CheckSucc ; | |
3654 | |
3655 if (UseBiasedLocking) { | |
3656 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
3657 } | |
3658 | |
3659 masm.movq (tmpReg, Address(objReg, 0)) ; | |
3660 masm.cmpq (Address(boxReg, 0), (int)NULL_WORD) ; | |
3661 masm.jcc (Assembler::zero, DONE_LABEL) ; | |
3662 masm.testq (tmpReg, 0x02) ; | |
3663 masm.jcc (Assembler::zero, Stacked) ; | |
3664 | |
3665 // It's inflated | |
3666 masm.movq (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3667 masm.xorq (boxReg, r15_thread) ; | |
3668 masm.orq (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
3669 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
3670 masm.movq (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
3671 masm.orq (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
3672 masm.jcc (Assembler::notZero, CheckSucc) ; | |
3673 masm.mov64 (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ; | |
3674 masm.jmp (DONE_LABEL) ; | |
3675 | |
3676 if ((EmitSync & 65536) == 0) { | |
3677 Label LSuccess, LGoSlowPath ; | |
3678 masm.bind (CheckSucc) ; | |
3679 masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ; | |
3680 masm.jcc (Assembler::zero, LGoSlowPath) ; | |
3681 | |
3682 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
3683 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
3684 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
3685 // are all faster when the write buffer is populated. | |
3686 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ; | |
3687 if (os::is_MP()) { | |
3688 masm.lock () ; masm.addq (Address(rsp, 0), 0) ; | |
3689 } | |
3690 masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ; | |
3691 masm.jcc (Assembler::notZero, LSuccess) ; | |
3692 | |
3693 masm.movptr (boxReg, (int)NULL_WORD) ; // box is really EAX | |
3694 if (os::is_MP()) { masm.lock(); } | |
3695 masm.cmpxchgq (r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); | |
3696 masm.jcc (Assembler::notEqual, LSuccess) ; | |
3697 // Intentional fall-through into slow-path | |
3698 | |
3699 masm.bind (LGoSlowPath) ; | |
3700 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
3701 masm.jmp (DONE_LABEL) ; | |
3702 | |
3703 masm.bind (LSuccess) ; | |
3704 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
3705 masm.jmp (DONE_LABEL) ; | |
3706 } | |
3707 | |
3708 masm.bind (Stacked) ; | |
3709 masm.movq (tmpReg, Address (boxReg, 0)) ; // re-fetch | |
3710 if (os::is_MP()) { masm.lock(); } | |
3711 masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
3712 | |
3713 if (EmitSync & 65536) { | |
3714 masm.bind (CheckSucc) ; | |
3715 } | |
3716 masm.bind(DONE_LABEL); | |
3717 if (EmitSync & 32768) { | |
3718 masm.nop(); // avoid branch to branch | |
3719 } | |
3720 } | |
3721 %} | |
3722 | |
3723 enc_class enc_String_Compare() | |
3724 %{ | |
3725 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL, | |
3726 POP_LABEL, DONE_LABEL, CONT_LABEL, | |
3727 WHILE_HEAD_LABEL; | |
3728 MacroAssembler masm(&cbuf); | |
3729 | |
3730 // Get the first character position in both strings | |
3731 // [8] char array, [12] offset, [16] count | |
3732 int value_offset = java_lang_String::value_offset_in_bytes(); | |
3733 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
3734 int count_offset = java_lang_String::count_offset_in_bytes(); | |
3735 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3736 | |
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3737 masm.load_heap_oop(rax, Address(rsi, value_offset)); |
0 | 3738 masm.movl(rcx, Address(rsi, offset_offset)); |
3739 masm.leaq(rax, Address(rax, rcx, Address::times_2, base_offset)); | |
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3740 masm.load_heap_oop(rbx, Address(rdi, value_offset)); |
0 | 3741 masm.movl(rcx, Address(rdi, offset_offset)); |
3742 masm.leaq(rbx, Address(rbx, rcx, Address::times_2, base_offset)); | |
3743 | |
3744 // Compute the minimum of the string lengths(rsi) and the | |
3745 // difference of the string lengths (stack) | |
3746 | |
3747 masm.movl(rdi, Address(rdi, count_offset)); | |
3748 masm.movl(rsi, Address(rsi, count_offset)); | |
3749 masm.movl(rcx, rdi); | |
3750 masm.subl(rdi, rsi); | |
3751 masm.pushq(rdi); | |
3752 masm.cmovl(Assembler::lessEqual, rsi, rcx); | |
3753 | |
3754 // Is the minimum length zero? | |
3755 masm.bind(RCX_GOOD_LABEL); | |
3756 masm.testl(rsi, rsi); | |
3757 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
3758 | |
3759 // Load first characters | |
3760 masm.load_unsigned_word(rcx, Address(rbx, 0)); | |
3761 masm.load_unsigned_word(rdi, Address(rax, 0)); | |
3762 | |
3763 // Compare first characters | |
3764 masm.subl(rcx, rdi); | |
3765 masm.jcc(Assembler::notZero, POP_LABEL); | |
3766 masm.decrementl(rsi); | |
3767 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
3768 | |
3769 { | |
3770 // Check after comparing first character to see if strings are equivalent | |
3771 Label LSkip2; | |
3772 // Check if the strings start at same location | |
3773 masm.cmpq(rbx, rax); | |
3774 masm.jcc(Assembler::notEqual, LSkip2); | |
3775 | |
3776 // Check if the length difference is zero (from stack) | |
3777 masm.cmpl(Address(rsp, 0), 0x0); | |
3778 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); | |
3779 | |
3780 // Strings might not be equivalent | |
3781 masm.bind(LSkip2); | |
3782 } | |
3783 | |
3784 // Shift RAX and RBX to the end of the arrays, negate min | |
3785 masm.leaq(rax, Address(rax, rsi, Address::times_2, 2)); | |
3786 masm.leaq(rbx, Address(rbx, rsi, Address::times_2, 2)); | |
3787 masm.negq(rsi); | |
3788 | |
3789 // Compare the rest of the characters | |
3790 masm.bind(WHILE_HEAD_LABEL); | |
3791 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0)); | |
3792 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0)); | |
3793 masm.subl(rcx, rdi); | |
3794 masm.jcc(Assembler::notZero, POP_LABEL); | |
3795 masm.incrementq(rsi); | |
3796 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); | |
3797 | |
3798 // Strings are equal up to min length. Return the length difference. | |
3799 masm.bind(LENGTH_DIFF_LABEL); | |
3800 masm.popq(rcx); | |
3801 masm.jmp(DONE_LABEL); | |
3802 | |
3803 // Discard the stored length difference | |
3804 masm.bind(POP_LABEL); | |
3805 masm.addq(rsp, 8); | |
3806 | |
3807 // That's it | |
3808 masm.bind(DONE_LABEL); | |
3809 %} | |
3810 | |
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3811 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{ |
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3812 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP; |
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3813 MacroAssembler masm(&cbuf); |
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3814 |
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3815 Register ary1Reg = as_Register($ary1$$reg); |
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3816 Register ary2Reg = as_Register($ary2$$reg); |
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3817 Register tmp1Reg = as_Register($tmp1$$reg); |
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3818 Register tmp2Reg = as_Register($tmp2$$reg); |
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3819 Register resultReg = as_Register($result$$reg); |
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3820 |
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3821 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
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3822 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
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3823 |
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3824 // Check the input args |
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3825 masm.cmpq(ary1Reg, ary2Reg); |
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3826 masm.jcc(Assembler::equal, TRUE_LABEL); |
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3827 masm.testq(ary1Reg, ary1Reg); |
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3828 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3829 masm.testq(ary2Reg, ary2Reg); |
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3830 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3831 |
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3832 // Check the lengths |
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3833 masm.movl(tmp2Reg, Address(ary1Reg, length_offset)); |
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3834 masm.movl(resultReg, Address(ary2Reg, length_offset)); |
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3835 masm.cmpl(tmp2Reg, resultReg); |
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3836 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3837 masm.testl(resultReg, resultReg); |
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3838 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3839 |
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3840 // Get the number of 4 byte vectors to compare |
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3841 masm.shrl(resultReg, 1); |
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3842 |
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3843 // Check for odd-length arrays |
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3844 masm.andl(tmp2Reg, 1); |
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3845 masm.testl(tmp2Reg, tmp2Reg); |
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3846 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR); |
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3847 |
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3848 // Compare 2-byte "tail" at end of arrays |
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3849 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
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3850 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
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3851 masm.cmpl(tmp1Reg, tmp2Reg); |
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3852 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3853 masm.testl(resultReg, resultReg); |
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3854 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3855 |
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3856 // Setup compare loop |
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3857 masm.bind(COMPARE_LOOP_HDR); |
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3858 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays |
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3859 masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
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3860 masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
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3861 masm.negq(resultReg); |
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3862 |
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3863 // 4-byte-wide compare loop |
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3864 masm.bind(COMPARE_LOOP); |
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3865 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0)); |
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3866 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0)); |
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3867 masm.cmpl(ary1Reg, ary2Reg); |
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3868 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3869 masm.incrementq(resultReg); |
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3870 masm.jcc(Assembler::notZero, COMPARE_LOOP); |
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3871 |
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3872 masm.bind(TRUE_LABEL); |
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3873 masm.movl(resultReg, 1); // return true |
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3874 masm.jmp(DONE_LABEL); |
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3875 |
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3876 masm.bind(FALSE_LABEL); |
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3877 masm.xorl(resultReg, resultReg); // return false |
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3878 |
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3879 // That's it |
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3880 masm.bind(DONE_LABEL); |
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3881 %} |
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3882 |
0 | 3883 enc_class enc_rethrow() |
3884 %{ | |
3885 cbuf.set_inst_mark(); | |
3886 emit_opcode(cbuf, 0xE9); // jmp entry | |
3887 emit_d32_reloc(cbuf, | |
3888 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4), | |
3889 runtime_call_Relocation::spec(), | |
3890 RELOC_DISP32); | |
3891 %} | |
3892 | |
3893 enc_class absF_encoding(regF dst) | |
3894 %{ | |
3895 int dstenc = $dst$$reg; | |
3896 address signmask_address = (address) StubRoutines::amd64::float_sign_mask(); | |
3897 | |
3898 cbuf.set_inst_mark(); | |
3899 if (dstenc >= 8) { | |
3900 emit_opcode(cbuf, Assembler::REX_R); | |
3901 dstenc -= 8; | |
3902 } | |
3903 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3904 emit_opcode(cbuf, 0x0F); | |
3905 emit_opcode(cbuf, 0x54); | |
3906 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3907 emit_d32_reloc(cbuf, signmask_address); | |
3908 %} | |
3909 | |
3910 enc_class absD_encoding(regD dst) | |
3911 %{ | |
3912 int dstenc = $dst$$reg; | |
3913 address signmask_address = (address) StubRoutines::amd64::double_sign_mask(); | |
3914 | |
3915 cbuf.set_inst_mark(); | |
3916 emit_opcode(cbuf, 0x66); | |
3917 if (dstenc >= 8) { | |
3918 emit_opcode(cbuf, Assembler::REX_R); | |
3919 dstenc -= 8; | |
3920 } | |
3921 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3922 emit_opcode(cbuf, 0x0F); | |
3923 emit_opcode(cbuf, 0x54); | |
3924 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3925 emit_d32_reloc(cbuf, signmask_address); | |
3926 %} | |
3927 | |
3928 enc_class negF_encoding(regF dst) | |
3929 %{ | |
3930 int dstenc = $dst$$reg; | |
3931 address signflip_address = (address) StubRoutines::amd64::float_sign_flip(); | |
3932 | |
3933 cbuf.set_inst_mark(); | |
3934 if (dstenc >= 8) { | |
3935 emit_opcode(cbuf, Assembler::REX_R); | |
3936 dstenc -= 8; | |
3937 } | |
3938 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3939 emit_opcode(cbuf, 0x0F); | |
3940 emit_opcode(cbuf, 0x57); | |
3941 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3942 emit_d32_reloc(cbuf, signflip_address); | |
3943 %} | |
3944 | |
3945 enc_class negD_encoding(regD dst) | |
3946 %{ | |
3947 int dstenc = $dst$$reg; | |
3948 address signflip_address = (address) StubRoutines::amd64::double_sign_flip(); | |
3949 | |
3950 cbuf.set_inst_mark(); | |
3951 emit_opcode(cbuf, 0x66); | |
3952 if (dstenc >= 8) { | |
3953 emit_opcode(cbuf, Assembler::REX_R); | |
3954 dstenc -= 8; | |
3955 } | |
3956 // XXX reg_mem doesn't support RIP-relative addressing yet | |
3957 emit_opcode(cbuf, 0x0F); | |
3958 emit_opcode(cbuf, 0x57); | |
3959 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
3960 emit_d32_reloc(cbuf, signflip_address); | |
3961 %} | |
3962 | |
3963 enc_class f2i_fixup(rRegI dst, regF src) | |
3964 %{ | |
3965 int dstenc = $dst$$reg; | |
3966 int srcenc = $src$$reg; | |
3967 | |
3968 // cmpl $dst, #0x80000000 | |
3969 if (dstenc >= 8) { | |
3970 emit_opcode(cbuf, Assembler::REX_B); | |
3971 } | |
3972 emit_opcode(cbuf, 0x81); | |
3973 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
3974 emit_d32(cbuf, 0x80000000); | |
3975 | |
3976 // jne,s done | |
3977 emit_opcode(cbuf, 0x75); | |
3978 if (srcenc < 8 && dstenc < 8) { | |
3979 emit_d8(cbuf, 0xF); | |
3980 } else if (srcenc >= 8 && dstenc >= 8) { | |
3981 emit_d8(cbuf, 0x11); | |
3982 } else { | |
3983 emit_d8(cbuf, 0x10); | |
3984 } | |
3985 | |
3986 // subq rsp, #8 | |
3987 emit_opcode(cbuf, Assembler::REX_W); | |
3988 emit_opcode(cbuf, 0x83); | |
3989 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
3990 emit_d8(cbuf, 8); | |
3991 | |
3992 // movss [rsp], $src | |
3993 emit_opcode(cbuf, 0xF3); | |
3994 if (srcenc >= 8) { | |
3995 emit_opcode(cbuf, Assembler::REX_R); | |
3996 } | |
3997 emit_opcode(cbuf, 0x0F); | |
3998 emit_opcode(cbuf, 0x11); | |
3999 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
4000 | |
4001 // call f2i_fixup | |
4002 cbuf.set_inst_mark(); | |
4003 emit_opcode(cbuf, 0xE8); | |
4004 emit_d32_reloc(cbuf, | |
4005 (int) | |
4006 (StubRoutines::amd64::f2i_fixup() - cbuf.code_end() - 4), | |
4007 runtime_call_Relocation::spec(), | |
4008 RELOC_DISP32); | |
4009 | |
4010 // popq $dst | |
4011 if (dstenc >= 8) { | |
4012 emit_opcode(cbuf, Assembler::REX_B); | |
4013 } | |
4014 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
4015 | |
4016 // done: | |
4017 %} | |
4018 | |
4019 enc_class f2l_fixup(rRegL dst, regF src) | |
4020 %{ | |
4021 int dstenc = $dst$$reg; | |
4022 int srcenc = $src$$reg; | |
4023 address const_address = (address) StubRoutines::amd64::double_sign_flip(); | |
4024 | |
4025 // cmpq $dst, [0x8000000000000000] | |
4026 cbuf.set_inst_mark(); | |
4027 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
4028 emit_opcode(cbuf, 0x39); | |
4029 // XXX reg_mem doesn't support RIP-relative addressing yet | |
4030 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
4031 emit_d32_reloc(cbuf, const_address); | |
4032 | |
4033 | |
4034 // jne,s done | |
4035 emit_opcode(cbuf, 0x75); | |
4036 if (srcenc < 8 && dstenc < 8) { | |
4037 emit_d8(cbuf, 0xF); | |
4038 } else if (srcenc >= 8 && dstenc >= 8) { | |
4039 emit_d8(cbuf, 0x11); | |
4040 } else { | |
4041 emit_d8(cbuf, 0x10); | |
4042 } | |
4043 | |
4044 // subq rsp, #8 | |
4045 emit_opcode(cbuf, Assembler::REX_W); | |
4046 emit_opcode(cbuf, 0x83); | |
4047 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
4048 emit_d8(cbuf, 8); | |
4049 | |
4050 // movss [rsp], $src | |
4051 emit_opcode(cbuf, 0xF3); | |
4052 if (srcenc >= 8) { | |
4053 emit_opcode(cbuf, Assembler::REX_R); | |
4054 } | |
4055 emit_opcode(cbuf, 0x0F); | |
4056 emit_opcode(cbuf, 0x11); | |
4057 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
4058 | |
4059 // call f2l_fixup | |
4060 cbuf.set_inst_mark(); | |
4061 emit_opcode(cbuf, 0xE8); | |
4062 emit_d32_reloc(cbuf, | |
4063 (int) | |
4064 (StubRoutines::amd64::f2l_fixup() - cbuf.code_end() - 4), | |
4065 runtime_call_Relocation::spec(), | |
4066 RELOC_DISP32); | |
4067 | |
4068 // popq $dst | |
4069 if (dstenc >= 8) { | |
4070 emit_opcode(cbuf, Assembler::REX_B); | |
4071 } | |
4072 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
4073 | |
4074 // done: | |
4075 %} | |
4076 | |
4077 enc_class d2i_fixup(rRegI dst, regD src) | |
4078 %{ | |
4079 int dstenc = $dst$$reg; | |
4080 int srcenc = $src$$reg; | |
4081 | |
4082 // cmpl $dst, #0x80000000 | |
4083 if (dstenc >= 8) { | |
4084 emit_opcode(cbuf, Assembler::REX_B); | |
4085 } | |
4086 emit_opcode(cbuf, 0x81); | |
4087 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
4088 emit_d32(cbuf, 0x80000000); | |
4089 | |
4090 // jne,s done | |
4091 emit_opcode(cbuf, 0x75); | |
4092 if (srcenc < 8 && dstenc < 8) { | |
4093 emit_d8(cbuf, 0xF); | |
4094 } else if (srcenc >= 8 && dstenc >= 8) { | |
4095 emit_d8(cbuf, 0x11); | |
4096 } else { | |
4097 emit_d8(cbuf, 0x10); | |
4098 } | |
4099 | |
4100 // subq rsp, #8 | |
4101 emit_opcode(cbuf, Assembler::REX_W); | |
4102 emit_opcode(cbuf, 0x83); | |
4103 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
4104 emit_d8(cbuf, 8); | |
4105 | |
4106 // movsd [rsp], $src | |
4107 emit_opcode(cbuf, 0xF2); | |
4108 if (srcenc >= 8) { | |
4109 emit_opcode(cbuf, Assembler::REX_R); | |
4110 } | |
4111 emit_opcode(cbuf, 0x0F); | |
4112 emit_opcode(cbuf, 0x11); | |
4113 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
4114 | |
4115 // call d2i_fixup | |
4116 cbuf.set_inst_mark(); | |
4117 emit_opcode(cbuf, 0xE8); | |
4118 emit_d32_reloc(cbuf, | |
4119 (int) | |
4120 (StubRoutines::amd64::d2i_fixup() - cbuf.code_end() - 4), | |
4121 runtime_call_Relocation::spec(), | |
4122 RELOC_DISP32); | |
4123 | |
4124 // popq $dst | |
4125 if (dstenc >= 8) { | |
4126 emit_opcode(cbuf, Assembler::REX_B); | |
4127 } | |
4128 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
4129 | |
4130 // done: | |
4131 %} | |
4132 | |
4133 enc_class d2l_fixup(rRegL dst, regD src) | |
4134 %{ | |
4135 int dstenc = $dst$$reg; | |
4136 int srcenc = $src$$reg; | |
4137 address const_address = (address) StubRoutines::amd64::double_sign_flip(); | |
4138 | |
4139 // cmpq $dst, [0x8000000000000000] | |
4140 cbuf.set_inst_mark(); | |
4141 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
4142 emit_opcode(cbuf, 0x39); | |
4143 // XXX reg_mem doesn't support RIP-relative addressing yet | |
4144 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
4145 emit_d32_reloc(cbuf, const_address); | |
4146 | |
4147 | |
4148 // jne,s done | |
4149 emit_opcode(cbuf, 0x75); | |
4150 if (srcenc < 8 && dstenc < 8) { | |
4151 emit_d8(cbuf, 0xF); | |
4152 } else if (srcenc >= 8 && dstenc >= 8) { | |
4153 emit_d8(cbuf, 0x11); | |
4154 } else { | |
4155 emit_d8(cbuf, 0x10); | |
4156 } | |
4157 | |
4158 // subq rsp, #8 | |
4159 emit_opcode(cbuf, Assembler::REX_W); | |
4160 emit_opcode(cbuf, 0x83); | |
4161 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
4162 emit_d8(cbuf, 8); | |
4163 | |
4164 // movsd [rsp], $src | |
4165 emit_opcode(cbuf, 0xF2); | |
4166 if (srcenc >= 8) { | |
4167 emit_opcode(cbuf, Assembler::REX_R); | |
4168 } | |
4169 emit_opcode(cbuf, 0x0F); | |
4170 emit_opcode(cbuf, 0x11); | |
4171 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
4172 | |
4173 // call d2l_fixup | |
4174 cbuf.set_inst_mark(); | |
4175 emit_opcode(cbuf, 0xE8); | |
4176 emit_d32_reloc(cbuf, | |
4177 (int) | |
4178 (StubRoutines::amd64::d2l_fixup() - cbuf.code_end() - 4), | |
4179 runtime_call_Relocation::spec(), | |
4180 RELOC_DISP32); | |
4181 | |
4182 // popq $dst | |
4183 if (dstenc >= 8) { | |
4184 emit_opcode(cbuf, Assembler::REX_B); | |
4185 } | |
4186 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
4187 | |
4188 // done: | |
4189 %} | |
4190 | |
4191 enc_class enc_membar_acquire | |
4192 %{ | |
4193 // [jk] not needed currently, if you enable this and it really | |
4194 // emits code don't forget to the remove the "size(0)" line in | |
4195 // membar_acquire() | |
4196 // MacroAssembler masm(&cbuf); | |
4197 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore | | |
4198 // Assembler::LoadLoad)); | |
4199 %} | |
4200 | |
4201 enc_class enc_membar_release | |
4202 %{ | |
4203 // [jk] not needed currently, if you enable this and it really | |
4204 // emits code don't forget to the remove the "size(0)" line in | |
4205 // membar_release() | |
4206 // MacroAssembler masm(&cbuf); | |
4207 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore | | |
4208 // Assembler::StoreStore)); | |
4209 %} | |
4210 | |
4211 enc_class enc_membar_volatile | |
4212 %{ | |
4213 MacroAssembler masm(&cbuf); | |
4214 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad | | |
4215 Assembler::StoreStore)); | |
4216 %} | |
4217 | |
4218 // Safepoint Poll. This polls the safepoint page, and causes an | |
4219 // exception if it is not readable. Unfortunately, it kills | |
4220 // RFLAGS in the process. | |
4221 enc_class enc_safepoint_poll | |
4222 %{ | |
4223 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
4224 // XXX reg_mem doesn't support RIP-relative addressing yet | |
4225 cbuf.set_inst_mark(); | |
4226 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX | |
4227 emit_opcode(cbuf, 0x85); // testl | |
4228 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
4229 // cbuf.inst_mark() is beginning of instruction | |
4230 emit_d32_reloc(cbuf, os::get_polling_page()); | |
4231 // relocInfo::poll_type, | |
4232 %} | |
4233 %} | |
4234 | |
4235 | |
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4236 |
0 | 4237 //----------FRAME-------------------------------------------------------------- |
4238 // Definition of frame structure and management information. | |
4239 // | |
4240 // S T A C K L A Y O U T Allocators stack-slot number | |
4241 // | (to get allocators register number | |
4242 // G Owned by | | v add OptoReg::stack0()) | |
4243 // r CALLER | | | |
4244 // o | +--------+ pad to even-align allocators stack-slot | |
4245 // w V | pad0 | numbers; owned by CALLER | |
4246 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
4247 // h ^ | in | 5 | |
4248 // | | args | 4 Holes in incoming args owned by SELF | |
4249 // | | | | 3 | |
4250 // | | +--------+ | |
4251 // V | | old out| Empty on Intel, window on Sparc | |
4252 // | old |preserve| Must be even aligned. | |
4253 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
4254 // | | in | 3 area for Intel ret address | |
4255 // Owned by |preserve| Empty on Sparc. | |
4256 // SELF +--------+ | |
4257 // | | pad2 | 2 pad to align old SP | |
4258 // | +--------+ 1 | |
4259 // | | locks | 0 | |
4260 // | +--------+----> OptoReg::stack0(), even aligned | |
4261 // | | pad1 | 11 pad to align new SP | |
4262 // | +--------+ | |
4263 // | | | 10 | |
4264 // | | spills | 9 spills | |
4265 // V | | 8 (pad0 slot for callee) | |
4266 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
4267 // ^ | out | 7 | |
4268 // | | args | 6 Holes in outgoing args owned by CALLEE | |
4269 // Owned by +--------+ | |
4270 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
4271 // | new |preserve| Must be even-aligned. | |
4272 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
4273 // | | | | |
4274 // | |
4275 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
4276 // known from SELF's arguments and the Java calling convention. | |
4277 // Region 6-7 is determined per call site. | |
4278 // Note 2: If the calling convention leaves holes in the incoming argument | |
4279 // area, those holes are owned by SELF. Holes in the outgoing area | |
4280 // are owned by the CALLEE. Holes should not be nessecary in the | |
4281 // incoming area, as the Java calling convention is completely under | |
4282 // the control of the AD file. Doubles can be sorted and packed to | |
4283 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
4284 // varargs C calling conventions. | |
4285 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
4286 // even aligned with pad0 as needed. | |
4287 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
4288 // region 6-11 is even aligned; it may be padded out more so that | |
4289 // the region from SP to FP meets the minimum stack alignment. | |
4290 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
4291 // alignment. Region 11, pad1, may be dynamically extended so that | |
4292 // SP meets the minimum alignment. | |
4293 | |
4294 frame | |
4295 %{ | |
4296 // What direction does stack grow in (assumed to be same for C & Java) | |
4297 stack_direction(TOWARDS_LOW); | |
4298 | |
4299 // These three registers define part of the calling convention | |
4300 // between compiled code and the interpreter. | |
4301 inline_cache_reg(RAX); // Inline Cache Register | |
4302 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
4303 // calling interpreter | |
4304 | |
4305 // Optional: name the operand used by cisc-spilling to access | |
4306 // [stack_pointer + offset] | |
4307 cisc_spilling_operand_name(indOffset32); | |
4308 | |
4309 // Number of stack slots consumed by locking an object | |
4310 sync_stack_slots(2); | |
4311 | |
4312 // Compiled code's Frame Pointer | |
4313 frame_pointer(RSP); | |
4314 | |
4315 // Interpreter stores its frame pointer in a register which is | |
4316 // stored to the stack by I2CAdaptors. | |
4317 // I2CAdaptors convert from interpreted java to compiled java. | |
4318 interpreter_frame_pointer(RBP); | |
4319 | |
4320 // Stack alignment requirement | |
4321 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
4322 | |
4323 // Number of stack slots between incoming argument block and the start of | |
4324 // a new frame. The PROLOG must add this many slots to the stack. The | |
4325 // EPILOG must remove this many slots. amd64 needs two slots for | |
4326 // return address. | |
4327 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
4328 | |
4329 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
4330 // for calls to C. Supports the var-args backing area for register parms. | |
4331 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
4332 | |
4333 // The after-PROLOG location of the return address. Location of | |
4334 // return address specifies a type (REG or STACK) and a number | |
4335 // representing the register number (i.e. - use a register name) or | |
4336 // stack slot. | |
4337 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
4338 // Otherwise, it is above the locks and verification slot and alignment word | |
4339 return_addr(STACK - 2 + | |
4340 round_to(2 + 2 * VerifyStackAtCalls + | |
4341 Compile::current()->fixed_slots(), | |
4342 WordsPerLong * 2)); | |
4343 | |
4344 // Body of function which returns an integer array locating | |
4345 // arguments either in registers or in stack slots. Passed an array | |
4346 // of ideal registers called "sig" and a "length" count. Stack-slot | |
4347 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
4348 // arguments for a CALLEE. Incoming stack arguments are | |
4349 // automatically biased by the preserve_stack_slots field above. | |
4350 | |
4351 calling_convention | |
4352 %{ | |
4353 // No difference between ingoing/outgoing just pass false | |
4354 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
4355 %} | |
4356 | |
4357 c_calling_convention | |
4358 %{ | |
4359 // This is obviously always outgoing | |
4360 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
4361 %} | |
4362 | |
4363 // Location of compiled Java return values. Same as C for now. | |
4364 return_value | |
4365 %{ | |
4366 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
4367 "only return normal values"); | |
4368 | |
4369 static const int lo[Op_RegL + 1] = { | |
4370 0, | |
4371 0, | |
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4372 RAX_num, // Op_RegN |
0 | 4373 RAX_num, // Op_RegI |
4374 RAX_num, // Op_RegP | |
4375 XMM0_num, // Op_RegF | |
4376 XMM0_num, // Op_RegD | |
4377 RAX_num // Op_RegL | |
4378 }; | |
4379 static const int hi[Op_RegL + 1] = { | |
4380 0, | |
4381 0, | |
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4382 OptoReg::Bad, // Op_RegN |
0 | 4383 OptoReg::Bad, // Op_RegI |
4384 RAX_H_num, // Op_RegP | |
4385 OptoReg::Bad, // Op_RegF | |
4386 XMM0_H_num, // Op_RegD | |
4387 RAX_H_num // Op_RegL | |
4388 }; | |
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4389 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
0 | 4390 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
4391 %} | |
4392 %} | |
4393 | |
4394 //----------ATTRIBUTES--------------------------------------------------------- | |
4395 //----------Operand Attributes------------------------------------------------- | |
4396 op_attrib op_cost(0); // Required cost attribute | |
4397 | |
4398 //----------Instruction Attributes--------------------------------------------- | |
4399 ins_attrib ins_cost(100); // Required cost attribute | |
4400 ins_attrib ins_size(8); // Required size attribute (in bits) | |
4401 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
4402 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
4403 // a non-matching short branch variant | |
4404 // of some long branch? | |
4405 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
4406 // be a power of 2) specifies the | |
4407 // alignment that some part of the | |
4408 // instruction (not necessarily the | |
4409 // start) requires. If > 1, a | |
4410 // compute_padding() function must be | |
4411 // provided for the instruction | |
4412 | |
4413 //----------OPERANDS----------------------------------------------------------- | |
4414 // Operand definitions must precede instruction definitions for correct parsing | |
4415 // in the ADLC because operands constitute user defined types which are used in | |
4416 // instruction definitions. | |
4417 | |
4418 //----------Simple Operands---------------------------------------------------- | |
4419 // Immediate Operands | |
4420 // Integer Immediate | |
4421 operand immI() | |
4422 %{ | |
4423 match(ConI); | |
4424 | |
4425 op_cost(10); | |
4426 format %{ %} | |
4427 interface(CONST_INTER); | |
4428 %} | |
4429 | |
4430 // Constant for test vs zero | |
4431 operand immI0() | |
4432 %{ | |
4433 predicate(n->get_int() == 0); | |
4434 match(ConI); | |
4435 | |
4436 op_cost(0); | |
4437 format %{ %} | |
4438 interface(CONST_INTER); | |
4439 %} | |
4440 | |
4441 // Constant for increment | |
4442 operand immI1() | |
4443 %{ | |
4444 predicate(n->get_int() == 1); | |
4445 match(ConI); | |
4446 | |
4447 op_cost(0); | |
4448 format %{ %} | |
4449 interface(CONST_INTER); | |
4450 %} | |
4451 | |
4452 // Constant for decrement | |
4453 operand immI_M1() | |
4454 %{ | |
4455 predicate(n->get_int() == -1); | |
4456 match(ConI); | |
4457 | |
4458 op_cost(0); | |
4459 format %{ %} | |
4460 interface(CONST_INTER); | |
4461 %} | |
4462 | |
4463 // Valid scale values for addressing modes | |
4464 operand immI2() | |
4465 %{ | |
4466 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
4467 match(ConI); | |
4468 | |
4469 format %{ %} | |
4470 interface(CONST_INTER); | |
4471 %} | |
4472 | |
4473 operand immI8() | |
4474 %{ | |
4475 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
4476 match(ConI); | |
4477 | |
4478 op_cost(5); | |
4479 format %{ %} | |
4480 interface(CONST_INTER); | |
4481 %} | |
4482 | |
4483 operand immI16() | |
4484 %{ | |
4485 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
4486 match(ConI); | |
4487 | |
4488 op_cost(10); | |
4489 format %{ %} | |
4490 interface(CONST_INTER); | |
4491 %} | |
4492 | |
4493 // Constant for long shifts | |
4494 operand immI_32() | |
4495 %{ | |
4496 predicate( n->get_int() == 32 ); | |
4497 match(ConI); | |
4498 | |
4499 op_cost(0); | |
4500 format %{ %} | |
4501 interface(CONST_INTER); | |
4502 %} | |
4503 | |
4504 // Constant for long shifts | |
4505 operand immI_64() | |
4506 %{ | |
4507 predicate( n->get_int() == 64 ); | |
4508 match(ConI); | |
4509 | |
4510 op_cost(0); | |
4511 format %{ %} | |
4512 interface(CONST_INTER); | |
4513 %} | |
4514 | |
4515 // Pointer Immediate | |
4516 operand immP() | |
4517 %{ | |
4518 match(ConP); | |
4519 | |
4520 op_cost(10); | |
4521 format %{ %} | |
4522 interface(CONST_INTER); | |
4523 %} | |
4524 | |
4525 // NULL Pointer Immediate | |
4526 operand immP0() | |
4527 %{ | |
4528 predicate(n->get_ptr() == 0); | |
4529 match(ConP); | |
4530 | |
4531 op_cost(5); | |
4532 format %{ %} | |
4533 interface(CONST_INTER); | |
4534 %} | |
4535 | |
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4536 // Pointer Immediate |
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4537 operand immN() %{ |
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4538 match(ConN); |
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4539 |
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4540 op_cost(10); |
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4541 format %{ %} |
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4542 interface(CONST_INTER); |
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4543 %} |
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4544 |
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4545 // NULL Pointer Immediate |
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4546 operand immN0() %{ |
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4547 predicate(n->get_narrowcon() == 0); |
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4548 match(ConN); |
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4549 |
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4550 op_cost(5); |
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4551 format %{ %} |
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4552 interface(CONST_INTER); |
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4553 %} |
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4554 |
0 | 4555 operand immP31() |
4556 %{ | |
4557 predicate(!n->as_Type()->type()->isa_oopptr() | |
4558 && (n->get_ptr() >> 31) == 0); | |
4559 match(ConP); | |
4560 | |
4561 op_cost(5); | |
4562 format %{ %} | |
4563 interface(CONST_INTER); | |
4564 %} | |
4565 | |
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4566 |
0 | 4567 // Long Immediate |
4568 operand immL() | |
4569 %{ | |
4570 match(ConL); | |
4571 | |
4572 op_cost(20); | |
4573 format %{ %} | |
4574 interface(CONST_INTER); | |
4575 %} | |
4576 | |
4577 // Long Immediate 8-bit | |
4578 operand immL8() | |
4579 %{ | |
4580 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
4581 match(ConL); | |
4582 | |
4583 op_cost(5); | |
4584 format %{ %} | |
4585 interface(CONST_INTER); | |
4586 %} | |
4587 | |
4588 // Long Immediate 32-bit unsigned | |
4589 operand immUL32() | |
4590 %{ | |
4591 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
4592 match(ConL); | |
4593 | |
4594 op_cost(10); | |
4595 format %{ %} | |
4596 interface(CONST_INTER); | |
4597 %} | |
4598 | |
4599 // Long Immediate 32-bit signed | |
4600 operand immL32() | |
4601 %{ | |
4602 predicate(n->get_long() == (int) (n->get_long())); | |
4603 match(ConL); | |
4604 | |
4605 op_cost(15); | |
4606 format %{ %} | |
4607 interface(CONST_INTER); | |
4608 %} | |
4609 | |
4610 // Long Immediate zero | |
4611 operand immL0() | |
4612 %{ | |
4613 predicate(n->get_long() == 0L); | |
4614 match(ConL); | |
4615 | |
4616 op_cost(10); | |
4617 format %{ %} | |
4618 interface(CONST_INTER); | |
4619 %} | |
4620 | |
4621 // Constant for increment | |
4622 operand immL1() | |
4623 %{ | |
4624 predicate(n->get_long() == 1); | |
4625 match(ConL); | |
4626 | |
4627 format %{ %} | |
4628 interface(CONST_INTER); | |
4629 %} | |
4630 | |
4631 // Constant for decrement | |
4632 operand immL_M1() | |
4633 %{ | |
4634 predicate(n->get_long() == -1); | |
4635 match(ConL); | |
4636 | |
4637 format %{ %} | |
4638 interface(CONST_INTER); | |
4639 %} | |
4640 | |
4641 // Long Immediate: the value 10 | |
4642 operand immL10() | |
4643 %{ | |
4644 predicate(n->get_long() == 10); | |
4645 match(ConL); | |
4646 | |
4647 format %{ %} | |
4648 interface(CONST_INTER); | |
4649 %} | |
4650 | |
4651 // Long immediate from 0 to 127. | |
4652 // Used for a shorter form of long mul by 10. | |
4653 operand immL_127() | |
4654 %{ | |
4655 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
4656 match(ConL); | |
4657 | |
4658 op_cost(10); | |
4659 format %{ %} | |
4660 interface(CONST_INTER); | |
4661 %} | |
4662 | |
4663 // Long Immediate: low 32-bit mask | |
4664 operand immL_32bits() | |
4665 %{ | |
4666 predicate(n->get_long() == 0xFFFFFFFFL); | |
4667 match(ConL); | |
4668 op_cost(20); | |
4669 | |
4670 format %{ %} | |
4671 interface(CONST_INTER); | |
4672 %} | |
4673 | |
4674 // Float Immediate zero | |
4675 operand immF0() | |
4676 %{ | |
4677 predicate(jint_cast(n->getf()) == 0); | |
4678 match(ConF); | |
4679 | |
4680 op_cost(5); | |
4681 format %{ %} | |
4682 interface(CONST_INTER); | |
4683 %} | |
4684 | |
4685 // Float Immediate | |
4686 operand immF() | |
4687 %{ | |
4688 match(ConF); | |
4689 | |
4690 op_cost(15); | |
4691 format %{ %} | |
4692 interface(CONST_INTER); | |
4693 %} | |
4694 | |
4695 // Double Immediate zero | |
4696 operand immD0() | |
4697 %{ | |
4698 predicate(jlong_cast(n->getd()) == 0); | |
4699 match(ConD); | |
4700 | |
4701 op_cost(5); | |
4702 format %{ %} | |
4703 interface(CONST_INTER); | |
4704 %} | |
4705 | |
4706 // Double Immediate | |
4707 operand immD() | |
4708 %{ | |
4709 match(ConD); | |
4710 | |
4711 op_cost(15); | |
4712 format %{ %} | |
4713 interface(CONST_INTER); | |
4714 %} | |
4715 | |
4716 // Immediates for special shifts (sign extend) | |
4717 | |
4718 // Constants for increment | |
4719 operand immI_16() | |
4720 %{ | |
4721 predicate(n->get_int() == 16); | |
4722 match(ConI); | |
4723 | |
4724 format %{ %} | |
4725 interface(CONST_INTER); | |
4726 %} | |
4727 | |
4728 operand immI_24() | |
4729 %{ | |
4730 predicate(n->get_int() == 24); | |
4731 match(ConI); | |
4732 | |
4733 format %{ %} | |
4734 interface(CONST_INTER); | |
4735 %} | |
4736 | |
4737 // Constant for byte-wide masking | |
4738 operand immI_255() | |
4739 %{ | |
4740 predicate(n->get_int() == 255); | |
4741 match(ConI); | |
4742 | |
4743 format %{ %} | |
4744 interface(CONST_INTER); | |
4745 %} | |
4746 | |
4747 // Constant for short-wide masking | |
4748 operand immI_65535() | |
4749 %{ | |
4750 predicate(n->get_int() == 65535); | |
4751 match(ConI); | |
4752 | |
4753 format %{ %} | |
4754 interface(CONST_INTER); | |
4755 %} | |
4756 | |
4757 // Constant for byte-wide masking | |
4758 operand immL_255() | |
4759 %{ | |
4760 predicate(n->get_long() == 255); | |
4761 match(ConL); | |
4762 | |
4763 format %{ %} | |
4764 interface(CONST_INTER); | |
4765 %} | |
4766 | |
4767 // Constant for short-wide masking | |
4768 operand immL_65535() | |
4769 %{ | |
4770 predicate(n->get_long() == 65535); | |
4771 match(ConL); | |
4772 | |
4773 format %{ %} | |
4774 interface(CONST_INTER); | |
4775 %} | |
4776 | |
4777 // Register Operands | |
4778 // Integer Register | |
4779 operand rRegI() | |
4780 %{ | |
4781 constraint(ALLOC_IN_RC(int_reg)); | |
4782 match(RegI); | |
4783 | |
4784 match(rax_RegI); | |
4785 match(rbx_RegI); | |
4786 match(rcx_RegI); | |
4787 match(rdx_RegI); | |
4788 match(rdi_RegI); | |
4789 | |
4790 format %{ %} | |
4791 interface(REG_INTER); | |
4792 %} | |
4793 | |
4794 // Special Registers | |
4795 operand rax_RegI() | |
4796 %{ | |
4797 constraint(ALLOC_IN_RC(int_rax_reg)); | |
4798 match(RegI); | |
4799 match(rRegI); | |
4800 | |
4801 format %{ "RAX" %} | |
4802 interface(REG_INTER); | |
4803 %} | |
4804 | |
4805 // Special Registers | |
4806 operand rbx_RegI() | |
4807 %{ | |
4808 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
4809 match(RegI); | |
4810 match(rRegI); | |
4811 | |
4812 format %{ "RBX" %} | |
4813 interface(REG_INTER); | |
4814 %} | |
4815 | |
4816 operand rcx_RegI() | |
4817 %{ | |
4818 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
4819 match(RegI); | |
4820 match(rRegI); | |
4821 | |
4822 format %{ "RCX" %} | |
4823 interface(REG_INTER); | |
4824 %} | |
4825 | |
4826 operand rdx_RegI() | |
4827 %{ | |
4828 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
4829 match(RegI); | |
4830 match(rRegI); | |
4831 | |
4832 format %{ "RDX" %} | |
4833 interface(REG_INTER); | |
4834 %} | |
4835 | |
4836 operand rdi_RegI() | |
4837 %{ | |
4838 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
4839 match(RegI); | |
4840 match(rRegI); | |
4841 | |
4842 format %{ "RDI" %} | |
4843 interface(REG_INTER); | |
4844 %} | |
4845 | |
4846 operand no_rcx_RegI() | |
4847 %{ | |
4848 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
4849 match(RegI); | |
4850 match(rax_RegI); | |
4851 match(rbx_RegI); | |
4852 match(rdx_RegI); | |
4853 match(rdi_RegI); | |
4854 | |
4855 format %{ %} | |
4856 interface(REG_INTER); | |
4857 %} | |
4858 | |
4859 operand no_rax_rdx_RegI() | |
4860 %{ | |
4861 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
4862 match(RegI); | |
4863 match(rbx_RegI); | |
4864 match(rcx_RegI); | |
4865 match(rdi_RegI); | |
4866 | |
4867 format %{ %} | |
4868 interface(REG_INTER); | |
4869 %} | |
4870 | |
4871 // Pointer Register | |
4872 operand any_RegP() | |
4873 %{ | |
4874 constraint(ALLOC_IN_RC(any_reg)); | |
4875 match(RegP); | |
4876 match(rax_RegP); | |
4877 match(rbx_RegP); | |
4878 match(rdi_RegP); | |
4879 match(rsi_RegP); | |
4880 match(rbp_RegP); | |
4881 match(r15_RegP); | |
4882 match(rRegP); | |
4883 | |
4884 format %{ %} | |
4885 interface(REG_INTER); | |
4886 %} | |
4887 | |
4888 operand rRegP() | |
4889 %{ | |
4890 constraint(ALLOC_IN_RC(ptr_reg)); | |
4891 match(RegP); | |
4892 match(rax_RegP); | |
4893 match(rbx_RegP); | |
4894 match(rdi_RegP); | |
4895 match(rsi_RegP); | |
4896 match(rbp_RegP); | |
4897 match(r15_RegP); // See Q&A below about r15_RegP. | |
4898 | |
4899 format %{ %} | |
4900 interface(REG_INTER); | |
4901 %} | |
4902 | |
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4903 |
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4904 operand r12RegL() %{ |
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4905 constraint(ALLOC_IN_RC(long_r12_reg)); |
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4906 match(RegL); |
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4907 |
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4908 format %{ %} |
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4909 interface(REG_INTER); |
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4910 %} |
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4911 |
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4912 operand rRegN() %{ |
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4913 constraint(ALLOC_IN_RC(int_reg)); |
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4914 match(RegN); |
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4915 |
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4916 format %{ %} |
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4917 interface(REG_INTER); |
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4918 %} |
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4919 |
0 | 4920 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
4921 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
4922 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
4923 // The output of an instruction is controlled by the allocator, which respects | |
4924 // register class masks, not match rules. Unless an instruction mentions | |
4925 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
4926 // by the allocator as an input. | |
4927 | |
4928 operand no_rax_RegP() | |
4929 %{ | |
4930 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
4931 match(RegP); | |
4932 match(rbx_RegP); | |
4933 match(rsi_RegP); | |
4934 match(rdi_RegP); | |
4935 | |
4936 format %{ %} | |
4937 interface(REG_INTER); | |
4938 %} | |
4939 | |
4940 operand no_rbp_RegP() | |
4941 %{ | |
4942 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
4943 match(RegP); | |
4944 match(rbx_RegP); | |
4945 match(rsi_RegP); | |
4946 match(rdi_RegP); | |
4947 | |
4948 format %{ %} | |
4949 interface(REG_INTER); | |
4950 %} | |
4951 | |
4952 operand no_rax_rbx_RegP() | |
4953 %{ | |
4954 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
4955 match(RegP); | |
4956 match(rsi_RegP); | |
4957 match(rdi_RegP); | |
4958 | |
4959 format %{ %} | |
4960 interface(REG_INTER); | |
4961 %} | |
4962 | |
4963 // Special Registers | |
4964 // Return a pointer value | |
4965 operand rax_RegP() | |
4966 %{ | |
4967 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
4968 match(RegP); | |
4969 match(rRegP); | |
4970 | |
4971 format %{ %} | |
4972 interface(REG_INTER); | |
4973 %} | |
4974 | |
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4975 // Special Registers |
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4976 // Return a compressed pointer value |
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4977 operand rax_RegN() |
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4978 %{ |
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4979 constraint(ALLOC_IN_RC(int_rax_reg)); |
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4980 match(RegN); |
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4981 match(rRegN); |
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4982 |
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4983 format %{ %} |
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4984 interface(REG_INTER); |
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4985 %} |
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4986 |
0 | 4987 // Used in AtomicAdd |
4988 operand rbx_RegP() | |
4989 %{ | |
4990 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
4991 match(RegP); | |
4992 match(rRegP); | |
4993 | |
4994 format %{ %} | |
4995 interface(REG_INTER); | |
4996 %} | |
4997 | |
4998 operand rsi_RegP() | |
4999 %{ | |
5000 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
5001 match(RegP); | |
5002 match(rRegP); | |
5003 | |
5004 format %{ %} | |
5005 interface(REG_INTER); | |
5006 %} | |
5007 | |
5008 // Used in rep stosq | |
5009 operand rdi_RegP() | |
5010 %{ | |
5011 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
5012 match(RegP); | |
5013 match(rRegP); | |
5014 | |
5015 format %{ %} | |
5016 interface(REG_INTER); | |
5017 %} | |
5018 | |
5019 operand rbp_RegP() | |
5020 %{ | |
5021 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
5022 match(RegP); | |
5023 match(rRegP); | |
5024 | |
5025 format %{ %} | |
5026 interface(REG_INTER); | |
5027 %} | |
5028 | |
5029 operand r15_RegP() | |
5030 %{ | |
5031 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
5032 match(RegP); | |
5033 match(rRegP); | |
5034 | |
5035 format %{ %} | |
5036 interface(REG_INTER); | |
5037 %} | |
5038 | |
5039 operand rRegL() | |
5040 %{ | |
5041 constraint(ALLOC_IN_RC(long_reg)); | |
5042 match(RegL); | |
5043 match(rax_RegL); | |
5044 match(rdx_RegL); | |
5045 | |
5046 format %{ %} | |
5047 interface(REG_INTER); | |
5048 %} | |
5049 | |
5050 // Special Registers | |
5051 operand no_rax_rdx_RegL() | |
5052 %{ | |
5053 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
5054 match(RegL); | |
5055 match(rRegL); | |
5056 | |
5057 format %{ %} | |
5058 interface(REG_INTER); | |
5059 %} | |
5060 | |
5061 operand no_rax_RegL() | |
5062 %{ | |
5063 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
5064 match(RegL); | |
5065 match(rRegL); | |
5066 match(rdx_RegL); | |
5067 | |
5068 format %{ %} | |
5069 interface(REG_INTER); | |
5070 %} | |
5071 | |
5072 operand no_rcx_RegL() | |
5073 %{ | |
5074 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
5075 match(RegL); | |
5076 match(rRegL); | |
5077 | |
5078 format %{ %} | |
5079 interface(REG_INTER); | |
5080 %} | |
5081 | |
5082 operand rax_RegL() | |
5083 %{ | |
5084 constraint(ALLOC_IN_RC(long_rax_reg)); | |
5085 match(RegL); | |
5086 match(rRegL); | |
5087 | |
5088 format %{ "RAX" %} | |
5089 interface(REG_INTER); | |
5090 %} | |
5091 | |
5092 operand rcx_RegL() | |
5093 %{ | |
5094 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
5095 match(RegL); | |
5096 match(rRegL); | |
5097 | |
5098 format %{ %} | |
5099 interface(REG_INTER); | |
5100 %} | |
5101 | |
5102 operand rdx_RegL() | |
5103 %{ | |
5104 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
5105 match(RegL); | |
5106 match(rRegL); | |
5107 | |
5108 format %{ %} | |
5109 interface(REG_INTER); | |
5110 %} | |
5111 | |
5112 // Flags register, used as output of compare instructions | |
5113 operand rFlagsReg() | |
5114 %{ | |
5115 constraint(ALLOC_IN_RC(int_flags)); | |
5116 match(RegFlags); | |
5117 | |
5118 format %{ "RFLAGS" %} | |
5119 interface(REG_INTER); | |
5120 %} | |
5121 | |
5122 // Flags register, used as output of FLOATING POINT compare instructions | |
5123 operand rFlagsRegU() | |
5124 %{ | |
5125 constraint(ALLOC_IN_RC(int_flags)); | |
5126 match(RegFlags); | |
5127 | |
5128 format %{ "RFLAGS_U" %} | |
5129 interface(REG_INTER); | |
5130 %} | |
5131 | |
5132 // Float register operands | |
5133 operand regF() | |
5134 %{ | |
5135 constraint(ALLOC_IN_RC(float_reg)); | |
5136 match(RegF); | |
5137 | |
5138 format %{ %} | |
5139 interface(REG_INTER); | |
5140 %} | |
5141 | |
5142 // Double register operands | |
5143 operand regD() | |
5144 %{ | |
5145 constraint(ALLOC_IN_RC(double_reg)); | |
5146 match(RegD); | |
5147 | |
5148 format %{ %} | |
5149 interface(REG_INTER); | |
5150 %} | |
5151 | |
5152 | |
5153 //----------Memory Operands---------------------------------------------------- | |
5154 // Direct Memory Operand | |
5155 // operand direct(immP addr) | |
5156 // %{ | |
5157 // match(addr); | |
5158 | |
5159 // format %{ "[$addr]" %} | |
5160 // interface(MEMORY_INTER) %{ | |
5161 // base(0xFFFFFFFF); | |
5162 // index(0x4); | |
5163 // scale(0x0); | |
5164 // disp($addr); | |
5165 // %} | |
5166 // %} | |
5167 | |
5168 // Indirect Memory Operand | |
5169 operand indirect(any_RegP reg) | |
5170 %{ | |
5171 constraint(ALLOC_IN_RC(ptr_reg)); | |
5172 match(reg); | |
5173 | |
5174 format %{ "[$reg]" %} | |
5175 interface(MEMORY_INTER) %{ | |
5176 base($reg); | |
5177 index(0x4); | |
5178 scale(0x0); | |
5179 disp(0x0); | |
5180 %} | |
5181 %} | |
5182 | |
5183 // Indirect Memory Plus Short Offset Operand | |
5184 operand indOffset8(any_RegP reg, immL8 off) | |
5185 %{ | |
5186 constraint(ALLOC_IN_RC(ptr_reg)); | |
5187 match(AddP reg off); | |
5188 | |
5189 format %{ "[$reg + $off (8-bit)]" %} | |
5190 interface(MEMORY_INTER) %{ | |
5191 base($reg); | |
5192 index(0x4); | |
5193 scale(0x0); | |
5194 disp($off); | |
5195 %} | |
5196 %} | |
5197 | |
5198 // Indirect Memory Plus Long Offset Operand | |
5199 operand indOffset32(any_RegP reg, immL32 off) | |
5200 %{ | |
5201 constraint(ALLOC_IN_RC(ptr_reg)); | |
5202 match(AddP reg off); | |
5203 | |
5204 format %{ "[$reg + $off (32-bit)]" %} | |
5205 interface(MEMORY_INTER) %{ | |
5206 base($reg); | |
5207 index(0x4); | |
5208 scale(0x0); | |
5209 disp($off); | |
5210 %} | |
5211 %} | |
5212 | |
5213 // Indirect Memory Plus Index Register Plus Offset Operand | |
5214 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
5215 %{ | |
5216 constraint(ALLOC_IN_RC(ptr_reg)); | |
5217 match(AddP (AddP reg lreg) off); | |
5218 | |
5219 op_cost(10); | |
5220 format %{"[$reg + $off + $lreg]" %} | |
5221 interface(MEMORY_INTER) %{ | |
5222 base($reg); | |
5223 index($lreg); | |
5224 scale(0x0); | |
5225 disp($off); | |
5226 %} | |
5227 %} | |
5228 | |
5229 // Indirect Memory Plus Index Register Plus Offset Operand | |
5230 operand indIndex(any_RegP reg, rRegL lreg) | |
5231 %{ | |
5232 constraint(ALLOC_IN_RC(ptr_reg)); | |
5233 match(AddP reg lreg); | |
5234 | |
5235 op_cost(10); | |
5236 format %{"[$reg + $lreg]" %} | |
5237 interface(MEMORY_INTER) %{ | |
5238 base($reg); | |
5239 index($lreg); | |
5240 scale(0x0); | |
5241 disp(0x0); | |
5242 %} | |
5243 %} | |
5244 | |
5245 // Indirect Memory Times Scale Plus Index Register | |
5246 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
5247 %{ | |
5248 constraint(ALLOC_IN_RC(ptr_reg)); | |
5249 match(AddP reg (LShiftL lreg scale)); | |
5250 | |
5251 op_cost(10); | |
5252 format %{"[$reg + $lreg << $scale]" %} | |
5253 interface(MEMORY_INTER) %{ | |
5254 base($reg); | |
5255 index($lreg); | |
5256 scale($scale); | |
5257 disp(0x0); | |
5258 %} | |
5259 %} | |
5260 | |
5261 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
5262 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
5263 %{ | |
5264 constraint(ALLOC_IN_RC(ptr_reg)); | |
5265 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
5266 | |
5267 op_cost(10); | |
5268 format %{"[$reg + $off + $lreg << $scale]" %} | |
5269 interface(MEMORY_INTER) %{ | |
5270 base($reg); | |
5271 index($lreg); | |
5272 scale($scale); | |
5273 disp($off); | |
5274 %} | |
5275 %} | |
5276 | |
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5277 // Indirect Narrow Oop Plus Offset Operand |
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5278 operand indNarrowOopOffset(rRegN src, immL32 off) %{ |
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5279 constraint(ALLOC_IN_RC(ptr_reg)); |
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5280 match(AddP (DecodeN src) off); |
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5281 |
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5282 op_cost(10); |
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5283 format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %} |
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5284 interface(MEMORY_INTER) %{ |
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5285 base(0xc); // R12 |
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5286 index($src); |
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5287 scale(0x3); |
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5288 disp($off); |
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5289 %} |
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5290 %} |
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5291 |
0 | 5292 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
5293 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
5294 %{ | |
5295 constraint(ALLOC_IN_RC(ptr_reg)); | |
5296 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
5297 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
5298 | |
5299 op_cost(10); | |
5300 format %{"[$reg + $off + $idx << $scale]" %} | |
5301 interface(MEMORY_INTER) %{ | |
5302 base($reg); | |
5303 index($idx); | |
5304 scale($scale); | |
5305 disp($off); | |
5306 %} | |
5307 %} | |
5308 | |
5309 //----------Special Memory Operands-------------------------------------------- | |
5310 // Stack Slot Operand - This operand is used for loading and storing temporary | |
5311 // values on the stack where a match requires a value to | |
5312 // flow through memory. | |
5313 operand stackSlotP(sRegP reg) | |
5314 %{ | |
5315 constraint(ALLOC_IN_RC(stack_slots)); | |
5316 // No match rule because this operand is only generated in matching | |
5317 | |
5318 format %{ "[$reg]" %} | |
5319 interface(MEMORY_INTER) %{ | |
5320 base(0x4); // RSP | |
5321 index(0x4); // No Index | |
5322 scale(0x0); // No Scale | |
5323 disp($reg); // Stack Offset | |
5324 %} | |
5325 %} | |
5326 | |
5327 operand stackSlotI(sRegI reg) | |
5328 %{ | |
5329 constraint(ALLOC_IN_RC(stack_slots)); | |
5330 // No match rule because this operand is only generated in matching | |
5331 | |
5332 format %{ "[$reg]" %} | |
5333 interface(MEMORY_INTER) %{ | |
5334 base(0x4); // RSP | |
5335 index(0x4); // No Index | |
5336 scale(0x0); // No Scale | |
5337 disp($reg); // Stack Offset | |
5338 %} | |
5339 %} | |
5340 | |
5341 operand stackSlotF(sRegF reg) | |
5342 %{ | |
5343 constraint(ALLOC_IN_RC(stack_slots)); | |
5344 // No match rule because this operand is only generated in matching | |
5345 | |
5346 format %{ "[$reg]" %} | |
5347 interface(MEMORY_INTER) %{ | |
5348 base(0x4); // RSP | |
5349 index(0x4); // No Index | |
5350 scale(0x0); // No Scale | |
5351 disp($reg); // Stack Offset | |
5352 %} | |
5353 %} | |
5354 | |
5355 operand stackSlotD(sRegD reg) | |
5356 %{ | |
5357 constraint(ALLOC_IN_RC(stack_slots)); | |
5358 // No match rule because this operand is only generated in matching | |
5359 | |
5360 format %{ "[$reg]" %} | |
5361 interface(MEMORY_INTER) %{ | |
5362 base(0x4); // RSP | |
5363 index(0x4); // No Index | |
5364 scale(0x0); // No Scale | |
5365 disp($reg); // Stack Offset | |
5366 %} | |
5367 %} | |
5368 operand stackSlotL(sRegL reg) | |
5369 %{ | |
5370 constraint(ALLOC_IN_RC(stack_slots)); | |
5371 // No match rule because this operand is only generated in matching | |
5372 | |
5373 format %{ "[$reg]" %} | |
5374 interface(MEMORY_INTER) %{ | |
5375 base(0x4); // RSP | |
5376 index(0x4); // No Index | |
5377 scale(0x0); // No Scale | |
5378 disp($reg); // Stack Offset | |
5379 %} | |
5380 %} | |
5381 | |
5382 //----------Conditional Branch Operands---------------------------------------- | |
5383 // Comparison Op - This is the operation of the comparison, and is limited to | |
5384 // the following set of codes: | |
5385 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
5386 // | |
5387 // Other attributes of the comparison, such as unsignedness, are specified | |
5388 // by the comparison instruction that sets a condition code flags register. | |
5389 // That result is represented by a flags operand whose subtype is appropriate | |
5390 // to the unsignedness (etc.) of the comparison. | |
5391 // | |
5392 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
5393 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
5394 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
5395 | |
5396 // Comparision Code | |
5397 operand cmpOp() | |
5398 %{ | |
5399 match(Bool); | |
5400 | |
5401 format %{ "" %} | |
5402 interface(COND_INTER) %{ | |
5403 equal(0x4); | |
5404 not_equal(0x5); | |
5405 less(0xC); | |
5406 greater_equal(0xD); | |
5407 less_equal(0xE); | |
5408 greater(0xF); | |
5409 %} | |
5410 %} | |
5411 | |
5412 // Comparison Code, unsigned compare. Used by FP also, with | |
5413 // C2 (unordered) turned into GT or LT already. The other bits | |
5414 // C0 and C3 are turned into Carry & Zero flags. | |
5415 operand cmpOpU() | |
5416 %{ | |
5417 match(Bool); | |
5418 | |
5419 format %{ "" %} | |
5420 interface(COND_INTER) %{ | |
5421 equal(0x4); | |
5422 not_equal(0x5); | |
5423 less(0x2); | |
5424 greater_equal(0x3); | |
5425 less_equal(0x6); | |
5426 greater(0x7); | |
5427 %} | |
5428 %} | |
5429 | |
5430 | |
5431 //----------OPERAND CLASSES---------------------------------------------------- | |
5432 // Operand Classes are groups of operands that are used as to simplify | |
5433 // instruction definitions by not requiring the AD writer to specify seperate | |
5434 // instructions for every form of operand when the instruction accepts | |
5435 // multiple operand types with the same basic encoding and format. The classic | |
5436 // case of this is memory operands. | |
5437 | |
5438 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
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5439 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
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5440 indNarrowOopOffset); |
0 | 5441 |
5442 //----------PIPELINE----------------------------------------------------------- | |
5443 // Rules which define the behavior of the target architectures pipeline. | |
5444 pipeline %{ | |
5445 | |
5446 //----------ATTRIBUTES--------------------------------------------------------- | |
5447 attributes %{ | |
5448 variable_size_instructions; // Fixed size instructions | |
5449 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
5450 instruction_unit_size = 1; // An instruction is 1 bytes long | |
5451 instruction_fetch_unit_size = 16; // The processor fetches one line | |
5452 instruction_fetch_units = 1; // of 16 bytes | |
5453 | |
5454 // List of nop instructions | |
5455 nops( MachNop ); | |
5456 %} | |
5457 | |
5458 //----------RESOURCES---------------------------------------------------------- | |
5459 // Resources are the functional units available to the machine | |
5460 | |
5461 // Generic P2/P3 pipeline | |
5462 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
5463 // 3 instructions decoded per cycle. | |
5464 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
5465 // 3 ALU op, only ALU0 handles mul instructions. | |
5466 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
5467 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
5468 BR, FPU, | |
5469 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
5470 | |
5471 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
5472 // Pipeline Description specifies the stages in the machine's pipeline | |
5473 | |
5474 // Generic P2/P3 pipeline | |
5475 pipe_desc(S0, S1, S2, S3, S4, S5); | |
5476 | |
5477 //----------PIPELINE CLASSES--------------------------------------------------- | |
5478 // Pipeline Classes describe the stages in which input and output are | |
5479 // referenced by the hardware pipeline. | |
5480 | |
5481 // Naming convention: ialu or fpu | |
5482 // Then: _reg | |
5483 // Then: _reg if there is a 2nd register | |
5484 // Then: _long if it's a pair of instructions implementing a long | |
5485 // Then: _fat if it requires the big decoder | |
5486 // Or: _mem if it requires the big decoder and a memory unit. | |
5487 | |
5488 // Integer ALU reg operation | |
5489 pipe_class ialu_reg(rRegI dst) | |
5490 %{ | |
5491 single_instruction; | |
5492 dst : S4(write); | |
5493 dst : S3(read); | |
5494 DECODE : S0; // any decoder | |
5495 ALU : S3; // any alu | |
5496 %} | |
5497 | |
5498 // Long ALU reg operation | |
5499 pipe_class ialu_reg_long(rRegL dst) | |
5500 %{ | |
5501 instruction_count(2); | |
5502 dst : S4(write); | |
5503 dst : S3(read); | |
5504 DECODE : S0(2); // any 2 decoders | |
5505 ALU : S3(2); // both alus | |
5506 %} | |
5507 | |
5508 // Integer ALU reg operation using big decoder | |
5509 pipe_class ialu_reg_fat(rRegI dst) | |
5510 %{ | |
5511 single_instruction; | |
5512 dst : S4(write); | |
5513 dst : S3(read); | |
5514 D0 : S0; // big decoder only | |
5515 ALU : S3; // any alu | |
5516 %} | |
5517 | |
5518 // Long ALU reg operation using big decoder | |
5519 pipe_class ialu_reg_long_fat(rRegL dst) | |
5520 %{ | |
5521 instruction_count(2); | |
5522 dst : S4(write); | |
5523 dst : S3(read); | |
5524 D0 : S0(2); // big decoder only; twice | |
5525 ALU : S3(2); // any 2 alus | |
5526 %} | |
5527 | |
5528 // Integer ALU reg-reg operation | |
5529 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
5530 %{ | |
5531 single_instruction; | |
5532 dst : S4(write); | |
5533 src : S3(read); | |
5534 DECODE : S0; // any decoder | |
5535 ALU : S3; // any alu | |
5536 %} | |
5537 | |
5538 // Long ALU reg-reg operation | |
5539 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
5540 %{ | |
5541 instruction_count(2); | |
5542 dst : S4(write); | |
5543 src : S3(read); | |
5544 DECODE : S0(2); // any 2 decoders | |
5545 ALU : S3(2); // both alus | |
5546 %} | |
5547 | |
5548 // Integer ALU reg-reg operation | |
5549 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
5550 %{ | |
5551 single_instruction; | |
5552 dst : S4(write); | |
5553 src : S3(read); | |
5554 D0 : S0; // big decoder only | |
5555 ALU : S3; // any alu | |
5556 %} | |
5557 | |
5558 // Long ALU reg-reg operation | |
5559 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
5560 %{ | |
5561 instruction_count(2); | |
5562 dst : S4(write); | |
5563 src : S3(read); | |
5564 D0 : S0(2); // big decoder only; twice | |
5565 ALU : S3(2); // both alus | |
5566 %} | |
5567 | |
5568 // Integer ALU reg-mem operation | |
5569 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
5570 %{ | |
5571 single_instruction; | |
5572 dst : S5(write); | |
5573 mem : S3(read); | |
5574 D0 : S0; // big decoder only | |
5575 ALU : S4; // any alu | |
5576 MEM : S3; // any mem | |
5577 %} | |
5578 | |
5579 // Integer mem operation (prefetch) | |
5580 pipe_class ialu_mem(memory mem) | |
5581 %{ | |
5582 single_instruction; | |
5583 mem : S3(read); | |
5584 D0 : S0; // big decoder only | |
5585 MEM : S3; // any mem | |
5586 %} | |
5587 | |
5588 // Integer Store to Memory | |
5589 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
5590 %{ | |
5591 single_instruction; | |
5592 mem : S3(read); | |
5593 src : S5(read); | |
5594 D0 : S0; // big decoder only | |
5595 ALU : S4; // any alu | |
5596 MEM : S3; | |
5597 %} | |
5598 | |
5599 // // Long Store to Memory | |
5600 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
5601 // %{ | |
5602 // instruction_count(2); | |
5603 // mem : S3(read); | |
5604 // src : S5(read); | |
5605 // D0 : S0(2); // big decoder only; twice | |
5606 // ALU : S4(2); // any 2 alus | |
5607 // MEM : S3(2); // Both mems | |
5608 // %} | |
5609 | |
5610 // Integer Store to Memory | |
5611 pipe_class ialu_mem_imm(memory mem) | |
5612 %{ | |
5613 single_instruction; | |
5614 mem : S3(read); | |
5615 D0 : S0; // big decoder only | |
5616 ALU : S4; // any alu | |
5617 MEM : S3; | |
5618 %} | |
5619 | |
5620 // Integer ALU0 reg-reg operation | |
5621 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
5622 %{ | |
5623 single_instruction; | |
5624 dst : S4(write); | |
5625 src : S3(read); | |
5626 D0 : S0; // Big decoder only | |
5627 ALU0 : S3; // only alu0 | |
5628 %} | |
5629 | |
5630 // Integer ALU0 reg-mem operation | |
5631 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
5632 %{ | |
5633 single_instruction; | |
5634 dst : S5(write); | |
5635 mem : S3(read); | |
5636 D0 : S0; // big decoder only | |
5637 ALU0 : S4; // ALU0 only | |
5638 MEM : S3; // any mem | |
5639 %} | |
5640 | |
5641 // Integer ALU reg-reg operation | |
5642 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
5643 %{ | |
5644 single_instruction; | |
5645 cr : S4(write); | |
5646 src1 : S3(read); | |
5647 src2 : S3(read); | |
5648 DECODE : S0; // any decoder | |
5649 ALU : S3; // any alu | |
5650 %} | |
5651 | |
5652 // Integer ALU reg-imm operation | |
5653 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
5654 %{ | |
5655 single_instruction; | |
5656 cr : S4(write); | |
5657 src1 : S3(read); | |
5658 DECODE : S0; // any decoder | |
5659 ALU : S3; // any alu | |
5660 %} | |
5661 | |
5662 // Integer ALU reg-mem operation | |
5663 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
5664 %{ | |
5665 single_instruction; | |
5666 cr : S4(write); | |
5667 src1 : S3(read); | |
5668 src2 : S3(read); | |
5669 D0 : S0; // big decoder only | |
5670 ALU : S4; // any alu | |
5671 MEM : S3; | |
5672 %} | |
5673 | |
5674 // Conditional move reg-reg | |
5675 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
5676 %{ | |
5677 instruction_count(4); | |
5678 y : S4(read); | |
5679 q : S3(read); | |
5680 p : S3(read); | |
5681 DECODE : S0(4); // any decoder | |
5682 %} | |
5683 | |
5684 // Conditional move reg-reg | |
5685 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
5686 %{ | |
5687 single_instruction; | |
5688 dst : S4(write); | |
5689 src : S3(read); | |
5690 cr : S3(read); | |
5691 DECODE : S0; // any decoder | |
5692 %} | |
5693 | |
5694 // Conditional move reg-mem | |
5695 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
5696 %{ | |
5697 single_instruction; | |
5698 dst : S4(write); | |
5699 src : S3(read); | |
5700 cr : S3(read); | |
5701 DECODE : S0; // any decoder | |
5702 MEM : S3; | |
5703 %} | |
5704 | |
5705 // Conditional move reg-reg long | |
5706 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
5707 %{ | |
5708 single_instruction; | |
5709 dst : S4(write); | |
5710 src : S3(read); | |
5711 cr : S3(read); | |
5712 DECODE : S0(2); // any 2 decoders | |
5713 %} | |
5714 | |
5715 // XXX | |
5716 // // Conditional move double reg-reg | |
5717 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
5718 // %{ | |
5719 // single_instruction; | |
5720 // dst : S4(write); | |
5721 // src : S3(read); | |
5722 // cr : S3(read); | |
5723 // DECODE : S0; // any decoder | |
5724 // %} | |
5725 | |
5726 // Float reg-reg operation | |
5727 pipe_class fpu_reg(regD dst) | |
5728 %{ | |
5729 instruction_count(2); | |
5730 dst : S3(read); | |
5731 DECODE : S0(2); // any 2 decoders | |
5732 FPU : S3; | |
5733 %} | |
5734 | |
5735 // Float reg-reg operation | |
5736 pipe_class fpu_reg_reg(regD dst, regD src) | |
5737 %{ | |
5738 instruction_count(2); | |
5739 dst : S4(write); | |
5740 src : S3(read); | |
5741 DECODE : S0(2); // any 2 decoders | |
5742 FPU : S3; | |
5743 %} | |
5744 | |
5745 // Float reg-reg operation | |
5746 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
5747 %{ | |
5748 instruction_count(3); | |
5749 dst : S4(write); | |
5750 src1 : S3(read); | |
5751 src2 : S3(read); | |
5752 DECODE : S0(3); // any 3 decoders | |
5753 FPU : S3(2); | |
5754 %} | |
5755 | |
5756 // Float reg-reg operation | |
5757 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
5758 %{ | |
5759 instruction_count(4); | |
5760 dst : S4(write); | |
5761 src1 : S3(read); | |
5762 src2 : S3(read); | |
5763 src3 : S3(read); | |
5764 DECODE : S0(4); // any 3 decoders | |
5765 FPU : S3(2); | |
5766 %} | |
5767 | |
5768 // Float reg-reg operation | |
5769 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
5770 %{ | |
5771 instruction_count(4); | |
5772 dst : S4(write); | |
5773 src1 : S3(read); | |
5774 src2 : S3(read); | |
5775 src3 : S3(read); | |
5776 DECODE : S1(3); // any 3 decoders | |
5777 D0 : S0; // Big decoder only | |
5778 FPU : S3(2); | |
5779 MEM : S3; | |
5780 %} | |
5781 | |
5782 // Float reg-mem operation | |
5783 pipe_class fpu_reg_mem(regD dst, memory mem) | |
5784 %{ | |
5785 instruction_count(2); | |
5786 dst : S5(write); | |
5787 mem : S3(read); | |
5788 D0 : S0; // big decoder only | |
5789 DECODE : S1; // any decoder for FPU POP | |
5790 FPU : S4; | |
5791 MEM : S3; // any mem | |
5792 %} | |
5793 | |
5794 // Float reg-mem operation | |
5795 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
5796 %{ | |
5797 instruction_count(3); | |
5798 dst : S5(write); | |
5799 src1 : S3(read); | |
5800 mem : S3(read); | |
5801 D0 : S0; // big decoder only | |
5802 DECODE : S1(2); // any decoder for FPU POP | |
5803 FPU : S4; | |
5804 MEM : S3; // any mem | |
5805 %} | |
5806 | |
5807 // Float mem-reg operation | |
5808 pipe_class fpu_mem_reg(memory mem, regD src) | |
5809 %{ | |
5810 instruction_count(2); | |
5811 src : S5(read); | |
5812 mem : S3(read); | |
5813 DECODE : S0; // any decoder for FPU PUSH | |
5814 D0 : S1; // big decoder only | |
5815 FPU : S4; | |
5816 MEM : S3; // any mem | |
5817 %} | |
5818 | |
5819 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
5820 %{ | |
5821 instruction_count(3); | |
5822 src1 : S3(read); | |
5823 src2 : S3(read); | |
5824 mem : S3(read); | |
5825 DECODE : S0(2); // any decoder for FPU PUSH | |
5826 D0 : S1; // big decoder only | |
5827 FPU : S4; | |
5828 MEM : S3; // any mem | |
5829 %} | |
5830 | |
5831 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
5832 %{ | |
5833 instruction_count(3); | |
5834 src1 : S3(read); | |
5835 src2 : S3(read); | |
5836 mem : S4(read); | |
5837 DECODE : S0; // any decoder for FPU PUSH | |
5838 D0 : S0(2); // big decoder only | |
5839 FPU : S4; | |
5840 MEM : S3(2); // any mem | |
5841 %} | |
5842 | |
5843 pipe_class fpu_mem_mem(memory dst, memory src1) | |
5844 %{ | |
5845 instruction_count(2); | |
5846 src1 : S3(read); | |
5847 dst : S4(read); | |
5848 D0 : S0(2); // big decoder only | |
5849 MEM : S3(2); // any mem | |
5850 %} | |
5851 | |
5852 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
5853 %{ | |
5854 instruction_count(3); | |
5855 src1 : S3(read); | |
5856 src2 : S3(read); | |
5857 dst : S4(read); | |
5858 D0 : S0(3); // big decoder only | |
5859 FPU : S4; | |
5860 MEM : S3(3); // any mem | |
5861 %} | |
5862 | |
5863 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
5864 %{ | |
5865 instruction_count(3); | |
5866 src1 : S4(read); | |
5867 mem : S4(read); | |
5868 DECODE : S0; // any decoder for FPU PUSH | |
5869 D0 : S0(2); // big decoder only | |
5870 FPU : S4; | |
5871 MEM : S3(2); // any mem | |
5872 %} | |
5873 | |
5874 // Float load constant | |
5875 pipe_class fpu_reg_con(regD dst) | |
5876 %{ | |
5877 instruction_count(2); | |
5878 dst : S5(write); | |
5879 D0 : S0; // big decoder only for the load | |
5880 DECODE : S1; // any decoder for FPU POP | |
5881 FPU : S4; | |
5882 MEM : S3; // any mem | |
5883 %} | |
5884 | |
5885 // Float load constant | |
5886 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
5887 %{ | |
5888 instruction_count(3); | |
5889 dst : S5(write); | |
5890 src : S3(read); | |
5891 D0 : S0; // big decoder only for the load | |
5892 DECODE : S1(2); // any decoder for FPU POP | |
5893 FPU : S4; | |
5894 MEM : S3; // any mem | |
5895 %} | |
5896 | |
5897 // UnConditional branch | |
5898 pipe_class pipe_jmp(label labl) | |
5899 %{ | |
5900 single_instruction; | |
5901 BR : S3; | |
5902 %} | |
5903 | |
5904 // Conditional branch | |
5905 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
5906 %{ | |
5907 single_instruction; | |
5908 cr : S1(read); | |
5909 BR : S3; | |
5910 %} | |
5911 | |
5912 // Allocation idiom | |
5913 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
5914 %{ | |
5915 instruction_count(1); force_serialization; | |
5916 fixed_latency(6); | |
5917 heap_ptr : S3(read); | |
5918 DECODE : S0(3); | |
5919 D0 : S2; | |
5920 MEM : S3; | |
5921 ALU : S3(2); | |
5922 dst : S5(write); | |
5923 BR : S5; | |
5924 %} | |
5925 | |
5926 // Generic big/slow expanded idiom | |
5927 pipe_class pipe_slow() | |
5928 %{ | |
5929 instruction_count(10); multiple_bundles; force_serialization; | |
5930 fixed_latency(100); | |
5931 D0 : S0(2); | |
5932 MEM : S3(2); | |
5933 %} | |
5934 | |
5935 // The real do-nothing guy | |
5936 pipe_class empty() | |
5937 %{ | |
5938 instruction_count(0); | |
5939 %} | |
5940 | |
5941 // Define the class for the Nop node | |
5942 define | |
5943 %{ | |
5944 MachNop = empty; | |
5945 %} | |
5946 | |
5947 %} | |
5948 | |
5949 //----------INSTRUCTIONS------------------------------------------------------- | |
5950 // | |
5951 // match -- States which machine-independent subtree may be replaced | |
5952 // by this instruction. | |
5953 // ins_cost -- The estimated cost of this instruction is used by instruction | |
5954 // selection to identify a minimum cost tree of machine | |
5955 // instructions that matches a tree of machine-independent | |
5956 // instructions. | |
5957 // format -- A string providing the disassembly for this instruction. | |
5958 // The value of an instruction's operand may be inserted | |
5959 // by referring to it with a '$' prefix. | |
5960 // opcode -- Three instruction opcodes may be provided. These are referred | |
5961 // to within an encode class as $primary, $secondary, and $tertiary | |
5962 // rrspectively. The primary opcode is commonly used to | |
5963 // indicate the type of machine instruction, while secondary | |
5964 // and tertiary are often used for prefix options or addressing | |
5965 // modes. | |
5966 // ins_encode -- A list of encode classes with parameters. The encode class | |
5967 // name must have been defined in an 'enc_class' specification | |
5968 // in the encode section of the architecture description. | |
5969 | |
5970 | |
5971 //----------Load/Store/Move Instructions--------------------------------------- | |
5972 //----------Load Instructions-------------------------------------------------- | |
5973 | |
5974 // Load Byte (8 bit signed) | |
5975 instruct loadB(rRegI dst, memory mem) | |
5976 %{ | |
5977 match(Set dst (LoadB mem)); | |
5978 | |
5979 ins_cost(125); | |
5980 format %{ "movsbl $dst, $mem\t# byte" %} | |
5981 opcode(0x0F, 0xBE); | |
5982 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
5983 ins_pipe(ialu_reg_mem); | |
5984 %} | |
5985 | |
5986 // Load Byte (8 bit signed) into long | |
5987 // instruct loadB2L(rRegL dst, memory mem) | |
5988 // %{ | |
5989 // match(Set dst (ConvI2L (LoadB mem))); | |
5990 | |
5991 // ins_cost(125); | |
5992 // format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
5993 // opcode(0x0F, 0xBE); | |
5994 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
5995 // ins_pipe(ialu_reg_mem); | |
5996 // %} | |
5997 | |
5998 // Load Byte (8 bit UNsigned) | |
5999 instruct loadUB(rRegI dst, memory mem, immI_255 bytemask) | |
6000 %{ | |
6001 match(Set dst (AndI (LoadB mem) bytemask)); | |
6002 | |
6003 ins_cost(125); | |
6004 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
6005 opcode(0x0F, 0xB6); | |
6006 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6007 ins_pipe(ialu_reg_mem); | |
6008 %} | |
6009 | |
6010 // Load Byte (8 bit UNsigned) into long | |
6011 // instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask) | |
6012 // %{ | |
6013 // match(Set dst (ConvI2L (AndI (LoadB mem) bytemask))); | |
6014 | |
6015 // ins_cost(125); | |
6016 // format %{ "movzbl $dst, $mem\t# ubyte -> long" %} | |
6017 // opcode(0x0F, 0xB6); | |
6018 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6019 // ins_pipe(ialu_reg_mem); | |
6020 // %} | |
6021 | |
6022 // Load Short (16 bit signed) | |
6023 instruct loadS(rRegI dst, memory mem) | |
6024 %{ | |
6025 match(Set dst (LoadS mem)); | |
6026 | |
6027 ins_cost(125); // XXX | |
6028 format %{ "movswl $dst, $mem\t# short" %} | |
6029 opcode(0x0F, 0xBF); | |
6030 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6031 ins_pipe(ialu_reg_mem); | |
6032 %} | |
6033 | |
6034 // Load Short (16 bit signed) into long | |
6035 // instruct loadS2L(rRegL dst, memory mem) | |
6036 // %{ | |
6037 // match(Set dst (ConvI2L (LoadS mem))); | |
6038 | |
6039 // ins_cost(125); // XXX | |
6040 // format %{ "movswq $dst, $mem\t# short -> long" %} | |
6041 // opcode(0x0F, 0xBF); | |
6042 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6043 // ins_pipe(ialu_reg_mem); | |
6044 // %} | |
6045 | |
6046 // Load Char (16 bit UNsigned) | |
6047 instruct loadC(rRegI dst, memory mem) | |
6048 %{ | |
6049 match(Set dst (LoadC mem)); | |
6050 | |
6051 ins_cost(125); | |
6052 format %{ "movzwl $dst, $mem\t# char" %} | |
6053 opcode(0x0F, 0xB7); | |
6054 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6055 ins_pipe(ialu_reg_mem); | |
6056 %} | |
6057 | |
6058 // Load Char (16 bit UNsigned) into long | |
6059 // instruct loadC2L(rRegL dst, memory mem) | |
6060 // %{ | |
6061 // match(Set dst (ConvI2L (LoadC mem))); | |
6062 | |
6063 // ins_cost(125); | |
6064 // format %{ "movzwl $dst, $mem\t# char -> long" %} | |
6065 // opcode(0x0F, 0xB7); | |
6066 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); | |
6067 // ins_pipe(ialu_reg_mem); | |
6068 // %} | |
6069 | |
6070 // Load Integer | |
6071 instruct loadI(rRegI dst, memory mem) | |
6072 %{ | |
6073 match(Set dst (LoadI mem)); | |
6074 | |
6075 ins_cost(125); // XXX | |
6076 format %{ "movl $dst, $mem\t# int" %} | |
6077 opcode(0x8B); | |
6078 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
6079 ins_pipe(ialu_reg_mem); | |
6080 %} | |
6081 | |
6082 // Load Long | |
6083 instruct loadL(rRegL dst, memory mem) | |
6084 %{ | |
6085 match(Set dst (LoadL mem)); | |
6086 | |
6087 ins_cost(125); // XXX | |
6088 format %{ "movq $dst, $mem\t# long" %} | |
6089 opcode(0x8B); | |
6090 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6091 ins_pipe(ialu_reg_mem); // XXX | |
6092 %} | |
6093 | |
6094 // Load Range | |
6095 instruct loadRange(rRegI dst, memory mem) | |
6096 %{ | |
6097 match(Set dst (LoadRange mem)); | |
6098 | |
6099 ins_cost(125); // XXX | |
6100 format %{ "movl $dst, $mem\t# range" %} | |
6101 opcode(0x8B); | |
6102 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
6103 ins_pipe(ialu_reg_mem); | |
6104 %} | |
6105 | |
6106 // Load Pointer | |
6107 instruct loadP(rRegP dst, memory mem) | |
6108 %{ | |
6109 match(Set dst (LoadP mem)); | |
6110 | |
6111 ins_cost(125); // XXX | |
6112 format %{ "movq $dst, $mem\t# ptr" %} | |
6113 opcode(0x8B); | |
6114 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6115 ins_pipe(ialu_reg_mem); // XXX | |
6116 %} | |
6117 | |
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6118 // Load Compressed Pointer |
163 | 6119 instruct loadN(rRegN dst, memory mem) |
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6120 %{ |
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6121 match(Set dst (LoadN mem)); |
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6122 |
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6123 ins_cost(125); // XXX |
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6124 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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6125 ins_encode %{ |
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6126 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6127 Register dst = as_Register($dst$$reg); |
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6128 __ movl(dst, addr); |
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6129 %} |
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6130 ins_pipe(ialu_reg_mem); // XXX |
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6131 %} |
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6132 |
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6133 |
0 | 6134 // Load Klass Pointer |
6135 instruct loadKlass(rRegP dst, memory mem) | |
6136 %{ | |
6137 match(Set dst (LoadKlass mem)); | |
6138 | |
6139 ins_cost(125); // XXX | |
6140 format %{ "movq $dst, $mem\t# class" %} | |
6141 opcode(0x8B); | |
6142 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6143 ins_pipe(ialu_reg_mem); // XXX | |
6144 %} | |
6145 | |
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6146 // Load narrow Klass Pointer |
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6147 instruct loadNKlass(rRegN dst, memory mem) |
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6148 %{ |
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6149 match(Set dst (LoadNKlass mem)); |
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6150 |
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6151 ins_cost(125); // XXX |
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6152 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
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6153 ins_encode %{ |
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6154 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6155 Register dst = as_Register($dst$$reg); |
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6156 __ movl(dst, addr); |
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6157 %} |
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6158 ins_pipe(ialu_reg_mem); // XXX |
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6159 %} |
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6160 |
0 | 6161 // Load Float |
6162 instruct loadF(regF dst, memory mem) | |
6163 %{ | |
6164 match(Set dst (LoadF mem)); | |
6165 | |
6166 ins_cost(145); // XXX | |
6167 format %{ "movss $dst, $mem\t# float" %} | |
6168 opcode(0xF3, 0x0F, 0x10); | |
6169 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
6170 ins_pipe(pipe_slow); // XXX | |
6171 %} | |
6172 | |
6173 // Load Double | |
6174 instruct loadD_partial(regD dst, memory mem) | |
6175 %{ | |
6176 predicate(!UseXmmLoadAndClearUpper); | |
6177 match(Set dst (LoadD mem)); | |
6178 | |
6179 ins_cost(145); // XXX | |
6180 format %{ "movlpd $dst, $mem\t# double" %} | |
6181 opcode(0x66, 0x0F, 0x12); | |
6182 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
6183 ins_pipe(pipe_slow); // XXX | |
6184 %} | |
6185 | |
6186 instruct loadD(regD dst, memory mem) | |
6187 %{ | |
6188 predicate(UseXmmLoadAndClearUpper); | |
6189 match(Set dst (LoadD mem)); | |
6190 | |
6191 ins_cost(145); // XXX | |
6192 format %{ "movsd $dst, $mem\t# double" %} | |
6193 opcode(0xF2, 0x0F, 0x10); | |
6194 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
6195 ins_pipe(pipe_slow); // XXX | |
6196 %} | |
6197 | |
6198 // Load Aligned Packed Byte to XMM register | |
6199 instruct loadA8B(regD dst, memory mem) %{ | |
6200 match(Set dst (Load8B mem)); | |
6201 ins_cost(125); | |
6202 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
6203 ins_encode( movq_ld(dst, mem)); | |
6204 ins_pipe( pipe_slow ); | |
6205 %} | |
6206 | |
6207 // Load Aligned Packed Short to XMM register | |
6208 instruct loadA4S(regD dst, memory mem) %{ | |
6209 match(Set dst (Load4S mem)); | |
6210 ins_cost(125); | |
6211 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
6212 ins_encode( movq_ld(dst, mem)); | |
6213 ins_pipe( pipe_slow ); | |
6214 %} | |
6215 | |
6216 // Load Aligned Packed Char to XMM register | |
6217 instruct loadA4C(regD dst, memory mem) %{ | |
6218 match(Set dst (Load4C mem)); | |
6219 ins_cost(125); | |
6220 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
6221 ins_encode( movq_ld(dst, mem)); | |
6222 ins_pipe( pipe_slow ); | |
6223 %} | |
6224 | |
6225 // Load Aligned Packed Integer to XMM register | |
6226 instruct load2IU(regD dst, memory mem) %{ | |
6227 match(Set dst (Load2I mem)); | |
6228 ins_cost(125); | |
6229 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
6230 ins_encode( movq_ld(dst, mem)); | |
6231 ins_pipe( pipe_slow ); | |
6232 %} | |
6233 | |
6234 // Load Aligned Packed Single to XMM | |
6235 instruct loadA2F(regD dst, memory mem) %{ | |
6236 match(Set dst (Load2F mem)); | |
6237 ins_cost(145); | |
6238 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
6239 ins_encode( movq_ld(dst, mem)); | |
6240 ins_pipe( pipe_slow ); | |
6241 %} | |
6242 | |
6243 // Load Effective Address | |
6244 instruct leaP8(rRegP dst, indOffset8 mem) | |
6245 %{ | |
6246 match(Set dst mem); | |
6247 | |
6248 ins_cost(110); // XXX | |
6249 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
6250 opcode(0x8D); | |
6251 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6252 ins_pipe(ialu_reg_reg_fat); | |
6253 %} | |
6254 | |
6255 instruct leaP32(rRegP dst, indOffset32 mem) | |
6256 %{ | |
6257 match(Set dst mem); | |
6258 | |
6259 ins_cost(110); | |
6260 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
6261 opcode(0x8D); | |
6262 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6263 ins_pipe(ialu_reg_reg_fat); | |
6264 %} | |
6265 | |
6266 // instruct leaPIdx(rRegP dst, indIndex mem) | |
6267 // %{ | |
6268 // match(Set dst mem); | |
6269 | |
6270 // ins_cost(110); | |
6271 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
6272 // opcode(0x8D); | |
6273 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6274 // ins_pipe(ialu_reg_reg_fat); | |
6275 // %} | |
6276 | |
6277 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
6278 %{ | |
6279 match(Set dst mem); | |
6280 | |
6281 ins_cost(110); | |
6282 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
6283 opcode(0x8D); | |
6284 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6285 ins_pipe(ialu_reg_reg_fat); | |
6286 %} | |
6287 | |
6288 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
6289 %{ | |
6290 match(Set dst mem); | |
6291 | |
6292 ins_cost(110); | |
6293 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
6294 opcode(0x8D); | |
6295 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6296 ins_pipe(ialu_reg_reg_fat); | |
6297 %} | |
6298 | |
6299 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
6300 %{ | |
6301 match(Set dst mem); | |
6302 | |
6303 ins_cost(110); | |
6304 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
6305 opcode(0x8D); | |
6306 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
6307 ins_pipe(ialu_reg_reg_fat); | |
6308 %} | |
6309 | |
6310 instruct loadConI(rRegI dst, immI src) | |
6311 %{ | |
6312 match(Set dst src); | |
6313 | |
6314 format %{ "movl $dst, $src\t# int" %} | |
6315 ins_encode(load_immI(dst, src)); | |
6316 ins_pipe(ialu_reg_fat); // XXX | |
6317 %} | |
6318 | |
6319 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
6320 %{ | |
6321 match(Set dst src); | |
6322 effect(KILL cr); | |
6323 | |
6324 ins_cost(50); | |
6325 format %{ "xorl $dst, $dst\t# int" %} | |
6326 opcode(0x33); /* + rd */ | |
6327 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
6328 ins_pipe(ialu_reg); | |
6329 %} | |
6330 | |
6331 instruct loadConL(rRegL dst, immL src) | |
6332 %{ | |
6333 match(Set dst src); | |
6334 | |
6335 ins_cost(150); | |
6336 format %{ "movq $dst, $src\t# long" %} | |
6337 ins_encode(load_immL(dst, src)); | |
6338 ins_pipe(ialu_reg); | |
6339 %} | |
6340 | |
6341 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
6342 %{ | |
6343 match(Set dst src); | |
6344 effect(KILL cr); | |
6345 | |
6346 ins_cost(50); | |
6347 format %{ "xorl $dst, $dst\t# long" %} | |
6348 opcode(0x33); /* + rd */ | |
6349 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
6350 ins_pipe(ialu_reg); // XXX | |
6351 %} | |
6352 | |
6353 instruct loadConUL32(rRegL dst, immUL32 src) | |
6354 %{ | |
6355 match(Set dst src); | |
6356 | |
6357 ins_cost(60); | |
6358 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
6359 ins_encode(load_immUL32(dst, src)); | |
6360 ins_pipe(ialu_reg); | |
6361 %} | |
6362 | |
6363 instruct loadConL32(rRegL dst, immL32 src) | |
6364 %{ | |
6365 match(Set dst src); | |
6366 | |
6367 ins_cost(70); | |
6368 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
6369 ins_encode(load_immL32(dst, src)); | |
6370 ins_pipe(ialu_reg); | |
6371 %} | |
6372 | |
6373 instruct loadConP(rRegP dst, immP src) | |
6374 %{ | |
6375 match(Set dst src); | |
6376 | |
6377 format %{ "movq $dst, $src\t# ptr" %} | |
6378 ins_encode(load_immP(dst, src)); | |
6379 ins_pipe(ialu_reg_fat); // XXX | |
6380 %} | |
6381 | |
6382 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
6383 %{ | |
6384 match(Set dst src); | |
6385 effect(KILL cr); | |
6386 | |
6387 ins_cost(50); | |
6388 format %{ "xorl $dst, $dst\t# ptr" %} | |
6389 opcode(0x33); /* + rd */ | |
6390 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
6391 ins_pipe(ialu_reg); | |
6392 %} | |
6393 | |
6394 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
6395 %{ | |
6396 match(Set dst src); | |
6397 effect(KILL cr); | |
6398 | |
6399 ins_cost(60); | |
6400 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
6401 ins_encode(load_immP31(dst, src)); | |
6402 ins_pipe(ialu_reg); | |
6403 %} | |
6404 | |
6405 instruct loadConF(regF dst, immF src) | |
6406 %{ | |
6407 match(Set dst src); | |
6408 ins_cost(125); | |
6409 | |
6410 format %{ "movss $dst, [$src]" %} | |
6411 ins_encode(load_conF(dst, src)); | |
6412 ins_pipe(pipe_slow); | |
6413 %} | |
6414 | |
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6415 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
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6416 match(Set dst src); |
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6417 effect(KILL cr); |
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6418 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
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6419 ins_encode %{ |
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6420 Register dst = $dst$$Register; |
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6421 __ xorq(dst, dst); |
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6422 %} |
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6423 ins_pipe(ialu_reg); |
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6424 %} |
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6425 |
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6426 instruct loadConN(rRegN dst, immN src) %{ |
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6427 match(Set dst src); |
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6428 |
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6429 ins_cost(125); |
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6430 format %{ "movl $dst, $src\t# compressed ptr" %} |
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6431 ins_encode %{ |
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6432 address con = (address)$src$$constant; |
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6433 Register dst = $dst$$Register; |
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6434 if (con == NULL) { |
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6435 ShouldNotReachHere(); |
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6436 } else { |
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6437 __ set_narrow_oop(dst, (jobject)$src$$constant); |
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6438 } |
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6439 %} |
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6440 ins_pipe(ialu_reg_fat); // XXX |
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6441 %} |
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6442 |
0 | 6443 instruct loadConF0(regF dst, immF0 src) |
6444 %{ | |
6445 match(Set dst src); | |
6446 ins_cost(100); | |
6447 | |
6448 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
6449 opcode(0x0F, 0x57); | |
6450 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
6451 ins_pipe(pipe_slow); | |
6452 %} | |
6453 | |
6454 // Use the same format since predicate() can not be used here. | |
6455 instruct loadConD(regD dst, immD src) | |
6456 %{ | |
6457 match(Set dst src); | |
6458 ins_cost(125); | |
6459 | |
6460 format %{ "movsd $dst, [$src]" %} | |
6461 ins_encode(load_conD(dst, src)); | |
6462 ins_pipe(pipe_slow); | |
6463 %} | |
6464 | |
6465 instruct loadConD0(regD dst, immD0 src) | |
6466 %{ | |
6467 match(Set dst src); | |
6468 ins_cost(100); | |
6469 | |
6470 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
6471 opcode(0x66, 0x0F, 0x57); | |
6472 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | |
6473 ins_pipe(pipe_slow); | |
6474 %} | |
6475 | |
6476 instruct loadSSI(rRegI dst, stackSlotI src) | |
6477 %{ | |
6478 match(Set dst src); | |
6479 | |
6480 ins_cost(125); | |
6481 format %{ "movl $dst, $src\t# int stk" %} | |
6482 opcode(0x8B); | |
6483 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
6484 ins_pipe(ialu_reg_mem); | |
6485 %} | |
6486 | |
6487 instruct loadSSL(rRegL dst, stackSlotL src) | |
6488 %{ | |
6489 match(Set dst src); | |
6490 | |
6491 ins_cost(125); | |
6492 format %{ "movq $dst, $src\t# long stk" %} | |
6493 opcode(0x8B); | |
6494 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
6495 ins_pipe(ialu_reg_mem); | |
6496 %} | |
6497 | |
6498 instruct loadSSP(rRegP dst, stackSlotP src) | |
6499 %{ | |
6500 match(Set dst src); | |
6501 | |
6502 ins_cost(125); | |
6503 format %{ "movq $dst, $src\t# ptr stk" %} | |
6504 opcode(0x8B); | |
6505 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
6506 ins_pipe(ialu_reg_mem); | |
6507 %} | |
6508 | |
6509 instruct loadSSF(regF dst, stackSlotF src) | |
6510 %{ | |
6511 match(Set dst src); | |
6512 | |
6513 ins_cost(125); | |
6514 format %{ "movss $dst, $src\t# float stk" %} | |
6515 opcode(0xF3, 0x0F, 0x10); | |
6516 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
6517 ins_pipe(pipe_slow); // XXX | |
6518 %} | |
6519 | |
6520 // Use the same format since predicate() can not be used here. | |
6521 instruct loadSSD(regD dst, stackSlotD src) | |
6522 %{ | |
6523 match(Set dst src); | |
6524 | |
6525 ins_cost(125); | |
6526 format %{ "movsd $dst, $src\t# double stk" %} | |
6527 ins_encode %{ | |
6528 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
6529 %} | |
6530 ins_pipe(pipe_slow); // XXX | |
6531 %} | |
6532 | |
6533 // Prefetch instructions. | |
6534 // Must be safe to execute with invalid address (cannot fault). | |
6535 | |
6536 instruct prefetchr( memory mem ) %{ | |
6537 predicate(ReadPrefetchInstr==3); | |
6538 match(PrefetchRead mem); | |
6539 ins_cost(125); | |
6540 | |
6541 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
6542 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ | |
6543 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
6544 ins_pipe(ialu_mem); | |
6545 %} | |
6546 | |
6547 instruct prefetchrNTA( memory mem ) %{ | |
6548 predicate(ReadPrefetchInstr==0); | |
6549 match(PrefetchRead mem); | |
6550 ins_cost(125); | |
6551 | |
6552 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
6553 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
6554 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
6555 ins_pipe(ialu_mem); | |
6556 %} | |
6557 | |
6558 instruct prefetchrT0( memory mem ) %{ | |
6559 predicate(ReadPrefetchInstr==1); | |
6560 match(PrefetchRead mem); | |
6561 ins_cost(125); | |
6562 | |
6563 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
6564 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
6565 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
6566 ins_pipe(ialu_mem); | |
6567 %} | |
6568 | |
6569 instruct prefetchrT2( memory mem ) %{ | |
6570 predicate(ReadPrefetchInstr==2); | |
6571 match(PrefetchRead mem); | |
6572 ins_cost(125); | |
6573 | |
6574 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
6575 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
6576 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
6577 ins_pipe(ialu_mem); | |
6578 %} | |
6579 | |
6580 instruct prefetchw( memory mem ) %{ | |
6581 predicate(AllocatePrefetchInstr==3); | |
6582 match(PrefetchWrite mem); | |
6583 ins_cost(125); | |
6584 | |
6585 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} | |
6586 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
6587 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
6588 ins_pipe(ialu_mem); | |
6589 %} | |
6590 | |
6591 instruct prefetchwNTA( memory mem ) %{ | |
6592 predicate(AllocatePrefetchInstr==0); | |
6593 match(PrefetchWrite mem); | |
6594 ins_cost(125); | |
6595 | |
6596 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
6597 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
6598 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
6599 ins_pipe(ialu_mem); | |
6600 %} | |
6601 | |
6602 instruct prefetchwT0( memory mem ) %{ | |
6603 predicate(AllocatePrefetchInstr==1); | |
6604 match(PrefetchWrite mem); | |
6605 ins_cost(125); | |
6606 | |
6607 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} | |
6608 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
6609 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
6610 ins_pipe(ialu_mem); | |
6611 %} | |
6612 | |
6613 instruct prefetchwT2( memory mem ) %{ | |
6614 predicate(AllocatePrefetchInstr==2); | |
6615 match(PrefetchWrite mem); | |
6616 ins_cost(125); | |
6617 | |
6618 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} | |
6619 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
6620 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
6621 ins_pipe(ialu_mem); | |
6622 %} | |
6623 | |
6624 //----------Store Instructions------------------------------------------------- | |
6625 | |
6626 // Store Byte | |
6627 instruct storeB(memory mem, rRegI src) | |
6628 %{ | |
6629 match(Set mem (StoreB mem src)); | |
6630 | |
6631 ins_cost(125); // XXX | |
6632 format %{ "movb $mem, $src\t# byte" %} | |
6633 opcode(0x88); | |
6634 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
6635 ins_pipe(ialu_mem_reg); | |
6636 %} | |
6637 | |
6638 // Store Char/Short | |
6639 instruct storeC(memory mem, rRegI src) | |
6640 %{ | |
6641 match(Set mem (StoreC mem src)); | |
6642 | |
6643 ins_cost(125); // XXX | |
6644 format %{ "movw $mem, $src\t# char/short" %} | |
6645 opcode(0x89); | |
6646 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
6647 ins_pipe(ialu_mem_reg); | |
6648 %} | |
6649 | |
6650 // Store Integer | |
6651 instruct storeI(memory mem, rRegI src) | |
6652 %{ | |
6653 match(Set mem (StoreI mem src)); | |
6654 | |
6655 ins_cost(125); // XXX | |
6656 format %{ "movl $mem, $src\t# int" %} | |
6657 opcode(0x89); | |
6658 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
6659 ins_pipe(ialu_mem_reg); | |
6660 %} | |
6661 | |
6662 // Store Long | |
6663 instruct storeL(memory mem, rRegL src) | |
6664 %{ | |
6665 match(Set mem (StoreL mem src)); | |
6666 | |
6667 ins_cost(125); // XXX | |
6668 format %{ "movq $mem, $src\t# long" %} | |
6669 opcode(0x89); | |
6670 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
6671 ins_pipe(ialu_mem_reg); // XXX | |
6672 %} | |
6673 | |
6674 // Store Pointer | |
6675 instruct storeP(memory mem, any_RegP src) | |
6676 %{ | |
6677 match(Set mem (StoreP mem src)); | |
6678 | |
6679 ins_cost(125); // XXX | |
6680 format %{ "movq $mem, $src\t# ptr" %} | |
6681 opcode(0x89); | |
6682 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
6683 ins_pipe(ialu_mem_reg); | |
6684 %} | |
6685 | |
6686 // Store NULL Pointer, mark word, or other simple pointer constant. | |
6687 instruct storeImmP(memory mem, immP31 src) | |
6688 %{ | |
6689 match(Set mem (StoreP mem src)); | |
6690 | |
6691 ins_cost(125); // XXX | |
6692 format %{ "movq $mem, $src\t# ptr" %} | |
6693 opcode(0xC7); /* C7 /0 */ | |
6694 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
6695 ins_pipe(ialu_mem_imm); | |
6696 %} | |
6697 | |
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6698 // Store Compressed Pointer |
163 | 6699 instruct storeN(memory mem, rRegN src) |
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6700 %{ |
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6701 match(Set mem (StoreN mem src)); |
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6702 |
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6703 ins_cost(125); // XXX |
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6704 format %{ "movl $mem, $src\t# compressed ptr" %} |
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6705 ins_encode %{ |
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6706 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6707 Register src = as_Register($src$$reg); |
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6708 __ movl(addr, src); |
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6709 %} |
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6710 ins_pipe(ialu_mem_reg); |
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6711 %} |
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6712 |
0 | 6713 // Store Integer Immediate |
6714 instruct storeImmI(memory mem, immI src) | |
6715 %{ | |
6716 match(Set mem (StoreI mem src)); | |
6717 | |
6718 ins_cost(150); | |
6719 format %{ "movl $mem, $src\t# int" %} | |
6720 opcode(0xC7); /* C7 /0 */ | |
6721 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
6722 ins_pipe(ialu_mem_imm); | |
6723 %} | |
6724 | |
6725 // Store Long Immediate | |
6726 instruct storeImmL(memory mem, immL32 src) | |
6727 %{ | |
6728 match(Set mem (StoreL mem src)); | |
6729 | |
6730 ins_cost(150); | |
6731 format %{ "movq $mem, $src\t# long" %} | |
6732 opcode(0xC7); /* C7 /0 */ | |
6733 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
6734 ins_pipe(ialu_mem_imm); | |
6735 %} | |
6736 | |
6737 // Store Short/Char Immediate | |
6738 instruct storeImmI16(memory mem, immI16 src) | |
6739 %{ | |
6740 predicate(UseStoreImmI16); | |
6741 match(Set mem (StoreC mem src)); | |
6742 | |
6743 ins_cost(150); | |
6744 format %{ "movw $mem, $src\t# short/char" %} | |
6745 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
6746 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
6747 ins_pipe(ialu_mem_imm); | |
6748 %} | |
6749 | |
6750 // Store Byte Immediate | |
6751 instruct storeImmB(memory mem, immI8 src) | |
6752 %{ | |
6753 match(Set mem (StoreB mem src)); | |
6754 | |
6755 ins_cost(150); // XXX | |
6756 format %{ "movb $mem, $src\t# byte" %} | |
6757 opcode(0xC6); /* C6 /0 */ | |
6758 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
6759 ins_pipe(ialu_mem_imm); | |
6760 %} | |
6761 | |
6762 // Store Aligned Packed Byte XMM register to memory | |
6763 instruct storeA8B(memory mem, regD src) %{ | |
6764 match(Set mem (Store8B mem src)); | |
6765 ins_cost(145); | |
6766 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
6767 ins_encode( movq_st(mem, src)); | |
6768 ins_pipe( pipe_slow ); | |
6769 %} | |
6770 | |
6771 // Store Aligned Packed Char/Short XMM register to memory | |
6772 instruct storeA4C(memory mem, regD src) %{ | |
6773 match(Set mem (Store4C mem src)); | |
6774 ins_cost(145); | |
6775 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
6776 ins_encode( movq_st(mem, src)); | |
6777 ins_pipe( pipe_slow ); | |
6778 %} | |
6779 | |
6780 // Store Aligned Packed Integer XMM register to memory | |
6781 instruct storeA2I(memory mem, regD src) %{ | |
6782 match(Set mem (Store2I mem src)); | |
6783 ins_cost(145); | |
6784 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
6785 ins_encode( movq_st(mem, src)); | |
6786 ins_pipe( pipe_slow ); | |
6787 %} | |
6788 | |
6789 // Store CMS card-mark Immediate | |
6790 instruct storeImmCM0(memory mem, immI0 src) | |
6791 %{ | |
6792 match(Set mem (StoreCM mem src)); | |
6793 | |
6794 ins_cost(150); // XXX | |
6795 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
6796 opcode(0xC6); /* C6 /0 */ | |
6797 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
6798 ins_pipe(ialu_mem_imm); | |
6799 %} | |
6800 | |
6801 // Store Aligned Packed Single Float XMM register to memory | |
6802 instruct storeA2F(memory mem, regD src) %{ | |
6803 match(Set mem (Store2F mem src)); | |
6804 ins_cost(145); | |
6805 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
6806 ins_encode( movq_st(mem, src)); | |
6807 ins_pipe( pipe_slow ); | |
6808 %} | |
6809 | |
6810 // Store Float | |
6811 instruct storeF(memory mem, regF src) | |
6812 %{ | |
6813 match(Set mem (StoreF mem src)); | |
6814 | |
6815 ins_cost(95); // XXX | |
6816 format %{ "movss $mem, $src\t# float" %} | |
6817 opcode(0xF3, 0x0F, 0x11); | |
6818 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
6819 ins_pipe(pipe_slow); // XXX | |
6820 %} | |
6821 | |
6822 // Store immediate Float value (it is faster than store from XMM register) | |
6823 instruct storeF_imm(memory mem, immF src) | |
6824 %{ | |
6825 match(Set mem (StoreF mem src)); | |
6826 | |
6827 ins_cost(50); | |
6828 format %{ "movl $mem, $src\t# float" %} | |
6829 opcode(0xC7); /* C7 /0 */ | |
6830 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
6831 ins_pipe(ialu_mem_imm); | |
6832 %} | |
6833 | |
6834 // Store Double | |
6835 instruct storeD(memory mem, regD src) | |
6836 %{ | |
6837 match(Set mem (StoreD mem src)); | |
6838 | |
6839 ins_cost(95); // XXX | |
6840 format %{ "movsd $mem, $src\t# double" %} | |
6841 opcode(0xF2, 0x0F, 0x11); | |
6842 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
6843 ins_pipe(pipe_slow); // XXX | |
6844 %} | |
6845 | |
6846 // Store immediate double 0.0 (it is faster than store from XMM register) | |
6847 instruct storeD0_imm(memory mem, immD0 src) | |
6848 %{ | |
6849 match(Set mem (StoreD mem src)); | |
6850 | |
6851 ins_cost(50); | |
6852 format %{ "movq $mem, $src\t# double 0." %} | |
6853 opcode(0xC7); /* C7 /0 */ | |
6854 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
6855 ins_pipe(ialu_mem_imm); | |
6856 %} | |
6857 | |
6858 instruct storeSSI(stackSlotI dst, rRegI src) | |
6859 %{ | |
6860 match(Set dst src); | |
6861 | |
6862 ins_cost(100); | |
6863 format %{ "movl $dst, $src\t# int stk" %} | |
6864 opcode(0x89); | |
6865 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
6866 ins_pipe( ialu_mem_reg ); | |
6867 %} | |
6868 | |
6869 instruct storeSSL(stackSlotL dst, rRegL src) | |
6870 %{ | |
6871 match(Set dst src); | |
6872 | |
6873 ins_cost(100); | |
6874 format %{ "movq $dst, $src\t# long stk" %} | |
6875 opcode(0x89); | |
6876 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
6877 ins_pipe(ialu_mem_reg); | |
6878 %} | |
6879 | |
6880 instruct storeSSP(stackSlotP dst, rRegP src) | |
6881 %{ | |
6882 match(Set dst src); | |
6883 | |
6884 ins_cost(100); | |
6885 format %{ "movq $dst, $src\t# ptr stk" %} | |
6886 opcode(0x89); | |
6887 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
6888 ins_pipe(ialu_mem_reg); | |
6889 %} | |
6890 | |
6891 instruct storeSSF(stackSlotF dst, regF src) | |
6892 %{ | |
6893 match(Set dst src); | |
6894 | |
6895 ins_cost(95); // XXX | |
6896 format %{ "movss $dst, $src\t# float stk" %} | |
6897 opcode(0xF3, 0x0F, 0x11); | |
6898 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
6899 ins_pipe(pipe_slow); // XXX | |
6900 %} | |
6901 | |
6902 instruct storeSSD(stackSlotD dst, regD src) | |
6903 %{ | |
6904 match(Set dst src); | |
6905 | |
6906 ins_cost(95); // XXX | |
6907 format %{ "movsd $dst, $src\t# double stk" %} | |
6908 opcode(0xF2, 0x0F, 0x11); | |
6909 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
6910 ins_pipe(pipe_slow); // XXX | |
6911 %} | |
6912 | |
6913 //----------BSWAP Instructions------------------------------------------------- | |
6914 instruct bytes_reverse_int(rRegI dst) %{ | |
6915 match(Set dst (ReverseBytesI dst)); | |
6916 | |
6917 format %{ "bswapl $dst" %} | |
6918 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
6919 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
6920 ins_pipe( ialu_reg ); | |
6921 %} | |
6922 | |
6923 instruct bytes_reverse_long(rRegL dst) %{ | |
6924 match(Set dst (ReverseBytesL dst)); | |
6925 | |
6926 format %{ "bswapq $dst" %} | |
6927 | |
6928 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
6929 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
6930 ins_pipe( ialu_reg); | |
6931 %} | |
6932 | |
6933 instruct loadI_reversed(rRegI dst, memory src) %{ | |
6934 match(Set dst (ReverseBytesI (LoadI src))); | |
6935 | |
6936 format %{ "bswap_movl $dst, $src" %} | |
6937 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
6938 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst)); | |
6939 ins_pipe( ialu_reg_mem ); | |
6940 %} | |
6941 | |
6942 instruct loadL_reversed(rRegL dst, memory src) %{ | |
6943 match(Set dst (ReverseBytesL (LoadL src))); | |
6944 | |
6945 format %{ "bswap_movq $dst, $src" %} | |
6946 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
6947 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst)); | |
6948 ins_pipe( ialu_reg_mem ); | |
6949 %} | |
6950 | |
6951 instruct storeI_reversed(memory dst, rRegI src) %{ | |
6952 match(Set dst (StoreI dst (ReverseBytesI src))); | |
6953 | |
6954 format %{ "movl_bswap $dst, $src" %} | |
6955 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
6956 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) ); | |
6957 ins_pipe( ialu_mem_reg ); | |
6958 %} | |
6959 | |
6960 instruct storeL_reversed(memory dst, rRegL src) %{ | |
6961 match(Set dst (StoreL dst (ReverseBytesL src))); | |
6962 | |
6963 format %{ "movq_bswap $dst, $src" %} | |
6964 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
6965 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) ); | |
6966 ins_pipe( ialu_mem_reg ); | |
6967 %} | |
6968 | |
6969 //----------MemBar Instructions----------------------------------------------- | |
6970 // Memory barrier flavors | |
6971 | |
6972 instruct membar_acquire() | |
6973 %{ | |
6974 match(MemBarAcquire); | |
6975 ins_cost(0); | |
6976 | |
6977 size(0); | |
6978 format %{ "MEMBAR-acquire" %} | |
6979 ins_encode(); | |
6980 ins_pipe(empty); | |
6981 %} | |
6982 | |
6983 instruct membar_acquire_lock() | |
6984 %{ | |
6985 match(MemBarAcquire); | |
6986 predicate(Matcher::prior_fast_lock(n)); | |
6987 ins_cost(0); | |
6988 | |
6989 size(0); | |
6990 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
6991 ins_encode(); | |
6992 ins_pipe(empty); | |
6993 %} | |
6994 | |
6995 instruct membar_release() | |
6996 %{ | |
6997 match(MemBarRelease); | |
6998 ins_cost(0); | |
6999 | |
7000 size(0); | |
7001 format %{ "MEMBAR-release" %} | |
7002 ins_encode(); | |
7003 ins_pipe(empty); | |
7004 %} | |
7005 | |
7006 instruct membar_release_lock() | |
7007 %{ | |
7008 match(MemBarRelease); | |
7009 predicate(Matcher::post_fast_unlock(n)); | |
7010 ins_cost(0); | |
7011 | |
7012 size(0); | |
7013 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
7014 ins_encode(); | |
7015 ins_pipe(empty); | |
7016 %} | |
7017 | |
7018 instruct membar_volatile() | |
7019 %{ | |
7020 match(MemBarVolatile); | |
7021 ins_cost(400); | |
7022 | |
7023 format %{ "MEMBAR-volatile" %} | |
7024 ins_encode(enc_membar_volatile); | |
7025 ins_pipe(pipe_slow); | |
7026 %} | |
7027 | |
7028 instruct unnecessary_membar_volatile() | |
7029 %{ | |
7030 match(MemBarVolatile); | |
7031 predicate(Matcher::post_store_load_barrier(n)); | |
7032 ins_cost(0); | |
7033 | |
7034 size(0); | |
7035 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
7036 ins_encode(); | |
7037 ins_pipe(empty); | |
7038 %} | |
7039 | |
7040 //----------Move Instructions-------------------------------------------------- | |
7041 | |
7042 instruct castX2P(rRegP dst, rRegL src) | |
7043 %{ | |
7044 match(Set dst (CastX2P src)); | |
7045 | |
7046 format %{ "movq $dst, $src\t# long->ptr" %} | |
7047 ins_encode(enc_copy_wide(dst, src)); | |
7048 ins_pipe(ialu_reg_reg); // XXX | |
7049 %} | |
7050 | |
7051 instruct castP2X(rRegL dst, rRegP src) | |
7052 %{ | |
7053 match(Set dst (CastP2X src)); | |
7054 | |
7055 format %{ "movq $dst, $src\t# ptr -> long" %} | |
7056 ins_encode(enc_copy_wide(dst, src)); | |
7057 ins_pipe(ialu_reg_reg); // XXX | |
7058 %} | |
7059 | |
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7060 |
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7061 // Convert oop pointer into compressed form |
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7062 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
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7063 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
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7064 match(Set dst (EncodeP src)); |
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7065 effect(KILL cr); |
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7066 format %{ "encode_heap_oop $dst,$src" %} |
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7067 ins_encode %{ |
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7068 Register s = $src$$Register; |
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7069 Register d = $dst$$Register; |
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7070 if (s != d) { |
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7071 __ movq(d, s); |
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7072 } |
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7073 __ encode_heap_oop(d); |
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7074 %} |
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7075 ins_pipe(ialu_reg_long); |
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7076 %} |
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7077 |
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7078 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
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7079 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
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7080 match(Set dst (EncodeP src)); |
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7081 effect(KILL cr); |
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7082 format %{ "encode_heap_oop_not_null $dst,$src" %} |
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7083 ins_encode %{ |
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7084 Register s = $src$$Register; |
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7085 Register d = $dst$$Register; |
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7086 __ encode_heap_oop_not_null(d, s); |
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7087 %} |
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7088 ins_pipe(ialu_reg_long); |
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7089 %} |
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7090 |
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7091 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
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7092 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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7093 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
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7094 match(Set dst (DecodeN src)); |
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7095 effect(KILL cr); |
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7096 format %{ "decode_heap_oop $dst,$src" %} |
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7097 ins_encode %{ |
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7098 Register s = $src$$Register; |
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7099 Register d = $dst$$Register; |
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7100 if (s != d) { |
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7101 __ movq(d, s); |
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7102 } |
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7103 __ decode_heap_oop(d); |
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7104 %} |
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7105 ins_pipe(ialu_reg_long); |
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7106 %} |
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7107 |
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7108 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{ |
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7109 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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7110 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
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7111 match(Set dst (DecodeN src)); |
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7112 format %{ "decode_heap_oop_not_null $dst,$src" %} |
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7113 ins_encode %{ |
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7114 Register s = $src$$Register; |
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7115 Register d = $dst$$Register; |
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7116 __ decode_heap_oop_not_null(d, s); |
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7117 %} |
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7118 ins_pipe(ialu_reg_long); |
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7119 %} |
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7120 |
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7121 |
0 | 7122 //----------Conditional Move--------------------------------------------------- |
7123 // Jump | |
7124 // dummy instruction for generating temp registers | |
7125 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
7126 match(Jump (LShiftL switch_val shift)); | |
7127 ins_cost(350); | |
7128 predicate(false); | |
7129 effect(TEMP dest); | |
7130 | |
7131 format %{ "leaq $dest, table_base\n\t" | |
7132 "jmp [$dest + $switch_val << $shift]\n\t" %} | |
7133 ins_encode(jump_enc_offset(switch_val, shift, dest)); | |
7134 ins_pipe(pipe_jmp); | |
7135 ins_pc_relative(1); | |
7136 %} | |
7137 | |
7138 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
7139 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
7140 ins_cost(350); | |
7141 effect(TEMP dest); | |
7142 | |
7143 format %{ "leaq $dest, table_base\n\t" | |
7144 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} | |
7145 ins_encode(jump_enc_addr(switch_val, shift, offset, dest)); | |
7146 ins_pipe(pipe_jmp); | |
7147 ins_pc_relative(1); | |
7148 %} | |
7149 | |
7150 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
7151 match(Jump switch_val); | |
7152 ins_cost(350); | |
7153 effect(TEMP dest); | |
7154 | |
7155 format %{ "leaq $dest, table_base\n\t" | |
7156 "jmp [$dest + $switch_val]\n\t" %} | |
7157 ins_encode(jump_enc(switch_val, dest)); | |
7158 ins_pipe(pipe_jmp); | |
7159 ins_pc_relative(1); | |
7160 %} | |
7161 | |
7162 // Conditional move | |
7163 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
7164 %{ | |
7165 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
7166 | |
7167 ins_cost(200); // XXX | |
7168 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
7169 opcode(0x0F, 0x40); | |
7170 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7171 ins_pipe(pipe_cmov_reg); | |
7172 %} | |
7173 | |
7174 instruct cmovI_regU(rRegI dst, rRegI src, rFlagsRegU cr, cmpOpU cop) | |
7175 %{ | |
7176 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
7177 | |
7178 ins_cost(200); // XXX | |
7179 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
7180 opcode(0x0F, 0x40); | |
7181 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7182 ins_pipe(pipe_cmov_reg); | |
7183 %} | |
7184 | |
7185 // Conditional move | |
7186 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) | |
7187 %{ | |
7188 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
7189 | |
7190 ins_cost(250); // XXX | |
7191 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
7192 opcode(0x0F, 0x40); | |
7193 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
7194 ins_pipe(pipe_cmov_mem); | |
7195 %} | |
7196 | |
7197 // Conditional move | |
7198 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
7199 %{ | |
7200 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
7201 | |
7202 ins_cost(250); // XXX | |
7203 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
7204 opcode(0x0F, 0x40); | |
7205 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
7206 ins_pipe(pipe_cmov_mem); | |
7207 %} | |
7208 | |
7209 // Conditional move | |
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7210 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
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7211 %{ |
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7212 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
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7213 |
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7214 ins_cost(200); // XXX |
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7215 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
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7216 opcode(0x0F, 0x40); |
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7217 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
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7218 ins_pipe(pipe_cmov_reg); |
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7219 %} |
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7220 |
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7221 // Conditional move |
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7222 instruct cmovN_regU(rRegN dst, rRegN src, rFlagsRegU cr, cmpOpU cop) |
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7223 %{ |
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7224 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
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7225 |
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7226 ins_cost(200); // XXX |
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7227 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
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7228 opcode(0x0F, 0x40); |
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7229 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
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7230 ins_pipe(pipe_cmov_reg); |
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7231 %} |
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7232 |
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7233 // Conditional move |
0 | 7234 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
7235 %{ | |
7236 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
7237 | |
7238 ins_cost(200); // XXX | |
7239 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
7240 opcode(0x0F, 0x40); | |
7241 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7242 ins_pipe(pipe_cmov_reg); // XXX | |
7243 %} | |
7244 | |
7245 // Conditional move | |
7246 instruct cmovP_regU(rRegP dst, rRegP src, rFlagsRegU cr, cmpOpU cop) | |
7247 %{ | |
7248 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
7249 | |
7250 ins_cost(200); // XXX | |
7251 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
7252 opcode(0x0F, 0x40); | |
7253 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7254 ins_pipe(pipe_cmov_reg); // XXX | |
7255 %} | |
7256 | |
7257 // DISABLED: Requires the ADLC to emit a bottom_type call that | |
7258 // correctly meets the two pointer arguments; one is an incoming | |
7259 // register but the other is a memory operand. ALSO appears to | |
7260 // be buggy with implicit null checks. | |
7261 // | |
7262 //// Conditional move | |
7263 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
7264 //%{ | |
7265 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
7266 // ins_cost(250); | |
7267 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
7268 // opcode(0x0F,0x40); | |
7269 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
7270 // ins_pipe( pipe_cmov_mem ); | |
7271 //%} | |
7272 // | |
7273 //// Conditional move | |
7274 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
7275 //%{ | |
7276 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
7277 // ins_cost(250); | |
7278 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
7279 // opcode(0x0F,0x40); | |
7280 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
7281 // ins_pipe( pipe_cmov_mem ); | |
7282 //%} | |
7283 | |
7284 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
7285 %{ | |
7286 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
7287 | |
7288 ins_cost(200); // XXX | |
7289 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
7290 opcode(0x0F, 0x40); | |
7291 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7292 ins_pipe(pipe_cmov_reg); // XXX | |
7293 %} | |
7294 | |
7295 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
7296 %{ | |
7297 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
7298 | |
7299 ins_cost(200); // XXX | |
7300 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
7301 opcode(0x0F, 0x40); | |
7302 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
7303 ins_pipe(pipe_cmov_mem); // XXX | |
7304 %} | |
7305 | |
7306 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
7307 %{ | |
7308 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
7309 | |
7310 ins_cost(200); // XXX | |
7311 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
7312 opcode(0x0F, 0x40); | |
7313 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
7314 ins_pipe(pipe_cmov_reg); // XXX | |
7315 %} | |
7316 | |
7317 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) | |
7318 %{ | |
7319 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
7320 | |
7321 ins_cost(200); // XXX | |
7322 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
7323 opcode(0x0F, 0x40); | |
7324 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
7325 ins_pipe(pipe_cmov_mem); // XXX | |
7326 %} | |
7327 | |
7328 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) | |
7329 %{ | |
7330 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
7331 | |
7332 ins_cost(200); // XXX | |
7333 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
7334 "movss $dst, $src\n" | |
7335 "skip:" %} | |
7336 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
7337 ins_pipe(pipe_slow); | |
7338 %} | |
7339 | |
7340 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
7341 // %{ | |
7342 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
7343 | |
7344 // ins_cost(200); // XXX | |
7345 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
7346 // "movss $dst, $src\n" | |
7347 // "skip:" %} | |
7348 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
7349 // ins_pipe(pipe_slow); | |
7350 // %} | |
7351 | |
7352 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
7353 %{ | |
7354 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
7355 | |
7356 ins_cost(200); // XXX | |
7357 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
7358 "movss $dst, $src\n" | |
7359 "skip:" %} | |
7360 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
7361 ins_pipe(pipe_slow); | |
7362 %} | |
7363 | |
7364 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) | |
7365 %{ | |
7366 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
7367 | |
7368 ins_cost(200); // XXX | |
7369 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
7370 "movsd $dst, $src\n" | |
7371 "skip:" %} | |
7372 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
7373 ins_pipe(pipe_slow); | |
7374 %} | |
7375 | |
7376 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
7377 %{ | |
7378 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
7379 | |
7380 ins_cost(200); // XXX | |
7381 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
7382 "movsd $dst, $src\n" | |
7383 "skip:" %} | |
7384 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
7385 ins_pipe(pipe_slow); | |
7386 %} | |
7387 | |
7388 //----------Arithmetic Instructions-------------------------------------------- | |
7389 //----------Addition Instructions---------------------------------------------- | |
7390 | |
7391 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
7392 %{ | |
7393 match(Set dst (AddI dst src)); | |
7394 effect(KILL cr); | |
7395 | |
7396 format %{ "addl $dst, $src\t# int" %} | |
7397 opcode(0x03); | |
7398 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
7399 ins_pipe(ialu_reg_reg); | |
7400 %} | |
7401 | |
7402 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
7403 %{ | |
7404 match(Set dst (AddI dst src)); | |
7405 effect(KILL cr); | |
7406 | |
7407 format %{ "addl $dst, $src\t# int" %} | |
7408 opcode(0x81, 0x00); /* /0 id */ | |
7409 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
7410 ins_pipe( ialu_reg ); | |
7411 %} | |
7412 | |
7413 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
7414 %{ | |
7415 match(Set dst (AddI dst (LoadI src))); | |
7416 effect(KILL cr); | |
7417 | |
7418 ins_cost(125); // XXX | |
7419 format %{ "addl $dst, $src\t# int" %} | |
7420 opcode(0x03); | |
7421 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
7422 ins_pipe(ialu_reg_mem); | |
7423 %} | |
7424 | |
7425 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
7426 %{ | |
7427 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
7428 effect(KILL cr); | |
7429 | |
7430 ins_cost(150); // XXX | |
7431 format %{ "addl $dst, $src\t# int" %} | |
7432 opcode(0x01); /* Opcode 01 /r */ | |
7433 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
7434 ins_pipe(ialu_mem_reg); | |
7435 %} | |
7436 | |
7437 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
7438 %{ | |
7439 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
7440 effect(KILL cr); | |
7441 | |
7442 ins_cost(125); // XXX | |
7443 format %{ "addl $dst, $src\t# int" %} | |
7444 opcode(0x81); /* Opcode 81 /0 id */ | |
7445 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
7446 ins_pipe(ialu_mem_imm); | |
7447 %} | |
7448 | |
7449 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
7450 %{ | |
7451 predicate(UseIncDec); | |
7452 match(Set dst (AddI dst src)); | |
7453 effect(KILL cr); | |
7454 | |
7455 format %{ "incl $dst\t# int" %} | |
7456 opcode(0xFF, 0x00); // FF /0 | |
7457 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
7458 ins_pipe(ialu_reg); | |
7459 %} | |
7460 | |
7461 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
7462 %{ | |
7463 predicate(UseIncDec); | |
7464 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
7465 effect(KILL cr); | |
7466 | |
7467 ins_cost(125); // XXX | |
7468 format %{ "incl $dst\t# int" %} | |
7469 opcode(0xFF); /* Opcode FF /0 */ | |
7470 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
7471 ins_pipe(ialu_mem_imm); | |
7472 %} | |
7473 | |
7474 // XXX why does that use AddI | |
7475 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
7476 %{ | |
7477 predicate(UseIncDec); | |
7478 match(Set dst (AddI dst src)); | |
7479 effect(KILL cr); | |
7480 | |
7481 format %{ "decl $dst\t# int" %} | |
7482 opcode(0xFF, 0x01); // FF /1 | |
7483 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
7484 ins_pipe(ialu_reg); | |
7485 %} | |
7486 | |
7487 // XXX why does that use AddI | |
7488 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
7489 %{ | |
7490 predicate(UseIncDec); | |
7491 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
7492 effect(KILL cr); | |
7493 | |
7494 ins_cost(125); // XXX | |
7495 format %{ "decl $dst\t# int" %} | |
7496 opcode(0xFF); /* Opcode FF /1 */ | |
7497 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
7498 ins_pipe(ialu_mem_imm); | |
7499 %} | |
7500 | |
7501 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
7502 %{ | |
7503 match(Set dst (AddI src0 src1)); | |
7504 | |
7505 ins_cost(110); | |
7506 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
7507 opcode(0x8D); /* 0x8D /r */ | |
7508 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
7509 ins_pipe(ialu_reg_reg); | |
7510 %} | |
7511 | |
7512 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
7513 %{ | |
7514 match(Set dst (AddL dst src)); | |
7515 effect(KILL cr); | |
7516 | |
7517 format %{ "addq $dst, $src\t# long" %} | |
7518 opcode(0x03); | |
7519 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
7520 ins_pipe(ialu_reg_reg); | |
7521 %} | |
7522 | |
7523 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
7524 %{ | |
7525 match(Set dst (AddL dst src)); | |
7526 effect(KILL cr); | |
7527 | |
7528 format %{ "addq $dst, $src\t# long" %} | |
7529 opcode(0x81, 0x00); /* /0 id */ | |
7530 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
7531 ins_pipe( ialu_reg ); | |
7532 %} | |
7533 | |
7534 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
7535 %{ | |
7536 match(Set dst (AddL dst (LoadL src))); | |
7537 effect(KILL cr); | |
7538 | |
7539 ins_cost(125); // XXX | |
7540 format %{ "addq $dst, $src\t# long" %} | |
7541 opcode(0x03); | |
7542 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
7543 ins_pipe(ialu_reg_mem); | |
7544 %} | |
7545 | |
7546 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
7547 %{ | |
7548 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
7549 effect(KILL cr); | |
7550 | |
7551 ins_cost(150); // XXX | |
7552 format %{ "addq $dst, $src\t# long" %} | |
7553 opcode(0x01); /* Opcode 01 /r */ | |
7554 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
7555 ins_pipe(ialu_mem_reg); | |
7556 %} | |
7557 | |
7558 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
7559 %{ | |
7560 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
7561 effect(KILL cr); | |
7562 | |
7563 ins_cost(125); // XXX | |
7564 format %{ "addq $dst, $src\t# long" %} | |
7565 opcode(0x81); /* Opcode 81 /0 id */ | |
7566 ins_encode(REX_mem_wide(dst), | |
7567 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
7568 ins_pipe(ialu_mem_imm); | |
7569 %} | |
7570 | |
7571 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
7572 %{ | |
7573 predicate(UseIncDec); | |
7574 match(Set dst (AddL dst src)); | |
7575 effect(KILL cr); | |
7576 | |
7577 format %{ "incq $dst\t# long" %} | |
7578 opcode(0xFF, 0x00); // FF /0 | |
7579 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
7580 ins_pipe(ialu_reg); | |
7581 %} | |
7582 | |
7583 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
7584 %{ | |
7585 predicate(UseIncDec); | |
7586 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
7587 effect(KILL cr); | |
7588 | |
7589 ins_cost(125); // XXX | |
7590 format %{ "incq $dst\t# long" %} | |
7591 opcode(0xFF); /* Opcode FF /0 */ | |
7592 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
7593 ins_pipe(ialu_mem_imm); | |
7594 %} | |
7595 | |
7596 // XXX why does that use AddL | |
7597 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
7598 %{ | |
7599 predicate(UseIncDec); | |
7600 match(Set dst (AddL dst src)); | |
7601 effect(KILL cr); | |
7602 | |
7603 format %{ "decq $dst\t# long" %} | |
7604 opcode(0xFF, 0x01); // FF /1 | |
7605 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
7606 ins_pipe(ialu_reg); | |
7607 %} | |
7608 | |
7609 // XXX why does that use AddL | |
7610 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
7611 %{ | |
7612 predicate(UseIncDec); | |
7613 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
7614 effect(KILL cr); | |
7615 | |
7616 ins_cost(125); // XXX | |
7617 format %{ "decq $dst\t# long" %} | |
7618 opcode(0xFF); /* Opcode FF /1 */ | |
7619 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
7620 ins_pipe(ialu_mem_imm); | |
7621 %} | |
7622 | |
7623 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
7624 %{ | |
7625 match(Set dst (AddL src0 src1)); | |
7626 | |
7627 ins_cost(110); | |
7628 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
7629 opcode(0x8D); /* 0x8D /r */ | |
7630 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
7631 ins_pipe(ialu_reg_reg); | |
7632 %} | |
7633 | |
7634 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
7635 %{ | |
7636 match(Set dst (AddP dst src)); | |
7637 effect(KILL cr); | |
7638 | |
7639 format %{ "addq $dst, $src\t# ptr" %} | |
7640 opcode(0x03); | |
7641 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
7642 ins_pipe(ialu_reg_reg); | |
7643 %} | |
7644 | |
7645 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
7646 %{ | |
7647 match(Set dst (AddP dst src)); | |
7648 effect(KILL cr); | |
7649 | |
7650 format %{ "addq $dst, $src\t# ptr" %} | |
7651 opcode(0x81, 0x00); /* /0 id */ | |
7652 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
7653 ins_pipe( ialu_reg ); | |
7654 %} | |
7655 | |
7656 // XXX addP mem ops ???? | |
7657 | |
7658 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
7659 %{ | |
7660 match(Set dst (AddP src0 src1)); | |
7661 | |
7662 ins_cost(110); | |
7663 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
7664 opcode(0x8D); /* 0x8D /r */ | |
7665 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
7666 ins_pipe(ialu_reg_reg); | |
7667 %} | |
7668 | |
7669 instruct checkCastPP(rRegP dst) | |
7670 %{ | |
7671 match(Set dst (CheckCastPP dst)); | |
7672 | |
7673 size(0); | |
7674 format %{ "# checkcastPP of $dst" %} | |
7675 ins_encode(/* empty encoding */); | |
7676 ins_pipe(empty); | |
7677 %} | |
7678 | |
7679 instruct castPP(rRegP dst) | |
7680 %{ | |
7681 match(Set dst (CastPP dst)); | |
7682 | |
7683 size(0); | |
7684 format %{ "# castPP of $dst" %} | |
7685 ins_encode(/* empty encoding */); | |
7686 ins_pipe(empty); | |
7687 %} | |
7688 | |
7689 instruct castII(rRegI dst) | |
7690 %{ | |
7691 match(Set dst (CastII dst)); | |
7692 | |
7693 size(0); | |
7694 format %{ "# castII of $dst" %} | |
7695 ins_encode(/* empty encoding */); | |
7696 ins_cost(0); | |
7697 ins_pipe(empty); | |
7698 %} | |
7699 | |
7700 // LoadP-locked same as a regular LoadP when used with compare-swap | |
7701 instruct loadPLocked(rRegP dst, memory mem) | |
7702 %{ | |
7703 match(Set dst (LoadPLocked mem)); | |
7704 | |
7705 ins_cost(125); // XXX | |
7706 format %{ "movq $dst, $mem\t# ptr locked" %} | |
7707 opcode(0x8B); | |
7708 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
7709 ins_pipe(ialu_reg_mem); // XXX | |
7710 %} | |
7711 | |
7712 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
7713 instruct loadLLocked(rRegL dst, memory mem) | |
7714 %{ | |
7715 match(Set dst (LoadLLocked mem)); | |
7716 | |
7717 ins_cost(125); // XXX | |
7718 format %{ "movq $dst, $mem\t# long locked" %} | |
7719 opcode(0x8B); | |
7720 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
7721 ins_pipe(ialu_reg_mem); // XXX | |
7722 %} | |
7723 | |
7724 // Conditional-store of the updated heap-top. | |
7725 // Used during allocation of the shared heap. | |
7726 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
7727 | |
7728 instruct storePConditional(memory heap_top_ptr, | |
7729 rax_RegP oldval, rRegP newval, | |
7730 rFlagsReg cr) | |
7731 %{ | |
7732 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7733 | |
7734 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " | |
7735 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
7736 opcode(0x0F, 0xB1); | |
7737 ins_encode(lock_prefix, | |
7738 REX_reg_mem_wide(newval, heap_top_ptr), | |
7739 OpcP, OpcS, | |
7740 reg_mem(newval, heap_top_ptr)); | |
7741 ins_pipe(pipe_cmpxchg); | |
7742 %} | |
7743 | |
7744 // Conditional-store of a long value | |
7745 // Returns a boolean value (0/1) on success. Implemented with a | |
7746 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI | |
7747 | |
7748 instruct storeLConditional(rRegI res, | |
7749 memory mem_ptr, | |
7750 rax_RegL oldval, rRegL newval, | |
7751 rFlagsReg cr) | |
7752 %{ | |
7753 match(Set res (StoreLConditional mem_ptr (Binary oldval newval))); | |
7754 effect(KILL cr); | |
7755 | |
7756 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) " | |
7757 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
7758 "sete $res\n\t" | |
7759 "movzbl $res, $res" %} | |
7760 opcode(0x0F, 0xB1); | |
7761 ins_encode(lock_prefix, | |
7762 REX_reg_mem_wide(newval, mem_ptr), | |
7763 OpcP, OpcS, | |
7764 reg_mem(newval, mem_ptr), | |
7765 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
7766 REX_reg_breg(res, res), // movzbl | |
7767 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
7768 ins_pipe(pipe_cmpxchg); | |
7769 %} | |
7770 | |
7771 // Conditional-store of a long value | |
7772 // ZF flag is set on success, reset otherwise. Implemented with a | |
7773 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI | |
7774 instruct storeLConditional_flags(memory mem_ptr, | |
7775 rax_RegL oldval, rRegL newval, | |
7776 rFlagsReg cr, | |
7777 immI0 zero) | |
7778 %{ | |
7779 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero)); | |
7780 | |
7781 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) " | |
7782 "If rax == $mem_ptr then store $newval into $mem_ptr" %} | |
7783 opcode(0x0F, 0xB1); | |
7784 ins_encode(lock_prefix, | |
7785 REX_reg_mem_wide(newval, mem_ptr), | |
7786 OpcP, OpcS, | |
7787 reg_mem(newval, mem_ptr)); | |
7788 ins_pipe(pipe_cmpxchg); | |
7789 %} | |
7790 | |
7791 instruct compareAndSwapP(rRegI res, | |
7792 memory mem_ptr, | |
7793 rax_RegP oldval, rRegP newval, | |
7794 rFlagsReg cr) | |
7795 %{ | |
7796 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
7797 effect(KILL cr, KILL oldval); | |
7798 | |
7799 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
7800 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
7801 "sete $res\n\t" | |
7802 "movzbl $res, $res" %} | |
7803 opcode(0x0F, 0xB1); | |
7804 ins_encode(lock_prefix, | |
7805 REX_reg_mem_wide(newval, mem_ptr), | |
7806 OpcP, OpcS, | |
7807 reg_mem(newval, mem_ptr), | |
7808 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
7809 REX_reg_breg(res, res), // movzbl | |
7810 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
7811 ins_pipe( pipe_cmpxchg ); | |
7812 %} | |
7813 | |
7814 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7815 instruct compareAndSwapL(rRegI res, | |
7816 memory mem_ptr, | |
7817 rax_RegL oldval, rRegL newval, | |
7818 rFlagsReg cr) | |
7819 %{ | |
7820 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
7821 effect(KILL cr, KILL oldval); | |
7822 | |
7823 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
7824 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
7825 "sete $res\n\t" | |
7826 "movzbl $res, $res" %} | |
7827 opcode(0x0F, 0xB1); | |
7828 ins_encode(lock_prefix, | |
7829 REX_reg_mem_wide(newval, mem_ptr), | |
7830 OpcP, OpcS, | |
7831 reg_mem(newval, mem_ptr), | |
7832 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
7833 REX_reg_breg(res, res), // movzbl | |
7834 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
7835 ins_pipe( pipe_cmpxchg ); | |
7836 %} | |
7837 | |
7838 instruct compareAndSwapI(rRegI res, | |
7839 memory mem_ptr, | |
7840 rax_RegI oldval, rRegI newval, | |
7841 rFlagsReg cr) | |
7842 %{ | |
7843 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7844 effect(KILL cr, KILL oldval); | |
7845 | |
7846 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
7847 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
7848 "sete $res\n\t" | |
7849 "movzbl $res, $res" %} | |
7850 opcode(0x0F, 0xB1); | |
7851 ins_encode(lock_prefix, | |
7852 REX_reg_mem(newval, mem_ptr), | |
7853 OpcP, OpcS, | |
7854 reg_mem(newval, mem_ptr), | |
7855 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
7856 REX_reg_breg(res, res), // movzbl | |
7857 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
7858 ins_pipe( pipe_cmpxchg ); | |
7859 %} | |
7860 | |
7861 | |
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7862 instruct compareAndSwapN(rRegI res, |
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7863 memory mem_ptr, |
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7864 rax_RegN oldval, rRegN newval, |
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7865 rFlagsReg cr) %{ |
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7866 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7867 effect(KILL cr, KILL oldval); |
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7868 |
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7869 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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7870 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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7871 "sete $res\n\t" |
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7872 "movzbl $res, $res" %} |
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7873 opcode(0x0F, 0xB1); |
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7874 ins_encode(lock_prefix, |
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7875 REX_reg_mem(newval, mem_ptr), |
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7876 OpcP, OpcS, |
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7877 reg_mem(newval, mem_ptr), |
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7878 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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7879 REX_reg_breg(res, res), // movzbl |
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7880 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
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7881 ins_pipe( pipe_cmpxchg ); |
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7882 %} |
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7883 |
0 | 7884 //----------Subtraction Instructions------------------------------------------- |
7885 | |
7886 // Integer Subtraction Instructions | |
7887 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
7888 %{ | |
7889 match(Set dst (SubI dst src)); | |
7890 effect(KILL cr); | |
7891 | |
7892 format %{ "subl $dst, $src\t# int" %} | |
7893 opcode(0x2B); | |
7894 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
7895 ins_pipe(ialu_reg_reg); | |
7896 %} | |
7897 | |
7898 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
7899 %{ | |
7900 match(Set dst (SubI dst src)); | |
7901 effect(KILL cr); | |
7902 | |
7903 format %{ "subl $dst, $src\t# int" %} | |
7904 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
7905 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
7906 ins_pipe(ialu_reg); | |
7907 %} | |
7908 | |
7909 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
7910 %{ | |
7911 match(Set dst (SubI dst (LoadI src))); | |
7912 effect(KILL cr); | |
7913 | |
7914 ins_cost(125); | |
7915 format %{ "subl $dst, $src\t# int" %} | |
7916 opcode(0x2B); | |
7917 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
7918 ins_pipe(ialu_reg_mem); | |
7919 %} | |
7920 | |
7921 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
7922 %{ | |
7923 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
7924 effect(KILL cr); | |
7925 | |
7926 ins_cost(150); | |
7927 format %{ "subl $dst, $src\t# int" %} | |
7928 opcode(0x29); /* Opcode 29 /r */ | |
7929 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
7930 ins_pipe(ialu_mem_reg); | |
7931 %} | |
7932 | |
7933 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
7934 %{ | |
7935 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
7936 effect(KILL cr); | |
7937 | |
7938 ins_cost(125); // XXX | |
7939 format %{ "subl $dst, $src\t# int" %} | |
7940 opcode(0x81); /* Opcode 81 /5 id */ | |
7941 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
7942 ins_pipe(ialu_mem_imm); | |
7943 %} | |
7944 | |
7945 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
7946 %{ | |
7947 match(Set dst (SubL dst src)); | |
7948 effect(KILL cr); | |
7949 | |
7950 format %{ "subq $dst, $src\t# long" %} | |
7951 opcode(0x2B); | |
7952 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
7953 ins_pipe(ialu_reg_reg); | |
7954 %} | |
7955 | |
7956 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
7957 %{ | |
7958 match(Set dst (SubL dst src)); | |
7959 effect(KILL cr); | |
7960 | |
7961 format %{ "subq $dst, $src\t# long" %} | |
7962 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
7963 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
7964 ins_pipe(ialu_reg); | |
7965 %} | |
7966 | |
7967 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
7968 %{ | |
7969 match(Set dst (SubL dst (LoadL src))); | |
7970 effect(KILL cr); | |
7971 | |
7972 ins_cost(125); | |
7973 format %{ "subq $dst, $src\t# long" %} | |
7974 opcode(0x2B); | |
7975 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
7976 ins_pipe(ialu_reg_mem); | |
7977 %} | |
7978 | |
7979 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
7980 %{ | |
7981 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
7982 effect(KILL cr); | |
7983 | |
7984 ins_cost(150); | |
7985 format %{ "subq $dst, $src\t# long" %} | |
7986 opcode(0x29); /* Opcode 29 /r */ | |
7987 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
7988 ins_pipe(ialu_mem_reg); | |
7989 %} | |
7990 | |
7991 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
7992 %{ | |
7993 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
7994 effect(KILL cr); | |
7995 | |
7996 ins_cost(125); // XXX | |
7997 format %{ "subq $dst, $src\t# long" %} | |
7998 opcode(0x81); /* Opcode 81 /5 id */ | |
7999 ins_encode(REX_mem_wide(dst), | |
8000 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
8001 ins_pipe(ialu_mem_imm); | |
8002 %} | |
8003 | |
8004 // Subtract from a pointer | |
8005 // XXX hmpf??? | |
8006 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
8007 %{ | |
8008 match(Set dst (AddP dst (SubI zero src))); | |
8009 effect(KILL cr); | |
8010 | |
8011 format %{ "subq $dst, $src\t# ptr - int" %} | |
8012 opcode(0x2B); | |
8013 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
8014 ins_pipe(ialu_reg_reg); | |
8015 %} | |
8016 | |
8017 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
8018 %{ | |
8019 match(Set dst (SubI zero dst)); | |
8020 effect(KILL cr); | |
8021 | |
8022 format %{ "negl $dst\t# int" %} | |
8023 opcode(0xF7, 0x03); // Opcode F7 /3 | |
8024 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8025 ins_pipe(ialu_reg); | |
8026 %} | |
8027 | |
8028 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
8029 %{ | |
8030 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
8031 effect(KILL cr); | |
8032 | |
8033 format %{ "negl $dst\t# int" %} | |
8034 opcode(0xF7, 0x03); // Opcode F7 /3 | |
8035 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8036 ins_pipe(ialu_reg); | |
8037 %} | |
8038 | |
8039 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
8040 %{ | |
8041 match(Set dst (SubL zero dst)); | |
8042 effect(KILL cr); | |
8043 | |
8044 format %{ "negq $dst\t# long" %} | |
8045 opcode(0xF7, 0x03); // Opcode F7 /3 | |
8046 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8047 ins_pipe(ialu_reg); | |
8048 %} | |
8049 | |
8050 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
8051 %{ | |
8052 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
8053 effect(KILL cr); | |
8054 | |
8055 format %{ "negq $dst\t# long" %} | |
8056 opcode(0xF7, 0x03); // Opcode F7 /3 | |
8057 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8058 ins_pipe(ialu_reg); | |
8059 %} | |
8060 | |
8061 | |
8062 //----------Multiplication/Division Instructions------------------------------- | |
8063 // Integer Multiplication Instructions | |
8064 // Multiply Register | |
8065 | |
8066 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
8067 %{ | |
8068 match(Set dst (MulI dst src)); | |
8069 effect(KILL cr); | |
8070 | |
8071 ins_cost(300); | |
8072 format %{ "imull $dst, $src\t# int" %} | |
8073 opcode(0x0F, 0xAF); | |
8074 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
8075 ins_pipe(ialu_reg_reg_alu0); | |
8076 %} | |
8077 | |
8078 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
8079 %{ | |
8080 match(Set dst (MulI src imm)); | |
8081 effect(KILL cr); | |
8082 | |
8083 ins_cost(300); | |
8084 format %{ "imull $dst, $src, $imm\t# int" %} | |
8085 opcode(0x69); /* 69 /r id */ | |
8086 ins_encode(REX_reg_reg(dst, src), | |
8087 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
8088 ins_pipe(ialu_reg_reg_alu0); | |
8089 %} | |
8090 | |
8091 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
8092 %{ | |
8093 match(Set dst (MulI dst (LoadI src))); | |
8094 effect(KILL cr); | |
8095 | |
8096 ins_cost(350); | |
8097 format %{ "imull $dst, $src\t# int" %} | |
8098 opcode(0x0F, 0xAF); | |
8099 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
8100 ins_pipe(ialu_reg_mem_alu0); | |
8101 %} | |
8102 | |
8103 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
8104 %{ | |
8105 match(Set dst (MulI (LoadI src) imm)); | |
8106 effect(KILL cr); | |
8107 | |
8108 ins_cost(300); | |
8109 format %{ "imull $dst, $src, $imm\t# int" %} | |
8110 opcode(0x69); /* 69 /r id */ | |
8111 ins_encode(REX_reg_mem(dst, src), | |
8112 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
8113 ins_pipe(ialu_reg_mem_alu0); | |
8114 %} | |
8115 | |
8116 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
8117 %{ | |
8118 match(Set dst (MulL dst src)); | |
8119 effect(KILL cr); | |
8120 | |
8121 ins_cost(300); | |
8122 format %{ "imulq $dst, $src\t# long" %} | |
8123 opcode(0x0F, 0xAF); | |
8124 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
8125 ins_pipe(ialu_reg_reg_alu0); | |
8126 %} | |
8127 | |
8128 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
8129 %{ | |
8130 match(Set dst (MulL src imm)); | |
8131 effect(KILL cr); | |
8132 | |
8133 ins_cost(300); | |
8134 format %{ "imulq $dst, $src, $imm\t# long" %} | |
8135 opcode(0x69); /* 69 /r id */ | |
8136 ins_encode(REX_reg_reg_wide(dst, src), | |
8137 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
8138 ins_pipe(ialu_reg_reg_alu0); | |
8139 %} | |
8140 | |
8141 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
8142 %{ | |
8143 match(Set dst (MulL dst (LoadL src))); | |
8144 effect(KILL cr); | |
8145 | |
8146 ins_cost(350); | |
8147 format %{ "imulq $dst, $src\t# long" %} | |
8148 opcode(0x0F, 0xAF); | |
8149 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
8150 ins_pipe(ialu_reg_mem_alu0); | |
8151 %} | |
8152 | |
8153 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
8154 %{ | |
8155 match(Set dst (MulL (LoadL src) imm)); | |
8156 effect(KILL cr); | |
8157 | |
8158 ins_cost(300); | |
8159 format %{ "imulq $dst, $src, $imm\t# long" %} | |
8160 opcode(0x69); /* 69 /r id */ | |
8161 ins_encode(REX_reg_mem_wide(dst, src), | |
8162 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
8163 ins_pipe(ialu_reg_mem_alu0); | |
8164 %} | |
8165 | |
145 | 8166 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
8167 %{ | |
8168 match(Set dst (MulHiL src rax)); | |
8169 effect(USE_KILL rax, KILL cr); | |
8170 | |
8171 ins_cost(300); | |
8172 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
8173 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
8174 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
8175 ins_pipe(ialu_reg_reg_alu0); | |
8176 %} | |
8177 | |
0 | 8178 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
8179 rFlagsReg cr) | |
8180 %{ | |
8181 match(Set rax (DivI rax div)); | |
8182 effect(KILL rdx, KILL cr); | |
8183 | |
8184 ins_cost(30*100+10*100); // XXX | |
8185 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
8186 "jne,s normal\n\t" | |
8187 "xorl rdx, rdx\n\t" | |
8188 "cmpl $div, -1\n\t" | |
8189 "je,s done\n" | |
8190 "normal: cdql\n\t" | |
8191 "idivl $div\n" | |
8192 "done:" %} | |
8193 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8194 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
8195 ins_pipe(ialu_reg_reg_alu0); | |
8196 %} | |
8197 | |
8198 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
8199 rFlagsReg cr) | |
8200 %{ | |
8201 match(Set rax (DivL rax div)); | |
8202 effect(KILL rdx, KILL cr); | |
8203 | |
8204 ins_cost(30*100+10*100); // XXX | |
8205 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
8206 "cmpq rax, rdx\n\t" | |
8207 "jne,s normal\n\t" | |
8208 "xorl rdx, rdx\n\t" | |
8209 "cmpq $div, -1\n\t" | |
8210 "je,s done\n" | |
8211 "normal: cdqq\n\t" | |
8212 "idivq $div\n" | |
8213 "done:" %} | |
8214 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8215 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
8216 ins_pipe(ialu_reg_reg_alu0); | |
8217 %} | |
8218 | |
8219 // Integer DIVMOD with Register, both quotient and mod results | |
8220 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
8221 rFlagsReg cr) | |
8222 %{ | |
8223 match(DivModI rax div); | |
8224 effect(KILL cr); | |
8225 | |
8226 ins_cost(30*100+10*100); // XXX | |
8227 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
8228 "jne,s normal\n\t" | |
8229 "xorl rdx, rdx\n\t" | |
8230 "cmpl $div, -1\n\t" | |
8231 "je,s done\n" | |
8232 "normal: cdql\n\t" | |
8233 "idivl $div\n" | |
8234 "done:" %} | |
8235 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8236 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
8237 ins_pipe(pipe_slow); | |
8238 %} | |
8239 | |
8240 // Long DIVMOD with Register, both quotient and mod results | |
8241 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
8242 rFlagsReg cr) | |
8243 %{ | |
8244 match(DivModL rax div); | |
8245 effect(KILL cr); | |
8246 | |
8247 ins_cost(30*100+10*100); // XXX | |
8248 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
8249 "cmpq rax, rdx\n\t" | |
8250 "jne,s normal\n\t" | |
8251 "xorl rdx, rdx\n\t" | |
8252 "cmpq $div, -1\n\t" | |
8253 "je,s done\n" | |
8254 "normal: cdqq\n\t" | |
8255 "idivq $div\n" | |
8256 "done:" %} | |
8257 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8258 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
8259 ins_pipe(pipe_slow); | |
8260 %} | |
8261 | |
8262 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
8263 // DivI cases are handled by the compiler | |
8264 | |
8265 // Magic constant, reciprical of 10 | |
8266 instruct loadConL_0x6666666666666667(rRegL dst) | |
8267 %{ | |
8268 effect(DEF dst); | |
8269 | |
8270 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
8271 ins_encode(load_immL(dst, 0x6666666666666667)); | |
8272 ins_pipe(ialu_reg); | |
8273 %} | |
8274 | |
8275 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
8276 %{ | |
8277 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
8278 | |
8279 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
8280 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
8281 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
8282 ins_pipe(ialu_reg_reg_alu0); | |
8283 %} | |
8284 | |
8285 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
8286 %{ | |
8287 effect(USE_DEF dst, KILL cr); | |
8288 | |
8289 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
8290 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8291 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
8292 ins_pipe(ialu_reg); | |
8293 %} | |
8294 | |
8295 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
8296 %{ | |
8297 effect(USE_DEF dst, KILL cr); | |
8298 | |
8299 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
8300 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8301 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
8302 ins_pipe(ialu_reg); | |
8303 %} | |
8304 | |
8305 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
8306 %{ | |
8307 match(Set dst (DivL src div)); | |
8308 | |
8309 ins_cost((5+8)*100); | |
8310 expand %{ | |
8311 rax_RegL rax; // Killed temp | |
8312 rFlagsReg cr; // Killed | |
8313 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
8314 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
8315 sarL_rReg_63(src, cr); // sarq src, 63 | |
8316 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
8317 subL_rReg(dst, src, cr); // subl rdx, src | |
8318 %} | |
8319 %} | |
8320 | |
8321 //----------------------------------------------------------------------------- | |
8322 | |
8323 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
8324 rFlagsReg cr) | |
8325 %{ | |
8326 match(Set rdx (ModI rax div)); | |
8327 effect(KILL rax, KILL cr); | |
8328 | |
8329 ins_cost(300); // XXX | |
8330 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
8331 "jne,s normal\n\t" | |
8332 "xorl rdx, rdx\n\t" | |
8333 "cmpl $div, -1\n\t" | |
8334 "je,s done\n" | |
8335 "normal: cdql\n\t" | |
8336 "idivl $div\n" | |
8337 "done:" %} | |
8338 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8339 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
8340 ins_pipe(ialu_reg_reg_alu0); | |
8341 %} | |
8342 | |
8343 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
8344 rFlagsReg cr) | |
8345 %{ | |
8346 match(Set rdx (ModL rax div)); | |
8347 effect(KILL rax, KILL cr); | |
8348 | |
8349 ins_cost(300); // XXX | |
8350 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
8351 "cmpq rax, rdx\n\t" | |
8352 "jne,s normal\n\t" | |
8353 "xorl rdx, rdx\n\t" | |
8354 "cmpq $div, -1\n\t" | |
8355 "je,s done\n" | |
8356 "normal: cdqq\n\t" | |
8357 "idivq $div\n" | |
8358 "done:" %} | |
8359 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
8360 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
8361 ins_pipe(ialu_reg_reg_alu0); | |
8362 %} | |
8363 | |
8364 // Integer Shift Instructions | |
8365 // Shift Left by one | |
8366 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
8367 %{ | |
8368 match(Set dst (LShiftI dst shift)); | |
8369 effect(KILL cr); | |
8370 | |
8371 format %{ "sall $dst, $shift" %} | |
8372 opcode(0xD1, 0x4); /* D1 /4 */ | |
8373 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8374 ins_pipe(ialu_reg); | |
8375 %} | |
8376 | |
8377 // Shift Left by one | |
8378 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8379 %{ | |
8380 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
8381 effect(KILL cr); | |
8382 | |
8383 format %{ "sall $dst, $shift\t" %} | |
8384 opcode(0xD1, 0x4); /* D1 /4 */ | |
8385 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8386 ins_pipe(ialu_mem_imm); | |
8387 %} | |
8388 | |
8389 // Shift Left by 8-bit immediate | |
8390 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
8391 %{ | |
8392 match(Set dst (LShiftI dst shift)); | |
8393 effect(KILL cr); | |
8394 | |
8395 format %{ "sall $dst, $shift" %} | |
8396 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
8397 ins_encode(reg_opc_imm(dst, shift)); | |
8398 ins_pipe(ialu_reg); | |
8399 %} | |
8400 | |
8401 // Shift Left by 8-bit immediate | |
8402 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8403 %{ | |
8404 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
8405 effect(KILL cr); | |
8406 | |
8407 format %{ "sall $dst, $shift" %} | |
8408 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
8409 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8410 ins_pipe(ialu_mem_imm); | |
8411 %} | |
8412 | |
8413 // Shift Left by variable | |
8414 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
8415 %{ | |
8416 match(Set dst (LShiftI dst shift)); | |
8417 effect(KILL cr); | |
8418 | |
8419 format %{ "sall $dst, $shift" %} | |
8420 opcode(0xD3, 0x4); /* D3 /4 */ | |
8421 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8422 ins_pipe(ialu_reg_reg); | |
8423 %} | |
8424 | |
8425 // Shift Left by variable | |
8426 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8427 %{ | |
8428 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
8429 effect(KILL cr); | |
8430 | |
8431 format %{ "sall $dst, $shift" %} | |
8432 opcode(0xD3, 0x4); /* D3 /4 */ | |
8433 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8434 ins_pipe(ialu_mem_reg); | |
8435 %} | |
8436 | |
8437 // Arithmetic shift right by one | |
8438 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
8439 %{ | |
8440 match(Set dst (RShiftI dst shift)); | |
8441 effect(KILL cr); | |
8442 | |
8443 format %{ "sarl $dst, $shift" %} | |
8444 opcode(0xD1, 0x7); /* D1 /7 */ | |
8445 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8446 ins_pipe(ialu_reg); | |
8447 %} | |
8448 | |
8449 // Arithmetic shift right by one | |
8450 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8451 %{ | |
8452 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
8453 effect(KILL cr); | |
8454 | |
8455 format %{ "sarl $dst, $shift" %} | |
8456 opcode(0xD1, 0x7); /* D1 /7 */ | |
8457 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8458 ins_pipe(ialu_mem_imm); | |
8459 %} | |
8460 | |
8461 // Arithmetic Shift Right by 8-bit immediate | |
8462 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
8463 %{ | |
8464 match(Set dst (RShiftI dst shift)); | |
8465 effect(KILL cr); | |
8466 | |
8467 format %{ "sarl $dst, $shift" %} | |
8468 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8469 ins_encode(reg_opc_imm(dst, shift)); | |
8470 ins_pipe(ialu_mem_imm); | |
8471 %} | |
8472 | |
8473 // Arithmetic Shift Right by 8-bit immediate | |
8474 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8475 %{ | |
8476 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
8477 effect(KILL cr); | |
8478 | |
8479 format %{ "sarl $dst, $shift" %} | |
8480 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8481 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8482 ins_pipe(ialu_mem_imm); | |
8483 %} | |
8484 | |
8485 // Arithmetic Shift Right by variable | |
8486 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
8487 %{ | |
8488 match(Set dst (RShiftI dst shift)); | |
8489 effect(KILL cr); | |
8490 | |
8491 format %{ "sarl $dst, $shift" %} | |
8492 opcode(0xD3, 0x7); /* D3 /7 */ | |
8493 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8494 ins_pipe(ialu_reg_reg); | |
8495 %} | |
8496 | |
8497 // Arithmetic Shift Right by variable | |
8498 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8499 %{ | |
8500 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
8501 effect(KILL cr); | |
8502 | |
8503 format %{ "sarl $dst, $shift" %} | |
8504 opcode(0xD3, 0x7); /* D3 /7 */ | |
8505 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8506 ins_pipe(ialu_mem_reg); | |
8507 %} | |
8508 | |
8509 // Logical shift right by one | |
8510 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
8511 %{ | |
8512 match(Set dst (URShiftI dst shift)); | |
8513 effect(KILL cr); | |
8514 | |
8515 format %{ "shrl $dst, $shift" %} | |
8516 opcode(0xD1, 0x5); /* D1 /5 */ | |
8517 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8518 ins_pipe(ialu_reg); | |
8519 %} | |
8520 | |
8521 // Logical shift right by one | |
8522 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8523 %{ | |
8524 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
8525 effect(KILL cr); | |
8526 | |
8527 format %{ "shrl $dst, $shift" %} | |
8528 opcode(0xD1, 0x5); /* D1 /5 */ | |
8529 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8530 ins_pipe(ialu_mem_imm); | |
8531 %} | |
8532 | |
8533 // Logical Shift Right by 8-bit immediate | |
8534 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
8535 %{ | |
8536 match(Set dst (URShiftI dst shift)); | |
8537 effect(KILL cr); | |
8538 | |
8539 format %{ "shrl $dst, $shift" %} | |
8540 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
8541 ins_encode(reg_opc_imm(dst, shift)); | |
8542 ins_pipe(ialu_reg); | |
8543 %} | |
8544 | |
8545 // Logical Shift Right by 8-bit immediate | |
8546 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8547 %{ | |
8548 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
8549 effect(KILL cr); | |
8550 | |
8551 format %{ "shrl $dst, $shift" %} | |
8552 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
8553 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8554 ins_pipe(ialu_mem_imm); | |
8555 %} | |
8556 | |
8557 // Logical Shift Right by variable | |
8558 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
8559 %{ | |
8560 match(Set dst (URShiftI dst shift)); | |
8561 effect(KILL cr); | |
8562 | |
8563 format %{ "shrl $dst, $shift" %} | |
8564 opcode(0xD3, 0x5); /* D3 /5 */ | |
8565 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8566 ins_pipe(ialu_reg_reg); | |
8567 %} | |
8568 | |
8569 // Logical Shift Right by variable | |
8570 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8571 %{ | |
8572 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
8573 effect(KILL cr); | |
8574 | |
8575 format %{ "shrl $dst, $shift" %} | |
8576 opcode(0xD3, 0x5); /* D3 /5 */ | |
8577 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8578 ins_pipe(ialu_mem_reg); | |
8579 %} | |
8580 | |
8581 // Long Shift Instructions | |
8582 // Shift Left by one | |
8583 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
8584 %{ | |
8585 match(Set dst (LShiftL dst shift)); | |
8586 effect(KILL cr); | |
8587 | |
8588 format %{ "salq $dst, $shift" %} | |
8589 opcode(0xD1, 0x4); /* D1 /4 */ | |
8590 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8591 ins_pipe(ialu_reg); | |
8592 %} | |
8593 | |
8594 // Shift Left by one | |
8595 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8596 %{ | |
8597 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
8598 effect(KILL cr); | |
8599 | |
8600 format %{ "salq $dst, $shift" %} | |
8601 opcode(0xD1, 0x4); /* D1 /4 */ | |
8602 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8603 ins_pipe(ialu_mem_imm); | |
8604 %} | |
8605 | |
8606 // Shift Left by 8-bit immediate | |
8607 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
8608 %{ | |
8609 match(Set dst (LShiftL dst shift)); | |
8610 effect(KILL cr); | |
8611 | |
8612 format %{ "salq $dst, $shift" %} | |
8613 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
8614 ins_encode(reg_opc_imm_wide(dst, shift)); | |
8615 ins_pipe(ialu_reg); | |
8616 %} | |
8617 | |
8618 // Shift Left by 8-bit immediate | |
8619 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8620 %{ | |
8621 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
8622 effect(KILL cr); | |
8623 | |
8624 format %{ "salq $dst, $shift" %} | |
8625 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
8626 ins_encode(REX_mem_wide(dst), OpcP, | |
8627 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8628 ins_pipe(ialu_mem_imm); | |
8629 %} | |
8630 | |
8631 // Shift Left by variable | |
8632 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
8633 %{ | |
8634 match(Set dst (LShiftL dst shift)); | |
8635 effect(KILL cr); | |
8636 | |
8637 format %{ "salq $dst, $shift" %} | |
8638 opcode(0xD3, 0x4); /* D3 /4 */ | |
8639 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8640 ins_pipe(ialu_reg_reg); | |
8641 %} | |
8642 | |
8643 // Shift Left by variable | |
8644 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8645 %{ | |
8646 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
8647 effect(KILL cr); | |
8648 | |
8649 format %{ "salq $dst, $shift" %} | |
8650 opcode(0xD3, 0x4); /* D3 /4 */ | |
8651 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8652 ins_pipe(ialu_mem_reg); | |
8653 %} | |
8654 | |
8655 // Arithmetic shift right by one | |
8656 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
8657 %{ | |
8658 match(Set dst (RShiftL dst shift)); | |
8659 effect(KILL cr); | |
8660 | |
8661 format %{ "sarq $dst, $shift" %} | |
8662 opcode(0xD1, 0x7); /* D1 /7 */ | |
8663 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8664 ins_pipe(ialu_reg); | |
8665 %} | |
8666 | |
8667 // Arithmetic shift right by one | |
8668 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8669 %{ | |
8670 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
8671 effect(KILL cr); | |
8672 | |
8673 format %{ "sarq $dst, $shift" %} | |
8674 opcode(0xD1, 0x7); /* D1 /7 */ | |
8675 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8676 ins_pipe(ialu_mem_imm); | |
8677 %} | |
8678 | |
8679 // Arithmetic Shift Right by 8-bit immediate | |
8680 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
8681 %{ | |
8682 match(Set dst (RShiftL dst shift)); | |
8683 effect(KILL cr); | |
8684 | |
8685 format %{ "sarq $dst, $shift" %} | |
8686 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8687 ins_encode(reg_opc_imm_wide(dst, shift)); | |
8688 ins_pipe(ialu_mem_imm); | |
8689 %} | |
8690 | |
8691 // Arithmetic Shift Right by 8-bit immediate | |
8692 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8693 %{ | |
8694 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
8695 effect(KILL cr); | |
8696 | |
8697 format %{ "sarq $dst, $shift" %} | |
8698 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
8699 ins_encode(REX_mem_wide(dst), OpcP, | |
8700 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8701 ins_pipe(ialu_mem_imm); | |
8702 %} | |
8703 | |
8704 // Arithmetic Shift Right by variable | |
8705 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
8706 %{ | |
8707 match(Set dst (RShiftL dst shift)); | |
8708 effect(KILL cr); | |
8709 | |
8710 format %{ "sarq $dst, $shift" %} | |
8711 opcode(0xD3, 0x7); /* D3 /7 */ | |
8712 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8713 ins_pipe(ialu_reg_reg); | |
8714 %} | |
8715 | |
8716 // Arithmetic Shift Right by variable | |
8717 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8718 %{ | |
8719 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
8720 effect(KILL cr); | |
8721 | |
8722 format %{ "sarq $dst, $shift" %} | |
8723 opcode(0xD3, 0x7); /* D3 /7 */ | |
8724 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8725 ins_pipe(ialu_mem_reg); | |
8726 %} | |
8727 | |
8728 // Logical shift right by one | |
8729 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
8730 %{ | |
8731 match(Set dst (URShiftL dst shift)); | |
8732 effect(KILL cr); | |
8733 | |
8734 format %{ "shrq $dst, $shift" %} | |
8735 opcode(0xD1, 0x5); /* D1 /5 */ | |
8736 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
8737 ins_pipe(ialu_reg); | |
8738 %} | |
8739 | |
8740 // Logical shift right by one | |
8741 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
8742 %{ | |
8743 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
8744 effect(KILL cr); | |
8745 | |
8746 format %{ "shrq $dst, $shift" %} | |
8747 opcode(0xD1, 0x5); /* D1 /5 */ | |
8748 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8749 ins_pipe(ialu_mem_imm); | |
8750 %} | |
8751 | |
8752 // Logical Shift Right by 8-bit immediate | |
8753 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
8754 %{ | |
8755 match(Set dst (URShiftL dst shift)); | |
8756 effect(KILL cr); | |
8757 | |
8758 format %{ "shrq $dst, $shift" %} | |
8759 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
8760 ins_encode(reg_opc_imm_wide(dst, shift)); | |
8761 ins_pipe(ialu_reg); | |
8762 %} | |
8763 | |
8764 // Logical Shift Right by 8-bit immediate | |
8765 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
8766 %{ | |
8767 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
8768 effect(KILL cr); | |
8769 | |
8770 format %{ "shrq $dst, $shift" %} | |
8771 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
8772 ins_encode(REX_mem_wide(dst), OpcP, | |
8773 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
8774 ins_pipe(ialu_mem_imm); | |
8775 %} | |
8776 | |
8777 // Logical Shift Right by variable | |
8778 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
8779 %{ | |
8780 match(Set dst (URShiftL dst shift)); | |
8781 effect(KILL cr); | |
8782 | |
8783 format %{ "shrq $dst, $shift" %} | |
8784 opcode(0xD3, 0x5); /* D3 /5 */ | |
8785 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8786 ins_pipe(ialu_reg_reg); | |
8787 %} | |
8788 | |
8789 // Logical Shift Right by variable | |
8790 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
8791 %{ | |
8792 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
8793 effect(KILL cr); | |
8794 | |
8795 format %{ "shrq $dst, $shift" %} | |
8796 opcode(0xD3, 0x5); /* D3 /5 */ | |
8797 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
8798 ins_pipe(ialu_mem_reg); | |
8799 %} | |
8800 | |
8801 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
8802 // This idiom is used by the compiler for the i2b bytecode. | |
8803 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
8804 %{ | |
8805 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
8806 | |
8807 format %{ "movsbl $dst, $src\t# i2b" %} | |
8808 opcode(0x0F, 0xBE); | |
8809 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
8810 ins_pipe(ialu_reg_reg); | |
8811 %} | |
8812 | |
8813 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
8814 // This idiom is used by the compiler the i2s bytecode. | |
8815 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
8816 %{ | |
8817 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
8818 | |
8819 format %{ "movswl $dst, $src\t# i2s" %} | |
8820 opcode(0x0F, 0xBF); | |
8821 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
8822 ins_pipe(ialu_reg_reg); | |
8823 %} | |
8824 | |
8825 // ROL/ROR instructions | |
8826 | |
8827 // ROL expand | |
8828 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
8829 effect(KILL cr, USE_DEF dst); | |
8830 | |
8831 format %{ "roll $dst" %} | |
8832 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
8833 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8834 ins_pipe(ialu_reg); | |
8835 %} | |
8836 | |
8837 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
8838 effect(USE_DEF dst, USE shift, KILL cr); | |
8839 | |
8840 format %{ "roll $dst, $shift" %} | |
8841 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
8842 ins_encode( reg_opc_imm(dst, shift) ); | |
8843 ins_pipe(ialu_reg); | |
8844 %} | |
8845 | |
8846 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
8847 %{ | |
8848 effect(USE_DEF dst, USE shift, KILL cr); | |
8849 | |
8850 format %{ "roll $dst, $shift" %} | |
8851 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
8852 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8853 ins_pipe(ialu_reg_reg); | |
8854 %} | |
8855 // end of ROL expand | |
8856 | |
8857 // Rotate Left by one | |
8858 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
8859 %{ | |
8860 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
8861 | |
8862 expand %{ | |
8863 rolI_rReg_imm1(dst, cr); | |
8864 %} | |
8865 %} | |
8866 | |
8867 // Rotate Left by 8-bit immediate | |
8868 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
8869 %{ | |
8870 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
8871 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
8872 | |
8873 expand %{ | |
8874 rolI_rReg_imm8(dst, lshift, cr); | |
8875 %} | |
8876 %} | |
8877 | |
8878 // Rotate Left by variable | |
8879 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
8880 %{ | |
8881 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
8882 | |
8883 expand %{ | |
8884 rolI_rReg_CL(dst, shift, cr); | |
8885 %} | |
8886 %} | |
8887 | |
8888 // Rotate Left by variable | |
8889 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
8890 %{ | |
8891 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
8892 | |
8893 expand %{ | |
8894 rolI_rReg_CL(dst, shift, cr); | |
8895 %} | |
8896 %} | |
8897 | |
8898 // ROR expand | |
8899 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
8900 %{ | |
8901 effect(USE_DEF dst, KILL cr); | |
8902 | |
8903 format %{ "rorl $dst" %} | |
8904 opcode(0xD1, 0x1); /* D1 /1 */ | |
8905 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8906 ins_pipe(ialu_reg); | |
8907 %} | |
8908 | |
8909 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
8910 %{ | |
8911 effect(USE_DEF dst, USE shift, KILL cr); | |
8912 | |
8913 format %{ "rorl $dst, $shift" %} | |
8914 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
8915 ins_encode(reg_opc_imm(dst, shift)); | |
8916 ins_pipe(ialu_reg); | |
8917 %} | |
8918 | |
8919 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
8920 %{ | |
8921 effect(USE_DEF dst, USE shift, KILL cr); | |
8922 | |
8923 format %{ "rorl $dst, $shift" %} | |
8924 opcode(0xD3, 0x1); /* D3 /1 */ | |
8925 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
8926 ins_pipe(ialu_reg_reg); | |
8927 %} | |
8928 // end of ROR expand | |
8929 | |
8930 // Rotate Right by one | |
8931 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
8932 %{ | |
8933 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
8934 | |
8935 expand %{ | |
8936 rorI_rReg_imm1(dst, cr); | |
8937 %} | |
8938 %} | |
8939 | |
8940 // Rotate Right by 8-bit immediate | |
8941 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
8942 %{ | |
8943 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
8944 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
8945 | |
8946 expand %{ | |
8947 rorI_rReg_imm8(dst, rshift, cr); | |
8948 %} | |
8949 %} | |
8950 | |
8951 // Rotate Right by variable | |
8952 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
8953 %{ | |
8954 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
8955 | |
8956 expand %{ | |
8957 rorI_rReg_CL(dst, shift, cr); | |
8958 %} | |
8959 %} | |
8960 | |
8961 // Rotate Right by variable | |
8962 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
8963 %{ | |
8964 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
8965 | |
8966 expand %{ | |
8967 rorI_rReg_CL(dst, shift, cr); | |
8968 %} | |
8969 %} | |
8970 | |
8971 // for long rotate | |
8972 // ROL expand | |
8973 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
8974 effect(USE_DEF dst, KILL cr); | |
8975 | |
8976 format %{ "rolq $dst" %} | |
8977 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
8978 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8979 ins_pipe(ialu_reg); | |
8980 %} | |
8981 | |
8982 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
8983 effect(USE_DEF dst, USE shift, KILL cr); | |
8984 | |
8985 format %{ "rolq $dst, $shift" %} | |
8986 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
8987 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
8988 ins_pipe(ialu_reg); | |
8989 %} | |
8990 | |
8991 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
8992 %{ | |
8993 effect(USE_DEF dst, USE shift, KILL cr); | |
8994 | |
8995 format %{ "rolq $dst, $shift" %} | |
8996 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
8997 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
8998 ins_pipe(ialu_reg_reg); | |
8999 %} | |
9000 // end of ROL expand | |
9001 | |
9002 // Rotate Left by one | |
9003 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
9004 %{ | |
9005 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
9006 | |
9007 expand %{ | |
9008 rolL_rReg_imm1(dst, cr); | |
9009 %} | |
9010 %} | |
9011 | |
9012 // Rotate Left by 8-bit immediate | |
9013 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
9014 %{ | |
9015 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
9016 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
9017 | |
9018 expand %{ | |
9019 rolL_rReg_imm8(dst, lshift, cr); | |
9020 %} | |
9021 %} | |
9022 | |
9023 // Rotate Left by variable | |
9024 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
9025 %{ | |
9026 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
9027 | |
9028 expand %{ | |
9029 rolL_rReg_CL(dst, shift, cr); | |
9030 %} | |
9031 %} | |
9032 | |
9033 // Rotate Left by variable | |
9034 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
9035 %{ | |
9036 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
9037 | |
9038 expand %{ | |
9039 rolL_rReg_CL(dst, shift, cr); | |
9040 %} | |
9041 %} | |
9042 | |
9043 // ROR expand | |
9044 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
9045 %{ | |
9046 effect(USE_DEF dst, KILL cr); | |
9047 | |
9048 format %{ "rorq $dst" %} | |
9049 opcode(0xD1, 0x1); /* D1 /1 */ | |
9050 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
9051 ins_pipe(ialu_reg); | |
9052 %} | |
9053 | |
9054 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
9055 %{ | |
9056 effect(USE_DEF dst, USE shift, KILL cr); | |
9057 | |
9058 format %{ "rorq $dst, $shift" %} | |
9059 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
9060 ins_encode(reg_opc_imm_wide(dst, shift)); | |
9061 ins_pipe(ialu_reg); | |
9062 %} | |
9063 | |
9064 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
9065 %{ | |
9066 effect(USE_DEF dst, USE shift, KILL cr); | |
9067 | |
9068 format %{ "rorq $dst, $shift" %} | |
9069 opcode(0xD3, 0x1); /* D3 /1 */ | |
9070 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
9071 ins_pipe(ialu_reg_reg); | |
9072 %} | |
9073 // end of ROR expand | |
9074 | |
9075 // Rotate Right by one | |
9076 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
9077 %{ | |
9078 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
9079 | |
9080 expand %{ | |
9081 rorL_rReg_imm1(dst, cr); | |
9082 %} | |
9083 %} | |
9084 | |
9085 // Rotate Right by 8-bit immediate | |
9086 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
9087 %{ | |
9088 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
9089 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
9090 | |
9091 expand %{ | |
9092 rorL_rReg_imm8(dst, rshift, cr); | |
9093 %} | |
9094 %} | |
9095 | |
9096 // Rotate Right by variable | |
9097 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
9098 %{ | |
9099 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
9100 | |
9101 expand %{ | |
9102 rorL_rReg_CL(dst, shift, cr); | |
9103 %} | |
9104 %} | |
9105 | |
9106 // Rotate Right by variable | |
9107 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
9108 %{ | |
9109 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
9110 | |
9111 expand %{ | |
9112 rorL_rReg_CL(dst, shift, cr); | |
9113 %} | |
9114 %} | |
9115 | |
9116 // Logical Instructions | |
9117 | |
9118 // Integer Logical Instructions | |
9119 | |
9120 // And Instructions | |
9121 // And Register with Register | |
9122 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
9123 %{ | |
9124 match(Set dst (AndI dst src)); | |
9125 effect(KILL cr); | |
9126 | |
9127 format %{ "andl $dst, $src\t# int" %} | |
9128 opcode(0x23); | |
9129 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
9130 ins_pipe(ialu_reg_reg); | |
9131 %} | |
9132 | |
9133 // And Register with Immediate 255 | |
9134 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
9135 %{ | |
9136 match(Set dst (AndI dst src)); | |
9137 | |
9138 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
9139 opcode(0x0F, 0xB6); | |
9140 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
9141 ins_pipe(ialu_reg); | |
9142 %} | |
9143 | |
9144 // And Register with Immediate 255 and promote to long | |
9145 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
9146 %{ | |
9147 match(Set dst (ConvI2L (AndI src mask))); | |
9148 | |
9149 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
9150 opcode(0x0F, 0xB6); | |
9151 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
9152 ins_pipe(ialu_reg); | |
9153 %} | |
9154 | |
9155 // And Register with Immediate 65535 | |
9156 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
9157 %{ | |
9158 match(Set dst (AndI dst src)); | |
9159 | |
9160 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
9161 opcode(0x0F, 0xB7); | |
9162 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
9163 ins_pipe(ialu_reg); | |
9164 %} | |
9165 | |
9166 // And Register with Immediate 65535 and promote to long | |
9167 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
9168 %{ | |
9169 match(Set dst (ConvI2L (AndI src mask))); | |
9170 | |
9171 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
9172 opcode(0x0F, 0xB7); | |
9173 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
9174 ins_pipe(ialu_reg); | |
9175 %} | |
9176 | |
9177 // And Register with Immediate | |
9178 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
9179 %{ | |
9180 match(Set dst (AndI dst src)); | |
9181 effect(KILL cr); | |
9182 | |
9183 format %{ "andl $dst, $src\t# int" %} | |
9184 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
9185 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
9186 ins_pipe(ialu_reg); | |
9187 %} | |
9188 | |
9189 // And Register with Memory | |
9190 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
9191 %{ | |
9192 match(Set dst (AndI dst (LoadI src))); | |
9193 effect(KILL cr); | |
9194 | |
9195 ins_cost(125); | |
9196 format %{ "andl $dst, $src\t# int" %} | |
9197 opcode(0x23); | |
9198 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
9199 ins_pipe(ialu_reg_mem); | |
9200 %} | |
9201 | |
9202 // And Memory with Register | |
9203 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
9204 %{ | |
9205 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
9206 effect(KILL cr); | |
9207 | |
9208 ins_cost(150); | |
9209 format %{ "andl $dst, $src\t# int" %} | |
9210 opcode(0x21); /* Opcode 21 /r */ | |
9211 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
9212 ins_pipe(ialu_mem_reg); | |
9213 %} | |
9214 | |
9215 // And Memory with Immediate | |
9216 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
9217 %{ | |
9218 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
9219 effect(KILL cr); | |
9220 | |
9221 ins_cost(125); | |
9222 format %{ "andl $dst, $src\t# int" %} | |
9223 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
9224 ins_encode(REX_mem(dst), OpcSE(src), | |
9225 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9226 ins_pipe(ialu_mem_imm); | |
9227 %} | |
9228 | |
9229 // Or Instructions | |
9230 // Or Register with Register | |
9231 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
9232 %{ | |
9233 match(Set dst (OrI dst src)); | |
9234 effect(KILL cr); | |
9235 | |
9236 format %{ "orl $dst, $src\t# int" %} | |
9237 opcode(0x0B); | |
9238 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
9239 ins_pipe(ialu_reg_reg); | |
9240 %} | |
9241 | |
9242 // Or Register with Immediate | |
9243 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
9244 %{ | |
9245 match(Set dst (OrI dst src)); | |
9246 effect(KILL cr); | |
9247 | |
9248 format %{ "orl $dst, $src\t# int" %} | |
9249 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
9250 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
9251 ins_pipe(ialu_reg); | |
9252 %} | |
9253 | |
9254 // Or Register with Memory | |
9255 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
9256 %{ | |
9257 match(Set dst (OrI dst (LoadI src))); | |
9258 effect(KILL cr); | |
9259 | |
9260 ins_cost(125); | |
9261 format %{ "orl $dst, $src\t# int" %} | |
9262 opcode(0x0B); | |
9263 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
9264 ins_pipe(ialu_reg_mem); | |
9265 %} | |
9266 | |
9267 // Or Memory with Register | |
9268 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
9269 %{ | |
9270 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
9271 effect(KILL cr); | |
9272 | |
9273 ins_cost(150); | |
9274 format %{ "orl $dst, $src\t# int" %} | |
9275 opcode(0x09); /* Opcode 09 /r */ | |
9276 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
9277 ins_pipe(ialu_mem_reg); | |
9278 %} | |
9279 | |
9280 // Or Memory with Immediate | |
9281 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
9282 %{ | |
9283 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
9284 effect(KILL cr); | |
9285 | |
9286 ins_cost(125); | |
9287 format %{ "orl $dst, $src\t# int" %} | |
9288 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
9289 ins_encode(REX_mem(dst), OpcSE(src), | |
9290 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9291 ins_pipe(ialu_mem_imm); | |
9292 %} | |
9293 | |
9294 // Xor Instructions | |
9295 // Xor Register with Register | |
9296 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
9297 %{ | |
9298 match(Set dst (XorI dst src)); | |
9299 effect(KILL cr); | |
9300 | |
9301 format %{ "xorl $dst, $src\t# int" %} | |
9302 opcode(0x33); | |
9303 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
9304 ins_pipe(ialu_reg_reg); | |
9305 %} | |
9306 | |
9307 // Xor Register with Immediate | |
9308 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
9309 %{ | |
9310 match(Set dst (XorI dst src)); | |
9311 effect(KILL cr); | |
9312 | |
9313 format %{ "xorl $dst, $src\t# int" %} | |
9314 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
9315 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
9316 ins_pipe(ialu_reg); | |
9317 %} | |
9318 | |
9319 // Xor Register with Memory | |
9320 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
9321 %{ | |
9322 match(Set dst (XorI dst (LoadI src))); | |
9323 effect(KILL cr); | |
9324 | |
9325 ins_cost(125); | |
9326 format %{ "xorl $dst, $src\t# int" %} | |
9327 opcode(0x33); | |
9328 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
9329 ins_pipe(ialu_reg_mem); | |
9330 %} | |
9331 | |
9332 // Xor Memory with Register | |
9333 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
9334 %{ | |
9335 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
9336 effect(KILL cr); | |
9337 | |
9338 ins_cost(150); | |
9339 format %{ "xorl $dst, $src\t# int" %} | |
9340 opcode(0x31); /* Opcode 31 /r */ | |
9341 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
9342 ins_pipe(ialu_mem_reg); | |
9343 %} | |
9344 | |
9345 // Xor Memory with Immediate | |
9346 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
9347 %{ | |
9348 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
9349 effect(KILL cr); | |
9350 | |
9351 ins_cost(125); | |
9352 format %{ "xorl $dst, $src\t# int" %} | |
9353 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
9354 ins_encode(REX_mem(dst), OpcSE(src), | |
9355 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9356 ins_pipe(ialu_mem_imm); | |
9357 %} | |
9358 | |
9359 | |
9360 // Long Logical Instructions | |
9361 | |
9362 // And Instructions | |
9363 // And Register with Register | |
9364 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
9365 %{ | |
9366 match(Set dst (AndL dst src)); | |
9367 effect(KILL cr); | |
9368 | |
9369 format %{ "andq $dst, $src\t# long" %} | |
9370 opcode(0x23); | |
9371 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
9372 ins_pipe(ialu_reg_reg); | |
9373 %} | |
9374 | |
9375 // And Register with Immediate 255 | |
9376 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
9377 %{ | |
9378 match(Set dst (AndL dst src)); | |
9379 | |
9380 format %{ "movzbq $dst, $src\t# long & 0xFF" %} | |
9381 opcode(0x0F, 0xB6); | |
9382 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
9383 ins_pipe(ialu_reg); | |
9384 %} | |
9385 | |
9386 // And Register with Immediate 65535 | |
9387 instruct andL_rReg_imm65535(rRegI dst, immL_65535 src) | |
9388 %{ | |
9389 match(Set dst (AndL dst src)); | |
9390 | |
9391 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
9392 opcode(0x0F, 0xB7); | |
9393 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
9394 ins_pipe(ialu_reg); | |
9395 %} | |
9396 | |
9397 // And Register with Immediate | |
9398 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
9399 %{ | |
9400 match(Set dst (AndL dst src)); | |
9401 effect(KILL cr); | |
9402 | |
9403 format %{ "andq $dst, $src\t# long" %} | |
9404 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
9405 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
9406 ins_pipe(ialu_reg); | |
9407 %} | |
9408 | |
9409 // And Register with Memory | |
9410 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
9411 %{ | |
9412 match(Set dst (AndL dst (LoadL src))); | |
9413 effect(KILL cr); | |
9414 | |
9415 ins_cost(125); | |
9416 format %{ "andq $dst, $src\t# long" %} | |
9417 opcode(0x23); | |
9418 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
9419 ins_pipe(ialu_reg_mem); | |
9420 %} | |
9421 | |
9422 // And Memory with Register | |
9423 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
9424 %{ | |
9425 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
9426 effect(KILL cr); | |
9427 | |
9428 ins_cost(150); | |
9429 format %{ "andq $dst, $src\t# long" %} | |
9430 opcode(0x21); /* Opcode 21 /r */ | |
9431 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
9432 ins_pipe(ialu_mem_reg); | |
9433 %} | |
9434 | |
9435 // And Memory with Immediate | |
9436 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
9437 %{ | |
9438 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
9439 effect(KILL cr); | |
9440 | |
9441 ins_cost(125); | |
9442 format %{ "andq $dst, $src\t# long" %} | |
9443 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
9444 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
9445 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9446 ins_pipe(ialu_mem_imm); | |
9447 %} | |
9448 | |
9449 // Or Instructions | |
9450 // Or Register with Register | |
9451 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
9452 %{ | |
9453 match(Set dst (OrL dst src)); | |
9454 effect(KILL cr); | |
9455 | |
9456 format %{ "orq $dst, $src\t# long" %} | |
9457 opcode(0x0B); | |
9458 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
9459 ins_pipe(ialu_reg_reg); | |
9460 %} | |
9461 | |
9462 // Or Register with Immediate | |
9463 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
9464 %{ | |
9465 match(Set dst (OrL dst src)); | |
9466 effect(KILL cr); | |
9467 | |
9468 format %{ "orq $dst, $src\t# long" %} | |
9469 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
9470 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
9471 ins_pipe(ialu_reg); | |
9472 %} | |
9473 | |
9474 // Or Register with Memory | |
9475 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
9476 %{ | |
9477 match(Set dst (OrL dst (LoadL src))); | |
9478 effect(KILL cr); | |
9479 | |
9480 ins_cost(125); | |
9481 format %{ "orq $dst, $src\t# long" %} | |
9482 opcode(0x0B); | |
9483 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
9484 ins_pipe(ialu_reg_mem); | |
9485 %} | |
9486 | |
9487 // Or Memory with Register | |
9488 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
9489 %{ | |
9490 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
9491 effect(KILL cr); | |
9492 | |
9493 ins_cost(150); | |
9494 format %{ "orq $dst, $src\t# long" %} | |
9495 opcode(0x09); /* Opcode 09 /r */ | |
9496 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
9497 ins_pipe(ialu_mem_reg); | |
9498 %} | |
9499 | |
9500 // Or Memory with Immediate | |
9501 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
9502 %{ | |
9503 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
9504 effect(KILL cr); | |
9505 | |
9506 ins_cost(125); | |
9507 format %{ "orq $dst, $src\t# long" %} | |
9508 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
9509 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
9510 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9511 ins_pipe(ialu_mem_imm); | |
9512 %} | |
9513 | |
9514 // Xor Instructions | |
9515 // Xor Register with Register | |
9516 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
9517 %{ | |
9518 match(Set dst (XorL dst src)); | |
9519 effect(KILL cr); | |
9520 | |
9521 format %{ "xorq $dst, $src\t# long" %} | |
9522 opcode(0x33); | |
9523 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
9524 ins_pipe(ialu_reg_reg); | |
9525 %} | |
9526 | |
9527 // Xor Register with Immediate | |
9528 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
9529 %{ | |
9530 match(Set dst (XorL dst src)); | |
9531 effect(KILL cr); | |
9532 | |
9533 format %{ "xorq $dst, $src\t# long" %} | |
9534 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
9535 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
9536 ins_pipe(ialu_reg); | |
9537 %} | |
9538 | |
9539 // Xor Register with Memory | |
9540 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
9541 %{ | |
9542 match(Set dst (XorL dst (LoadL src))); | |
9543 effect(KILL cr); | |
9544 | |
9545 ins_cost(125); | |
9546 format %{ "xorq $dst, $src\t# long" %} | |
9547 opcode(0x33); | |
9548 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
9549 ins_pipe(ialu_reg_mem); | |
9550 %} | |
9551 | |
9552 // Xor Memory with Register | |
9553 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
9554 %{ | |
9555 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
9556 effect(KILL cr); | |
9557 | |
9558 ins_cost(150); | |
9559 format %{ "xorq $dst, $src\t# long" %} | |
9560 opcode(0x31); /* Opcode 31 /r */ | |
9561 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
9562 ins_pipe(ialu_mem_reg); | |
9563 %} | |
9564 | |
9565 // Xor Memory with Immediate | |
9566 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
9567 %{ | |
9568 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
9569 effect(KILL cr); | |
9570 | |
9571 ins_cost(125); | |
9572 format %{ "xorq $dst, $src\t# long" %} | |
9573 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
9574 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
9575 RM_opc_mem(secondary, dst), Con8or32(src)); | |
9576 ins_pipe(ialu_mem_imm); | |
9577 %} | |
9578 | |
9579 // Convert Int to Boolean | |
9580 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
9581 %{ | |
9582 match(Set dst (Conv2B src)); | |
9583 effect(KILL cr); | |
9584 | |
9585 format %{ "testl $src, $src\t# ci2b\n\t" | |
9586 "setnz $dst\n\t" | |
9587 "movzbl $dst, $dst" %} | |
9588 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
9589 setNZ_reg(dst), | |
9590 REX_reg_breg(dst, dst), // movzbl | |
9591 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
9592 ins_pipe(pipe_slow); // XXX | |
9593 %} | |
9594 | |
9595 // Convert Pointer to Boolean | |
9596 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
9597 %{ | |
9598 match(Set dst (Conv2B src)); | |
9599 effect(KILL cr); | |
9600 | |
9601 format %{ "testq $src, $src\t# cp2b\n\t" | |
9602 "setnz $dst\n\t" | |
9603 "movzbl $dst, $dst" %} | |
9604 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
9605 setNZ_reg(dst), | |
9606 REX_reg_breg(dst, dst), // movzbl | |
9607 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
9608 ins_pipe(pipe_slow); // XXX | |
9609 %} | |
9610 | |
9611 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
9612 %{ | |
9613 match(Set dst (CmpLTMask p q)); | |
9614 effect(KILL cr); | |
9615 | |
9616 ins_cost(400); // XXX | |
9617 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
9618 "setlt $dst\n\t" | |
9619 "movzbl $dst, $dst\n\t" | |
9620 "negl $dst" %} | |
9621 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
9622 setLT_reg(dst), | |
9623 REX_reg_breg(dst, dst), // movzbl | |
9624 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
9625 neg_reg(dst)); | |
9626 ins_pipe(pipe_slow); | |
9627 %} | |
9628 | |
9629 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
9630 %{ | |
9631 match(Set dst (CmpLTMask dst zero)); | |
9632 effect(KILL cr); | |
9633 | |
9634 ins_cost(100); // XXX | |
9635 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
9636 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
9637 ins_encode(reg_opc_imm(dst, 0x1F)); | |
9638 ins_pipe(ialu_reg); | |
9639 %} | |
9640 | |
9641 | |
9642 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, | |
9643 rRegI tmp, | |
9644 rFlagsReg cr) | |
9645 %{ | |
9646 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
9647 effect(TEMP tmp, KILL cr); | |
9648 | |
9649 ins_cost(400); // XXX | |
9650 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
9651 "sbbl $tmp, $tmp\n\t" | |
9652 "andl $tmp, $y\n\t" | |
9653 "addl $p, $tmp" %} | |
9654 ins_encode(enc_cmpLTP(p, q, y, tmp)); | |
9655 ins_pipe(pipe_cmplt); | |
9656 %} | |
9657 | |
9658 /* If I enable this, I encourage spilling in the inner loop of compress. | |
9659 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr ) | |
9660 %{ | |
9661 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
9662 effect( TEMP tmp, KILL cr ); | |
9663 ins_cost(400); | |
9664 | |
9665 format %{ "SUB $p,$q\n\t" | |
9666 "SBB RCX,RCX\n\t" | |
9667 "AND RCX,$y\n\t" | |
9668 "ADD $p,RCX" %} | |
9669 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
9670 %} | |
9671 */ | |
9672 | |
9673 //---------- FP Instructions------------------------------------------------ | |
9674 | |
9675 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
9676 %{ | |
9677 match(Set cr (CmpF src1 src2)); | |
9678 | |
9679 ins_cost(145); | |
9680 format %{ "ucomiss $src1, $src2\n\t" | |
9681 "jnp,s exit\n\t" | |
9682 "pushfq\t# saw NaN, set CF\n\t" | |
9683 "andq [rsp], #0xffffff2b\n\t" | |
9684 "popfq\n" | |
9685 "exit: nop\t# avoid branch to branch" %} | |
9686 opcode(0x0F, 0x2E); | |
9687 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
9688 cmpfp_fixup); | |
9689 ins_pipe(pipe_slow); | |
9690 %} | |
9691 | |
9692 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) | |
9693 %{ | |
9694 match(Set cr (CmpF src1 (LoadF src2))); | |
9695 | |
9696 ins_cost(145); | |
9697 format %{ "ucomiss $src1, $src2\n\t" | |
9698 "jnp,s exit\n\t" | |
9699 "pushfq\t# saw NaN, set CF\n\t" | |
9700 "andq [rsp], #0xffffff2b\n\t" | |
9701 "popfq\n" | |
9702 "exit: nop\t# avoid branch to branch" %} | |
9703 opcode(0x0F, 0x2E); | |
9704 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
9705 cmpfp_fixup); | |
9706 ins_pipe(pipe_slow); | |
9707 %} | |
9708 | |
9709 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2) | |
9710 %{ | |
9711 match(Set cr (CmpF src1 src2)); | |
9712 | |
9713 ins_cost(145); | |
9714 format %{ "ucomiss $src1, $src2\n\t" | |
9715 "jnp,s exit\n\t" | |
9716 "pushfq\t# saw NaN, set CF\n\t" | |
9717 "andq [rsp], #0xffffff2b\n\t" | |
9718 "popfq\n" | |
9719 "exit: nop\t# avoid branch to branch" %} | |
9720 opcode(0x0F, 0x2E); | |
9721 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
9722 cmpfp_fixup); | |
9723 ins_pipe(pipe_slow); | |
9724 %} | |
9725 | |
9726 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) | |
9727 %{ | |
9728 match(Set cr (CmpD src1 src2)); | |
9729 | |
9730 ins_cost(145); | |
9731 format %{ "ucomisd $src1, $src2\n\t" | |
9732 "jnp,s exit\n\t" | |
9733 "pushfq\t# saw NaN, set CF\n\t" | |
9734 "andq [rsp], #0xffffff2b\n\t" | |
9735 "popfq\n" | |
9736 "exit: nop\t# avoid branch to branch" %} | |
9737 opcode(0x66, 0x0F, 0x2E); | |
9738 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
9739 cmpfp_fixup); | |
9740 ins_pipe(pipe_slow); | |
9741 %} | |
9742 | |
9743 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) | |
9744 %{ | |
9745 match(Set cr (CmpD src1 (LoadD src2))); | |
9746 | |
9747 ins_cost(145); | |
9748 format %{ "ucomisd $src1, $src2\n\t" | |
9749 "jnp,s exit\n\t" | |
9750 "pushfq\t# saw NaN, set CF\n\t" | |
9751 "andq [rsp], #0xffffff2b\n\t" | |
9752 "popfq\n" | |
9753 "exit: nop\t# avoid branch to branch" %} | |
9754 opcode(0x66, 0x0F, 0x2E); | |
9755 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
9756 cmpfp_fixup); | |
9757 ins_pipe(pipe_slow); | |
9758 %} | |
9759 | |
9760 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2) | |
9761 %{ | |
9762 match(Set cr (CmpD src1 src2)); | |
9763 | |
9764 ins_cost(145); | |
9765 format %{ "ucomisd $src1, [$src2]\n\t" | |
9766 "jnp,s exit\n\t" | |
9767 "pushfq\t# saw NaN, set CF\n\t" | |
9768 "andq [rsp], #0xffffff2b\n\t" | |
9769 "popfq\n" | |
9770 "exit: nop\t# avoid branch to branch" %} | |
9771 opcode(0x66, 0x0F, 0x2E); | |
9772 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
9773 cmpfp_fixup); | |
9774 ins_pipe(pipe_slow); | |
9775 %} | |
9776 | |
9777 // Compare into -1,0,1 | |
9778 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
9779 %{ | |
9780 match(Set dst (CmpF3 src1 src2)); | |
9781 effect(KILL cr); | |
9782 | |
9783 ins_cost(275); | |
9784 format %{ "ucomiss $src1, $src2\n\t" | |
9785 "movl $dst, #-1\n\t" | |
9786 "jp,s done\n\t" | |
9787 "jb,s done\n\t" | |
9788 "setne $dst\n\t" | |
9789 "movzbl $dst, $dst\n" | |
9790 "done:" %} | |
9791 | |
9792 opcode(0x0F, 0x2E); | |
9793 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
9794 cmpfp3(dst)); | |
9795 ins_pipe(pipe_slow); | |
9796 %} | |
9797 | |
9798 // Compare into -1,0,1 | |
9799 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
9800 %{ | |
9801 match(Set dst (CmpF3 src1 (LoadF src2))); | |
9802 effect(KILL cr); | |
9803 | |
9804 ins_cost(275); | |
9805 format %{ "ucomiss $src1, $src2\n\t" | |
9806 "movl $dst, #-1\n\t" | |
9807 "jp,s done\n\t" | |
9808 "jb,s done\n\t" | |
9809 "setne $dst\n\t" | |
9810 "movzbl $dst, $dst\n" | |
9811 "done:" %} | |
9812 | |
9813 opcode(0x0F, 0x2E); | |
9814 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
9815 cmpfp3(dst)); | |
9816 ins_pipe(pipe_slow); | |
9817 %} | |
9818 | |
9819 // Compare into -1,0,1 | |
9820 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr) | |
9821 %{ | |
9822 match(Set dst (CmpF3 src1 src2)); | |
9823 effect(KILL cr); | |
9824 | |
9825 ins_cost(275); | |
9826 format %{ "ucomiss $src1, [$src2]\n\t" | |
9827 "movl $dst, #-1\n\t" | |
9828 "jp,s done\n\t" | |
9829 "jb,s done\n\t" | |
9830 "setne $dst\n\t" | |
9831 "movzbl $dst, $dst\n" | |
9832 "done:" %} | |
9833 | |
9834 opcode(0x0F, 0x2E); | |
9835 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
9836 cmpfp3(dst)); | |
9837 ins_pipe(pipe_slow); | |
9838 %} | |
9839 | |
9840 // Compare into -1,0,1 | |
9841 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
9842 %{ | |
9843 match(Set dst (CmpD3 src1 src2)); | |
9844 effect(KILL cr); | |
9845 | |
9846 ins_cost(275); | |
9847 format %{ "ucomisd $src1, $src2\n\t" | |
9848 "movl $dst, #-1\n\t" | |
9849 "jp,s done\n\t" | |
9850 "jb,s done\n\t" | |
9851 "setne $dst\n\t" | |
9852 "movzbl $dst, $dst\n" | |
9853 "done:" %} | |
9854 | |
9855 opcode(0x66, 0x0F, 0x2E); | |
9856 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
9857 cmpfp3(dst)); | |
9858 ins_pipe(pipe_slow); | |
9859 %} | |
9860 | |
9861 // Compare into -1,0,1 | |
9862 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
9863 %{ | |
9864 match(Set dst (CmpD3 src1 (LoadD src2))); | |
9865 effect(KILL cr); | |
9866 | |
9867 ins_cost(275); | |
9868 format %{ "ucomisd $src1, $src2\n\t" | |
9869 "movl $dst, #-1\n\t" | |
9870 "jp,s done\n\t" | |
9871 "jb,s done\n\t" | |
9872 "setne $dst\n\t" | |
9873 "movzbl $dst, $dst\n" | |
9874 "done:" %} | |
9875 | |
9876 opcode(0x66, 0x0F, 0x2E); | |
9877 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
9878 cmpfp3(dst)); | |
9879 ins_pipe(pipe_slow); | |
9880 %} | |
9881 | |
9882 // Compare into -1,0,1 | |
9883 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr) | |
9884 %{ | |
9885 match(Set dst (CmpD3 src1 src2)); | |
9886 effect(KILL cr); | |
9887 | |
9888 ins_cost(275); | |
9889 format %{ "ucomisd $src1, [$src2]\n\t" | |
9890 "movl $dst, #-1\n\t" | |
9891 "jp,s done\n\t" | |
9892 "jb,s done\n\t" | |
9893 "setne $dst\n\t" | |
9894 "movzbl $dst, $dst\n" | |
9895 "done:" %} | |
9896 | |
9897 opcode(0x66, 0x0F, 0x2E); | |
9898 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
9899 cmpfp3(dst)); | |
9900 ins_pipe(pipe_slow); | |
9901 %} | |
9902 | |
9903 instruct addF_reg(regF dst, regF src) | |
9904 %{ | |
9905 match(Set dst (AddF dst src)); | |
9906 | |
9907 format %{ "addss $dst, $src" %} | |
9908 ins_cost(150); // XXX | |
9909 opcode(0xF3, 0x0F, 0x58); | |
9910 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
9911 ins_pipe(pipe_slow); | |
9912 %} | |
9913 | |
9914 instruct addF_mem(regF dst, memory src) | |
9915 %{ | |
9916 match(Set dst (AddF dst (LoadF src))); | |
9917 | |
9918 format %{ "addss $dst, $src" %} | |
9919 ins_cost(150); // XXX | |
9920 opcode(0xF3, 0x0F, 0x58); | |
9921 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
9922 ins_pipe(pipe_slow); | |
9923 %} | |
9924 | |
9925 instruct addF_imm(regF dst, immF src) | |
9926 %{ | |
9927 match(Set dst (AddF dst src)); | |
9928 | |
9929 format %{ "addss $dst, [$src]" %} | |
9930 ins_cost(150); // XXX | |
9931 opcode(0xF3, 0x0F, 0x58); | |
9932 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
9933 ins_pipe(pipe_slow); | |
9934 %} | |
9935 | |
9936 instruct addD_reg(regD dst, regD src) | |
9937 %{ | |
9938 match(Set dst (AddD dst src)); | |
9939 | |
9940 format %{ "addsd $dst, $src" %} | |
9941 ins_cost(150); // XXX | |
9942 opcode(0xF2, 0x0F, 0x58); | |
9943 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
9944 ins_pipe(pipe_slow); | |
9945 %} | |
9946 | |
9947 instruct addD_mem(regD dst, memory src) | |
9948 %{ | |
9949 match(Set dst (AddD dst (LoadD src))); | |
9950 | |
9951 format %{ "addsd $dst, $src" %} | |
9952 ins_cost(150); // XXX | |
9953 opcode(0xF2, 0x0F, 0x58); | |
9954 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
9955 ins_pipe(pipe_slow); | |
9956 %} | |
9957 | |
9958 instruct addD_imm(regD dst, immD src) | |
9959 %{ | |
9960 match(Set dst (AddD dst src)); | |
9961 | |
9962 format %{ "addsd $dst, [$src]" %} | |
9963 ins_cost(150); // XXX | |
9964 opcode(0xF2, 0x0F, 0x58); | |
9965 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
9966 ins_pipe(pipe_slow); | |
9967 %} | |
9968 | |
9969 instruct subF_reg(regF dst, regF src) | |
9970 %{ | |
9971 match(Set dst (SubF dst src)); | |
9972 | |
9973 format %{ "subss $dst, $src" %} | |
9974 ins_cost(150); // XXX | |
9975 opcode(0xF3, 0x0F, 0x5C); | |
9976 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
9977 ins_pipe(pipe_slow); | |
9978 %} | |
9979 | |
9980 instruct subF_mem(regF dst, memory src) | |
9981 %{ | |
9982 match(Set dst (SubF dst (LoadF src))); | |
9983 | |
9984 format %{ "subss $dst, $src" %} | |
9985 ins_cost(150); // XXX | |
9986 opcode(0xF3, 0x0F, 0x5C); | |
9987 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
9988 ins_pipe(pipe_slow); | |
9989 %} | |
9990 | |
9991 instruct subF_imm(regF dst, immF src) | |
9992 %{ | |
9993 match(Set dst (SubF dst src)); | |
9994 | |
9995 format %{ "subss $dst, [$src]" %} | |
9996 ins_cost(150); // XXX | |
9997 opcode(0xF3, 0x0F, 0x5C); | |
9998 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
9999 ins_pipe(pipe_slow); | |
10000 %} | |
10001 | |
10002 instruct subD_reg(regD dst, regD src) | |
10003 %{ | |
10004 match(Set dst (SubD dst src)); | |
10005 | |
10006 format %{ "subsd $dst, $src" %} | |
10007 ins_cost(150); // XXX | |
10008 opcode(0xF2, 0x0F, 0x5C); | |
10009 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10010 ins_pipe(pipe_slow); | |
10011 %} | |
10012 | |
10013 instruct subD_mem(regD dst, memory src) | |
10014 %{ | |
10015 match(Set dst (SubD dst (LoadD src))); | |
10016 | |
10017 format %{ "subsd $dst, $src" %} | |
10018 ins_cost(150); // XXX | |
10019 opcode(0xF2, 0x0F, 0x5C); | |
10020 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10021 ins_pipe(pipe_slow); | |
10022 %} | |
10023 | |
10024 instruct subD_imm(regD dst, immD src) | |
10025 %{ | |
10026 match(Set dst (SubD dst src)); | |
10027 | |
10028 format %{ "subsd $dst, [$src]" %} | |
10029 ins_cost(150); // XXX | |
10030 opcode(0xF2, 0x0F, 0x5C); | |
10031 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
10032 ins_pipe(pipe_slow); | |
10033 %} | |
10034 | |
10035 instruct mulF_reg(regF dst, regF src) | |
10036 %{ | |
10037 match(Set dst (MulF dst src)); | |
10038 | |
10039 format %{ "mulss $dst, $src" %} | |
10040 ins_cost(150); // XXX | |
10041 opcode(0xF3, 0x0F, 0x59); | |
10042 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10043 ins_pipe(pipe_slow); | |
10044 %} | |
10045 | |
10046 instruct mulF_mem(regF dst, memory src) | |
10047 %{ | |
10048 match(Set dst (MulF dst (LoadF src))); | |
10049 | |
10050 format %{ "mulss $dst, $src" %} | |
10051 ins_cost(150); // XXX | |
10052 opcode(0xF3, 0x0F, 0x59); | |
10053 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10054 ins_pipe(pipe_slow); | |
10055 %} | |
10056 | |
10057 instruct mulF_imm(regF dst, immF src) | |
10058 %{ | |
10059 match(Set dst (MulF dst src)); | |
10060 | |
10061 format %{ "mulss $dst, [$src]" %} | |
10062 ins_cost(150); // XXX | |
10063 opcode(0xF3, 0x0F, 0x59); | |
10064 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
10065 ins_pipe(pipe_slow); | |
10066 %} | |
10067 | |
10068 instruct mulD_reg(regD dst, regD src) | |
10069 %{ | |
10070 match(Set dst (MulD dst src)); | |
10071 | |
10072 format %{ "mulsd $dst, $src" %} | |
10073 ins_cost(150); // XXX | |
10074 opcode(0xF2, 0x0F, 0x59); | |
10075 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10076 ins_pipe(pipe_slow); | |
10077 %} | |
10078 | |
10079 instruct mulD_mem(regD dst, memory src) | |
10080 %{ | |
10081 match(Set dst (MulD dst (LoadD src))); | |
10082 | |
10083 format %{ "mulsd $dst, $src" %} | |
10084 ins_cost(150); // XXX | |
10085 opcode(0xF2, 0x0F, 0x59); | |
10086 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10087 ins_pipe(pipe_slow); | |
10088 %} | |
10089 | |
10090 instruct mulD_imm(regD dst, immD src) | |
10091 %{ | |
10092 match(Set dst (MulD dst src)); | |
10093 | |
10094 format %{ "mulsd $dst, [$src]" %} | |
10095 ins_cost(150); // XXX | |
10096 opcode(0xF2, 0x0F, 0x59); | |
10097 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
10098 ins_pipe(pipe_slow); | |
10099 %} | |
10100 | |
10101 instruct divF_reg(regF dst, regF src) | |
10102 %{ | |
10103 match(Set dst (DivF dst src)); | |
10104 | |
10105 format %{ "divss $dst, $src" %} | |
10106 ins_cost(150); // XXX | |
10107 opcode(0xF3, 0x0F, 0x5E); | |
10108 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10109 ins_pipe(pipe_slow); | |
10110 %} | |
10111 | |
10112 instruct divF_mem(regF dst, memory src) | |
10113 %{ | |
10114 match(Set dst (DivF dst (LoadF src))); | |
10115 | |
10116 format %{ "divss $dst, $src" %} | |
10117 ins_cost(150); // XXX | |
10118 opcode(0xF3, 0x0F, 0x5E); | |
10119 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10120 ins_pipe(pipe_slow); | |
10121 %} | |
10122 | |
10123 instruct divF_imm(regF dst, immF src) | |
10124 %{ | |
10125 match(Set dst (DivF dst src)); | |
10126 | |
10127 format %{ "divss $dst, [$src]" %} | |
10128 ins_cost(150); // XXX | |
10129 opcode(0xF3, 0x0F, 0x5E); | |
10130 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
10131 ins_pipe(pipe_slow); | |
10132 %} | |
10133 | |
10134 instruct divD_reg(regD dst, regD src) | |
10135 %{ | |
10136 match(Set dst (DivD dst src)); | |
10137 | |
10138 format %{ "divsd $dst, $src" %} | |
10139 ins_cost(150); // XXX | |
10140 opcode(0xF2, 0x0F, 0x5E); | |
10141 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10142 ins_pipe(pipe_slow); | |
10143 %} | |
10144 | |
10145 instruct divD_mem(regD dst, memory src) | |
10146 %{ | |
10147 match(Set dst (DivD dst (LoadD src))); | |
10148 | |
10149 format %{ "divsd $dst, $src" %} | |
10150 ins_cost(150); // XXX | |
10151 opcode(0xF2, 0x0F, 0x5E); | |
10152 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10153 ins_pipe(pipe_slow); | |
10154 %} | |
10155 | |
10156 instruct divD_imm(regD dst, immD src) | |
10157 %{ | |
10158 match(Set dst (DivD dst src)); | |
10159 | |
10160 format %{ "divsd $dst, [$src]" %} | |
10161 ins_cost(150); // XXX | |
10162 opcode(0xF2, 0x0F, 0x5E); | |
10163 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
10164 ins_pipe(pipe_slow); | |
10165 %} | |
10166 | |
10167 instruct sqrtF_reg(regF dst, regF src) | |
10168 %{ | |
10169 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
10170 | |
10171 format %{ "sqrtss $dst, $src" %} | |
10172 ins_cost(150); // XXX | |
10173 opcode(0xF3, 0x0F, 0x51); | |
10174 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10175 ins_pipe(pipe_slow); | |
10176 %} | |
10177 | |
10178 instruct sqrtF_mem(regF dst, memory src) | |
10179 %{ | |
10180 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
10181 | |
10182 format %{ "sqrtss $dst, $src" %} | |
10183 ins_cost(150); // XXX | |
10184 opcode(0xF3, 0x0F, 0x51); | |
10185 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10186 ins_pipe(pipe_slow); | |
10187 %} | |
10188 | |
10189 instruct sqrtF_imm(regF dst, immF src) | |
10190 %{ | |
10191 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
10192 | |
10193 format %{ "sqrtss $dst, [$src]" %} | |
10194 ins_cost(150); // XXX | |
10195 opcode(0xF3, 0x0F, 0x51); | |
10196 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
10197 ins_pipe(pipe_slow); | |
10198 %} | |
10199 | |
10200 instruct sqrtD_reg(regD dst, regD src) | |
10201 %{ | |
10202 match(Set dst (SqrtD src)); | |
10203 | |
10204 format %{ "sqrtsd $dst, $src" %} | |
10205 ins_cost(150); // XXX | |
10206 opcode(0xF2, 0x0F, 0x51); | |
10207 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10208 ins_pipe(pipe_slow); | |
10209 %} | |
10210 | |
10211 instruct sqrtD_mem(regD dst, memory src) | |
10212 %{ | |
10213 match(Set dst (SqrtD (LoadD src))); | |
10214 | |
10215 format %{ "sqrtsd $dst, $src" %} | |
10216 ins_cost(150); // XXX | |
10217 opcode(0xF2, 0x0F, 0x51); | |
10218 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10219 ins_pipe(pipe_slow); | |
10220 %} | |
10221 | |
10222 instruct sqrtD_imm(regD dst, immD src) | |
10223 %{ | |
10224 match(Set dst (SqrtD src)); | |
10225 | |
10226 format %{ "sqrtsd $dst, [$src]" %} | |
10227 ins_cost(150); // XXX | |
10228 opcode(0xF2, 0x0F, 0x51); | |
10229 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
10230 ins_pipe(pipe_slow); | |
10231 %} | |
10232 | |
10233 instruct absF_reg(regF dst) | |
10234 %{ | |
10235 match(Set dst (AbsF dst)); | |
10236 | |
10237 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
10238 ins_encode(absF_encoding(dst)); | |
10239 ins_pipe(pipe_slow); | |
10240 %} | |
10241 | |
10242 instruct absD_reg(regD dst) | |
10243 %{ | |
10244 match(Set dst (AbsD dst)); | |
10245 | |
10246 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
10247 "# abs double by sign masking" %} | |
10248 ins_encode(absD_encoding(dst)); | |
10249 ins_pipe(pipe_slow); | |
10250 %} | |
10251 | |
10252 instruct negF_reg(regF dst) | |
10253 %{ | |
10254 match(Set dst (NegF dst)); | |
10255 | |
10256 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
10257 ins_encode(negF_encoding(dst)); | |
10258 ins_pipe(pipe_slow); | |
10259 %} | |
10260 | |
10261 instruct negD_reg(regD dst) | |
10262 %{ | |
10263 match(Set dst (NegD dst)); | |
10264 | |
10265 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
10266 "# neg double by sign flipping" %} | |
10267 ins_encode(negD_encoding(dst)); | |
10268 ins_pipe(pipe_slow); | |
10269 %} | |
10270 | |
10271 // -----------Trig and Trancendental Instructions------------------------------ | |
10272 instruct cosD_reg(regD dst) %{ | |
10273 match(Set dst (CosD dst)); | |
10274 | |
10275 format %{ "dcos $dst\n\t" %} | |
10276 opcode(0xD9, 0xFF); | |
10277 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
10278 ins_pipe( pipe_slow ); | |
10279 %} | |
10280 | |
10281 instruct sinD_reg(regD dst) %{ | |
10282 match(Set dst (SinD dst)); | |
10283 | |
10284 format %{ "dsin $dst\n\t" %} | |
10285 opcode(0xD9, 0xFE); | |
10286 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
10287 ins_pipe( pipe_slow ); | |
10288 %} | |
10289 | |
10290 instruct tanD_reg(regD dst) %{ | |
10291 match(Set dst (TanD dst)); | |
10292 | |
10293 format %{ "dtan $dst\n\t" %} | |
10294 ins_encode( Push_SrcXD(dst), | |
10295 Opcode(0xD9), Opcode(0xF2), //fptan | |
10296 Opcode(0xDD), Opcode(0xD8), //fstp st | |
10297 Push_ResultXD(dst) ); | |
10298 ins_pipe( pipe_slow ); | |
10299 %} | |
10300 | |
10301 instruct log10D_reg(regD dst) %{ | |
10302 // The source and result Double operands in XMM registers | |
10303 match(Set dst (Log10D dst)); | |
10304 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
10305 // fyl2x ; compute log_10(2) * log_2(x) | |
10306 format %{ "fldlg2\t\t\t#Log10\n\t" | |
10307 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
10308 %} | |
10309 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
10310 Push_SrcXD(dst), | |
10311 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
10312 Push_ResultXD(dst)); | |
10313 | |
10314 ins_pipe( pipe_slow ); | |
10315 %} | |
10316 | |
10317 instruct logD_reg(regD dst) %{ | |
10318 // The source and result Double operands in XMM registers | |
10319 match(Set dst (LogD dst)); | |
10320 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
10321 // fyl2x ; compute log_e(2) * log_2(x) | |
10322 format %{ "fldln2\t\t\t#Log_e\n\t" | |
10323 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
10324 %} | |
10325 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
10326 Push_SrcXD(dst), | |
10327 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
10328 Push_ResultXD(dst)); | |
10329 ins_pipe( pipe_slow ); | |
10330 %} | |
10331 | |
10332 | |
10333 | |
10334 //----------Arithmetic Conversion Instructions--------------------------------- | |
10335 | |
10336 instruct roundFloat_nop(regF dst) | |
10337 %{ | |
10338 match(Set dst (RoundFloat dst)); | |
10339 | |
10340 ins_cost(0); | |
10341 ins_encode(); | |
10342 ins_pipe(empty); | |
10343 %} | |
10344 | |
10345 instruct roundDouble_nop(regD dst) | |
10346 %{ | |
10347 match(Set dst (RoundDouble dst)); | |
10348 | |
10349 ins_cost(0); | |
10350 ins_encode(); | |
10351 ins_pipe(empty); | |
10352 %} | |
10353 | |
10354 instruct convF2D_reg_reg(regD dst, regF src) | |
10355 %{ | |
10356 match(Set dst (ConvF2D src)); | |
10357 | |
10358 format %{ "cvtss2sd $dst, $src" %} | |
10359 opcode(0xF3, 0x0F, 0x5A); | |
10360 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10361 ins_pipe(pipe_slow); // XXX | |
10362 %} | |
10363 | |
10364 instruct convF2D_reg_mem(regD dst, memory src) | |
10365 %{ | |
10366 match(Set dst (ConvF2D (LoadF src))); | |
10367 | |
10368 format %{ "cvtss2sd $dst, $src" %} | |
10369 opcode(0xF3, 0x0F, 0x5A); | |
10370 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10371 ins_pipe(pipe_slow); // XXX | |
10372 %} | |
10373 | |
10374 instruct convD2F_reg_reg(regF dst, regD src) | |
10375 %{ | |
10376 match(Set dst (ConvD2F src)); | |
10377 | |
10378 format %{ "cvtsd2ss $dst, $src" %} | |
10379 opcode(0xF2, 0x0F, 0x5A); | |
10380 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10381 ins_pipe(pipe_slow); // XXX | |
10382 %} | |
10383 | |
10384 instruct convD2F_reg_mem(regF dst, memory src) | |
10385 %{ | |
10386 match(Set dst (ConvD2F (LoadD src))); | |
10387 | |
10388 format %{ "cvtsd2ss $dst, $src" %} | |
10389 opcode(0xF2, 0x0F, 0x5A); | |
10390 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10391 ins_pipe(pipe_slow); // XXX | |
10392 %} | |
10393 | |
10394 // XXX do mem variants | |
10395 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
10396 %{ | |
10397 match(Set dst (ConvF2I src)); | |
10398 effect(KILL cr); | |
10399 | |
10400 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
10401 "cmpl $dst, #0x80000000\n\t" | |
10402 "jne,s done\n\t" | |
10403 "subq rsp, #8\n\t" | |
10404 "movss [rsp], $src\n\t" | |
10405 "call f2i_fixup\n\t" | |
10406 "popq $dst\n" | |
10407 "done: "%} | |
10408 opcode(0xF3, 0x0F, 0x2C); | |
10409 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
10410 f2i_fixup(dst, src)); | |
10411 ins_pipe(pipe_slow); | |
10412 %} | |
10413 | |
10414 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
10415 %{ | |
10416 match(Set dst (ConvF2L src)); | |
10417 effect(KILL cr); | |
10418 | |
10419 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
10420 "cmpq $dst, [0x8000000000000000]\n\t" | |
10421 "jne,s done\n\t" | |
10422 "subq rsp, #8\n\t" | |
10423 "movss [rsp], $src\n\t" | |
10424 "call f2l_fixup\n\t" | |
10425 "popq $dst\n" | |
10426 "done: "%} | |
10427 opcode(0xF3, 0x0F, 0x2C); | |
10428 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
10429 f2l_fixup(dst, src)); | |
10430 ins_pipe(pipe_slow); | |
10431 %} | |
10432 | |
10433 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
10434 %{ | |
10435 match(Set dst (ConvD2I src)); | |
10436 effect(KILL cr); | |
10437 | |
10438 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
10439 "cmpl $dst, #0x80000000\n\t" | |
10440 "jne,s done\n\t" | |
10441 "subq rsp, #8\n\t" | |
10442 "movsd [rsp], $src\n\t" | |
10443 "call d2i_fixup\n\t" | |
10444 "popq $dst\n" | |
10445 "done: "%} | |
10446 opcode(0xF2, 0x0F, 0x2C); | |
10447 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
10448 d2i_fixup(dst, src)); | |
10449 ins_pipe(pipe_slow); | |
10450 %} | |
10451 | |
10452 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
10453 %{ | |
10454 match(Set dst (ConvD2L src)); | |
10455 effect(KILL cr); | |
10456 | |
10457 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
10458 "cmpq $dst, [0x8000000000000000]\n\t" | |
10459 "jne,s done\n\t" | |
10460 "subq rsp, #8\n\t" | |
10461 "movsd [rsp], $src\n\t" | |
10462 "call d2l_fixup\n\t" | |
10463 "popq $dst\n" | |
10464 "done: "%} | |
10465 opcode(0xF2, 0x0F, 0x2C); | |
10466 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
10467 d2l_fixup(dst, src)); | |
10468 ins_pipe(pipe_slow); | |
10469 %} | |
10470 | |
10471 instruct convI2F_reg_reg(regF dst, rRegI src) | |
10472 %{ | |
71 | 10473 predicate(!UseXmmI2F); |
0 | 10474 match(Set dst (ConvI2F src)); |
10475 | |
10476 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
10477 opcode(0xF3, 0x0F, 0x2A); | |
10478 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10479 ins_pipe(pipe_slow); // XXX | |
10480 %} | |
10481 | |
10482 instruct convI2F_reg_mem(regF dst, memory src) | |
10483 %{ | |
10484 match(Set dst (ConvI2F (LoadI src))); | |
10485 | |
10486 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
10487 opcode(0xF3, 0x0F, 0x2A); | |
10488 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10489 ins_pipe(pipe_slow); // XXX | |
10490 %} | |
10491 | |
10492 instruct convI2D_reg_reg(regD dst, rRegI src) | |
10493 %{ | |
71 | 10494 predicate(!UseXmmI2D); |
0 | 10495 match(Set dst (ConvI2D src)); |
10496 | |
10497 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
10498 opcode(0xF2, 0x0F, 0x2A); | |
10499 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10500 ins_pipe(pipe_slow); // XXX | |
10501 %} | |
10502 | |
10503 instruct convI2D_reg_mem(regD dst, memory src) | |
10504 %{ | |
10505 match(Set dst (ConvI2D (LoadI src))); | |
10506 | |
10507 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
10508 opcode(0xF2, 0x0F, 0x2A); | |
10509 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10510 ins_pipe(pipe_slow); // XXX | |
10511 %} | |
10512 | |
71 | 10513 instruct convXI2F_reg(regF dst, rRegI src) |
10514 %{ | |
10515 predicate(UseXmmI2F); | |
10516 match(Set dst (ConvI2F src)); | |
10517 | |
10518 format %{ "movdl $dst, $src\n\t" | |
10519 "cvtdq2psl $dst, $dst\t# i2f" %} | |
10520 ins_encode %{ | |
10521 __ movdl($dst$$XMMRegister, $src$$Register); | |
10522 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
10523 %} | |
10524 ins_pipe(pipe_slow); // XXX | |
10525 %} | |
10526 | |
10527 instruct convXI2D_reg(regD dst, rRegI src) | |
10528 %{ | |
10529 predicate(UseXmmI2D); | |
10530 match(Set dst (ConvI2D src)); | |
10531 | |
10532 format %{ "movdl $dst, $src\n\t" | |
10533 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
10534 ins_encode %{ | |
10535 __ movdl($dst$$XMMRegister, $src$$Register); | |
10536 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
10537 %} | |
10538 ins_pipe(pipe_slow); // XXX | |
10539 %} | |
10540 | |
0 | 10541 instruct convL2F_reg_reg(regF dst, rRegL src) |
10542 %{ | |
10543 match(Set dst (ConvL2F src)); | |
10544 | |
10545 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
10546 opcode(0xF3, 0x0F, 0x2A); | |
10547 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10548 ins_pipe(pipe_slow); // XXX | |
10549 %} | |
10550 | |
10551 instruct convL2F_reg_mem(regF dst, memory src) | |
10552 %{ | |
10553 match(Set dst (ConvL2F (LoadL src))); | |
10554 | |
10555 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
10556 opcode(0xF3, 0x0F, 0x2A); | |
10557 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10558 ins_pipe(pipe_slow); // XXX | |
10559 %} | |
10560 | |
10561 instruct convL2D_reg_reg(regD dst, rRegL src) | |
10562 %{ | |
10563 match(Set dst (ConvL2D src)); | |
10564 | |
10565 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
10566 opcode(0xF2, 0x0F, 0x2A); | |
10567 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
10568 ins_pipe(pipe_slow); // XXX | |
10569 %} | |
10570 | |
10571 instruct convL2D_reg_mem(regD dst, memory src) | |
10572 %{ | |
10573 match(Set dst (ConvL2D (LoadL src))); | |
10574 | |
10575 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
10576 opcode(0xF2, 0x0F, 0x2A); | |
10577 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10578 ins_pipe(pipe_slow); // XXX | |
10579 %} | |
10580 | |
10581 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
10582 %{ | |
10583 match(Set dst (ConvI2L src)); | |
10584 | |
10585 ins_cost(125); | |
10586 format %{ "movslq $dst, $src\t# i2l" %} | |
10587 opcode(0x63); // needs REX.W | |
10588 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
10589 ins_pipe(ialu_reg_reg); | |
10590 %} | |
10591 | |
10592 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
10593 // %{ | |
10594 // match(Set dst (ConvI2L src)); | |
10595 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
10596 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
10597 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
10598 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
10599 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
10600 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
10601 | |
10602 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
10603 // ins_encode(enc_copy(dst, src)); | |
10604 // // opcode(0x63); // needs REX.W | |
10605 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
10606 // ins_pipe(ialu_reg_reg); | |
10607 // %} | |
10608 | |
10609 instruct convI2L_reg_mem(rRegL dst, memory src) | |
10610 %{ | |
10611 match(Set dst (ConvI2L (LoadI src))); | |
10612 | |
10613 format %{ "movslq $dst, $src\t# i2l" %} | |
10614 opcode(0x63); // needs REX.W | |
10615 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src)); | |
10616 ins_pipe(ialu_reg_mem); | |
10617 %} | |
10618 | |
10619 // Zero-extend convert int to long | |
10620 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
10621 %{ | |
10622 match(Set dst (AndL (ConvI2L src) mask)); | |
10623 | |
10624 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
10625 ins_encode(enc_copy(dst, src)); | |
10626 ins_pipe(ialu_reg_reg); | |
10627 %} | |
10628 | |
10629 // Zero-extend convert int to long | |
10630 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
10631 %{ | |
10632 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
10633 | |
10634 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
10635 opcode(0x8B); | |
10636 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
10637 ins_pipe(ialu_reg_mem); | |
10638 %} | |
10639 | |
10640 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
10641 %{ | |
10642 match(Set dst (AndL src mask)); | |
10643 | |
10644 format %{ "movl $dst, $src\t# zero-extend long" %} | |
10645 ins_encode(enc_copy_always(dst, src)); | |
10646 ins_pipe(ialu_reg_reg); | |
10647 %} | |
10648 | |
10649 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
10650 %{ | |
10651 match(Set dst (ConvL2I src)); | |
10652 | |
10653 format %{ "movl $dst, $src\t# l2i" %} | |
10654 ins_encode(enc_copy_always(dst, src)); | |
10655 ins_pipe(ialu_reg_reg); | |
10656 %} | |
10657 | |
10658 | |
10659 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
10660 match(Set dst (MoveF2I src)); | |
10661 effect(DEF dst, USE src); | |
10662 | |
10663 ins_cost(125); | |
10664 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
10665 opcode(0x8B); | |
10666 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
10667 ins_pipe(ialu_reg_mem); | |
10668 %} | |
10669 | |
10670 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
10671 match(Set dst (MoveI2F src)); | |
10672 effect(DEF dst, USE src); | |
10673 | |
10674 ins_cost(125); | |
10675 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
10676 opcode(0xF3, 0x0F, 0x10); | |
10677 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10678 ins_pipe(pipe_slow); | |
10679 %} | |
10680 | |
10681 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
10682 match(Set dst (MoveD2L src)); | |
10683 effect(DEF dst, USE src); | |
10684 | |
10685 ins_cost(125); | |
10686 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
10687 opcode(0x8B); | |
10688 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
10689 ins_pipe(ialu_reg_mem); | |
10690 %} | |
10691 | |
10692 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
10693 predicate(!UseXmmLoadAndClearUpper); | |
10694 match(Set dst (MoveL2D src)); | |
10695 effect(DEF dst, USE src); | |
10696 | |
10697 ins_cost(125); | |
10698 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
10699 opcode(0x66, 0x0F, 0x12); | |
10700 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10701 ins_pipe(pipe_slow); | |
10702 %} | |
10703 | |
10704 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
10705 predicate(UseXmmLoadAndClearUpper); | |
10706 match(Set dst (MoveL2D src)); | |
10707 effect(DEF dst, USE src); | |
10708 | |
10709 ins_cost(125); | |
10710 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
10711 opcode(0xF2, 0x0F, 0x10); | |
10712 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
10713 ins_pipe(pipe_slow); | |
10714 %} | |
10715 | |
10716 | |
10717 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
10718 match(Set dst (MoveF2I src)); | |
10719 effect(DEF dst, USE src); | |
10720 | |
10721 ins_cost(95); // XXX | |
10722 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
10723 opcode(0xF3, 0x0F, 0x11); | |
10724 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
10725 ins_pipe(pipe_slow); | |
10726 %} | |
10727 | |
10728 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
10729 match(Set dst (MoveI2F src)); | |
10730 effect(DEF dst, USE src); | |
10731 | |
10732 ins_cost(100); | |
10733 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
10734 opcode(0x89); | |
10735 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
10736 ins_pipe( ialu_mem_reg ); | |
10737 %} | |
10738 | |
10739 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
10740 match(Set dst (MoveD2L src)); | |
10741 effect(DEF dst, USE src); | |
10742 | |
10743 ins_cost(95); // XXX | |
10744 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
10745 opcode(0xF2, 0x0F, 0x11); | |
10746 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
10747 ins_pipe(pipe_slow); | |
10748 %} | |
10749 | |
10750 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
10751 match(Set dst (MoveL2D src)); | |
10752 effect(DEF dst, USE src); | |
10753 | |
10754 ins_cost(100); | |
10755 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
10756 opcode(0x89); | |
10757 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
10758 ins_pipe(ialu_mem_reg); | |
10759 %} | |
10760 | |
10761 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
10762 match(Set dst (MoveF2I src)); | |
10763 effect(DEF dst, USE src); | |
10764 ins_cost(85); | |
10765 format %{ "movd $dst,$src\t# MoveF2I" %} | |
10766 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | |
10767 ins_pipe( pipe_slow ); | |
10768 %} | |
10769 | |
10770 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
10771 match(Set dst (MoveD2L src)); | |
10772 effect(DEF dst, USE src); | |
10773 ins_cost(85); | |
10774 format %{ "movd $dst,$src\t# MoveD2L" %} | |
10775 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | |
10776 ins_pipe( pipe_slow ); | |
10777 %} | |
10778 | |
10779 // The next instructions have long latency and use Int unit. Set high cost. | |
10780 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
10781 match(Set dst (MoveI2F src)); | |
10782 effect(DEF dst, USE src); | |
10783 ins_cost(300); | |
10784 format %{ "movd $dst,$src\t# MoveI2F" %} | |
10785 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | |
10786 ins_pipe( pipe_slow ); | |
10787 %} | |
10788 | |
10789 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
10790 match(Set dst (MoveL2D src)); | |
10791 effect(DEF dst, USE src); | |
10792 ins_cost(300); | |
10793 format %{ "movd $dst,$src\t# MoveL2D" %} | |
10794 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | |
10795 ins_pipe( pipe_slow ); | |
10796 %} | |
10797 | |
10798 // Replicate scalar to packed byte (1 byte) values in xmm | |
10799 instruct Repl8B_reg(regD dst, regD src) %{ | |
10800 match(Set dst (Replicate8B src)); | |
10801 format %{ "MOVDQA $dst,$src\n\t" | |
10802 "PUNPCKLBW $dst,$dst\n\t" | |
10803 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
10804 ins_encode( pshufd_8x8(dst, src)); | |
10805 ins_pipe( pipe_slow ); | |
10806 %} | |
10807 | |
10808 // Replicate scalar to packed byte (1 byte) values in xmm | |
10809 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
10810 match(Set dst (Replicate8B src)); | |
10811 format %{ "MOVD $dst,$src\n\t" | |
10812 "PUNPCKLBW $dst,$dst\n\t" | |
10813 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
10814 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
10815 ins_pipe( pipe_slow ); | |
10816 %} | |
10817 | |
10818 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
10819 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
10820 match(Set dst (Replicate8B zero)); | |
10821 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
10822 ins_encode( pxor(dst, dst)); | |
10823 ins_pipe( fpu_reg_reg ); | |
10824 %} | |
10825 | |
10826 // Replicate scalar to packed shore (2 byte) values in xmm | |
10827 instruct Repl4S_reg(regD dst, regD src) %{ | |
10828 match(Set dst (Replicate4S src)); | |
10829 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
10830 ins_encode( pshufd_4x16(dst, src)); | |
10831 ins_pipe( fpu_reg_reg ); | |
10832 %} | |
10833 | |
10834 // Replicate scalar to packed shore (2 byte) values in xmm | |
10835 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
10836 match(Set dst (Replicate4S src)); | |
10837 format %{ "MOVD $dst,$src\n\t" | |
10838 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
10839 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
10840 ins_pipe( fpu_reg_reg ); | |
10841 %} | |
10842 | |
10843 // Replicate scalar zero to packed short (2 byte) values in xmm | |
10844 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
10845 match(Set dst (Replicate4S zero)); | |
10846 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
10847 ins_encode( pxor(dst, dst)); | |
10848 ins_pipe( fpu_reg_reg ); | |
10849 %} | |
10850 | |
10851 // Replicate scalar to packed char (2 byte) values in xmm | |
10852 instruct Repl4C_reg(regD dst, regD src) %{ | |
10853 match(Set dst (Replicate4C src)); | |
10854 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
10855 ins_encode( pshufd_4x16(dst, src)); | |
10856 ins_pipe( fpu_reg_reg ); | |
10857 %} | |
10858 | |
10859 // Replicate scalar to packed char (2 byte) values in xmm | |
10860 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
10861 match(Set dst (Replicate4C src)); | |
10862 format %{ "MOVD $dst,$src\n\t" | |
10863 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
10864 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
10865 ins_pipe( fpu_reg_reg ); | |
10866 %} | |
10867 | |
10868 // Replicate scalar zero to packed char (2 byte) values in xmm | |
10869 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
10870 match(Set dst (Replicate4C zero)); | |
10871 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
10872 ins_encode( pxor(dst, dst)); | |
10873 ins_pipe( fpu_reg_reg ); | |
10874 %} | |
10875 | |
10876 // Replicate scalar to packed integer (4 byte) values in xmm | |
10877 instruct Repl2I_reg(regD dst, regD src) %{ | |
10878 match(Set dst (Replicate2I src)); | |
10879 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
10880 ins_encode( pshufd(dst, src, 0x00)); | |
10881 ins_pipe( fpu_reg_reg ); | |
10882 %} | |
10883 | |
10884 // Replicate scalar to packed integer (4 byte) values in xmm | |
10885 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
10886 match(Set dst (Replicate2I src)); | |
10887 format %{ "MOVD $dst,$src\n\t" | |
10888 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
10889 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
10890 ins_pipe( fpu_reg_reg ); | |
10891 %} | |
10892 | |
10893 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
10894 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
10895 match(Set dst (Replicate2I zero)); | |
10896 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
10897 ins_encode( pxor(dst, dst)); | |
10898 ins_pipe( fpu_reg_reg ); | |
10899 %} | |
10900 | |
10901 // Replicate scalar to packed single precision floating point values in xmm | |
10902 instruct Repl2F_reg(regD dst, regD src) %{ | |
10903 match(Set dst (Replicate2F src)); | |
10904 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
10905 ins_encode( pshufd(dst, src, 0xe0)); | |
10906 ins_pipe( fpu_reg_reg ); | |
10907 %} | |
10908 | |
10909 // Replicate scalar to packed single precision floating point values in xmm | |
10910 instruct Repl2F_regF(regD dst, regF src) %{ | |
10911 match(Set dst (Replicate2F src)); | |
10912 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
10913 ins_encode( pshufd(dst, src, 0xe0)); | |
10914 ins_pipe( fpu_reg_reg ); | |
10915 %} | |
10916 | |
10917 // Replicate scalar to packed single precision floating point values in xmm | |
10918 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
10919 match(Set dst (Replicate2F zero)); | |
10920 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
10921 ins_encode( pxor(dst, dst)); | |
10922 ins_pipe( fpu_reg_reg ); | |
10923 %} | |
10924 | |
10925 | |
10926 // ======================================================================= | |
10927 // fast clearing of an array | |
10928 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
10929 rFlagsReg cr) | |
10930 %{ | |
10931 match(Set dummy (ClearArray cnt base)); | |
10932 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
10933 | |
10934 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
10935 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
10936 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
10937 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
10938 ins_pipe(pipe_slow); | |
10939 %} | |
10940 | |
10941 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1, | |
10942 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) | |
10943 %{ | |
10944 match(Set result (StrComp str1 str2)); | |
10945 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); | |
10946 //ins_cost(300); | |
10947 | |
10948 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %} | |
10949 ins_encode( enc_String_Compare() ); | |
10950 ins_pipe( pipe_slow ); | |
10951 %} | |
10952 | |
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10953 // fast array equals |
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10954 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, |
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10955 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) %{ |
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10956 match(Set result (AryEq ary1 ary2)); |
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10957 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr); |
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10958 //ins_cost(300); |
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10959 |
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10960 format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %} |
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10961 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) ); |
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10962 ins_pipe( pipe_slow ); |
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10963 %} |
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10964 |
0 | 10965 //----------Control Flow Instructions------------------------------------------ |
10966 // Signed compare Instructions | |
10967 | |
10968 // XXX more variants!! | |
10969 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
10970 %{ | |
10971 match(Set cr (CmpI op1 op2)); | |
10972 effect(DEF cr, USE op1, USE op2); | |
10973 | |
10974 format %{ "cmpl $op1, $op2" %} | |
10975 opcode(0x3B); /* Opcode 3B /r */ | |
10976 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
10977 ins_pipe(ialu_cr_reg_reg); | |
10978 %} | |
10979 | |
10980 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
10981 %{ | |
10982 match(Set cr (CmpI op1 op2)); | |
10983 | |
10984 format %{ "cmpl $op1, $op2" %} | |
10985 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
10986 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
10987 ins_pipe(ialu_cr_reg_imm); | |
10988 %} | |
10989 | |
10990 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
10991 %{ | |
10992 match(Set cr (CmpI op1 (LoadI op2))); | |
10993 | |
10994 ins_cost(500); // XXX | |
10995 format %{ "cmpl $op1, $op2" %} | |
10996 opcode(0x3B); /* Opcode 3B /r */ | |
10997 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
10998 ins_pipe(ialu_cr_reg_mem); | |
10999 %} | |
11000 | |
11001 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
11002 %{ | |
11003 match(Set cr (CmpI src zero)); | |
11004 | |
11005 format %{ "testl $src, $src" %} | |
11006 opcode(0x85); | |
11007 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
11008 ins_pipe(ialu_cr_reg_imm); | |
11009 %} | |
11010 | |
11011 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
11012 %{ | |
11013 match(Set cr (CmpI (AndI src con) zero)); | |
11014 | |
11015 format %{ "testl $src, $con" %} | |
11016 opcode(0xF7, 0x00); | |
11017 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
11018 ins_pipe(ialu_cr_reg_imm); | |
11019 %} | |
11020 | |
11021 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
11022 %{ | |
11023 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
11024 | |
11025 format %{ "testl $src, $mem" %} | |
11026 opcode(0x85); | |
11027 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
11028 ins_pipe(ialu_cr_reg_mem); | |
11029 %} | |
11030 | |
11031 // Unsigned compare Instructions; really, same as signed except they | |
11032 // produce an rFlagsRegU instead of rFlagsReg. | |
11033 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
11034 %{ | |
11035 match(Set cr (CmpU op1 op2)); | |
11036 | |
11037 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
11038 opcode(0x3B); /* Opcode 3B /r */ | |
11039 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
11040 ins_pipe(ialu_cr_reg_reg); | |
11041 %} | |
11042 | |
11043 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
11044 %{ | |
11045 match(Set cr (CmpU op1 op2)); | |
11046 | |
11047 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
11048 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
11049 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
11050 ins_pipe(ialu_cr_reg_imm); | |
11051 %} | |
11052 | |
11053 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
11054 %{ | |
11055 match(Set cr (CmpU op1 (LoadI op2))); | |
11056 | |
11057 ins_cost(500); // XXX | |
11058 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
11059 opcode(0x3B); /* Opcode 3B /r */ | |
11060 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
11061 ins_pipe(ialu_cr_reg_mem); | |
11062 %} | |
11063 | |
11064 // // // Cisc-spilled version of cmpU_rReg | |
11065 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
11066 // //%{ | |
11067 // // match(Set cr (CmpU (LoadI op1) op2)); | |
11068 // // | |
11069 // // format %{ "CMPu $op1,$op2" %} | |
11070 // // ins_cost(500); | |
11071 // // opcode(0x39); /* Opcode 39 /r */ | |
11072 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
11073 // //%} | |
11074 | |
11075 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
11076 %{ | |
11077 match(Set cr (CmpU src zero)); | |
11078 | |
11079 format %{ "testl $src, $src\t# unsigned" %} | |
11080 opcode(0x85); | |
11081 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
11082 ins_pipe(ialu_cr_reg_imm); | |
11083 %} | |
11084 | |
11085 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
11086 %{ | |
11087 match(Set cr (CmpP op1 op2)); | |
11088 | |
11089 format %{ "cmpq $op1, $op2\t# ptr" %} | |
11090 opcode(0x3B); /* Opcode 3B /r */ | |
11091 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
11092 ins_pipe(ialu_cr_reg_reg); | |
11093 %} | |
11094 | |
11095 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
11096 %{ | |
11097 match(Set cr (CmpP op1 (LoadP op2))); | |
11098 | |
11099 ins_cost(500); // XXX | |
11100 format %{ "cmpq $op1, $op2\t# ptr" %} | |
11101 opcode(0x3B); /* Opcode 3B /r */ | |
11102 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
11103 ins_pipe(ialu_cr_reg_mem); | |
11104 %} | |
11105 | |
11106 // // // Cisc-spilled version of cmpP_rReg | |
11107 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
11108 // //%{ | |
11109 // // match(Set cr (CmpP (LoadP op1) op2)); | |
11110 // // | |
11111 // // format %{ "CMPu $op1,$op2" %} | |
11112 // // ins_cost(500); | |
11113 // // opcode(0x39); /* Opcode 39 /r */ | |
11114 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
11115 // //%} | |
11116 | |
11117 // XXX this is generalized by compP_rReg_mem??? | |
11118 // Compare raw pointer (used in out-of-heap check). | |
11119 // Only works because non-oop pointers must be raw pointers | |
11120 // and raw pointers have no anti-dependencies. | |
11121 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
11122 %{ | |
11123 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
11124 match(Set cr (CmpP op1 (LoadP op2))); | |
11125 | |
11126 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
11127 opcode(0x3B); /* Opcode 3B /r */ | |
11128 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
11129 ins_pipe(ialu_cr_reg_mem); | |
11130 %} | |
11131 | |
11132 // This will generate a signed flags result. This should be OK since | |
11133 // any compare to a zero should be eq/neq. | |
11134 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
11135 %{ | |
11136 match(Set cr (CmpP src zero)); | |
11137 | |
11138 format %{ "testq $src, $src\t# ptr" %} | |
11139 opcode(0x85); | |
11140 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
11141 ins_pipe(ialu_cr_reg_imm); | |
11142 %} | |
11143 | |
11144 // This will generate a signed flags result. This should be OK since | |
11145 // any compare to a zero should be eq/neq. | |
11146 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero) | |
11147 %{ | |
11148 match(Set cr (CmpP (LoadP op) zero)); | |
11149 | |
11150 ins_cost(500); // XXX | |
11151 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
11152 opcode(0xF7); /* Opcode F7 /0 */ | |
11153 ins_encode(REX_mem_wide(op), | |
11154 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
11155 ins_pipe(ialu_cr_reg_imm); | |
11156 %} | |
11157 | |
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11158 |
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11159 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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11160 %{ |
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11161 match(Set cr (CmpN op1 op2)); |
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11162 |
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11163 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
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11164 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %} |
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11165 ins_pipe(ialu_cr_reg_reg); |
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11166 %} |
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11167 |
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11168 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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11169 %{ |
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11170 match(Set cr (CmpN src (LoadN mem))); |
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11171 |
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11172 ins_cost(500); // XXX |
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11173 format %{ "cmpl $src, mem\t# compressed ptr" %} |
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11174 ins_encode %{ |
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11175 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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11176 __ cmpl(as_Register($src$$reg), adr); |
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11177 %} |
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11178 ins_pipe(ialu_cr_reg_mem); |
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11179 %} |
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11180 |
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11181 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
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11182 match(Set cr (CmpN src zero)); |
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11183 |
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11184 format %{ "testl $src, $src\t# compressed ptr" %} |
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11185 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
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11186 ins_pipe(ialu_cr_reg_imm); |
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11187 %} |
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11188 |
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11189 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero) |
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11190 %{ |
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11191 match(Set cr (CmpN (LoadN mem) zero)); |
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11192 |
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11193 ins_cost(500); // XXX |
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11194 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
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11195 ins_encode %{ |
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11196 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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11197 __ cmpl(addr, (int)0xFFFFFFFF); |
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11198 %} |
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11199 ins_pipe(ialu_cr_reg_mem); |
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11200 %} |
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11201 |
0 | 11202 // Yanked all unsigned pointer compare operations. |
11203 // Pointer compares are done with CmpP which is already unsigned. | |
11204 | |
11205 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
11206 %{ | |
11207 match(Set cr (CmpL op1 op2)); | |
11208 | |
11209 format %{ "cmpq $op1, $op2" %} | |
11210 opcode(0x3B); /* Opcode 3B /r */ | |
11211 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
11212 ins_pipe(ialu_cr_reg_reg); | |
11213 %} | |
11214 | |
11215 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
11216 %{ | |
11217 match(Set cr (CmpL op1 op2)); | |
11218 | |
11219 format %{ "cmpq $op1, $op2" %} | |
11220 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
11221 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
11222 ins_pipe(ialu_cr_reg_imm); | |
11223 %} | |
11224 | |
11225 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
11226 %{ | |
11227 match(Set cr (CmpL op1 (LoadL op2))); | |
11228 | |
11229 ins_cost(500); // XXX | |
11230 format %{ "cmpq $op1, $op2" %} | |
11231 opcode(0x3B); /* Opcode 3B /r */ | |
11232 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
11233 ins_pipe(ialu_cr_reg_mem); | |
11234 %} | |
11235 | |
11236 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
11237 %{ | |
11238 match(Set cr (CmpL src zero)); | |
11239 | |
11240 format %{ "testq $src, $src" %} | |
11241 opcode(0x85); | |
11242 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
11243 ins_pipe(ialu_cr_reg_imm); | |
11244 %} | |
11245 | |
11246 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
11247 %{ | |
11248 match(Set cr (CmpL (AndL src con) zero)); | |
11249 | |
11250 format %{ "testq $src, $con\t# long" %} | |
11251 opcode(0xF7, 0x00); | |
11252 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
11253 ins_pipe(ialu_cr_reg_imm); | |
11254 %} | |
11255 | |
11256 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
11257 %{ | |
11258 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
11259 | |
11260 format %{ "testq $src, $mem" %} | |
11261 opcode(0x85); | |
11262 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
11263 ins_pipe(ialu_cr_reg_mem); | |
11264 %} | |
11265 | |
11266 // Manifest a CmpL result in an integer register. Very painful. | |
11267 // This is the test to avoid. | |
11268 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
11269 %{ | |
11270 match(Set dst (CmpL3 src1 src2)); | |
11271 effect(KILL flags); | |
11272 | |
11273 ins_cost(275); // XXX | |
11274 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
11275 "movl $dst, -1\n\t" | |
11276 "jl,s done\n\t" | |
11277 "setne $dst\n\t" | |
11278 "movzbl $dst, $dst\n\t" | |
11279 "done:" %} | |
11280 ins_encode(cmpl3_flag(src1, src2, dst)); | |
11281 ins_pipe(pipe_slow); | |
11282 %} | |
11283 | |
11284 //----------Max and Min-------------------------------------------------------- | |
11285 // Min Instructions | |
11286 | |
11287 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
11288 %{ | |
11289 effect(USE_DEF dst, USE src, USE cr); | |
11290 | |
11291 format %{ "cmovlgt $dst, $src\t# min" %} | |
11292 opcode(0x0F, 0x4F); | |
11293 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
11294 ins_pipe(pipe_cmov_reg); | |
11295 %} | |
11296 | |
11297 | |
11298 instruct minI_rReg(rRegI dst, rRegI src) | |
11299 %{ | |
11300 match(Set dst (MinI dst src)); | |
11301 | |
11302 ins_cost(200); | |
11303 expand %{ | |
11304 rFlagsReg cr; | |
11305 compI_rReg(cr, dst, src); | |
11306 cmovI_reg_g(dst, src, cr); | |
11307 %} | |
11308 %} | |
11309 | |
11310 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
11311 %{ | |
11312 effect(USE_DEF dst, USE src, USE cr); | |
11313 | |
11314 format %{ "cmovllt $dst, $src\t# max" %} | |
11315 opcode(0x0F, 0x4C); | |
11316 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
11317 ins_pipe(pipe_cmov_reg); | |
11318 %} | |
11319 | |
11320 | |
11321 instruct maxI_rReg(rRegI dst, rRegI src) | |
11322 %{ | |
11323 match(Set dst (MaxI dst src)); | |
11324 | |
11325 ins_cost(200); | |
11326 expand %{ | |
11327 rFlagsReg cr; | |
11328 compI_rReg(cr, dst, src); | |
11329 cmovI_reg_l(dst, src, cr); | |
11330 %} | |
11331 %} | |
11332 | |
11333 // ============================================================================ | |
11334 // Branch Instructions | |
11335 | |
11336 // Jump Direct - Label defines a relative address from JMP+1 | |
11337 instruct jmpDir(label labl) | |
11338 %{ | |
11339 match(Goto); | |
11340 effect(USE labl); | |
11341 | |
11342 ins_cost(300); | |
11343 format %{ "jmp $labl" %} | |
11344 size(5); | |
11345 opcode(0xE9); | |
11346 ins_encode(OpcP, Lbl(labl)); | |
11347 ins_pipe(pipe_jmp); | |
11348 ins_pc_relative(1); | |
11349 %} | |
11350 | |
11351 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11352 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
11353 %{ | |
11354 match(If cop cr); | |
11355 effect(USE labl); | |
11356 | |
11357 ins_cost(300); | |
11358 format %{ "j$cop $labl" %} | |
11359 size(6); | |
11360 opcode(0x0F, 0x80); | |
11361 ins_encode(Jcc(cop, labl)); | |
11362 ins_pipe(pipe_jcc); | |
11363 ins_pc_relative(1); | |
11364 %} | |
11365 | |
11366 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11367 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
11368 %{ | |
11369 match(CountedLoopEnd cop cr); | |
11370 effect(USE labl); | |
11371 | |
11372 ins_cost(300); | |
11373 format %{ "j$cop $labl\t# loop end" %} | |
11374 size(6); | |
11375 opcode(0x0F, 0x80); | |
11376 ins_encode(Jcc(cop, labl)); | |
11377 ins_pipe(pipe_jcc); | |
11378 ins_pc_relative(1); | |
11379 %} | |
11380 | |
11381 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11382 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) | |
11383 %{ | |
11384 match(CountedLoopEnd cop cmp); | |
11385 effect(USE labl); | |
11386 | |
11387 ins_cost(300); | |
11388 format %{ "j$cop,u $labl\t# loop end" %} | |
11389 size(6); | |
11390 opcode(0x0F, 0x80); | |
11391 ins_encode(Jcc(cop, labl)); | |
11392 ins_pipe(pipe_jcc); | |
11393 ins_pc_relative(1); | |
11394 %} | |
11395 | |
11396 // Jump Direct Conditional - using unsigned comparison | |
11397 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) | |
11398 %{ | |
11399 match(If cop cmp); | |
11400 effect(USE labl); | |
11401 | |
11402 ins_cost(300); | |
11403 format %{ "j$cop,u $labl" %} | |
11404 size(6); | |
11405 opcode(0x0F, 0x80); | |
11406 ins_encode(Jcc(cop, labl)); | |
11407 ins_pipe(pipe_jcc); | |
11408 ins_pc_relative(1); | |
11409 %} | |
11410 | |
11411 // ============================================================================ | |
11412 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
11413 // superklass array for an instance of the superklass. Set a hidden | |
11414 // internal cache on a hit (cache is checked with exposed code in | |
11415 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
11416 // encoding ALSO sets flags. | |
11417 | |
11418 instruct partialSubtypeCheck(rdi_RegP result, | |
11419 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
11420 rFlagsReg cr) | |
11421 %{ | |
11422 match(Set result (PartialSubtypeCheck sub super)); | |
11423 effect(KILL rcx, KILL cr); | |
11424 | |
11425 ins_cost(1100); // slightly larger than the next version | |
11426 format %{ "cmpq rax, rsi\n\t" | |
11427 "jeq,s hit\n\t" | |
11428 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" | |
11429 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" | |
11430 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
11431 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
11432 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
11433 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
11434 "hit:\n\t" | |
11435 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
11436 "miss:\t" %} | |
11437 | |
11438 opcode(0x1); // Force a XOR of RDI | |
11439 ins_encode(enc_PartialSubtypeCheck()); | |
11440 ins_pipe(pipe_slow); | |
11441 %} | |
11442 | |
11443 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
11444 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
11445 immP0 zero, | |
11446 rdi_RegP result) | |
11447 %{ | |
11448 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
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|
11449 predicate(!UseCompressedOops); // decoding oop kills condition codes |
0 | 11450 effect(KILL rcx, KILL result); |
11451 | |
11452 ins_cost(1000); | |
11453 format %{ "cmpq rax, rsi\n\t" | |
11454 "jeq,s miss\t# Actually a hit; we are done.\n\t" | |
11455 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" | |
11456 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" | |
11457 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
11458 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
11459 "jne,s miss\t\t# Missed: flags nz\n\t" | |
11460 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
11461 "miss:\t" %} | |
11462 | |
11463 opcode(0x0); // No need to XOR RDI | |
11464 ins_encode(enc_PartialSubtypeCheck()); | |
11465 ins_pipe(pipe_slow); | |
11466 %} | |
11467 | |
11468 // ============================================================================ | |
11469 // Branch Instructions -- short offset versions | |
11470 // | |
11471 // These instructions are used to replace jumps of a long offset (the default | |
11472 // match) with jumps of a shorter offset. These instructions are all tagged | |
11473 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
11474 // match rules in general matching. Instead, the ADLC generates a conversion | |
11475 // method in the MachNode which can be used to do in-place replacement of the | |
11476 // long variant with the shorter variant. The compiler will determine if a | |
11477 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
11478 // specific code section of the file. | |
11479 | |
11480 // Jump Direct - Label defines a relative address from JMP+1 | |
11481 instruct jmpDir_short(label labl) | |
11482 %{ | |
11483 match(Goto); | |
11484 effect(USE labl); | |
11485 | |
11486 ins_cost(300); | |
11487 format %{ "jmp,s $labl" %} | |
11488 size(2); | |
11489 opcode(0xEB); | |
11490 ins_encode(OpcP, LblShort(labl)); | |
11491 ins_pipe(pipe_jmp); | |
11492 ins_pc_relative(1); | |
11493 ins_short_branch(1); | |
11494 %} | |
11495 | |
11496 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11497 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) | |
11498 %{ | |
11499 match(If cop cr); | |
11500 effect(USE labl); | |
11501 | |
11502 ins_cost(300); | |
11503 format %{ "j$cop,s $labl" %} | |
11504 size(2); | |
11505 opcode(0x70); | |
11506 ins_encode(JccShort(cop, labl)); | |
11507 ins_pipe(pipe_jcc); | |
11508 ins_pc_relative(1); | |
11509 ins_short_branch(1); | |
11510 %} | |
11511 | |
11512 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11513 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) | |
11514 %{ | |
11515 match(CountedLoopEnd cop cr); | |
11516 effect(USE labl); | |
11517 | |
11518 ins_cost(300); | |
11519 format %{ "j$cop,s $labl" %} | |
11520 size(2); | |
11521 opcode(0x70); | |
11522 ins_encode(JccShort(cop, labl)); | |
11523 ins_pipe(pipe_jcc); | |
11524 ins_pc_relative(1); | |
11525 ins_short_branch(1); | |
11526 %} | |
11527 | |
11528 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
11529 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) | |
11530 %{ | |
11531 match(CountedLoopEnd cop cmp); | |
11532 effect(USE labl); | |
11533 | |
11534 ins_cost(300); | |
11535 format %{ "j$cop,us $labl" %} | |
11536 size(2); | |
11537 opcode(0x70); | |
11538 ins_encode(JccShort(cop, labl)); | |
11539 ins_pipe(pipe_jcc); | |
11540 ins_pc_relative(1); | |
11541 ins_short_branch(1); | |
11542 %} | |
11543 | |
11544 // Jump Direct Conditional - using unsigned comparison | |
11545 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) | |
11546 %{ | |
11547 match(If cop cmp); | |
11548 effect(USE labl); | |
11549 | |
11550 ins_cost(300); | |
11551 format %{ "j$cop,us $labl" %} | |
11552 size(2); | |
11553 opcode(0x70); | |
11554 ins_encode(JccShort(cop, labl)); | |
11555 ins_pipe(pipe_jcc); | |
11556 ins_pc_relative(1); | |
11557 ins_short_branch(1); | |
11558 %} | |
11559 | |
11560 // ============================================================================ | |
11561 // inlined locking and unlocking | |
11562 | |
11563 instruct cmpFastLock(rFlagsReg cr, | |
11564 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
11565 %{ | |
11566 match(Set cr (FastLock object box)); | |
11567 effect(TEMP tmp, TEMP scr); | |
11568 | |
11569 ins_cost(300); | |
11570 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
11571 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
11572 ins_pipe(pipe_slow); | |
11573 ins_pc_relative(1); | |
11574 %} | |
11575 | |
11576 instruct cmpFastUnlock(rFlagsReg cr, | |
11577 rRegP object, rax_RegP box, rRegP tmp) | |
11578 %{ | |
11579 match(Set cr (FastUnlock object box)); | |
11580 effect(TEMP tmp); | |
11581 | |
11582 ins_cost(300); | |
11583 format %{ "fastunlock $object, $box, $tmp" %} | |
11584 ins_encode(Fast_Unlock(object, box, tmp)); | |
11585 ins_pipe(pipe_slow); | |
11586 ins_pc_relative(1); | |
11587 %} | |
11588 | |
11589 | |
11590 // ============================================================================ | |
11591 // Safepoint Instructions | |
11592 instruct safePoint_poll(rFlagsReg cr) | |
11593 %{ | |
11594 match(SafePoint); | |
11595 effect(KILL cr); | |
11596 | |
11597 format %{ "testl rax, [rip + #offset_to_poll_page]\t" | |
11598 "# Safepoint: poll for GC" %} | |
11599 size(6); // Opcode + ModRM + Disp32 == 6 bytes | |
11600 ins_cost(125); | |
11601 ins_encode(enc_safepoint_poll); | |
11602 ins_pipe(ialu_reg_mem); | |
11603 %} | |
11604 | |
11605 // ============================================================================ | |
11606 // Procedure Call/Return Instructions | |
11607 // Call Java Static Instruction | |
11608 // Note: If this code changes, the corresponding ret_addr_offset() and | |
11609 // compute_padding() functions will have to be adjusted. | |
11610 instruct CallStaticJavaDirect(method meth) | |
11611 %{ | |
11612 match(CallStaticJava); | |
11613 effect(USE meth); | |
11614 | |
11615 ins_cost(300); | |
11616 format %{ "call,static " %} | |
11617 opcode(0xE8); /* E8 cd */ | |
11618 ins_encode(Java_Static_Call(meth), call_epilog); | |
11619 ins_pipe(pipe_slow); | |
11620 ins_pc_relative(1); | |
11621 ins_alignment(4); | |
11622 %} | |
11623 | |
11624 // Call Java Dynamic Instruction | |
11625 // Note: If this code changes, the corresponding ret_addr_offset() and | |
11626 // compute_padding() functions will have to be adjusted. | |
11627 instruct CallDynamicJavaDirect(method meth) | |
11628 %{ | |
11629 match(CallDynamicJava); | |
11630 effect(USE meth); | |
11631 | |
11632 ins_cost(300); | |
11633 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
11634 "call,dynamic " %} | |
11635 opcode(0xE8); /* E8 cd */ | |
11636 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
11637 ins_pipe(pipe_slow); | |
11638 ins_pc_relative(1); | |
11639 ins_alignment(4); | |
11640 %} | |
11641 | |
11642 // Call Runtime Instruction | |
11643 instruct CallRuntimeDirect(method meth) | |
11644 %{ | |
11645 match(CallRuntime); | |
11646 effect(USE meth); | |
11647 | |
11648 ins_cost(300); | |
11649 format %{ "call,runtime " %} | |
11650 opcode(0xE8); /* E8 cd */ | |
11651 ins_encode(Java_To_Runtime(meth)); | |
11652 ins_pipe(pipe_slow); | |
11653 ins_pc_relative(1); | |
11654 %} | |
11655 | |
11656 // Call runtime without safepoint | |
11657 instruct CallLeafDirect(method meth) | |
11658 %{ | |
11659 match(CallLeaf); | |
11660 effect(USE meth); | |
11661 | |
11662 ins_cost(300); | |
11663 format %{ "call_leaf,runtime " %} | |
11664 opcode(0xE8); /* E8 cd */ | |
11665 ins_encode(Java_To_Runtime(meth)); | |
11666 ins_pipe(pipe_slow); | |
11667 ins_pc_relative(1); | |
11668 %} | |
11669 | |
11670 // Call runtime without safepoint | |
11671 instruct CallLeafNoFPDirect(method meth) | |
11672 %{ | |
11673 match(CallLeafNoFP); | |
11674 effect(USE meth); | |
11675 | |
11676 ins_cost(300); | |
11677 format %{ "call_leaf_nofp,runtime " %} | |
11678 opcode(0xE8); /* E8 cd */ | |
11679 ins_encode(Java_To_Runtime(meth)); | |
11680 ins_pipe(pipe_slow); | |
11681 ins_pc_relative(1); | |
11682 %} | |
11683 | |
11684 // Return Instruction | |
11685 // Remove the return address & jump to it. | |
11686 // Notice: We always emit a nop after a ret to make sure there is room | |
11687 // for safepoint patching | |
11688 instruct Ret() | |
11689 %{ | |
11690 match(Return); | |
11691 | |
11692 format %{ "ret" %} | |
11693 opcode(0xC3); | |
11694 ins_encode(OpcP); | |
11695 ins_pipe(pipe_jmp); | |
11696 %} | |
11697 | |
11698 // Tail Call; Jump from runtime stub to Java code. | |
11699 // Also known as an 'interprocedural jump'. | |
11700 // Target of jump will eventually return to caller. | |
11701 // TailJump below removes the return address. | |
11702 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
11703 %{ | |
11704 match(TailCall jump_target method_oop); | |
11705 | |
11706 ins_cost(300); | |
11707 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
11708 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
11709 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
11710 ins_pipe(pipe_jmp); | |
11711 %} | |
11712 | |
11713 // Tail Jump; remove the return address; jump to target. | |
11714 // TailCall above leaves the return address around. | |
11715 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
11716 %{ | |
11717 match(TailJump jump_target ex_oop); | |
11718 | |
11719 ins_cost(300); | |
11720 format %{ "popq rdx\t# pop return address\n\t" | |
11721 "jmp $jump_target" %} | |
11722 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
11723 ins_encode(Opcode(0x5a), // popq rdx | |
11724 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
11725 ins_pipe(pipe_jmp); | |
11726 %} | |
11727 | |
11728 // Create exception oop: created by stack-crawling runtime code. | |
11729 // Created exception is now available to this handler, and is setup | |
11730 // just prior to jumping to this handler. No code emitted. | |
11731 instruct CreateException(rax_RegP ex_oop) | |
11732 %{ | |
11733 match(Set ex_oop (CreateEx)); | |
11734 | |
11735 size(0); | |
11736 // use the following format syntax | |
11737 format %{ "# exception oop is in rax; no code emitted" %} | |
11738 ins_encode(); | |
11739 ins_pipe(empty); | |
11740 %} | |
11741 | |
11742 // Rethrow exception: | |
11743 // The exception oop will come in the first argument position. | |
11744 // Then JUMP (not call) to the rethrow stub code. | |
11745 instruct RethrowException() | |
11746 %{ | |
11747 match(Rethrow); | |
11748 | |
11749 // use the following format syntax | |
11750 format %{ "jmp rethrow_stub" %} | |
11751 ins_encode(enc_rethrow); | |
11752 ins_pipe(pipe_jmp); | |
11753 %} | |
11754 | |
11755 | |
11756 //----------PEEPHOLE RULES----------------------------------------------------- | |
11757 // These must follow all instruction definitions as they use the names | |
11758 // defined in the instructions definitions. | |
11759 // | |
11760 // peepmatch ( root_instr_name [precerding_instruction]* ); | |
11761 // | |
11762 // peepconstraint %{ | |
11763 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
11764 // [, ...] ); | |
11765 // // instruction numbers are zero-based using left to right order in peepmatch | |
11766 // | |
11767 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
11768 // // provide an instruction_number.operand_name for each operand that appears | |
11769 // // in the replacement instruction's match rule | |
11770 // | |
11771 // ---------VM FLAGS--------------------------------------------------------- | |
11772 // | |
11773 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
11774 // | |
11775 // Each peephole rule is given an identifying number starting with zero and | |
11776 // increasing by one in the order seen by the parser. An individual peephole | |
11777 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
11778 // on the command-line. | |
11779 // | |
11780 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
11781 // | |
11782 // Only match adjacent instructions in same basic block | |
11783 // Only equality constraints | |
11784 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
11785 // Only one replacement instruction | |
11786 // | |
11787 // ---------EXAMPLE---------------------------------------------------------- | |
11788 // | |
11789 // // pertinent parts of existing instructions in architecture description | |
11790 // instruct movI(rRegI dst, rRegI src) | |
11791 // %{ | |
11792 // match(Set dst (CopyI src)); | |
11793 // %} | |
11794 // | |
11795 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
11796 // %{ | |
11797 // match(Set dst (AddI dst src)); | |
11798 // effect(KILL cr); | |
11799 // %} | |
11800 // | |
11801 // // Change (inc mov) to lea | |
11802 // peephole %{ | |
11803 // // increment preceeded by register-register move | |
11804 // peepmatch ( incI_rReg movI ); | |
11805 // // require that the destination register of the increment | |
11806 // // match the destination register of the move | |
11807 // peepconstraint ( 0.dst == 1.dst ); | |
11808 // // construct a replacement instruction that sets | |
11809 // // the destination to ( move's source register + one ) | |
11810 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
11811 // %} | |
11812 // | |
11813 | |
11814 // Implementation no longer uses movX instructions since | |
11815 // machine-independent system no longer uses CopyX nodes. | |
11816 // | |
11817 // peephole | |
11818 // %{ | |
11819 // peepmatch (incI_rReg movI); | |
11820 // peepconstraint (0.dst == 1.dst); | |
11821 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
11822 // %} | |
11823 | |
11824 // peephole | |
11825 // %{ | |
11826 // peepmatch (decI_rReg movI); | |
11827 // peepconstraint (0.dst == 1.dst); | |
11828 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
11829 // %} | |
11830 | |
11831 // peephole | |
11832 // %{ | |
11833 // peepmatch (addI_rReg_imm movI); | |
11834 // peepconstraint (0.dst == 1.dst); | |
11835 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
11836 // %} | |
11837 | |
11838 // peephole | |
11839 // %{ | |
11840 // peepmatch (incL_rReg movL); | |
11841 // peepconstraint (0.dst == 1.dst); | |
11842 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
11843 // %} | |
11844 | |
11845 // peephole | |
11846 // %{ | |
11847 // peepmatch (decL_rReg movL); | |
11848 // peepconstraint (0.dst == 1.dst); | |
11849 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
11850 // %} | |
11851 | |
11852 // peephole | |
11853 // %{ | |
11854 // peepmatch (addL_rReg_imm movL); | |
11855 // peepconstraint (0.dst == 1.dst); | |
11856 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
11857 // %} | |
11858 | |
11859 // peephole | |
11860 // %{ | |
11861 // peepmatch (addP_rReg_imm movP); | |
11862 // peepconstraint (0.dst == 1.dst); | |
11863 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
11864 // %} | |
11865 | |
11866 // // Change load of spilled value to only a spill | |
11867 // instruct storeI(memory mem, rRegI src) | |
11868 // %{ | |
11869 // match(Set mem (StoreI mem src)); | |
11870 // %} | |
11871 // | |
11872 // instruct loadI(rRegI dst, memory mem) | |
11873 // %{ | |
11874 // match(Set dst (LoadI mem)); | |
11875 // %} | |
11876 // | |
11877 | |
11878 peephole | |
11879 %{ | |
11880 peepmatch (loadI storeI); | |
11881 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
11882 peepreplace (storeI(1.mem 1.mem 1.src)); | |
11883 %} | |
11884 | |
11885 peephole | |
11886 %{ | |
11887 peepmatch (loadL storeL); | |
11888 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
11889 peepreplace (storeL(1.mem 1.mem 1.src)); | |
11890 %} | |
11891 | |
11892 //----------SMARTSPILL RULES--------------------------------------------------- | |
11893 // These must follow all instruction definitions as they use the names | |
11894 // defined in the instructions definitions. |