Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 681:fbde8ec322d0
6761600: Use sse 4.2 in intrinsics
Summary: Use SSE 4.2 in intrinsics for String.{compareTo/equals/indexOf} and Arrays.equals.
Reviewed-by: kvn, never, jrose
author | cfang |
---|---|
date | Tue, 31 Mar 2009 14:07:08 -0700 |
parents | bd441136a5ce |
children | 6b2273dd6fa9 |
rev | line source |
---|---|
0 | 1 // |
624 | 2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
21 // have any questions. | |
22 // | |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); | |
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); | |
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()); | |
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next()); | |
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()); | |
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next()); | |
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()); | |
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next()); | |
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()); | |
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next()); | |
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()); | |
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next()); | |
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()); | |
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next()); | |
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()); | |
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next()); | |
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()); | |
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next()); | |
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()); | |
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next()); | |
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()); | |
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next()); | |
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()); | |
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next()); | |
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()); | |
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next()); | |
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()); | |
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next()); | |
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()); | |
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next()); | |
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()); | |
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next()); | |
228 | |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
429 %} | |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
463 // Macros to extract hi & lo halves from a long pair. | |
464 // G0 is not part of any long pair, so assert on that. | |
605 | 465 // Prevents accidentally using G1 instead of G0. |
0 | 466 #define LONG_HI_REG(x) (x) |
467 #define LONG_LO_REG(x) (x) | |
468 | |
469 %} | |
470 | |
471 source %{ | |
472 #define __ _masm. | |
473 | |
474 // tertiary op of a LoadP or StoreP encoding | |
475 #define REGP_OP true | |
476 | |
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
479 static Register reg_to_register_object(int register_encoding); | |
480 | |
481 // Used by the DFA in dfa_sparc.cpp. | |
482 // Check for being able to use a V9 branch-on-register. Requires a | |
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
484 // extended. Doesn't work following an integer ADD, for example, because of | |
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
487 // replace them with zero, which could become sign-extension in a different OS | |
488 // release. There's no obvious reason why an interrupt will ever fill these | |
489 // bits with non-zero junk (the registers are reloaded with standard LD | |
490 // instructions which either zero-fill or sign-fill). | |
491 bool can_branch_register( Node *bol, Node *cmp ) { | |
492 if( !BranchOnRegister ) return false; | |
493 #ifdef _LP64 | |
494 if( cmp->Opcode() == Op_CmpP ) | |
495 return true; // No problems with pointer compares | |
496 #endif | |
497 if( cmp->Opcode() == Op_CmpL ) | |
498 return true; // No problems with long compares | |
499 | |
500 if( !SparcV9RegsHiBitsZero ) return false; | |
501 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
502 bol->as_Bool()->_test._test != BoolTest::eq ) | |
503 return false; | |
504 | |
505 // Check for comparing against a 'safe' value. Any operation which | |
506 // clears out the high word is safe. Thus, loads and certain shifts | |
507 // are safe, as are non-negative constants. Any operation which | |
508 // preserves zero bits in the high word is safe as long as each of its | |
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
510 // inputs are safe. At present, the only important case to recognize | |
511 // seems to be loads. Constants should fold away, and shifts & | |
512 // logicals can use the 'cc' forms. | |
513 Node *x = cmp->in(1); | |
514 if( x->is_Load() ) return true; | |
515 if( x->is_Phi() ) { | |
516 for( uint i = 1; i < x->req(); i++ ) | |
517 if( !x->in(i)->is_Load() ) | |
518 return false; | |
519 return true; | |
520 } | |
521 return false; | |
522 } | |
523 | |
524 // **************************************************************************** | |
525 | |
526 // REQUIRED FUNCTIONALITY | |
527 | |
528 // !!!!! Special hack to get all type of calls to specify the byte offset | |
529 // from the start of the call to the point where the return address | |
530 // will point. | |
531 // The "return address" is the address of the call instruction, plus 8. | |
532 | |
533 int MachCallStaticJavaNode::ret_addr_offset() { | |
534 return NativeCall::instruction_size; // call; delay slot | |
535 } | |
536 | |
537 int MachCallDynamicJavaNode::ret_addr_offset() { | |
538 int vtable_index = this->_vtable_index; | |
539 if (vtable_index < 0) { | |
540 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
542 return (NativeMovConstReg::instruction_size + | |
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
544 } else { | |
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
548 int klass_load_size; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
549 if (UseCompressedOops) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
550 assert(Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
551 if (Universe::narrow_oop_base() == NULL) |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
553 else |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
554 klass_load_size = 3*BytesPerInstWord; |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
555 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
556 klass_load_size = 1*BytesPerInstWord; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
557 } |
0 | 558 if( Assembler::is_simm13(v_off) ) { |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
559 return klass_load_size + |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 561 NativeCall::instruction_size); // call; delay slot |
562 } else { | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
563 return klass_load_size + |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 565 NativeCall::instruction_size); // call; delay slot |
566 } | |
567 } | |
568 } | |
569 | |
570 int MachCallRuntimeNode::ret_addr_offset() { | |
571 #ifdef _LP64 | |
572 return NativeFarCall::instruction_size; // farcall; delay slot | |
573 #else | |
574 return NativeCall::instruction_size; // call; delay slot | |
575 #endif | |
576 } | |
577 | |
578 // Indicate if the safepoint node needs the polling page as an input. | |
579 // Since Sparc does not have absolute addressing, it does. | |
580 bool SafePointNode::needs_polling_address_input() { | |
581 return true; | |
582 } | |
583 | |
584 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
585 void emit_break(CodeBuffer &cbuf) { | |
586 MacroAssembler _masm(&cbuf); | |
587 __ breakpoint_trap(); | |
588 } | |
589 | |
590 #ifndef PRODUCT | |
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
592 st->print("TA"); | |
593 } | |
594 #endif | |
595 | |
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
597 emit_break(cbuf); | |
598 } | |
599 | |
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
601 return MachNode::size(ra_); | |
602 } | |
603 | |
604 // Traceable jump | |
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
606 MacroAssembler _masm(&cbuf); | |
607 Register rdest = reg_to_register_object(jump_target); | |
608 __ JMP(rdest, 0); | |
609 __ delayed()->nop(); | |
610 } | |
611 | |
612 // Traceable jump and set exception pc | |
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
614 MacroAssembler _masm(&cbuf); | |
615 Register rdest = reg_to_register_object(jump_target); | |
616 __ JMP(rdest, 0); | |
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
618 } | |
619 | |
620 void emit_nop(CodeBuffer &cbuf) { | |
621 MacroAssembler _masm(&cbuf); | |
622 __ nop(); | |
623 } | |
624 | |
625 void emit_illtrap(CodeBuffer &cbuf) { | |
626 MacroAssembler _masm(&cbuf); | |
627 __ illtrap(0); | |
628 } | |
629 | |
630 | |
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
632 assert(n->rule() != loadUB_rule, ""); | |
633 | |
634 intptr_t offset = 0; | |
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
636 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
639 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
640 atype = atype->add_offset(offset); | |
641 assert(disp32 == offset, "wrong disp32"); | |
642 return atype->_offset; | |
643 } | |
644 | |
645 | |
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
647 assert(n->rule() != loadUB_rule, ""); | |
648 | |
649 intptr_t offset = 0; | |
650 Node* addr = n->in(2); | |
651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
653 Node* a = addr->in(2/*AddPNode::Address*/); | |
654 Node* o = addr->in(3/*AddPNode::Offset*/); | |
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
656 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
657 assert(atype->isa_oop_ptr(), "still an oop"); | |
658 } | |
659 offset = atype->is_ptr()->_offset; | |
660 if (offset != Type::OffsetBot) offset += disp32; | |
661 return offset; | |
662 } | |
663 | |
664 // Standard Sparc opcode form2 field breakdown | |
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
667 int op = (f30 << 30) | | |
668 (f29 << 29) | | |
669 (f25 << 25) | | |
670 (f22 << 22) | | |
671 (f20 << 20) | | |
672 (f19 << 19) | | |
673 (f0 << 0); | |
674 *((int*)(cbuf.code_end())) = op; | |
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
676 } | |
677 | |
678 // Standard Sparc opcode form2 field breakdown | |
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
680 f0 >>= 10; // Drop 10 bits | |
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
682 int op = (f30 << 30) | | |
683 (f25 << 25) | | |
684 (f22 << 22) | | |
685 (f0 << 0); | |
686 *((int*)(cbuf.code_end())) = op; | |
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
688 } | |
689 | |
690 // Standard Sparc opcode form3 field breakdown | |
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
692 int op = (f30 << 30) | | |
693 (f25 << 25) | | |
694 (f19 << 19) | | |
695 (f14 << 14) | | |
696 (f5 << 5) | | |
697 (f0 << 0); | |
698 *((int*)(cbuf.code_end())) = op; | |
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
700 } | |
701 | |
702 // Standard Sparc opcode form3 field breakdown | |
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
704 simm13 &= (1<<13)-1; // Mask to 13 bits | |
705 int op = (f30 << 30) | | |
706 (f25 << 25) | | |
707 (f19 << 19) | | |
708 (f14 << 14) | | |
709 (1 << 13) | // bit to indicate immediate-mode | |
710 (simm13<<0); | |
711 *((int*)(cbuf.code_end())) = op; | |
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
713 } | |
714 | |
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
716 simm10 &= (1<<10)-1; // Mask to 10 bits | |
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
718 } | |
719 | |
720 #ifdef ASSERT | |
721 // Helper function for VerifyOops in emit_form3_mem_reg | |
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
723 warning("VerifyOops encountered unexpected instruction:"); | |
724 n->dump(2); | |
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
726 } | |
727 #endif | |
728 | |
729 | |
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
731 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
732 | |
733 #ifdef ASSERT | |
734 // The following code implements the +VerifyOops feature. | |
735 // It verifies oop values which are loaded into or stored out of | |
736 // the current method activation. +VerifyOops complements techniques | |
737 // like ScavengeALot, because it eagerly inspects oops in transit, | |
738 // as they enter or leave the stack, as opposed to ScavengeALot, | |
739 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
740 // For this reason, +VerifyOops can sometimes detect bugs very close | |
741 // to their point of creation. It can also serve as a cross-check | |
742 // on the validity of oop maps, when used toegether with ScavengeALot. | |
743 | |
744 // It would be good to verify oops at other points, especially | |
745 // when an oop is used as a base pointer for a load or store. | |
746 // This is presently difficult, because it is hard to know when | |
747 // a base address is biased or not. (If we had such information, | |
748 // it would be easy and useful to make a two-argument version of | |
749 // verify_oop which unbiases the base, and performs verification.) | |
750 | |
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
752 bool is_verified_oop_base = false; | |
753 bool is_verified_oop_load = false; | |
754 bool is_verified_oop_store = false; | |
755 int tmp_enc = -1; | |
756 if (VerifyOops && src1_enc != R_SP_enc) { | |
757 // classify the op, mainly for an assert check | |
758 int st_op = 0, ld_op = 0; | |
759 switch (primary) { | |
760 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
761 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
763 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
764 case Assembler::std_op3: st_op = Op_StoreL; break; | |
765 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
766 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
767 | |
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
779 | |
780 default: ShouldNotReachHere(); | |
781 } | |
782 if (tertiary == REGP_OP) { | |
783 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
785 else ShouldNotReachHere(); | |
786 if (st_op) { | |
787 // a store | |
788 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
789 Node* n2 = n->in(3); | |
790 if (n2 != NULL) { | |
791 const Type* t = n2->bottom_type(); | |
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
793 } | |
794 } else { | |
795 // a load | |
796 const Type* t = n->bottom_type(); | |
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
798 } | |
799 } | |
800 | |
801 if (ld_op) { | |
802 // a Load | |
803 // inputs are (0:control, 1:memory, 2:address) | |
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
818 !(n->rule() == loadUB_rule)) { | |
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
820 } | |
821 } else if (st_op) { | |
822 // a Store | |
823 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
830 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
831 } | |
832 } | |
833 | |
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
835 Node* addr = n->in(2); | |
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
838 if (atype != NULL) { | |
839 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
841 if (offset != offset_2) { | |
842 get_offset_from_base(n, atype, disp32); | |
843 get_offset_from_base_2(n, atype, disp32); | |
844 } | |
845 assert(offset == offset_2, "different offsets"); | |
846 if (offset == disp32) { | |
847 // we now know that src1 is a true oop pointer | |
848 is_verified_oop_base = true; | |
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
850 if( primary == Assembler::ldd_op3 ) { | |
851 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
852 } else { | |
853 tmp_enc = dst_enc; | |
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
855 assert(src1_enc != dst_enc, ""); | |
856 } | |
857 } | |
858 } | |
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
860 || offset == oopDesc::mark_offset_in_bytes())) { | |
861 // loading the mark should not be allowed either, but | |
862 // we don't check this since it conflicts with InlineObjectHash | |
863 // usage of LoadINode to get the mark. We could keep the | |
864 // check if we create a new LoadMarkNode | |
865 // but do not verify the object before its header is initialized | |
866 ShouldNotReachHere(); | |
867 } | |
868 } | |
869 } | |
870 } | |
871 } | |
872 #endif | |
873 | |
874 uint instr; | |
875 instr = (Assembler::ldst_op << 30) | |
876 | (dst_enc << 25) | |
877 | (primary << 19) | |
878 | (src1_enc << 14); | |
879 | |
880 uint index = src2_enc; | |
881 int disp = disp32; | |
882 | |
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
884 disp += STACK_BIAS; | |
885 | |
886 // We should have a compiler bailout here rather than a guarantee. | |
887 // Better yet would be some mechanism to handle variable-size matches correctly. | |
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
889 | |
890 if( disp == 0 ) { | |
891 // use reg-reg form | |
892 // bit 13 is already zero | |
893 instr |= index; | |
894 } else { | |
895 // use reg-imm form | |
896 instr |= 0x00002000; // set bit 13 to one | |
897 instr |= disp & 0x1FFF; | |
898 } | |
899 | |
900 uint *code = (uint*)cbuf.code_end(); | |
901 *code = instr; | |
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
903 | |
904 #ifdef ASSERT | |
905 { | |
906 MacroAssembler _masm(&cbuf); | |
907 if (is_verified_oop_base) { | |
908 __ verify_oop(reg_to_register_object(src1_enc)); | |
909 } | |
910 if (is_verified_oop_store) { | |
911 __ verify_oop(reg_to_register_object(dst_enc)); | |
912 } | |
913 if (tmp_enc != -1) { | |
914 __ mov(O7, reg_to_register_object(tmp_enc)); | |
915 } | |
916 if (is_verified_oop_load) { | |
917 __ verify_oop(reg_to_register_object(dst_enc)); | |
918 } | |
919 } | |
920 #endif | |
921 } | |
922 | |
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { | |
925 | |
926 uint instr; | |
927 instr = (Assembler::ldst_op << 30) | |
928 | (dst_enc << 25) | |
929 | (primary << 19) | |
930 | (src1_enc << 14); | |
931 | |
932 int disp = disp32; | |
933 int index = src2_enc; | |
934 | |
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
936 disp += STACK_BIAS; | |
937 | |
938 // We should have a compiler bailout here rather than a guarantee. | |
939 // Better yet would be some mechanism to handle variable-size matches correctly. | |
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
941 | |
942 if( disp != 0 ) { | |
943 // use reg-reg form | |
944 // set src2=R_O7 contains offset | |
945 index = R_O7_enc; | |
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); | |
947 } | |
948 instr |= (asi << 5); | |
949 instr |= index; | |
950 uint *code = (uint*)cbuf.code_end(); | |
951 *code = instr; | |
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
953 } | |
954 | |
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
956 // The method which records debug information at every safepoint | |
957 // expects the call to be the first instruction in the snippet as | |
958 // it creates a PcDesc structure which tracks the offset of a call | |
959 // from the start of the codeBlob. This offset is computed as | |
960 // code_end() - code_begin() of the code which has been emitted | |
961 // so far. | |
962 // In this particular case we have skirted around the problem by | |
963 // putting the "mov" instruction in the delay slot but the problem | |
964 // may bite us again at some other point and a cleaner/generic | |
965 // solution using relocations would be needed. | |
966 MacroAssembler _masm(&cbuf); | |
967 __ set_inst_mark(); | |
968 | |
969 // We flush the current window just so that there is a valid stack copy | |
970 // the fact that the current window becomes active again instantly is | |
971 // not a problem there is nothing live in it. | |
972 | |
973 #ifdef ASSERT | |
974 int startpos = __ offset(); | |
975 #endif /* ASSERT */ | |
976 | |
977 #ifdef _LP64 | |
978 // Calls to the runtime or native may not be reachable from compiled code, | |
979 // so we generate the far call sequence on 64 bit sparc. | |
980 // This code sequence is relocatable to any address, even on LP64. | |
981 if ( force_far_call ) { | |
982 __ relocate(rtype); | |
983 Address dest(O7, (address)entry_point); | |
984 __ jumpl_to(dest, O7); | |
985 } | |
986 else | |
987 #endif | |
988 { | |
989 __ call((address)entry_point, rtype); | |
990 } | |
991 | |
992 if (preserve_g2) __ delayed()->mov(G2, L7); | |
993 else __ delayed()->nop(); | |
994 | |
995 if (preserve_g2) __ mov(L7, G2); | |
996 | |
997 #ifdef ASSERT | |
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
999 #ifdef _LP64 | |
1000 // Trash argument dump slots. | |
1001 __ set(0xb0b8ac0db0b8ac0d, G1); | |
1002 __ mov(G1, G5); | |
1003 __ stx(G1, SP, STACK_BIAS + 0x80); | |
1004 __ stx(G1, SP, STACK_BIAS + 0x88); | |
1005 __ stx(G1, SP, STACK_BIAS + 0x90); | |
1006 __ stx(G1, SP, STACK_BIAS + 0x98); | |
1007 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
1008 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
1009 #else // _LP64 | |
1010 // this is also a native call, so smash the first 7 stack locations, | |
1011 // and the various registers | |
1012 | |
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1014 // while [SP+0x44..0x58] are the argument dump slots. | |
1015 __ set((intptr_t)0xbaadf00d, G1); | |
1016 __ mov(G1, G5); | |
1017 __ sllx(G1, 32, G1); | |
1018 __ or3(G1, G5, G1); | |
1019 __ mov(G1, G5); | |
1020 __ stx(G1, SP, 0x40); | |
1021 __ stx(G1, SP, 0x48); | |
1022 __ stx(G1, SP, 0x50); | |
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1024 #endif // _LP64 | |
1025 } | |
1026 #endif /*ASSERT*/ | |
1027 } | |
1028 | |
1029 //============================================================================= | |
1030 // REQUIRED FUNCTIONALITY for encoding | |
1031 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1032 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1033 | |
1034 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) { | |
1035 MacroAssembler _masm(&cbuf); | |
1036 if (ForceRelocatable) { | |
1037 Address addr(reg, (address)val); | |
1038 __ sethi(addr, ForceRelocatable); | |
1039 __ add(addr, reg); | |
1040 } else { | |
1041 __ set(val, reg); | |
1042 } | |
1043 } | |
1044 | |
1045 | |
1046 //============================================================================= | |
1047 | |
1048 #ifndef PRODUCT | |
1049 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1050 Compile* C = ra_->C; | |
1051 | |
1052 for (int i = 0; i < OptoPrologueNops; i++) { | |
1053 st->print_cr("NOP"); st->print("\t"); | |
1054 } | |
1055 | |
1056 if( VerifyThread ) { | |
1057 st->print_cr("Verify_Thread"); st->print("\t"); | |
1058 } | |
1059 | |
1060 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1061 | |
1062 // Calls to C2R adapters often do not accept exceptional returns. | |
1063 // We require that their callers must bang for them. But be careful, because | |
1064 // some VM calls (such as call site linkage) can use several kilobytes of | |
1065 // stack. But the stack safety zone should account for that. | |
1066 // See bugs 4446381, 4468289, 4497237. | |
1067 if (C->need_stack_bang(framesize)) { | |
1068 st->print_cr("! stack bang"); st->print("\t"); | |
1069 } | |
1070 | |
1071 if (Assembler::is_simm13(-framesize)) { | |
1072 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1073 } else { | |
1074 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1075 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1076 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1077 } | |
1078 | |
1079 } | |
1080 #endif | |
1081 | |
1082 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1083 Compile* C = ra_->C; | |
1084 MacroAssembler _masm(&cbuf); | |
1085 | |
1086 for (int i = 0; i < OptoPrologueNops; i++) { | |
1087 __ nop(); | |
1088 } | |
1089 | |
1090 __ verify_thread(); | |
1091 | |
1092 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1093 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1094 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1095 | |
1096 // Calls to C2R adapters often do not accept exceptional returns. | |
1097 // We require that their callers must bang for them. But be careful, because | |
1098 // some VM calls (such as call site linkage) can use several kilobytes of | |
1099 // stack. But the stack safety zone should account for that. | |
1100 // See bugs 4446381, 4468289, 4497237. | |
1101 if (C->need_stack_bang(framesize)) { | |
1102 __ generate_stack_overflow_check(framesize); | |
1103 } | |
1104 | |
1105 if (Assembler::is_simm13(-framesize)) { | |
1106 __ save(SP, -framesize, SP); | |
1107 } else { | |
1108 __ sethi(-framesize & ~0x3ff, G3); | |
1109 __ add(G3, -framesize & 0x3ff, G3); | |
1110 __ save(SP, G3, SP); | |
1111 } | |
1112 C->set_frame_complete( __ offset() ); | |
1113 } | |
1114 | |
1115 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1116 return MachNode::size(ra_); | |
1117 } | |
1118 | |
1119 int MachPrologNode::reloc() const { | |
1120 return 10; // a large enough number | |
1121 } | |
1122 | |
1123 //============================================================================= | |
1124 #ifndef PRODUCT | |
1125 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1126 Compile* C = ra_->C; | |
1127 | |
1128 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1129 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1130 #ifdef _LP64 | |
1131 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1132 #else | |
1133 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1134 #endif | |
1135 } | |
1136 | |
1137 if( do_polling() ) | |
1138 st->print("RET\n\t"); | |
1139 | |
1140 st->print("RESTORE"); | |
1141 } | |
1142 #endif | |
1143 | |
1144 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1145 MacroAssembler _masm(&cbuf); | |
1146 Compile* C = ra_->C; | |
1147 | |
1148 __ verify_thread(); | |
1149 | |
1150 // If this does safepoint polling, then do it here | |
1151 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1152 Address polling_page(L0, (address)os::get_polling_page()); | |
1153 __ sethi(polling_page, false); | |
1154 __ relocate(relocInfo::poll_return_type); | |
1155 __ ld_ptr( L0, 0, G0 ); | |
1156 } | |
1157 | |
1158 // If this is a return, then stuff the restore in the delay slot | |
1159 if( do_polling() ) { | |
1160 __ ret(); | |
1161 __ delayed()->restore(); | |
1162 } else { | |
1163 __ restore(); | |
1164 } | |
1165 } | |
1166 | |
1167 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1168 return MachNode::size(ra_); | |
1169 } | |
1170 | |
1171 int MachEpilogNode::reloc() const { | |
1172 return 16; // a large enough number | |
1173 } | |
1174 | |
1175 const Pipeline * MachEpilogNode::pipeline() const { | |
1176 return MachNode::pipeline_class(); | |
1177 } | |
1178 | |
1179 int MachEpilogNode::safepoint_offset() const { | |
1180 assert( do_polling(), "no return for this epilog node"); | |
1181 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
1182 } | |
1183 | |
1184 //============================================================================= | |
1185 | |
1186 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1187 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1188 static enum RC rc_class( OptoReg::Name reg ) { | |
1189 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1190 if (OptoReg::is_stack(reg)) return rc_stack; | |
1191 VMReg r = OptoReg::as_VMReg(reg); | |
1192 if (r->is_Register()) return rc_int; | |
1193 assert(r->is_FloatRegister(), "must be"); | |
1194 return rc_float; | |
1195 } | |
1196 | |
1197 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1198 if( cbuf ) { | |
1199 // Better yet would be some mechanism to handle variable-size matches correctly | |
1200 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1201 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1202 } else { | |
1203 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1204 } | |
1205 } | |
1206 #ifndef PRODUCT | |
1207 else if( !do_size ) { | |
1208 if( size != 0 ) st->print("\n\t"); | |
1209 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1210 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1211 } | |
1212 #endif | |
1213 return size+4; | |
1214 } | |
1215 | |
1216 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1217 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1218 #ifndef PRODUCT | |
1219 else if( !do_size ) { | |
1220 if( size != 0 ) st->print("\n\t"); | |
1221 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1222 } | |
1223 #endif | |
1224 return size+4; | |
1225 } | |
1226 | |
1227 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1228 PhaseRegAlloc *ra_, | |
1229 bool do_size, | |
1230 outputStream* st ) const { | |
1231 // Get registers to move | |
1232 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1233 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1234 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1235 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1236 | |
1237 enum RC src_second_rc = rc_class(src_second); | |
1238 enum RC src_first_rc = rc_class(src_first); | |
1239 enum RC dst_second_rc = rc_class(dst_second); | |
1240 enum RC dst_first_rc = rc_class(dst_first); | |
1241 | |
1242 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1243 | |
1244 // Generate spill code! | |
1245 int size = 0; | |
1246 | |
1247 if( src_first == dst_first && src_second == dst_second ) | |
1248 return size; // Self copy, no move | |
1249 | |
1250 // -------------------------------------- | |
1251 // Check for mem-mem move. Load into unused float registers and fall into | |
1252 // the float-store case. | |
1253 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1254 int offset = ra_->reg2offset(src_first); | |
1255 // Further check for aligned-adjacent pair, so we can use a double load | |
1256 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1257 src_second = OptoReg::Name(R_F31_num); | |
1258 src_second_rc = rc_float; | |
1259 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1260 } else { | |
1261 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1262 } | |
1263 src_first = OptoReg::Name(R_F30_num); | |
1264 src_first_rc = rc_float; | |
1265 } | |
1266 | |
1267 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1268 int offset = ra_->reg2offset(src_second); | |
1269 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1270 src_second = OptoReg::Name(R_F31_num); | |
1271 src_second_rc = rc_float; | |
1272 } | |
1273 | |
1274 // -------------------------------------- | |
1275 // Check for float->int copy; requires a trip through memory | |
1276 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
1277 int offset = frame::register_save_words*wordSize; | |
1278 if( cbuf ) { | |
1279 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
1280 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1281 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1282 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1283 } | |
1284 #ifndef PRODUCT | |
1285 else if( !do_size ) { | |
1286 if( size != 0 ) st->print("\n\t"); | |
1287 st->print( "SUB R_SP,16,R_SP\n"); | |
1288 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1289 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1290 st->print("\tADD R_SP,16,R_SP\n"); | |
1291 } | |
1292 #endif | |
1293 size += 16; | |
1294 } | |
1295 | |
1296 // -------------------------------------- | |
1297 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1298 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1299 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1300 // there. Misaligned sources only come from native-long-returns (handled | |
1301 // special below). | |
1302 #ifndef _LP64 | |
1303 if( src_first_rc == rc_int && // source is already big-endian | |
1304 src_second_rc != rc_bad && // 64-bit move | |
1305 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1306 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1307 // Do the big-endian flop. | |
1308 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1309 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1310 } | |
1311 #endif | |
1312 | |
1313 // -------------------------------------- | |
1314 // Check for integer reg-reg copy | |
1315 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1316 #ifndef _LP64 | |
1317 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1318 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1319 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1320 // operand contains the least significant word of the 64-bit value and vice versa. | |
1321 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1322 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1323 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1324 if( cbuf ) { | |
1325 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1326 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1327 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1328 #ifndef PRODUCT | |
1329 } else if( !do_size ) { | |
1330 if( size != 0 ) st->print("\n\t"); | |
1331 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1332 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1333 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1334 #endif | |
1335 } | |
1336 return size+12; | |
1337 } | |
1338 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1339 // returning a long value in I0/I1 | |
1340 // a SpillCopy must be able to target a return instruction's reg_class | |
1341 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1342 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1343 // operand contains the least significant word of the 64-bit value and vice versa. | |
1344 OptoReg::Name tdest = dst_first; | |
1345 | |
1346 if (src_first == dst_first) { | |
1347 tdest = OptoReg::Name(R_O7_num); | |
1348 size += 4; | |
1349 } | |
1350 | |
1351 if( cbuf ) { | |
1352 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1353 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1354 // ShrL_reg_imm6 | |
1355 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1356 // ShrR_reg_imm6 src, 0, dst | |
1357 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1358 if (tdest != dst_first) { | |
1359 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1360 } | |
1361 } | |
1362 #ifndef PRODUCT | |
1363 else if( !do_size ) { | |
1364 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1365 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1366 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1367 if (tdest != dst_first) { | |
1368 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1369 } | |
1370 } | |
1371 #endif // PRODUCT | |
1372 return size+8; | |
1373 } | |
1374 #endif // !_LP64 | |
1375 // Else normal reg-reg copy | |
1376 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1377 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1378 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1379 // This moves an aligned adjacent pair. | |
1380 // See if we are done. | |
1381 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1382 return size; | |
1383 } | |
1384 | |
1385 // Check for integer store | |
1386 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1387 int offset = ra_->reg2offset(dst_first); | |
1388 // Further check for aligned-adjacent pair, so we can use a double store | |
1389 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1390 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1391 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1392 } | |
1393 | |
1394 // Check for integer load | |
1395 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1396 int offset = ra_->reg2offset(src_first); | |
1397 // Further check for aligned-adjacent pair, so we can use a double load | |
1398 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1399 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1400 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1401 } | |
1402 | |
1403 // Check for float reg-reg copy | |
1404 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1405 // Further check for aligned-adjacent pair, so we can use a double move | |
1406 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1407 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1408 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1409 } | |
1410 | |
1411 // Check for float store | |
1412 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1413 int offset = ra_->reg2offset(dst_first); | |
1414 // Further check for aligned-adjacent pair, so we can use a double store | |
1415 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1416 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1417 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1418 } | |
1419 | |
1420 // Check for float load | |
1421 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1422 int offset = ra_->reg2offset(src_first); | |
1423 // Further check for aligned-adjacent pair, so we can use a double load | |
1424 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1425 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1426 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1427 } | |
1428 | |
1429 // -------------------------------------------------------------------- | |
1430 // Check for hi bits still needing moving. Only happens for misaligned | |
1431 // arguments to native calls. | |
1432 if( src_second == dst_second ) | |
1433 return size; // Self copy; no move | |
1434 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1435 | |
1436 #ifndef _LP64 | |
1437 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1438 // pairs, so there's never any need to move the high bits separately. |
0 | 1439 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1440 // all sorts of silly alignment problems. | |
1441 | |
1442 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1443 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1444 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1445 // happened already as part of a 64-bit move) | |
1446 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1447 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1448 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1449 // Shift src_second down to dst_second's low bits. | |
1450 if( cbuf ) { | |
1451 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1452 #ifndef PRODUCT | |
1453 } else if( !do_size ) { | |
1454 if( size != 0 ) st->print("\n\t"); | |
1455 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1456 #endif | |
1457 } | |
1458 return size+4; | |
1459 } | |
1460 | |
1461 // Check for high word integer store. Must down-shift the hi bits | |
1462 // into a temp register, then fall into the case of storing int bits. | |
1463 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1464 // Shift src_second down to dst_second's low bits. | |
1465 if( cbuf ) { | |
1466 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1467 #ifndef PRODUCT | |
1468 } else if( !do_size ) { | |
1469 if( size != 0 ) st->print("\n\t"); | |
1470 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1471 #endif | |
1472 } | |
1473 size+=4; | |
1474 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1475 } | |
1476 | |
1477 // Check for high word integer load | |
1478 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1479 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1480 | |
1481 // Check for high word integer store | |
1482 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1483 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1484 | |
1485 // Check for high word float store | |
1486 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1487 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1488 | |
1489 #endif // !_LP64 | |
1490 | |
1491 Unimplemented(); | |
1492 } | |
1493 | |
1494 #ifndef PRODUCT | |
1495 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1496 implementation( NULL, ra_, false, st ); | |
1497 } | |
1498 #endif | |
1499 | |
1500 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1501 implementation( &cbuf, ra_, false, NULL ); | |
1502 } | |
1503 | |
1504 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1505 return implementation( NULL, ra_, true, NULL ); | |
1506 } | |
1507 | |
1508 //============================================================================= | |
1509 #ifndef PRODUCT | |
1510 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1511 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1512 } | |
1513 #endif | |
1514 | |
1515 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1516 MacroAssembler _masm(&cbuf); | |
1517 for(int i = 0; i < _count; i += 1) { | |
1518 __ nop(); | |
1519 } | |
1520 } | |
1521 | |
1522 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1523 return 4 * _count; | |
1524 } | |
1525 | |
1526 | |
1527 //============================================================================= | |
1528 #ifndef PRODUCT | |
1529 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1530 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1531 int reg = ra_->get_reg_first(this); | |
1532 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1533 } | |
1534 #endif | |
1535 | |
1536 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1537 MacroAssembler _masm(&cbuf); | |
1538 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1539 int reg = ra_->get_encode(this); | |
1540 | |
1541 if (Assembler::is_simm13(offset)) { | |
1542 __ add(SP, offset, reg_to_register_object(reg)); | |
1543 } else { | |
1544 __ set(offset, O7); | |
1545 __ add(SP, O7, reg_to_register_object(reg)); | |
1546 } | |
1547 } | |
1548 | |
1549 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1550 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1551 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1552 return ra_->C->scratch_emit_size(this); | |
1553 } | |
1554 | |
1555 //============================================================================= | |
1556 | |
1557 // emit call stub, compiled java to interpretor | |
1558 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1559 | |
1560 // Stub is fixed up when the corresponding call is converted from calling | |
1561 // compiled code to calling interpreted code. | |
1562 // set (empty), G5 | |
1563 // jmp -1 | |
1564 | |
1565 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
1566 | |
1567 MacroAssembler _masm(&cbuf); | |
1568 | |
1569 address base = | |
1570 __ start_a_stub(Compile::MAX_stubs_size); | |
1571 if (base == NULL) return; // CodeBuffer::expand failed | |
1572 | |
1573 // static stub relocation stores the instruction address of the call | |
1574 __ relocate(static_stub_Relocation::spec(mark)); | |
1575 | |
1576 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
1577 | |
1578 __ set_inst_mark(); | |
1579 Address a(G3, (address)-1); | |
1580 __ JUMP(a, 0); | |
1581 | |
1582 __ delayed()->nop(); | |
1583 | |
1584 // Update current stubs pointer and restore code_end. | |
1585 __ end_a_stub(); | |
1586 } | |
1587 | |
1588 // size of call stub, compiled java to interpretor | |
1589 uint size_java_to_interp() { | |
1590 // This doesn't need to be accurate but it must be larger or equal to | |
1591 // the real size of the stub. | |
1592 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1593 NativeJump::instruction_size + // sethi; jmp; nop | |
1594 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1595 } | |
1596 // relocation entries for call stub, compiled java to interpretor | |
1597 uint reloc_java_to_interp() { | |
1598 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1599 } | |
1600 | |
1601 | |
1602 //============================================================================= | |
1603 #ifndef PRODUCT | |
1604 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1605 st->print_cr("\nUEP:"); | |
1606 #ifdef _LP64 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1607 if (UseCompressedOops) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1608 assert(Universe::heap() != NULL, "java heap should be initialized"); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1609 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1610 st->print_cr("\tSLL R_G5,3,R_G5"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1611 if (Universe::narrow_oop_base() != NULL) |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1612 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1613 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1614 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1615 } |
0 | 1616 st->print_cr("\tCMP R_G5,R_G3" ); |
1617 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1618 #else // _LP64 | |
1619 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1620 st->print_cr("\tCMP R_G5,R_G3" ); | |
1621 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1622 #endif // _LP64 | |
1623 } | |
1624 #endif | |
1625 | |
1626 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1627 MacroAssembler _masm(&cbuf); | |
1628 Label L; | |
1629 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1630 Register temp_reg = G3; | |
1631 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1632 | |
605 | 1633 // Load klass from receiver |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1634 __ load_klass(O0, temp_reg); |
0 | 1635 // Compare against expected klass |
1636 __ cmp(temp_reg, G5_ic_reg); | |
1637 // Branch to miss code, checks xcc or icc depending | |
1638 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1639 } | |
1640 | |
1641 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1642 return MachNode::size(ra_); | |
1643 } | |
1644 | |
1645 | |
1646 //============================================================================= | |
1647 | |
1648 uint size_exception_handler() { | |
1649 if (TraceJumps) { | |
1650 return (400); // just a guess | |
1651 } | |
1652 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1653 } | |
1654 | |
1655 uint size_deopt_handler() { | |
1656 if (TraceJumps) { | |
1657 return (400); // just a guess | |
1658 } | |
1659 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1660 } | |
1661 | |
1662 // Emit exception handler code. | |
1663 int emit_exception_handler(CodeBuffer& cbuf) { | |
1664 Register temp_reg = G3; | |
1665 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin()); | |
1666 MacroAssembler _masm(&cbuf); | |
1667 | |
1668 address base = | |
1669 __ start_a_stub(size_exception_handler()); | |
1670 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1671 | |
1672 int offset = __ offset(); | |
1673 | |
1674 __ JUMP(exception_blob, 0); // sethi;jmp | |
1675 __ delayed()->nop(); | |
1676 | |
1677 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1678 | |
1679 __ end_a_stub(); | |
1680 | |
1681 return offset; | |
1682 } | |
1683 | |
1684 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1685 // Can't use any of the current frame's registers as we may have deopted | |
1686 // at a poll and everything (including G3) can be live. | |
1687 Register temp_reg = L0; | |
1688 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack()); | |
1689 MacroAssembler _masm(&cbuf); | |
1690 | |
1691 address base = | |
1692 __ start_a_stub(size_deopt_handler()); | |
1693 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1694 | |
1695 int offset = __ offset(); | |
1696 __ save_frame(0); | |
1697 __ JUMP(deopt_blob, 0); // sethi;jmp | |
1698 __ delayed()->restore(); | |
1699 | |
1700 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1701 | |
1702 __ end_a_stub(); | |
1703 return offset; | |
1704 | |
1705 } | |
1706 | |
1707 // Given a register encoding, produce a Integer Register object | |
1708 static Register reg_to_register_object(int register_encoding) { | |
1709 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1710 return as_Register(register_encoding); | |
1711 } | |
1712 | |
1713 // Given a register encoding, produce a single-precision Float Register object | |
1714 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1715 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1716 return as_SingleFloatRegister(register_encoding); | |
1717 } | |
1718 | |
1719 // Given a register encoding, produce a double-precision Float Register object | |
1720 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1721 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1722 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1723 return as_DoubleFloatRegister(register_encoding); | |
1724 } | |
1725 | |
1726 int Matcher::regnum_to_fpu_offset(int regnum) { | |
1727 return regnum - 32; // The FP registers are in the second chunk | |
1728 } | |
1729 | |
1730 #ifdef ASSERT | |
1731 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1732 #endif | |
1733 | |
1734 // Vector width in bytes | |
1735 const uint Matcher::vector_width_in_bytes(void) { | |
1736 return 8; | |
1737 } | |
1738 | |
1739 // Vector ideal reg | |
1740 const uint Matcher::vector_ideal_reg(void) { | |
1741 return Op_RegD; | |
1742 } | |
1743 | |
1744 // USII supports fxtof through the whole range of number, USIII doesn't | |
1745 const bool Matcher::convL2FSupported(void) { | |
1746 return VM_Version::has_fast_fxtof(); | |
1747 } | |
1748 | |
1749 // Is this branch offset short enough that a short branch can be used? | |
1750 // | |
1751 // NOTE: If the platform does not provide any short branch variants, then | |
1752 // this method should return false for offset 0. | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1753 bool Matcher::is_short_branch_offset(int rule, int offset) { |
0 | 1754 return false; |
1755 } | |
1756 | |
1757 const bool Matcher::isSimpleConstant64(jlong value) { | |
1758 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1759 // Depends on optimizations in MacroAssembler::setx. | |
1760 int hi = (int)(value >> 32); | |
1761 int lo = (int)(value & ~0); | |
1762 return (hi == 0) || (hi == -1) || (lo == 0); | |
1763 } | |
1764 | |
1765 // No scaling for the parameter the ClearArray node. | |
1766 const bool Matcher::init_array_count_is_in_bytes = true; | |
1767 | |
1768 // Threshold size for cleararray. | |
1769 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1770 | |
1771 // Should the Matcher clone shifts on addressing modes, expecting them to | |
1772 // be subsumed into complex addressing expressions or compute them into | |
1773 // registers? True for Intel but false for most RISCs | |
1774 const bool Matcher::clone_shift_expressions = false; | |
1775 | |
1776 // Is it better to copy float constants, or load them directly from memory? | |
1777 // Intel can load a float constant from a direct address, requiring no | |
1778 // extra registers. Most RISCs will have to materialize an address into a | |
1779 // register first, so they would do better to copy the constant from stack. | |
1780 const bool Matcher::rematerialize_float_constants = false; | |
1781 | |
1782 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1783 // needed. Else we split the double into 2 integer pieces and move it | |
1784 // piece-by-piece. Only happens when passing doubles into C code as the | |
1785 // Java calling convention forces doubles to be aligned. | |
1786 #ifdef _LP64 | |
1787 const bool Matcher::misaligned_doubles_ok = true; | |
1788 #else | |
1789 const bool Matcher::misaligned_doubles_ok = false; | |
1790 #endif | |
1791 | |
1792 // No-op on SPARC. | |
1793 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1794 } | |
1795 | |
1796 // Advertise here if the CPU requires explicit rounding operations | |
1797 // to implement the UseStrictFP mode. | |
1798 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1799 | |
1800 // Do floats take an entire double register or just half? | |
1801 const bool Matcher::float_in_double = false; | |
1802 | |
1803 // Do ints take an entire long register or just half? | |
1804 // Note that we if-def off of _LP64. | |
1805 // The relevant question is how the int is callee-saved. In _LP64 | |
1806 // the whole long is written but de-opt'ing will have to extract | |
1807 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1808 #ifdef _LP64 | |
1809 const bool Matcher::int_in_long = true; | |
1810 #else | |
1811 const bool Matcher::int_in_long = false; | |
1812 #endif | |
1813 | |
1814 // Return whether or not this register is ever used as an argument. This | |
1815 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1816 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1817 // arguments in those registers not be available to the callee. | |
1818 bool Matcher::can_be_java_arg( int reg ) { | |
1819 // Standard sparc 6 args in registers | |
1820 if( reg == R_I0_num || | |
1821 reg == R_I1_num || | |
1822 reg == R_I2_num || | |
1823 reg == R_I3_num || | |
1824 reg == R_I4_num || | |
1825 reg == R_I5_num ) return true; | |
1826 #ifdef _LP64 | |
1827 // 64-bit builds can pass 64-bit pointers and longs in | |
1828 // the high I registers | |
1829 if( reg == R_I0H_num || | |
1830 reg == R_I1H_num || | |
1831 reg == R_I2H_num || | |
1832 reg == R_I3H_num || | |
1833 reg == R_I4H_num || | |
1834 reg == R_I5H_num ) return true; | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1835 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1836 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1837 return true; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1838 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
1839 |
0 | 1840 #else |
1841 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1842 // Longs cannot be passed in O regs, because O regs become I regs | |
1843 // after a 'save' and I regs get their high bits chopped off on | |
1844 // interrupt. | |
1845 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1846 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1847 #endif | |
1848 // A few float args in registers | |
1849 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1850 | |
1851 return false; | |
1852 } | |
1853 | |
1854 bool Matcher::is_spillable_arg( int reg ) { | |
1855 return can_be_java_arg(reg); | |
1856 } | |
1857 | |
1858 // Register for DIVI projection of divmodI | |
1859 RegMask Matcher::divI_proj_mask() { | |
1860 ShouldNotReachHere(); | |
1861 return RegMask(); | |
1862 } | |
1863 | |
1864 // Register for MODI projection of divmodI | |
1865 RegMask Matcher::modI_proj_mask() { | |
1866 ShouldNotReachHere(); | |
1867 return RegMask(); | |
1868 } | |
1869 | |
1870 // Register for DIVL projection of divmodL | |
1871 RegMask Matcher::divL_proj_mask() { | |
1872 ShouldNotReachHere(); | |
1873 return RegMask(); | |
1874 } | |
1875 | |
1876 // Register for MODL projection of divmodL | |
1877 RegMask Matcher::modL_proj_mask() { | |
1878 ShouldNotReachHere(); | |
1879 return RegMask(); | |
1880 } | |
1881 | |
1882 %} | |
1883 | |
1884 | |
1885 // The intptr_t operand types, defined by textual substitution. | |
1886 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
1887 #ifdef _LP64 | |
1888 #define immX immL | |
1889 #define immX13 immL13 | |
1890 #define iRegX iRegL | |
1891 #define g1RegX g1RegL | |
1892 #else | |
1893 #define immX immI | |
1894 #define immX13 immI13 | |
1895 #define iRegX iRegI | |
1896 #define g1RegX g1RegI | |
1897 #endif | |
1898 | |
1899 //----------ENCODING BLOCK----------------------------------------------------- | |
1900 // This block specifies the encoding classes used by the compiler to output | |
1901 // byte streams. Encoding classes are parameterized macros used by | |
1902 // Machine Instruction Nodes in order to generate the bit encoding of the | |
1903 // instruction. Operands specify their base encoding interface with the | |
1904 // interface keyword. There are currently supported four interfaces, | |
1905 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
1906 // operand to generate a function which returns its register number when | |
1907 // queried. CONST_INTER causes an operand to generate a function which | |
1908 // returns the value of the constant when queried. MEMORY_INTER causes an | |
1909 // operand to generate four functions which return the Base Register, the | |
1910 // Index Register, the Scale Value, and the Offset Value of the operand when | |
1911 // queried. COND_INTER causes an operand to generate six functions which | |
1912 // return the encoding code (ie - encoding bits for the instruction) | |
1913 // associated with each basic boolean condition for a conditional instruction. | |
1914 // | |
1915 // Instructions specify two basic values for encoding. Again, a function | |
1916 // is available to check if the constant displacement is an oop. They use the | |
1917 // ins_encode keyword to specify their encoding classes (which must be | |
1918 // a sequence of enc_class names, and their parameters, specified in | |
1919 // the encoding block), and they use the | |
1920 // opcode keyword to specify, in order, their primary, secondary, and | |
1921 // tertiary opcode. Only the opcode sections which a particular instruction | |
1922 // needs for encoding need to be specified. | |
1923 encode %{ | |
1924 enc_class enc_untested %{ | |
1925 #ifdef ASSERT | |
1926 MacroAssembler _masm(&cbuf); | |
1927 __ untested("encoding"); | |
1928 #endif | |
1929 %} | |
1930 | |
1931 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
1932 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
1933 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
1934 %} | |
1935 | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1936 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1937 emit_form3_mem_reg(cbuf, this, $primary, -1, |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1938 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1939 %} |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1940 |
0 | 1941 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1942 emit_form3_mem_reg_asi(cbuf, this, $primary, -1, |
0 | 1943 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); |
1944 %} | |
1945 | |
1946 enc_class form3_mem_prefetch_read( memory mem ) %{ | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1947 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1948 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
1949 %} | |
1950 | |
1951 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1952 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1953 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
1954 %} | |
1955 | |
1956 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
1957 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1958 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1959 guarantee($mem$$index == R_G0_enc, "double index?"); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 1962 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
1963 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
1964 %} | |
1965 | |
1966 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
1967 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1968 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1969 guarantee($mem$$index == R_G0_enc, "double index?"); | |
1970 // Load long with 2 instructions | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1971 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1972 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 1973 %} |
1974 | |
1975 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
1976 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
1977 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 1979 %} |
1980 | |
1981 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
1982 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1983 if( $rs2$$reg != $rd$$reg ) | |
1984 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1985 %} | |
1986 | |
1987 // Target lo half of long | |
1988 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
1989 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1990 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
1991 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1992 %} | |
1993 | |
1994 // Source lo half of long | |
1995 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
1996 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1997 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
1999 %} | |
2000 | |
2001 // Target hi half of long | |
2002 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2003 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2004 %} | |
2005 | |
2006 // Source lo half of long, and leave it sign extended. | |
2007 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2008 // Sign extend low half | |
2009 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2010 %} | |
2011 | |
2012 // Source hi half of long, and leave it sign extended. | |
2013 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2014 // Shift high half to low half | |
2015 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2016 %} | |
2017 | |
2018 // Source hi half of long | |
2019 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2020 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2021 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2022 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2023 %} | |
2024 | |
2025 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2026 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2027 %} | |
2028 | |
2029 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2030 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2031 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2032 %} | |
2033 | |
2034 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2035 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2036 // clear if nothing else is happening | |
2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2038 // blt,a,pn done | |
2039 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2040 // mov dst,-1 in delay slot | |
2041 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2042 %} | |
2043 | |
2044 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2045 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2046 %} | |
2047 | |
2048 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2049 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2050 %} | |
2051 | |
2052 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2053 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2054 %} | |
2055 | |
2056 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2057 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2058 %} | |
2059 | |
2060 enc_class move_return_pc_to_o1() %{ | |
2061 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2062 %} | |
2063 | |
2064 #ifdef _LP64 | |
2065 /* %%% merge with enc_to_bool */ | |
2066 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2067 MacroAssembler _masm(&cbuf); | |
2068 | |
2069 Register src_reg = reg_to_register_object($src$$reg); | |
2070 Register dst_reg = reg_to_register_object($dst$$reg); | |
2071 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2072 %} | |
2073 #endif | |
2074 | |
2075 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2076 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2077 MacroAssembler _masm(&cbuf); | |
2078 | |
2079 Register p_reg = reg_to_register_object($p$$reg); | |
2080 Register q_reg = reg_to_register_object($q$$reg); | |
2081 Register y_reg = reg_to_register_object($y$$reg); | |
2082 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2083 | |
2084 __ subcc( p_reg, q_reg, p_reg ); | |
2085 __ add ( p_reg, y_reg, tmp_reg ); | |
2086 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2087 %} | |
2088 | |
2089 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2090 // fcmp %fcc0,$src,$src | |
2091 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2092 // branch %fcc0 not-nan, predict taken | |
2093 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2094 // fdtoi $src,$dst | |
2095 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2096 // fitos $dst,$dst (if nan) | |
2097 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2098 // clear $dst (if nan) | |
2099 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2100 // carry on here... | |
2101 %} | |
2102 | |
2103 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2104 // fcmp %fcc0,$src,$src check for NAN | |
2105 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2106 // branch %fcc0 not-nan, predict taken | |
2107 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2108 // fdtox $src,$dst convert in delay slot | |
2109 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2110 // fxtod $dst,$dst (if nan) | |
2111 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2112 // clear $dst (if nan) | |
2113 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2114 // carry on here... | |
2115 %} | |
2116 | |
2117 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2118 // fcmps %fcc0,$src,$src | |
2119 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2120 // branch %fcc0 not-nan, predict taken | |
2121 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2122 // fstoi $src,$dst | |
2123 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2124 // fitos $dst,$dst (if nan) | |
2125 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2126 // clear $dst (if nan) | |
2127 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2128 // carry on here... | |
2129 %} | |
2130 | |
2131 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2132 // fcmps %fcc0,$src,$src | |
2133 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2134 // branch %fcc0 not-nan, predict taken | |
2135 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2136 // fstox $src,$dst | |
2137 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2138 // fxtod $dst,$dst (if nan) | |
2139 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2140 // clear $dst (if nan) | |
2141 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2142 // carry on here... | |
2143 %} | |
2144 | |
2145 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2146 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2147 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2148 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2149 | |
2150 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2151 | |
2152 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2153 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2154 | |
2155 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2156 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2157 %} | |
2158 | |
2159 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2160 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2161 %} | |
2162 | |
2163 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2164 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2165 %} | |
2166 | |
2167 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2168 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2169 %} | |
2170 | |
2171 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2172 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2173 %} | |
2174 | |
2175 // Encloding class for traceable jumps | |
2176 enc_class form_jmpl(g3RegP dest) %{ | |
2177 emit_jmpl(cbuf, $dest$$reg); | |
2178 %} | |
2179 | |
2180 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2181 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2182 %} | |
2183 | |
2184 enc_class form2_nop() %{ | |
2185 emit_nop(cbuf); | |
2186 %} | |
2187 | |
2188 enc_class form2_illtrap() %{ | |
2189 emit_illtrap(cbuf); | |
2190 %} | |
2191 | |
2192 | |
2193 // Compare longs and convert into -1, 0, 1. | |
2194 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2195 // CMP $src1,$src2 | |
2196 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2197 // blt,a,pn done | |
2198 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2199 // mov dst,-1 in delay slot | |
2200 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2201 // bgt,a,pn done | |
2202 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2203 // mov dst,1 in delay slot | |
2204 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2205 // CLR $dst | |
2206 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2207 %} | |
2208 | |
2209 enc_class enc_PartialSubtypeCheck() %{ | |
2210 MacroAssembler _masm(&cbuf); | |
2211 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2212 __ delayed()->nop(); | |
2213 %} | |
2214 | |
2215 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
2216 MacroAssembler _masm(&cbuf); | |
2217 Label &L = *($labl$$label); | |
2218 Assembler::Predict predict_taken = | |
2219 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2220 | |
2221 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
2222 __ delayed()->nop(); | |
2223 %} | |
2224 | |
2225 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
2226 MacroAssembler _masm(&cbuf); | |
2227 Label &L = *($labl$$label); | |
2228 Assembler::Predict predict_taken = | |
2229 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2230 | |
2231 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
2232 __ delayed()->nop(); | |
2233 %} | |
2234 | |
2235 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
2236 MacroAssembler _masm(&cbuf); | |
2237 Label &L = *($labl$$label); | |
2238 Assembler::Predict predict_taken = | |
2239 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2240 | |
2241 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
2242 __ delayed()->nop(); | |
2243 %} | |
2244 | |
2245 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
2246 MacroAssembler _masm(&cbuf); | |
2247 Label &L = *($labl$$label); | |
2248 Assembler::Predict predict_taken = | |
2249 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2250 | |
2251 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
2252 __ delayed()->nop(); | |
2253 %} | |
2254 | |
2255 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
2256 MacroAssembler _masm(&cbuf); | |
2257 | |
2258 Register switch_reg = as_Register($switch_val$$reg); | |
2259 Register table_reg = O7; | |
2260 | |
2261 address table_base = __ address_table_constant(_index2label); | |
2262 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
2263 | |
2264 // Load table address | |
2265 Address the_pc(table_reg, table_base, rspec); | |
2266 __ load_address(the_pc); | |
2267 | |
2268 // Jump to base address + switch value | |
2269 __ ld_ptr(table_reg, switch_reg, table_reg); | |
2270 __ jmp(table_reg, G0); | |
2271 __ delayed()->nop(); | |
2272 | |
2273 %} | |
2274 | |
2275 enc_class enc_ba( Label labl ) %{ | |
2276 MacroAssembler _masm(&cbuf); | |
2277 Label &L = *($labl$$label); | |
2278 __ ba(false, L); | |
2279 __ delayed()->nop(); | |
2280 %} | |
2281 | |
2282 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
2283 MacroAssembler _masm(&cbuf); | |
2284 Label &L = *$labl$$label; | |
2285 Assembler::Predict predict_taken = | |
2286 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2287 | |
2288 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
2289 __ delayed()->nop(); | |
2290 %} | |
2291 | |
2292 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2293 int op = (Assembler::arith_op << 30) | | |
2294 ($dst$$reg << 25) | | |
2295 (Assembler::movcc_op3 << 19) | | |
2296 (1 << 18) | // cc2 bit for 'icc' | |
2297 ($cmp$$cmpcode << 14) | | |
2298 (0 << 13) | // select register move | |
2299 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2300 ($src$$reg << 0); | |
2301 *((int*)(cbuf.code_end())) = op; | |
2302 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2303 %} | |
2304 | |
2305 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2306 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2307 int op = (Assembler::arith_op << 30) | | |
2308 ($dst$$reg << 25) | | |
2309 (Assembler::movcc_op3 << 19) | | |
2310 (1 << 18) | // cc2 bit for 'icc' | |
2311 ($cmp$$cmpcode << 14) | | |
2312 (1 << 13) | // select immediate move | |
2313 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2314 (simm11 << 0); | |
2315 *((int*)(cbuf.code_end())) = op; | |
2316 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2317 %} | |
2318 | |
2319 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2320 int op = (Assembler::arith_op << 30) | | |
2321 ($dst$$reg << 25) | | |
2322 (Assembler::movcc_op3 << 19) | | |
2323 (0 << 18) | // cc2 bit for 'fccX' | |
2324 ($cmp$$cmpcode << 14) | | |
2325 (0 << 13) | // select register move | |
2326 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2327 ($src$$reg << 0); | |
2328 *((int*)(cbuf.code_end())) = op; | |
2329 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2330 %} | |
2331 | |
2332 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2333 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2334 int op = (Assembler::arith_op << 30) | | |
2335 ($dst$$reg << 25) | | |
2336 (Assembler::movcc_op3 << 19) | | |
2337 (0 << 18) | // cc2 bit for 'fccX' | |
2338 ($cmp$$cmpcode << 14) | | |
2339 (1 << 13) | // select immediate move | |
2340 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2341 (simm11 << 0); | |
2342 *((int*)(cbuf.code_end())) = op; | |
2343 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2344 %} | |
2345 | |
2346 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2347 int op = (Assembler::arith_op << 30) | | |
2348 ($dst$$reg << 25) | | |
2349 (Assembler::fpop2_op3 << 19) | | |
2350 (0 << 18) | | |
2351 ($cmp$$cmpcode << 14) | | |
2352 (1 << 13) | // select register move | |
2353 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2354 ($primary << 5) | // select single, double or quad | |
2355 ($src$$reg << 0); | |
2356 *((int*)(cbuf.code_end())) = op; | |
2357 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2358 %} | |
2359 | |
2360 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2361 int op = (Assembler::arith_op << 30) | | |
2362 ($dst$$reg << 25) | | |
2363 (Assembler::fpop2_op3 << 19) | | |
2364 (0 << 18) | | |
2365 ($cmp$$cmpcode << 14) | | |
2366 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2367 ($primary << 5) | // select single, double or quad | |
2368 ($src$$reg << 0); | |
2369 *((int*)(cbuf.code_end())) = op; | |
2370 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2371 %} | |
2372 | |
2373 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2374 // the condition comes from opcode-field instead of an argument. | |
2375 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2376 int op = (Assembler::arith_op << 30) | | |
2377 ($dst$$reg << 25) | | |
2378 (Assembler::movcc_op3 << 19) | | |
2379 (1 << 18) | // cc2 bit for 'icc' | |
2380 ($primary << 14) | | |
2381 (0 << 13) | // select register move | |
2382 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2383 ($src$$reg << 0); | |
2384 *((int*)(cbuf.code_end())) = op; | |
2385 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2386 %} | |
2387 | |
2388 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2389 int op = (Assembler::arith_op << 30) | | |
2390 ($dst$$reg << 25) | | |
2391 (Assembler::movcc_op3 << 19) | | |
2392 (6 << 16) | // cc2 bit for 'xcc' | |
2393 ($primary << 14) | | |
2394 (0 << 13) | // select register move | |
2395 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2396 ($src$$reg << 0); | |
2397 *((int*)(cbuf.code_end())) = op; | |
2398 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2399 %} | |
2400 | |
2401 // Utility encoding for loading a 64 bit Pointer into a register | |
2402 // The 64 bit pointer is stored in the generated code stream | |
2403 enc_class SetPtr( immP src, iRegP rd ) %{ | |
2404 Register dest = reg_to_register_object($rd$$reg); | |
2405 // [RGV] This next line should be generated from ADLC | |
2406 if ( _opnds[1]->constant_is_oop() ) { | |
2407 intptr_t val = $src$$constant; | |
2408 MacroAssembler _masm(&cbuf); | |
2409 __ set_oop_constant((jobject)val, dest); | |
2410 } else { // non-oop pointers, e.g. card mark base, heap top | |
2411 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false); | |
2412 } | |
2413 %} | |
2414 | |
2415 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2416 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2417 %} | |
2418 | |
2419 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2420 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2421 %} | |
2422 | |
2423 enc_class Set32( immI src, iRegI rd ) %{ | |
2424 MacroAssembler _masm(&cbuf); | |
2425 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2426 %} | |
2427 | |
2428 enc_class SetNull( iRegI rd ) %{ | |
2429 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
2430 %} | |
2431 | |
2432 enc_class call_epilog %{ | |
2433 if( VerifyStackAtCalls ) { | |
2434 MacroAssembler _masm(&cbuf); | |
2435 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2436 Register temp_reg = G3; | |
2437 __ add(SP, framesize, temp_reg); | |
2438 __ cmp(temp_reg, FP); | |
2439 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2440 } | |
2441 %} | |
2442 | |
2443 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2444 // to G1 so the register allocator will not have to deal with the misaligned register | |
2445 // pair. | |
2446 enc_class adjust_long_from_native_call %{ | |
2447 #ifndef _LP64 | |
2448 if (returns_long()) { | |
2449 // sllx O0,32,O0 | |
2450 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2451 // srl O1,0,O1 | |
2452 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2453 // or O0,O1,G1 | |
2454 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2455 } | |
2456 #endif | |
2457 %} | |
2458 | |
2459 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2460 // CALL directly to the runtime | |
2461 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2463 /*preserve_g2=*/true, /*force far call*/true); | |
2464 %} | |
2465 | |
2466 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
2467 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2468 // who we intended to call. | |
2469 if ( !_method ) { | |
2470 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2471 } else if (_optimized_virtual) { | |
2472 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2473 } else { | |
2474 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2475 } | |
2476 if( _method ) { // Emit stub for static call | |
2477 emit_java_to_interp(cbuf); | |
2478 } | |
2479 %} | |
2480 | |
2481 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2482 MacroAssembler _masm(&cbuf); | |
2483 __ set_inst_mark(); | |
2484 int vtable_index = this->_vtable_index; | |
2485 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2486 if (vtable_index < 0) { | |
2487 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
2488 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
2489 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2490 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2491 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
2492 // !!!!! | |
2493 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
2494 // emit_call_dynamic_prologue( cbuf ); | |
2495 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
2496 | |
2497 address virtual_call_oop_addr = __ inst_mark(); | |
2498 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2499 // who we intended to call. | |
2500 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
2501 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
2502 } else { | |
2503 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2504 // Just go thru the vtable | |
2505 // get receiver klass (receiver already checked for non-null) | |
2506 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2507 int off = __ offset(); | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2508 __ load_klass(O0, G3_scratch); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2509 int klass_load_size; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2510 if (UseCompressedOops) { |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2511 assert(Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2512 if (Universe::narrow_oop_base() == NULL) |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2513 klass_load_size = 2*BytesPerInstWord; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2514 else |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
2515 klass_load_size = 3*BytesPerInstWord; |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2516 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2517 klass_load_size = 1*BytesPerInstWord; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2518 } |
0 | 2519 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2520 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
2521 if( __ is_simm13(v_off) ) { | |
2522 __ ld_ptr(G3, v_off, G5_method); | |
2523 } else { | |
2524 // Generate 2 instructions | |
2525 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2526 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2527 // ld_ptr, set_hi, set | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2528 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2529 "Unexpected instruction size(s)"); |
0 | 2530 __ ld_ptr(G3, G5_method, G5_method); |
2531 } | |
2532 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2533 // However it may very well end up in handle_wrong_method if the | |
2534 // method is abstract for the particular class. | |
2535 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
2536 // jump to target (either compiled code or c2iadapter) | |
2537 __ jmpl(G3_scratch, G0, O7); | |
2538 __ delayed()->nop(); | |
2539 } | |
2540 %} | |
2541 | |
2542 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2543 MacroAssembler _masm(&cbuf); | |
2544 | |
2545 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2546 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2547 // we might be calling a C2I adapter which needs it. | |
2548 | |
2549 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2550 // Load nmethod | |
2551 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
2552 | |
2553 // CALL to compiled java, indirect the contents of G3 | |
2554 __ set_inst_mark(); | |
2555 __ callr(temp_reg, G0); | |
2556 __ delayed()->nop(); | |
2557 %} | |
2558 | |
2559 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2560 MacroAssembler _masm(&cbuf); | |
2561 Register Rdividend = reg_to_register_object($src1$$reg); | |
2562 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2563 Register Rresult = reg_to_register_object($dst$$reg); | |
2564 | |
2565 __ sra(Rdivisor, 0, Rdivisor); | |
2566 __ sra(Rdividend, 0, Rdividend); | |
2567 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2568 %} | |
2569 | |
2570 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2571 MacroAssembler _masm(&cbuf); | |
2572 | |
2573 Register Rdividend = reg_to_register_object($src1$$reg); | |
2574 int divisor = $imm$$constant; | |
2575 Register Rresult = reg_to_register_object($dst$$reg); | |
2576 | |
2577 __ sra(Rdividend, 0, Rdividend); | |
2578 __ sdivx(Rdividend, divisor, Rresult); | |
2579 %} | |
2580 | |
2581 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2582 MacroAssembler _masm(&cbuf); | |
2583 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2584 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2585 Register Rdst = reg_to_register_object($dst$$reg); | |
2586 | |
2587 __ sra( Rsrc1, 0, Rsrc1 ); | |
2588 __ sra( Rsrc2, 0, Rsrc2 ); | |
2589 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2590 __ srlx( Rdst, 32, Rdst ); | |
2591 %} | |
2592 | |
2593 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2594 MacroAssembler _masm(&cbuf); | |
2595 Register Rdividend = reg_to_register_object($src1$$reg); | |
2596 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2597 Register Rresult = reg_to_register_object($dst$$reg); | |
2598 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2599 | |
2600 assert(Rdividend != Rscratch, ""); | |
2601 assert(Rdivisor != Rscratch, ""); | |
2602 | |
2603 __ sra(Rdividend, 0, Rdividend); | |
2604 __ sra(Rdivisor, 0, Rdivisor); | |
2605 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2606 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2607 __ sub(Rdividend, Rscratch, Rresult); | |
2608 %} | |
2609 | |
2610 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2611 MacroAssembler _masm(&cbuf); | |
2612 | |
2613 Register Rdividend = reg_to_register_object($src1$$reg); | |
2614 int divisor = $imm$$constant; | |
2615 Register Rresult = reg_to_register_object($dst$$reg); | |
2616 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2617 | |
2618 assert(Rdividend != Rscratch, ""); | |
2619 | |
2620 __ sra(Rdividend, 0, Rdividend); | |
2621 __ sdivx(Rdividend, divisor, Rscratch); | |
2622 __ mulx(Rscratch, divisor, Rscratch); | |
2623 __ sub(Rdividend, Rscratch, Rresult); | |
2624 %} | |
2625 | |
2626 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2627 MacroAssembler _masm(&cbuf); | |
2628 | |
2629 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2630 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2631 | |
2632 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2633 %} | |
2634 | |
2635 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2636 MacroAssembler _masm(&cbuf); | |
2637 | |
2638 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2639 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2640 | |
2641 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2642 %} | |
2643 | |
2644 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2645 MacroAssembler _masm(&cbuf); | |
2646 | |
2647 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2648 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2649 | |
2650 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2651 %} | |
2652 | |
2653 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2654 MacroAssembler _masm(&cbuf); | |
2655 | |
2656 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2657 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2658 | |
2659 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2660 %} | |
2661 | |
2662 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2663 MacroAssembler _masm(&cbuf); | |
2664 | |
2665 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2666 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2667 | |
2668 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2669 %} | |
2670 | |
2671 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2672 MacroAssembler _masm(&cbuf); | |
2673 | |
2674 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2675 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2676 | |
2677 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2678 %} | |
2679 | |
2680 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2681 MacroAssembler _masm(&cbuf); | |
2682 | |
2683 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2684 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2685 | |
2686 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2687 %} | |
2688 | |
2689 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2690 MacroAssembler _masm(&cbuf); | |
2691 | |
2692 Register Roop = reg_to_register_object($oop$$reg); | |
2693 Register Rbox = reg_to_register_object($box$$reg); | |
2694 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2695 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2696 | |
2697 assert(Roop != Rscratch, ""); | |
2698 assert(Roop != Rmark, ""); | |
2699 assert(Rbox != Rscratch, ""); | |
2700 assert(Rbox != Rmark, ""); | |
2701 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2702 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2703 %} |
2704 | |
2705 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2706 MacroAssembler _masm(&cbuf); | |
2707 | |
2708 Register Roop = reg_to_register_object($oop$$reg); | |
2709 Register Rbox = reg_to_register_object($box$$reg); | |
2710 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2711 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2712 | |
2713 assert(Roop != Rscratch, ""); | |
2714 assert(Roop != Rmark, ""); | |
2715 assert(Rbox != Rscratch, ""); | |
2716 assert(Rbox != Rmark, ""); | |
2717 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2718 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2719 %} |
2720 | |
2721 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2722 MacroAssembler _masm(&cbuf); | |
2723 Register Rmem = reg_to_register_object($mem$$reg); | |
2724 Register Rold = reg_to_register_object($old$$reg); | |
2725 Register Rnew = reg_to_register_object($new$$reg); | |
2726 | |
2727 // casx_under_lock picks 1 of 3 encodings: | |
2728 // For 32-bit pointers you get a 32-bit CAS | |
2729 // For 64-bit pointers you get a 64-bit CASX | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
2730 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2731 __ cmp( Rold, Rnew ); |
2732 %} | |
2733 | |
2734 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2735 Register Rmem = reg_to_register_object($mem$$reg); | |
2736 Register Rold = reg_to_register_object($old$$reg); | |
2737 Register Rnew = reg_to_register_object($new$$reg); | |
2738 | |
2739 MacroAssembler _masm(&cbuf); | |
2740 __ mov(Rnew, O7); | |
2741 __ casx(Rmem, Rold, O7); | |
2742 __ cmp( Rold, O7 ); | |
2743 %} | |
2744 | |
2745 // raw int cas, used for compareAndSwap | |
2746 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2747 Register Rmem = reg_to_register_object($mem$$reg); | |
2748 Register Rold = reg_to_register_object($old$$reg); | |
2749 Register Rnew = reg_to_register_object($new$$reg); | |
2750 | |
2751 MacroAssembler _masm(&cbuf); | |
2752 __ mov(Rnew, O7); | |
2753 __ cas(Rmem, Rold, O7); | |
2754 __ cmp( Rold, O7 ); | |
2755 %} | |
2756 | |
2757 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2758 Register Rres = reg_to_register_object($res$$reg); | |
2759 | |
2760 MacroAssembler _masm(&cbuf); | |
2761 __ mov(1, Rres); | |
2762 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2763 %} | |
2764 | |
2765 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2766 Register Rres = reg_to_register_object($res$$reg); | |
2767 | |
2768 MacroAssembler _masm(&cbuf); | |
2769 __ mov(1, Rres); | |
2770 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2771 %} | |
2772 | |
2773 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2774 MacroAssembler _masm(&cbuf); | |
2775 Register Rdst = reg_to_register_object($dst$$reg); | |
2776 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2777 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2778 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2779 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2780 | |
2781 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2782 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2783 %} | |
2784 | |
2785 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
2786 MacroAssembler _masm(&cbuf); | |
2787 Register dest = reg_to_register_object($dst$$reg); | |
2788 Register temp = reg_to_register_object($tmp$$reg); | |
2789 __ set64( $src$$constant, dest, temp ); | |
2790 %} | |
2791 | |
2792 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate | |
2793 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant); | |
2794 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
2795 #ifdef _LP64 | |
2796 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2797 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2798 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true); | |
2799 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 ); | |
2800 #else // _LP64 | |
2801 uint *code; | |
2802 int tmp_reg = $tmp$$reg; | |
2803 | |
2804 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2805 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address ); | |
2806 | |
2807 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2808 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address ); | |
2809 #endif // _LP64 | |
2810 %} | |
2811 | |
2812 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate | |
2813 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant); | |
2814 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
2815 #ifdef _LP64 | |
2816 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2817 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2818 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); | |
2819 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); | |
2820 #else // _LP64 | |
2821 uint *code; | |
2822 int tmp_reg = $tmp$$reg; | |
2823 | |
2824 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2825 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); | |
2826 | |
2827 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2828 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); | |
2829 #endif // _LP64 | |
2830 %} | |
2831 | |
2832 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
2833 // Load a constant replicated "count" times with width "width" | |
2834 int bit_width = $width$$constant * 8; | |
2835 jlong elt_val = $src$$constant; | |
2836 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
2837 jlong val = elt_val; | |
2838 for (int i = 0; i < $count$$constant - 1; i++) { | |
2839 val <<= bit_width; | |
2840 val |= elt_val; | |
2841 } | |
2842 jdouble dval = *(jdouble*)&val; // coerce to double type | |
2843 address double_address = MacroAssembler(&cbuf).double_constant(dval); | |
2844 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
2845 #ifdef _LP64 | |
2846 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2847 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2848 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); | |
2849 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); | |
2850 #else // _LP64 | |
2851 uint *code; | |
2852 int tmp_reg = $tmp$$reg; | |
2853 | |
2854 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2855 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); | |
2856 | |
2857 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
2858 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); | |
2859 #endif // _LP64 | |
2860 %} | |
2861 | |
2862 | |
2863 enc_class ShouldNotEncodeThis ( ) %{ | |
2864 ShouldNotCallThis(); | |
2865 %} | |
2866 | |
2867 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
2868 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
2869 MacroAssembler _masm(&cbuf); | |
2870 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
2871 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
2872 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
2873 | |
2874 Label loop; | |
2875 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
2876 | |
2877 // Loop and clear, walking backwards through the array. | |
2878 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
2879 __ bind(loop); | |
2880 __ deccc(nof_bytes_tmp, 8); | |
2881 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
2882 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
2883 // %%%% this mini-loop must not cross a cache boundary! | |
2884 %} | |
2885 | |
2886 | |
2887 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ | |
2888 Label Ldone, Lloop; | |
2889 MacroAssembler _masm(&cbuf); | |
2890 | |
2891 Register str1_reg = reg_to_register_object($str1$$reg); | |
2892 Register str2_reg = reg_to_register_object($str2$$reg); | |
2893 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
2894 Register tmp2_reg = reg_to_register_object($tmp2$$reg); | |
2895 Register result_reg = reg_to_register_object($result$$reg); | |
2896 | |
2897 // Get the first character position in both strings | |
2898 // [8] char array, [12] offset, [16] count | |
2899 int value_offset = java_lang_String:: value_offset_in_bytes(); | |
2900 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
2901 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
2902 | |
2903 // load str1 (jchar*) base address into tmp1_reg | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2904 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); |
0 | 2905 __ ld(Address(str1_reg, 0, offset_offset), result_reg); |
2906 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); | |
2907 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted | |
2908 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
2909 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted |
0 | 2910 __ add(result_reg, tmp1_reg, tmp1_reg); |
2911 | |
2912 // load str2 (jchar*) base address into tmp2_reg | |
2913 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted | |
2914 __ ld(Address(str2_reg, 0, offset_offset), result_reg); | |
2915 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); | |
2916 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted | |
2917 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
2918 __ subcc(str1_reg, str2_reg, O7); // hoisted | |
2919 __ add(result_reg, tmp2_reg, tmp2_reg); | |
2920 | |
2921 // Compute the minimum of the string lengths(str1_reg) and the | |
2922 // difference of the string lengths (stack) | |
2923 | |
2924 // discard string base pointers, after loading up the lengths | |
2925 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted | |
2926 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted | |
2927 | |
2928 // See if the lengths are different, and calculate min in str1_reg. | |
2929 // Stash diff in O7 in case we need it for a tie-breaker. | |
2930 Label Lskip; | |
2931 // __ subcc(str1_reg, str2_reg, O7); // hoisted | |
2932 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit | |
2933 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
2934 // str2 is shorter, so use its count: | |
2935 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit | |
2936 __ bind(Lskip); | |
2937 | |
2938 // reallocate str1_reg, str2_reg, result_reg | |
2939 // Note: limit_reg holds the string length pre-scaled by 2 | |
2940 Register limit_reg = str1_reg; | |
2941 Register chr2_reg = str2_reg; | |
2942 Register chr1_reg = result_reg; | |
2943 // tmp{12} are the base pointers | |
2944 | |
2945 // Is the minimum length zero? | |
2946 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2947 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2948 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2949 | |
2950 // Load first characters | |
2951 __ lduh(tmp1_reg, 0, chr1_reg); | |
2952 __ lduh(tmp2_reg, 0, chr2_reg); | |
2953 | |
2954 // Compare first characters | |
2955 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2956 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2957 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2958 __ delayed()->nop(); | |
2959 | |
2960 { | |
2961 // Check after comparing first character to see if strings are equivalent | |
2962 Label LSkip2; | |
2963 // Check if the strings start at same location | |
2964 __ cmp(tmp1_reg, tmp2_reg); | |
2965 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); | |
2966 __ delayed()->nop(); | |
2967 | |
2968 // Check if the length difference is zero (in O7) | |
2969 __ cmp(G0, O7); | |
2970 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2971 __ delayed()->mov(G0, result_reg); // result is zero | |
2972 | |
2973 // Strings might not be equal | |
2974 __ bind(LSkip2); | |
2975 } | |
2976 | |
2977 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2978 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2979 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2980 | |
2981 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit | |
2982 __ add(tmp1_reg, limit_reg, tmp1_reg); | |
2983 __ add(tmp2_reg, limit_reg, tmp2_reg); | |
2984 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) | |
2985 | |
2986 // Compare the rest of the characters | |
2987 __ lduh(tmp1_reg, limit_reg, chr1_reg); | |
2988 __ bind(Lloop); | |
2989 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
2990 __ lduh(tmp2_reg, limit_reg, chr2_reg); | |
2991 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2992 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2993 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2994 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2995 // annul LDUH if branch is not taken to prevent access past end of string | |
2996 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
2997 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
2998 | |
2999 // If strings are equal up to min length, return the length difference. | |
3000 __ mov(O7, result_reg); | |
3001 | |
3002 // Otherwise, return the difference between the first mismatched chars. | |
3003 __ bind(Ldone); | |
3004 %} | |
3005 | |
681 | 3006 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ |
3007 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; | |
3008 MacroAssembler _masm(&cbuf); | |
3009 | |
3010 Register str1_reg = reg_to_register_object($str1$$reg); | |
3011 Register str2_reg = reg_to_register_object($str2$$reg); | |
3012 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
3013 Register tmp2_reg = reg_to_register_object($tmp2$$reg); | |
3014 Register result_reg = reg_to_register_object($result$$reg); | |
3015 | |
3016 // Get the first character position in both strings | |
3017 // [8] char array, [12] offset, [16] count | |
3018 int value_offset = java_lang_String:: value_offset_in_bytes(); | |
3019 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
3020 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
3021 | |
3022 // load str1 (jchar*) base address into tmp1_reg | |
3023 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); | |
3024 __ ld(Address(str1_reg, 0, offset_offset), result_reg); | |
3025 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); | |
3026 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted | |
3027 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
3028 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted | |
3029 __ add(result_reg, tmp1_reg, tmp1_reg); | |
3030 | |
3031 // load str2 (jchar*) base address into tmp2_reg | |
3032 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted | |
3033 __ ld(Address(str2_reg, 0, offset_offset), result_reg); | |
3034 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); | |
3035 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted | |
3036 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
3037 __ cmp(str1_reg, str2_reg); // hoisted | |
3038 __ add(result_reg, tmp2_reg, tmp2_reg); | |
3039 | |
3040 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); | |
3041 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3042 __ delayed()->mov(G0, result_reg); // not equal | |
3043 | |
3044 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone); | |
3045 __ delayed()->add(G0, 1, result_reg); //equals | |
3046 | |
3047 __ cmp(tmp1_reg, tmp2_reg); //same string ? | |
3048 __ brx(Assembler::equal, true, Assembler::pn, Ldone); | |
3049 __ delayed()->add(G0, 1, result_reg); | |
3050 | |
3051 //rename registers | |
3052 Register limit_reg = str1_reg; | |
3053 Register chr2_reg = str2_reg; | |
3054 Register chr1_reg = result_reg; | |
3055 // tmp{12} are the base pointers | |
3056 | |
3057 //check for alignment and position the pointers to the ends | |
3058 __ or3(tmp1_reg, tmp2_reg, chr1_reg); | |
3059 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned | |
3060 __ br(Assembler::notZero, false, Assembler::pn, Lchar); | |
3061 __ delayed()->nop(); | |
3062 | |
3063 __ bind(Lword); | |
3064 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2) | |
3065 __ andn(limit_reg, 0x3, limit_reg); | |
3066 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word); | |
3067 __ delayed()->nop(); | |
3068 | |
3069 __ add(tmp1_reg, limit_reg, tmp1_reg); | |
3070 __ add(tmp2_reg, limit_reg, tmp2_reg); | |
3071 __ neg(limit_reg); | |
3072 | |
3073 __ lduw(tmp1_reg, limit_reg, chr1_reg); | |
3074 __ bind(Lword_loop); | |
3075 __ lduw(tmp2_reg, limit_reg, chr2_reg); | |
3076 __ cmp(chr1_reg, chr2_reg); | |
3077 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3078 __ delayed()->mov(G0, result_reg); | |
3079 __ inccc(limit_reg, 2*sizeof(jchar)); | |
3080 // annul LDUW if branch i s not taken to prevent access past end of string | |
3081 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken | |
3082 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
3083 | |
3084 __ bind(Lpost_word); | |
3085 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone); | |
3086 __ delayed()->add(G0, 1, result_reg); | |
3087 | |
3088 __ lduh(tmp1_reg, 0, chr1_reg); | |
3089 __ lduh(tmp2_reg, 0, chr2_reg); | |
3090 __ cmp (chr1_reg, chr2_reg); | |
3091 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3092 __ delayed()->mov(G0, result_reg); | |
3093 __ ba(false,Ldone); | |
3094 __ delayed()->add(G0, 1, result_reg); | |
3095 | |
3096 __ bind(Lchar); | |
3097 __ add(tmp1_reg, limit_reg, tmp1_reg); | |
3098 __ add(tmp2_reg, limit_reg, tmp2_reg); | |
3099 __ neg(limit_reg); //negate count | |
3100 | |
3101 __ lduh(tmp1_reg, limit_reg, chr1_reg); | |
3102 __ bind(Lchar_loop); | |
3103 __ lduh(tmp2_reg, limit_reg, chr2_reg); | |
3104 __ cmp(chr1_reg, chr2_reg); | |
3105 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3106 __ delayed()->mov(G0, result_reg); //not equal | |
3107 __ inccc(limit_reg, sizeof(jchar)); | |
3108 // annul LDUH if branch is not taken to prevent access past end of string | |
3109 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken | |
3110 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
3111 | |
3112 __ add(G0, 1, result_reg); //equal | |
3113 | |
3114 __ bind(Ldone); | |
3115 %} | |
3116 | |
3117 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ | |
3118 Label Lvector, Ldone, Lloop; | |
3119 MacroAssembler _masm(&cbuf); | |
3120 | |
3121 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3122 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3123 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
3124 Register tmp2_reg = reg_to_register_object($tmp2$$reg); | |
3125 Register result_reg = reg_to_register_object($result$$reg); | |
3126 | |
3127 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3128 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3129 | |
3130 // return true if the same array | |
3131 __ cmp(ary1_reg, ary2_reg); | |
3132 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
3133 __ delayed()->add(G0, 1, result_reg); // equal | |
3134 | |
3135 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3136 __ delayed()->mov(G0, result_reg); // not equal | |
3137 | |
3138 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3139 __ delayed()->mov(G0, result_reg); // not equal | |
3140 | |
3141 //load the lengths of arrays | |
3142 __ ld(Address(ary1_reg, 0, length_offset), tmp1_reg); | |
3143 __ ld(Address(ary2_reg, 0, length_offset), tmp2_reg); | |
3144 | |
3145 // return false if the two arrays are not equal length | |
3146 __ cmp(tmp1_reg, tmp2_reg); | |
3147 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3148 __ delayed()->mov(G0, result_reg); // not equal | |
3149 | |
3150 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone); | |
3151 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal | |
3152 | |
3153 // load array addresses | |
3154 __ add(ary1_reg, base_offset, ary1_reg); | |
3155 __ add(ary2_reg, base_offset, ary2_reg); | |
3156 | |
3157 // renaming registers | |
3158 Register chr1_reg = tmp2_reg; // for characters in ary1 | |
3159 Register chr2_reg = result_reg; // for characters in ary2 | |
3160 Register limit_reg = tmp1_reg; // length | |
3161 | |
3162 // set byte count | |
3163 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
3164 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ? | |
3165 __ br(Assembler::zero, false, Assembler::pt, Lvector); | |
3166 __ delayed()->nop(); | |
3167 | |
3168 //compare the trailing char | |
3169 __ sub(limit_reg, sizeof(jchar), limit_reg); | |
3170 __ lduh(ary1_reg, limit_reg, chr1_reg); | |
3171 __ lduh(ary2_reg, limit_reg, chr2_reg); | |
3172 __ cmp(chr1_reg, chr2_reg); | |
3173 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
3174 __ delayed()->mov(G0, result_reg); // not equal | |
3175 | |
3176 // only one char ? | |
3177 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone); | |
3178 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal | |
3179 | |
3180 __ bind(Lvector); | |
3181 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit | |
3182 __ add(ary1_reg, limit_reg, ary1_reg); | |
3183 __ add(ary2_reg, limit_reg, ary2_reg); | |
3184 __ neg(limit_reg, limit_reg); | |
3185 | |
3186 __ lduw(ary1_reg, limit_reg, chr1_reg); | |
3187 __ bind(Lloop); | |
3188 __ lduw(ary2_reg, limit_reg, chr2_reg); | |
3189 __ cmp(chr1_reg, chr2_reg); | |
3190 __ br(Assembler::notEqual, false, Assembler::pt, Ldone); | |
3191 __ delayed()->mov(G0, result_reg); // not equal | |
3192 __ inccc(limit_reg, 2*sizeof(jchar)); | |
3193 // annul LDUW if branch is not taken to prevent access past end of string | |
3194 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken | |
3195 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted | |
3196 | |
3197 __ add(G0, 1, result_reg); // equals | |
3198 | |
3199 __ bind(Ldone); | |
3200 %} | |
3201 | |
0 | 3202 enc_class enc_rethrow() %{ |
3203 cbuf.set_inst_mark(); | |
3204 Register temp_reg = G3; | |
3205 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub()); | |
3206 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); | |
3207 MacroAssembler _masm(&cbuf); | |
3208 #ifdef ASSERT | |
3209 __ save_frame(0); | |
3210 Address last_rethrow_addr(L1, (address)&last_rethrow); | |
3211 __ sethi(last_rethrow_addr); | |
3212 __ get_pc(L2); | |
3213 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
3214 __ st_ptr(L2, last_rethrow_addr); | |
3215 __ restore(); | |
3216 #endif | |
3217 __ JUMP(rethrow_stub, 0); // sethi;jmp | |
3218 __ delayed()->nop(); | |
3219 %} | |
3220 | |
3221 enc_class emit_mem_nop() %{ | |
3222 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
3223 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3224 *code = (unsigned int)0xc0839040; | |
3225 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3226 %} | |
3227 | |
3228 enc_class emit_fadd_nop() %{ | |
3229 // Generates the instruction FMOVS f31,f31 | |
3230 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3231 *code = (unsigned int)0xbfa0003f; | |
3232 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3233 %} | |
3234 | |
3235 enc_class emit_br_nop() %{ | |
3236 // Generates the instruction BPN,PN . | |
3237 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3238 *code = (unsigned int)0x00400000; | |
3239 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3240 %} | |
3241 | |
3242 enc_class enc_membar_acquire %{ | |
3243 MacroAssembler _masm(&cbuf); | |
3244 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3245 %} | |
3246 | |
3247 enc_class enc_membar_release %{ | |
3248 MacroAssembler _masm(&cbuf); | |
3249 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3250 %} | |
3251 | |
3252 enc_class enc_membar_volatile %{ | |
3253 MacroAssembler _masm(&cbuf); | |
3254 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3255 %} | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3256 |
0 | 3257 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
3258 MacroAssembler _masm(&cbuf); | |
3259 Register src_reg = reg_to_register_object($src$$reg); | |
3260 Register dst_reg = reg_to_register_object($dst$$reg); | |
3261 __ sllx(src_reg, 56, dst_reg); | |
3262 __ srlx(dst_reg, 8, O7); | |
3263 __ or3 (dst_reg, O7, dst_reg); | |
3264 __ srlx(dst_reg, 16, O7); | |
3265 __ or3 (dst_reg, O7, dst_reg); | |
3266 __ srlx(dst_reg, 32, O7); | |
3267 __ or3 (dst_reg, O7, dst_reg); | |
3268 %} | |
3269 | |
3270 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
3271 MacroAssembler _masm(&cbuf); | |
3272 Register src_reg = reg_to_register_object($src$$reg); | |
3273 Register dst_reg = reg_to_register_object($dst$$reg); | |
3274 __ sll(src_reg, 24, dst_reg); | |
3275 __ srl(dst_reg, 8, O7); | |
3276 __ or3(dst_reg, O7, dst_reg); | |
3277 __ srl(dst_reg, 16, O7); | |
3278 __ or3(dst_reg, O7, dst_reg); | |
3279 %} | |
3280 | |
3281 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
3282 MacroAssembler _masm(&cbuf); | |
3283 Register src_reg = reg_to_register_object($src$$reg); | |
3284 Register dst_reg = reg_to_register_object($dst$$reg); | |
3285 __ sllx(src_reg, 48, dst_reg); | |
3286 __ srlx(dst_reg, 16, O7); | |
3287 __ or3 (dst_reg, O7, dst_reg); | |
3288 __ srlx(dst_reg, 32, O7); | |
3289 __ or3 (dst_reg, O7, dst_reg); | |
3290 %} | |
3291 | |
3292 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
3293 MacroAssembler _masm(&cbuf); | |
3294 Register src_reg = reg_to_register_object($src$$reg); | |
3295 Register dst_reg = reg_to_register_object($dst$$reg); | |
3296 __ sllx(src_reg, 32, dst_reg); | |
3297 __ srlx(dst_reg, 32, O7); | |
3298 __ or3 (dst_reg, O7, dst_reg); | |
3299 %} | |
3300 | |
3301 %} | |
3302 | |
3303 //----------FRAME-------------------------------------------------------------- | |
3304 // Definition of frame structure and management information. | |
3305 // | |
3306 // S T A C K L A Y O U T Allocators stack-slot number | |
3307 // | (to get allocators register number | |
3308 // G Owned by | | v add VMRegImpl::stack0) | |
3309 // r CALLER | | | |
3310 // o | +--------+ pad to even-align allocators stack-slot | |
3311 // w V | pad0 | numbers; owned by CALLER | |
3312 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3313 // h ^ | in | 5 | |
3314 // | | args | 4 Holes in incoming args owned by SELF | |
3315 // | | | | 3 | |
3316 // | | +--------+ | |
3317 // V | | old out| Empty on Intel, window on Sparc | |
3318 // | old |preserve| Must be even aligned. | |
3319 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3320 // | | in | 3 area for Intel ret address | |
3321 // Owned by |preserve| Empty on Sparc. | |
3322 // SELF +--------+ | |
3323 // | | pad2 | 2 pad to align old SP | |
3324 // | +--------+ 1 | |
3325 // | | locks | 0 | |
3326 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3327 // | | pad1 | 11 pad to align new SP | |
3328 // | +--------+ | |
3329 // | | | 10 | |
3330 // | | spills | 9 spills | |
3331 // V | | 8 (pad0 slot for callee) | |
3332 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3333 // ^ | out | 7 | |
3334 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3335 // Owned by +--------+ | |
3336 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3337 // | new |preserve| Must be even-aligned. | |
3338 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3339 // | | | | |
3340 // | |
3341 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3342 // known from SELF's arguments and the Java calling convention. | |
3343 // Region 6-7 is determined per call site. | |
3344 // Note 2: If the calling convention leaves holes in the incoming argument | |
3345 // area, those holes are owned by SELF. Holes in the outgoing area | |
3346 // are owned by the CALLEE. Holes should not be nessecary in the | |
3347 // incoming area, as the Java calling convention is completely under | |
3348 // the control of the AD file. Doubles can be sorted and packed to | |
3349 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3350 // varargs C calling conventions. | |
3351 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3352 // even aligned with pad0 as needed. | |
3353 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3354 // region 6-11 is even aligned; it may be padded out more so that | |
3355 // the region from SP to FP meets the minimum stack alignment. | |
3356 | |
3357 frame %{ | |
3358 // What direction does stack grow in (assumed to be same for native & Java) | |
3359 stack_direction(TOWARDS_LOW); | |
3360 | |
3361 // These two registers define part of the calling convention | |
3362 // between compiled code and the interpreter. | |
3363 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
3364 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
3365 | |
3366 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3367 cisc_spilling_operand_name(indOffset); | |
3368 | |
3369 // Number of stack slots consumed by a Monitor enter | |
3370 #ifdef _LP64 | |
3371 sync_stack_slots(2); | |
3372 #else | |
3373 sync_stack_slots(1); | |
3374 #endif | |
3375 | |
3376 // Compiled code's Frame Pointer | |
3377 frame_pointer(R_SP); | |
3378 | |
3379 // Stack alignment requirement | |
3380 stack_alignment(StackAlignmentInBytes); | |
3381 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3382 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3383 | |
3384 // Number of stack slots between incoming argument block and the start of | |
3385 // a new frame. The PROLOG must add this many slots to the stack. The | |
3386 // EPILOG must remove this many slots. | |
3387 in_preserve_stack_slots(0); | |
3388 | |
3389 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3390 // for calls to C. Supports the var-args backing area for register parms. | |
3391 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3392 #ifdef _LP64 | |
3393 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3394 varargs_C_out_slots_killed(12); | |
3395 #else | |
3396 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3397 varargs_C_out_slots_killed( 7); | |
3398 #endif | |
3399 | |
3400 // The after-PROLOG location of the return address. Location of | |
3401 // return address specifies a type (REG or STACK) and a number | |
3402 // representing the register number (i.e. - use a register name) or | |
3403 // stack slot. | |
3404 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3405 | |
3406 // Body of function which returns an OptoRegs array locating | |
3407 // arguments either in registers or in stack slots for calling | |
3408 // java | |
3409 calling_convention %{ | |
3410 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3411 | |
3412 %} | |
3413 | |
3414 // Body of function which returns an OptoRegs array locating | |
3415 // arguments either in registers or in stack slots for callin | |
3416 // C. | |
3417 c_calling_convention %{ | |
3418 // This is obviously always outgoing | |
3419 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3420 %} | |
3421 | |
3422 // Location of native (C/C++) and interpreter return values. This is specified to | |
3423 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3424 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3425 // to and from the register pairs is done by the appropriate call and epilog | |
3426 // opcodes. This simplifies the register allocator. | |
3427 c_return_value %{ | |
3428 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3429 #ifdef _LP64 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3430 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3431 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3432 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3433 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3434 #else // !_LP64 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3435 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3436 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3437 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3438 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3439 #endif |
3440 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3441 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3442 %} | |
3443 | |
3444 // Location of compiled Java return values. Same as C | |
3445 return_value %{ | |
3446 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3447 #ifdef _LP64 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3448 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3449 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3450 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3451 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3452 #else // !_LP64 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3453 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3454 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3455 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3456 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3457 #endif |
3458 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3459 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3460 %} | |
3461 | |
3462 %} | |
3463 | |
3464 | |
3465 //----------ATTRIBUTES--------------------------------------------------------- | |
3466 //----------Operand Attributes------------------------------------------------- | |
3467 op_attrib op_cost(1); // Required cost attribute | |
3468 | |
3469 //----------Instruction Attributes--------------------------------------------- | |
3470 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3471 ins_attrib ins_size(32); // Required size attribute (in bits) | |
3472 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
3473 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
3474 // non-matching short branch variant of some | |
3475 // long branch? | |
3476 | |
3477 //----------OPERANDS----------------------------------------------------------- | |
3478 // Operand definitions must precede instruction definitions for correct parsing | |
3479 // in the ADLC because operands constitute user defined types which are used in | |
3480 // instruction definitions. | |
3481 | |
3482 //----------Simple Operands---------------------------------------------------- | |
3483 // Immediate Operands | |
3484 // Integer Immediate: 32-bit | |
3485 operand immI() %{ | |
3486 match(ConI); | |
3487 | |
3488 op_cost(0); | |
3489 // formats are generated automatically for constants and base registers | |
3490 format %{ %} | |
3491 interface(CONST_INTER); | |
3492 %} | |
3493 | |
3494 // Integer Immediate: 13-bit | |
3495 operand immI13() %{ | |
3496 predicate(Assembler::is_simm13(n->get_int())); | |
3497 match(ConI); | |
3498 op_cost(0); | |
3499 | |
3500 format %{ %} | |
3501 interface(CONST_INTER); | |
3502 %} | |
3503 | |
3504 // Unsigned (positive) Integer Immediate: 13-bit | |
3505 operand immU13() %{ | |
3506 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3507 match(ConI); | |
3508 op_cost(0); | |
3509 | |
3510 format %{ %} | |
3511 interface(CONST_INTER); | |
3512 %} | |
3513 | |
3514 // Integer Immediate: 6-bit | |
3515 operand immU6() %{ | |
3516 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3517 match(ConI); | |
3518 op_cost(0); | |
3519 format %{ %} | |
3520 interface(CONST_INTER); | |
3521 %} | |
3522 | |
3523 // Integer Immediate: 11-bit | |
3524 operand immI11() %{ | |
3525 predicate(Assembler::is_simm(n->get_int(),11)); | |
3526 match(ConI); | |
3527 op_cost(0); | |
3528 format %{ %} | |
3529 interface(CONST_INTER); | |
3530 %} | |
3531 | |
3532 // Integer Immediate: 0-bit | |
3533 operand immI0() %{ | |
3534 predicate(n->get_int() == 0); | |
3535 match(ConI); | |
3536 op_cost(0); | |
3537 | |
3538 format %{ %} | |
3539 interface(CONST_INTER); | |
3540 %} | |
3541 | |
3542 // Integer Immediate: the value 10 | |
3543 operand immI10() %{ | |
3544 predicate(n->get_int() == 10); | |
3545 match(ConI); | |
3546 op_cost(0); | |
3547 | |
3548 format %{ %} | |
3549 interface(CONST_INTER); | |
3550 %} | |
3551 | |
3552 // Integer Immediate: the values 0-31 | |
3553 operand immU5() %{ | |
3554 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3555 match(ConI); | |
3556 op_cost(0); | |
3557 | |
3558 format %{ %} | |
3559 interface(CONST_INTER); | |
3560 %} | |
3561 | |
3562 // Integer Immediate: the values 1-31 | |
3563 operand immI_1_31() %{ | |
3564 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3565 match(ConI); | |
3566 op_cost(0); | |
3567 | |
3568 format %{ %} | |
3569 interface(CONST_INTER); | |
3570 %} | |
3571 | |
3572 // Integer Immediate: the values 32-63 | |
3573 operand immI_32_63() %{ | |
3574 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3575 match(ConI); | |
3576 op_cost(0); | |
3577 | |
3578 format %{ %} | |
3579 interface(CONST_INTER); | |
3580 %} | |
3581 | |
3582 // Integer Immediate: the value 255 | |
3583 operand immI_255() %{ | |
3584 predicate( n->get_int() == 255 ); | |
3585 match(ConI); | |
3586 op_cost(0); | |
3587 | |
3588 format %{ %} | |
3589 interface(CONST_INTER); | |
3590 %} | |
3591 | |
3592 // Long Immediate: the value FF | |
3593 operand immL_FF() %{ | |
3594 predicate( n->get_long() == 0xFFL ); | |
3595 match(ConL); | |
3596 op_cost(0); | |
3597 | |
3598 format %{ %} | |
3599 interface(CONST_INTER); | |
3600 %} | |
3601 | |
3602 // Long Immediate: the value FFFF | |
3603 operand immL_FFFF() %{ | |
3604 predicate( n->get_long() == 0xFFFFL ); | |
3605 match(ConL); | |
3606 op_cost(0); | |
3607 | |
3608 format %{ %} | |
3609 interface(CONST_INTER); | |
3610 %} | |
3611 | |
3612 // Pointer Immediate: 32 or 64-bit | |
3613 operand immP() %{ | |
3614 match(ConP); | |
3615 | |
3616 op_cost(5); | |
3617 // formats are generated automatically for constants and base registers | |
3618 format %{ %} | |
3619 interface(CONST_INTER); | |
3620 %} | |
3621 | |
3622 operand immP13() %{ | |
3623 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3624 match(ConP); | |
3625 op_cost(0); | |
3626 | |
3627 format %{ %} | |
3628 interface(CONST_INTER); | |
3629 %} | |
3630 | |
3631 operand immP0() %{ | |
3632 predicate(n->get_ptr() == 0); | |
3633 match(ConP); | |
3634 op_cost(0); | |
3635 | |
3636 format %{ %} | |
3637 interface(CONST_INTER); | |
3638 %} | |
3639 | |
3640 operand immP_poll() %{ | |
3641 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3642 match(ConP); | |
3643 | |
3644 // formats are generated automatically for constants and base registers | |
3645 format %{ %} | |
3646 interface(CONST_INTER); | |
3647 %} | |
3648 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3649 // Pointer Immediate |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3650 operand immN() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3651 %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3652 match(ConN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3653 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3654 op_cost(10); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3655 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3656 interface(CONST_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3657 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3658 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3659 // NULL Pointer Immediate |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3660 operand immN0() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3661 %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3662 predicate(n->get_narrowcon() == 0); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3663 match(ConN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3664 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3665 op_cost(0); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3666 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3667 interface(CONST_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3668 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3669 |
0 | 3670 operand immL() %{ |
3671 match(ConL); | |
3672 op_cost(40); | |
3673 // formats are generated automatically for constants and base registers | |
3674 format %{ %} | |
3675 interface(CONST_INTER); | |
3676 %} | |
3677 | |
3678 operand immL0() %{ | |
3679 predicate(n->get_long() == 0L); | |
3680 match(ConL); | |
3681 op_cost(0); | |
3682 // formats are generated automatically for constants and base registers | |
3683 format %{ %} | |
3684 interface(CONST_INTER); | |
3685 %} | |
3686 | |
3687 // Long Immediate: 13-bit | |
3688 operand immL13() %{ | |
3689 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3690 match(ConL); | |
3691 op_cost(0); | |
3692 | |
3693 format %{ %} | |
3694 interface(CONST_INTER); | |
3695 %} | |
3696 | |
3697 // Long Immediate: low 32-bit mask | |
3698 operand immL_32bits() %{ | |
3699 predicate(n->get_long() == 0xFFFFFFFFL); | |
3700 match(ConL); | |
3701 op_cost(0); | |
3702 | |
3703 format %{ %} | |
3704 interface(CONST_INTER); | |
3705 %} | |
3706 | |
3707 // Double Immediate | |
3708 operand immD() %{ | |
3709 match(ConD); | |
3710 | |
3711 op_cost(40); | |
3712 format %{ %} | |
3713 interface(CONST_INTER); | |
3714 %} | |
3715 | |
3716 operand immD0() %{ | |
3717 #ifdef _LP64 | |
3718 // on 64-bit architectures this comparision is faster | |
3719 predicate(jlong_cast(n->getd()) == 0); | |
3720 #else | |
3721 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3722 #endif | |
3723 match(ConD); | |
3724 | |
3725 op_cost(0); | |
3726 format %{ %} | |
3727 interface(CONST_INTER); | |
3728 %} | |
3729 | |
3730 // Float Immediate | |
3731 operand immF() %{ | |
3732 match(ConF); | |
3733 | |
3734 op_cost(20); | |
3735 format %{ %} | |
3736 interface(CONST_INTER); | |
3737 %} | |
3738 | |
3739 // Float Immediate: 0 | |
3740 operand immF0() %{ | |
3741 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3742 match(ConF); | |
3743 | |
3744 op_cost(0); | |
3745 format %{ %} | |
3746 interface(CONST_INTER); | |
3747 %} | |
3748 | |
3749 // Integer Register Operands | |
3750 // Integer Register | |
3751 operand iRegI() %{ | |
3752 constraint(ALLOC_IN_RC(int_reg)); | |
3753 match(RegI); | |
3754 | |
3755 match(notemp_iRegI); | |
3756 match(g1RegI); | |
3757 match(o0RegI); | |
3758 match(iRegIsafe); | |
3759 | |
3760 format %{ %} | |
3761 interface(REG_INTER); | |
3762 %} | |
3763 | |
3764 operand notemp_iRegI() %{ | |
3765 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3766 match(RegI); | |
3767 | |
3768 match(o0RegI); | |
3769 | |
3770 format %{ %} | |
3771 interface(REG_INTER); | |
3772 %} | |
3773 | |
3774 operand o0RegI() %{ | |
3775 constraint(ALLOC_IN_RC(o0_regI)); | |
3776 match(iRegI); | |
3777 | |
3778 format %{ %} | |
3779 interface(REG_INTER); | |
3780 %} | |
3781 | |
3782 // Pointer Register | |
3783 operand iRegP() %{ | |
3784 constraint(ALLOC_IN_RC(ptr_reg)); | |
3785 match(RegP); | |
3786 | |
3787 match(lock_ptr_RegP); | |
3788 match(g1RegP); | |
3789 match(g2RegP); | |
3790 match(g3RegP); | |
3791 match(g4RegP); | |
3792 match(i0RegP); | |
3793 match(o0RegP); | |
3794 match(o1RegP); | |
3795 match(l7RegP); | |
3796 | |
3797 format %{ %} | |
3798 interface(REG_INTER); | |
3799 %} | |
3800 | |
3801 operand sp_ptr_RegP() %{ | |
3802 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3803 match(RegP); | |
3804 match(iRegP); | |
3805 | |
3806 format %{ %} | |
3807 interface(REG_INTER); | |
3808 %} | |
3809 | |
3810 operand lock_ptr_RegP() %{ | |
3811 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3812 match(RegP); | |
3813 match(i0RegP); | |
3814 match(o0RegP); | |
3815 match(o1RegP); | |
3816 match(l7RegP); | |
3817 | |
3818 format %{ %} | |
3819 interface(REG_INTER); | |
3820 %} | |
3821 | |
3822 operand g1RegP() %{ | |
3823 constraint(ALLOC_IN_RC(g1_regP)); | |
3824 match(iRegP); | |
3825 | |
3826 format %{ %} | |
3827 interface(REG_INTER); | |
3828 %} | |
3829 | |
3830 operand g2RegP() %{ | |
3831 constraint(ALLOC_IN_RC(g2_regP)); | |
3832 match(iRegP); | |
3833 | |
3834 format %{ %} | |
3835 interface(REG_INTER); | |
3836 %} | |
3837 | |
3838 operand g3RegP() %{ | |
3839 constraint(ALLOC_IN_RC(g3_regP)); | |
3840 match(iRegP); | |
3841 | |
3842 format %{ %} | |
3843 interface(REG_INTER); | |
3844 %} | |
3845 | |
3846 operand g1RegI() %{ | |
3847 constraint(ALLOC_IN_RC(g1_regI)); | |
3848 match(iRegI); | |
3849 | |
3850 format %{ %} | |
3851 interface(REG_INTER); | |
3852 %} | |
3853 | |
3854 operand g3RegI() %{ | |
3855 constraint(ALLOC_IN_RC(g3_regI)); | |
3856 match(iRegI); | |
3857 | |
3858 format %{ %} | |
3859 interface(REG_INTER); | |
3860 %} | |
3861 | |
3862 operand g4RegI() %{ | |
3863 constraint(ALLOC_IN_RC(g4_regI)); | |
3864 match(iRegI); | |
3865 | |
3866 format %{ %} | |
3867 interface(REG_INTER); | |
3868 %} | |
3869 | |
3870 operand g4RegP() %{ | |
3871 constraint(ALLOC_IN_RC(g4_regP)); | |
3872 match(iRegP); | |
3873 | |
3874 format %{ %} | |
3875 interface(REG_INTER); | |
3876 %} | |
3877 | |
3878 operand i0RegP() %{ | |
3879 constraint(ALLOC_IN_RC(i0_regP)); | |
3880 match(iRegP); | |
3881 | |
3882 format %{ %} | |
3883 interface(REG_INTER); | |
3884 %} | |
3885 | |
3886 operand o0RegP() %{ | |
3887 constraint(ALLOC_IN_RC(o0_regP)); | |
3888 match(iRegP); | |
3889 | |
3890 format %{ %} | |
3891 interface(REG_INTER); | |
3892 %} | |
3893 | |
3894 operand o1RegP() %{ | |
3895 constraint(ALLOC_IN_RC(o1_regP)); | |
3896 match(iRegP); | |
3897 | |
3898 format %{ %} | |
3899 interface(REG_INTER); | |
3900 %} | |
3901 | |
3902 operand o2RegP() %{ | |
3903 constraint(ALLOC_IN_RC(o2_regP)); | |
3904 match(iRegP); | |
3905 | |
3906 format %{ %} | |
3907 interface(REG_INTER); | |
3908 %} | |
3909 | |
3910 operand o7RegP() %{ | |
3911 constraint(ALLOC_IN_RC(o7_regP)); | |
3912 match(iRegP); | |
3913 | |
3914 format %{ %} | |
3915 interface(REG_INTER); | |
3916 %} | |
3917 | |
3918 operand l7RegP() %{ | |
3919 constraint(ALLOC_IN_RC(l7_regP)); | |
3920 match(iRegP); | |
3921 | |
3922 format %{ %} | |
3923 interface(REG_INTER); | |
3924 %} | |
3925 | |
3926 operand o7RegI() %{ | |
3927 constraint(ALLOC_IN_RC(o7_regI)); | |
3928 match(iRegI); | |
3929 | |
3930 format %{ %} | |
3931 interface(REG_INTER); | |
3932 %} | |
3933 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3934 operand iRegN() %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3935 constraint(ALLOC_IN_RC(int_reg)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3936 match(RegN); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3937 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3938 format %{ %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3939 interface(REG_INTER); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3940 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
3941 |
0 | 3942 // Long Register |
3943 operand iRegL() %{ | |
3944 constraint(ALLOC_IN_RC(long_reg)); | |
3945 match(RegL); | |
3946 | |
3947 format %{ %} | |
3948 interface(REG_INTER); | |
3949 %} | |
3950 | |
3951 operand o2RegL() %{ | |
3952 constraint(ALLOC_IN_RC(o2_regL)); | |
3953 match(iRegL); | |
3954 | |
3955 format %{ %} | |
3956 interface(REG_INTER); | |
3957 %} | |
3958 | |
3959 operand o7RegL() %{ | |
3960 constraint(ALLOC_IN_RC(o7_regL)); | |
3961 match(iRegL); | |
3962 | |
3963 format %{ %} | |
3964 interface(REG_INTER); | |
3965 %} | |
3966 | |
3967 operand g1RegL() %{ | |
3968 constraint(ALLOC_IN_RC(g1_regL)); | |
3969 match(iRegL); | |
3970 | |
3971 format %{ %} | |
3972 interface(REG_INTER); | |
3973 %} | |
3974 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3975 operand g3RegL() %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3976 constraint(ALLOC_IN_RC(g3_regL)); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3977 match(iRegL); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3978 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3979 format %{ %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3980 interface(REG_INTER); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3981 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3982 |
0 | 3983 // Int Register safe |
3984 // This is 64bit safe | |
3985 operand iRegIsafe() %{ | |
3986 constraint(ALLOC_IN_RC(long_reg)); | |
3987 | |
3988 match(iRegI); | |
3989 | |
3990 format %{ %} | |
3991 interface(REG_INTER); | |
3992 %} | |
3993 | |
3994 // Condition Code Flag Register | |
3995 operand flagsReg() %{ | |
3996 constraint(ALLOC_IN_RC(int_flags)); | |
3997 match(RegFlags); | |
3998 | |
3999 format %{ "ccr" %} // both ICC and XCC | |
4000 interface(REG_INTER); | |
4001 %} | |
4002 | |
4003 // Condition Code Register, unsigned comparisons. | |
4004 operand flagsRegU() %{ | |
4005 constraint(ALLOC_IN_RC(int_flags)); | |
4006 match(RegFlags); | |
4007 | |
4008 format %{ "icc_U" %} | |
4009 interface(REG_INTER); | |
4010 %} | |
4011 | |
4012 // Condition Code Register, pointer comparisons. | |
4013 operand flagsRegP() %{ | |
4014 constraint(ALLOC_IN_RC(int_flags)); | |
4015 match(RegFlags); | |
4016 | |
4017 #ifdef _LP64 | |
4018 format %{ "xcc_P" %} | |
4019 #else | |
4020 format %{ "icc_P" %} | |
4021 #endif | |
4022 interface(REG_INTER); | |
4023 %} | |
4024 | |
4025 // Condition Code Register, long comparisons. | |
4026 operand flagsRegL() %{ | |
4027 constraint(ALLOC_IN_RC(int_flags)); | |
4028 match(RegFlags); | |
4029 | |
4030 format %{ "xcc_L" %} | |
4031 interface(REG_INTER); | |
4032 %} | |
4033 | |
4034 // Condition Code Register, floating comparisons, unordered same as "less". | |
4035 operand flagsRegF() %{ | |
4036 constraint(ALLOC_IN_RC(float_flags)); | |
4037 match(RegFlags); | |
4038 match(flagsRegF0); | |
4039 | |
4040 format %{ %} | |
4041 interface(REG_INTER); | |
4042 %} | |
4043 | |
4044 operand flagsRegF0() %{ | |
4045 constraint(ALLOC_IN_RC(float_flag0)); | |
4046 match(RegFlags); | |
4047 | |
4048 format %{ %} | |
4049 interface(REG_INTER); | |
4050 %} | |
4051 | |
4052 | |
4053 // Condition Code Flag Register used by long compare | |
4054 operand flagsReg_long_LTGE() %{ | |
4055 constraint(ALLOC_IN_RC(int_flags)); | |
4056 match(RegFlags); | |
4057 format %{ "icc_LTGE" %} | |
4058 interface(REG_INTER); | |
4059 %} | |
4060 operand flagsReg_long_EQNE() %{ | |
4061 constraint(ALLOC_IN_RC(int_flags)); | |
4062 match(RegFlags); | |
4063 format %{ "icc_EQNE" %} | |
4064 interface(REG_INTER); | |
4065 %} | |
4066 operand flagsReg_long_LEGT() %{ | |
4067 constraint(ALLOC_IN_RC(int_flags)); | |
4068 match(RegFlags); | |
4069 format %{ "icc_LEGT" %} | |
4070 interface(REG_INTER); | |
4071 %} | |
4072 | |
4073 | |
4074 operand regD() %{ | |
4075 constraint(ALLOC_IN_RC(dflt_reg)); | |
4076 match(RegD); | |
4077 | |
551 | 4078 match(regD_low); |
4079 | |
0 | 4080 format %{ %} |
4081 interface(REG_INTER); | |
4082 %} | |
4083 | |
4084 operand regF() %{ | |
4085 constraint(ALLOC_IN_RC(sflt_reg)); | |
4086 match(RegF); | |
4087 | |
4088 format %{ %} | |
4089 interface(REG_INTER); | |
4090 %} | |
4091 | |
4092 operand regD_low() %{ | |
4093 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4094 match(regD); |
0 | 4095 |
4096 format %{ %} | |
4097 interface(REG_INTER); | |
4098 %} | |
4099 | |
4100 // Special Registers | |
4101 | |
4102 // Method Register | |
4103 operand inline_cache_regP(iRegP reg) %{ | |
4104 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4105 match(reg); | |
4106 format %{ %} | |
4107 interface(REG_INTER); | |
4108 %} | |
4109 | |
4110 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4111 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4112 match(reg); | |
4113 format %{ %} | |
4114 interface(REG_INTER); | |
4115 %} | |
4116 | |
4117 | |
4118 //----------Complex Operands--------------------------------------------------- | |
4119 // Indirect Memory Reference | |
4120 operand indirect(sp_ptr_RegP reg) %{ | |
4121 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4122 match(reg); | |
4123 | |
4124 op_cost(100); | |
4125 format %{ "[$reg]" %} | |
4126 interface(MEMORY_INTER) %{ | |
4127 base($reg); | |
4128 index(0x0); | |
4129 scale(0x0); | |
4130 disp(0x0); | |
4131 %} | |
4132 %} | |
4133 | |
4134 // Indirect with Offset | |
4135 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ | |
4136 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4137 match(AddP reg offset); | |
4138 | |
4139 op_cost(100); | |
4140 format %{ "[$reg + $offset]" %} | |
4141 interface(MEMORY_INTER) %{ | |
4142 base($reg); | |
4143 index(0x0); | |
4144 scale(0x0); | |
4145 disp($offset); | |
4146 %} | |
4147 %} | |
4148 | |
4149 // Note: Intel has a swapped version also, like this: | |
4150 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4151 // constraint(ALLOC_IN_RC(int_reg)); | |
4152 // match(AddP offset reg); | |
4153 // | |
4154 // op_cost(100); | |
4155 // format %{ "[$reg + $offset]" %} | |
4156 // interface(MEMORY_INTER) %{ | |
4157 // base($reg); | |
4158 // index(0x0); | |
4159 // scale(0x0); | |
4160 // disp($offset); | |
4161 // %} | |
4162 //%} | |
4163 //// However, it doesn't make sense for SPARC, since | |
4164 // we have no particularly good way to embed oops in | |
4165 // single instructions. | |
4166 | |
4167 // Indirect with Register Index | |
4168 operand indIndex(iRegP addr, iRegX index) %{ | |
4169 constraint(ALLOC_IN_RC(ptr_reg)); | |
4170 match(AddP addr index); | |
4171 | |
4172 op_cost(100); | |
4173 format %{ "[$addr + $index]" %} | |
4174 interface(MEMORY_INTER) %{ | |
4175 base($addr); | |
4176 index($index); | |
4177 scale(0x0); | |
4178 disp(0x0); | |
4179 %} | |
4180 %} | |
4181 | |
4182 //----------Special Memory Operands-------------------------------------------- | |
4183 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4184 // values on the stack where a match requires a value to | |
4185 // flow through memory. | |
4186 operand stackSlotI(sRegI reg) %{ | |
4187 constraint(ALLOC_IN_RC(stack_slots)); | |
4188 op_cost(100); | |
4189 //match(RegI); | |
4190 format %{ "[$reg]" %} | |
4191 interface(MEMORY_INTER) %{ | |
4192 base(0xE); // R_SP | |
4193 index(0x0); | |
4194 scale(0x0); | |
4195 disp($reg); // Stack Offset | |
4196 %} | |
4197 %} | |
4198 | |
4199 operand stackSlotP(sRegP reg) %{ | |
4200 constraint(ALLOC_IN_RC(stack_slots)); | |
4201 op_cost(100); | |
4202 //match(RegP); | |
4203 format %{ "[$reg]" %} | |
4204 interface(MEMORY_INTER) %{ | |
4205 base(0xE); // R_SP | |
4206 index(0x0); | |
4207 scale(0x0); | |
4208 disp($reg); // Stack Offset | |
4209 %} | |
4210 %} | |
4211 | |
4212 operand stackSlotF(sRegF reg) %{ | |
4213 constraint(ALLOC_IN_RC(stack_slots)); | |
4214 op_cost(100); | |
4215 //match(RegF); | |
4216 format %{ "[$reg]" %} | |
4217 interface(MEMORY_INTER) %{ | |
4218 base(0xE); // R_SP | |
4219 index(0x0); | |
4220 scale(0x0); | |
4221 disp($reg); // Stack Offset | |
4222 %} | |
4223 %} | |
4224 operand stackSlotD(sRegD reg) %{ | |
4225 constraint(ALLOC_IN_RC(stack_slots)); | |
4226 op_cost(100); | |
4227 //match(RegD); | |
4228 format %{ "[$reg]" %} | |
4229 interface(MEMORY_INTER) %{ | |
4230 base(0xE); // R_SP | |
4231 index(0x0); | |
4232 scale(0x0); | |
4233 disp($reg); // Stack Offset | |
4234 %} | |
4235 %} | |
4236 operand stackSlotL(sRegL reg) %{ | |
4237 constraint(ALLOC_IN_RC(stack_slots)); | |
4238 op_cost(100); | |
4239 //match(RegL); | |
4240 format %{ "[$reg]" %} | |
4241 interface(MEMORY_INTER) %{ | |
4242 base(0xE); // R_SP | |
4243 index(0x0); | |
4244 scale(0x0); | |
4245 disp($reg); // Stack Offset | |
4246 %} | |
4247 %} | |
4248 | |
4249 // Operands for expressing Control Flow | |
4250 // NOTE: Label is a predefined operand which should not be redefined in | |
4251 // the AD file. It is generically handled within the ADLC. | |
4252 | |
4253 //----------Conditional Branch Operands---------------------------------------- | |
4254 // Comparison Op - This is the operation of the comparison, and is limited to | |
4255 // the following set of codes: | |
4256 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4257 // | |
4258 // Other attributes of the comparison, such as unsignedness, are specified | |
4259 // by the comparison instruction that sets a condition code flags register. | |
4260 // That result is represented by a flags operand whose subtype is appropriate | |
4261 // to the unsignedness (etc.) of the comparison. | |
4262 // | |
4263 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4264 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4265 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4266 | |
4267 operand cmpOp() %{ | |
4268 match(Bool); | |
4269 | |
4270 format %{ "" %} | |
4271 interface(COND_INTER) %{ | |
4272 equal(0x1); | |
4273 not_equal(0x9); | |
4274 less(0x3); | |
4275 greater_equal(0xB); | |
4276 less_equal(0x2); | |
4277 greater(0xA); | |
4278 %} | |
4279 %} | |
4280 | |
4281 // Comparison Op, unsigned | |
4282 operand cmpOpU() %{ | |
4283 match(Bool); | |
4284 | |
4285 format %{ "u" %} | |
4286 interface(COND_INTER) %{ | |
4287 equal(0x1); | |
4288 not_equal(0x9); | |
4289 less(0x5); | |
4290 greater_equal(0xD); | |
4291 less_equal(0x4); | |
4292 greater(0xC); | |
4293 %} | |
4294 %} | |
4295 | |
4296 // Comparison Op, pointer (same as unsigned) | |
4297 operand cmpOpP() %{ | |
4298 match(Bool); | |
4299 | |
4300 format %{ "p" %} | |
4301 interface(COND_INTER) %{ | |
4302 equal(0x1); | |
4303 not_equal(0x9); | |
4304 less(0x5); | |
4305 greater_equal(0xD); | |
4306 less_equal(0x4); | |
4307 greater(0xC); | |
4308 %} | |
4309 %} | |
4310 | |
4311 // Comparison Op, branch-register encoding | |
4312 operand cmpOp_reg() %{ | |
4313 match(Bool); | |
4314 | |
4315 format %{ "" %} | |
4316 interface(COND_INTER) %{ | |
4317 equal (0x1); | |
4318 not_equal (0x5); | |
4319 less (0x3); | |
4320 greater_equal(0x7); | |
4321 less_equal (0x2); | |
4322 greater (0x6); | |
4323 %} | |
4324 %} | |
4325 | |
4326 // Comparison Code, floating, unordered same as less | |
4327 operand cmpOpF() %{ | |
4328 match(Bool); | |
4329 | |
4330 format %{ "fl" %} | |
4331 interface(COND_INTER) %{ | |
4332 equal(0x9); | |
4333 not_equal(0x1); | |
4334 less(0x3); | |
4335 greater_equal(0xB); | |
4336 less_equal(0xE); | |
4337 greater(0x6); | |
4338 %} | |
4339 %} | |
4340 | |
4341 // Used by long compare | |
4342 operand cmpOp_commute() %{ | |
4343 match(Bool); | |
4344 | |
4345 format %{ "" %} | |
4346 interface(COND_INTER) %{ | |
4347 equal(0x1); | |
4348 not_equal(0x9); | |
4349 less(0xA); | |
4350 greater_equal(0x2); | |
4351 less_equal(0xB); | |
4352 greater(0x3); | |
4353 %} | |
4354 %} | |
4355 | |
4356 //----------OPERAND CLASSES---------------------------------------------------- | |
4357 // Operand Classes are groups of operands that are used to simplify | |
605 | 4358 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4359 // instructions for every form of operand when the instruction accepts |
4360 // multiple operand types with the same basic encoding and format. The classic | |
4361 // case of this is memory operands. | |
4362 // Indirect is not included since its use is limited to Compare & Swap | |
4363 opclass memory( indirect, indOffset13, indIndex ); | |
4364 | |
4365 //----------PIPELINE----------------------------------------------------------- | |
4366 pipeline %{ | |
4367 | |
4368 //----------ATTRIBUTES--------------------------------------------------------- | |
4369 attributes %{ | |
4370 fixed_size_instructions; // Fixed size instructions | |
4371 branch_has_delay_slot; // Branch has delay slot following | |
4372 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4373 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4374 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4375 instruction_fetch_units = 1; // of 16 bytes | |
4376 | |
4377 // List of nop instructions | |
4378 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4379 %} | |
4380 | |
4381 //----------RESOURCES---------------------------------------------------------- | |
4382 // Resources are the functional units available to the machine | |
4383 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4384 | |
4385 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4386 // Pipeline Description specifies the stages in the machine's pipeline | |
4387 | |
4388 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4389 | |
4390 //----------PIPELINE CLASSES--------------------------------------------------- | |
4391 // Pipeline Classes describe the stages in which input and output are | |
4392 // referenced by the hardware pipeline. | |
4393 | |
4394 // Integer ALU reg-reg operation | |
4395 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4396 single_instruction; | |
4397 dst : E(write); | |
4398 src1 : R(read); | |
4399 src2 : R(read); | |
4400 IALU : R; | |
4401 %} | |
4402 | |
4403 // Integer ALU reg-reg long operation | |
4404 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4405 instruction_count(2); | |
4406 dst : E(write); | |
4407 src1 : R(read); | |
4408 src2 : R(read); | |
4409 IALU : R; | |
4410 IALU : R; | |
4411 %} | |
4412 | |
4413 // Integer ALU reg-reg long dependent operation | |
4414 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4415 instruction_count(1); multiple_bundles; | |
4416 dst : E(write); | |
4417 src1 : R(read); | |
4418 src2 : R(read); | |
4419 cr : E(write); | |
4420 IALU : R(2); | |
4421 %} | |
4422 | |
4423 // Integer ALU reg-imm operaion | |
4424 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4425 single_instruction; | |
4426 dst : E(write); | |
4427 src1 : R(read); | |
4428 IALU : R; | |
4429 %} | |
4430 | |
4431 // Integer ALU reg-reg operation with condition code | |
4432 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4433 single_instruction; | |
4434 dst : E(write); | |
4435 cr : E(write); | |
4436 src1 : R(read); | |
4437 src2 : R(read); | |
4438 IALU : R; | |
4439 %} | |
4440 | |
4441 // Integer ALU reg-imm operation with condition code | |
4442 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4443 single_instruction; | |
4444 dst : E(write); | |
4445 cr : E(write); | |
4446 src1 : R(read); | |
4447 IALU : R; | |
4448 %} | |
4449 | |
4450 // Integer ALU zero-reg operation | |
4451 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4452 single_instruction; | |
4453 dst : E(write); | |
4454 src2 : R(read); | |
4455 IALU : R; | |
4456 %} | |
4457 | |
4458 // Integer ALU zero-reg operation with condition code only | |
4459 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4460 single_instruction; | |
4461 cr : E(write); | |
4462 src : R(read); | |
4463 IALU : R; | |
4464 %} | |
4465 | |
4466 // Integer ALU reg-reg operation with condition code only | |
4467 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4468 single_instruction; | |
4469 cr : E(write); | |
4470 src1 : R(read); | |
4471 src2 : R(read); | |
4472 IALU : R; | |
4473 %} | |
4474 | |
4475 // Integer ALU reg-imm operation with condition code only | |
4476 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4477 single_instruction; | |
4478 cr : E(write); | |
4479 src1 : R(read); | |
4480 IALU : R; | |
4481 %} | |
4482 | |
4483 // Integer ALU reg-reg-zero operation with condition code only | |
4484 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4485 single_instruction; | |
4486 cr : E(write); | |
4487 src1 : R(read); | |
4488 src2 : R(read); | |
4489 IALU : R; | |
4490 %} | |
4491 | |
4492 // Integer ALU reg-imm-zero operation with condition code only | |
4493 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4494 single_instruction; | |
4495 cr : E(write); | |
4496 src1 : R(read); | |
4497 IALU : R; | |
4498 %} | |
4499 | |
4500 // Integer ALU reg-reg operation with condition code, src1 modified | |
4501 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4502 single_instruction; | |
4503 cr : E(write); | |
4504 src1 : E(write); | |
4505 src1 : R(read); | |
4506 src2 : R(read); | |
4507 IALU : R; | |
4508 %} | |
4509 | |
4510 // Integer ALU reg-imm operation with condition code, src1 modified | |
4511 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4512 single_instruction; | |
4513 cr : E(write); | |
4514 src1 : E(write); | |
4515 src1 : R(read); | |
4516 IALU : R; | |
4517 %} | |
4518 | |
4519 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4520 multiple_bundles; | |
4521 dst : E(write)+4; | |
4522 cr : E(write); | |
4523 src1 : R(read); | |
4524 src2 : R(read); | |
4525 IALU : R(3); | |
4526 BR : R(2); | |
4527 %} | |
4528 | |
4529 // Integer ALU operation | |
4530 pipe_class ialu_none(iRegI dst) %{ | |
4531 single_instruction; | |
4532 dst : E(write); | |
4533 IALU : R; | |
4534 %} | |
4535 | |
4536 // Integer ALU reg operation | |
4537 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4538 single_instruction; may_have_no_code; | |
4539 dst : E(write); | |
4540 src : R(read); | |
4541 IALU : R; | |
4542 %} | |
4543 | |
4544 // Integer ALU reg conditional operation | |
4545 // This instruction has a 1 cycle stall, and cannot execute | |
4546 // in the same cycle as the instruction setting the condition | |
4547 // code. We kludge this by pretending to read the condition code | |
4548 // 1 cycle earlier, and by marking the functional units as busy | |
4549 // for 2 cycles with the result available 1 cycle later than | |
4550 // is really the case. | |
4551 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4552 single_instruction; | |
4553 op2_out : C(write); | |
4554 op1 : R(read); | |
4555 cr : R(read); // This is really E, with a 1 cycle stall | |
4556 BR : R(2); | |
4557 MS : R(2); | |
4558 %} | |
4559 | |
4560 #ifdef _LP64 | |
4561 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4562 instruction_count(1); multiple_bundles; | |
4563 dst : C(write)+1; | |
4564 src : R(read)+1; | |
4565 IALU : R(1); | |
4566 BR : E(2); | |
4567 MS : E(2); | |
4568 %} | |
4569 #endif | |
4570 | |
4571 // Integer ALU reg operation | |
4572 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4573 single_instruction; may_have_no_code; | |
4574 dst : E(write); | |
4575 src : R(read); | |
4576 IALU : R; | |
4577 %} | |
4578 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4579 single_instruction; may_have_no_code; | |
4580 dst : E(write); | |
4581 src : R(read); | |
4582 IALU : R; | |
4583 %} | |
4584 | |
4585 // Two integer ALU reg operations | |
4586 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4587 instruction_count(2); | |
4588 dst : E(write); | |
4589 src : R(read); | |
4590 A0 : R; | |
4591 A1 : R; | |
4592 %} | |
4593 | |
4594 // Two integer ALU reg operations | |
4595 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4596 instruction_count(2); may_have_no_code; | |
4597 dst : E(write); | |
4598 src : R(read); | |
4599 A0 : R; | |
4600 A1 : R; | |
4601 %} | |
4602 | |
4603 // Integer ALU imm operation | |
4604 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4605 single_instruction; | |
4606 dst : E(write); | |
4607 IALU : R; | |
4608 %} | |
4609 | |
4610 // Integer ALU reg-reg with carry operation | |
4611 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4612 single_instruction; | |
4613 dst : E(write); | |
4614 src1 : R(read); | |
4615 src2 : R(read); | |
4616 IALU : R; | |
4617 %} | |
4618 | |
4619 // Integer ALU cc operation | |
4620 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4621 single_instruction; | |
4622 dst : E(write); | |
4623 cc : R(read); | |
4624 IALU : R; | |
4625 %} | |
4626 | |
4627 // Integer ALU cc / second IALU operation | |
4628 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4629 instruction_count(1); multiple_bundles; | |
4630 dst : E(write)+1; | |
4631 src : R(read); | |
4632 IALU : R; | |
4633 %} | |
4634 | |
4635 // Integer ALU cc / second IALU operation | |
4636 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4637 instruction_count(1); multiple_bundles; | |
4638 dst : E(write)+1; | |
4639 p : R(read); | |
4640 q : R(read); | |
4641 IALU : R; | |
4642 %} | |
4643 | |
4644 // Integer ALU hi-lo-reg operation | |
4645 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4646 instruction_count(1); multiple_bundles; | |
4647 dst : E(write)+1; | |
4648 IALU : R(2); | |
4649 %} | |
4650 | |
4651 // Float ALU hi-lo-reg operation (with temp) | |
4652 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4653 instruction_count(1); multiple_bundles; | |
4654 dst : E(write)+1; | |
4655 IALU : R(2); | |
4656 %} | |
4657 | |
4658 // Long Constant | |
4659 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4660 instruction_count(2); multiple_bundles; | |
4661 dst : E(write)+1; | |
4662 IALU : R(2); | |
4663 IALU : R(2); | |
4664 %} | |
4665 | |
4666 // Pointer Constant | |
4667 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4668 instruction_count(0); multiple_bundles; | |
4669 fixed_latency(6); | |
4670 %} | |
4671 | |
4672 // Polling Address | |
4673 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4674 #ifdef _LP64 | |
4675 instruction_count(0); multiple_bundles; | |
4676 fixed_latency(6); | |
4677 #else | |
4678 dst : E(write); | |
4679 IALU : R; | |
4680 #endif | |
4681 %} | |
4682 | |
4683 // Long Constant small | |
4684 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4685 instruction_count(2); | |
4686 dst : E(write); | |
4687 IALU : R; | |
4688 IALU : R; | |
4689 %} | |
4690 | |
4691 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4692 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4693 instruction_count(1); multiple_bundles; | |
4694 src : R(read); | |
4695 dst : M(write)+1; | |
4696 IALU : R; | |
4697 MS : E; | |
4698 %} | |
4699 | |
4700 // Integer ALU nop operation | |
4701 pipe_class ialu_nop() %{ | |
4702 single_instruction; | |
4703 IALU : R; | |
4704 %} | |
4705 | |
4706 // Integer ALU nop operation | |
4707 pipe_class ialu_nop_A0() %{ | |
4708 single_instruction; | |
4709 A0 : R; | |
4710 %} | |
4711 | |
4712 // Integer ALU nop operation | |
4713 pipe_class ialu_nop_A1() %{ | |
4714 single_instruction; | |
4715 A1 : R; | |
4716 %} | |
4717 | |
4718 // Integer Multiply reg-reg operation | |
4719 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4720 single_instruction; | |
4721 dst : E(write); | |
4722 src1 : R(read); | |
4723 src2 : R(read); | |
4724 MS : R(5); | |
4725 %} | |
4726 | |
4727 // Integer Multiply reg-imm operation | |
4728 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4729 single_instruction; | |
4730 dst : E(write); | |
4731 src1 : R(read); | |
4732 MS : R(5); | |
4733 %} | |
4734 | |
4735 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4736 single_instruction; | |
4737 dst : E(write)+4; | |
4738 src1 : R(read); | |
4739 src2 : R(read); | |
4740 MS : R(6); | |
4741 %} | |
4742 | |
4743 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4744 single_instruction; | |
4745 dst : E(write)+4; | |
4746 src1 : R(read); | |
4747 MS : R(6); | |
4748 %} | |
4749 | |
4750 // Integer Divide reg-reg | |
4751 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4752 instruction_count(1); multiple_bundles; | |
4753 dst : E(write); | |
4754 temp : E(write); | |
4755 src1 : R(read); | |
4756 src2 : R(read); | |
4757 temp : R(read); | |
4758 MS : R(38); | |
4759 %} | |
4760 | |
4761 // Integer Divide reg-imm | |
4762 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4763 instruction_count(1); multiple_bundles; | |
4764 dst : E(write); | |
4765 temp : E(write); | |
4766 src1 : R(read); | |
4767 temp : R(read); | |
4768 MS : R(38); | |
4769 %} | |
4770 | |
4771 // Long Divide | |
4772 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4773 dst : E(write)+71; | |
4774 src1 : R(read); | |
4775 src2 : R(read)+1; | |
4776 MS : R(70); | |
4777 %} | |
4778 | |
4779 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4780 dst : E(write)+71; | |
4781 src1 : R(read); | |
4782 MS : R(70); | |
4783 %} | |
4784 | |
4785 // Floating Point Add Float | |
4786 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4787 single_instruction; | |
4788 dst : X(write); | |
4789 src1 : E(read); | |
4790 src2 : E(read); | |
4791 FA : R; | |
4792 %} | |
4793 | |
4794 // Floating Point Add Double | |
4795 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4796 single_instruction; | |
4797 dst : X(write); | |
4798 src1 : E(read); | |
4799 src2 : E(read); | |
4800 FA : R; | |
4801 %} | |
4802 | |
4803 // Floating Point Conditional Move based on integer flags | |
4804 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4805 single_instruction; | |
4806 dst : X(write); | |
4807 src : E(read); | |
4808 cr : R(read); | |
4809 FA : R(2); | |
4810 BR : R(2); | |
4811 %} | |
4812 | |
4813 // Floating Point Conditional Move based on integer flags | |
4814 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4815 single_instruction; | |
4816 dst : X(write); | |
4817 src : E(read); | |
4818 cr : R(read); | |
4819 FA : R(2); | |
4820 BR : R(2); | |
4821 %} | |
4822 | |
4823 // Floating Point Multiply Float | |
4824 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4825 single_instruction; | |
4826 dst : X(write); | |
4827 src1 : E(read); | |
4828 src2 : E(read); | |
4829 FM : R; | |
4830 %} | |
4831 | |
4832 // Floating Point Multiply Double | |
4833 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4834 single_instruction; | |
4835 dst : X(write); | |
4836 src1 : E(read); | |
4837 src2 : E(read); | |
4838 FM : R; | |
4839 %} | |
4840 | |
4841 // Floating Point Divide Float | |
4842 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4843 single_instruction; | |
4844 dst : X(write); | |
4845 src1 : E(read); | |
4846 src2 : E(read); | |
4847 FM : R; | |
4848 FDIV : C(14); | |
4849 %} | |
4850 | |
4851 // Floating Point Divide Double | |
4852 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4853 single_instruction; | |
4854 dst : X(write); | |
4855 src1 : E(read); | |
4856 src2 : E(read); | |
4857 FM : R; | |
4858 FDIV : C(17); | |
4859 %} | |
4860 | |
4861 // Floating Point Move/Negate/Abs Float | |
4862 pipe_class faddF_reg(regF dst, regF src) %{ | |
4863 single_instruction; | |
4864 dst : W(write); | |
4865 src : E(read); | |
4866 FA : R(1); | |
4867 %} | |
4868 | |
4869 // Floating Point Move/Negate/Abs Double | |
4870 pipe_class faddD_reg(regD dst, regD src) %{ | |
4871 single_instruction; | |
4872 dst : W(write); | |
4873 src : E(read); | |
4874 FA : R; | |
4875 %} | |
4876 | |
4877 // Floating Point Convert F->D | |
4878 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4879 single_instruction; | |
4880 dst : X(write); | |
4881 src : E(read); | |
4882 FA : R; | |
4883 %} | |
4884 | |
4885 // Floating Point Convert I->D | |
4886 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4887 single_instruction; | |
4888 dst : X(write); | |
4889 src : E(read); | |
4890 FA : R; | |
4891 %} | |
4892 | |
4893 // Floating Point Convert LHi->D | |
4894 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4895 single_instruction; | |
4896 dst : X(write); | |
4897 src : E(read); | |
4898 FA : R; | |
4899 %} | |
4900 | |
4901 // Floating Point Convert L->D | |
4902 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4903 single_instruction; | |
4904 dst : X(write); | |
4905 src : E(read); | |
4906 FA : R; | |
4907 %} | |
4908 | |
4909 // Floating Point Convert L->F | |
4910 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4911 single_instruction; | |
4912 dst : X(write); | |
4913 src : E(read); | |
4914 FA : R; | |
4915 %} | |
4916 | |
4917 // Floating Point Convert D->F | |
4918 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4919 single_instruction; | |
4920 dst : X(write); | |
4921 src : E(read); | |
4922 FA : R; | |
4923 %} | |
4924 | |
4925 // Floating Point Convert I->L | |
4926 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4927 single_instruction; | |
4928 dst : X(write); | |
4929 src : E(read); | |
4930 FA : R; | |
4931 %} | |
4932 | |
4933 // Floating Point Convert D->F | |
4934 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4935 instruction_count(1); multiple_bundles; | |
4936 dst : X(write)+6; | |
4937 src : E(read); | |
4938 FA : R; | |
4939 %} | |
4940 | |
4941 // Floating Point Convert D->L | |
4942 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4943 instruction_count(1); multiple_bundles; | |
4944 dst : X(write)+6; | |
4945 src : E(read); | |
4946 FA : R; | |
4947 %} | |
4948 | |
4949 // Floating Point Convert F->I | |
4950 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4951 instruction_count(1); multiple_bundles; | |
4952 dst : X(write)+6; | |
4953 src : E(read); | |
4954 FA : R; | |
4955 %} | |
4956 | |
4957 // Floating Point Convert F->L | |
4958 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4959 instruction_count(1); multiple_bundles; | |
4960 dst : X(write)+6; | |
4961 src : E(read); | |
4962 FA : R; | |
4963 %} | |
4964 | |
4965 // Floating Point Convert I->F | |
4966 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4967 single_instruction; | |
4968 dst : X(write); | |
4969 src : E(read); | |
4970 FA : R; | |
4971 %} | |
4972 | |
4973 // Floating Point Compare | |
4974 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4975 single_instruction; | |
4976 cr : X(write); | |
4977 src1 : E(read); | |
4978 src2 : E(read); | |
4979 FA : R; | |
4980 %} | |
4981 | |
4982 // Floating Point Compare | |
4983 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4984 single_instruction; | |
4985 cr : X(write); | |
4986 src1 : E(read); | |
4987 src2 : E(read); | |
4988 FA : R; | |
4989 %} | |
4990 | |
4991 // Floating Add Nop | |
4992 pipe_class fadd_nop() %{ | |
4993 single_instruction; | |
4994 FA : R; | |
4995 %} | |
4996 | |
4997 // Integer Store to Memory | |
4998 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
4999 single_instruction; | |
5000 mem : R(read); | |
5001 src : C(read); | |
5002 MS : R; | |
5003 %} | |
5004 | |
5005 // Integer Store to Memory | |
5006 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
5007 single_instruction; | |
5008 mem : R(read); | |
5009 src : C(read); | |
5010 MS : R; | |
5011 %} | |
5012 | |
5013 // Integer Store Zero to Memory | |
5014 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
5015 single_instruction; | |
5016 mem : R(read); | |
5017 MS : R; | |
5018 %} | |
5019 | |
5020 // Special Stack Slot Store | |
5021 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
5022 single_instruction; | |
5023 stkSlot : R(read); | |
5024 src : C(read); | |
5025 MS : R; | |
5026 %} | |
5027 | |
5028 // Special Stack Slot Store | |
5029 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
5030 instruction_count(2); multiple_bundles; | |
5031 stkSlot : R(read); | |
5032 src : C(read); | |
5033 MS : R(2); | |
5034 %} | |
5035 | |
5036 // Float Store | |
5037 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
5038 single_instruction; | |
5039 mem : R(read); | |
5040 src : C(read); | |
5041 MS : R; | |
5042 %} | |
5043 | |
5044 // Float Store | |
5045 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
5046 single_instruction; | |
5047 mem : R(read); | |
5048 MS : R; | |
5049 %} | |
5050 | |
5051 // Double Store | |
5052 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5053 instruction_count(1); | |
5054 mem : R(read); | |
5055 src : C(read); | |
5056 MS : R; | |
5057 %} | |
5058 | |
5059 // Double Store | |
5060 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5061 single_instruction; | |
5062 mem : R(read); | |
5063 MS : R; | |
5064 %} | |
5065 | |
5066 // Special Stack Slot Float Store | |
5067 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5068 single_instruction; | |
5069 stkSlot : R(read); | |
5070 src : C(read); | |
5071 MS : R; | |
5072 %} | |
5073 | |
5074 // Special Stack Slot Double Store | |
5075 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5076 single_instruction; | |
5077 stkSlot : R(read); | |
5078 src : C(read); | |
5079 MS : R; | |
5080 %} | |
5081 | |
5082 // Integer Load (when sign bit propagation not needed) | |
5083 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5084 single_instruction; | |
5085 mem : R(read); | |
5086 dst : C(write); | |
5087 MS : R; | |
5088 %} | |
5089 | |
5090 // Integer Load from stack operand | |
5091 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5092 single_instruction; | |
5093 mem : R(read); | |
5094 dst : C(write); | |
5095 MS : R; | |
5096 %} | |
5097 | |
5098 // Integer Load (when sign bit propagation or masking is needed) | |
5099 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5100 single_instruction; | |
5101 mem : R(read); | |
5102 dst : M(write); | |
5103 MS : R; | |
5104 %} | |
5105 | |
5106 // Float Load | |
5107 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5108 single_instruction; | |
5109 mem : R(read); | |
5110 dst : M(write); | |
5111 MS : R; | |
5112 %} | |
5113 | |
5114 // Float Load | |
5115 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5116 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5117 mem : R(read); | |
5118 dst : M(write); | |
5119 MS : R; | |
5120 %} | |
5121 | |
5122 // Float Load | |
5123 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5124 single_instruction; | |
5125 stkSlot : R(read); | |
5126 dst : M(write); | |
5127 MS : R; | |
5128 %} | |
5129 | |
5130 // Float Load | |
5131 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5132 single_instruction; | |
5133 stkSlot : R(read); | |
5134 dst : M(write); | |
5135 MS : R; | |
5136 %} | |
5137 | |
5138 // Memory Nop | |
5139 pipe_class mem_nop() %{ | |
5140 single_instruction; | |
5141 MS : R; | |
5142 %} | |
5143 | |
5144 pipe_class sethi(iRegP dst, immI src) %{ | |
5145 single_instruction; | |
5146 dst : E(write); | |
5147 IALU : R; | |
5148 %} | |
5149 | |
5150 pipe_class loadPollP(iRegP poll) %{ | |
5151 single_instruction; | |
5152 poll : R(read); | |
5153 MS : R; | |
5154 %} | |
5155 | |
5156 pipe_class br(Universe br, label labl) %{ | |
5157 single_instruction_with_delay_slot; | |
5158 BR : R; | |
5159 %} | |
5160 | |
5161 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5162 single_instruction_with_delay_slot; | |
5163 cr : E(read); | |
5164 BR : R; | |
5165 %} | |
5166 | |
5167 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5168 single_instruction_with_delay_slot; | |
5169 op1 : E(read); | |
5170 BR : R; | |
5171 MS : R; | |
5172 %} | |
5173 | |
5174 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
5175 single_instruction_with_delay_slot; | |
5176 cr : E(read); | |
5177 BR : R; | |
5178 %} | |
5179 | |
5180 pipe_class br_nop() %{ | |
5181 single_instruction; | |
5182 BR : R; | |
5183 %} | |
5184 | |
5185 pipe_class simple_call(method meth) %{ | |
5186 instruction_count(2); multiple_bundles; force_serialization; | |
5187 fixed_latency(100); | |
5188 BR : R(1); | |
5189 MS : R(1); | |
5190 A0 : R(1); | |
5191 %} | |
5192 | |
5193 pipe_class compiled_call(method meth) %{ | |
5194 instruction_count(1); multiple_bundles; force_serialization; | |
5195 fixed_latency(100); | |
5196 MS : R(1); | |
5197 %} | |
5198 | |
5199 pipe_class call(method meth) %{ | |
5200 instruction_count(0); multiple_bundles; force_serialization; | |
5201 fixed_latency(100); | |
5202 %} | |
5203 | |
5204 pipe_class tail_call(Universe ignore, label labl) %{ | |
5205 single_instruction; has_delay_slot; | |
5206 fixed_latency(100); | |
5207 BR : R(1); | |
5208 MS : R(1); | |
5209 %} | |
5210 | |
5211 pipe_class ret(Universe ignore) %{ | |
5212 single_instruction; has_delay_slot; | |
5213 BR : R(1); | |
5214 MS : R(1); | |
5215 %} | |
5216 | |
5217 pipe_class ret_poll(g3RegP poll) %{ | |
5218 instruction_count(3); has_delay_slot; | |
5219 poll : E(read); | |
5220 MS : R; | |
5221 %} | |
5222 | |
5223 // The real do-nothing guy | |
5224 pipe_class empty( ) %{ | |
5225 instruction_count(0); | |
5226 %} | |
5227 | |
5228 pipe_class long_memory_op() %{ | |
5229 instruction_count(0); multiple_bundles; force_serialization; | |
5230 fixed_latency(25); | |
5231 MS : R(1); | |
5232 %} | |
5233 | |
5234 // Check-cast | |
5235 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5236 array : R(read); | |
5237 match : R(read); | |
5238 IALU : R(2); | |
5239 BR : R(2); | |
5240 MS : R; | |
5241 %} | |
5242 | |
5243 // Convert FPU flags into +1,0,-1 | |
5244 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5245 src1 : E(read); | |
5246 src2 : E(read); | |
5247 dst : E(write); | |
5248 FA : R; | |
5249 MS : R(2); | |
5250 BR : R(2); | |
5251 %} | |
5252 | |
5253 // Compare for p < q, and conditionally add y | |
5254 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5255 p : E(read); | |
5256 q : E(read); | |
5257 y : E(read); | |
5258 IALU : R(3) | |
5259 %} | |
5260 | |
5261 // Perform a compare, then move conditionally in a branch delay slot. | |
5262 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5263 src2 : E(read); | |
5264 srcdst : E(read); | |
5265 IALU : R; | |
5266 BR : R; | |
5267 %} | |
5268 | |
5269 // Define the class for the Nop node | |
5270 define %{ | |
5271 MachNop = ialu_nop; | |
5272 %} | |
5273 | |
5274 %} | |
5275 | |
5276 //----------INSTRUCTIONS------------------------------------------------------- | |
5277 | |
5278 //------------Special Stack Slot instructions - no match rules----------------- | |
5279 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5280 // No match rule to avoid chain rule match. | |
5281 effect(DEF dst, USE src); | |
5282 ins_cost(MEMORY_REF_COST); | |
5283 size(4); | |
5284 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5285 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5286 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5287 ins_pipe(floadF_stk); |
5288 %} | |
5289 | |
5290 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5291 // No match rule to avoid chain rule match. | |
5292 effect(DEF dst, USE src); | |
5293 ins_cost(MEMORY_REF_COST); | |
5294 size(4); | |
5295 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5296 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5297 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5298 ins_pipe(floadD_stk); |
5299 %} | |
5300 | |
5301 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5302 // No match rule to avoid chain rule match. | |
5303 effect(DEF dst, USE src); | |
5304 ins_cost(MEMORY_REF_COST); | |
5305 size(4); | |
5306 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5307 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5308 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5309 ins_pipe(fstoreF_stk_reg); |
5310 %} | |
5311 | |
5312 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5313 // No match rule to avoid chain rule match. | |
5314 effect(DEF dst, USE src); | |
5315 ins_cost(MEMORY_REF_COST); | |
5316 size(4); | |
5317 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5318 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5319 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5320 ins_pipe(fstoreD_stk_reg); |
5321 %} | |
5322 | |
5323 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5324 effect(DEF dst, USE src); | |
5325 ins_cost(MEMORY_REF_COST*2); | |
5326 size(8); | |
5327 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5328 "STW R_G0,$dst.lo" %} | |
5329 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5330 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5331 ins_pipe(lstoreI_stk_reg); |
5332 %} | |
5333 | |
5334 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5335 // No match rule to avoid chain rule match. | |
5336 effect(DEF dst, USE src); | |
5337 ins_cost(MEMORY_REF_COST); | |
5338 size(4); | |
5339 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5340 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5341 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5342 ins_pipe(istore_stk_reg); |
5343 %} | |
5344 | |
5345 //---------- Chain stack slots between similar types -------- | |
5346 | |
5347 // Load integer from stack slot | |
5348 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5349 match(Set dst src); | |
5350 ins_cost(MEMORY_REF_COST); | |
5351 | |
5352 size(4); | |
5353 format %{ "LDUW $src,$dst\t!stk" %} | |
5354 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5355 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5356 ins_pipe(iload_mem); |
5357 %} | |
5358 | |
5359 // Store integer to stack slot | |
5360 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5361 match(Set dst src); | |
5362 ins_cost(MEMORY_REF_COST); | |
5363 | |
5364 size(4); | |
5365 format %{ "STW $src,$dst\t!stk" %} | |
5366 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5367 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5368 ins_pipe(istore_mem_reg); |
5369 %} | |
5370 | |
5371 // Load long from stack slot | |
5372 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5373 match(Set dst src); | |
5374 | |
5375 ins_cost(MEMORY_REF_COST); | |
5376 size(4); | |
5377 format %{ "LDX $src,$dst\t! long" %} | |
5378 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5379 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5380 ins_pipe(iload_mem); |
5381 %} | |
5382 | |
5383 // Store long to stack slot | |
5384 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5385 match(Set dst src); | |
5386 | |
5387 ins_cost(MEMORY_REF_COST); | |
5388 size(4); | |
5389 format %{ "STX $src,$dst\t! long" %} | |
5390 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5391 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5392 ins_pipe(istore_mem_reg); |
5393 %} | |
5394 | |
5395 #ifdef _LP64 | |
5396 // Load pointer from stack slot, 64-bit encoding | |
5397 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5398 match(Set dst src); | |
5399 ins_cost(MEMORY_REF_COST); | |
5400 size(4); | |
5401 format %{ "LDX $src,$dst\t!ptr" %} | |
5402 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5403 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5404 ins_pipe(iload_mem); |
5405 %} | |
5406 | |
5407 // Store pointer to stack slot | |
5408 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5409 match(Set dst src); | |
5410 ins_cost(MEMORY_REF_COST); | |
5411 size(4); | |
5412 format %{ "STX $src,$dst\t!ptr" %} | |
5413 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5414 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5415 ins_pipe(istore_mem_reg); |
5416 %} | |
5417 #else // _LP64 | |
5418 // Load pointer from stack slot, 32-bit encoding | |
5419 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5420 match(Set dst src); | |
5421 ins_cost(MEMORY_REF_COST); | |
5422 format %{ "LDUW $src,$dst\t!ptr" %} | |
5423 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5424 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5425 ins_pipe(iload_mem); |
5426 %} | |
5427 | |
5428 // Store pointer to stack slot | |
5429 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5430 match(Set dst src); | |
5431 ins_cost(MEMORY_REF_COST); | |
5432 format %{ "STW $src,$dst\t!ptr" %} | |
5433 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5434 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5435 ins_pipe(istore_mem_reg); |
5436 %} | |
5437 #endif // _LP64 | |
5438 | |
5439 //------------Special Nop instructions for bundling - no match rules----------- | |
5440 // Nop using the A0 functional unit | |
5441 instruct Nop_A0() %{ | |
5442 ins_cost(0); | |
5443 | |
5444 format %{ "NOP ! Alu Pipeline" %} | |
5445 opcode(Assembler::or_op3, Assembler::arith_op); | |
5446 ins_encode( form2_nop() ); | |
5447 ins_pipe(ialu_nop_A0); | |
5448 %} | |
5449 | |
5450 // Nop using the A1 functional unit | |
5451 instruct Nop_A1( ) %{ | |
5452 ins_cost(0); | |
5453 | |
5454 format %{ "NOP ! Alu Pipeline" %} | |
5455 opcode(Assembler::or_op3, Assembler::arith_op); | |
5456 ins_encode( form2_nop() ); | |
5457 ins_pipe(ialu_nop_A1); | |
5458 %} | |
5459 | |
5460 // Nop using the memory functional unit | |
5461 instruct Nop_MS( ) %{ | |
5462 ins_cost(0); | |
5463 | |
5464 format %{ "NOP ! Memory Pipeline" %} | |
5465 ins_encode( emit_mem_nop ); | |
5466 ins_pipe(mem_nop); | |
5467 %} | |
5468 | |
5469 // Nop using the floating add functional unit | |
5470 instruct Nop_FA( ) %{ | |
5471 ins_cost(0); | |
5472 | |
5473 format %{ "NOP ! Floating Add Pipeline" %} | |
5474 ins_encode( emit_fadd_nop ); | |
5475 ins_pipe(fadd_nop); | |
5476 %} | |
5477 | |
5478 // Nop using the branch functional unit | |
5479 instruct Nop_BR( ) %{ | |
5480 ins_cost(0); | |
5481 | |
5482 format %{ "NOP ! Branch Pipeline" %} | |
5483 ins_encode( emit_br_nop ); | |
5484 ins_pipe(br_nop); | |
5485 %} | |
5486 | |
5487 //----------Load/Store/Move Instructions--------------------------------------- | |
5488 //----------Load Instructions-------------------------------------------------- | |
5489 // Load Byte (8bit signed) | |
5490 instruct loadB(iRegI dst, memory mem) %{ | |
5491 match(Set dst (LoadB mem)); | |
5492 ins_cost(MEMORY_REF_COST); | |
5493 | |
5494 size(4); | |
624 | 5495 format %{ "LDSB $mem,$dst\t! byte" %} |
5496 opcode(Assembler::ldsb_op3); | |
5497 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5498 ins_pipe(iload_mask_mem); | |
5499 %} | |
5500 | |
5501 // Load Byte (8bit signed) into a Long Register | |
5502 instruct loadB2L(iRegL dst, memory mem) %{ | |
5503 match(Set dst (ConvI2L (LoadB mem))); | |
5504 ins_cost(MEMORY_REF_COST); | |
5505 | |
5506 size(4); | |
5507 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
0 | 5508 opcode(Assembler::ldsb_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5509 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5510 ins_pipe(iload_mask_mem); |
5511 %} | |
5512 | |
624 | 5513 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5514 instruct loadUB(iRegI dst, memory mem) %{ | |
5515 match(Set dst (LoadUB mem)); | |
0 | 5516 ins_cost(MEMORY_REF_COST); |
5517 | |
5518 size(4); | |
624 | 5519 format %{ "LDUB $mem,$dst\t! ubyte" %} |
5520 opcode(Assembler::ldub_op3); | |
5521 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5522 ins_pipe(iload_mask_mem); | |
5523 %} | |
5524 | |
5525 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5526 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5527 match(Set dst (ConvI2L (LoadUB mem))); | |
5528 ins_cost(MEMORY_REF_COST); | |
5529 | |
5530 size(4); | |
5531 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
0 | 5532 opcode(Assembler::ldub_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5533 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5534 ins_pipe(iload_mask_mem); |
5535 %} | |
5536 | |
624 | 5537 // Load Short (16bit signed) |
5538 instruct loadS(iRegI dst, memory mem) %{ | |
5539 match(Set dst (LoadS mem)); | |
5540 ins_cost(MEMORY_REF_COST); | |
5541 | |
5542 size(4); | |
5543 format %{ "LDSH $mem,$dst\t! short" %} | |
5544 opcode(Assembler::ldsh_op3); | |
5545 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5546 ins_pipe(iload_mask_mem); | |
5547 %} | |
5548 | |
5549 // Load Short (16bit signed) into a Long Register | |
5550 instruct loadS2L(iRegL dst, memory mem) %{ | |
5551 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5552 ins_cost(MEMORY_REF_COST); |
5553 | |
5554 size(4); | |
624 | 5555 format %{ "LDSH $mem,$dst\t! short -> long" %} |
5556 opcode(Assembler::ldsh_op3); | |
5557 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5558 ins_pipe(iload_mask_mem); | |
5559 %} | |
5560 | |
5561 // Load Unsigned Short/Char (16bit UNsigned) | |
5562 instruct loadUS(iRegI dst, memory mem) %{ | |
5563 match(Set dst (LoadUS mem)); | |
5564 ins_cost(MEMORY_REF_COST); | |
5565 | |
5566 size(4); | |
5567 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
5568 opcode(Assembler::lduh_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5569 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5570 ins_pipe(iload_mask_mem); |
5571 %} | |
5572 | |
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
551
diff
changeset
|
5573 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5574 instruct loadUS2L(iRegL dst, memory mem) %{ |
5575 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5576 ins_cost(MEMORY_REF_COST); |
5577 | |
5578 size(4); | |
624 | 5579 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
0 | 5580 opcode(Assembler::lduh_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5581 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5582 ins_pipe(iload_mask_mem); |
5583 %} | |
5584 | |
5585 // Load Integer | |
5586 instruct loadI(iRegI dst, memory mem) %{ | |
5587 match(Set dst (LoadI mem)); | |
5588 ins_cost(MEMORY_REF_COST); | |
624 | 5589 |
5590 size(4); | |
5591 format %{ "LDUW $mem,$dst\t! int" %} | |
5592 opcode(Assembler::lduw_op3); | |
5593 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5594 ins_pipe(iload_mem); | |
5595 %} | |
5596 | |
5597 // Load Integer into a Long Register | |
5598 instruct loadI2L(iRegL dst, memory mem) %{ | |
5599 match(Set dst (ConvI2L (LoadI mem))); | |
5600 ins_cost(MEMORY_REF_COST); | |
5601 | |
5602 size(4); | |
5603 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
5604 opcode(Assembler::ldsw_op3); | |
5605 ins_encode(simple_form3_mem_reg( mem, dst ) ); | |
5606 ins_pipe(iload_mem); | |
5607 %} | |
5608 | |
5609 // Load Unsigned Integer into a Long Register | |
5610 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5611 match(Set dst (LoadUI2L mem)); | |
5612 ins_cost(MEMORY_REF_COST); | |
5613 | |
5614 size(4); | |
5615 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
0 | 5616 opcode(Assembler::lduw_op3); |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5617 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5618 ins_pipe(iload_mem); |
5619 %} | |
5620 | |
5621 // Load Long - aligned | |
5622 instruct loadL(iRegL dst, memory mem ) %{ | |
5623 match(Set dst (LoadL mem)); | |
5624 ins_cost(MEMORY_REF_COST); | |
624 | 5625 |
0 | 5626 size(4); |
5627 format %{ "LDX $mem,$dst\t! long" %} | |
5628 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5629 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5630 ins_pipe(iload_mem); |
5631 %} | |
5632 | |
5633 // Load Long - UNaligned | |
5634 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5635 match(Set dst (LoadL_unaligned mem)); | |
5636 effect(KILL tmp); | |
5637 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5638 size(16); | |
5639 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5640 "\tLDUW $mem ,$dst\n" | |
5641 "\tSLLX #32, $dst, $dst\n" | |
5642 "\tOR $dst, R_O7, $dst" %} | |
5643 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5644 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5645 ins_pipe(iload_mem); |
5646 %} | |
5647 | |
5648 // Load Aligned Packed Byte into a Double Register | |
5649 instruct loadA8B(regD dst, memory mem) %{ | |
5650 match(Set dst (Load8B mem)); | |
5651 ins_cost(MEMORY_REF_COST); | |
5652 size(4); | |
5653 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
5654 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5655 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5656 ins_pipe(floadD_mem); |
5657 %} | |
5658 | |
5659 // Load Aligned Packed Char into a Double Register | |
5660 instruct loadA4C(regD dst, memory mem) %{ | |
5661 match(Set dst (Load4C mem)); | |
5662 ins_cost(MEMORY_REF_COST); | |
5663 size(4); | |
5664 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
5665 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5666 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5667 ins_pipe(floadD_mem); |
5668 %} | |
5669 | |
5670 // Load Aligned Packed Short into a Double Register | |
5671 instruct loadA4S(regD dst, memory mem) %{ | |
5672 match(Set dst (Load4S mem)); | |
5673 ins_cost(MEMORY_REF_COST); | |
5674 size(4); | |
5675 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
5676 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5677 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5678 ins_pipe(floadD_mem); |
5679 %} | |
5680 | |
5681 // Load Aligned Packed Int into a Double Register | |
5682 instruct loadA2I(regD dst, memory mem) %{ | |
5683 match(Set dst (Load2I mem)); | |
5684 ins_cost(MEMORY_REF_COST); | |
5685 size(4); | |
5686 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
5687 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5688 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5689 ins_pipe(floadD_mem); |
5690 %} | |
5691 | |
5692 // Load Range | |
5693 instruct loadRange(iRegI dst, memory mem) %{ | |
5694 match(Set dst (LoadRange mem)); | |
5695 ins_cost(MEMORY_REF_COST); | |
5696 | |
5697 size(4); | |
5698 format %{ "LDUW $mem,$dst\t! range" %} | |
5699 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5700 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5701 ins_pipe(iload_mem); |
5702 %} | |
5703 | |
5704 // Load Integer into %f register (for fitos/fitod) | |
5705 instruct loadI_freg(regF dst, memory mem) %{ | |
5706 match(Set dst (LoadI mem)); | |
5707 ins_cost(MEMORY_REF_COST); | |
5708 size(4); | |
5709 | |
5710 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5711 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5712 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5713 ins_pipe(floadF_mem); |
5714 %} | |
5715 | |
5716 // Load Pointer | |
5717 instruct loadP(iRegP dst, memory mem) %{ | |
5718 match(Set dst (LoadP mem)); | |
5719 ins_cost(MEMORY_REF_COST); | |
5720 size(4); | |
5721 | |
5722 #ifndef _LP64 | |
5723 format %{ "LDUW $mem,$dst\t! ptr" %} | |
5724 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
5725 #else | |
5726 format %{ "LDX $mem,$dst\t! ptr" %} | |
5727 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
5728 #endif | |
5729 ins_encode( form3_mem_reg( mem, dst ) ); | |
5730 ins_pipe(iload_mem); | |
5731 %} | |
5732 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5733 // Load Compressed Pointer |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5734 instruct loadN(iRegN dst, memory mem) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5735 match(Set dst (LoadN mem)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5736 ins_cost(MEMORY_REF_COST); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5737 size(4); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5738 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5739 format %{ "LDUW $mem,$dst\t! compressed ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5740 ins_encode %{ |
624 | 5741 Register index = $mem$$index$$Register; |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5742 if (index != G0) { |
624 | 5743 __ lduw($mem$$base$$Register, index, $dst$$Register); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5744 } else { |
624 | 5745 __ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5746 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5747 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5748 ins_pipe(iload_mem); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5749 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5750 |
0 | 5751 // Load Klass Pointer |
5752 instruct loadKlass(iRegP dst, memory mem) %{ | |
5753 match(Set dst (LoadKlass mem)); | |
5754 ins_cost(MEMORY_REF_COST); | |
5755 size(4); | |
5756 | |
5757 #ifndef _LP64 | |
5758 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
5759 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
5760 #else | |
5761 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
5762 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
5763 #endif | |
5764 ins_encode( form3_mem_reg( mem, dst ) ); | |
5765 ins_pipe(iload_mem); | |
5766 %} | |
5767 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5768 // Load narrow Klass Pointer |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5769 instruct loadNKlass(iRegN dst, memory mem) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5770 match(Set dst (LoadNKlass mem)); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5771 ins_cost(MEMORY_REF_COST); |
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
164
diff
changeset
|
5772 size(4); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5773 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5774 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5775 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5776 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5777 Register base = as_Register($mem$$base); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5778 Register index = as_Register($mem$$index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5779 Register dst = $dst$$Register; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5780 if (index != G0) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5781 __ lduw(base, index, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5782 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5783 __ lduw(base, $mem$$disp, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5784 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5785 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5786 ins_pipe(iload_mem); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5787 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5788 |
0 | 5789 // Load Double |
5790 instruct loadD(regD dst, memory mem) %{ | |
5791 match(Set dst (LoadD mem)); | |
5792 ins_cost(MEMORY_REF_COST); | |
5793 | |
5794 size(4); | |
5795 format %{ "LDDF $mem,$dst" %} | |
5796 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5797 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5798 ins_pipe(floadD_mem); |
5799 %} | |
5800 | |
5801 // Load Double - UNaligned | |
5802 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
5803 match(Set dst (LoadD_unaligned mem)); | |
5804 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5805 size(8); | |
5806 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
5807 "\tLDF $mem+4,$dst.lo\t!" %} | |
5808 opcode(Assembler::ldf_op3); | |
5809 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
5810 ins_pipe(iload_mem); | |
5811 %} | |
5812 | |
5813 // Load Float | |
5814 instruct loadF(regF dst, memory mem) %{ | |
5815 match(Set dst (LoadF mem)); | |
5816 ins_cost(MEMORY_REF_COST); | |
5817 | |
5818 size(4); | |
5819 format %{ "LDF $mem,$dst" %} | |
5820 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5821 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5822 ins_pipe(floadF_mem); |
5823 %} | |
5824 | |
5825 // Load Constant | |
5826 instruct loadConI( iRegI dst, immI src ) %{ | |
5827 match(Set dst src); | |
5828 ins_cost(DEFAULT_COST * 3/2); | |
5829 format %{ "SET $src,$dst" %} | |
5830 ins_encode( Set32(src, dst) ); | |
5831 ins_pipe(ialu_hi_lo_reg); | |
5832 %} | |
5833 | |
5834 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
5835 match(Set dst src); | |
5836 | |
5837 size(4); | |
5838 format %{ "MOV $src,$dst" %} | |
5839 ins_encode( Set13( src, dst ) ); | |
5840 ins_pipe(ialu_imm); | |
5841 %} | |
5842 | |
5843 instruct loadConP(iRegP dst, immP src) %{ | |
5844 match(Set dst src); | |
5845 ins_cost(DEFAULT_COST * 3/2); | |
5846 format %{ "SET $src,$dst\t!ptr" %} | |
5847 // This rule does not use "expand" unlike loadConI because then | |
5848 // the result type is not known to be an Oop. An ADLC | |
5849 // enhancement will be needed to make that work - not worth it! | |
5850 | |
5851 ins_encode( SetPtr( src, dst ) ); | |
5852 ins_pipe(loadConP); | |
5853 | |
5854 %} | |
5855 | |
5856 instruct loadConP0(iRegP dst, immP0 src) %{ | |
5857 match(Set dst src); | |
5858 | |
5859 size(4); | |
5860 format %{ "CLR $dst\t!ptr" %} | |
5861 ins_encode( SetNull( dst ) ); | |
5862 ins_pipe(ialu_imm); | |
5863 %} | |
5864 | |
5865 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
5866 match(Set dst src); | |
5867 ins_cost(DEFAULT_COST); | |
5868 format %{ "SET $src,$dst\t!ptr" %} | |
5869 ins_encode %{ | |
5870 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page()); | |
5871 __ sethi(polling_page, false ); | |
5872 %} | |
5873 ins_pipe(loadConP_poll); | |
5874 %} | |
5875 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5876 instruct loadConN0(iRegN dst, immN0 src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5877 match(Set dst src); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5878 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5879 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5880 format %{ "CLR $dst\t! compressed NULL ptr" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5881 ins_encode( SetNull( dst ) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5882 ins_pipe(ialu_imm); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5883 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5884 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5885 instruct loadConN(iRegN dst, immN src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5886 match(Set dst src); |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5887 ins_cost(DEFAULT_COST * 3/2); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5888 format %{ "SET $src,$dst\t! compressed ptr" %} |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5889 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5890 Register dst = $dst$$Register; |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5891 __ set_narrow_oop((jobject)$src$$constant, dst); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5892 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5893 ins_pipe(ialu_hi_lo_reg); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5894 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
5895 |
0 | 5896 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
5897 // %%% maybe this should work like loadConD | |
5898 match(Set dst src); | |
5899 effect(KILL tmp); | |
5900 ins_cost(DEFAULT_COST * 4); | |
5901 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
5902 ins_encode( LdImmL(src, dst, tmp) ); | |
5903 ins_pipe(loadConL); | |
5904 %} | |
5905 | |
5906 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
5907 match(Set dst src); | |
5908 ins_cost(DEFAULT_COST); | |
5909 size(4); | |
5910 format %{ "CLR $dst\t! long" %} | |
5911 ins_encode( Set13( src, dst ) ); | |
5912 ins_pipe(ialu_imm); | |
5913 %} | |
5914 | |
5915 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
5916 match(Set dst src); | |
5917 ins_cost(DEFAULT_COST * 2); | |
5918 | |
5919 size(4); | |
5920 format %{ "MOV $src,$dst\t! long" %} | |
5921 ins_encode( Set13( src, dst ) ); | |
5922 ins_pipe(ialu_imm); | |
5923 %} | |
5924 | |
5925 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
5926 match(Set dst src); | |
5927 effect(KILL tmp); | |
5928 | |
5929 #ifdef _LP64 | |
5930 size(36); | |
5931 #else | |
5932 size(8); | |
5933 #endif | |
5934 | |
5935 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
5936 "LDF [$tmp+lo(&$src)],$dst" %} | |
5937 ins_encode( LdImmF(src, dst, tmp) ); | |
5938 ins_pipe(loadConFD); | |
5939 %} | |
5940 | |
5941 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
5942 match(Set dst src); | |
5943 effect(KILL tmp); | |
5944 | |
5945 #ifdef _LP64 | |
5946 size(36); | |
5947 #else | |
5948 size(8); | |
5949 #endif | |
5950 | |
5951 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
5952 "LDDF [$tmp+lo(&$src)],$dst" %} | |
5953 ins_encode( LdImmD(src, dst, tmp) ); | |
5954 ins_pipe(loadConFD); | |
5955 %} | |
5956 | |
5957 // Prefetch instructions. | |
5958 // Must be safe to execute with invalid address (cannot fault). | |
5959 | |
5960 instruct prefetchr( memory mem ) %{ | |
5961 match( PrefetchRead mem ); | |
5962 ins_cost(MEMORY_REF_COST); | |
5963 | |
5964 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
5965 opcode(Assembler::prefetch_op3); | |
5966 ins_encode( form3_mem_prefetch_read( mem ) ); | |
5967 ins_pipe(iload_mem); | |
5968 %} | |
5969 | |
5970 instruct prefetchw( memory mem ) %{ | |
5971 match( PrefetchWrite mem ); | |
5972 ins_cost(MEMORY_REF_COST); | |
5973 | |
5974 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
5975 opcode(Assembler::prefetch_op3); | |
5976 ins_encode( form3_mem_prefetch_write( mem ) ); | |
5977 ins_pipe(iload_mem); | |
5978 %} | |
5979 | |
5980 | |
5981 //----------Store Instructions------------------------------------------------- | |
5982 // Store Byte | |
5983 instruct storeB(memory mem, iRegI src) %{ | |
5984 match(Set mem (StoreB mem src)); | |
5985 ins_cost(MEMORY_REF_COST); | |
5986 | |
5987 size(4); | |
5988 format %{ "STB $src,$mem\t! byte" %} | |
5989 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5990 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 5991 ins_pipe(istore_mem_reg); |
5992 %} | |
5993 | |
5994 instruct storeB0(memory mem, immI0 src) %{ | |
5995 match(Set mem (StoreB mem src)); | |
5996 ins_cost(MEMORY_REF_COST); | |
5997 | |
5998 size(4); | |
5999 format %{ "STB $src,$mem\t! byte" %} | |
6000 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6001 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6002 ins_pipe(istore_mem_zero); |
6003 %} | |
6004 | |
6005 instruct storeCM0(memory mem, immI0 src) %{ | |
6006 match(Set mem (StoreCM mem src)); | |
6007 ins_cost(MEMORY_REF_COST); | |
6008 | |
6009 size(4); | |
6010 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6011 opcode(Assembler::stb_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6012 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6013 ins_pipe(istore_mem_zero); |
6014 %} | |
6015 | |
6016 // Store Char/Short | |
6017 instruct storeC(memory mem, iRegI src) %{ | |
6018 match(Set mem (StoreC mem src)); | |
6019 ins_cost(MEMORY_REF_COST); | |
6020 | |
6021 size(4); | |
6022 format %{ "STH $src,$mem\t! short" %} | |
6023 opcode(Assembler::sth_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6024 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6025 ins_pipe(istore_mem_reg); |
6026 %} | |
6027 | |
6028 instruct storeC0(memory mem, immI0 src) %{ | |
6029 match(Set mem (StoreC mem src)); | |
6030 ins_cost(MEMORY_REF_COST); | |
6031 | |
6032 size(4); | |
6033 format %{ "STH $src,$mem\t! short" %} | |
6034 opcode(Assembler::sth_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6035 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6036 ins_pipe(istore_mem_zero); |
6037 %} | |
6038 | |
6039 // Store Integer | |
6040 instruct storeI(memory mem, iRegI src) %{ | |
6041 match(Set mem (StoreI mem src)); | |
6042 ins_cost(MEMORY_REF_COST); | |
6043 | |
6044 size(4); | |
6045 format %{ "STW $src,$mem" %} | |
6046 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6047 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6048 ins_pipe(istore_mem_reg); |
6049 %} | |
6050 | |
6051 // Store Long | |
6052 instruct storeL(memory mem, iRegL src) %{ | |
6053 match(Set mem (StoreL mem src)); | |
6054 ins_cost(MEMORY_REF_COST); | |
6055 size(4); | |
6056 format %{ "STX $src,$mem\t! long" %} | |
6057 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6058 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6059 ins_pipe(istore_mem_reg); |
6060 %} | |
6061 | |
6062 instruct storeI0(memory mem, immI0 src) %{ | |
6063 match(Set mem (StoreI mem src)); | |
6064 ins_cost(MEMORY_REF_COST); | |
6065 | |
6066 size(4); | |
6067 format %{ "STW $src,$mem" %} | |
6068 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6069 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6070 ins_pipe(istore_mem_zero); |
6071 %} | |
6072 | |
6073 instruct storeL0(memory mem, immL0 src) %{ | |
6074 match(Set mem (StoreL mem src)); | |
6075 ins_cost(MEMORY_REF_COST); | |
6076 | |
6077 size(4); | |
6078 format %{ "STX $src,$mem" %} | |
6079 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6080 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6081 ins_pipe(istore_mem_zero); |
6082 %} | |
6083 | |
6084 // Store Integer from float register (used after fstoi) | |
6085 instruct storeI_Freg(memory mem, regF src) %{ | |
6086 match(Set mem (StoreI mem src)); | |
6087 ins_cost(MEMORY_REF_COST); | |
6088 | |
6089 size(4); | |
6090 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6091 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6092 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6093 ins_pipe(fstoreF_mem_reg); |
6094 %} | |
6095 | |
6096 // Store Pointer | |
6097 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6098 match(Set dst (StoreP dst src)); | |
6099 ins_cost(MEMORY_REF_COST); | |
6100 size(4); | |
6101 | |
6102 #ifndef _LP64 | |
6103 format %{ "STW $src,$dst\t! ptr" %} | |
6104 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6105 #else | |
6106 format %{ "STX $src,$dst\t! ptr" %} | |
6107 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6108 #endif | |
6109 ins_encode( form3_mem_reg( dst, src ) ); | |
6110 ins_pipe(istore_mem_spORreg); | |
6111 %} | |
6112 | |
6113 instruct storeP0(memory dst, immP0 src) %{ | |
6114 match(Set dst (StoreP dst src)); | |
6115 ins_cost(MEMORY_REF_COST); | |
6116 size(4); | |
6117 | |
6118 #ifndef _LP64 | |
6119 format %{ "STW $src,$dst\t! ptr" %} | |
6120 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6121 #else | |
6122 format %{ "STX $src,$dst\t! ptr" %} | |
6123 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6124 #endif | |
6125 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6126 ins_pipe(istore_mem_zero); | |
6127 %} | |
6128 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6129 // Store Compressed Pointer |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6130 instruct storeN(memory dst, iRegN src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6131 match(Set dst (StoreN dst src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6132 ins_cost(MEMORY_REF_COST); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6133 size(4); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6134 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6135 format %{ "STW $src,$dst\t! compressed ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6136 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6137 Register base = as_Register($dst$$base); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6138 Register index = as_Register($dst$$index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6139 Register src = $src$$Register; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6140 if (index != G0) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6141 __ stw(src, base, index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6142 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6143 __ stw(src, base, $dst$$disp); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6144 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6145 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6146 ins_pipe(istore_mem_spORreg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6147 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6148 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6149 instruct storeN0(memory dst, immN0 src) %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6150 match(Set dst (StoreN dst src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6151 ins_cost(MEMORY_REF_COST); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6152 size(4); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6153 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6154 format %{ "STW $src,$dst\t! compressed ptr" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6155 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6156 Register base = as_Register($dst$$base); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6157 Register index = as_Register($dst$$index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6158 if (index != G0) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6159 __ stw(0, base, index); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6160 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6161 __ stw(0, base, $dst$$disp); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6162 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6163 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6164 ins_pipe(istore_mem_zero); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6165 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6166 |
0 | 6167 // Store Double |
6168 instruct storeD( memory mem, regD src) %{ | |
6169 match(Set mem (StoreD mem src)); | |
6170 ins_cost(MEMORY_REF_COST); | |
6171 | |
6172 size(4); | |
6173 format %{ "STDF $src,$mem" %} | |
6174 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6175 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6176 ins_pipe(fstoreD_mem_reg); |
6177 %} | |
6178 | |
6179 instruct storeD0( memory mem, immD0 src) %{ | |
6180 match(Set mem (StoreD mem src)); | |
6181 ins_cost(MEMORY_REF_COST); | |
6182 | |
6183 size(4); | |
6184 format %{ "STX $src,$mem" %} | |
6185 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6186 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6187 ins_pipe(fstoreD_mem_zero); |
6188 %} | |
6189 | |
6190 // Store Float | |
6191 instruct storeF( memory mem, regF src) %{ | |
6192 match(Set mem (StoreF mem src)); | |
6193 ins_cost(MEMORY_REF_COST); | |
6194 | |
6195 size(4); | |
6196 format %{ "STF $src,$mem" %} | |
6197 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6198 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6199 ins_pipe(fstoreF_mem_reg); |
6200 %} | |
6201 | |
6202 instruct storeF0( memory mem, immF0 src) %{ | |
6203 match(Set mem (StoreF mem src)); | |
6204 ins_cost(MEMORY_REF_COST); | |
6205 | |
6206 size(4); | |
6207 format %{ "STW $src,$mem\t! storeF0" %} | |
6208 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6209 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6210 ins_pipe(fstoreF_mem_zero); |
6211 %} | |
6212 | |
6213 // Store Aligned Packed Bytes in Double register to memory | |
6214 instruct storeA8B(memory mem, regD src) %{ | |
6215 match(Set mem (Store8B mem src)); | |
6216 ins_cost(MEMORY_REF_COST); | |
6217 size(4); | |
6218 format %{ "STDF $src,$mem\t! packed8B" %} | |
6219 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6220 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6221 ins_pipe(fstoreD_mem_reg); |
6222 %} | |
6223 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6224 // Convert oop pointer into compressed form |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6225 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6226 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6227 match(Set dst (EncodeP src)); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6228 format %{ "encode_heap_oop $src, $dst" %} |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6229 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6230 __ encode_heap_oop($src$$Register, $dst$$Register); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6231 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6232 ins_pipe(ialu_reg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6233 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6234 |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6235 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6236 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6237 match(Set dst (EncodeP src)); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6238 format %{ "encode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6239 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6240 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6241 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6242 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6243 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6244 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6245 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6246 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6247 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6248 match(Set dst (DecodeN src)); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6249 format %{ "decode_heap_oop $src, $dst" %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6250 ins_encode %{ |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6251 __ decode_heap_oop($src$$Register, $dst$$Register); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6252 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6253 ins_pipe(ialu_reg); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6254 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6255 |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6256 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6257 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
181
diff
changeset
|
6258 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6259 match(Set dst (DecodeN src)); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6260 format %{ "decode_heap_oop_not_null $src, $dst" %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6261 ins_encode %{ |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6262 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6263 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6264 ins_pipe(ialu_reg); |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6265 %} |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6266 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6267 |
0 | 6268 // Store Zero into Aligned Packed Bytes |
6269 instruct storeA8B0(memory mem, immI0 zero) %{ | |
6270 match(Set mem (Store8B mem zero)); | |
6271 ins_cost(MEMORY_REF_COST); | |
6272 size(4); | |
6273 format %{ "STX $zero,$mem\t! packed8B" %} | |
6274 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6275 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6276 ins_pipe(fstoreD_mem_zero); |
6277 %} | |
6278 | |
6279 // Store Aligned Packed Chars/Shorts in Double register to memory | |
6280 instruct storeA4C(memory mem, regD src) %{ | |
6281 match(Set mem (Store4C mem src)); | |
6282 ins_cost(MEMORY_REF_COST); | |
6283 size(4); | |
6284 format %{ "STDF $src,$mem\t! packed4C" %} | |
6285 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6286 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6287 ins_pipe(fstoreD_mem_reg); |
6288 %} | |
6289 | |
6290 // Store Zero into Aligned Packed Chars/Shorts | |
6291 instruct storeA4C0(memory mem, immI0 zero) %{ | |
6292 match(Set mem (Store4C mem (Replicate4C zero))); | |
6293 ins_cost(MEMORY_REF_COST); | |
6294 size(4); | |
6295 format %{ "STX $zero,$mem\t! packed4C" %} | |
6296 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6297 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6298 ins_pipe(fstoreD_mem_zero); |
6299 %} | |
6300 | |
6301 // Store Aligned Packed Ints in Double register to memory | |
6302 instruct storeA2I(memory mem, regD src) %{ | |
6303 match(Set mem (Store2I mem src)); | |
6304 ins_cost(MEMORY_REF_COST); | |
6305 size(4); | |
6306 format %{ "STDF $src,$mem\t! packed2I" %} | |
6307 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6308 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6309 ins_pipe(fstoreD_mem_reg); |
6310 %} | |
6311 | |
6312 // Store Zero into Aligned Packed Ints | |
6313 instruct storeA2I0(memory mem, immI0 zero) %{ | |
6314 match(Set mem (Store2I mem zero)); | |
6315 ins_cost(MEMORY_REF_COST); | |
6316 size(4); | |
6317 format %{ "STX $zero,$mem\t! packed2I" %} | |
6318 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6319 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6320 ins_pipe(fstoreD_mem_zero); |
6321 %} | |
6322 | |
6323 | |
6324 //----------MemBar Instructions----------------------------------------------- | |
6325 // Memory barrier flavors | |
6326 | |
6327 instruct membar_acquire() %{ | |
6328 match(MemBarAcquire); | |
6329 ins_cost(4*MEMORY_REF_COST); | |
6330 | |
6331 size(0); | |
6332 format %{ "MEMBAR-acquire" %} | |
6333 ins_encode( enc_membar_acquire ); | |
6334 ins_pipe(long_memory_op); | |
6335 %} | |
6336 | |
6337 instruct membar_acquire_lock() %{ | |
6338 match(MemBarAcquire); | |
6339 predicate(Matcher::prior_fast_lock(n)); | |
6340 ins_cost(0); | |
6341 | |
6342 size(0); | |
6343 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6344 ins_encode( ); | |
6345 ins_pipe(empty); | |
6346 %} | |
6347 | |
6348 instruct membar_release() %{ | |
6349 match(MemBarRelease); | |
6350 ins_cost(4*MEMORY_REF_COST); | |
6351 | |
6352 size(0); | |
6353 format %{ "MEMBAR-release" %} | |
6354 ins_encode( enc_membar_release ); | |
6355 ins_pipe(long_memory_op); | |
6356 %} | |
6357 | |
6358 instruct membar_release_lock() %{ | |
6359 match(MemBarRelease); | |
6360 predicate(Matcher::post_fast_unlock(n)); | |
6361 ins_cost(0); | |
6362 | |
6363 size(0); | |
6364 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6365 ins_encode( ); | |
6366 ins_pipe(empty); | |
6367 %} | |
6368 | |
6369 instruct membar_volatile() %{ | |
6370 match(MemBarVolatile); | |
6371 ins_cost(4*MEMORY_REF_COST); | |
6372 | |
6373 size(4); | |
6374 format %{ "MEMBAR-volatile" %} | |
6375 ins_encode( enc_membar_volatile ); | |
6376 ins_pipe(long_memory_op); | |
6377 %} | |
6378 | |
6379 instruct unnecessary_membar_volatile() %{ | |
6380 match(MemBarVolatile); | |
6381 predicate(Matcher::post_store_load_barrier(n)); | |
6382 ins_cost(0); | |
6383 | |
6384 size(0); | |
6385 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6386 ins_encode( ); | |
6387 ins_pipe(empty); | |
6388 %} | |
6389 | |
6390 //----------Register Move Instructions----------------------------------------- | |
6391 instruct roundDouble_nop(regD dst) %{ | |
6392 match(Set dst (RoundDouble dst)); | |
6393 ins_cost(0); | |
6394 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6395 ins_encode( ); | |
6396 ins_pipe(empty); | |
6397 %} | |
6398 | |
6399 | |
6400 instruct roundFloat_nop(regF dst) %{ | |
6401 match(Set dst (RoundFloat dst)); | |
6402 ins_cost(0); | |
6403 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6404 ins_encode( ); | |
6405 ins_pipe(empty); | |
6406 %} | |
6407 | |
6408 | |
6409 // Cast Index to Pointer for unsafe natives | |
6410 instruct castX2P(iRegX src, iRegP dst) %{ | |
6411 match(Set dst (CastX2P src)); | |
6412 | |
6413 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6414 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6415 ins_pipe(ialu_reg); | |
6416 %} | |
6417 | |
6418 // Cast Pointer to Index for unsafe natives | |
6419 instruct castP2X(iRegP src, iRegX dst) %{ | |
6420 match(Set dst (CastP2X src)); | |
6421 | |
6422 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6423 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6424 ins_pipe(ialu_reg); | |
6425 %} | |
6426 | |
6427 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6428 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6429 match(Set stkSlot src); // chain rule | |
6430 ins_cost(MEMORY_REF_COST); | |
6431 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6432 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6433 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6434 ins_pipe(fstoreD_stk_reg); |
6435 %} | |
6436 | |
6437 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6438 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6439 match(Set dst stkSlot); // chain rule | |
6440 ins_cost(MEMORY_REF_COST); | |
6441 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6442 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6443 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6444 ins_pipe(floadD_stk); |
6445 %} | |
6446 | |
6447 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6448 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6449 match(Set stkSlot src); // chain rule | |
6450 ins_cost(MEMORY_REF_COST); | |
6451 format %{ "STF $src,$stkSlot\t!stk" %} | |
6452 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6453 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6454 ins_pipe(fstoreF_stk_reg); |
6455 %} | |
6456 | |
6457 //----------Conditional Move--------------------------------------------------- | |
6458 // Conditional move | |
6459 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6460 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6461 ins_cost(150); | |
6462 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6463 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6464 ins_pipe(ialu_reg); | |
6465 %} | |
6466 | |
6467 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6468 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6469 ins_cost(140); | |
6470 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6471 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6472 ins_pipe(ialu_imm); | |
6473 %} | |
6474 | |
6475 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6476 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6477 ins_cost(150); | |
6478 size(4); | |
6479 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6480 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6481 ins_pipe(ialu_reg); | |
6482 %} | |
6483 | |
6484 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6485 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6486 ins_cost(140); | |
6487 size(4); | |
6488 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6489 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6490 ins_pipe(ialu_imm); | |
6491 %} | |
6492 | |
81
dee7a3f3dc9d
6636352: Unit tests for supplementary character support fail with -XX:+AggressiveOpts
never
parents:
0
diff
changeset
|
6493 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6494 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6495 ins_cost(150); | |
6496 size(4); | |
6497 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6498 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6499 ins_pipe(ialu_reg); | |
6500 %} | |
6501 | |
81
dee7a3f3dc9d
6636352: Unit tests for supplementary character support fail with -XX:+AggressiveOpts
never
parents:
0
diff
changeset
|
6502 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6503 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6504 ins_cost(140); | |
6505 size(4); | |
6506 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6507 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6508 ins_pipe(ialu_imm); | |
6509 %} | |
6510 | |
6511 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6512 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6513 ins_cost(150); | |
6514 size(4); | |
6515 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6516 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6517 ins_pipe(ialu_reg); | |
6518 %} | |
6519 | |
6520 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6521 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6522 ins_cost(140); | |
6523 size(4); | |
6524 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6525 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6526 ins_pipe(ialu_imm); | |
6527 %} | |
6528 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6529 // Conditional move for RegN. Only cmov(reg,reg). |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6530 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6531 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6532 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6533 format %{ "MOV$cmp $pcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6534 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6535 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6536 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6537 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6538 // This instruction also works with CmpN so we don't need cmovNN_reg. |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6539 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6540 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6541 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6542 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6543 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6544 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6545 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6546 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6547 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6548 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6549 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6550 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6551 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6552 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6553 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6554 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6555 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6556 |
0 | 6557 // Conditional move |
6558 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6559 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6560 ins_cost(150); | |
6561 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6562 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6563 ins_pipe(ialu_reg); | |
6564 %} | |
6565 | |
6566 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6567 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6568 ins_cost(140); | |
6569 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6570 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6571 ins_pipe(ialu_imm); | |
6572 %} | |
6573 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6574 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6575 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6576 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6577 ins_cost(150); | |
6578 | |
6579 size(4); | |
6580 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6581 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6582 ins_pipe(ialu_reg); | |
6583 %} | |
6584 | |
6585 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ | |
6586 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6587 ins_cost(140); | |
6588 | |
6589 size(4); | |
6590 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6591 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6592 ins_pipe(ialu_imm); | |
6593 %} | |
6594 | |
6595 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ | |
6596 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6597 ins_cost(150); | |
6598 size(4); | |
6599 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6600 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6601 ins_pipe(ialu_imm); | |
6602 %} | |
6603 | |
6604 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6605 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6606 ins_cost(140); | |
6607 size(4); | |
6608 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6609 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6610 ins_pipe(ialu_imm); | |
6611 %} | |
6612 | |
6613 // Conditional move | |
6614 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6615 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6616 ins_cost(150); | |
6617 opcode(0x101); | |
6618 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6619 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6620 ins_pipe(int_conditional_float_move); | |
6621 %} | |
6622 | |
6623 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6624 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6625 ins_cost(150); | |
6626 | |
6627 size(4); | |
6628 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6629 opcode(0x101); | |
6630 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6631 ins_pipe(int_conditional_float_move); | |
6632 %} | |
6633 | |
6634 // Conditional move, | |
6635 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6636 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6637 ins_cost(150); | |
6638 size(4); | |
6639 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6640 opcode(0x1); | |
6641 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6642 ins_pipe(int_conditional_double_move); | |
6643 %} | |
6644 | |
6645 // Conditional move | |
6646 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6647 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6648 ins_cost(150); | |
6649 size(4); | |
6650 opcode(0x102); | |
6651 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6652 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6653 ins_pipe(int_conditional_double_move); | |
6654 %} | |
6655 | |
6656 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6657 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6658 ins_cost(150); | |
6659 | |
6660 size(4); | |
6661 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
6662 opcode(0x102); | |
6663 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6664 ins_pipe(int_conditional_double_move); | |
6665 %} | |
6666 | |
6667 // Conditional move, | |
6668 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
6669 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
6670 ins_cost(150); | |
6671 size(4); | |
6672 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
6673 opcode(0x2); | |
6674 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6675 ins_pipe(int_conditional_double_move); | |
6676 %} | |
6677 | |
6678 // Conditional move | |
6679 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
6680 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6681 ins_cost(150); | |
6682 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6683 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6684 ins_pipe(ialu_reg); | |
6685 %} | |
6686 | |
6687 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
6688 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6689 ins_cost(140); | |
6690 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6691 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6692 ins_pipe(ialu_imm); | |
6693 %} | |
6694 | |
6695 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
6696 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
6697 ins_cost(150); | |
6698 | |
6699 size(4); | |
6700 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
6701 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6702 ins_pipe(ialu_reg); | |
6703 %} | |
6704 | |
6705 | |
6706 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ | |
6707 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
6708 ins_cost(150); | |
6709 | |
6710 size(4); | |
6711 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
6712 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6713 ins_pipe(ialu_reg); | |
6714 %} | |
6715 | |
6716 | |
6717 | |
6718 //----------OS and Locking Instructions---------------------------------------- | |
6719 | |
6720 // This name is KNOWN by the ADLC and cannot be changed. | |
6721 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
6722 // for this guy. | |
6723 instruct tlsLoadP(g2RegP dst) %{ | |
6724 match(Set dst (ThreadLocal)); | |
6725 | |
6726 size(0); | |
6727 ins_cost(0); | |
6728 format %{ "# TLS is in G2" %} | |
6729 ins_encode( /*empty encoding*/ ); | |
6730 ins_pipe(ialu_none); | |
6731 %} | |
6732 | |
6733 instruct checkCastPP( iRegP dst ) %{ | |
6734 match(Set dst (CheckCastPP dst)); | |
6735 | |
6736 size(0); | |
6737 format %{ "# checkcastPP of $dst" %} | |
6738 ins_encode( /*empty encoding*/ ); | |
6739 ins_pipe(empty); | |
6740 %} | |
6741 | |
6742 | |
6743 instruct castPP( iRegP dst ) %{ | |
6744 match(Set dst (CastPP dst)); | |
6745 format %{ "# castPP of $dst" %} | |
6746 ins_encode( /*empty encoding*/ ); | |
6747 ins_pipe(empty); | |
6748 %} | |
6749 | |
6750 instruct castII( iRegI dst ) %{ | |
6751 match(Set dst (CastII dst)); | |
6752 format %{ "# castII of $dst" %} | |
6753 ins_encode( /*empty encoding*/ ); | |
6754 ins_cost(0); | |
6755 ins_pipe(empty); | |
6756 %} | |
6757 | |
6758 //----------Arithmetic Instructions-------------------------------------------- | |
6759 // Addition Instructions | |
6760 // Register Addition | |
6761 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
6762 match(Set dst (AddI src1 src2)); | |
6763 | |
6764 size(4); | |
6765 format %{ "ADD $src1,$src2,$dst" %} | |
6766 ins_encode %{ | |
6767 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
6768 %} | |
6769 ins_pipe(ialu_reg_reg); | |
6770 %} | |
6771 | |
6772 // Immediate Addition | |
6773 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
6774 match(Set dst (AddI src1 src2)); | |
6775 | |
6776 size(4); | |
6777 format %{ "ADD $src1,$src2,$dst" %} | |
6778 opcode(Assembler::add_op3, Assembler::arith_op); | |
6779 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
6780 ins_pipe(ialu_reg_imm); | |
6781 %} | |
6782 | |
6783 // Pointer Register Addition | |
6784 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
6785 match(Set dst (AddP src1 src2)); | |
6786 | |
6787 size(4); | |
6788 format %{ "ADD $src1,$src2,$dst" %} | |
6789 opcode(Assembler::add_op3, Assembler::arith_op); | |
6790 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6791 ins_pipe(ialu_reg_reg); | |
6792 %} | |
6793 | |
6794 // Pointer Immediate Addition | |
6795 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
6796 match(Set dst (AddP src1 src2)); | |
6797 | |
6798 size(4); | |
6799 format %{ "ADD $src1,$src2,$dst" %} | |
6800 opcode(Assembler::add_op3, Assembler::arith_op); | |
6801 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
6802 ins_pipe(ialu_reg_imm); | |
6803 %} | |
6804 | |
6805 // Long Addition | |
6806 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
6807 match(Set dst (AddL src1 src2)); | |
6808 | |
6809 size(4); | |
6810 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
6811 opcode(Assembler::add_op3, Assembler::arith_op); | |
6812 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6813 ins_pipe(ialu_reg_reg); | |
6814 %} | |
6815 | |
6816 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
6817 match(Set dst (AddL src1 con)); | |
6818 | |
6819 size(4); | |
6820 format %{ "ADD $src1,$con,$dst" %} | |
6821 opcode(Assembler::add_op3, Assembler::arith_op); | |
6822 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
6823 ins_pipe(ialu_reg_imm); | |
6824 %} | |
6825 | |
6826 //----------Conditional_store-------------------------------------------------- | |
6827 // Conditional-store of the updated heap-top. | |
6828 // Used during allocation of the shared heap. | |
6829 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
6830 | |
6831 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
6832 instruct loadPLocked(iRegP dst, memory mem) %{ | |
6833 match(Set dst (LoadPLocked mem)); | |
6834 ins_cost(MEMORY_REF_COST); | |
6835 | |
6836 #ifndef _LP64 | |
6837 size(4); | |
6838 format %{ "LDUW $mem,$dst\t! ptr" %} | |
6839 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
6840 #else | |
6841 format %{ "LDX $mem,$dst\t! ptr" %} | |
6842 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
6843 #endif | |
6844 ins_encode( form3_mem_reg( mem, dst ) ); | |
6845 ins_pipe(iload_mem); | |
6846 %} | |
6847 | |
6848 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
6849 instruct loadLLocked(iRegL dst, memory mem) %{ | |
6850 match(Set dst (LoadLLocked mem)); | |
6851 ins_cost(MEMORY_REF_COST); | |
6852 size(4); | |
6853 format %{ "LDX $mem,$dst\t! long" %} | |
6854 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
6855 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 6856 ins_pipe(iload_mem); |
6857 %} | |
6858 | |
6859 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
6860 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
6861 effect( KILL newval ); | |
6862 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
6863 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
6864 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
6865 ins_pipe( long_memory_op ); | |
6866 %} | |
6867 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6868 // Conditional-store of an int value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6869 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6870 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6871 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6872 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6873 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6874 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 6875 ins_pipe( long_memory_op ); |
6876 %} | |
6877 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6878 // Conditional-store of a long value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6879 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6880 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6881 effect( KILL newval ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6882 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6883 "CMP $oldval,$newval\t\t! See if we made progress" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
6884 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 6885 ins_pipe( long_memory_op ); |
6886 %} | |
6887 | |
6888 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
6889 | |
6890 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6891 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
6892 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
6893 format %{ | |
6894 "MOV $newval,O7\n\t" | |
6895 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
6896 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
6897 "MOV 1,$res\n\t" | |
6898 "MOVne xcc,R_G0,$res" | |
6899 %} | |
6900 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
6901 enc_lflags_ne_to_boolean(res) ); | |
6902 ins_pipe( long_memory_op ); | |
6903 %} | |
6904 | |
6905 | |
6906 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6907 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
6908 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
6909 format %{ | |
6910 "MOV $newval,O7\n\t" | |
6911 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
6912 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
6913 "MOV 1,$res\n\t" | |
6914 "MOVne icc,R_G0,$res" | |
6915 %} | |
6916 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
6917 enc_iflags_ne_to_boolean(res) ); | |
6918 ins_pipe( long_memory_op ); | |
6919 %} | |
6920 | |
6921 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
6922 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
6923 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
6924 format %{ | |
6925 "MOV $newval,O7\n\t" | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6926 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 6927 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
6928 "MOV 1,$res\n\t" | |
6929 "MOVne xcc,R_G0,$res" | |
6930 %} | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6931 #ifdef _LP64 |
0 | 6932 ins_encode( enc_casx(mem_ptr, oldval, newval), |
6933 enc_lflags_ne_to_boolean(res) ); | |
6934 #else | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6935 ins_encode( enc_casi(mem_ptr, oldval, newval), |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6936 enc_iflags_ne_to_boolean(res) ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6937 #endif |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6938 ins_pipe( long_memory_op ); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6939 %} |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6940 |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
6941 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
6942 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
6943 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 6944 format %{ |
6945 "MOV $newval,O7\n\t" | |
6946 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
6947 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
6948 "MOV 1,$res\n\t" | |
6949 "MOVne icc,R_G0,$res" | |
6950 %} | |
181
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
6951 ins_encode( enc_casi(mem_ptr, oldval, newval), |
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
6952 enc_iflags_ne_to_boolean(res) ); |
0 | 6953 ins_pipe( long_memory_op ); |
6954 %} | |
6955 | |
6956 //--------------------- | |
6957 // Subtraction Instructions | |
6958 // Register Subtraction | |
6959 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
6960 match(Set dst (SubI src1 src2)); | |
6961 | |
6962 size(4); | |
6963 format %{ "SUB $src1,$src2,$dst" %} | |
6964 opcode(Assembler::sub_op3, Assembler::arith_op); | |
6965 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6966 ins_pipe(ialu_reg_reg); | |
6967 %} | |
6968 | |
6969 // Immediate Subtraction | |
6970 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
6971 match(Set dst (SubI src1 src2)); | |
6972 | |
6973 size(4); | |
6974 format %{ "SUB $src1,$src2,$dst" %} | |
6975 opcode(Assembler::sub_op3, Assembler::arith_op); | |
6976 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
6977 ins_pipe(ialu_reg_imm); | |
6978 %} | |
6979 | |
6980 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
6981 match(Set dst (SubI zero src2)); | |
6982 | |
6983 size(4); | |
6984 format %{ "NEG $src2,$dst" %} | |
6985 opcode(Assembler::sub_op3, Assembler::arith_op); | |
6986 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
6987 ins_pipe(ialu_zero_reg); | |
6988 %} | |
6989 | |
6990 // Long subtraction | |
6991 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
6992 match(Set dst (SubL src1 src2)); | |
6993 | |
6994 size(4); | |
6995 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
6996 opcode(Assembler::sub_op3, Assembler::arith_op); | |
6997 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
6998 ins_pipe(ialu_reg_reg); | |
6999 %} | |
7000 | |
7001 // Immediate Subtraction | |
7002 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7003 match(Set dst (SubL src1 con)); | |
7004 | |
7005 size(4); | |
7006 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7007 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7008 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7009 ins_pipe(ialu_reg_imm); | |
7010 %} | |
7011 | |
7012 // Long negation | |
7013 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7014 match(Set dst (SubL zero src2)); | |
7015 | |
7016 size(4); | |
7017 format %{ "NEG $src2,$dst\t! long" %} | |
7018 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7019 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7020 ins_pipe(ialu_zero_reg); | |
7021 %} | |
7022 | |
7023 // Multiplication Instructions | |
7024 // Integer Multiplication | |
7025 // Register Multiplication | |
7026 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7027 match(Set dst (MulI src1 src2)); | |
7028 | |
7029 size(4); | |
7030 format %{ "MULX $src1,$src2,$dst" %} | |
7031 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7032 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7033 ins_pipe(imul_reg_reg); | |
7034 %} | |
7035 | |
7036 // Immediate Multiplication | |
7037 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7038 match(Set dst (MulI src1 src2)); | |
7039 | |
7040 size(4); | |
7041 format %{ "MULX $src1,$src2,$dst" %} | |
7042 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7043 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7044 ins_pipe(imul_reg_imm); | |
7045 %} | |
7046 | |
7047 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7048 match(Set dst (MulL src1 src2)); | |
7049 ins_cost(DEFAULT_COST * 5); | |
7050 size(4); | |
7051 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7052 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7053 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7054 ins_pipe(mulL_reg_reg); | |
7055 %} | |
7056 | |
7057 // Immediate Multiplication | |
7058 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7059 match(Set dst (MulL src1 src2)); | |
7060 ins_cost(DEFAULT_COST * 5); | |
7061 size(4); | |
7062 format %{ "MULX $src1,$src2,$dst" %} | |
7063 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7064 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7065 ins_pipe(mulL_reg_imm); | |
7066 %} | |
7067 | |
7068 // Integer Division | |
7069 // Register Division | |
7070 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7071 match(Set dst (DivI src1 src2)); | |
7072 ins_cost((2+71)*DEFAULT_COST); | |
7073 | |
7074 format %{ "SRA $src2,0,$src2\n\t" | |
7075 "SRA $src1,0,$src1\n\t" | |
7076 "SDIVX $src1,$src2,$dst" %} | |
7077 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7078 ins_pipe(sdiv_reg_reg); | |
7079 %} | |
7080 | |
7081 // Immediate Division | |
7082 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7083 match(Set dst (DivI src1 src2)); | |
7084 ins_cost((2+71)*DEFAULT_COST); | |
7085 | |
7086 format %{ "SRA $src1,0,$src1\n\t" | |
7087 "SDIVX $src1,$src2,$dst" %} | |
7088 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7089 ins_pipe(sdiv_reg_imm); | |
7090 %} | |
7091 | |
7092 //----------Div-By-10-Expansion------------------------------------------------ | |
7093 // Extract hi bits of a 32x32->64 bit multiply. | |
7094 // Expand rule only, not matched | |
7095 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7096 effect( DEF dst, USE src1, USE src2 ); | |
7097 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7098 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7099 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7100 ins_pipe(sdiv_reg_reg); | |
7101 %} | |
7102 | |
605 | 7103 // Magic constant, reciprocal of 10 |
0 | 7104 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7105 effect( DEF dst ); | |
7106 | |
7107 size(8); | |
7108 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7109 ins_encode( Set32(0x66666667, dst) ); | |
7110 ins_pipe(ialu_hi_lo_reg); | |
7111 %} | |
7112 | |
605 | 7113 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7114 instruct sra_31( iRegI dst, iRegI src ) %{ |
7115 effect( DEF dst, USE src ); | |
7116 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7117 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7118 ins_pipe(ialu_reg_reg); | |
7119 %} | |
7120 | |
7121 // Arithmetic Shift Right by 8-bit immediate | |
7122 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7123 effect( DEF dst, USE src ); | |
7124 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7125 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7126 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7127 ins_pipe(ialu_reg_imm); | |
7128 %} | |
7129 | |
7130 // Integer DIV with 10 | |
7131 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7132 match(Set dst (DivI src div)); | |
7133 ins_cost((6+6)*DEFAULT_COST); | |
7134 expand %{ | |
7135 iRegIsafe tmp1; // Killed temps; | |
7136 iRegIsafe tmp2; // Killed temps; | |
7137 iRegI tmp3; // Killed temps; | |
7138 iRegI tmp4; // Killed temps; | |
7139 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7140 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7141 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7142 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7143 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7144 %} | |
7145 %} | |
7146 | |
7147 // Register Long Division | |
7148 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7149 match(Set dst (DivL src1 src2)); | |
7150 ins_cost(DEFAULT_COST*71); | |
7151 size(4); | |
7152 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7153 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7155 ins_pipe(divL_reg_reg); | |
7156 %} | |
7157 | |
7158 // Register Long Division | |
7159 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7160 match(Set dst (DivL src1 src2)); | |
7161 ins_cost(DEFAULT_COST*71); | |
7162 size(4); | |
7163 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7164 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7165 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7166 ins_pipe(divL_reg_imm); | |
7167 %} | |
7168 | |
7169 // Integer Remainder | |
7170 // Register Remainder | |
7171 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7172 match(Set dst (ModI src1 src2)); | |
7173 effect( KILL ccr, KILL temp); | |
7174 | |
7175 format %{ "SREM $src1,$src2,$dst" %} | |
7176 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7177 ins_pipe(sdiv_reg_reg); | |
7178 %} | |
7179 | |
7180 // Immediate Remainder | |
7181 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7182 match(Set dst (ModI src1 src2)); | |
7183 effect( KILL ccr, KILL temp); | |
7184 | |
7185 format %{ "SREM $src1,$src2,$dst" %} | |
7186 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7187 ins_pipe(sdiv_reg_imm); | |
7188 %} | |
7189 | |
7190 // Register Long Remainder | |
7191 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7192 effect(DEF dst, USE src1, USE src2); | |
7193 size(4); | |
7194 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7195 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7196 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7197 ins_pipe(divL_reg_reg); | |
7198 %} | |
7199 | |
7200 // Register Long Division | |
7201 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7202 effect(DEF dst, USE src1, USE src2); | |
7203 size(4); | |
7204 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7205 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7206 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7207 ins_pipe(divL_reg_imm); | |
7208 %} | |
7209 | |
7210 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7211 effect(DEF dst, USE src1, USE src2); | |
7212 size(4); | |
7213 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7214 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7215 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7216 ins_pipe(mulL_reg_reg); | |
7217 %} | |
7218 | |
7219 // Immediate Multiplication | |
7220 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7221 effect(DEF dst, USE src1, USE src2); | |
7222 size(4); | |
7223 format %{ "MULX $src1,$src2,$dst" %} | |
7224 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7225 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7226 ins_pipe(mulL_reg_imm); | |
7227 %} | |
7228 | |
7229 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7230 effect(DEF dst, USE src1, USE src2); | |
7231 size(4); | |
7232 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7233 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7234 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7235 ins_pipe(ialu_reg_reg); | |
7236 %} | |
7237 | |
7238 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7239 effect(DEF dst, USE src1, USE src2); | |
7240 size(4); | |
7241 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7242 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7243 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7244 ins_pipe(ialu_reg_reg); | |
7245 %} | |
7246 | |
7247 // Register Long Remainder | |
7248 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7249 match(Set dst (ModL src1 src2)); | |
7250 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7251 expand %{ | |
7252 iRegL tmp1; | |
7253 iRegL tmp2; | |
7254 divL_reg_reg_1(tmp1, src1, src2); | |
7255 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7256 subL_reg_reg_1(dst, src1, tmp2); | |
7257 %} | |
7258 %} | |
7259 | |
7260 // Register Long Remainder | |
7261 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7262 match(Set dst (ModL src1 src2)); | |
7263 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7264 expand %{ | |
7265 iRegL tmp1; | |
7266 iRegL tmp2; | |
7267 divL_reg_imm13_1(tmp1, src1, src2); | |
7268 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7269 subL_reg_reg_2 (dst, src1, tmp2); | |
7270 %} | |
7271 %} | |
7272 | |
7273 // Integer Shift Instructions | |
7274 // Register Shift Left | |
7275 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7276 match(Set dst (LShiftI src1 src2)); | |
7277 | |
7278 size(4); | |
7279 format %{ "SLL $src1,$src2,$dst" %} | |
7280 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7281 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7282 ins_pipe(ialu_reg_reg); | |
7283 %} | |
7284 | |
7285 // Register Shift Left Immediate | |
7286 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7287 match(Set dst (LShiftI src1 src2)); | |
7288 | |
7289 size(4); | |
7290 format %{ "SLL $src1,$src2,$dst" %} | |
7291 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7292 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7293 ins_pipe(ialu_reg_imm); | |
7294 %} | |
7295 | |
7296 // Register Shift Left | |
7297 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7298 match(Set dst (LShiftL src1 src2)); | |
7299 | |
7300 size(4); | |
7301 format %{ "SLLX $src1,$src2,$dst" %} | |
7302 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7303 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7304 ins_pipe(ialu_reg_reg); | |
7305 %} | |
7306 | |
7307 // Register Shift Left Immediate | |
7308 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7309 match(Set dst (LShiftL src1 src2)); | |
7310 | |
7311 size(4); | |
7312 format %{ "SLLX $src1,$src2,$dst" %} | |
7313 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7314 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7315 ins_pipe(ialu_reg_imm); | |
7316 %} | |
7317 | |
7318 // Register Arithmetic Shift Right | |
7319 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7320 match(Set dst (RShiftI src1 src2)); | |
7321 size(4); | |
7322 format %{ "SRA $src1,$src2,$dst" %} | |
7323 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7324 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7325 ins_pipe(ialu_reg_reg); | |
7326 %} | |
7327 | |
7328 // Register Arithmetic Shift Right Immediate | |
7329 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7330 match(Set dst (RShiftI src1 src2)); | |
7331 | |
7332 size(4); | |
7333 format %{ "SRA $src1,$src2,$dst" %} | |
7334 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7335 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7336 ins_pipe(ialu_reg_imm); | |
7337 %} | |
7338 | |
7339 // Register Shift Right Arithmatic Long | |
7340 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7341 match(Set dst (RShiftL src1 src2)); | |
7342 | |
7343 size(4); | |
7344 format %{ "SRAX $src1,$src2,$dst" %} | |
7345 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7346 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7347 ins_pipe(ialu_reg_reg); | |
7348 %} | |
7349 | |
7350 // Register Shift Left Immediate | |
7351 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7352 match(Set dst (RShiftL src1 src2)); | |
7353 | |
7354 size(4); | |
7355 format %{ "SRAX $src1,$src2,$dst" %} | |
7356 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7357 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7358 ins_pipe(ialu_reg_imm); | |
7359 %} | |
7360 | |
7361 // Register Shift Right | |
7362 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7363 match(Set dst (URShiftI src1 src2)); | |
7364 | |
7365 size(4); | |
7366 format %{ "SRL $src1,$src2,$dst" %} | |
7367 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7368 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7369 ins_pipe(ialu_reg_reg); | |
7370 %} | |
7371 | |
7372 // Register Shift Right Immediate | |
7373 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7374 match(Set dst (URShiftI src1 src2)); | |
7375 | |
7376 size(4); | |
7377 format %{ "SRL $src1,$src2,$dst" %} | |
7378 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7379 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7380 ins_pipe(ialu_reg_imm); | |
7381 %} | |
7382 | |
7383 // Register Shift Right | |
7384 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7385 match(Set dst (URShiftL src1 src2)); | |
7386 | |
7387 size(4); | |
7388 format %{ "SRLX $src1,$src2,$dst" %} | |
7389 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7390 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7391 ins_pipe(ialu_reg_reg); | |
7392 %} | |
7393 | |
7394 // Register Shift Right Immediate | |
7395 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7396 match(Set dst (URShiftL src1 src2)); | |
7397 | |
7398 size(4); | |
7399 format %{ "SRLX $src1,$src2,$dst" %} | |
7400 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7401 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7402 ins_pipe(ialu_reg_imm); | |
7403 %} | |
7404 | |
7405 // Register Shift Right Immediate with a CastP2X | |
7406 #ifdef _LP64 | |
7407 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7408 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7409 size(4); | |
7410 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7411 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7412 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7413 ins_pipe(ialu_reg_imm); | |
7414 %} | |
7415 #else | |
7416 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7417 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7418 size(4); | |
7419 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7420 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7421 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7422 ins_pipe(ialu_reg_imm); | |
7423 %} | |
7424 #endif | |
7425 | |
7426 | |
7427 //----------Floating Point Arithmetic Instructions----------------------------- | |
7428 | |
7429 // Add float single precision | |
7430 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7431 match(Set dst (AddF src1 src2)); | |
7432 | |
7433 size(4); | |
7434 format %{ "FADDS $src1,$src2,$dst" %} | |
7435 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7436 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7437 ins_pipe(faddF_reg_reg); | |
7438 %} | |
7439 | |
7440 // Add float double precision | |
7441 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7442 match(Set dst (AddD src1 src2)); | |
7443 | |
7444 size(4); | |
7445 format %{ "FADDD $src1,$src2,$dst" %} | |
7446 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7447 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7448 ins_pipe(faddD_reg_reg); | |
7449 %} | |
7450 | |
7451 // Sub float single precision | |
7452 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7453 match(Set dst (SubF src1 src2)); | |
7454 | |
7455 size(4); | |
7456 format %{ "FSUBS $src1,$src2,$dst" %} | |
7457 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7458 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7459 ins_pipe(faddF_reg_reg); | |
7460 %} | |
7461 | |
7462 // Sub float double precision | |
7463 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7464 match(Set dst (SubD src1 src2)); | |
7465 | |
7466 size(4); | |
7467 format %{ "FSUBD $src1,$src2,$dst" %} | |
7468 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7469 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7470 ins_pipe(faddD_reg_reg); | |
7471 %} | |
7472 | |
7473 // Mul float single precision | |
7474 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7475 match(Set dst (MulF src1 src2)); | |
7476 | |
7477 size(4); | |
7478 format %{ "FMULS $src1,$src2,$dst" %} | |
7479 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7480 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7481 ins_pipe(fmulF_reg_reg); | |
7482 %} | |
7483 | |
7484 // Mul float double precision | |
7485 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7486 match(Set dst (MulD src1 src2)); | |
7487 | |
7488 size(4); | |
7489 format %{ "FMULD $src1,$src2,$dst" %} | |
7490 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7491 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7492 ins_pipe(fmulD_reg_reg); | |
7493 %} | |
7494 | |
7495 // Div float single precision | |
7496 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7497 match(Set dst (DivF src1 src2)); | |
7498 | |
7499 size(4); | |
7500 format %{ "FDIVS $src1,$src2,$dst" %} | |
7501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7502 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7503 ins_pipe(fdivF_reg_reg); | |
7504 %} | |
7505 | |
7506 // Div float double precision | |
7507 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7508 match(Set dst (DivD src1 src2)); | |
7509 | |
7510 size(4); | |
7511 format %{ "FDIVD $src1,$src2,$dst" %} | |
7512 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7513 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7514 ins_pipe(fdivD_reg_reg); | |
7515 %} | |
7516 | |
7517 // Absolute float double precision | |
7518 instruct absD_reg(regD dst, regD src) %{ | |
7519 match(Set dst (AbsD src)); | |
7520 | |
7521 format %{ "FABSd $src,$dst" %} | |
7522 ins_encode(fabsd(dst, src)); | |
7523 ins_pipe(faddD_reg); | |
7524 %} | |
7525 | |
7526 // Absolute float single precision | |
7527 instruct absF_reg(regF dst, regF src) %{ | |
7528 match(Set dst (AbsF src)); | |
7529 | |
7530 format %{ "FABSs $src,$dst" %} | |
7531 ins_encode(fabss(dst, src)); | |
7532 ins_pipe(faddF_reg); | |
7533 %} | |
7534 | |
7535 instruct negF_reg(regF dst, regF src) %{ | |
7536 match(Set dst (NegF src)); | |
7537 | |
7538 size(4); | |
7539 format %{ "FNEGs $src,$dst" %} | |
7540 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7541 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7542 ins_pipe(faddF_reg); | |
7543 %} | |
7544 | |
7545 instruct negD_reg(regD dst, regD src) %{ | |
7546 match(Set dst (NegD src)); | |
7547 | |
7548 format %{ "FNEGd $src,$dst" %} | |
7549 ins_encode(fnegd(dst, src)); | |
7550 ins_pipe(faddD_reg); | |
7551 %} | |
7552 | |
7553 // Sqrt float double precision | |
7554 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7555 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7556 | |
7557 size(4); | |
7558 format %{ "FSQRTS $src,$dst" %} | |
7559 ins_encode(fsqrts(dst, src)); | |
7560 ins_pipe(fdivF_reg_reg); | |
7561 %} | |
7562 | |
7563 // Sqrt float double precision | |
7564 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7565 match(Set dst (SqrtD src)); | |
7566 | |
7567 size(4); | |
7568 format %{ "FSQRTD $src,$dst" %} | |
7569 ins_encode(fsqrtd(dst, src)); | |
7570 ins_pipe(fdivD_reg_reg); | |
7571 %} | |
7572 | |
7573 //----------Logical Instructions----------------------------------------------- | |
7574 // And Instructions | |
7575 // Register And | |
7576 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7577 match(Set dst (AndI src1 src2)); | |
7578 | |
7579 size(4); | |
7580 format %{ "AND $src1,$src2,$dst" %} | |
7581 opcode(Assembler::and_op3, Assembler::arith_op); | |
7582 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7583 ins_pipe(ialu_reg_reg); | |
7584 %} | |
7585 | |
7586 // Immediate And | |
7587 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7588 match(Set dst (AndI src1 src2)); | |
7589 | |
7590 size(4); | |
7591 format %{ "AND $src1,$src2,$dst" %} | |
7592 opcode(Assembler::and_op3, Assembler::arith_op); | |
7593 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7594 ins_pipe(ialu_reg_imm); | |
7595 %} | |
7596 | |
7597 // Register And Long | |
7598 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7599 match(Set dst (AndL src1 src2)); | |
7600 | |
7601 ins_cost(DEFAULT_COST); | |
7602 size(4); | |
7603 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7604 opcode(Assembler::and_op3, Assembler::arith_op); | |
7605 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7606 ins_pipe(ialu_reg_reg); | |
7607 %} | |
7608 | |
7609 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7610 match(Set dst (AndL src1 con)); | |
7611 | |
7612 ins_cost(DEFAULT_COST); | |
7613 size(4); | |
7614 format %{ "AND $src1,$con,$dst\t! long" %} | |
7615 opcode(Assembler::and_op3, Assembler::arith_op); | |
7616 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7617 ins_pipe(ialu_reg_imm); | |
7618 %} | |
7619 | |
7620 // Or Instructions | |
7621 // Register Or | |
7622 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7623 match(Set dst (OrI src1 src2)); | |
7624 | |
7625 size(4); | |
7626 format %{ "OR $src1,$src2,$dst" %} | |
7627 opcode(Assembler::or_op3, Assembler::arith_op); | |
7628 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7629 ins_pipe(ialu_reg_reg); | |
7630 %} | |
7631 | |
7632 // Immediate Or | |
7633 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7634 match(Set dst (OrI src1 src2)); | |
7635 | |
7636 size(4); | |
7637 format %{ "OR $src1,$src2,$dst" %} | |
7638 opcode(Assembler::or_op3, Assembler::arith_op); | |
7639 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7640 ins_pipe(ialu_reg_imm); | |
7641 %} | |
7642 | |
7643 // Register Or Long | |
7644 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7645 match(Set dst (OrL src1 src2)); | |
7646 | |
7647 ins_cost(DEFAULT_COST); | |
7648 size(4); | |
7649 format %{ "OR $src1,$src2,$dst\t! long" %} | |
7650 opcode(Assembler::or_op3, Assembler::arith_op); | |
7651 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7652 ins_pipe(ialu_reg_reg); | |
7653 %} | |
7654 | |
7655 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7656 match(Set dst (OrL src1 con)); | |
7657 ins_cost(DEFAULT_COST*2); | |
7658 | |
7659 ins_cost(DEFAULT_COST); | |
7660 size(4); | |
7661 format %{ "OR $src1,$con,$dst\t! long" %} | |
7662 opcode(Assembler::or_op3, Assembler::arith_op); | |
7663 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7664 ins_pipe(ialu_reg_imm); | |
7665 %} | |
7666 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7667 #ifndef _LP64 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7668 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7669 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7670 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7671 match(Set dst (OrI src1 (CastP2X src2))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7672 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7673 size(4); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7674 format %{ "OR $src1,$src2,$dst" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7675 opcode(Assembler::or_op3, Assembler::arith_op); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7676 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7677 ins_pipe(ialu_reg_reg); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7678 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7679 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7680 #else |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7681 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7682 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7683 match(Set dst (OrL src1 (CastP2X src2))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7684 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7685 ins_cost(DEFAULT_COST); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7686 size(4); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7687 format %{ "OR $src1,$src2,$dst\t! long" %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7688 opcode(Assembler::or_op3, Assembler::arith_op); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7689 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7690 ins_pipe(ialu_reg_reg); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7691 %} |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7692 |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7693 #endif |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7694 |
0 | 7695 // Xor Instructions |
7696 // Register Xor | |
7697 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7698 match(Set dst (XorI src1 src2)); | |
7699 | |
7700 size(4); | |
7701 format %{ "XOR $src1,$src2,$dst" %} | |
7702 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7704 ins_pipe(ialu_reg_reg); | |
7705 %} | |
7706 | |
7707 // Immediate Xor | |
7708 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7709 match(Set dst (XorI src1 src2)); | |
7710 | |
7711 size(4); | |
7712 format %{ "XOR $src1,$src2,$dst" %} | |
7713 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7714 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7715 ins_pipe(ialu_reg_imm); | |
7716 %} | |
7717 | |
7718 // Register Xor Long | |
7719 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7720 match(Set dst (XorL src1 src2)); | |
7721 | |
7722 ins_cost(DEFAULT_COST); | |
7723 size(4); | |
7724 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
7725 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7726 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7727 ins_pipe(ialu_reg_reg); | |
7728 %} | |
7729 | |
7730 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7731 match(Set dst (XorL src1 con)); | |
7732 | |
7733 ins_cost(DEFAULT_COST); | |
7734 size(4); | |
7735 format %{ "XOR $src1,$con,$dst\t! long" %} | |
7736 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7737 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7738 ins_pipe(ialu_reg_imm); | |
7739 %} | |
7740 | |
7741 //----------Convert to Boolean------------------------------------------------- | |
7742 // Nice hack for 32-bit tests but doesn't work for | |
7743 // 64-bit pointers. | |
7744 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
7745 match(Set dst (Conv2B src)); | |
7746 effect( KILL ccr ); | |
7747 ins_cost(DEFAULT_COST*2); | |
7748 format %{ "CMP R_G0,$src\n\t" | |
7749 "ADDX R_G0,0,$dst" %} | |
7750 ins_encode( enc_to_bool( src, dst ) ); | |
7751 ins_pipe(ialu_reg_ialu); | |
7752 %} | |
7753 | |
7754 #ifndef _LP64 | |
7755 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
7756 match(Set dst (Conv2B src)); | |
7757 effect( KILL ccr ); | |
7758 ins_cost(DEFAULT_COST*2); | |
7759 format %{ "CMP R_G0,$src\n\t" | |
7760 "ADDX R_G0,0,$dst" %} | |
7761 ins_encode( enc_to_bool( src, dst ) ); | |
7762 ins_pipe(ialu_reg_ialu); | |
7763 %} | |
7764 #else | |
7765 instruct convP2B( iRegI dst, iRegP src ) %{ | |
7766 match(Set dst (Conv2B src)); | |
7767 ins_cost(DEFAULT_COST*2); | |
7768 format %{ "MOV $src,$dst\n\t" | |
7769 "MOVRNZ $src,1,$dst" %} | |
7770 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
7771 ins_pipe(ialu_clr_and_mover); | |
7772 %} | |
7773 #endif | |
7774 | |
7775 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
7776 match(Set dst (CmpLTMask p q)); | |
7777 effect( KILL ccr ); | |
7778 ins_cost(DEFAULT_COST*4); | |
7779 format %{ "CMP $p,$q\n\t" | |
7780 "MOV #0,$dst\n\t" | |
7781 "BLT,a .+8\n\t" | |
7782 "MOV #-1,$dst" %} | |
7783 ins_encode( enc_ltmask(p,q,dst) ); | |
7784 ins_pipe(ialu_reg_reg_ialu); | |
7785 %} | |
7786 | |
7787 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
7788 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
7789 effect(KILL ccr, TEMP tmp); | |
7790 ins_cost(DEFAULT_COST*3); | |
7791 | |
7792 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
7793 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
7794 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
7795 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
7796 ins_pipe( cadd_cmpltmask ); | |
7797 %} | |
7798 | |
7799 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
7800 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
7801 effect( KILL ccr, TEMP tmp); | |
7802 ins_cost(DEFAULT_COST*3); | |
7803 | |
7804 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
7805 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
7806 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
7807 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
7808 ins_pipe( cadd_cmpltmask ); | |
7809 %} | |
7810 | |
7811 //----------Arithmetic Conversion Instructions--------------------------------- | |
7812 // The conversions operations are all Alpha sorted. Please keep it that way! | |
7813 | |
7814 instruct convD2F_reg(regF dst, regD src) %{ | |
7815 match(Set dst (ConvD2F src)); | |
7816 size(4); | |
7817 format %{ "FDTOS $src,$dst" %} | |
7818 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
7819 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
7820 ins_pipe(fcvtD2F); | |
7821 %} | |
7822 | |
7823 | |
7824 // Convert a double to an int in a float register. | |
7825 // If the double is a NAN, stuff a zero in instead. | |
7826 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
7827 effect(DEF dst, USE src, KILL fcc0); | |
7828 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
7829 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
7830 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
7831 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
7832 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
7833 "skip:" %} | |
7834 ins_encode(form_d2i_helper(src,dst)); | |
7835 ins_pipe(fcvtD2I); | |
7836 %} | |
7837 | |
7838 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
7839 match(Set dst (ConvD2I src)); | |
7840 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
7841 expand %{ | |
7842 regF tmp; | |
7843 convD2I_helper(tmp, src); | |
7844 regF_to_stkI(dst, tmp); | |
7845 %} | |
7846 %} | |
7847 | |
7848 // Convert a double to a long in a double register. | |
7849 // If the double is a NAN, stuff a zero in instead. | |
7850 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
7851 effect(DEF dst, USE src, KILL fcc0); | |
7852 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
7853 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
7854 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
7855 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
7856 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
7857 "skip:" %} | |
7858 ins_encode(form_d2l_helper(src,dst)); | |
7859 ins_pipe(fcvtD2L); | |
7860 %} | |
7861 | |
7862 | |
7863 // Double to Long conversion | |
7864 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
7865 match(Set dst (ConvD2L src)); | |
7866 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
7867 expand %{ | |
7868 regD tmp; | |
7869 convD2L_helper(tmp, src); | |
7870 regD_to_stkL(dst, tmp); | |
7871 %} | |
7872 %} | |
7873 | |
7874 | |
7875 instruct convF2D_reg(regD dst, regF src) %{ | |
7876 match(Set dst (ConvF2D src)); | |
7877 format %{ "FSTOD $src,$dst" %} | |
7878 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
7879 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
7880 ins_pipe(fcvtF2D); | |
7881 %} | |
7882 | |
7883 | |
7884 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
7885 effect(DEF dst, USE src, KILL fcc0); | |
7886 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
7887 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
7888 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
7889 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
7890 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
7891 "skip:" %} | |
7892 ins_encode(form_f2i_helper(src,dst)); | |
7893 ins_pipe(fcvtF2I); | |
7894 %} | |
7895 | |
7896 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
7897 match(Set dst (ConvF2I src)); | |
7898 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
7899 expand %{ | |
7900 regF tmp; | |
7901 convF2I_helper(tmp, src); | |
7902 regF_to_stkI(dst, tmp); | |
7903 %} | |
7904 %} | |
7905 | |
7906 | |
7907 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
7908 effect(DEF dst, USE src, KILL fcc0); | |
7909 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
7910 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
7911 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
7912 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
7913 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
7914 "skip:" %} | |
7915 ins_encode(form_f2l_helper(src,dst)); | |
7916 ins_pipe(fcvtF2L); | |
7917 %} | |
7918 | |
7919 // Float to Long conversion | |
7920 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
7921 match(Set dst (ConvF2L src)); | |
7922 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
7923 expand %{ | |
7924 regD tmp; | |
7925 convF2L_helper(tmp, src); | |
7926 regD_to_stkL(dst, tmp); | |
7927 %} | |
7928 %} | |
7929 | |
7930 | |
7931 instruct convI2D_helper(regD dst, regF tmp) %{ | |
7932 effect(USE tmp, DEF dst); | |
7933 format %{ "FITOD $tmp,$dst" %} | |
7934 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
7935 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
7936 ins_pipe(fcvtI2D); | |
7937 %} | |
7938 | |
7939 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
7940 match(Set dst (ConvI2D src)); | |
7941 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
7942 expand %{ | |
7943 regF tmp; | |
7944 stkI_to_regF( tmp, src); | |
7945 convI2D_helper( dst, tmp); | |
7946 %} | |
7947 %} | |
7948 | |
7949 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
7950 match(Set dst (ConvI2D (LoadI mem))); | |
7951 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
7952 size(8); | |
7953 format %{ "LDF $mem,$dst\n\t" | |
7954 "FITOD $dst,$dst" %} | |
7955 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
7956 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 7957 ins_pipe(floadF_mem); |
7958 %} | |
7959 | |
7960 | |
7961 instruct convI2F_helper(regF dst, regF tmp) %{ | |
7962 effect(DEF dst, USE tmp); | |
7963 format %{ "FITOS $tmp,$dst" %} | |
7964 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
7965 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
7966 ins_pipe(fcvtI2F); | |
7967 %} | |
7968 | |
7969 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
7970 match(Set dst (ConvI2F src)); | |
7971 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
7972 expand %{ | |
7973 regF tmp; | |
7974 stkI_to_regF(tmp,src); | |
7975 convI2F_helper(dst, tmp); | |
7976 %} | |
7977 %} | |
7978 | |
7979 instruct convI2F_mem( regF dst, memory mem ) %{ | |
7980 match(Set dst (ConvI2F (LoadI mem))); | |
7981 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
7982 size(8); | |
7983 format %{ "LDF $mem,$dst\n\t" | |
7984 "FITOS $dst,$dst" %} | |
7985 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
7986 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 7987 ins_pipe(floadF_mem); |
7988 %} | |
7989 | |
7990 | |
7991 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
7992 match(Set dst (ConvI2L src)); | |
7993 size(4); | |
7994 format %{ "SRA $src,0,$dst\t! int->long" %} | |
7995 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7996 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
7997 ins_pipe(ialu_reg_reg); | |
7998 %} | |
7999 | |
8000 // Zero-extend convert int to long | |
8001 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8002 match(Set dst (AndL (ConvI2L src) mask) ); | |
8003 size(4); | |
8004 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8005 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8006 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8007 ins_pipe(ialu_reg_reg); | |
8008 %} | |
8009 | |
8010 // Zero-extend long | |
8011 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8012 match(Set dst (AndL src mask) ); | |
8013 size(4); | |
8014 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8015 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8016 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8017 ins_pipe(ialu_reg_reg); | |
8018 %} | |
8019 | |
8020 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
8021 match(Set dst (MoveF2I src)); | |
8022 effect(DEF dst, USE src); | |
8023 ins_cost(MEMORY_REF_COST); | |
8024 | |
8025 size(4); | |
8026 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8027 opcode(Assembler::lduw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8028 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8029 ins_pipe(iload_mem); |
8030 %} | |
8031 | |
8032 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8033 match(Set dst (MoveI2F src)); | |
8034 effect(DEF dst, USE src); | |
8035 ins_cost(MEMORY_REF_COST); | |
8036 | |
8037 size(4); | |
8038 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8039 opcode(Assembler::ldf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8040 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8041 ins_pipe(floadF_stk); |
8042 %} | |
8043 | |
8044 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8045 match(Set dst (MoveD2L src)); | |
8046 effect(DEF dst, USE src); | |
8047 ins_cost(MEMORY_REF_COST); | |
8048 | |
8049 size(4); | |
8050 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8051 opcode(Assembler::ldx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8052 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8053 ins_pipe(iload_mem); |
8054 %} | |
8055 | |
8056 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8057 match(Set dst (MoveL2D src)); | |
8058 effect(DEF dst, USE src); | |
8059 ins_cost(MEMORY_REF_COST); | |
8060 | |
8061 size(4); | |
8062 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8063 opcode(Assembler::lddf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8064 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8065 ins_pipe(floadD_stk); |
8066 %} | |
8067 | |
8068 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8069 match(Set dst (MoveF2I src)); | |
8070 effect(DEF dst, USE src); | |
8071 ins_cost(MEMORY_REF_COST); | |
8072 | |
8073 size(4); | |
8074 format %{ "STF $src,$dst\t!MoveF2I" %} | |
8075 opcode(Assembler::stf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8076 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8077 ins_pipe(fstoreF_stk_reg); |
8078 %} | |
8079 | |
8080 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8081 match(Set dst (MoveI2F src)); | |
8082 effect(DEF dst, USE src); | |
8083 ins_cost(MEMORY_REF_COST); | |
8084 | |
8085 size(4); | |
8086 format %{ "STW $src,$dst\t!MoveI2F" %} | |
8087 opcode(Assembler::stw_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8088 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8089 ins_pipe(istore_mem_reg); |
8090 %} | |
8091 | |
8092 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8093 match(Set dst (MoveD2L src)); | |
8094 effect(DEF dst, USE src); | |
8095 ins_cost(MEMORY_REF_COST); | |
8096 | |
8097 size(4); | |
8098 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
8099 opcode(Assembler::stdf_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8100 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8101 ins_pipe(fstoreD_stk_reg); |
8102 %} | |
8103 | |
8104 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8105 match(Set dst (MoveL2D src)); | |
8106 effect(DEF dst, USE src); | |
8107 ins_cost(MEMORY_REF_COST); | |
8108 | |
8109 size(4); | |
8110 format %{ "STX $src,$dst\t!MoveL2D" %} | |
8111 opcode(Assembler::stx_op3); | |
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
8112 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8113 ins_pipe(istore_mem_reg); |
8114 %} | |
8115 | |
8116 | |
8117 //----------- | |
8118 // Long to Double conversion using V8 opcodes. | |
8119 // Still useful because cheetah traps and becomes | |
8120 // amazingly slow for some common numbers. | |
8121 | |
8122 // Magic constant, 0x43300000 | |
8123 instruct loadConI_x43300000(iRegI dst) %{ | |
8124 effect(DEF dst); | |
8125 size(4); | |
8126 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8127 ins_encode(SetHi22(0x43300000, dst)); | |
8128 ins_pipe(ialu_none); | |
8129 %} | |
8130 | |
8131 // Magic constant, 0x41f00000 | |
8132 instruct loadConI_x41f00000(iRegI dst) %{ | |
8133 effect(DEF dst); | |
8134 size(4); | |
8135 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8136 ins_encode(SetHi22(0x41f00000, dst)); | |
8137 ins_pipe(ialu_none); | |
8138 %} | |
8139 | |
8140 // Construct a double from two float halves | |
8141 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8142 effect(DEF dst, USE src1, USE src2); | |
8143 size(8); | |
8144 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8145 "FMOVS $src2.lo,$dst.lo" %} | |
8146 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8147 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8148 ins_pipe(faddD_reg_reg); | |
8149 %} | |
8150 | |
8151 // Convert integer in high half of a double register (in the lower half of | |
8152 // the double register file) to double | |
8153 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8154 effect(DEF dst, USE src); | |
8155 size(4); | |
8156 format %{ "FITOD $src,$dst" %} | |
8157 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8158 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8159 ins_pipe(fcvtLHi2D); | |
8160 %} | |
8161 | |
8162 // Add float double precision | |
8163 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8164 effect(DEF dst, USE src1, USE src2); | |
8165 size(4); | |
8166 format %{ "FADDD $src1,$src2,$dst" %} | |
8167 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8168 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8169 ins_pipe(faddD_reg_reg); | |
8170 %} | |
8171 | |
8172 // Sub float double precision | |
8173 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8174 effect(DEF dst, USE src1, USE src2); | |
8175 size(4); | |
8176 format %{ "FSUBD $src1,$src2,$dst" %} | |
8177 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8178 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8179 ins_pipe(faddD_reg_reg); | |
8180 %} | |
8181 | |
8182 // Mul float double precision | |
8183 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8184 effect(DEF dst, USE src1, USE src2); | |
8185 size(4); | |
8186 format %{ "FMULD $src1,$src2,$dst" %} | |
8187 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8188 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8189 ins_pipe(fmulD_reg_reg); | |
8190 %} | |
8191 | |
8192 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8193 match(Set dst (ConvL2D src)); | |
8194 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8195 | |
8196 expand %{ | |
8197 regD_low tmpsrc; | |
8198 iRegI ix43300000; | |
8199 iRegI ix41f00000; | |
8200 stackSlotL lx43300000; | |
8201 stackSlotL lx41f00000; | |
8202 regD_low dx43300000; | |
8203 regD dx41f00000; | |
8204 regD tmp1; | |
8205 regD_low tmp2; | |
8206 regD tmp3; | |
8207 regD tmp4; | |
8208 | |
8209 stkL_to_regD(tmpsrc, src); | |
8210 | |
8211 loadConI_x43300000(ix43300000); | |
8212 loadConI_x41f00000(ix41f00000); | |
8213 regI_to_stkLHi(lx43300000, ix43300000); | |
8214 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8215 stkL_to_regD(dx43300000, lx43300000); | |
8216 stkL_to_regD(dx41f00000, lx41f00000); | |
8217 | |
8218 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8219 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8220 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8221 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8222 addD_regD_regD(dst, tmp3, tmp4); | |
8223 %} | |
8224 %} | |
8225 | |
8226 // Long to Double conversion using fast fxtof | |
8227 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8228 effect(DEF dst, USE tmp); | |
8229 size(4); | |
8230 format %{ "FXTOD $tmp,$dst" %} | |
8231 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8232 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8233 ins_pipe(fcvtL2D); | |
8234 %} | |
8235 | |
8236 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
8237 predicate(VM_Version::has_fast_fxtof()); | |
8238 match(Set dst (ConvL2D src)); | |
8239 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8240 expand %{ | |
8241 regD tmp; | |
8242 stkL_to_regD(tmp, src); | |
8243 convL2D_helper(dst, tmp); | |
8244 %} | |
8245 %} | |
8246 | |
8247 //----------- | |
8248 // Long to Float conversion using V8 opcodes. | |
8249 // Still useful because cheetah traps and becomes | |
8250 // amazingly slow for some common numbers. | |
8251 | |
8252 // Long to Float conversion using fast fxtof | |
8253 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8254 effect(DEF dst, USE tmp); | |
8255 size(4); | |
8256 format %{ "FXTOS $tmp,$dst" %} | |
8257 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8258 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8259 ins_pipe(fcvtL2F); | |
8260 %} | |
8261 | |
8262 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
8263 match(Set dst (ConvL2F src)); | |
8264 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8265 expand %{ | |
8266 regD tmp; | |
8267 stkL_to_regD(tmp, src); | |
8268 convL2F_helper(dst, tmp); | |
8269 %} | |
8270 %} | |
8271 //----------- | |
8272 | |
8273 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8274 match(Set dst (ConvL2I src)); | |
8275 #ifndef _LP64 | |
8276 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8277 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8278 ins_pipe(ialu_move_reg_I_to_L); | |
8279 #else | |
8280 size(4); | |
8281 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8282 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8283 ins_pipe(ialu_reg); | |
8284 #endif | |
8285 %} | |
8286 | |
8287 // Register Shift Right Immediate | |
8288 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8289 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8290 | |
8291 size(4); | |
8292 format %{ "SRAX $src,$cnt,$dst" %} | |
8293 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8294 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8295 ins_pipe(ialu_reg_imm); | |
8296 %} | |
8297 | |
8298 // Replicate scalar to packed byte values in Double register | |
8299 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
8300 effect(DEF dst, USE src); | |
8301 format %{ "SLLX $src,56,$dst\n\t" | |
8302 "SRLX $dst, 8,O7\n\t" | |
8303 "OR $dst,O7,$dst\n\t" | |
8304 "SRLX $dst,16,O7\n\t" | |
8305 "OR $dst,O7,$dst\n\t" | |
8306 "SRLX $dst,32,O7\n\t" | |
8307 "OR $dst,O7,$dst\t! replicate8B" %} | |
8308 ins_encode( enc_repl8b(src, dst)); | |
8309 ins_pipe(ialu_reg); | |
8310 %} | |
8311 | |
8312 // Replicate scalar to packed byte values in Double register | |
8313 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
8314 match(Set dst (Replicate8B src)); | |
8315 expand %{ | |
8316 iRegL tmp; | |
8317 Repl8B_reg_helper(tmp, src); | |
8318 regL_to_stkD(dst, tmp); | |
8319 %} | |
8320 %} | |
8321 | |
8322 // Replicate scalar constant to packed byte values in Double register | |
8323 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
8324 match(Set dst (Replicate8B src)); | |
8325 #ifdef _LP64 | |
8326 size(36); | |
8327 #else | |
8328 size(8); | |
8329 #endif | |
8330 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
8331 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
8332 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
8333 ins_pipe(loadConFD); | |
8334 %} | |
8335 | |
8336 // Replicate scalar to packed char values into stack slot | |
8337 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
8338 effect(DEF dst, USE src); | |
8339 format %{ "SLLX $src,48,$dst\n\t" | |
8340 "SRLX $dst,16,O7\n\t" | |
8341 "OR $dst,O7,$dst\n\t" | |
8342 "SRLX $dst,32,O7\n\t" | |
8343 "OR $dst,O7,$dst\t! replicate4C" %} | |
8344 ins_encode( enc_repl4s(src, dst) ); | |
8345 ins_pipe(ialu_reg); | |
8346 %} | |
8347 | |
8348 // Replicate scalar to packed char values into stack slot | |
8349 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
8350 match(Set dst (Replicate4C src)); | |
8351 expand %{ | |
8352 iRegL tmp; | |
8353 Repl4C_reg_helper(tmp, src); | |
8354 regL_to_stkD(dst, tmp); | |
8355 %} | |
8356 %} | |
8357 | |
8358 // Replicate scalar constant to packed char values in Double register | |
8359 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
8360 match(Set dst (Replicate4C src)); | |
8361 #ifdef _LP64 | |
8362 size(36); | |
8363 #else | |
8364 size(8); | |
8365 #endif | |
8366 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
8367 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8368 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8369 ins_pipe(loadConFD); | |
8370 %} | |
8371 | |
8372 // Replicate scalar to packed short values into stack slot | |
8373 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
8374 effect(DEF dst, USE src); | |
8375 format %{ "SLLX $src,48,$dst\n\t" | |
8376 "SRLX $dst,16,O7\n\t" | |
8377 "OR $dst,O7,$dst\n\t" | |
8378 "SRLX $dst,32,O7\n\t" | |
8379 "OR $dst,O7,$dst\t! replicate4S" %} | |
8380 ins_encode( enc_repl4s(src, dst) ); | |
8381 ins_pipe(ialu_reg); | |
8382 %} | |
8383 | |
8384 // Replicate scalar to packed short values into stack slot | |
8385 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
8386 match(Set dst (Replicate4S src)); | |
8387 expand %{ | |
8388 iRegL tmp; | |
8389 Repl4S_reg_helper(tmp, src); | |
8390 regL_to_stkD(dst, tmp); | |
8391 %} | |
8392 %} | |
8393 | |
8394 // Replicate scalar constant to packed short values in Double register | |
8395 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
8396 match(Set dst (Replicate4S src)); | |
8397 #ifdef _LP64 | |
8398 size(36); | |
8399 #else | |
8400 size(8); | |
8401 #endif | |
8402 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
8403 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8404 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8405 ins_pipe(loadConFD); | |
8406 %} | |
8407 | |
8408 // Replicate scalar to packed int values in Double register | |
8409 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
8410 effect(DEF dst, USE src); | |
8411 format %{ "SLLX $src,32,$dst\n\t" | |
8412 "SRLX $dst,32,O7\n\t" | |
8413 "OR $dst,O7,$dst\t! replicate2I" %} | |
8414 ins_encode( enc_repl2i(src, dst)); | |
8415 ins_pipe(ialu_reg); | |
8416 %} | |
8417 | |
8418 // Replicate scalar to packed int values in Double register | |
8419 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
8420 match(Set dst (Replicate2I src)); | |
8421 expand %{ | |
8422 iRegL tmp; | |
8423 Repl2I_reg_helper(tmp, src); | |
8424 regL_to_stkD(dst, tmp); | |
8425 %} | |
8426 %} | |
8427 | |
8428 // Replicate scalar zero constant to packed int values in Double register | |
8429 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
8430 match(Set dst (Replicate2I src)); | |
8431 #ifdef _LP64 | |
8432 size(36); | |
8433 #else | |
8434 size(8); | |
8435 #endif | |
8436 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
8437 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
8438 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
8439 ins_pipe(loadConFD); | |
8440 %} | |
8441 | |
8442 //----------Control Flow Instructions------------------------------------------ | |
8443 // Compare Instructions | |
8444 // Compare Integers | |
8445 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8446 match(Set icc (CmpI op1 op2)); | |
8447 effect( DEF icc, USE op1, USE op2 ); | |
8448 | |
8449 size(4); | |
8450 format %{ "CMP $op1,$op2" %} | |
8451 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8452 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8453 ins_pipe(ialu_cconly_reg_reg); | |
8454 %} | |
8455 | |
8456 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8457 match(Set icc (CmpU op1 op2)); | |
8458 | |
8459 size(4); | |
8460 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8461 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8462 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8463 ins_pipe(ialu_cconly_reg_reg); | |
8464 %} | |
8465 | |
8466 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8467 match(Set icc (CmpI op1 op2)); | |
8468 effect( DEF icc, USE op1 ); | |
8469 | |
8470 size(4); | |
8471 format %{ "CMP $op1,$op2" %} | |
8472 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8473 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8474 ins_pipe(ialu_cconly_reg_imm); | |
8475 %} | |
8476 | |
8477 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8478 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8479 | |
8480 size(4); | |
8481 format %{ "BTST $op2,$op1" %} | |
8482 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8483 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8484 ins_pipe(ialu_cconly_reg_reg_zero); | |
8485 %} | |
8486 | |
8487 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8488 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8489 | |
8490 size(4); | |
8491 format %{ "BTST $op2,$op1" %} | |
8492 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8493 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8494 ins_pipe(ialu_cconly_reg_imm_zero); | |
8495 %} | |
8496 | |
8497 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8498 match(Set xcc (CmpL op1 op2)); | |
8499 effect( DEF xcc, USE op1, USE op2 ); | |
8500 | |
8501 size(4); | |
8502 format %{ "CMP $op1,$op2\t\t! long" %} | |
8503 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8504 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8505 ins_pipe(ialu_cconly_reg_reg); | |
8506 %} | |
8507 | |
8508 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8509 match(Set xcc (CmpL op1 con)); | |
8510 effect( DEF xcc, USE op1, USE con ); | |
8511 | |
8512 size(4); | |
8513 format %{ "CMP $op1,$con\t\t! long" %} | |
8514 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8515 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8516 ins_pipe(ialu_cconly_reg_reg); | |
8517 %} | |
8518 | |
8519 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8520 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8521 effect( DEF xcc, USE op1, USE op2 ); | |
8522 | |
8523 size(4); | |
8524 format %{ "BTST $op1,$op2\t\t! long" %} | |
8525 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8526 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8527 ins_pipe(ialu_cconly_reg_reg); | |
8528 %} | |
8529 | |
8530 // useful for checking the alignment of a pointer: | |
8531 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8532 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8533 effect( DEF xcc, USE op1, USE con ); | |
8534 | |
8535 size(4); | |
8536 format %{ "BTST $op1,$con\t\t! long" %} | |
8537 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8538 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8539 ins_pipe(ialu_cconly_reg_reg); | |
8540 %} | |
8541 | |
8542 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8543 match(Set icc (CmpU op1 op2)); | |
8544 | |
8545 size(4); | |
8546 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8547 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8548 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8549 ins_pipe(ialu_cconly_reg_imm); | |
8550 %} | |
8551 | |
8552 // Compare Pointers | |
8553 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8554 match(Set pcc (CmpP op1 op2)); | |
8555 | |
8556 size(4); | |
8557 format %{ "CMP $op1,$op2\t! ptr" %} | |
8558 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8559 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8560 ins_pipe(ialu_cconly_reg_reg); | |
8561 %} | |
8562 | |
8563 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8564 match(Set pcc (CmpP op1 op2)); | |
8565 | |
8566 size(4); | |
8567 format %{ "CMP $op1,$op2\t! ptr" %} | |
8568 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8569 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8570 ins_pipe(ialu_cconly_reg_imm); | |
8571 %} | |
8572 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8573 // Compare Narrow oops |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8574 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8575 match(Set icc (CmpN op1 op2)); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8576 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8577 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8578 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8579 opcode(Assembler::subcc_op3, Assembler::arith_op); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8580 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8581 ins_pipe(ialu_cconly_reg_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8582 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8583 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8584 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8585 match(Set icc (CmpN op1 op2)); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8586 |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8587 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8588 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8589 opcode(Assembler::subcc_op3, Assembler::arith_op); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8590 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8591 ins_pipe(ialu_cconly_reg_imm); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8592 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8593 |
0 | 8594 //----------Max and Min-------------------------------------------------------- |
8595 // Min Instructions | |
8596 // Conditional move for min | |
8597 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8598 effect( USE_DEF op2, USE op1, USE icc ); | |
8599 | |
8600 size(4); | |
8601 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8602 opcode(Assembler::less); | |
8603 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8604 ins_pipe(ialu_reg_flags); | |
8605 %} | |
8606 | |
8607 // Min Register with Register. | |
8608 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8609 match(Set op2 (MinI op1 op2)); | |
8610 ins_cost(DEFAULT_COST*2); | |
8611 expand %{ | |
8612 flagsReg icc; | |
8613 compI_iReg(icc,op1,op2); | |
8614 cmovI_reg_lt(op2,op1,icc); | |
8615 %} | |
8616 %} | |
8617 | |
8618 // Max Instructions | |
8619 // Conditional move for max | |
8620 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8621 effect( USE_DEF op2, USE op1, USE icc ); | |
8622 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8623 opcode(Assembler::greater); | |
8624 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8625 ins_pipe(ialu_reg_flags); | |
8626 %} | |
8627 | |
8628 // Max Register with Register | |
8629 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8630 match(Set op2 (MaxI op1 op2)); | |
8631 ins_cost(DEFAULT_COST*2); | |
8632 expand %{ | |
8633 flagsReg icc; | |
8634 compI_iReg(icc,op1,op2); | |
8635 cmovI_reg_gt(op2,op1,icc); | |
8636 %} | |
8637 %} | |
8638 | |
8639 | |
8640 //----------Float Compares---------------------------------------------------- | |
8641 // Compare floating, generate condition code | |
8642 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
8643 match(Set fcc (CmpF src1 src2)); | |
8644 | |
8645 size(4); | |
8646 format %{ "FCMPs $fcc,$src1,$src2" %} | |
8647 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
8648 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
8649 ins_pipe(faddF_fcc_reg_reg_zero); | |
8650 %} | |
8651 | |
8652 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
8653 match(Set fcc (CmpD src1 src2)); | |
8654 | |
8655 size(4); | |
8656 format %{ "FCMPd $fcc,$src1,$src2" %} | |
8657 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
8658 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
8659 ins_pipe(faddD_fcc_reg_reg_zero); | |
8660 %} | |
8661 | |
8662 | |
8663 // Compare floating, generate -1,0,1 | |
8664 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
8665 match(Set dst (CmpF3 src1 src2)); | |
8666 effect(KILL fcc0); | |
8667 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8668 format %{ "fcmpl $dst,$src1,$src2" %} | |
8669 // Primary = float | |
8670 opcode( true ); | |
8671 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8672 ins_pipe( floating_cmp ); | |
8673 %} | |
8674 | |
8675 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
8676 match(Set dst (CmpD3 src1 src2)); | |
8677 effect(KILL fcc0); | |
8678 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8679 format %{ "dcmpl $dst,$src1,$src2" %} | |
8680 // Primary = double (not float) | |
8681 opcode( false ); | |
8682 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8683 ins_pipe( floating_cmp ); | |
8684 %} | |
8685 | |
8686 //----------Branches--------------------------------------------------------- | |
8687 // Jump | |
8688 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
8689 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
8690 match(Jump switch_val); | |
8691 | |
8692 ins_cost(350); | |
8693 | |
8694 format %{ "SETHI [hi(table_base)],O7\n\t" | |
8695 "ADD O7, lo(table_base), O7\n\t" | |
8696 "LD [O7+$switch_val], O7\n\t" | |
8697 "JUMP O7" | |
8698 %} | |
8699 ins_encode( jump_enc( switch_val, table) ); | |
8700 ins_pc_relative(1); | |
8701 ins_pipe(ialu_reg_reg); | |
8702 %} | |
8703 | |
8704 // Direct Branch. Use V8 version with longer range. | |
8705 instruct branch(label labl) %{ | |
8706 match(Goto); | |
8707 effect(USE labl); | |
8708 | |
8709 size(8); | |
8710 ins_cost(BRANCH_COST); | |
8711 format %{ "BA $labl" %} | |
8712 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
8713 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
8714 ins_encode( enc_ba( labl ) ); | |
8715 ins_pc_relative(1); | |
8716 ins_pipe(br); | |
8717 %} | |
8718 | |
8719 // Conditional Direct Branch | |
8720 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
8721 match(If cmp icc); | |
8722 effect(USE labl); | |
8723 | |
8724 size(8); | |
8725 ins_cost(BRANCH_COST); | |
8726 format %{ "BP$cmp $icc,$labl" %} | |
8727 // Prim = bits 24-22, Secnd = bits 31-30 | |
8728 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8729 ins_pc_relative(1); | |
8730 ins_pipe(br_cc); | |
8731 %} | |
8732 | |
8733 // Branch-on-register tests all 64 bits. We assume that values | |
8734 // in 64-bit registers always remains zero or sign extended | |
8735 // unless our code munges the high bits. Interrupts can chop | |
8736 // the high order bits to zero or sign at any time. | |
8737 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
8738 match(If cmp (CmpI op1 zero)); | |
8739 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8740 effect(USE labl); | |
8741 | |
8742 size(8); | |
8743 ins_cost(BRANCH_COST); | |
8744 format %{ "BR$cmp $op1,$labl" %} | |
8745 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8746 ins_pc_relative(1); | |
8747 ins_pipe(br_reg); | |
8748 %} | |
8749 | |
8750 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
8751 match(If cmp (CmpP op1 null)); | |
8752 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8753 effect(USE labl); | |
8754 | |
8755 size(8); | |
8756 ins_cost(BRANCH_COST); | |
8757 format %{ "BR$cmp $op1,$labl" %} | |
8758 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8759 ins_pc_relative(1); | |
8760 ins_pipe(br_reg); | |
8761 %} | |
8762 | |
8763 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
8764 match(If cmp (CmpL op1 zero)); | |
8765 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8766 effect(USE labl); | |
8767 | |
8768 size(8); | |
8769 ins_cost(BRANCH_COST); | |
8770 format %{ "BR$cmp $op1,$labl" %} | |
8771 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8772 ins_pc_relative(1); | |
8773 ins_pipe(br_reg); | |
8774 %} | |
8775 | |
8776 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
8777 match(If cmp icc); | |
8778 effect(USE labl); | |
8779 | |
8780 format %{ "BP$cmp $icc,$labl" %} | |
8781 // Prim = bits 24-22, Secnd = bits 31-30 | |
8782 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8783 ins_pc_relative(1); | |
8784 ins_pipe(br_cc); | |
8785 %} | |
8786 | |
8787 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
8788 match(If cmp pcc); | |
8789 effect(USE labl); | |
8790 | |
8791 size(8); | |
8792 ins_cost(BRANCH_COST); | |
8793 format %{ "BP$cmp $pcc,$labl" %} | |
8794 // Prim = bits 24-22, Secnd = bits 31-30 | |
8795 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
8796 ins_pc_relative(1); | |
8797 ins_pipe(br_cc); | |
8798 %} | |
8799 | |
8800 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
8801 match(If cmp fcc); | |
8802 effect(USE labl); | |
8803 | |
8804 size(8); | |
8805 ins_cost(BRANCH_COST); | |
8806 format %{ "FBP$cmp $fcc,$labl" %} | |
8807 // Prim = bits 24-22, Secnd = bits 31-30 | |
8808 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
8809 ins_pc_relative(1); | |
8810 ins_pipe(br_fcc); | |
8811 %} | |
8812 | |
8813 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
8814 match(CountedLoopEnd cmp icc); | |
8815 effect(USE labl); | |
8816 | |
8817 size(8); | |
8818 ins_cost(BRANCH_COST); | |
8819 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
8820 // Prim = bits 24-22, Secnd = bits 31-30 | |
8821 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8822 ins_pc_relative(1); | |
8823 ins_pipe(br_cc); | |
8824 %} | |
8825 | |
8826 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
8827 match(CountedLoopEnd cmp icc); | |
8828 effect(USE labl); | |
8829 | |
8830 size(8); | |
8831 ins_cost(BRANCH_COST); | |
8832 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
8833 // Prim = bits 24-22, Secnd = bits 31-30 | |
8834 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8835 ins_pc_relative(1); | |
8836 ins_pipe(br_cc); | |
8837 %} | |
8838 | |
8839 // ============================================================================ | |
8840 // Long Compare | |
8841 // | |
8842 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
8843 // is tricky. The flavor of compare used depends on whether we are testing | |
8844 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
8845 // The GE test is the negated LT test. The LE test can be had by commuting | |
8846 // the operands (yielding a GE test) and then negating; negate again for the | |
8847 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
8848 // NE test is negated from that. | |
8849 | |
8850 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
8851 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
8852 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
8853 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
8854 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
8855 // foo match ends up with the wrong leaf. One fix is to not match both | |
8856 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
8857 // both forms beat the trinary form of long-compare and both are very useful | |
8858 // on Intel which has so few registers. | |
8859 | |
8860 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
8861 match(If cmp xcc); | |
8862 effect(USE labl); | |
8863 | |
8864 size(8); | |
8865 ins_cost(BRANCH_COST); | |
8866 format %{ "BP$cmp $xcc,$labl" %} | |
8867 // Prim = bits 24-22, Secnd = bits 31-30 | |
8868 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
8869 ins_pc_relative(1); | |
8870 ins_pipe(br_cc); | |
8871 %} | |
8872 | |
8873 // Manifest a CmpL3 result in an integer register. Very painful. | |
8874 // This is the test to avoid. | |
8875 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
8876 match(Set dst (CmpL3 src1 src2) ); | |
8877 effect( KILL ccr ); | |
8878 ins_cost(6*DEFAULT_COST); | |
8879 size(24); | |
8880 format %{ "CMP $src1,$src2\t\t! long\n" | |
8881 "\tBLT,a,pn done\n" | |
8882 "\tMOV -1,$dst\t! delay slot\n" | |
8883 "\tBGT,a,pn done\n" | |
8884 "\tMOV 1,$dst\t! delay slot\n" | |
8885 "\tCLR $dst\n" | |
8886 "done:" %} | |
8887 ins_encode( cmpl_flag(src1,src2,dst) ); | |
8888 ins_pipe(cmpL_reg); | |
8889 %} | |
8890 | |
8891 // Conditional move | |
8892 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
8893 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
8894 ins_cost(150); | |
8895 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
8896 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
8897 ins_pipe(ialu_reg); | |
8898 %} | |
8899 | |
8900 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
8901 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
8902 ins_cost(140); | |
8903 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
8904 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
8905 ins_pipe(ialu_imm); | |
8906 %} | |
8907 | |
8908 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
8909 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
8910 ins_cost(150); | |
8911 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
8912 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
8913 ins_pipe(ialu_reg); | |
8914 %} | |
8915 | |
8916 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
8917 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
8918 ins_cost(140); | |
8919 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
8920 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
8921 ins_pipe(ialu_imm); | |
8922 %} | |
8923 | |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8924 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8925 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8926 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8927 format %{ "MOV$cmp $xcc,$src,$dst" %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8928 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8929 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8930 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
8931 |
0 | 8932 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
8933 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
8934 ins_cost(150); | |
8935 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
8936 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
8937 ins_pipe(ialu_reg); | |
8938 %} | |
8939 | |
8940 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
8941 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
8942 ins_cost(140); | |
8943 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
8944 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
8945 ins_pipe(ialu_imm); | |
8946 %} | |
8947 | |
8948 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
8949 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
8950 ins_cost(150); | |
8951 opcode(0x101); | |
8952 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
8953 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
8954 ins_pipe(int_conditional_float_move); | |
8955 %} | |
8956 | |
8957 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
8958 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
8959 ins_cost(150); | |
8960 opcode(0x102); | |
8961 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
8962 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
8963 ins_pipe(int_conditional_float_move); | |
8964 %} | |
8965 | |
8966 // ============================================================================ | |
8967 // Safepoint Instruction | |
8968 instruct safePoint_poll(iRegP poll) %{ | |
8969 match(SafePoint poll); | |
8970 effect(USE poll); | |
8971 | |
8972 size(4); | |
8973 #ifdef _LP64 | |
8974 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
8975 #else | |
8976 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
8977 #endif | |
8978 ins_encode %{ | |
8979 __ relocate(relocInfo::poll_type); | |
8980 __ ld_ptr($poll$$Register, 0, G0); | |
8981 %} | |
8982 ins_pipe(loadPollP); | |
8983 %} | |
8984 | |
8985 // ============================================================================ | |
8986 // Call Instructions | |
8987 // Call Java Static Instruction | |
8988 instruct CallStaticJavaDirect( method meth ) %{ | |
8989 match(CallStaticJava); | |
8990 effect(USE meth); | |
8991 | |
8992 size(8); | |
8993 ins_cost(CALL_COST); | |
8994 format %{ "CALL,static ; NOP ==> " %} | |
8995 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
8996 ins_pc_relative(1); | |
8997 ins_pipe(simple_call); | |
8998 %} | |
8999 | |
9000 // Call Java Dynamic Instruction | |
9001 instruct CallDynamicJavaDirect( method meth ) %{ | |
9002 match(CallDynamicJava); | |
9003 effect(USE meth); | |
9004 | |
9005 ins_cost(CALL_COST); | |
9006 format %{ "SET (empty),R_G5\n\t" | |
9007 "CALL,dynamic ; NOP ==> " %} | |
9008 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9009 ins_pc_relative(1); | |
9010 ins_pipe(call); | |
9011 %} | |
9012 | |
9013 // Call Runtime Instruction | |
9014 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9015 match(CallRuntime); | |
9016 effect(USE meth, KILL l7); | |
9017 ins_cost(CALL_COST); | |
9018 format %{ "CALL,runtime" %} | |
9019 ins_encode( Java_To_Runtime( meth ), | |
9020 call_epilog, adjust_long_from_native_call ); | |
9021 ins_pc_relative(1); | |
9022 ins_pipe(simple_call); | |
9023 %} | |
9024 | |
9025 // Call runtime without safepoint - same as CallRuntime | |
9026 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9027 match(CallLeaf); | |
9028 effect(USE meth, KILL l7); | |
9029 ins_cost(CALL_COST); | |
9030 format %{ "CALL,runtime leaf" %} | |
9031 ins_encode( Java_To_Runtime( meth ), | |
9032 call_epilog, | |
9033 adjust_long_from_native_call ); | |
9034 ins_pc_relative(1); | |
9035 ins_pipe(simple_call); | |
9036 %} | |
9037 | |
9038 // Call runtime without safepoint - same as CallLeaf | |
9039 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9040 match(CallLeafNoFP); | |
9041 effect(USE meth, KILL l7); | |
9042 ins_cost(CALL_COST); | |
9043 format %{ "CALL,runtime leaf nofp" %} | |
9044 ins_encode( Java_To_Runtime( meth ), | |
9045 call_epilog, | |
9046 adjust_long_from_native_call ); | |
9047 ins_pc_relative(1); | |
9048 ins_pipe(simple_call); | |
9049 %} | |
9050 | |
9051 // Tail Call; Jump from runtime stub to Java code. | |
9052 // Also known as an 'interprocedural jump'. | |
9053 // Target of jump will eventually return to caller. | |
9054 // TailJump below removes the return address. | |
9055 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9056 match(TailCall jump_target method_oop ); | |
9057 | |
9058 ins_cost(CALL_COST); | |
9059 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9060 ins_encode(form_jmpl(jump_target)); | |
9061 ins_pipe(tail_call); | |
9062 %} | |
9063 | |
9064 | |
9065 // Return Instruction | |
9066 instruct Ret() %{ | |
9067 match(Return); | |
9068 | |
9069 // The epilogue node did the ret already. | |
9070 size(0); | |
9071 format %{ "! return" %} | |
9072 ins_encode(); | |
9073 ins_pipe(empty); | |
9074 %} | |
9075 | |
9076 | |
9077 // Tail Jump; remove the return address; jump to target. | |
9078 // TailCall above leaves the return address around. | |
9079 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9080 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9081 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9082 // in %i0. | |
9083 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9084 match( TailJump jump_target ex_oop ); | |
9085 ins_cost(CALL_COST); | |
9086 format %{ "! discard R_O7\n\t" | |
9087 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9088 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9089 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9090 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9091 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9092 ins_pipe(tail_call); | |
9093 %} | |
9094 | |
9095 // Create exception oop: created by stack-crawling runtime code. | |
9096 // Created exception is now available to this handler, and is setup | |
9097 // just prior to jumping to this handler. No code emitted. | |
9098 instruct CreateException( o0RegP ex_oop ) | |
9099 %{ | |
9100 match(Set ex_oop (CreateEx)); | |
9101 ins_cost(0); | |
9102 | |
9103 size(0); | |
9104 // use the following format syntax | |
9105 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9106 ins_encode(); | |
9107 ins_pipe(empty); | |
9108 %} | |
9109 | |
9110 | |
9111 // Rethrow exception: | |
9112 // The exception oop will come in the first argument position. | |
9113 // Then JUMP (not call) to the rethrow stub code. | |
9114 instruct RethrowException() | |
9115 %{ | |
9116 match(Rethrow); | |
9117 ins_cost(CALL_COST); | |
9118 | |
9119 // use the following format syntax | |
9120 format %{ "Jmp rethrow_stub" %} | |
9121 ins_encode(enc_rethrow); | |
9122 ins_pipe(tail_call); | |
9123 %} | |
9124 | |
9125 | |
9126 // Die now | |
9127 instruct ShouldNotReachHere( ) | |
9128 %{ | |
9129 match(Halt); | |
9130 ins_cost(CALL_COST); | |
9131 | |
9132 size(4); | |
9133 // Use the following format syntax | |
9134 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9135 ins_encode( form2_illtrap() ); | |
9136 ins_pipe(tail_call); | |
9137 %} | |
9138 | |
9139 // ============================================================================ | |
9140 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
9141 // array for an instance of the superklass. Set a hidden internal cache on a | |
9142 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
9143 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
9144 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
9145 match(Set index (PartialSubtypeCheck sub super)); | |
9146 effect( KILL pcc, KILL o7 ); | |
9147 ins_cost(DEFAULT_COST*10); | |
9148 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
9149 ins_encode( enc_PartialSubtypeCheck() ); | |
9150 ins_pipe(partial_subtype_check_pipe); | |
9151 %} | |
9152 | |
9153 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
9154 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
9155 effect( KILL idx, KILL o7 ); | |
9156 ins_cost(DEFAULT_COST*10); | |
9157 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
9158 ins_encode( enc_PartialSubtypeCheck() ); | |
9159 ins_pipe(partial_subtype_check_pipe); | |
9160 %} | |
9161 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9162 |
0 | 9163 // ============================================================================ |
9164 // inlined locking and unlocking | |
9165 | |
9166 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9167 match(Set pcc (FastLock object box)); | |
9168 | |
9169 effect(KILL scratch, TEMP scratch2); | |
9170 ins_cost(100); | |
9171 | |
9172 size(4*112); // conservative overestimation ... | |
9173 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9174 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
9175 ins_pipe(long_memory_op); | |
9176 %} | |
9177 | |
9178 | |
9179 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9180 match(Set pcc (FastUnlock object box)); | |
9181 effect(KILL scratch, TEMP scratch2); | |
9182 ins_cost(100); | |
9183 | |
9184 size(4*120); // conservative overestimation ... | |
9185 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9186 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
9187 ins_pipe(long_memory_op); | |
9188 %} | |
9189 | |
9190 // Count and Base registers are fixed because the allocator cannot | |
9191 // kill unknown registers. The encodings are generic. | |
9192 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
9193 match(Set dummy (ClearArray cnt base)); | |
9194 effect(TEMP temp, KILL ccr); | |
9195 ins_cost(300); | |
9196 format %{ "MOV $cnt,$temp\n" | |
9197 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
9198 " BRge loop\t\t! Clearing loop\n" | |
9199 " STX G0,[$base+$temp]\t! delay slot" %} | |
9200 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
9201 ins_pipe(long_memory_op); | |
9202 %} | |
9203 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9204 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9205 o7RegI tmp3, flagsReg ccr) %{ |
0 | 9206 match(Set result (StrComp str1 str2)); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
81
diff
changeset
|
9207 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); |
0 | 9208 ins_cost(300); |
9209 format %{ "String Compare $str1,$str2 -> $result" %} | |
9210 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) ); | |
9211 ins_pipe(long_memory_op); | |
9212 %} | |
9213 | |
681 | 9214 instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, |
9215 o7RegI tmp3, flagsReg ccr) %{ | |
9216 match(Set result (StrEquals str1 str2)); | |
9217 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); | |
9218 ins_cost(300); | |
9219 format %{ "String Equals $str1,$str2 -> $result" %} | |
9220 ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) ); | |
9221 ins_pipe(long_memory_op); | |
9222 %} | |
9223 | |
9224 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, | |
9225 flagsReg ccr) %{ | |
9226 match(Set result (AryEq ary1 ary2)); | |
9227 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
9228 ins_cost(300); | |
9229 format %{ "Array Equals $ary1,$ary2 -> $result" %} | |
9230 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result)); | |
9231 ins_pipe(long_memory_op); | |
9232 %} | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9233 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9234 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9235 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9236 instruct popCountI(iRegI dst, iRegI src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9237 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9238 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9239 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9240 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9241 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9242 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9243 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9244 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9245 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9246 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9247 // Note: Long.bitCount(long) returns an int. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9248 instruct popCountL(iRegI dst, iRegL src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9249 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9250 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9251 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9252 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9253 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9254 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9255 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9256 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9257 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9258 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9259 |
0 | 9260 // ============================================================================ |
9261 //------------Bytes reverse-------------------------------------------------- | |
9262 | |
9263 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
9264 match(Set dst (ReverseBytesI src)); | |
9265 effect(DEF dst, USE src); | |
9266 | |
9267 // Op cost is artificially doubled to make sure that load or store | |
9268 // instructions are preferred over this one which requires a spill | |
9269 // onto a stack slot. | |
9270 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9271 size(8); | |
9272 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9273 opcode(Assembler::lduwa_op3); | |
9274 ins_encode( form3_mem_reg_little(src, dst) ); | |
9275 ins_pipe( iload_mem ); | |
9276 %} | |
9277 | |
9278 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ | |
9279 match(Set dst (ReverseBytesL src)); | |
9280 effect(DEF dst, USE src); | |
9281 | |
9282 // Op cost is artificially doubled to make sure that load or store | |
9283 // instructions are preferred over this one which requires a spill | |
9284 // onto a stack slot. | |
9285 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9286 size(8); | |
9287 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9288 | |
9289 opcode(Assembler::ldxa_op3); | |
9290 ins_encode( form3_mem_reg_little(src, dst) ); | |
9291 ins_pipe( iload_mem ); | |
9292 %} | |
9293 | |
9294 // Load Integer reversed byte order | |
9295 instruct loadI_reversed(iRegI dst, memory src) %{ | |
9296 match(Set dst (ReverseBytesI (LoadI src))); | |
9297 | |
9298 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9299 size(8); | |
9300 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9301 | |
9302 opcode(Assembler::lduwa_op3); | |
9303 ins_encode( form3_mem_reg_little( src, dst) ); | |
9304 ins_pipe(iload_mem); | |
9305 %} | |
9306 | |
9307 // Load Long - aligned and reversed | |
9308 instruct loadL_reversed(iRegL dst, memory src) %{ | |
9309 match(Set dst (ReverseBytesL (LoadL src))); | |
9310 | |
9311 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9312 size(8); | |
9313 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9314 | |
9315 opcode(Assembler::ldxa_op3); | |
9316 ins_encode( form3_mem_reg_little( src, dst ) ); | |
9317 ins_pipe(iload_mem); | |
9318 %} | |
9319 | |
9320 // Store Integer reversed byte order | |
9321 instruct storeI_reversed(memory dst, iRegI src) %{ | |
9322 match(Set dst (StoreI dst (ReverseBytesI src))); | |
9323 | |
9324 ins_cost(MEMORY_REF_COST); | |
9325 size(8); | |
9326 format %{ "STWA $src, $dst\t!asi=primary_little" %} | |
9327 | |
9328 opcode(Assembler::stwa_op3); | |
9329 ins_encode( form3_mem_reg_little( dst, src) ); | |
9330 ins_pipe(istore_mem_reg); | |
9331 %} | |
9332 | |
9333 // Store Long reversed byte order | |
9334 instruct storeL_reversed(memory dst, iRegL src) %{ | |
9335 match(Set dst (StoreL dst (ReverseBytesL src))); | |
9336 | |
9337 ins_cost(MEMORY_REF_COST); | |
9338 size(8); | |
9339 format %{ "STXA $src, $dst\t!asi=primary_little" %} | |
9340 | |
9341 opcode(Assembler::stxa_op3); | |
9342 ins_encode( form3_mem_reg_little( dst, src) ); | |
9343 ins_pipe(istore_mem_reg); | |
9344 %} | |
9345 | |
9346 //----------PEEPHOLE RULES----------------------------------------------------- | |
9347 // These must follow all instruction definitions as they use the names | |
9348 // defined in the instructions definitions. | |
9349 // | |
605 | 9350 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 9351 // |
9352 // peepconstraint %{ | |
9353 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
9354 // [, ...] ); | |
9355 // // instruction numbers are zero-based using left to right order in peepmatch | |
9356 // | |
9357 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
9358 // // provide an instruction_number.operand_name for each operand that appears | |
9359 // // in the replacement instruction's match rule | |
9360 // | |
9361 // ---------VM FLAGS--------------------------------------------------------- | |
9362 // | |
9363 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
9364 // | |
9365 // Each peephole rule is given an identifying number starting with zero and | |
9366 // increasing by one in the order seen by the parser. An individual peephole | |
9367 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
9368 // on the command-line. | |
9369 // | |
9370 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
9371 // | |
9372 // Only match adjacent instructions in same basic block | |
9373 // Only equality constraints | |
9374 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
9375 // Only one replacement instruction | |
9376 // | |
9377 // ---------EXAMPLE---------------------------------------------------------- | |
9378 // | |
9379 // // pertinent parts of existing instructions in architecture description | |
9380 // instruct movI(eRegI dst, eRegI src) %{ | |
9381 // match(Set dst (CopyI src)); | |
9382 // %} | |
9383 // | |
9384 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
9385 // match(Set dst (AddI dst src)); | |
9386 // effect(KILL cr); | |
9387 // %} | |
9388 // | |
9389 // // Change (inc mov) to lea | |
9390 // peephole %{ | |
9391 // // increment preceeded by register-register move | |
9392 // peepmatch ( incI_eReg movI ); | |
9393 // // require that the destination register of the increment | |
9394 // // match the destination register of the move | |
9395 // peepconstraint ( 0.dst == 1.dst ); | |
9396 // // construct a replacement instruction that sets | |
9397 // // the destination to ( move's source register + one ) | |
9398 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
9399 // %} | |
9400 // | |
9401 | |
9402 // // Change load of spilled value to only a spill | |
9403 // instruct storeI(memory mem, eRegI src) %{ | |
9404 // match(Set mem (StoreI mem src)); | |
9405 // %} | |
9406 // | |
9407 // instruct loadI(eRegI dst, memory mem) %{ | |
9408 // match(Set dst (LoadI mem)); | |
9409 // %} | |
9410 // | |
9411 // peephole %{ | |
9412 // peepmatch ( loadI storeI ); | |
9413 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
9414 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
9415 // %} | |
9416 | |
9417 //----------SMARTSPILL RULES--------------------------------------------------- | |
9418 // These must follow all instruction definitions as they use the names | |
9419 // defined in the instructions definitions. | |
9420 // | |
9421 // SPARC will probably not have any of these rules due to RISC instruction set. | |
9422 | |
9423 //----------PIPELINE----------------------------------------------------------- | |
9424 // Rules which define the behavior of the target architectures pipeline. |