AMD64Assembler (Graal OpenJDK Project Documentation)

java.lang.Object
- com.oracle.graal.asm.Assembler
- - com.oracle.graal.asm.amd64.AMD64Assembler

Direct Known Subclasses:

AMD64MacroAssembler
```
public class AMD64Assembler
extends Assembler
```
This class implements an assembler that can encode most X86 instructions.

Nested Class Summary

Nested Classes
Modifier and Type	Class and Description
`static class`	`AMD64Assembler.AMD64BinaryArithmetic` Arithmetic operation with operand order of RM, MR or MI.
`static class`	`AMD64Assembler.AMD64ImmOp` Base class for AMD64 opcodes with immediate operands.
`static class`	`AMD64Assembler.AMD64MIOp` Opcodes with operand order of MI.
`static class`	`AMD64Assembler.AMD64MOp` Opcodes with operand order of M.
`static class`	`AMD64Assembler.AMD64MROp` Opcode with operand order of MR.
`static class`	`AMD64Assembler.AMD64Op` Base class for AMD64 opcodes.
`static class`	`AMD64Assembler.AMD64RMIOp` Opcodes with operand order of RMI.
`static class`	`AMD64Assembler.AMD64RMOp` Opcode with operand order of RM.
`static class`	`AMD64Assembler.AMD64RROp` Opcode with operand order of either RM or MR.
`static class`	`AMD64Assembler.AMD64Shift` Shift operation with operand order of M1, MC or MI.
`static class`	`AMD64Assembler.ConditionFlag` The x86 condition codes used for conditional jumps/moves.
`private static class`	`AMD64Assembler.OpAssertion` Operand size and register type constraints.
`static class`	`AMD64Assembler.OperandSize` The x86 operand sizes.
`private static class`	`AMD64Assembler.Prefix` Constants for X86 prefix bytes.
`static class`	`AMD64Assembler.SSEOp`

Nested classes/interfaces inherited from class com.oracle.graal.asm.Assembler
Assembler.InstructionCounter, Assembler.LabelHint

Field Summary

Fields
Modifier and Type	Field and Description
`Register`	`frameRegister` The register to which `Register.Frame` and `Register.CallerFrame` are bound.
`private static int`	`MinEncodingNeedsRex`
`private static AMD64Address`	`Placeholder` A sentinel value used as a place holder in an instruction stream for an address that will be patched.

Fields inherited from class com.oracle.graal.asm.Assembler
target

Constructor Summary

Constructors
Constructor and Description

AMD64Assembler(TargetDescription target, RegisterConfig registerConfig)
Constructs an assembler for the AMD64 architecture.

Constructors
Constructor and Description
`AMD64Assembler(TargetDescription target, RegisterConfig registerConfig)` Constructs an assembler for the AMD64 architecture.

Method Summary

All Methods Static Methods Instance Methods Concrete Methods
Modifier and Type	Method and Description
`void`	`addl(AMD64Address dst, int imm32)`
`void`	`addl(Register dst, int imm32)`
`void`	`addq(AMD64Address dst, int imm32)`
`void`	`addq(AMD64Address dst, Register src)`
`void`	`addq(Register dst, int imm32)`
`void`	`addq(Register dst, Register src)`
`private void`	`addrNop4()`
`private void`	`addrNop5()`
`private void`	`addrNop7()`
`private void`	`addrNop8()`
`void`	`align(int modulus)`
`void`	`andl(Register dst, int imm32)`
`void`	`andq(Register dst, int imm32)`
`void`	`bswapl(Register reg)`
`void`	`bswapq(Register reg)`
`void`	`call()` Emits a direct call instruction.
`void`	`call(Register src)`
`void`	`cdql()`
`void`	`cdqq()`
`void`	`cmovl(AMD64Assembler.ConditionFlag cc, Register dst, AMD64Address src)`
`void`	`cmovl(AMD64Assembler.ConditionFlag cc, Register dst, Register src)`
`void`	`cmovq(AMD64Assembler.ConditionFlag cc, Register dst, AMD64Address src)`
`void`	`cmovq(AMD64Assembler.ConditionFlag cc, Register dst, Register src)`
`void`	`cmpl(AMD64Address dst, int imm32)`
`void`	`cmpl(Register dst, AMD64Address src)`
`void`	`cmpl(Register dst, int imm32)`
`void`	`cmpl(Register dst, Register src)`
`void`	`cmpq(Register dst, AMD64Address src)`
`void`	`cmpq(Register dst, int imm32)`
`void`	`cmpq(Register dst, Register src)`
`void`	`cmpxchgl(Register reg, AMD64Address adr)`
`void`	`cmpxchgq(Register reg, AMD64Address adr)`
`protected void`	`decl(AMD64Address dst)`
`protected void`	`decl(Register dst)`
`void`	`decq(AMD64Address dst)`
`protected void`	`decq(Register dst)`
`private void`	`emitFPUArith(int b1, int b2, int i)`
`protected void`	`emitModRM(int reg, Register rm)` Emit the ModR/M byte for one register operand and an opcode extension in the R field.
`protected void`	`emitModRM(Register reg, Register rm)` Emit the ModR/M byte for two register operands.
`protected void`	`emitOperandHelper(int reg, AMD64Address addr)` Emits the ModR/M byte and optionally the SIB byte for one memory operand and an opcode extension in the R field.
`protected void`	`emitOperandHelper(Register reg, AMD64Address addr)` Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.
`private void`	`emitx87(int b1, int b2, int i)`
`private static int`	`encode(Register r)`
`void`	`ensureUniquePC()` Emits a NOP instruction to advance the current PC.
`void`	`fcos()`
`void`	`ffree(int i)`
`void`	`fincstp()`
`void`	`fldd(AMD64Address src)`
`void`	`fldlg2()`
`void`	`fldln2()`
`void`	`flds(AMD64Address src)`
`void`	`fnstswAX()`
`void`	`fprem()`
`void`	`fptan()`
`void`	`fsin()`
`void`	`fstp(int i)`
`void`	`fstpd(AMD64Address src)`
`void`	`fstps(AMD64Address src)`
`void`	`fwait()`
`void`	`fxch(int i)`
`void`	`fyl2x()`
`AMD64Address`	`getPlaceholder()` Returns a target specific placeholder address that can be used for code patching.
`protected static int`	`getRXB(Register reg, AMD64Address rm)` Get RXB bits for register-memory instruction.
`protected static int`	`getRXB(Register reg, Register rm)` Get RXB bits for register-register instruction.
`void`	`hlt()`
`void`	`illegal()` Emits an instruction which is considered to be illegal.
`void`	`imull(Register dst, Register src, int value)`
`protected void`	`incl(AMD64Address dst)`
`protected void`	`incl(Register dst)`
`void`	`incq(AMD64Address dst)`
`void`	`incq(Register dst)`
`void`	`int3()`
`void`	`jcc(AMD64Assembler.ConditionFlag cc, int jumpTarget, boolean forceDisp32)`
`void`	`jcc(AMD64Assembler.ConditionFlag cc, Label l)`
`void`	`jccb(AMD64Assembler.ConditionFlag cc, Label l)`
`void`	`jmp(int jumpTarget, boolean forceDisp32)`
`void`	`jmp(Label l)`
`void`	`jmp(Register entry)`
`void`	`jmpb(Label l)`
`void`	`leaq(Register dst, AMD64Address src)`
`void`	`leave()`
`void`	`lock()`
`AMD64Address`	`makeAddress(Register base, int displacement)` This is used by the CompilationResultBuilder to convert a `StackSlot` to an `AbstractAddress`.
`void`	`membar(int barriers)`
`void`	`movapd(Register dst, Register src)`
`void`	`movaps(Register dst, Register src)`
`void`	`movb(AMD64Address dst, int imm8)`
`void`	`movb(AMD64Address dst, Register src)`
`void`	`movdq(Register dst, Register src)`
`void`	`movdqu(Register dst, AMD64Address src)`
`void`	`movl(AMD64Address dst, int imm32)`
`void`	`movl(AMD64Address dst, Register src)`
`void`	`movl(Register dst, AMD64Address src)`
`void`	`movl(Register dst, int imm32)`
`void`	`movl(Register dst, Register src)`
`void`	`movlpd(Register dst, AMD64Address src)` New CPUs require use of movsd and movss to avoid partial register stall when loading from memory.
`void`	`movq(AMD64Address dst, Register src)`
`void`	`movq(Register dst, AMD64Address src)`
`void`	`movq(Register dst, long imm64)`
`void`	`movq(Register dst, Register src)`
`void`	`movsbl(Register dst, AMD64Address src)`
`void`	`movsbl(Register dst, Register src)`
`void`	`movsbq(Register dst, AMD64Address src)`
`void`	`movsbq(Register dst, Register src)`
`void`	`movsd(AMD64Address dst, Register src)`
`void`	`movsd(Register dst, AMD64Address src)`
`void`	`movsd(Register dst, Register src)`
`void`	`movslq(AMD64Address dst, int imm32)`
`void`	`movslq(Register dst, AMD64Address src)`
`void`	`movslq(Register dst, int imm32)`
`void`	`movslq(Register dst, Register src)`
`void`	`movss(AMD64Address dst, Register src)`
`void`	`movss(Register dst, AMD64Address src)`
`void`	`movss(Register dst, Register src)`
`void`	`movswl(Register dst, AMD64Address src)`
`void`	`movw(AMD64Address dst, int imm16)`
`void`	`movw(AMD64Address dst, Register src)`
`void`	`movzbl(Register dst, AMD64Address src)`
`void`	`movzwl(Register dst, AMD64Address src)`
`private static boolean`	`needsRex(Register reg)`
`void`	`negq(Register dst)`
`void`	`nop()`
`void`	`nop(int count)`
`void`	`nullCheck(AMD64Address address)`
`protected void`	`patchJumpTarget(int branch, int branchTarget)`
`void`	`pop(Register dst)`
`void`	`popfq()`
`void`	`prefetchnta(AMD64Address src)`
`private void`	`prefetchPrefix(AMD64Address src)`
`(package private) void`	`prefetchr(AMD64Address src)`
`void`	`prefetcht0(AMD64Address src)`
`void`	`prefetcht1(AMD64Address src)`
`void`	`prefetcht2(AMD64Address src)`
`void`	`prefetchw(AMD64Address src)`
`private void`	`prefix(AMD64Address adr)`
`private void`	`prefix(AMD64Address adr, Register reg)`
`private void`	`prefix(AMD64Address adr, Register reg, boolean byteinst)`
`private int`	`prefixAndEncode(int regEnc)`
`private int`	`prefixAndEncode(int regEnc, boolean byteinst)`
`private int`	`prefixAndEncode(int dstEncoding, boolean dstIsByte, int srcEncoding, boolean srcIsByte)`
`private int`	`prefixAndEncode(int dstEnc, int srcEnc)`
`private void`	`prefixq(AMD64Address adr)`
`private void`	`prefixq(AMD64Address adr, Register src)`
`private int`	`prefixqAndEncode(int regEnc)`
`private int`	`prefixqAndEncode(int regEncoding, int rmEncoding)` Creates prefix and the encoding of the lower 6 bits of the ModRM-Byte.
`void`	`ptest(Register dst, Register src)`
`void`	`push(Register src)`
`void`	`pushfq()`
`void`	`pxor(Register dst, Register src)`
`void`	`ret(int imm16)`
`void`	`shlq(Register dst, int imm8)`
`void`	`shrq(Register dst, int imm8)`
`void`	`subl(AMD64Address dst, int imm32)`
`void`	`subl(Register dst, int imm32)`
`void`	`subq(AMD64Address dst, int imm32)`
`void`	`subq(Register dst, int imm32)`
`void`	`subq(Register dst, Register src)`
`void`	`subqWide(Register dst, int imm32)`
`private boolean`	`supports(AMD64.CPUFeature feature)`
`void`	`testl(Register dst, AMD64Address src)`
`void`	`testl(Register dst, int imm32)`
`void`	`testl(Register dst, Register src)`
`void`	`testq(Register dst, Register src)`
`void`	`xaddl(AMD64Address dst, Register src)`
`void`	`xaddq(AMD64Address dst, Register src)`
`void`	`xchgl(Register dst, AMD64Address src)`
`void`	`xchgq(Register dst, AMD64Address src)`
`void`	`xorl(Register dst, Register src)`
`void`	`xorpd(Register dst, Register src)`
`void`	`xorps(Register dst, Register src)`

Methods inherited from class com.oracle.graal.asm.Assembler
bind, close, createLabelName, emitByte, emitByte, emitInt, emitInt, emitLong, emitLong, emitShort, emitShort, emitString, emitString, emitString0, getByte, getInstructionCounter, getInt, getShort, nameOf, position, requestLabelHint, reset

Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail
- MinEncodingNeedsRex
```
private static final int MinEncodingNeedsRex
```
  See Also:
  
  Constant Field Values
- Placeholder
```
private static final AMD64Address Placeholder
```
  A sentinel value used as a place holder in an instruction stream for an address that will be patched.
- frameRegister
```
public final Register frameRegister
```
  The register to which Register.Frame and Register.CallerFrame are bound.

Constructor Detail
- AMD64Assembler
```
public AMD64Assembler(TargetDescription target,
                      RegisterConfig registerConfig)
```
  Constructs an assembler for the AMD64 architecture.
  
  Parameters:
  
  registerConfig - the register configuration used to bind Register.Frame and Register.CallerFrame to physical registers. This value can be null if this assembler instance will not be used to assemble instructions using these logical registers.

Method Detail

supports

private boolean supports(AMD64.CPUFeature feature)

encode

private static int encode(Register r)

getRXB
```
protected static int getRXB(Register reg,
                            Register rm)
```
Get RXB bits for register-register instruction. In that encoding, ModRM.rm contains a register index. The R bit extends the ModRM.reg field and the B bit extends the ModRM.rm field. The X bit must be 0.

getRXB
```
protected static int getRXB(Register reg,
                            AMD64Address rm)
```
Get RXB bits for register-memory instruction. The R bit extends the ModRM.reg field. There are two cases for the memory operand:
ModRM.rm contains the base register: In that case, B extends the ModRM.rm field and X = 0.
There is an SIB byte: In that case, X extends SIB.index and B extends SIB.base.

emitModRM
```
protected void emitModRM(int reg,
                         Register rm)
```
Emit the ModR/M byte for one register operand and an opcode extension in the R field.
Format: [ 11 reg r/m ]

emitModRM

protected void emitModRM(Register reg,
                         Register rm)

Emit the ModR/M byte for two register operands.

Format: [ 11 reg r/m ]

emitOperandHelper

protected void emitOperandHelper(Register reg,
                                 AMD64Address addr)

Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.

emitOperandHelper

protected void emitOperandHelper(int reg,
                                 AMD64Address addr)

Emits the ModR/M byte and optionally the SIB byte for one memory operand and an opcode extension in the R field.

addl

public final void addl(AMD64Address dst,
                       int imm32)

addl

public final void addl(Register dst,
                       int imm32)

addrNop4
```
private void addrNop4()
```

addrNop5
```
private void addrNop5()
```

addrNop7
```
private void addrNop7()
```

addrNop8
```
private void addrNop8()
```

andl

public final void andl(Register dst,
                       int imm32)

bswapl

public final void bswapl(Register reg)

cdql
```
public final void cdql()
```

cmovl

public final void cmovl(AMD64Assembler.ConditionFlag cc,
                        Register dst,
                        Register src)

cmovl

public final void cmovl(AMD64Assembler.ConditionFlag cc,
                        Register dst,
                        AMD64Address src)

cmpl

public final void cmpl(Register dst,
                       int imm32)

cmpl

public final void cmpl(Register dst,
                       Register src)

cmpl

public final void cmpl(Register dst,
                       AMD64Address src)

cmpl

public final void cmpl(AMD64Address dst,
                       int imm32)

cmpxchgl

public final void cmpxchgl(Register reg,
                           AMD64Address adr)

decl

protected final void decl(AMD64Address dst)

hlt
```
public final void hlt()
```

imull

public final void imull(Register dst,
                        Register src,
                        int value)

incl

protected final void incl(AMD64Address dst)

jcc

public void jcc(AMD64Assembler.ConditionFlag cc,
                int jumpTarget,
                boolean forceDisp32)

jcc

public final void jcc(AMD64Assembler.ConditionFlag cc,
                      Label l)

jccb

public final void jccb(AMD64Assembler.ConditionFlag cc,
                       Label l)

jmp

public final void jmp(int jumpTarget,
                      boolean forceDisp32)

jmp
```
public final void jmp(Label l)
```
Specified by:

jmp in class Assembler

jmp

public final void jmp(Register entry)

jmpb
```
public final void jmpb(Label l)
```

leaq

public final void leaq(Register dst,
                       AMD64Address src)

leave
```
public final void leave()
```

lock
```
public final void lock()
```

movapd

public final void movapd(Register dst,
                         Register src)

movaps

public final void movaps(Register dst,
                         Register src)

movb

public final void movb(AMD64Address dst,
                       int imm8)

movb

public final void movb(AMD64Address dst,
                       Register src)

movl

public final void movl(Register dst,
                       int imm32)

movl

public final void movl(Register dst,
                       Register src)

movl

public final void movl(Register dst,
                       AMD64Address src)

movl

public final void movl(AMD64Address dst,
                       int imm32)

movl

public final void movl(AMD64Address dst,
                       Register src)

movlpd
```
public final void movlpd(Register dst,
                         AMD64Address src)
```
New CPUs require use of movsd and movss to avoid partial register stall when loading from memory. But for old Opteron use movlpd instead of movsd. The selection is done in AMD64MacroAssembler.movdbl(Register, AMD64Address) and AMD64MacroAssembler.movflt(Register, Register).

movq

public final void movq(Register dst,
                       AMD64Address src)

movq

public final void movq(Register dst,
                       Register src)

movq

public final void movq(AMD64Address dst,
                       Register src)

movsbl

public final void movsbl(Register dst,
                         AMD64Address src)

movsbl

public final void movsbl(Register dst,
                         Register src)

movsbq

public final void movsbq(Register dst,
                         AMD64Address src)

movsbq

public final void movsbq(Register dst,
                         Register src)

movsd

public final void movsd(Register dst,
                        Register src)

movsd

public final void movsd(Register dst,
                        AMD64Address src)

movsd

public final void movsd(AMD64Address dst,
                        Register src)

movss

public final void movss(Register dst,
                        Register src)

movss

public final void movss(Register dst,
                        AMD64Address src)

movss

public final void movss(AMD64Address dst,
                        Register src)

movswl

public final void movswl(Register dst,
                         AMD64Address src)

movw

public final void movw(AMD64Address dst,
                       int imm16)

movw

public final void movw(AMD64Address dst,
                       Register src)

movzbl

public final void movzbl(Register dst,
                         AMD64Address src)

movzwl

public final void movzwl(Register dst,
                         AMD64Address src)

ensureUniquePC
```
public final void ensureUniquePC()
```
Description copied from class: Assembler

Emits a NOP instruction to advance the current PC.

Specified by:

ensureUniquePC in class Assembler

nop
```
public final void nop()
```

nop
```
public void nop(int count)
```

pop
```
public final void pop(Register dst)
```

popfq
```
public void popfq()
```

ptest

public final void ptest(Register dst,
                        Register src)

push
```
public final void push(Register src)
```

pushfq
```
public void pushfq()
```

pxor

public final void pxor(Register dst,
                       Register src)

ret
```
public final void ret(int imm16)
```

subl

public final void subl(AMD64Address dst,
                       int imm32)

subl

public final void subl(Register dst,
                       int imm32)

testl

public final void testl(Register dst,
                        int imm32)

testl

public final void testl(Register dst,
                        Register src)

testl

public final void testl(Register dst,
                        AMD64Address src)

xorl

public final void xorl(Register dst,
                       Register src)

xorpd

public final void xorpd(Register dst,
                        Register src)

xorps

public final void xorps(Register dst,
                        Register src)

decl

protected final void decl(Register dst)

incl

protected final void incl(Register dst)

prefixAndEncode

private int prefixAndEncode(int regEnc)

prefixAndEncode

private int prefixAndEncode(int regEnc,
                            boolean byteinst)

prefixqAndEncode

private int prefixqAndEncode(int regEnc)

prefixAndEncode

private int prefixAndEncode(int dstEnc,
                            int srcEnc)

prefixAndEncode

private int prefixAndEncode(int dstEncoding,
                            boolean dstIsByte,
                            int srcEncoding,
                            boolean srcIsByte)

prefixqAndEncode
```
private int prefixqAndEncode(int regEncoding,
                             int rmEncoding)
```
Creates prefix and the encoding of the lower 6 bits of the ModRM-Byte. It emits an operand prefix. If the given operands exceed 3 bits, the 4th bit is encoded in the prefix.

Parameters:

regEncoding - the encoding of the register part of the ModRM-Byte

rmEncoding - the encoding of the r/m part of the ModRM-Byte

Returns:

the lower 6 bits of the ModRM-Byte that should be emitted

needsRex

private static boolean needsRex(Register reg)

prefix

private void prefix(AMD64Address adr)

prefixq

private void prefixq(AMD64Address adr)

prefix

private void prefix(AMD64Address adr,
                    Register reg)

prefix

private void prefix(AMD64Address adr,
                    Register reg,
                    boolean byteinst)

prefixq

private void prefixq(AMD64Address adr,
                     Register src)

addq

public final void addq(Register dst,
                       int imm32)

addq

public final void addq(AMD64Address dst,
                       int imm32)

addq

public final void addq(Register dst,
                       Register src)

addq

public final void addq(AMD64Address dst,
                       Register src)

andq

public final void andq(Register dst,
                       int imm32)

bswapq

public final void bswapq(Register reg)

cdqq
```
public final void cdqq()
```

cmovq

public final void cmovq(AMD64Assembler.ConditionFlag cc,
                        Register dst,
                        Register src)

cmovq

public final void cmovq(AMD64Assembler.ConditionFlag cc,
                        Register dst,
                        AMD64Address src)

cmpq

public final void cmpq(Register dst,
                       int imm32)

cmpq

public final void cmpq(Register dst,
                       Register src)

cmpq

public final void cmpq(Register dst,
                       AMD64Address src)

cmpxchgq

public final void cmpxchgq(Register reg,
                           AMD64Address adr)

decq

protected final void decq(Register dst)

decq

public final void decq(AMD64Address dst)

incq
```
public final void incq(Register dst)
```

incq

public final void incq(AMD64Address dst)

movq

public final void movq(Register dst,
                       long imm64)

movslq

public final void movslq(Register dst,
                         int imm32)

movdq

public final void movdq(Register dst,
                        Register src)

movdqu

public final void movdqu(Register dst,
                         AMD64Address src)

movslq

public final void movslq(AMD64Address dst,
                         int imm32)

movslq

public final void movslq(Register dst,
                         AMD64Address src)

movslq

public final void movslq(Register dst,
                         Register src)

negq
```
public final void negq(Register dst)
```

shlq

public final void shlq(Register dst,
                       int imm8)

shrq

public final void shrq(Register dst,
                       int imm8)

subq

public final void subq(Register dst,
                       int imm32)

subq

public final void subq(AMD64Address dst,
                       int imm32)

subqWide

public final void subqWide(Register dst,
                           int imm32)

subq

public final void subq(Register dst,
                       Register src)

testq

public final void testq(Register dst,
                        Register src)

xaddl

public final void xaddl(AMD64Address dst,
                        Register src)

xaddq

public final void xaddq(AMD64Address dst,
                        Register src)

xchgl

public final void xchgl(Register dst,
                        AMD64Address src)

xchgq

public final void xchgq(Register dst,
                        AMD64Address src)

membar

public final void membar(int barriers)

patchJumpTarget

protected final void patchJumpTarget(int branch,
                                     int branchTarget)

Specified by:: patchJumpTarget in class Assembler

nullCheck

public void nullCheck(AMD64Address address)

align
```
public void align(int modulus)
```
Specified by:

align in class Assembler

call
```
public final void call()
```
Emits a direct call instruction. Note that the actual call target is not specified, because all calls need patching anyway. Therefore, 0 is emitted as the call target, and the user is responsible to add the call address to the appropriate patching tables.

call
```
public final void call(Register src)
```

int3
```
public final void int3()
```

emitx87

private void emitx87(int b1,
                     int b2,
                     int i)

fldd

public final void fldd(AMD64Address src)

flds

public final void flds(AMD64Address src)

fldln2
```
public final void fldln2()
```

fldlg2
```
public final void fldlg2()
```

fyl2x
```
public final void fyl2x()
```

fstps

public final void fstps(AMD64Address src)

fstpd

public final void fstpd(AMD64Address src)

emitFPUArith

private void emitFPUArith(int b1,
                          int b2,
                          int i)

ffree
```
public void ffree(int i)
```

fincstp
```
public void fincstp()
```

fxch
```
public void fxch(int i)
```

fnstswAX
```
public void fnstswAX()
```

fwait
```
public void fwait()
```

fprem
```
public void fprem()
```

fsin
```
public final void fsin()
```

fcos
```
public final void fcos()
```

fptan
```
public final void fptan()
```

fstp
```
public final void fstp(int i)
```

makeAddress
```
public AMD64Address makeAddress(Register base,
                                int displacement)
```
Description copied from class: Assembler

This is used by the CompilationResultBuilder to convert a StackSlot to an AbstractAddress.

Specified by:

makeAddress in class Assembler

getPlaceholder
```
public AMD64Address getPlaceholder()
```
Description copied from class: Assembler

Returns a target specific placeholder address that can be used for code patching.

Specified by:

getPlaceholder in class Assembler

prefetchPrefix

private void prefetchPrefix(AMD64Address src)

prefetchnta

public void prefetchnta(AMD64Address src)

prefetchr
```
void prefetchr(AMD64Address src)
```

prefetcht0

public void prefetcht0(AMD64Address src)

prefetcht1

public void prefetcht1(AMD64Address src)

prefetcht2

public void prefetcht2(AMD64Address src)

prefetchw

public void prefetchw(AMD64Address src)

illegal
```
public void illegal()
```
Emits an instruction which is considered to be illegal. This is used if we deliberately want to crash the program (debugging etc.).

Class AMD64Assembler

Nested Class Summary

Nested classes/interfaces inherited from class com.oracle.graal.asm.Assembler

Field Summary

Fields inherited from class com.oracle.graal.asm.Assembler

Constructor Summary

Method Summary

Methods inherited from class com.oracle.graal.asm.Assembler

Methods inherited from class java.lang.Object

Field Detail

MinEncodingNeedsRex

Placeholder

frameRegister

Constructor Detail

AMD64Assembler

Method Detail

supports

encode

getRXB

getRXB

emitModRM

emitModRM

emitOperandHelper

emitOperandHelper

addl

addl

addrNop4

addrNop5

addrNop7

addrNop8

andl

bswapl

cdql

cmovl

cmovl

cmpl

cmpl

cmpl

cmpl

cmpxchgl

decl

hlt

imull

incl

jcc

jcc

jccb

jmp

jmp

jmp

jmpb

leaq

leave

lock

movapd

movaps

movb

movb

movl

movl

movl

movl

movl

movlpd

movq

movq

movq

movsbl

movsbl

movsbq

movsbq

movsd

movsd

movsd

movss

movss

movss

movswl

movw

movw